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Fix some typos
This patch fixes three typos. The first is a repetition of CONFIG_CMD_BSP. The second makes the #endif comment match its #if. The third is a spelling error. Signed-off-by: Adrian Filipi <adrian.filipi@eurotech.com>
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3 changed files with 2 additions and 3 deletions
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README
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README
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@ -623,7 +623,6 @@ The following options need to be configured:
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CONFIG_CMD_SPI * SPI serial bus support
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CONFIG_CMD_SPI * SPI serial bus support
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CONFIG_CMD_USB * USB support
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CONFIG_CMD_USB * USB support
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CONFIG_CMD_VFD * VFD support (TRAB)
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CONFIG_CMD_VFD * VFD support (TRAB)
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CONFIG_CMD_BSP * Board SPecific functions
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CONFIG_CMD_CDP * Cisco Discover Protocol support
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CONFIG_CMD_CDP * Cisco Discover Protocol support
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CONFIG_CMD_FSL * Microblaze FSL support
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CONFIG_CMD_FSL * Microblaze FSL support
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@ -69,4 +69,4 @@ int usb_cpu_init_fail (void)
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}
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}
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# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */
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# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */
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#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */
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#endif /* defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) */
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@ -9,7 +9,7 @@ The PPC440EP(x)/GR(x) cpu's can boot directly from NAND FLASH,
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completely without NOR FLASH. This can be done by using the NAND
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completely without NOR FLASH. This can be done by using the NAND
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boot feature of the 440 NAND flash controller (NDFC).
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boot feature of the 440 NAND flash controller (NDFC).
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Here a short desciption of the different boot stages:
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Here a short description of the different boot stages:
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a) IPL (Initial Program Loader, integrated inside CPU)
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a) IPL (Initial Program Loader, integrated inside CPU)
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------------------------------------------------------
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------------------------------------------------------
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