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xilinx: Enable SIMPLE_PM_BUS

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Enable simple-pm-bus driver to handle case where axi bus coming between PS
(fixed) part to PL (programmable) part has own clock or power domain.
That's why enable driver to be ready for this configuration.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b9f4bb85be502616edf3be2b79e52a0e2c03e821.1725349691.git.michal.simek@amd.com
This commit is contained in:
Michal Simek 2024-09-03 09:48:15 +02:00
parent fc001432e5
commit 8ef2deefc5
6 changed files with 7 additions and 0 deletions
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1
configs/amd_versal2_virt_defconfig
View file

@ -72,6 +72,7 @@ CONFIG_NETCONSOLE=y
CONFIG_IP_DEFRAG=y CONFIG_IP_DEFRAG=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_TFTP_BLOCKSIZE=4096
CONFIG_SIMPLE_PM_BUS=y
CONFIG_CLK_CCF=y CONFIG_CLK_CCF=y
CONFIG_CLK_SCMI=y CONFIG_CLK_SCMI=y
CONFIG_DFU_RAM=y CONFIG_DFU_RAM=y

1
configs/xilinx_versal_net_virt_defconfig
View file

@ -73,6 +73,7 @@ CONFIG_NETCONSOLE=y
CONFIG_IP_DEFRAG=y CONFIG_IP_DEFRAG=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_TFTP_BLOCKSIZE=4096
CONFIG_SIMPLE_PM_BUS=y
CONFIG_CLK_VERSAL=y CONFIG_CLK_VERSAL=y
CONFIG_DFU_RAM=y CONFIG_DFU_RAM=y
CONFIG_ARM_FFA_TRANSPORT=y CONFIG_ARM_FFA_TRANSPORT=y

1
configs/xilinx_versal_virt_defconfig
View file

@ -72,6 +72,7 @@ CONFIG_NETCONSOLE=y
CONFIG_IP_DEFRAG=y CONFIG_IP_DEFRAG=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_TFTP_BLOCKSIZE=4096
CONFIG_SIMPLE_PM_BUS=y
CONFIG_CLK_VERSAL=y CONFIG_CLK_VERSAL=y
CONFIG_DFU_TIMEOUT=y CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_RAM=y CONFIG_DFU_RAM=y

2
configs/xilinx_zynq_virt_defconfig
View file

@ -94,6 +94,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y CONFIG_NETCONSOLE=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SIMPLE_PM_BUS=y
CONFIG_DFU_TIMEOUT=y CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_MMC=y CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y CONFIG_DFU_RAM=y
@ -138,6 +139,7 @@ CONFIG_PHY_XILINX=y
CONFIG_DM_ETH_PHY=y CONFIG_DM_ETH_PHY=y
CONFIG_MII=y CONFIG_MII=y
CONFIG_ZYNQ_GEM=y CONFIG_ZYNQ_GEM=y
CONFIG_POWER_DOMAIN=y
CONFIG_ARM_DCC=y CONFIG_ARM_DCC=y
CONFIG_ZYNQ_SERIAL=y CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_SPI=y CONFIG_ZYNQ_SPI=y

1
configs/xilinx_zynqmp_kria_defconfig
View file

@ -117,6 +117,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y CONFIG_NETCONSOLE=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SIMPLE_PM_BUS=y
CONFIG_SATA=y CONFIG_SATA=y
CONFIG_SCSI_AHCI=y CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y CONFIG_SATA_CEVA=y

1
configs/xilinx_zynqmp_virt_defconfig
View file

@ -118,6 +118,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y CONFIG_NETCONSOLE=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SIMPLE_PM_BUS=y
CONFIG_SATA=y CONFIG_SATA=y
CONFIG_SCSI_AHCI=y CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y CONFIG_SATA_CEVA=y