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clk: renesas: Synchronize R-Car R8A779F0 S4 clock tables with Linux 6.10.9

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Synchronize R-Car R8A779F0 S4 clock tables with Linux 6.10.9,
commit 1611860f184a2c9e74ed593948d43657734a7098 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut 2024-09-13 01:53:57 +02:00
parent d46a040e73
commit 8c417ceaed
1 changed files with 9 additions and 3 deletions
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12
drivers/clk/renesas/r8a779f0-cpg-mssr.c
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@ -15,6 +15,12 @@
#include "renesas-cpg-mssr.h" #include "renesas-cpg-mssr.h"
#include "rcar-gen3-cpg.h" #include "rcar-gen3-cpg.h"
#define CPG_SD0CKCR 0x870 /* SD-IF0 Clock Frequency Control Register */
#define CPG_CANFDCKCR 0x878 /* CAN-FD Clock Frequency Control Register */
#define CPG_MSOCKCR 0x87c /* MSIOF Clock Frequency Control Register */
#define CPG_CSICKCR 0x880 /* CSI Clock Frequency Control Register */
#define CPG_DSIEXTCKCR 0x884 /* DSI Clock Frequency Control Register */
enum clk_ids { enum clk_ids {
/* Core Clock Outputs exported to DT */ /* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A779F0_CLK_R, LAST_DT_CORE_CLK = R8A779F0_CLK_R,
@ -110,13 +116,13 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
DEF_FIXED("sasyncperd2",R8A779F0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1), DEF_FIXED("sasyncperd2",R8A779F0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1),
DEF_FIXED("sasyncperd4",R8A779F0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1), DEF_FIXED("sasyncperd4",R8A779F0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1),
DEF_GEN4_SDH("sd0h", R8A779F0_CLK_SD0H, CLK_SDSRC, 0x870), DEF_GEN4_SDH("sd0h", R8A779F0_CLK_SD0H, CLK_SDSRC, CPG_SD0CKCR),
DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, R8A779F0_CLK_SD0H, 0x870), DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, R8A779F0_CLK_SD0H, CPG_SD0CKCR),
DEF_BASE("rpc", R8A779F0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), DEF_BASE("rpc", R8A779F0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
DEF_BASE("rpcd2", R8A779F0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC), DEF_BASE("rpcd2", R8A779F0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC),
DEF_DIV6P1("mso", R8A779F0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), DEF_DIV6P1("mso", R8A779F0_CLK_MSO, CLK_PLL5_DIV4, CPG_MSOCKCR),
DEF_GEN4_OSC("osc", R8A779F0_CLK_OSC, CLK_EXTAL, 8), DEF_GEN4_OSC("osc", R8A779F0_CLK_OSC, CLK_EXTAL, 8),
DEF_GEN4_MDSEL("r", R8A779F0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), DEF_GEN4_MDSEL("r", R8A779F0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),