Merge branch 'misc' of https://source.denx.de/u-boot/custodians/u-boot-tegra

Improvements for PMIC GPIO children, tegra20 pinmux driver fix, tegra
dts updates, various small adjustments and tweaks.

arch/arm/dts/tegra124-nyan-big-u-boot.dtsi

@@ -4,16 +4,9 @@
  * Written by Simon Glass <sjg@chromium.org>
  */
 
-#include "tegra-u-boot.dtsi"
+#include "tegra124-u-boot.dtsi"
 
 / {
-	host1x@50000000 {
-		bootph-all;
-		dc@54200000 {
-			bootph-all;
-		};
-	};
-
 	spi@7000d400 {
 		spi-deactivate-delay = <500>;
 		spi-max-frequency = <3000000>;

arch/arm/dts/tegra124-u-boot.dtsi

@@ -1,3 +1,16 @@
 #include <config.h>
 
 #include "tegra-u-boot.dtsi"
+
+/ {
+	host1x@50000000 {
+		bootph-all;
+		dc@54200000 {
+			bootph-all;
+		};
+
+		dc@54240000 {
+			bootph-all;
+		};
+	};
+};

arch/arm/dts/tegra124.dtsi

@@ -136,6 +136,38 @@
 			status = "disabled";
 		};
 
+		dsi@54300000 {
+			compatible = "nvidia,tegra124-dsi";
+			reg = <0x54300000 0x00040000>;
+			clocks = <&tegra_car TEGRA124_CLK_DSIA>,
+				 <&tegra_car TEGRA124_CLK_DSIALP>,
+				 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>;
+			clock-names = "dsi", "lp", "parent";
+			resets = <&tegra_car 48>;
+			reset-names = "dsi";
+			nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
+			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		dsi@54400000 {
+			compatible = "nvidia,tegra124-dsi";
+			reg = <0x54400000 0x00040000>;
+			clocks = <&tegra_car TEGRA124_CLK_DSIB>,
+				 <&tegra_car TEGRA124_CLK_DSIBLP>,
+				 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>;
+			clock-names = "dsi", "lp", "parent";
+			resets = <&tegra_car 82>;
+			reset-names = "dsi";
+			nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
+			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		sor@54540000 {
 			compatible = "nvidia,tegra124-sor";
 			reg = <0x54540000 0x00040000>;
@@ -737,6 +769,13 @@
 		#thermal-sensor-cells = <1>;
 	};
 
+	mipi: mipi@700e3000 {
+		compatible = "nvidia,tegra124-mipi";
+		reg = <0x700e3000 0x100>;
+		clocks = <&tegra_car TEGRA124_CLK_MIPI_CAL>;
+		#nvidia,mipi-calibrate-cells = <1>;
+	};
+
 	dfll: clock@70110000 {
 		compatible = "nvidia,tegra124-dfll";
 		reg = <0x70110000 0x100>, /* DFLL control */

arch/arm/dts/tegra30.dtsi

@@ -218,10 +218,29 @@
 		dsi@54300000 {
 			compatible = "nvidia,tegra30-dsi";
 			reg = <0x54300000 0x00040000>;
-			clocks = <&tegra_car TEGRA30_CLK_DSIA>;
+			clocks = <&tegra_car TEGRA30_CLK_DSIA>,
+				 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
+			clock-names = "dsi", "parent";
 			resets = <&tegra_car 48>;
 			reset-names = "dsi";
 			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		dsi@54400000 {
+			compatible = "nvidia,tegra30-dsi";
+			reg = <0x54400000 0x00040000>;
+			clocks = <&tegra_car TEGRA30_CLK_DSIB>,
+				 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
+			clock-names = "dsi", "parent";
+			resets = <&tegra_car 84>;
+			reset-names = "dsi";
+			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
 		};
 	};
 

arch/arm/include/asm/arch-tegra124/clock-tables.h

@@ -24,6 +24,7 @@ enum clock_id {
 	CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
 	CLOCK_ID_EPCI,
 	CLOCK_ID_SFROM32KHZ,
+	CLOCK_ID_DISPLAY2,
 	CLOCK_ID_DP,	/* Special for Tegra124 */
 
 	/* These are the base clocks (inputs to the Tegra SoC) */
@@ -37,7 +38,6 @@ enum clock_id {
 	 * These are clock IDs that are used in table clock_source[][]
 	 * but will not be assigned as a clock source for any peripheral.
 	 */
-	CLOCK_ID_DISPLAY2,
 	CLOCK_ID_CGENERAL2,
 	CLOCK_ID_CGENERAL3,
 	CLOCK_ID_MEMORY2,

arch/arm/include/asm/arch-tegra210/clock-tables.h

@@ -24,6 +24,7 @@ enum clock_id {
 	CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
 	CLOCK_ID_EPCI,
 	CLOCK_ID_SFROM32KHZ,
+	CLOCK_ID_DISPLAY2,
 	CLOCK_ID_DP,
 
 	/* These are the base clocks (inputs to the Tegra SoC) */
@@ -37,7 +38,6 @@ enum clock_id {
 	 * These are clock IDs that are used in table clock_source[][]
 	 * but will not be assigned as a clock source for any peripheral.
 	 */
-	CLOCK_ID_DISPLAY2,
 	CLOCK_ID_CGENERAL_0,
 	CLOCK_ID_CGENERAL_1,
 	CLOCK_ID_CGENERAL2,

arch/arm/mach-tegra/tegra124/clock.c

@@ -598,6 +598,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
 	  .lock_ena = 9,  .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 },	/* PLLE */
 	{ .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
 	  .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF },	/* PLLS (RESERVED) */
+	{ .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
+	  .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF },	/* PLLD2 */
 	{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF,  .p_shift = 20,  .p_mask = 0xF,
 	  .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 },	/* PLLDP */
 };
@@ -852,6 +854,9 @@ enum clock_id clk_id_to_pll_id(int clk_id)
 	case TEGRA124_CLK_PLL_D:
 	case TEGRA124_CLK_PLL_D_OUT0:
 		return CLOCK_ID_DISPLAY;
+	case TEGRA124_CLK_PLL_D2:
+	case TEGRA124_CLK_PLL_D2_OUT0:
+		return CLOCK_ID_DISPLAY2;
 	case TEGRA124_CLK_PLL_X:
 		return CLOCK_ID_XCPU;
 	case TEGRA124_CLK_PLL_E:
@@ -1194,6 +1199,8 @@ struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
 	case CLOCK_ID_EPCI:
 	case CLOCK_ID_SFROM32KHZ:
 		return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE];
+	case CLOCK_ID_DISPLAY2:
+		return &clkrst->plld2;
 	case CLOCK_ID_DP:
 		return &clkrst->plldp;
 	default:

arch/arm/mach-tegra/tegra210/clock.c

@@ -668,6 +668,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
 	  .lock_ena = 9,  .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 },	/* PLLE */
 	{ .m_shift = 0, .m_mask = 0, .n_shift = 0, .n_mask = 0, .p_shift = 0, .p_mask = 0,
 	  .lock_ena = 0, .lock_det = 0, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 },	/* PLLS (gone)*/
+	{ .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
+	  .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF },	/* PLLD2 */
 	{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF,  .p_shift = 19,  .p_mask = 0x1F,
 	  .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 },	/* PLLDP */
 };
@@ -939,6 +941,9 @@ enum clock_id clk_id_to_pll_id(int clk_id)
 	case TEGRA210_CLK_PLL_D:
 	case TEGRA210_CLK_PLL_D_OUT0:
 		return CLOCK_ID_DISPLAY;
+	case TEGRA210_CLK_PLL_D2:
+	case TEGRA210_CLK_PLL_D2_OUT0:
+		return CLOCK_ID_DISPLAY2;
 	case TEGRA210_CLK_PLL_X:
 		return CLOCK_ID_XCPU;
 	case TEGRA210_CLK_PLL_E:
@@ -1276,6 +1281,8 @@ struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
 	case CLOCK_ID_EPCI:
 	case CLOCK_ID_SFROM32KHZ:
 		return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE];
+	case CLOCK_ID_DISPLAY2:
+		return &clkrst->plld2;
 	default:
 		return NULL;
 	}

board/asus/grouper/Makefile

@@ -6,7 +6,7 @@
 #  (C) Copyright 2021
 #  Svyatoslav Ryhel <clamor95@gmail.com>
 
-obj-$(CONFIG_SPL_BUILD) += grouper-spl.o
+obj-$(CONFIG_XPL_BUILD) += grouper-spl.o
 obj-$(CONFIG_MULTI_DTB_FIT) += board-info.o
 
 obj-y += grouper.o

board/asus/transformer-t30/Makefile

@@ -6,7 +6,7 @@
 #  (C) Copyright 2021
 #  Svyatoslav Ryhel <clamor95@gmail.com>
 
-obj-$(CONFIG_SPL_BUILD) += transformer-t30-spl.o
+obj-$(CONFIG_XPL_BUILD) += transformer-t30-spl.o
 obj-$(CONFIG_MULTI_DTB_FIT) += board-info.o
 
 obj-y += transformer-t30.o

board/asus/transformer-t30/board-info.c

@@ -11,14 +11,14 @@
 #include <asm/arch/pinmux.h>
 
 /*
- *	PCB_ID[1] is kb_row5_pr5
  *	PCB_ID[3] is kb_col7_pq7
  *	PCB_ID[4] is kb_row2_pr2
  *	PCB_ID[5] is kb_col5_pq5
+ *	PCB_ID[7] is gmi_cs1_n_pj2
  *
  *			  Project ID
  *	=====================================================
- *	PCB_ID[1] PCB_ID[5] PCB_ID[4] PCB_ID[3]	Project
+ *	PCB_ID[7] PCB_ID[5] PCB_ID[4] PCB_ID[3]	Project
  *	0	  0	    0	      0		TF201
  *	0	  0	    0	      1		P1801
  *	0	  0	    1	      0		TF300T
@@ -45,10 +45,10 @@ static const char * const project_id_to_fdt[] = {
 	[TF600T] = "tegra30-asus-tf600t",
 };
 
-static int id_gpio_get_value(u32 pingrp, u32 pin)
+static int id_gpio_get_value(u32 pingrp, u32 func, u32 pin)
 {
 	/* Configure pinmux */
-	pinmux_set_func(pingrp, PMUX_FUNC_KBC);
+	pinmux_set_func(pingrp, func);
 	pinmux_set_pullupdown(pingrp, PMUX_PULL_DOWN);
 	pinmux_tristate_enable(pingrp);
 	pinmux_set_io(pingrp, PMUX_PIN_INPUT);
@@ -65,19 +65,19 @@ static int id_gpio_get_value(u32 pingrp, u32 pin)
 
 static int get_project_id(void)
 {
-	u32 pcb_id1, pcb_id3, pcb_id4, pcb_id5;
+	u32 pcb_id3, pcb_id4, pcb_id5, pcb_id7;
 
-	pcb_id1 = id_gpio_get_value(PMUX_PINGRP_KB_ROW5_PR5,
-				    TEGRA_GPIO(R, 5));
 	pcb_id3 = id_gpio_get_value(PMUX_PINGRP_KB_COL7_PQ7,
-				    TEGRA_GPIO(Q, 7));
+				    PMUX_FUNC_KBC, TEGRA_GPIO(Q, 7));
 	pcb_id4 = id_gpio_get_value(PMUX_PINGRP_KB_ROW2_PR2,
-				    TEGRA_GPIO(R, 2));
+				    PMUX_FUNC_KBC, TEGRA_GPIO(R, 2));
 	pcb_id5 = id_gpio_get_value(PMUX_PINGRP_KB_COL5_PQ5,
-				    TEGRA_GPIO(Q, 5));
+				    PMUX_FUNC_KBC, TEGRA_GPIO(Q, 5));
+	pcb_id7 = id_gpio_get_value(PMUX_PINGRP_GMI_CS1_N_PJ2,
+				    PMUX_FUNC_RSVD1, TEGRA_GPIO(J, 2));
 
 	/* Construct board ID */
-	int proj_id = pcb_id1 << 3 | pcb_id5 << 2 |
+	int proj_id = pcb_id7 << 3 | pcb_id5 << 2 |
 		      pcb_id4 << 1 | pcb_id3;
 
 	log_debug("[TRANSFORMER]: project id %d (%s)\n", proj_id,

doc/board/asus/grouper.rst

@@ -25,7 +25,7 @@ along with cellular one.
 
 .. code-block:: bash
 
-    $ export CROSS_COMPILE=arm-linux-gnueabi-
+    $ export CROSS_COMPILE=arm-none-eabi-
     $ make grouper_defconfig # For all grouper versions and tilapia
     $ make
 
@@ -79,18 +79,18 @@ Flashing with the NV3P protocol
 *******************************
 
 Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can
-enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by
+enter it by pre-loading vendor bootloader with the Fusée Gelée.
-pre-loading vendor bootloader with the Fusée Gelée.
 
 With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in
 encrypted state in form, which can just be written RAW at the start of eMMC.
 
 .. code-block:: bash
 
-    $ wheelie --blob blob.bin
+    $ ./run_bootloader.sh -s T30 -t ./bct/grouper.bct -b android_bootloader.bin
-    $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin
+    $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin
 
-When flashing is done, reboot the device.
+When flashing is done, reboot the device. Note that if you have cellular version,
+use ``tilapia.bct``.
 
 Flashing with a pre-loaded U-Boot
 *********************************

doc/board/asus/transformer_t20.rst

@@ -25,7 +25,7 @@ defconfig. Valid fragments are ``tf101.config``, ``tf101g.config`` and
 
 .. code-block:: bash
 
-    $ export CROSS_COMPILE=arm-linux-gnueabi-
+    $ export CROSS_COMPILE=arm-none-eabi-
     $ make transformer_t20_defconfig tf101.config # For TF101
     $ make
 
@@ -84,8 +84,8 @@ encrypted state in form, which can just be written RAW at the start of eMMC.
 
 .. code-block:: bash
 
-    $ wheelie --blob blob.bin
+    $ wheelie -1 --bl bootloader.bin --bct tf101.bct --odm 0x300d8011 || break
-    $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin
+    $ nvflash --resume --rawdevicewrite 0 2048 repart-block.bin
 
 When flashing is done, reboot the device.
 

doc/board/asus/transformer_t30.rst

@@ -22,6 +22,7 @@ Build U-Boot
 
 U-Boot features ability to detect transformer device model on which it is
 loaded. The list of supported devices include:
+
 - ASUS Transformer Prime TF201
 - ASUS Transformer Pad (3G/LTE) TF300T/TG/TL
 - ASUS Transformer Infinity TF700T
@@ -30,7 +31,7 @@ loaded. The list of supported devices include:
 
 .. code-block:: bash
 
-    $ export CROSS_COMPILE=arm-linux-gnueabi-
+    $ export CROSS_COMPILE=arm-none-eabi-
     $ make transformer_t30_defconfig
     $ make
 
@@ -84,18 +85,18 @@ Flashing with the NV3P protocol
 *******************************
 
 Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can
-enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by
+enter it by pre-loading vendor bootloader with the Fusée Gelée.
-pre-loading vendor bootloader with the Fusée Gelée.
 
 With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in
 encrypted state in form, which can just be written RAW at the start of eMMC.
 
 .. code-block:: bash
 
-    $ wheelie --blob blob.bin
+    $ ./run_bootloader.sh -s T30 -t ./bct/tf201.bct -b android_bootloader.bin
-    $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin
+    $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin
 
-When flashing is done, reboot the device.
+When flashing is done, reboot the device. Note that you should adjust bct file
+name according to your device.
 
 Flashing with a pre-loaded U-Boot
 *********************************

doc/board/htc/endeavoru.rst

@@ -21,7 +21,7 @@ Build U-Boot
 
 .. code-block:: bash
 
-    $ export CROSS_COMPILE=arm-linux-gnueabi-
+    $ export CROSS_COMPILE=arm-none-eabi-
     $ make endeavoru_defconfig
     $ make
 
@@ -72,16 +72,15 @@ Flashing with the NV3P protocol
 *******************************
 
 Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can
-enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by
+enter it by pre-loading vendor bootloader with the Fusée Gelée.
-pre-loading vendor bootloader with the Fusée Gelée.
 
 With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in
 encrypted state in form, which can just be written RAW at the start of eMMC.
 
 .. code-block:: bash
 
-    $ wheelie --blob blob.bin
+    $ ./run_bootloader.sh -s T30 -t ./bct/endeavoru.bct -b android_bootloader.bin
-    $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin
+    $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin
 
 When flashing is done, reboot the device.
 

doc/board/lg/x3_t30.rst

@@ -24,7 +24,7 @@ board defconfig. Valid fragments are ``p880.config`` and ``p895.config``.
 
 .. code-block:: bash
 
-    $ export CROSS_COMPILE=arm-linux-gnueabi-
+    $ export CROSS_COMPILE=arm-none-eabi-
     $ make x3_t30_defconfig p895.config # For LG Optimus Vu
     $ make
 
@@ -75,18 +75,18 @@ Flashing with the NV3P protocol
 *******************************
 
 Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can
-enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by
+enter it by pre-loading vendor bootloader with the Fusée Gelée.
-pre-loading vendor bootloader with the Fusée Gelée.
 
 With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in
 encrypted state in form, which can just be written RAW at the start of eMMC.
 
 .. code-block:: bash
 
-    $ wheelie --blob blob.bin
+    $ ./run_bootloader.sh -s T30 -t ./bct/p895.bct -b android_bootloader.bin
-    $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin
+    $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin
 
-When flashing is done, reboot the device.
+When flashing is done, reboot the device. Note that if you have Optimus 4x HD,
+use ``p880.bct``.
 
 Flashing with a pre-loaded U-Boot
 *********************************
@@ -122,7 +122,7 @@ the user to use/partition it in any way the user desires.
 Self Upgrading
 --------------
 
-Place your ``u-boot-dtb-tegra.bin`` on the first partition of the eMMC (using
+Place your ``u-boot-dtb-tegra.bin`` on the first partition of the eMMC or MicroSD
-ability of u-boot to mount it). Enter bootmenu, choose update bootloader option
+card if it is supported (using ability of u-boot to mount it). Enter bootmenu,
-with Power button and U-Boot should update itself. Once the process is
+choose update bootloader option with Power button and U-Boot should update itself.
-completed, U-Boot will ask to press any button to reboot.
+Once the process is completed, U-Boot will ask to press any button to reboot.

doc/board/microsoft/surface-rt.rst

@@ -14,7 +14,7 @@ Build U-Boot
 
 .. code-block:: bash
 
-    $ export CROSS_COMPILE=arm-linux-gnueabi-
+    $ export CROSS_COMPILE=arm-none-eabi-
     $ make surface-rt_defconfig
     $ make
 
@@ -38,4 +38,4 @@ directory with
 To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD and then on
 eMMC. Additionally, if the Volume Down button is pressed while loading, the
 device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC
-as mass storage, fastboot, reboot, reboot RCM, poweroffand enter U-Boot console.
+as mass storage, fastboot, reboot, reboot RCM, poweroff and enter U-Boot console.

doc/board/wexler/qc750.rst

@@ -21,7 +21,7 @@ Build U-Boot
 
 .. code-block:: bash
 
-    $ export CROSS_COMPILE=arm-linux-gnueabi-
+    $ export CROSS_COMPILE=arm-none-eabi-
     $ make qc750_defconfig
     $ make
 
@@ -71,16 +71,15 @@ pre-loading just built U-Boot into RAM.
 Flashing with the NV3P protocol
 *******************************
 
-Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can
+Nv3p is a custom Nvidia protocol used to recover bricked devices. Tegrarcm is
-enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by
+used to handle such state.
-pre-loading vendor bootloader with the Fusée Gelée.
 
 With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in
 encrypted state in form, which can just be written RAW at the start of eMMC.
 
 .. code-block:: bash
 
-    $ wheelie --bct qc750.bct --bl bootloader.bin
+    $ tegrarcm --bct qc750.bct --bootloader android_bootloader.bin --loadaddr 0x80108000
     $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin
 
 When flashing is done, reboot the device.

drivers/gpio/gpio-uclass.c

@@ -1145,29 +1145,9 @@ static int gpio_request_tail(int ret, const char *nodename,
 		ret = uclass_get_device_by_ofnode(UCLASS_GPIO, args->node,
 						  &desc->dev);
 		if (ret) {
-#if CONFIG_IS_ENABLED(MAX77663_GPIO) || CONFIG_IS_ENABLED(PALMAS_GPIO)
-			struct udevice *pmic;
-			ret = uclass_get_device_by_ofnode(UCLASS_PMIC, args->node,
-							  &pmic);
-			if (ret) {
-				log_debug("%s: PMIC device get failed, err %d\n",
-					  __func__, ret);
-				goto err;
-			}
-
-			device_foreach_child(desc->dev, pmic) {
-				if (device_get_uclass_id(desc->dev) == UCLASS_GPIO)
-					break;
-			}
-
-			/* if loop exits without GPIO device return error */
-			if (device_get_uclass_id(desc->dev) != UCLASS_GPIO)
-				goto err;
-#else
 			debug("%s: uclass_get_device_by_ofnode failed\n",
 			      __func__);
 			goto err;
-#endif
 		}
 	}
 	ret = gpio_find_and_xlate(desc, args);

drivers/pinctrl/tegra/pinctrl-tegra20.c

@@ -97,9 +97,9 @@ static int tegra_pinctrl_set_state(struct udevice *dev, struct udevice *config)
 		 * then actual pins setup (with node name prefix
 		 * conf_*) and then drive setup.
 		 */
-		if (!strncmp(child->name, "conf_", 5))
+		if (!strncmp(child->name, "conf", 4))
 			tegra_pinctrl_set_pin(child);
-		else if (!strncmp(child->name, "drive_", 6))
+		else if (!strncmp(child->name, "drive", 5))
 			debug("%s: drive configuration is not supported\n", __func__);
 		else
 			tegra_pinctrl_set_func(child);

drivers/power/pmic/max77663.c

@@ -47,8 +47,9 @@ static int max77663_bind(struct udevice *dev)
 	int children, ret;
 
 	if (IS_ENABLED(CONFIG_SYSRESET_MAX77663)) {
-		ret = device_bind_driver(dev, MAX77663_RST_DRIVER,
+		ret = device_bind_driver_to_node(dev, MAX77663_RST_DRIVER,
-					 "sysreset", NULL);
+						 "sysreset", dev_ofnode(dev),
+						 NULL);
 		if (ret) {
 			log_err("cannot bind SYSRESET (ret = %d)\n", ret);
 			return ret;
@@ -56,8 +57,8 @@ static int max77663_bind(struct udevice *dev)
 	}
 
 	if (IS_ENABLED(CONFIG_MAX77663_GPIO)) {
-		ret = device_bind_driver(dev, MAX77663_GPIO_DRIVER,
+		ret = device_bind_driver_to_node(dev, MAX77663_GPIO_DRIVER,
-					 "gpio", NULL);
+						 "gpio", dev_ofnode(dev), NULL);
 		if (ret) {
 			log_err("cannot bind GPIOs (ret = %d)\n", ret);
 			return ret;

drivers/power/pmic/palmas.c

@@ -49,8 +49,9 @@ static int palmas_bind(struct udevice *dev)
 	int children, ret;
 
 	if (IS_ENABLED(CONFIG_SYSRESET_PALMAS)) {
-		ret = device_bind_driver(dev, PALMAS_RST_DRIVER,
+		ret = device_bind_driver_to_node(dev, PALMAS_RST_DRIVER,
-					 "sysreset", NULL);
+						 "sysreset", dev_ofnode(dev),
+						 NULL);
 		if (ret) {
 			log_err("cannot bind SYSRESET (ret = %d)\n", ret);
 			return ret;