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ram: renesas: dbsc5: Make struct renesas_dbsc5_board_config public

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Make struct renesas_dbsc5_board_config {} definition public via
include/dbsc5.h, so this structure can be defined in board files
and passed into the DBSC5 DRAM driver by overriding weak function
dbsc5_get_board_data() on board level.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut 2025-03-16 14:51:44 +01:00
parent 74e2811361
commit 885fd621a3
2 changed files with 57 additions and 47 deletions
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48
drivers/ram/renesas/dbsc5/dram.c
View file

@ -4,6 +4,7 @@
*/
#include <asm/io.h>
#include <dbsc5.h>
#include <dm.h>
#include <errno.h>
#include <hang.h>
@ -12,13 +13,6 @@
#include <linux/sizes.h>
#include "dbsc5.h"
/* The number of channels V4H has */
#define DRAM_CH_CNT 4
/* The number of slices V4H has */
#define SLICE_CNT 2
/* The number of chip select V4H has */
#define CS_CNT 2
/* Number of array elements in Data Slice */
#define DDR_PHY_SLICE_REGSET_SIZE_V4H 0x100
/* Number of array elements in Data Slice */
@ -1375,46 +1369,6 @@ static const u32 PI_DARRAY3_1_CSx_Fx[CS_CNT][3] = {
#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva)))
struct renesas_dbsc5_board_config {
/* Channels in use */
u8 bdcfg_phyvalid;
/* Read vref (SoC) training range */
u32 bdcfg_vref_r;
/* Write vref (MR14, MR15) training range */
u16 bdcfg_vref_w;
/* CA vref (MR12) training range */
u16 bdcfg_vref_ca;
/* RFM required check */
bool bdcfg_rfm_chk;
/* Board parameter about channels */
struct {
/*
* 0x00: 4Gb dual channel die / 2Gb single channel die
* 0x01: 6Gb dual channel die / 3Gb single channel die
* 0x02: 8Gb dual channel die / 4Gb single channel die
* 0x03: 12Gb dual channel die / 6Gb single channel die
* 0x04: 16Gb dual channel die / 8Gb single channel die
* 0x05: 24Gb dual channel die / 12Gb single channel die
* 0x06: 32Gb dual channel die / 16Gb single channel die
* 0x07: 24Gb single channel die
* 0x08: 32Gb single channel die
* 0xFF: NO_MEMORY
*/
u8 bdcfg_ddr_density[CS_CNT];
/* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */
u32 bdcfg_ca_swap;
/* SoC dqsX([1][0]) -> MEM dqsY: */
u8 bdcfg_dqs_swap;
/* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */
u32 bdcfg_dq_swap[SLICE_CNT];
/* SoC dm -> MEM dqY/dm: (8 means DM) */
u8 bdcfg_dm_swap[SLICE_CNT];
/* SoC ckeX([1][0]) -> MEM csY */
u8 bdcfg_cs_swap;
} ch[4];
};
struct renesas_dbsc5_dram_priv {
void __iomem *regs;
void __iomem *cpg_regs;

56
include/dbsc5.h Normal file
View file

@ -0,0 +1,56 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2024-2025 Renesas Electronics Corp.
*/
#ifndef __INCLUDE_DBSC5_H__
#define __INCLUDE_DBSC5_H__
/* The number of channels V4H has */
#define DRAM_CH_CNT 4
/* The number of slices V4H has */
#define SLICE_CNT 2
/* The number of chip select V4H has */
#define CS_CNT 2
struct renesas_dbsc5_board_config {
/* Channels in use */
u8 bdcfg_phyvalid;
/* Read vref (SoC) training range */
u32 bdcfg_vref_r;
/* Write vref (MR14, MR15) training range */
u16 bdcfg_vref_w;
/* CA vref (MR12) training range */
u16 bdcfg_vref_ca;
/* RFM required check */
bool bdcfg_rfm_chk;
/* Board parameter about channels */
struct {
/*
* 0x00: 4Gb dual channel die / 2Gb single channel die
* 0x01: 6Gb dual channel die / 3Gb single channel die
* 0x02: 8Gb dual channel die / 4Gb single channel die
* 0x03: 12Gb dual channel die / 6Gb single channel die
* 0x04: 16Gb dual channel die / 8Gb single channel die
* 0x05: 24Gb dual channel die / 12Gb single channel die
* 0x06: 32Gb dual channel die / 16Gb single channel die
* 0x07: 24Gb single channel die
* 0x08: 32Gb single channel die
* 0xFF: NO_MEMORY
*/
u8 bdcfg_ddr_density[CS_CNT];
/* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */
u32 bdcfg_ca_swap;
/* SoC dqsX([1][0]) -> MEM dqsY: */
u8 bdcfg_dqs_swap;
/* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */
u32 bdcfg_dq_swap[SLICE_CNT];
/* SoC dm -> MEM dqY/dm: (8 means DM) */
u8 bdcfg_dm_swap[SLICE_CNT];
/* SoC ckeX([1][0]) -> MEM csY */
u8 bdcfg_cs_swap;
} ch[4];
};
#endif /* __INCLUDE_DBSC5_H__ */