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Layerscape: Add crypto node in device tree
LS(1021/1012/1028/1043/1046/1088/2088), LX2160 - updated device tree Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Gaurav Jain
Stefano Babic
parent
cb5d0419f5
commit
88071ca2bb
7 changed files with 291 additions and 3 deletions
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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/*
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* Copyright 2020 NXP
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* Copyright 2020-2021 NXP
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* Copyright 2016 Freescale Semiconductor
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* Copyright 2016 Freescale Semiconductor
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*/
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*/
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@ -71,6 +71,50 @@
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bus-width = <4>;
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bus-width = <4>;
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};
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};
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crypto: crypto@1700000 {
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compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
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"fsl,sec-v4.0";
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fsl,sec-era = <8>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x00 0x1700000 0x100000>;
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reg = <0x00 0x1700000 0x0 0x100000>;
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interrupts = <0 75 0x4>;
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dma-coherent;
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sec_jr0: jr@10000 {
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compatible = "fsl,sec-v5.4-job-ring",
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"fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x10000 0x10000>;
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interrupts = <0 71 0x4>;
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};
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sec_jr1: jr@20000 {
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compatible = "fsl,sec-v5.4-job-ring",
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"fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x20000 0x10000>;
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interrupts = <0 72 0x4>;
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};
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sec_jr2: jr@30000 {
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compatible = "fsl,sec-v5.4-job-ring",
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"fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x30000 0x10000>;
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interrupts = <0 73 0x4>;
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};
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sec_jr3: jr@40000 {
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compatible = "fsl,sec-v5.4-job-ring",
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"fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x40000 0x10000>;
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interrupts = <0 74 0x4>;
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};
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};
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gpio0: gpio@2300000 {
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gpio0: gpio@2300000 {
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compatible = "fsl,qoriq-gpio";
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compatible = "fsl,qoriq-gpio";
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reg = <0x0 0x2300000 0x0 0x10000>;
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reg = <0x0 0x2300000 0x0 0x10000>;
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@ -2,7 +2,7 @@
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/*
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/*
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* Device Tree Include file for NXP Layerscape-1043A family SoC.
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* Device Tree Include file for NXP Layerscape-1043A family SoC.
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*
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*
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* Copyright 2020 NXP
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* Copyright 2020-2021 NXP
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* Copyright (C) 2014-2015, Freescale Semiconductor
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* Copyright (C) 2014-2015, Freescale Semiconductor
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*
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*
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* Mingkai Hu <Mingkai.hu@freescale.com>
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* Mingkai Hu <Mingkai.hu@freescale.com>
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@ -125,6 +125,49 @@
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interrupts = <0 43 0x4>;
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interrupts = <0 43 0x4>;
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};
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};
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crypto: crypto@1700000 {
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compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
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"fsl,sec-v4.0";
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fsl,sec-era = <3>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x00 0x1700000 0x100000>;
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reg = <0x00 0x1700000 0x0 0x100000>;
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interrupts = <0 75 0x4>;
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sec_jr0: jr@10000 {
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compatible = "fsl,sec-v5.4-job-ring",
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"fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x10000 0x10000>;
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interrupts = <0 71 0x4>;
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};
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sec_jr1: jr@20000 {
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compatible = "fsl,sec-v5.4-job-ring",
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"fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x20000 0x10000>;
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interrupts = <0 72 0x4>;
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};
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sec_jr2: jr@30000 {
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compatible = "fsl,sec-v5.4-job-ring",
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"fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x30000 0x10000>;
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interrupts = <0 73 0x4>;
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};
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sec_jr3: jr@40000 {
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compatible = "fsl,sec-v5.4-job-ring",
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"fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x40000 0x10000>;
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interrupts = <0 74 0x4>;
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};
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};
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i2c0: i2c@2180000 {
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i2c0: i2c@2180000 {
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compatible = "fsl,vf610-i2c";
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#address-cells = <1>;
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@ -3,6 +3,7 @@
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* Device Tree Include file for Freescale Layerscape-1046A family SoC.
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* Device Tree Include file for Freescale Layerscape-1046A family SoC.
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*
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*
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* Copyright (C) 2016, Freescale Semiconductor
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* Copyright (C) 2016, Freescale Semiconductor
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* Copyright 2021 NXP
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*
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*
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* Mingkai Hu <mingkai.hu@nxp.com>
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* Mingkai Hu <mingkai.hu@nxp.com>
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*/
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*/
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@ -124,6 +125,49 @@
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interrupts = <0 43 0x4>;
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interrupts = <0 43 0x4>;
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};
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};
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crypto: crypto@1700000 {
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compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
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"fsl,sec-v4.0";
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fsl,sec-era = <8>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x00 0x1700000 0x100000>;
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reg = <0x00 0x1700000 0x0 0x100000>;
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interrupts = <0 75 0x4>;
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sec_jr0: jr@10000 {
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compatible = "fsl,sec-v5.4-job-ring",
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"fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x10000 0x10000>;
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interrupts = <0 71 0x4>;
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};
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sec_jr1: jr@20000 {
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compatible = "fsl,sec-v5.4-job-ring",
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"fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x20000 0x10000>;
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interrupts = <0 72 0x4>;
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};
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sec_jr2: jr@30000 {
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compatible = "fsl,sec-v5.4-job-ring",
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"fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x30000 0x10000>;
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interrupts = <0 73 0x4>;
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};
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sec_jr3: jr@40000 {
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compatible = "fsl,sec-v5.4-job-ring",
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"fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x40000 0x10000>;
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interrupts = <0 74 0x4>;
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};
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};
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i2c0: i2c@2180000 {
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i2c0: i2c@2180000 {
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compatible = "fsl,vf610-i2c";
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#address-cells = <1>;
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@ -174,6 +174,45 @@
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dr_mode = "host";
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dr_mode = "host";
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};
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};
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crypto: crypto@8000000 {
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compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
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fsl,sec-era = <8>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x00 0x8000000 0x100000>;
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reg = <0x00 0x8000000 0x0 0x100000>;
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interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
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dma-coherent;
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sec_jr0: jr@10000 {
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compatible = "fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x10000 0x10000>;
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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};
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sec_jr1: jr@20000 {
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compatible = "fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x20000 0x10000>;
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interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
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};
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sec_jr2: jr@30000 {
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compatible = "fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x30000 0x10000>;
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interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
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};
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sec_jr3: jr@40000 {
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compatible = "fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x40000 0x10000>;
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interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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pcie1: pcie@3400000 {
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pcie1: pcie@3400000 {
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compatible = "fsl,ls-pcie", "snps,dw-pcie";
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compatible = "fsl,ls-pcie", "snps,dw-pcie";
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reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
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reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
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@ -239,6 +239,45 @@
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status = "disabled";
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status = "disabled";
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};
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};
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crypto: crypto@8000000 {
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compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
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fsl,sec-era = <8>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x00 0x8000000 0x100000>;
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reg = <0x00 0x8000000 0x0 0x100000>;
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interrupts = <0 139 0x4>; /* Level high type */
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dma-coherent;
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sec_jr0: jr@10000 {
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compatible = "fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x10000 0x10000>;
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interrupts = <0 140 0x4>; /* Level high type */
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};
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sec_jr1: jr@20000 {
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compatible = "fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x20000 0x10000>;
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interrupts = <0 141 0x4>; /* Level high type */
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};
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sec_jr2: jr@30000 {
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compatible = "fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x30000 0x10000>;
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interrupts = <0 142 0x4>; /* Level high type */
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};
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sec_jr3: jr@40000 {
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compatible = "fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x40000 0x10000>;
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interrupts = <0 143 0x4>; /* Level high type */
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};
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};
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fsl_mc: fsl-mc@80c000000 {
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fsl_mc: fsl-mc@80c000000 {
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compatible = "fsl,qoriq-mc", "simple-mfd";
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compatible = "fsl,qoriq-mc", "simple-mfd";
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reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
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reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
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@ -2,7 +2,7 @@
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/*
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/*
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* NXP lx2160a SOC common device tree source
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* NXP lx2160a SOC common device tree source
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*
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*
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* Copyright 2018-2020 NXP
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* Copyright 2018-2021 NXP
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*
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*
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*/
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*/
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@ -27,6 +27,45 @@
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clock-output-names = "sysclk";
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clock-output-names = "sysclk";
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};
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};
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crypto: crypto@8000000 {
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compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
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fsl,sec-era = <10>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x00 0x8000000 0x100000>;
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reg = <0x00 0x8000000 0x0 0x100000>;
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interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
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dma-coherent;
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sec_jr0: jr@10000 {
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compatible = "fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x10000 0x10000>;
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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};
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sec_jr1: jr@20000 {
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compatible = "fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x20000 0x10000>;
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interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
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};
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sec_jr2: jr@30000 {
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compatible = "fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x30000 0x10000>;
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interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
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};
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sec_jr3: jr@40000 {
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compatible = "fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x40000 0x10000>;
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interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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clockgen: clocking@1300000 {
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clockgen: clocking@1300000 {
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compatible = "fsl,ls2080a-clockgen";
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compatible = "fsl,ls2080a-clockgen";
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reg = <0 0x1300000 0 0xa0000>;
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reg = <0 0x1300000 0 0xa0000>;
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@ -3,6 +3,7 @@
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* Freescale ls1021a SOC common device tree source
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* Freescale ls1021a SOC common device tree source
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*
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*
|
||||||
* Copyright 2013-2015 Freescale Semiconductor, Inc.
|
* Copyright 2013-2015 Freescale Semiconductor, Inc.
|
||||||
|
* Copyright 2021 NXP
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include "skeleton.dtsi"
|
#include "skeleton.dtsi"
|
||||||
|
|
@ -144,6 +145,45 @@
|
||||||
big-endian;
|
big-endian;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
crypto: crypto@1700000 {
|
||||||
|
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
|
||||||
|
fsl,sec-era = <7>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
reg = <0x1700000 0x100000>;
|
||||||
|
ranges = <0x0 0x1700000 0x100000>;
|
||||||
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
|
||||||
|
sec_jr0: jr@10000 {
|
||||||
|
compatible = "fsl,sec-v5.0-job-ring",
|
||||||
|
"fsl,sec-v4.0-job-ring";
|
||||||
|
reg = <0x10000 0x10000>;
|
||||||
|
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
};
|
||||||
|
|
||||||
|
sec_jr1: jr@20000 {
|
||||||
|
compatible = "fsl,sec-v5.0-job-ring",
|
||||||
|
"fsl,sec-v4.0-job-ring";
|
||||||
|
reg = <0x20000 0x10000>;
|
||||||
|
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
};
|
||||||
|
|
||||||
|
sec_jr2: jr@30000 {
|
||||||
|
compatible = "fsl,sec-v5.0-job-ring",
|
||||||
|
"fsl,sec-v4.0-job-ring";
|
||||||
|
reg = <0x30000 0x10000>;
|
||||||
|
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
};
|
||||||
|
|
||||||
|
sec_jr3: jr@40000 {
|
||||||
|
compatible = "fsl,sec-v5.0-job-ring",
|
||||||
|
"fsl,sec-v4.0-job-ring";
|
||||||
|
reg = <0x40000 0x10000>;
|
||||||
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
};
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
clockgen: clocking@1ee1000 {
|
clockgen: clocking@1ee1000 {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
|
|
|
||||||
Loading…
Add table
Reference in a new issue