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armv8: layerscape: add PSCI support for cpu release

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For cpu release command, check whether PSCI is supported firstly,
if supported, use PSCI to kick off secondary cores, otherwise still
use spin table.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
[Fixed checkpatch alignment CHECKs]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Jiafei Pan 2021-04-21 12:12:49 +08:00 • committed by Priyanka Jain
parent c0eeb730f8
commit 84c2e044a9
3 changed files with 37 additions and 17 deletions
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2
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View file

@ -1063,7 +1063,7 @@ int cpu_eth_init(struct bd_info *bis)
return error; return error;
} }
static inline int check_psci(void) int check_psci(void)
{ {
unsigned int psci_ver; unsigned int psci_ver;

1
arch/arm/cpu/armv8/fsl-layerscape/cpu.h
View file

@ -6,3 +6,4 @@
int fsl_qoriq_core_to_cluster(unsigned int core); int fsl_qoriq_core_to_cluster(unsigned int core);
u32 initiator_type(u32 cluster, int init_id); u32 initiator_type(u32 cluster, int init_id);
u32 cpu_mask(void); u32 cpu_mask(void);
int check_psci(void);

21
arch/arm/cpu/armv8/fsl-layerscape/mp.c
View file

@ -10,10 +10,12 @@
#include <asm/cache.h> #include <asm/cache.h>
#include <asm/global_data.h> #include <asm/global_data.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/ptrace.h>
#include <asm/system.h> #include <asm/system.h>
#include <asm/arch/mp.h> #include <asm/arch/mp.h>
#include <asm/arch/soc.h> #include <asm/arch/soc.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/psci.h>
#include "cpu.h" #include "cpu.h"
#include <asm/arch-fsl-layerscape/soc.h> #include <asm/arch-fsl-layerscape/soc.h>
#include <efi_loader.h> #include <efi_loader.h>
@ -301,12 +303,15 @@ int cpu_release(u32 nr, int argc, char *const argv[])
u64 *table = get_spin_tbl_addr(); u64 *table = get_spin_tbl_addr();
int pos; int pos;
boot_addr = simple_strtoull(argv[0], NULL, 16);
if (check_psci()) {
/* SPIN Table is used */
pos = core_to_pos(nr); pos = core_to_pos(nr);
if (pos <= 0) if (pos <= 0)
return -1; return -1;
table += pos * WORDS_PER_SPIN_TABLE_ENTRY; table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
boot_addr = simple_strtoull(argv[0], NULL, 16);
table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr; table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr;
flush_dcache_range((unsigned long)table, flush_dcache_range((unsigned long)table,
(unsigned long)table + SPIN_TABLE_ELEM_SIZE); (unsigned long)table + SPIN_TABLE_ELEM_SIZE);
@ -319,6 +324,20 @@ int cpu_release(u32 nr, int argc, char *const argv[])
* slave_cpu loop in lowlevel.S) * slave_cpu loop in lowlevel.S)
*/ */
asm volatile("sev"); asm volatile("sev");
} else {
/* Use PSCI to kick the core */
struct pt_regs regs;
printf("begin to kick cpu core #%d to address %llx\n",
nr, boot_addr);
regs.regs[0] = PSCI_0_2_FN64_CPU_ON;
regs.regs[1] = nr;
regs.regs[2] = boot_addr;
regs.regs[3] = 0;
smc_call(&regs);
if (regs.regs[0])
return -1;
}
return 0; return 0;
} }