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driver/ddr: Fix DDR4 driver for ARM

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Previously the driver was only tested on Power SoCs. Different barrier
instructions are needed for ARM SoCs.

Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
York Sun 2014-06-23 15:36:44 -07:00
parent 6666017f44
commit 8340e7ac86
4 changed files with 13 additions and 2 deletions
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7
drivers/ddr/fsl/fsl_ddr_gen4.c
View file

@ -8,6 +8,7 @@
#include <asm/io.h>
#include <fsl_ddr_sdram.h>
#include <asm/processor.h>
#include <fsl_immap.h>
#include <fsl_ddr.h>
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
@ -183,12 +184,14 @@ step2:
* we choose the max, that is 500 us for all of case.
*/
udelay(500);
asm volatile("sync;isync");
mb();
isb();
/* Let the controller go */
temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
asm volatile("sync;isync");
mb();
isb();
total_gb_size_per_controller = 0;
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {