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ddr: imx8m: Return error values from LPDDR4 training

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In cases when the same SPL should run on boards with i.MX8MM, that
differ in DDR configuration, it is necessary to try different
parameters and check if the training done by the firmware suceeds or
not.

Therefore we return the DDR training/initialization success to the
upper layer in order to be able to retry with different settings if
necessary.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
This commit is contained in:
Frieder Schrempf 2019-12-11 10:01:19 +00:00 • committed by Stefano Babic
parent 162c72c804
commit 83083febf5
4 changed files with 23 additions and 11 deletions
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9
drivers/ddr/imx/imx8m/ddrphy_train.c
View file

@ -8,13 +8,14 @@
#include <asm/arch/ddr.h>
#include <asm/arch/lpddr4_define.h>
void ddr_cfg_phy(struct dram_timing_info *dram_timing)
int ddr_cfg_phy(struct dram_timing_info *dram_timing)
{
struct dram_cfg_param *dram_cfg;
struct dram_fsp_msg *fsp_msg;
unsigned int num;
int i = 0;
int j = 0;
int ret;
/* initialize PHY configuration */
dram_cfg = dram_timing->ddrphy_cfg;
@ -60,7 +61,9 @@ void ddr_cfg_phy(struct dram_timing_info *dram_timing)
dwc_ddrphy_apb_wr(0xd0099, 0x0);
/* Wait for the training firmware to complete */
wait_ddrphy_training_complete();
ret = wait_ddrphy_training_complete();
if (ret)
return ret;
/* Halt the microcontroller. */
dwc_ddrphy_apb_wr(0xd0099, 0x1);
@ -83,4 +86,6 @@ void ddr_cfg_phy(struct dram_timing_info *dram_timing)
/* save the ddr PHY trained CSR in memory for low power use */
ddrphy_trained_csr_save(ddrphy_trained_csr, ddrphy_trained_csr_num);
return 0;
}