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soc: zynqmp: Add support for zu1eg_lr device

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There is new chip coming which is using new _lr suffix that's why record it
in the list to enable bitstream in bit format loading.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/12a939e2c88e82a9828852a8f7f33dfa14a6a4b8.1722351201.git.michal.simek@amd.com
This commit is contained in:
Michal Simek 2024-07-30 16:53:23 +02:00
parent 5389564b52
commit 81b2831062
1 changed files with 8 additions and 0 deletions
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8
drivers/soc/soc_xilinx_zynqmp.c
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@ -44,6 +44,7 @@ enum {
ZYNQMP_VARIANT_DR_SE = BIT(4),
ZYNQMP_VARIANT_EG_SE = BIT(5),
ZYNQMP_VARIANT_TEG = BIT(6),
ZYNQMP_VARIANT_EG_LR = BIT(7),
};
struct zynqmp_device {
@ -64,6 +65,11 @@ static const struct zynqmp_device zynqmp_devices[] = {
.device = 1,
.variants = ZYNQMP_VARIANT_EG,
},
{
.id = 0x04689093,
.device = 1,
.variants = ZYNQMP_VARIANT_EG_LR,
},
{
.id = 0x04711093,
.device = 2,
@ -300,6 +306,8 @@ static int soc_xilinx_zynqmp_detect_machine(struct udevice *dev, u32 idcode,
strlcat(priv->machine, "eg", sizeof(priv->machine));
} else if (device->variants & ZYNQMP_VARIANT_EG_SE) {
strlcat(priv->machine, "eg_SE", sizeof(priv->machine));
} else if (device->variants & ZYNQMP_VARIANT_EG_LR) {
strlcat(priv->machine, "eg_LR", sizeof(priv->machine));
} else if (device->variants & ZYNQMP_VARIANT_DR) {
strlcat(priv->machine, "dr", sizeof(priv->machine));
} else if (device->variants & ZYNQMP_VARIANT_DR_SE) {