From 33672c970b0854586b3c533f3bf17056e96d7cf6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 21 Jan 2020 20:03:09 +0100 Subject: [PATCH 1/9] mtd: rawnand: denali-spl: Add missing hardware init on SoCFPGA On Altera SoCFPGA, upon either cold-boot or power-on reset, the Denali NAND IP is initialized by the BootROM ; upon warm-reset, the Denali NAND IP is NOT initialized by BootROM. In fact, upon warm-reset, the SoCFPGA BootROM checks whether the SPL image in on-chip RAM is valid and if so, completely skips re-loading the SPL from the boot media. This does sometimes lead to problems where the software left the boot media in inconsistent state before warm-reset, and because the BootROM does not reset the boot media, the boot media is left in this inconsistent state, often until another component attempts to access the boot media and fails with an difficult to debug failure. To mitigate this problem, the SPL on Altera SoCFPGA always resets all the IPs on the SoC early on boot. This results in a couple of register values, pre-programmed by the BootROM, to be lost during this reset. To restore correct operation of the IP on SoCFPGA, these values must be programmed back into the controller by the driver. Note that on other SoCs which do not use the HW-controlled bootstrap, more registers may have to be programmed. This also aligns the SPL behavior with the full Denali NAND driver, which sets these values in denali_hw_init(). Signed-off-by: Marek Vasut Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/raw/denali_spl.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mtd/nand/raw/denali_spl.c b/drivers/mtd/nand/raw/denali_spl.c index dbaba3cab2a..b8b29812aab 100644 --- a/drivers/mtd/nand/raw/denali_spl.c +++ b/drivers/mtd/nand/raw/denali_spl.c @@ -173,6 +173,13 @@ void nand_init(void) page_size = readl(denali_flash_reg + DEVICE_MAIN_AREA_SIZE); oob_size = readl(denali_flash_reg + DEVICE_SPARE_AREA_SIZE); pages_per_block = readl(denali_flash_reg + PAGES_PER_BLOCK); + + /* Do as denali_hw_init() does. */ + writel(CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES, + denali_flash_reg + SPARE_AREA_SKIP_BYTES); + writel(0x0F, denali_flash_reg + RB_PIN_ENABLED); + writel(CHIP_EN_DONT_CARE__FLAG, denali_flash_reg + CHIP_ENABLE_DONT_CARE); + writel(0xffff, denali_flash_reg + SPARE_AREA_MARKER); } int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) From 11bcc5841ae6765e010a419bd6354b15ae4e1096 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 21 Jan 2020 20:03:10 +0100 Subject: [PATCH 2/9] mtd: rawnand: denali_dt: make the core clock optional The "nand_x" and "ecc" clocks are currently optional. Make the core clock optional in the same way. This will allow platforms with no clock driver support to use this driver. Signed-off-by: Masahiro Yamada Tested-by: Marek Vasut # On SoCFPGA Arria V --- drivers/mtd/nand/raw/denali_dt.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index 0ce81324b90..b1e14982c44 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -91,7 +91,7 @@ static int denali_dt_probe(struct udevice *dev) if (ret) ret = clk_get_by_index(dev, 0, &clk); if (ret) - return ret; + clk.dev = NULL; ret = clk_get_by_name(dev, "nand_x", &clk_x); if (ret) @@ -101,9 +101,11 @@ static int denali_dt_probe(struct udevice *dev) if (ret) clk_ecc.dev = NULL; - ret = clk_enable(&clk); - if (ret) - return ret; + if (clk.dev) { + ret = clk_enable(&clk); + if (ret) + return ret; + } if (clk_x.dev) { ret = clk_enable(&clk_x); From 9925df051a7964e939298fe54df60153409b6352 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 21 Jan 2020 20:03:11 +0100 Subject: [PATCH 3/9] mtd: rawnand: denali: Do not reset the block before booting the kernel The Denali NAND driver in mainline Linux currently cannot deassert the reset. The upcoming Linux 5.6 will support the reset controlling, and also set up SPARE_AREA_SKIP_BYTES correctly. So, the Denali driver in the future kernel will work without relying on any bootloader or firmware. However, we still need to take care of stable kernel versions for a while. U-boot should not assert the reset of this controller. Fixes: ed784ac3822b ("mtd: rawnand: denali: add reset handling") Signed-off-by: Marek Vasut [yamada.masahiro: reword the commit description] Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/raw/denali.h | 2 -- drivers/mtd/nand/raw/denali_dt.c | 15 ++++----------- 2 files changed, 4 insertions(+), 13 deletions(-) diff --git a/drivers/mtd/nand/raw/denali.h b/drivers/mtd/nand/raw/denali.h index 63ae828768c..019deda094e 100644 --- a/drivers/mtd/nand/raw/denali.h +++ b/drivers/mtd/nand/raw/denali.h @@ -10,7 +10,6 @@ #include #include #include -#include #define DEVICE_RESET 0x0 #define DEVICE_RESET__BANK(bank) BIT(bank) @@ -316,7 +315,6 @@ struct denali_nand_info { void (*host_write)(struct denali_nand_info *denali, u32 addr, u32 data); void (*setup_dma)(struct denali_nand_info *denali, dma_addr_t dma_addr, int page, int write); - struct reset_ctl_bulk resets; }; #define DENALI_CAP_HW_ECC_FIXUP BIT(0) diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index b1e14982c44..91d0f20aaeb 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -9,6 +9,7 @@ #include #include #include +#include #include "denali.h" @@ -63,6 +64,7 @@ static int denali_dt_probe(struct udevice *dev) struct denali_nand_info *denali = dev_get_priv(dev); const struct denali_dt_data *data; struct clk clk, clk_x, clk_ecc; + struct reset_ctl_bulk resets; struct resource res; int ret; @@ -133,30 +135,21 @@ static int denali_dt_probe(struct udevice *dev) denali->clk_x_rate = 200000000; } - ret = reset_get_bulk(dev, &denali->resets); + ret = reset_get_bulk(dev, &resets); if (ret) dev_warn(dev, "Can't get reset: %d\n", ret); else - reset_deassert_bulk(&denali->resets); + reset_deassert_bulk(&resets); return denali_init(denali); } -static int denali_dt_remove(struct udevice *dev) -{ - struct denali_nand_info *denali = dev_get_priv(dev); - - return reset_release_bulk(&denali->resets); -} - U_BOOT_DRIVER(denali_nand_dt) = { .name = "denali-nand-dt", .id = UCLASS_MISC, .of_match = denali_nand_dt_ids, .probe = denali_dt_probe, .priv_auto_alloc_size = sizeof(struct denali_nand_info), - .remove = denali_dt_remove, - .flags = DM_FLAG_OS_PREPARE, }; void board_nand_init(void) From 21d4a3ca549b5b1b8243c845b15f91142bfa3528 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 30 Jan 2020 00:55:54 +0900 Subject: [PATCH 4/9] mtd: rawnand: denali_dt: insert udelay() after reset deassert When the reset signal is de-asserted, the HW-controlled bootstrap starts running unless it is disabled in the SoC integration. It issues some commands to detect a NAND chip, and sets up registers automatically. Until this process finishes, software should avoid any register access. Without this delay function, some of UniPhier boards hangs up while executing nand_scan_ident(). (denali_read_byte() is blocked) Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/raw/denali_dt.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index 91d0f20aaeb..1afc61f8767 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -136,11 +136,19 @@ static int denali_dt_probe(struct udevice *dev) } ret = reset_get_bulk(dev, &resets); - if (ret) + if (ret) { dev_warn(dev, "Can't get reset: %d\n", ret); - else + } else { reset_deassert_bulk(&resets); + /* + * When the reset is deasserted, the initialization sequence is + * kicked (bootstrap process). The driver must wait until it is + * finished. Otherwise, it will result in unpredictable behavior. + */ + udelay(200); + } + return denali_init(denali); } From 80924cc164c703991a2518feff705fdf5e7fbc14 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 30 Jan 2020 00:55:55 +0900 Subject: [PATCH 5/9] mtd: rawnand: denali: set SPARE_AREA_SKIP_BYTES based on DT compatible Currently, the denali NAND driver in U-Boot configures the SPARE_AREA_SKIP_BYTES based on the CONFIG option. Recently, Linux kernel merged a patch that associates the proper value for this register with the DT compatible string. Do likewise in U-Boot too. The denali_spl.c still uses CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES. Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/raw/denali.c | 15 +++++++++++---- drivers/mtd/nand/raw/denali_dt.c | 16 +++++++++++----- 2 files changed, 22 insertions(+), 9 deletions(-) diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c index 8537c609fb6..be1b3627ad0 100644 --- a/drivers/mtd/nand/raw/denali.c +++ b/drivers/mtd/nand/raw/denali.c @@ -1069,11 +1069,18 @@ static void denali_hw_init(struct denali_nand_info *denali) denali->revision = swab16(ioread32(denali->reg + REVISION)); /* - * tell driver how many bit controller will skip before writing - * ECC code in OOB. This is normally used for bad block marker + * Set how many bytes should be skipped before writing data in OOB. + * If a platform requests a non-zero value, set it to the register. + * Otherwise, read the value out, expecting it has already been set up + * by firmware. */ - denali->oob_skip_bytes = CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES; - iowrite32(denali->oob_skip_bytes, denali->reg + SPARE_AREA_SKIP_BYTES); + if (denali->oob_skip_bytes) + iowrite32(denali->oob_skip_bytes, + denali->reg + SPARE_AREA_SKIP_BYTES); + else + denali->oob_skip_bytes = ioread32(denali->reg + + SPARE_AREA_SKIP_BYTES); + denali_detect_max_banks(denali); iowrite32(0x0F, denali->reg + RB_PIN_ENABLED); iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE); diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index 1afc61f8767..587e480faa1 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -16,6 +16,7 @@ struct denali_dt_data { unsigned int revision; unsigned int caps; + unsigned int oob_skip_bytes; const struct nand_ecc_caps *ecc_caps; }; @@ -23,6 +24,7 @@ NAND_ECC_CAPS_SINGLE(denali_socfpga_ecc_caps, denali_calc_ecc_bytes, 512, 8, 15); static const struct denali_dt_data denali_socfpga_data = { .caps = DENALI_CAP_HW_ECC_FIXUP, + .oob_skip_bytes = 2, .ecc_caps = &denali_socfpga_ecc_caps, }; @@ -31,6 +33,7 @@ NAND_ECC_CAPS_SINGLE(denali_uniphier_v5a_ecc_caps, denali_calc_ecc_bytes, static const struct denali_dt_data denali_uniphier_v5a_data = { .caps = DENALI_CAP_HW_ECC_FIXUP | DENALI_CAP_DMA_64BIT, + .oob_skip_bytes = 8, .ecc_caps = &denali_uniphier_v5a_ecc_caps, }; @@ -40,6 +43,7 @@ static const struct denali_dt_data denali_uniphier_v5b_data = { .revision = 0x0501, .caps = DENALI_CAP_HW_ECC_FIXUP | DENALI_CAP_DMA_64BIT, + .oob_skip_bytes = 8, .ecc_caps = &denali_uniphier_v5b_ecc_caps, }; @@ -69,11 +73,13 @@ static int denali_dt_probe(struct udevice *dev) int ret; data = (void *)dev_get_driver_data(dev); - if (data) { - denali->revision = data->revision; - denali->caps = data->caps; - denali->ecc_caps = data->ecc_caps; - } + if (WARN_ON(!data)) + return -EINVAL; + + denali->revision = data->revision; + denali->caps = data->caps; + denali->oob_skip_bytes = data->oob_skip_bytes; + denali->ecc_caps = data->ecc_caps; denali->dev = dev; From 5bacb4402e338e856410ed841ae9bd85171b5022 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 30 Jan 2020 00:55:57 +0900 Subject: [PATCH 6/9] ARM: uniphier: remove adhoc reset deassertion for the NAND controller Now that the reset controlling of the Denali NAND driver (denali_dt.c) works for this platform, remove the adhoc reset deassert code. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/board_init.c | 2 -- arch/arm/mach-uniphier/clk/Makefile | 4 ++-- arch/arm/mach-uniphier/clk/clk-ld4.c | 32 --------------------------- arch/arm/mach-uniphier/clk/clk-pro4.c | 14 ++---------- arch/arm/mach-uniphier/clk/clk-pro5.c | 14 ++---------- arch/arm/mach-uniphier/clk/clk-pxs2.c | 14 ++---------- arch/arm/mach-uniphier/init.h | 1 - 7 files changed, 8 insertions(+), 73 deletions(-) delete mode 100644 arch/arm/mach-uniphier/clk/clk-ld4.c diff --git a/arch/arm/mach-uniphier/board_init.c b/arch/arm/mach-uniphier/board_init.c index 7535f915286..99727a30042 100644 --- a/arch/arm/mach-uniphier/board_init.c +++ b/arch/arm/mach-uniphier/board_init.c @@ -40,7 +40,6 @@ static const struct uniphier_initdata uniphier_initdata[] = { .soc_id = UNIPHIER_LD4_ID, .sbc_init = uniphier_ld4_sbc_init, .pll_init = uniphier_ld4_pll_init, - .clk_init = uniphier_ld4_clk_init, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PRO4) @@ -56,7 +55,6 @@ static const struct uniphier_initdata uniphier_initdata[] = { .soc_id = UNIPHIER_SLD8_ID, .sbc_init = uniphier_ld4_sbc_init, .pll_init = uniphier_ld4_pll_init, - .clk_init = uniphier_ld4_clk_init, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PRO5) diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile index d12f49e5230..c49e44754c0 100644 --- a/arch/arm/mach-uniphier/clk/Makefile +++ b/arch/arm/mach-uniphier/clk/Makefile @@ -11,9 +11,9 @@ obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o else -obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-ld4.o pll-ld4.o dpll-tail.o +obj-$(CONFIG_ARCH_UNIPHIER_LD4) += pll-ld4.o dpll-tail.o obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-pro4.o pll-pro4.o dpll-tail.o -obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o pll-ld4.o dpll-tail.o +obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += pll-ld4.o dpll-tail.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o diff --git a/arch/arm/mach-uniphier/clk/clk-ld4.c b/arch/arm/mach-uniphier/clk/clk-ld4.c deleted file mode 100644 index 03939425039..00000000000 --- a/arch/arm/mach-uniphier/clk/clk-ld4.c +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2011-2015 Panasonic Corporation - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - */ - -#include - -#include "../init.h" -#include "../sc-regs.h" - -void uniphier_ld4_clk_init(void) -{ - u32 tmp; - - /* deassert reset */ - tmp = readl(sc_base + SC_RSTCTRL); -#ifdef CONFIG_NAND_DENALI - tmp |= SC_RSTCTRL_NRST_NAND; -#endif - writel(tmp, sc_base + SC_RSTCTRL); - readl(sc_base + SC_RSTCTRL); /* dummy read */ - - /* provide clocks */ - tmp = readl(sc_base + SC_CLKCTRL); -#ifdef CONFIG_NAND_DENALI - tmp |= SC_CLKCTRL_CEN_NAND; -#endif - writel(tmp, sc_base + SC_CLKCTRL); - readl(sc_base + SC_CLKCTRL); /* dummy read */ -} diff --git a/arch/arm/mach-uniphier/clk/clk-pro4.c b/arch/arm/mach-uniphier/clk/clk-pro4.c index 2b364dca410..798128b3024 100644 --- a/arch/arm/mach-uniphier/clk/clk-pro4.c +++ b/arch/arm/mach-uniphier/clk/clk-pro4.c @@ -12,36 +12,26 @@ void uniphier_pro4_clk_init(void) { +#ifdef CONFIG_USB_DWC3_UNIPHIER u32 tmp; /* deassert reset */ tmp = readl(sc_base + SC_RSTCTRL); -#ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 | SC_RSTCTRL_NRST_GIO; -#endif -#ifdef CONFIG_NAND_DENALI - tmp |= SC_RSTCTRL_NRST_NAND; -#endif writel(tmp, sc_base + SC_RSTCTRL); readl(sc_base + SC_RSTCTRL); /* dummy read */ -#ifdef CONFIG_USB_DWC3_UNIPHIER tmp = readl(sc_base + SC_RSTCTRL2); tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1; writel(tmp, sc_base + SC_RSTCTRL2); readl(sc_base + SC_RSTCTRL2); /* dummy read */ -#endif /* provide clocks */ tmp = readl(sc_base + SC_CLKCTRL); -#ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | SC_CLKCTRL_CEN_GIO; -#endif -#ifdef CONFIG_NAND_DENALI - tmp |= SC_CLKCTRL_CEN_NAND; -#endif writel(tmp, sc_base + SC_CLKCTRL); readl(sc_base + SC_CLKCTRL); /* dummy read */ +#endif } diff --git a/arch/arm/mach-uniphier/clk/clk-pro5.c b/arch/arm/mach-uniphier/clk/clk-pro5.c index 874964b2d5b..36006fd256c 100644 --- a/arch/arm/mach-uniphier/clk/clk-pro5.c +++ b/arch/arm/mach-uniphier/clk/clk-pro5.c @@ -10,35 +10,25 @@ void uniphier_pro5_clk_init(void) { +#ifdef CONFIG_USB_DWC3_UNIPHIER u32 tmp; /* deassert reset */ tmp = readl(sc_base + SC_RSTCTRL); -#ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO; -#endif -#ifdef CONFIG_NAND_DENALI - tmp |= SC_RSTCTRL_NRST_NAND; -#endif writel(tmp, sc_base + SC_RSTCTRL); readl(sc_base + SC_RSTCTRL); /* dummy read */ -#ifdef CONFIG_USB_DWC3_UNIPHIER tmp = readl(sc_base + SC_RSTCTRL2); tmp |= SC_RSTCTRL2_NRST_USB3B1; writel(tmp, sc_base + SC_RSTCTRL2); readl(sc_base + SC_RSTCTRL2); /* dummy read */ -#endif /* provide clocks */ tmp = readl(sc_base + SC_CLKCTRL); -#ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | SC_CLKCTRL_CEN_GIO; -#endif -#ifdef CONFIG_NAND_DENALI - tmp |= SC_CLKCTRL_CEN_NAND; -#endif writel(tmp, sc_base + SC_CLKCTRL); readl(sc_base + SC_CLKCTRL); /* dummy read */ +#endif } diff --git a/arch/arm/mach-uniphier/clk/clk-pxs2.c b/arch/arm/mach-uniphier/clk/clk-pxs2.c index 8cb4f87ae54..c2a75ce0001 100644 --- a/arch/arm/mach-uniphier/clk/clk-pxs2.c +++ b/arch/arm/mach-uniphier/clk/clk-pxs2.c @@ -11,20 +11,15 @@ void uniphier_pxs2_clk_init(void) { +#ifdef CONFIG_USB_DWC3_UNIPHIER u32 tmp; /* deassert reset */ tmp = readl(sc_base + SC_RSTCTRL); -#ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO; -#endif -#ifdef CONFIG_NAND_DENALI - tmp |= SC_RSTCTRL_NRST_NAND; -#endif writel(tmp, sc_base + SC_RSTCTRL); readl(sc_base + SC_RSTCTRL); /* dummy read */ -#ifdef CONFIG_USB_DWC3_UNIPHIER tmp = readl(sc_base + SC_RSTCTRL2); tmp |= SC_RSTCTRL2_NRST_USB3B1; writel(tmp, sc_base + SC_RSTCTRL2); @@ -33,17 +28,12 @@ void uniphier_pxs2_clk_init(void) tmp = readl(sc_base + SC_RSTCTRL6); tmp |= 0x37; writel(tmp, sc_base + SC_RSTCTRL6); -#endif /* provide clocks */ tmp = readl(sc_base + SC_CLKCTRL); -#ifdef CONFIG_USB_DWC3_UNIPHIER tmp |= BIT(20) | BIT(19) | SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | SC_CLKCTRL_CEN_GIO; -#endif -#ifdef CONFIG_NAND_DENALI - tmp |= SC_CLKCTRL_CEN_NAND; -#endif writel(tmp, sc_base + SC_CLKCTRL); readl(sc_base + SC_CLKCTRL); /* dummy read */ +#endif } diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h index b37ab2fa508..9dc5b885a5f 100644 --- a/arch/arm/mach-uniphier/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -90,7 +90,6 @@ void uniphier_ld11_pll_init(void); void uniphier_ld20_pll_init(void); void uniphier_pxs3_pll_init(void); -void uniphier_ld4_clk_init(void); void uniphier_pro4_clk_init(void); void uniphier_pro5_clk_init(void); void uniphier_pxs2_clk_init(void); From 407b01b3b3f548d951b3c35a40bb49bb82f31748 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 30 Jan 2020 22:07:59 +0900 Subject: [PATCH 7/9] mtd: rawnand: denali_dt: use UCLASS_MTD instead of UCLASS_MISC UCLASS_MTD is a better fit for NAND drivers. Make NAND_DENALI_DT depend on DM_MTD, which is needed to compile drivers/mtd/mtd-uclass.c Also, make ARCH_UNIPHIER select DM_MTD because all the defconfig of this platform enables NAND_DENALI_DT. Signed-off-by: Masahiro Yamada Reviewed-by: Miquel Raynal --- arch/arm/Kconfig | 1 + drivers/mtd/nand/raw/Kconfig | 2 +- drivers/mtd/nand/raw/denali_dt.c | 4 ++-- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 12363151688..f04b6a6d368 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1548,6 +1548,7 @@ config ARCH_UNIPHIER select DM_GPIO select DM_I2C select DM_MMC + select DM_MTD select DM_RESET select DM_SERIAL select DM_USB diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 7814d84ba01..23201ca7204 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -116,7 +116,7 @@ config NAND_DENALI config NAND_DENALI_DT bool "Support Denali NAND controller as a DT device" select NAND_DENALI - depends on OF_CONTROL && DM + depends on OF_CONTROL && DM_MTD help Enable the driver for NAND flash on platforms using a Denali NAND controller as a DT device. diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index 587e480faa1..759ad40e517 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -160,7 +160,7 @@ static int denali_dt_probe(struct udevice *dev) U_BOOT_DRIVER(denali_nand_dt) = { .name = "denali-nand-dt", - .id = UCLASS_MISC, + .id = UCLASS_MTD, .of_match = denali_nand_dt_ids, .probe = denali_dt_probe, .priv_auto_alloc_size = sizeof(struct denali_nand_info), @@ -171,7 +171,7 @@ void board_nand_init(void) struct udevice *dev; int ret; - ret = uclass_get_device_by_driver(UCLASS_MISC, + ret = uclass_get_device_by_driver(UCLASS_MTD, DM_GET_DRIVER(denali_nand_dt), &dev); if (ret && ret != -ENODEV) From 6da69d33f5280c9c80690310e1fb3d3e1c821d3e Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 30 Jan 2020 22:20:37 +0900 Subject: [PATCH 8/9] ARM: uniphier: set gd->ram_base correctly gd->ram_base is not set at all if the end address of the DRAM ch0 exceeds the 4GB limit. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/dram_init.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index 13821a92883..5f9d90fe6dc 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -248,12 +248,7 @@ int dram_init(void) max_size = (1ULL << 32) - dram_map[i].base; - if (dram_map[i].size > max_size) { - gd->ram_size += max_size; - break; - } - - gd->ram_size += dram_map[i].size; + gd->ram_size = min(dram_map[i].size, max_size); if (!valid_bank_found) gd->ram_base = dram_map[i].base; From 76cd7d47fb8ac191553b741bb424e93c94ca759a Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 30 Jan 2020 22:20:38 +0900 Subject: [PATCH 9/9] ARM: uniphier: use $loadaddr for source command If the "source" command is not given the address, it uses CONFIG_SYS_LOAD_ADDR, which is compile-time determined. Using the "loadaddr" environment variable is handier because it is relocated according to the memory base when CONFIG_POSITION_INDEPENDENT is enabled. Signed-off-by: Masahiro Yamada --- include/configs/uniphier.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 29866668c49..b95fb9c93fa 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -169,17 +169,17 @@ "ubi part UBI && " \ "ubifsmount ubi0:boot && " \ "ubifsload ${loadaddr} ${script} && " \ - "source\0" \ + "source $loadaddr\0" \ "norscript=echo Running ${script} from tftp ... && " \ "tftpboot ${script} &&" \ - "source\0" \ + "source $loadaddr\0" \ "usbscript=usb start && " \ "setenv devtype usb && " \ "setenv devnum 0 && " \ "run loadscript_fat\0" \ "loadscript_fat=echo Running ${script} from ${devtype}${devnum} ... && " \ "load ${devtype} ${devnum}:1 ${loadaddr} ${script} && " \ - "source\0" \ + "source $loadaddr\0" \ "sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \ "tftpboot $tmp_addr $second_image && " \ "setexpr tmp_addr $nor_base + 0x70000 && " \