Djam/u-boot
1
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2025-05-08 10:39:08 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

powerpc/8xxx: Enabled address hashing for 85xx

Browse source 
For 85xx silicon which supports address hashing, it can be activated by
hwconfig.

Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
york 2010-07-02 22:25:54 +00:00 • committed by Kumar Gala
parent 5800e7ab32
commit 7fd101c97b
5 changed files with 34 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

15
doc/README.fsl-ddr
View file

@ -71,5 +71,16 @@ The ways to configure the ddr interleaving mode
# bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
The above memory controller interleaving and bank interleaving can be mixed. The syntax is
setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1"
Memory controller address hashing
==================================
If the DDR controller supports address hashing, it can be enabled by hwconfig.
Syntax is:
hwconfig=fsl_ddr:addr_hash=true
Combination of hwconfig
=======================
Hwconfig can be combined with multiple parameters, for example, on a supported
platform
hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3