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net: mediatek: fix coding style of AN8855 switch driver

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This patch fixed the following coding style suggested by checkpatch.pl:
1. Use tab instead of space
2. Use BIT() instead of <<
3. Use mdelay for long time delay
4. Remove useless parenthesises

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This commit is contained in:
Weijie Gao 2025-01-24 16:04:28 +08:00 • committed by Tom Rini
parent ea02a07728
commit 7f95b5d7e6
1 changed files with 44 additions and 45 deletions
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65
drivers/net/mtk_eth/an8855.c
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@ -22,7 +22,7 @@
#define AN8855_FORCE_MODE_LNK BIT(31) #define AN8855_FORCE_MODE_LNK BIT(31)
#define AN8855_FORCE_MODE 0xb31593f0 #define AN8855_FORCE_MODE 0xb31593f0
#define AN8855_PORT_CTRL_BASE (0x10208000) #define AN8855_PORT_CTRL_BASE 0x10208000
#define AN8855_PORT_CTRL_REG(p, r) (AN8855_PORT_CTRL_BASE + (p) * 0x200 + (r)) #define AN8855_PORT_CTRL_REG(p, r) (AN8855_PORT_CTRL_BASE + (p) * 0x200 + (r))
#define AN8855_PORTMATRIX_REG(p) AN8855_PORT_CTRL_REG(p, 0x44) #define AN8855_PORTMATRIX_REG(p) AN8855_PORT_CTRL_REG(p, 0x44)
@ -135,49 +135,49 @@
#define PHY_SINGLE_LED_ON_DUR(i) (0x3e9 + ((i) * 2)) #define PHY_SINGLE_LED_ON_DUR(i) (0x3e9 + ((i) * 2))
#define PHY_SINGLE_LED_BLK_DUR(i) (0x3ea + ((i) * 2)) #define PHY_SINGLE_LED_BLK_DUR(i) (0x3ea + ((i) * 2))
#define PHY_PMA_CTRL (0x340) #define PHY_PMA_CTRL 0x340
#define PHY_DEV1F 0x1f #define PHY_DEV1F 0x1f
#define PHY_LED_ON_CTRL(i) (0x24 + ((i) * 2)) #define PHY_LED_ON_CTRL(i) (0x24 + ((i) * 2))
#define LED_ON_EN (1 << 15) #define LED_ON_EN BIT(15)
#define LED_ON_POL (1 << 14) #define LED_ON_POL BIT(14)
#define LED_ON_EVT_MASK (0x7f) #define LED_ON_EVT_MASK 0x7f
/* LED ON Event */ /* LED ON Event */
#define LED_ON_EVT_FORCE (1 << 6) #define LED_ON_EVT_FORCE BIT(6)
#define LED_ON_EVT_LINK_HD (1 << 5) #define LED_ON_EVT_LINK_HD BIT(5)
#define LED_ON_EVT_LINK_FD (1 << 4) #define LED_ON_EVT_LINK_FD BIT(4)
#define LED_ON_EVT_LINK_DOWN (1 << 3) #define LED_ON_EVT_LINK_DOWN BIT(3)
#define LED_ON_EVT_LINK_10M (1 << 2) #define LED_ON_EVT_LINK_10M BIT(2)
#define LED_ON_EVT_LINK_100M (1 << 1) #define LED_ON_EVT_LINK_100M BIT(1)
#define LED_ON_EVT_LINK_1000M (1 << 0) #define LED_ON_EVT_LINK_1000M BIT(0)
#define PHY_LED_BLK_CTRL(i) (0x25 + ((i) * 2)) #define PHY_LED_BLK_CTRL(i) (0x25 + ((i) * 2))
#define LED_BLK_EVT_MASK (0x3ff) #define LED_BLK_EVT_MASK 0x3ff
/* LED Blinking Event */ /* LED Blinking Event */
#define LED_BLK_EVT_FORCE (1 << 9) #define LED_BLK_EVT_FORCE BIT(9)
#define LED_BLK_EVT_10M_RX_ACT (1 << 5) #define LED_BLK_EVT_10M_RX_ACT BIT(5)
#define LED_BLK_EVT_10M_TX_ACT (1 << 4) #define LED_BLK_EVT_10M_TX_ACT BIT(4)
#define LED_BLK_EVT_100M_RX_ACT (1 << 3) #define LED_BLK_EVT_100M_RX_ACT BIT(3)
#define LED_BLK_EVT_100M_TX_ACT (1 << 2) #define LED_BLK_EVT_100M_TX_ACT BIT(2)
#define LED_BLK_EVT_1000M_RX_ACT (1 << 1) #define LED_BLK_EVT_1000M_RX_ACT BIT(1)
#define LED_BLK_EVT_1000M_TX_ACT (1 << 0) #define LED_BLK_EVT_1000M_TX_ACT BIT(0)
#define PHY_LED_BCR (0x21) #define PHY_LED_BCR (0x21)
#define LED_BCR_EXT_CTRL (1 << 15) #define LED_BCR_EXT_CTRL BIT(15)
#define LED_BCR_CLK_EN (1 << 3) #define LED_BCR_CLK_EN BIT(3)
#define LED_BCR_TIME_TEST (1 << 2) #define LED_BCR_TIME_TEST BIT(2)
#define LED_BCR_MODE_MASK (3) #define LED_BCR_MODE_MASK 3
#define LED_BCR_MODE_DISABLE (0) #define LED_BCR_MODE_DISABLE 0
#define PHY_LED_ON_DUR (0x22) #define PHY_LED_ON_DUR 0x22
#define LED_ON_DUR_MASK (0xffff) #define LED_ON_DUR_MASK 0xffff
#define PHY_LED_BLK_DUR (0x23) #define PHY_LED_BLK_DUR 0x23
#define LED_BLK_DUR_MASK (0xffff) #define LED_BLK_DUR_MASK 0xffff
#define PHY_LED_BLINK_DUR_CTRL (0x720) #define PHY_LED_BLINK_DUR_CTRL 0x720
/* Definition of LED */ /* Definition of LED */
#define LED_ON_EVENT (LED_ON_EVT_LINK_1000M | \ #define LED_ON_EVENT (LED_ON_EVT_LINK_1000M | \
@ -993,7 +993,7 @@ static int an8855_setup(struct mtk_eth_switch_priv *swpriv)
/* Switch soft reset */ /* Switch soft reset */
an8855_reg_write(priv, AN8855_SYS_CTRL_REG, AN8855_SW_SYS_RST); an8855_reg_write(priv, AN8855_SYS_CTRL_REG, AN8855_SW_SYS_RST);
udelay(100000); mdelay(100);
an8855_reg_read(priv, AN8855_PKG_SEL, &val); an8855_reg_read(priv, AN8855_PKG_SEL, &val);
if ((val & 0x7) == PAG_SEL_AN8855H) { if ((val & 0x7) == PAG_SEL_AN8855H) {
@ -1003,8 +1003,7 @@ static int an8855_setup(struct mtk_eth_switch_priv *swpriv)
/* Invert for LED activity change */ /* Invert for LED activity change */
an8855_reg_read(priv, AN8855_RG_GPIO_L_INV, &val); an8855_reg_read(priv, AN8855_RG_GPIO_L_INV, &val);
for (id = 0; id < ARRAY_SIZE(led_cfg); id++) { for (id = 0; id < ARRAY_SIZE(led_cfg); id++) {
if ((led_cfg[id].pol == LED_HIGH) && if (led_cfg[id].pol == LED_HIGH && led_cfg[id].en == 1)
(led_cfg[id].en == 1))
val |= 0x1 << id; val |= 0x1 << id;
} }
an8855_reg_write(priv, AN8855_RG_GPIO_L_INV, (val | 0x1)); an8855_reg_write(priv, AN8855_RG_GPIO_L_INV, (val | 0x1));