Merge branch '2022-03-25-assorted-updates' into next

- Assorted PCI cleanups
- Allow building with -Og
- ast2600 pwm support
- PFUZE100 bootcount driver

Kconfig

@@ -72,15 +72,32 @@ config CLANG_VERSION
 	int
 	default $(shell,$(srctree)/scripts/clang-version.sh $(CC))
 
+choice
+	prompt "Optimization level"
+	default CC_OPTIMIZE_FOR_SIZE
+
 config CC_OPTIMIZE_FOR_SIZE
 	bool "Optimize for size"
-	default y
 	help
-	  Enabling this option will pass "-Os" instead of "-O2" to gcc
+	  Enabling this option will pass "-Os" to gcc, resulting in a smaller
-	  resulting in a smaller U-Boot image.
+	  U-Boot image.
 
 	  This option is enabled by default for U-Boot.
 
+config CC_OPTIMIZE_FOR_SPEED
+	bool "Optimize for speed"
+	help
+	  Enabling this option will pass "-O2" to gcc, resulting in a faster
+	  U-Boot image.
+
+config CC_OPTIMIZE_FOR_DEBUG
+	bool "Optimize for debugging"
+	help
+	  Enabling this option will pass "-Og" to gcc, enabling optimizations
+	  which don't interfere with debugging.
+
+endchoice
+
 config OPTIMIZE_INLINING
 	bool "Allow compiler to uninline functions marked 'inline' in full U-Boot"
 	help

Makefile

@@ -683,10 +683,16 @@ endif
 
 ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE
 KBUILD_CFLAGS	+= -Os
-else
+endif
+
+ifdef CONFIG_CC_OPTIMIZE_FOR_SPEED
 KBUILD_CFLAGS	+= -O2
 endif
 
+ifdef CONFIG_CC_OPTIMIZE_FOR_DEBUG
+KBUILD_CFLAGS	+= -Og
+endif
+
 LTO_CFLAGS :=
 LTO_FINAL_LDFLAGS :=
 export LTO_CFLAGS LTO_FINAL_LDFLAGS

arch/arm/dts/ast2600-evb.dts

@@ -37,6 +37,26 @@
 	};
 };
 
+&pwm {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm0_default
+			&pinctrl_pwm1_default
+			&pinctrl_pwm2_default
+			&pinctrl_pwm3_default
+			&pinctrl_pwm4_default
+			&pinctrl_pwm5_default
+			&pinctrl_pwm6_default
+			&pinctrl_pwm7_default
+			&pinctrl_pwm8g1_default
+			&pinctrl_pwm9g1_default
+			&pinctrl_pwm10g1_default
+			&pinctrl_pwm11g1_default
+			&pinctrl_pwm12g1_default
+			&pinctrl_pwm13g1_default
+			&pinctrl_pwm14g1_default>;
+};
+
 &uart5 {
 	u-boot,dm-pre-reloc;
 	status = "okay";

arch/arm/dts/ast2600.dtsi

@@ -113,6 +113,21 @@
 			reg = < 0x1e600000 0x100>;
 		};
 
+		pwm_tach: pwm_tach@1e610000 {
+			compatible = "aspeed,ast2600-pwm-tach", "simple-mfd", "syscon";
+			reg = <0x1e610000 0x100>;
+			clocks = <&scu ASPEED_CLK_AHB>;
+			resets = <&rst ASPEED_RESET_PWM>;
+
+			pwm: pwm {
+				compatible = "aspeed,ast2600-pwm";
+				#pwm-cells = <3>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+		};
+
 		fmc: flash-controller@1e620000 {
 			reg = < 0x1e620000 0xc4
 				0x20000000 0x10000000 >;
@@ -1626,6 +1641,86 @@
 		groups = "PWM7";
 	};
 
+	pinctrl_pwm8g0_default: pwm8g0_default {
+		function = "PWM8G0";
+		groups = "PWM8G0";
+	};
+
+	pinctrl_pwm8g1_default: pwm8g1_default {
+		function = "PWM8G1";
+		groups = "PWM8G1";
+	};
+
+	pinctrl_pwm9g0_default: pwm9g0_default {
+		function = "PWM9G0";
+		groups = "PWM9G0";
+	};
+
+	pinctrl_pwm9g1_default: pwm9g1_default {
+		function = "PWM9G1";
+		groups = "PWM9G1";
+	};
+
+	pinctrl_pwm10g0_default: pwm10g0_default {
+		function = "PWM10G0";
+		groups = "PWM10G0";
+	};
+
+	pinctrl_pwm10g1_default: pwm10g1_default {
+		function = "PWM10G1";
+		groups = "PWM10G1";
+	};
+
+	pinctrl_pwm11g0_default: pwm11g0_default {
+		function = "PWM11G0";
+		groups = "PWM11G0";
+	};
+
+	pinctrl_pwm11g1_default: pwm11g1_default {
+		function = "PWM11G1";
+		groups = "PWM11G1";
+	};
+
+	pinctrl_pwm12g0_default: pwm12g0_default {
+		function = "PWM12G0";
+		groups = "PWM12G0";
+	};
+
+	pinctrl_pwm12g1_default: pwm12g1_default {
+		function = "PWM12G1";
+		groups = "PWM12G1";
+	};
+
+	pinctrl_pwm13g0_default: pwm13g0_default {
+		function = "PWM13G0";
+		groups = "PWM13G0";
+	};
+
+	pinctrl_pwm13g1_default: pwm13g1_default {
+		function = "PWM13G1";
+		groups = "PWM13G1";
+	};
+
+	pinctrl_pwm14g0_default: pwm14g0_default {
+		function = "PWM14G0";
+		groups = "PWM14G0";
+	};
+
+	pinctrl_pwm14g1_default: pwm14g1_default {
+		function = "PWM14G1";
+		groups = "PWM14G1";
+	};
+
+	pinctrl_pwm15g0_default: pwm15g0_default {
+		function = "PWM15G0";
+		groups = "PWM15G0";
+	};
+
+	pinctrl_pwm15g1_default: pwm15g1_default {
+		function = "PWM15G1";
+		groups = "PWM15G1";
+	};
+
 	pinctrl_rgmii1_default: rgmii1_default {
 		function = "RGMII1";
 		groups = "RGMII1";

arch/sandbox/include/asm/test.h

@@ -9,6 +9,7 @@
 #define __ASM_TEST_H
 
 #include <video.h>
+#include <pci_ids.h>
 
 /* The sandbox driver always permits an I2C device with this address */
 #define SANDBOX_I2C_TEST_ADDR		0x59
@@ -17,8 +18,8 @@
 #define SANDBOX_PCI_SWAP_CASE_EMUL_ID	0x5678
 #define SANDBOX_PCI_PMC_EMUL_ID		0x5677
 #define SANDBOX_PCI_P2SB_EMUL_ID	0x5676
-#define SANDBOX_PCI_CLASS_CODE		PCI_CLASS_CODE_COMM
+#define SANDBOX_PCI_CLASS_CODE		(PCI_CLASS_COMMUNICATION_SERIAL >> 8)
-#define SANDBOX_PCI_CLASS_SUB_CODE	PCI_CLASS_SUB_CODE_COMM_SERIAL
+#define SANDBOX_PCI_CLASS_SUB_CODE	(PCI_CLASS_COMMUNICATION_SERIAL & 0xff)
 
 #define PCI_CAP_ID_PM_OFFSET		0x50
 #define PCI_CAP_ID_EXP_OFFSET		0x60

arch/sh/lib/Makefile

@@ -12,7 +12,7 @@ obj-$(CONFIG_CMD_SH_ZIMAGEBOOT) += zimageboot.o
 
 udivsi3-y			:= udivsi3_i4i-Os.o
 
-ifneq ($(CONFIG_CC_OPTIMIZE_FOR_SIZE),y)
+ifeq ($(CONFIG_CC_OPTIMIZE_FOR_SPEED),y)
 udivsi3-$(CONFIG_CPU_SH4)	:= udivsi3_i4i.o
 endif
 udivsi3-y			+= udivsi3.o

board/armltd/vexpress64/pcie.c

@@ -150,7 +150,7 @@ static void xr3pci_init(void)
 	/* allow ECRC */
 	writel(0x6006, XR3_CONFIG_BASE + XR3PCI_PEX_SPC2);
 	/* setup the correct class code for the host bridge */
-	writel(PCI_CLASS_BRIDGE_PCI << 16, XR3_CONFIG_BASE + XR3PCI_BRIDGE_PCI_IDS);
+	writel(PCI_CLASS_BRIDGE_PCI_NORMAL << 8, XR3_CONFIG_BASE + XR3PCI_BRIDGE_PCI_IDS);
 
 	/* reset phy and root complex */
 	writel(JUNO_RESET_CTRL_PHY | JUNO_RESET_CTRL_RC,

disk/Kconfig

@@ -4,10 +4,6 @@ menu "Partition Types"
 config PARTITIONS
 	bool "Enable Partition Labels (disklabels) support"
 	default y
-	select SPL_SPRINTF if SPL
-	select TPL_SPRINTF if TPL
-	select SPL_STRTO if SPL
-	select TPL_STRTO if TPL
 	help
 	  Partition Labels (disklabels) Supported:
 	  Zero or more of the following:
@@ -23,6 +19,26 @@ config PARTITIONS
 	  you must configure support for at least one non-MTD partition type
 	  as well.
 
+config SPL_PARTITIONS
+	bool "Enable Partition Labels (disklabels) support in SPL"
+	default y if PARTITIONS
+	select SPL_SPRINTF
+	select SPL_STRTO
+	help
+	  Enable this for base partition support in SPL. The required
+	  partition table types shold be enabled separately. This add a
+	  small amount of size to SPL, typically 500 bytes.
+
+config TPL_PARTITIONS
+	bool "Enable Partition Labels (disklabels) support in TPL"
+	default y if PARTITIONS
+	select TPL_SPRINTF
+	select TPL_STRTO
+	help
+	  Enable this for base partition support in SPL. The required
+	  partition table types shold be enabled separately. This add a
+	  small amount of size to SPL, typically 500 bytes.
+
 config MAC_PARTITION
 	bool "Enable Apple's MacOS partition table"
 	depends on PARTITIONS

disk/Makefile

@@ -5,7 +5,7 @@
 
 #ccflags-y += -DET_DEBUG -DDEBUG
 
-obj-$(CONFIG_PARTITIONS)	+= part.o
+obj-$(CONFIG_$(SPL_TPL_)PARTITIONS)  += part.o
 obj-$(CONFIG_$(SPL_)MAC_PARTITION)   += part_mac.o
 obj-$(CONFIG_$(SPL_)DOS_PARTITION)   += part_dos.o
 obj-$(CONFIG_$(SPL_)ISO_PARTITION)   += part_iso.o

drivers/block/blk-uclass.c

@@ -712,7 +712,7 @@ int blk_unbind_all(int if_type)
 
 static int blk_post_probe(struct udevice *dev)
 {
-	if (IS_ENABLED(CONFIG_PARTITIONS) &&
+	if (CONFIG_IS_ENABLED(PARTITIONS) &&
 	    IS_ENABLED(CONFIG_HAVE_BLOCK_DEVICE)) {
 		struct blk_desc *desc = dev_get_uclass_plat(dev);
 

drivers/bootcount/Kconfig

@@ -127,6 +127,13 @@ config DM_BOOTCOUNT_I2C_EEPROM
 	  pointing to the underlying i2c eeprom device) and an optional 'offset'
 	  property are supported.
 
+config DM_BOOTCOUNT_PMIC_PFUZE100
+	bool "Enable Bootcount driver for PMIC PFUZE100"
+	depends on DM_PMIC_PFUZE100
+	help
+	  Enable support for the bootcounter using PMIC PFUZE100 registers.
+	  This works only, if the PMIC is not connected.
+
 config DM_BOOTCOUNT_SPI_FLASH
 	bool "Support SPI flash devices as a backing store for bootcount"
 	depends on DM_SPI_FLASH

drivers/bootcount/Makefile

@@ -11,6 +11,7 @@ obj-$(CONFIG_BOOTCOUNT_EXT)	+= bootcount_ext.o
 obj-$(CONFIG_BOOTCOUNT_AM33XX_NVMEM)	+= bootcount_nvmem.o
 
 obj-$(CONFIG_DM_BOOTCOUNT)      += bootcount-uclass.o
+obj-$(CONFIG_DM_BOOTCOUNT_PMIC_PFUZE100) += pmic_pfuze100.o
 obj-$(CONFIG_DM_BOOTCOUNT_RTC)  += rtc.o
 obj-$(CONFIG_DM_BOOTCOUNT_I2C_EEPROM)	+= i2c-eeprom.o
 obj-$(CONFIG_DM_BOOTCOUNT_SPI_FLASH)	+= spi-flash.o

drivers/bootcount/pmic_pfuze100.c

@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018-2022 Denx Software Engineering GmbH
+ * Heiko Schocher <hs@denx.de>
+ * Philip Oberfichtner <pro@denx.de>
+ *
+ * A bootcount driver using the registers MEMA - MEMD on the PFUZE100.
+ * This works only, if the PMIC is not connected.
+ */
+
+#include <common.h>
+#include <bootcount.h>
+#include <dm.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PFUZE_BC_MAGIC 0xdead
+
+struct bootcount_pmic_priv {
+	struct udevice *pmic;
+};
+
+static int pfuze100_get_magic(struct udevice *dev, u32 *magic)
+{
+	int ret;
+
+	ret = pmic_reg_read(dev, PFUZE100_MEMA);
+	if (ret < 0)
+		return ret;
+	*magic = ret;
+
+	ret = pmic_reg_read(dev, PFUZE100_MEMB);
+	if (ret < 0)
+		return ret;
+	*magic += ret << 8;
+
+	return 0;
+}
+
+static int pfuze100_set_magic(struct udevice *dev)
+{
+	int ret;
+
+	ret = pmic_reg_write(dev, PFUZE100_MEMA, PFUZE_BC_MAGIC & 0xff);
+	if (ret)
+		return ret;
+
+	ret = pmic_reg_write(dev, PFUZE100_MEMB, (PFUZE_BC_MAGIC >> 8) & 0xff);
+	return ret;
+}
+
+static int pfuze100_get_value(struct udevice *dev, u32 *a)
+{
+	int ret;
+
+	ret = pmic_reg_read(dev, PFUZE100_MEMC);
+	if (ret < 0)
+		return ret;
+	*a = ret;
+
+	ret = pmic_reg_read(dev, PFUZE100_MEMD);
+	if (ret < 0)
+		return ret;
+	*a += ret << 8;
+
+	return 0;
+}
+
+static int pfuze100_set_value(struct udevice *dev, u32 val)
+{
+	int ret;
+
+	ret = pmic_reg_write(dev, PFUZE100_MEMC, val & 0xff);
+	if (ret)
+		return ret;
+
+	ret = pmic_reg_write(dev, PFUZE100_MEMD, (val >> 8) & 0xff);
+	return ret;
+}
+
+static int bootcount_pmic_set(struct udevice *dev, const u32 a)
+{
+	struct bootcount_pmic_priv *priv = dev_get_priv(dev);
+
+	if (pfuze100_set_magic(priv->pmic)) {
+		debug("%s: writing magic failed\n", __func__);
+		return -EIO;
+	}
+
+	if (pfuze100_set_value(priv->pmic, a)) {
+		debug("%s: writing value failed\n", __func__);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int bootcount_pmic_get(struct udevice *dev, u32 *a)
+{
+	struct bootcount_pmic_priv *priv = dev_get_priv(dev);
+	u32 magic;
+
+	if (pfuze100_get_magic(priv->pmic, &magic)) {
+		debug("%s: reading magic failed\n", __func__);
+		return -EIO;
+	}
+
+	if (magic != PFUZE_BC_MAGIC) {
+		*a = 0;
+		return 0;
+	}
+
+	if (pfuze100_get_value(priv->pmic, a)) {
+		debug("%s: reading value failed\n", __func__);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int bootcount_pmic_probe(struct udevice *dev)
+{
+	struct ofnode_phandle_args phandle_args;
+	struct bootcount_pmic_priv *priv = dev_get_priv(dev);
+	struct udevice *pmic;
+
+	if (dev_read_phandle_with_args(dev, "pmic", NULL, 0, 0, &phandle_args)) {
+		debug("%s: pmic backing device not specified\n", dev->name);
+		return -ENOENT;
+	}
+
+	if (uclass_get_device_by_ofnode(UCLASS_PMIC, phandle_args.node, &pmic)) {
+		debug("%s: could not get backing device\n", dev->name);
+		return -ENODEV;
+	}
+
+	priv->pmic = pmic;
+
+	return 0;
+}
+
+static const struct bootcount_ops bootcount_pmic_ops = {
+	.get = bootcount_pmic_get,
+	.set = bootcount_pmic_set,
+};
+
+static const struct udevice_id bootcount_pmic_ids[] = {
+	{ .compatible = "u-boot,bootcount-pmic" },
+	{ }
+};
+
+U_BOOT_DRIVER(bootcount_pmic) = {
+	.name	= "bootcount-pmic",
+	.id	= UCLASS_BOOTCOUNT,
+	.priv_auto	= sizeof(struct bootcount_pmic_priv),
+	.probe	= bootcount_pmic_probe,
+	.of_match = bootcount_pmic_ids,
+	.ops	= &bootcount_pmic_ops,
+};

drivers/pci/pci-aardvark.c

@@ -800,7 +800,7 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie)
 	 */
 	reg = advk_readl(pcie, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION);
 	reg &= ~0xffffff00;
-	reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8;
+	reg |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
 	advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION);
 
 	/* Enable generation and checking of ECRC on PCIe Root Port */

drivers/pci/pci-rcar-gen3.c

@@ -289,7 +289,7 @@ static int rcar_gen3_pcie_hw_init(struct udevice *dev)
 	 * class to match. Hardware takes care of propagating the IDSETR
 	 * settings, so there is no need to bother with a quirk.
 	 */
-	writel(PCI_CLASS_BRIDGE_PCI << 16, priv->regs + IDSETR1);
+	writel(PCI_CLASS_BRIDGE_PCI_NORMAL << 8, priv->regs + IDSETR1);
 
 	/*
 	 * Setup Secondary Bus Number & Subordinate Bus Number, even though

drivers/pci/pci_mvebu.c

@@ -440,7 +440,7 @@ static int mvebu_pcie_probe(struct udevice *dev)
 	 */
 	reg = readl(pcie->base + MVPCIE_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION);
 	reg &= ~0xffffff00;
-	reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8;
+	reg |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
 	writel(reg, pcie->base + MVPCIE_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION);
 
 	/*

drivers/pci/pci_tegra.c

@@ -325,8 +325,8 @@ static int pci_tegra_read_config(const struct udevice *bus, pci_dev_t bdf,
 	/* fixup root port class */
 	if (PCI_BUS(bdf) == 0) {
 		if ((offset & ~3) == PCI_CLASS_REVISION) {
-			value &= ~0x00ff0000;
+			value &= ~0x00ffff00;
-			value |= PCI_CLASS_BRIDGE_PCI << 16;
+			value |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
 		}
 	}
 #endif

drivers/pci/pcie_dw_mvebu.c

@@ -539,9 +539,9 @@ static int pcie_dw_mvebu_probe(struct udevice *dev)
 				  PCIE_ATU_TYPE_MEM, pcie->mem.phys_start,
 				  pcie->mem.bus_start, pcie->mem.size);
 
-	/* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
+	/* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI_NORMAL */
 	clrsetbits_le32(pcie->ctrl_base + PCI_CLASS_REVISION,
-			0xffff << 16, PCI_CLASS_BRIDGE_PCI << 16);
+			0xffffff << 8, PCI_CLASS_BRIDGE_PCI_NORMAL << 8);
 
 	pcie_dw_set_host_bars(pcie->ctrl_base);
 

drivers/pci/pcie_fsl.c

@@ -532,7 +532,7 @@ static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
 
 	fsl_pcie_hose_read_config_dword(pcie, classcode_reg, &val);
 	val &= 0xff;
-	val |= PCI_CLASS_BRIDGE_PCI << 16;
+	val |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
 	fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val);
 
 	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0)

drivers/pci/pcie_imx.c

@@ -300,9 +300,9 @@ static int imx_pcie_regions_setup(struct imx_pcie_priv *priv)
 	setbits_le32(priv->dbi_base + PCI_COMMAND,
 		     PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 
-	/* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
+	/* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI_NORMAL */
 	setbits_le32(priv->dbi_base + PCI_CLASS_REVISION,
-		     PCI_CLASS_BRIDGE_PCI << 16);
+		     PCI_CLASS_BRIDGE_PCI_NORMAL << 8);
 
 	/* Region #0 is used for Outbound CFG space access. */
 	writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);

drivers/pci/pcie_iproc.c

@@ -1123,7 +1123,7 @@ static int iproc_pcie_check_link(struct iproc_pcie *pcie)
 				    PCI_BRIDGE_CTRL_REG_OFFSET,
 				    4, &class);
 	class &= ~PCI_BRIDGE_CTRL_REG_CLASS_MASK;
-	class |= (PCI_CLASS_BRIDGE_PCI << 8);
+	class |= PCI_CLASS_BRIDGE_PCI_NORMAL;
 	iproc_pci_raw_config_write32(pcie, 0,
 				     PCI_BRIDGE_CTRL_REG_OFFSET,
 				     4, class);

drivers/pci/pcie_rockchip.c

@@ -351,7 +351,7 @@ static int rockchip_pcie_init_port(struct udevice *dev)
 
 	/* Initialize Root Complex registers. */
 	writel(PCIE_LM_VENDOR_ROCKCHIP, priv->apb_base + PCIE_LM_VENDOR_ID);
-	writel(PCI_CLASS_BRIDGE_PCI << 16,
+	writel(PCI_CLASS_BRIDGE_PCI_NORMAL << 8,
 	       priv->apb_base + PCIE_RC_BASE + PCI_CLASS_REVISION);
 	writel(PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS,
 	       priv->apb_base + PCIE_LM_RCBAR);

drivers/pinctrl/aspeed/pinctrl_ast2600.c

@@ -335,6 +335,102 @@ static struct aspeed_sig_desc pcie1rc_link[] = {
 	{ 0x500, BIT(24), 0 }, /* dedicate rc reset */
 };
 
+static struct aspeed_sig_desc pwm0[] = {
+	{0x41c, BIT(16), 0},
+};
+
+static struct aspeed_sig_desc pwm1[] = {
+	{0x41c, BIT(17), 0},
+};
+
+static struct aspeed_sig_desc pwm2[] = {
+	{0x41c, BIT(18), 0},
+};
+
+static struct aspeed_sig_desc pwm3[] = {
+	{0x41c, BIT(19), 0},
+};
+
+static struct aspeed_sig_desc pwm4[] = {
+	{0x41c, BIT(20), 0},
+};
+
+static struct aspeed_sig_desc pwm5[] = {
+	{0x41c, BIT(21), 0},
+};
+
+static struct aspeed_sig_desc pwm6[] = {
+	{0x41c, BIT(22), 0},
+};
+
+static struct aspeed_sig_desc pwm7[] = {
+	{0x41c, BIT(23), 0},
+};
+
+static struct aspeed_sig_desc pwm8g0[] = {
+	{0x4B4, BIT(8), 0},
+};
+
+static struct aspeed_sig_desc pwm8g1[] = {
+	{0x41c, BIT(24), 0},
+};
+
+static struct aspeed_sig_desc pwm9g0[] = {
+	{0x4B4, BIT(9), 0},
+};
+
+static struct aspeed_sig_desc pwm9g1[] = {
+	{0x41c, BIT(25), 0},
+};
+
+static struct aspeed_sig_desc pwm10g0[] = {
+	{0x4B4, BIT(10), 0},
+};
+
+static struct aspeed_sig_desc pwm10g1[] = {
+	{0x41c, BIT(26), 0},
+};
+
+static struct aspeed_sig_desc pwm11g0[] = {
+	{0x4B4, BIT(11), 0},
+};
+
+static struct aspeed_sig_desc pwm11g1[] = {
+	{0x41c, BIT(27), 0},
+};
+
+static struct aspeed_sig_desc pwm12g0[] = {
+	{0x4B4, BIT(12), 0},
+};
+
+static struct aspeed_sig_desc pwm12g1[] = {
+	{0x41c, BIT(28), 0},
+};
+
+static struct aspeed_sig_desc pwm13g0[] = {
+	{0x4B4, BIT(13), 0},
+};
+
+static struct aspeed_sig_desc pwm13g1[] = {
+	{0x41c, BIT(29), 0},
+};
+
+static struct aspeed_sig_desc pwm14g0[] = {
+	{0x4B4, BIT(14), 0},
+};
+
+static struct aspeed_sig_desc pwm14g1[] = {
+	{0x41c, BIT(30), 0},
+};
+
+static struct aspeed_sig_desc pwm15g0[] = {
+	{0x4B4, BIT(15), 0},
+};
+
+static struct aspeed_sig_desc pwm15g1[] = {
+	{0x41c, BIT(31), 0},
+};
+
 static const struct aspeed_group_config ast2600_groups[] = {
 	{ "MAC1LINK", ARRAY_SIZE(mac1_link), mac1_link },
 	{ "MAC2LINK", ARRAY_SIZE(mac2_link), mac2_link },
@@ -394,6 +490,30 @@ static const struct aspeed_group_config ast2600_groups[] = {
 	{ "USB2BH", ARRAY_SIZE(usb2bh_link), usb2bh_link },
 	{ "PCIE0RC", ARRAY_SIZE(pcie0rc_link), pcie0rc_link },
 	{ "PCIE1RC", ARRAY_SIZE(pcie1rc_link), pcie1rc_link },
+	{ "PWM0", ARRAY_SIZE(pwm0), pwm0 },
+	{ "PWM1", ARRAY_SIZE(pwm1), pwm1 },
+	{ "PWM2", ARRAY_SIZE(pwm2), pwm2 },
+	{ "PWM3", ARRAY_SIZE(pwm3), pwm3 },
+	{ "PWM4", ARRAY_SIZE(pwm4), pwm4 },
+	{ "PWM5", ARRAY_SIZE(pwm5), pwm5 },
+	{ "PWM6", ARRAY_SIZE(pwm6), pwm6 },
+	{ "PWM7", ARRAY_SIZE(pwm7), pwm7 },
+	{ "PWM8G0", ARRAY_SIZE(pwm8g0), pwm8g0 },
+	{ "PWM8G1", ARRAY_SIZE(pwm8g1), pwm8g1 },
+	{ "PWM9G0", ARRAY_SIZE(pwm9g0), pwm9g0 },
+	{ "PWM9G1", ARRAY_SIZE(pwm9g1), pwm9g1 },
+	{ "PWM10G0", ARRAY_SIZE(pwm10g0), pwm10g0 },
+	{ "PWM10G1", ARRAY_SIZE(pwm10g1), pwm10g1 },
+	{ "PWM11G0", ARRAY_SIZE(pwm11g0), pwm11g0 },
+	{ "PWM11G1", ARRAY_SIZE(pwm11g1), pwm11g1 },
+	{ "PWM12G0", ARRAY_SIZE(pwm12g0), pwm12g0 },
+	{ "PWM12G1", ARRAY_SIZE(pwm12g1), pwm12g1 },
+	{ "PWM13G0", ARRAY_SIZE(pwm13g0), pwm13g0 },
+	{ "PWM13G1", ARRAY_SIZE(pwm13g1), pwm13g1 },
+	{ "PWM14G0", ARRAY_SIZE(pwm14g0), pwm14g0 },
+	{ "PWM14G1", ARRAY_SIZE(pwm14g1), pwm14g1 },
+	{ "PWM15G0", ARRAY_SIZE(pwm15g0), pwm15g0 },
+	{ "PWM15G1", ARRAY_SIZE(pwm15g1), pwm15g1 },
 };
 
 static int ast2600_pinctrl_get_groups_count(struct udevice *dev)

drivers/pwm/Kconfig

@@ -9,6 +9,14 @@ config DM_PWM
 	  frequency/period can be controlled along with the proportion of that
 	  time that the signal is high.
 
+config PWM_ASPEED
+	bool "Enable support for the Aspeed PWM"
+	depends on DM_PWM
+	help
+	  This PWM is found on Ast2600 SoCs. It supports a programmable period
+	  and duty cycle. It provides 16 channels which can be independently
+	  programmed.
+
 config PWM_AT91
 	bool "Enable support for PWM found on AT91 SoC's"
 	depends on DM_PWM && ARCH_AT91

drivers/pwm/Makefile

@@ -10,6 +10,7 @@
 
 obj-$(CONFIG_DM_PWM)		+= pwm-uclass.o
 
+obj-$(CONFIG_PWM_ASPEED)	+= pwm-aspeed.o
 obj-$(CONFIG_PWM_AT91)		+= pwm-at91.o
 obj-$(CONFIG_PWM_CROS_EC)	+= cros_ec_pwm.o
 obj-$(CONFIG_PWM_EXYNOS)	+= exynos_pwm.o

drivers/pwm/pwm-aspeed.c

@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Aspeed Technology Inc.
+ *
+ * PWM controller driver for Aspeed ast2600 SoCs.
+ * This drivers doesn't support earlier version of the IP.
+ *
+ * The formula of pwm period duration:
+ * period duration = ((DIV_L + 1) * (PERIOD + 1) << DIV_H) / input-clk
+ *
+ * The formula of pwm duty cycle duration:
+ * duty cycle duration = period duration * DUTY_CYCLE_FALLING_POINT / (PERIOD + 1)
+ * = ((DIV_L + 1) * DUTY_CYCLE_FALLING_POINT << DIV_H) / input-clk
+ *
+ * The software driver fixes the period to 255, which causes the high-frequency
+ * precision of the PWM to be coarse, in exchange for the fineness of the duty cycle.
+ *
+ * Register usage:
+ * PIN_ENABLE: When it is unset the pwm controller will always output low to the extern.
+ * Use to determine whether the PWM channel is enabled or disabled
+ * CLK_ENABLE: When it is unset the pwm controller will reset the duty counter to 0 and
+ * output low to the PIN_ENABLE mux after that the driver can still change the pwm period
+ * and duty and the value will apply when CLK_ENABLE be set again.
+ * Use to determine whether duty_cycle bigger than 0.
+ * PWM_ASPEED_CTRL_INVERSE: When it is toggled the output value will inverse immediately.
+ * PWM_ASPEED_DUTY_CYCLE_FALLING_POINT/PWM_ASPEED_DUTY_CYCLE_RISING_POINT: When these two
+ * values are equal it means the duty cycle = 100%.
+ *
+ * Limitations:
+ * - When changing both duty cycle and period, we cannot prevent in
+ *   software that the output might produce a period with mixed
+ *   settings.
+ * - Disabling the PWM doesn't complete the current period.
+ *
+ * Improvements:
+ * - When only changing one of duty cycle or period, our pwm controller will not
+ *   generate the glitch, the configure will change at next cycle of pwm.
+ *   This improvement can disable/enable through PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE.
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <dm.h>
+#include <pwm.h>
+#include <clk.h>
+#include <reset.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <dm/device_compat.h>
+#include <linux/math64.h>
+#include <linux/bitfield.h>
+#include <asm/io.h>
+
+/* The channel number of Aspeed pwm controller */
+#define PWM_ASPEED_NR_PWMS 16
+
+/* PWM Control Register */
+#define PWM_ASPEED_CTRL(ch) ((ch) * 0x10 + 0x00)
+#define PWM_ASPEED_CTRL_LOAD_SEL_RISING_AS_WDT BIT(19)
+#define PWM_ASPEED_CTRL_DUTY_LOAD_AS_WDT_ENABLE BIT(18)
+#define PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE BIT(17)
+#define PWM_ASPEED_CTRL_CLK_ENABLE BIT(16)
+#define PWM_ASPEED_CTRL_LEVEL_OUTPUT BIT(15)
+#define PWM_ASPEED_CTRL_INVERSE BIT(14)
+#define PWM_ASPEED_CTRL_OPEN_DRAIN_ENABLE BIT(13)
+#define PWM_ASPEED_CTRL_PIN_ENABLE BIT(12)
+#define PWM_ASPEED_CTRL_CLK_DIV_H GENMASK(11, 8)
+#define PWM_ASPEED_CTRL_CLK_DIV_L GENMASK(7, 0)
+
+/* PWM Duty Cycle Register */
+#define PWM_ASPEED_DUTY_CYCLE(ch) ((ch) * 0x10 + 0x04)
+#define PWM_ASPEED_DUTY_CYCLE_PERIOD GENMASK(31, 24)
+#define PWM_ASPEED_DUTY_CYCLE_POINT_AS_WDT GENMASK(23, 16)
+#define PWM_ASPEED_DUTY_CYCLE_FALLING_POINT GENMASK(15, 8)
+#define PWM_ASPEED_DUTY_CYCLE_RISING_POINT GENMASK(7, 0)
+
+/* PWM fixed value */
+#define PWM_ASPEED_FIXED_PERIOD 0xff
+
+#define NSEC_PER_SEC			1000000000L
+
+struct aspeed_pwm_priv {
+	struct clk clk;
+	struct regmap *regmap;
+	struct reset_ctl reset;
+};
+
+static int aspeed_pwm_set_invert(struct udevice *dev, uint channel, bool polarity)
+{
+	struct aspeed_pwm_priv *priv = dev_get_priv(dev);
+
+	if (channel >= PWM_ASPEED_NR_PWMS)
+		return -EINVAL;
+
+	regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL(channel),
+			   PWM_ASPEED_CTRL_INVERSE,
+			   FIELD_PREP(PWM_ASPEED_CTRL_INVERSE,
+				      polarity));
+	return 0;
+}
+
+static int aspeed_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
+{
+	struct aspeed_pwm_priv *priv = dev_get_priv(dev);
+
+	if (channel >= PWM_ASPEED_NR_PWMS)
+		return -EINVAL;
+
+	regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL(channel),
+			   PWM_ASPEED_CTRL_PIN_ENABLE,
+			   enable ? PWM_ASPEED_CTRL_PIN_ENABLE : 0);
+	return 0;
+}
+
+static int aspeed_pwm_set_config(struct udevice *dev, uint channel,
+				 uint period_ns, uint duty_ns)
+{
+	struct aspeed_pwm_priv *priv = dev_get_priv(dev);
+	u32 duty_pt;
+	unsigned long rate;
+	u64 div_h, div_l, divisor;
+	bool clk_en;
+
+	if (channel >= PWM_ASPEED_NR_PWMS)
+		return -EINVAL;
+	dev_dbg(dev, "expect period: %dns, duty_cycle: %dns\n", period_ns,
+		duty_ns);
+
+	rate = clk_get_rate(&priv->clk);
+	/*
+	 * Pick the smallest value for div_h so that div_l can be the biggest
+	 * which results in a finer resolution near the target period value.
+	 */
+	divisor = (u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1) *
+		  (PWM_ASPEED_CTRL_CLK_DIV_L + 1);
+	div_h = order_base_2(div64_u64((u64)rate * period_ns + divisor - 1, divisor));
+	if (div_h > 0xf)
+		div_h = 0xf;
+
+	divisor = ((u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1)) << div_h;
+	div_l = div64_u64((u64)rate * period_ns, divisor);
+
+	if (div_l == 0)
+		return -ERANGE;
+
+	div_l -= 1;
+
+	if (div_l > 255)
+		div_l = 255;
+
+	dev_dbg(dev, "clk source: %ld div_h %lld, div_l : %lld\n", rate, div_h,
+		div_l);
+	/* duty_pt = duty_cycle * (PERIOD + 1) / period */
+	duty_pt = div64_u64(duty_ns * (u64)rate,
+			    (u64)NSEC_PER_SEC * (div_l + 1) << div_h);
+	dev_dbg(dev, "duty_cycle = %d, duty_pt = %d\n", duty_ns,
+		duty_pt);
+
+	if (duty_pt == 0) {
+		clk_en = 0;
+	} else {
+		clk_en = 1;
+		if (duty_pt >= (PWM_ASPEED_FIXED_PERIOD + 1))
+			duty_pt = 0;
+		/*
+		 * Fixed DUTY_CYCLE_PERIOD to its max value to get a
+		 * fine-grained resolution for duty_cycle at the expense of a
+		 * coarser period resolution.
+		 */
+		regmap_update_bits(priv->regmap, PWM_ASPEED_DUTY_CYCLE(channel),
+				   PWM_ASPEED_DUTY_CYCLE_PERIOD |
+				       PWM_ASPEED_DUTY_CYCLE_RISING_POINT |
+				       PWM_ASPEED_DUTY_CYCLE_FALLING_POINT,
+				   FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_PERIOD,
+					      PWM_ASPEED_FIXED_PERIOD) |
+				       FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_FALLING_POINT,
+						  duty_pt));
+	}
+
+	regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL(channel),
+			   PWM_ASPEED_CTRL_CLK_DIV_H |
+			       PWM_ASPEED_CTRL_CLK_DIV_L |
+			       PWM_ASPEED_CTRL_CLK_ENABLE,
+			   FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_H, div_h) |
+			       FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_L, div_l) |
+			       FIELD_PREP(PWM_ASPEED_CTRL_CLK_ENABLE, clk_en));
+	return 0;
+}
+
+static int aspeed_pwm_probe(struct udevice *dev)
+{
+	int ret;
+	struct aspeed_pwm_priv *priv = dev_get_priv(dev);
+	struct udevice *parent_dev = dev_get_parent(dev);
+
+	priv->regmap = syscon_node_to_regmap(dev_ofnode(dev->parent));
+	if (IS_ERR(priv->regmap)) {
+		dev_err(dev, "Couldn't get regmap\n");
+		return PTR_ERR(priv->regmap);
+	}
+
+	ret = clk_get_by_index(parent_dev, 0, &priv->clk);
+	if (ret < 0) {
+		dev_err(dev, "get clock failed\n");
+		return ret;
+	}
+
+	ret = reset_get_by_index(parent_dev, 0, &priv->reset);
+	if (ret) {
+		dev_err(dev, "get reset failed\n");
+		return ret;
+	}
+	ret = reset_deassert(&priv->reset);
+	if (ret) {
+		dev_err(dev, "cannot deassert reset control: %pe\n",
+			ERR_PTR(ret));
+		return ret;
+	}
+
+	return 0;
+}
+
+static int aspeed_pwm_remove(struct udevice *dev)
+{
+	struct aspeed_pwm_priv *priv = dev_get_priv(dev);
+
+	reset_assert(&priv->reset);
+
+	return 0;
+}
+
+static const struct pwm_ops aspeed_pwm_ops = {
+	.set_invert	= aspeed_pwm_set_invert,
+	.set_config	= aspeed_pwm_set_config,
+	.set_enable	= aspeed_pwm_set_enable,
+};
+
+static const struct udevice_id aspeed_pwm_ids[] = {
+	{ .compatible = "aspeed,ast2600-pwm" },
+	{ }
+};
+
+U_BOOT_DRIVER(aspeed_pwm) = {
+	.name = "aspeed_pwm",
+	.id = UCLASS_PWM,
+	.of_match = aspeed_pwm_ids,
+	.ops = &aspeed_pwm_ops,
+	.probe = aspeed_pwm_probe,
+	.remove = aspeed_pwm_remove,
+	.priv_auto = sizeof(struct aspeed_pwm_priv),
+};

include/pci.h

@@ -55,130 +55,7 @@
 #define PCI_CLASS_PROG		0x09	/* Reg. Level Programming Interface */
 #define PCI_CLASS_DEVICE	0x0a	/* Device class */
 #define PCI_CLASS_CODE		0x0b	/* Device class code */
-#define  PCI_CLASS_CODE_TOO_OLD	0x00
-#define  PCI_CLASS_CODE_STORAGE 0x01
-#define  PCI_CLASS_CODE_NETWORK 0x02
-#define  PCI_CLASS_CODE_DISPLAY	0x03
-#define  PCI_CLASS_CODE_MULTIMEDIA 0x04
-#define  PCI_CLASS_CODE_MEMORY	0x05
-#define  PCI_CLASS_CODE_BRIDGE	0x06
-#define  PCI_CLASS_CODE_COMM	0x07
-#define  PCI_CLASS_CODE_PERIPHERAL 0x08
-#define  PCI_CLASS_CODE_INPUT	0x09
-#define  PCI_CLASS_CODE_DOCKING	0x0A
-#define  PCI_CLASS_CODE_PROCESSOR 0x0B
-#define  PCI_CLASS_CODE_SERIAL	0x0C
-#define  PCI_CLASS_CODE_WIRELESS 0x0D
-#define  PCI_CLASS_CODE_I2O	0x0E
-#define  PCI_CLASS_CODE_SATELLITE 0x0F
-#define  PCI_CLASS_CODE_CRYPTO	0x10
-#define  PCI_CLASS_CODE_DATA	0x11
-/* Base Class 0x12 - 0xFE is reserved */
-#define  PCI_CLASS_CODE_OTHER	0xFF
-
 #define PCI_CLASS_SUB_CODE	0x0a	/* Device sub-class code */
-#define  PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA	0x00
-#define  PCI_CLASS_SUB_CODE_TOO_OLD_VGA		0x01
-#define  PCI_CLASS_SUB_CODE_STORAGE_SCSI	0x00
-#define  PCI_CLASS_SUB_CODE_STORAGE_IDE		0x01
-#define  PCI_CLASS_SUB_CODE_STORAGE_FLOPPY	0x02
-#define  PCI_CLASS_SUB_CODE_STORAGE_IPIBUS	0x03
-#define  PCI_CLASS_SUB_CODE_STORAGE_RAID	0x04
-#define  PCI_CLASS_SUB_CODE_STORAGE_ATA		0x05
-#define  PCI_CLASS_SUB_CODE_STORAGE_SATA	0x06
-#define  PCI_CLASS_SUB_CODE_STORAGE_SAS		0x07
-#define  PCI_CLASS_SUB_CODE_STORAGE_OTHER	0x80
-#define  PCI_CLASS_SUB_CODE_NETWORK_ETHERNET	0x00
-#define  PCI_CLASS_SUB_CODE_NETWORK_TOKENRING	0x01
-#define  PCI_CLASS_SUB_CODE_NETWORK_FDDI	0x02
-#define  PCI_CLASS_SUB_CODE_NETWORK_ATM		0x03
-#define  PCI_CLASS_SUB_CODE_NETWORK_ISDN	0x04
-#define  PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP	0x05
-#define  PCI_CLASS_SUB_CODE_NETWORK_PICMG	0x06
-#define  PCI_CLASS_SUB_CODE_NETWORK_OTHER	0x80
-#define  PCI_CLASS_SUB_CODE_DISPLAY_VGA		0x00
-#define  PCI_CLASS_SUB_CODE_DISPLAY_XGA		0x01
-#define  PCI_CLASS_SUB_CODE_DISPLAY_3D		0x02
-#define  PCI_CLASS_SUB_CODE_DISPLAY_OTHER	0x80
-#define  PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO	0x00
-#define  PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO	0x01
-#define  PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE	0x02
-#define  PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER	0x80
-#define  PCI_CLASS_SUB_CODE_MEMORY_RAM		0x00
-#define  PCI_CLASS_SUB_CODE_MEMORY_FLASH	0x01
-#define  PCI_CLASS_SUB_CODE_MEMORY_OTHER	0x80
-#define  PCI_CLASS_SUB_CODE_BRIDGE_HOST		0x00
-#define  PCI_CLASS_SUB_CODE_BRIDGE_ISA		0x01
-#define  PCI_CLASS_SUB_CODE_BRIDGE_EISA		0x02
-#define  PCI_CLASS_SUB_CODE_BRIDGE_MCA		0x03
-#define  PCI_CLASS_SUB_CODE_BRIDGE_PCI		0x04
-#define  PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA	0x05
-#define  PCI_CLASS_SUB_CODE_BRIDGE_NUBUS	0x06
-#define  PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS	0x07
-#define  PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY	0x08
-#define  PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI	0x09
-#define  PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND	0x0A
-#define  PCI_CLASS_SUB_CODE_BRIDGE_OTHER	0x80
-#define  PCI_CLASS_SUB_CODE_COMM_SERIAL		0x00
-#define  PCI_CLASS_SUB_CODE_COMM_PARALLEL	0x01
-#define  PCI_CLASS_SUB_CODE_COMM_MULTIPORT	0x02
-#define  PCI_CLASS_SUB_CODE_COMM_MODEM		0x03
-#define  PCI_CLASS_SUB_CODE_COMM_GPIB		0x04
-#define  PCI_CLASS_SUB_CODE_COMM_SMARTCARD	0x05
-#define  PCI_CLASS_SUB_CODE_COMM_OTHER		0x80
-#define  PCI_CLASS_SUB_CODE_PERIPHERAL_PIC	0x00
-#define  PCI_CLASS_SUB_CODE_PERIPHERAL_DMA	0x01
-#define  PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER	0x02
-#define  PCI_CLASS_SUB_CODE_PERIPHERAL_RTC	0x03
-#define  PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG	0x04
-#define  PCI_CLASS_SUB_CODE_PERIPHERAL_SD	0x05
-#define  PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER	0x80
-#define  PCI_CLASS_SUB_CODE_INPUT_KEYBOARD	0x00
-#define  PCI_CLASS_SUB_CODE_INPUT_DIGITIZER	0x01
-#define  PCI_CLASS_SUB_CODE_INPUT_MOUSE		0x02
-#define  PCI_CLASS_SUB_CODE_INPUT_SCANNER	0x03
-#define  PCI_CLASS_SUB_CODE_INPUT_GAMEPORT	0x04
-#define  PCI_CLASS_SUB_CODE_INPUT_OTHER		0x80
-#define  PCI_CLASS_SUB_CODE_DOCKING_GENERIC	0x00
-#define  PCI_CLASS_SUB_CODE_DOCKING_OTHER	0x80
-#define  PCI_CLASS_SUB_CODE_PROCESSOR_386	0x00
-#define  PCI_CLASS_SUB_CODE_PROCESSOR_486	0x01
-#define  PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM	0x02
-#define  PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA	0x10
-#define  PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC	0x20
-#define  PCI_CLASS_SUB_CODE_PROCESSOR_MIPS	0x30
-#define  PCI_CLASS_SUB_CODE_PROCESSOR_COPROC	0x40
-#define  PCI_CLASS_SUB_CODE_SERIAL_1394		0x00
-#define  PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS	0x01
-#define  PCI_CLASS_SUB_CODE_SERIAL_SSA		0x02
-#define  PCI_CLASS_SUB_CODE_SERIAL_USB		0x03
-#define  PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN	0x04
-#define  PCI_CLASS_SUB_CODE_SERIAL_SMBUS	0x05
-#define  PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND	0x06
-#define  PCI_CLASS_SUB_CODE_SERIAL_IPMI		0x07
-#define  PCI_CLASS_SUB_CODE_SERIAL_SERCOS	0x08
-#define  PCI_CLASS_SUB_CODE_SERIAL_CANBUS	0x09
-#define  PCI_CLASS_SUB_CODE_WIRELESS_IRDA	0x00
-#define  PCI_CLASS_SUB_CODE_WIRELESS_IR		0x01
-#define  PCI_CLASS_SUB_CODE_WIRELESS_RF		0x10
-#define  PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH	0x11
-#define  PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND	0x12
-#define  PCI_CLASS_SUB_CODE_WIRELESS_80211A	0x20
-#define  PCI_CLASS_SUB_CODE_WIRELESS_80211B	0x21
-#define  PCI_CLASS_SUB_CODE_WIRELESS_OTHER	0x80
-#define  PCI_CLASS_SUB_CODE_I2O_V1_0		0x00
-#define  PCI_CLASS_SUB_CODE_SATELLITE_TV	0x01
-#define  PCI_CLASS_SUB_CODE_SATELLITE_AUDIO	0x02
-#define  PCI_CLASS_SUB_CODE_SATELLITE_VOICE	0x03
-#define  PCI_CLASS_SUB_CODE_SATELLITE_DATA	0x04
-#define  PCI_CLASS_SUB_CODE_CRYPTO_NETWORK	0x00
-#define  PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10
-#define  PCI_CLASS_SUB_CODE_CRYPTO_OTHER	0x80
-#define  PCI_CLASS_SUB_CODE_DATA_DPIO		0x00
-#define  PCI_CLASS_SUB_CODE_DATA_PERFCNTR	0x01
-#define  PCI_CLASS_SUB_CODE_DATA_COMMSYNC	0x10
-#define  PCI_CLASS_SUB_CODE_DATA_MGMT		0x20
-#define  PCI_CLASS_SUB_CODE_DATA_OTHER		0x80
 
 #define PCI_CACHE_LINE_SIZE	0x0c	/* 8 bits */
 #define PCI_LATENCY_TIMER	0x0d	/* 8 bits */

include/pci_ids.h

@@ -55,6 +55,8 @@
 #define PCI_CLASS_BRIDGE_EISA		0x0602
 #define PCI_CLASS_BRIDGE_MC		0x0603
 #define PCI_CLASS_BRIDGE_PCI		0x0604
+#define PCI_CLASS_BRIDGE_PCI_NORMAL		0x060400
+#define PCI_CLASS_BRIDGE_PCI_SUBTRACTIVE	0x060401
 #define PCI_CLASS_BRIDGE_PCMCIA		0x0605
 #define PCI_CLASS_BRIDGE_NUBUS		0x0606
 #define PCI_CLASS_BRIDGE_CARDBUS	0x0607

include/power/pfuze100_pmic.h

@@ -18,6 +18,11 @@ enum {
 	PFUZE100_REVID		= 0x03,
 	PFUZE100_FABID		= 0x04,
 
+	PFUZE100_MEMA		= 0x1c,
+	PFUZE100_MEMB		= 0x1d,
+	PFUZE100_MEMC		= 0x1e,
+	PFUZE100_MEMD		= 0x1f,
+
 	PFUZE100_SW1ABVOL	= 0x20,
 	PFUZE100_SW1ABSTBY	= 0x21,
 	PFUZE100_SW1ABOFF	= 0x22,