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board: starfive: support Pine64 Star64 board

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Similar to the Milk-V Mars, The Star64 board contains few differences to the
VisionFive 2 boards, so can be part of the same U-boot build.

Signed-off-by: Henry Bell <dmoo_dv@protonmail.com>
Cc: ycliang@andestech.com
Cc: heinrich.schuchardt@canonical.com
Reviewed-by: E Shattow <lucent@gmail.com>
This commit is contained in:
H Bell 2024-05-22 19:12:48 +00:00 • committed by Leo Yu-Chi Liang
parent 684775fec9
commit 7ebf7e77c0
2 changed files with 93 additions and 0 deletions
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89
board/starfive/visionfive2/spl.c
View file

@ -86,6 +86,43 @@ static const struct starfive_vf2_pro starfive_verb[] = {
"tx-internal-delay-ps", "0"}, "tx-internal-delay-ps", "0"},
}; };
static const struct starfive_vf2_pro star64_pine64[] = {
{"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL},
{"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL},
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
"motorcomm,tx-clk-adj-enabled", NULL},
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
"motorcomm,tx-clk-10-inverted", NULL},
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
"motorcomm,tx-clk-100-inverted", NULL},
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
"motorcomm,tx-clk-1000-inverted", NULL},
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
"motorcomm,rx-clk-drv-microamp", "2910"},
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
"motorcomm,rx-data-drv-microamp", "2910"},
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
"rx-internal-delay-ps", "1900"},
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
"tx-internal-delay-ps", "1500"},
{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
"motorcomm,tx-clk-adj-enabled", NULL},
{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
"motorcomm,tx-clk-10-inverted", NULL},
{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
"motorcomm,tx-clk-100-inverted", NULL},
{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
"motorcomm,rx-clk-drv-microamp", "2910"},
{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
"motorcomm,rx-data-drv-microamp", "2910"},
{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
"rx-internal-delay-ps", "0"},
{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
"tx-internal-delay-ps", "300"},
};
void spl_fdt_fixup_mars(void *fdt) void spl_fdt_fixup_mars(void *fdt)
{ {
static const char compat[] = "milkv,mars\0starfive,jh7110"; static const char compat[] = "milkv,mars\0starfive,jh7110";
@ -250,6 +287,56 @@ void spl_fdt_fixup_version_b(void *fdt)
} }
} }
void spl_fdt_fixup_star64(void *fdt)
{
static const char compat[] = "pine64,star64\0starfive,jh7110";
u32 phandle;
u8 i;
int offset;
int ret;
fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat));
fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
"Pine64 Star64");
/* gmac0 */
offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000");
phandle = fdt_get_phandle(fdt, offset);
offset = fdt_path_offset(fdt, "/soc/ethernet@16030000");
fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX);
fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle);
fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
JH7110_AONCLK_GMAC0_RMII_RTX);
/* gmac1 */
offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000");
phandle = fdt_get_phandle(fdt, offset);
offset = fdt_path_offset(fdt, "/soc/ethernet@16040000");
fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX);
fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle);
fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
JH7110_SYSCLK_GMAC1_RMII_RTX);
for (i = 0; i < ARRAY_SIZE(star64_pine64); i++) {
offset = fdt_path_offset(fdt, star64_pine64[i].path);
if (star64_pine64[i].value)
ret = fdt_setprop_u32(fdt, offset, star64_pine64[i].name,
dectoul(star64_pine64[i].value, NULL));
else
ret = fdt_setprop_empty(fdt, offset, star64_pine64[i].name);
if (ret) {
pr_err("%s set prop %s fail.\n", __func__, star64_pine64[i].name);
break;
}
}
}
void spl_perform_fixups(struct spl_image_info *spl_image) void spl_perform_fixups(struct spl_image_info *spl_image)
{ {
u8 version; u8 version;
@ -278,6 +365,8 @@ void spl_perform_fixups(struct spl_image_info *spl_image)
spl_fdt_fixup_version_b(spl_image->fdt_addr); spl_fdt_fixup_version_b(spl_image->fdt_addr);
break; break;
}; };
} else if (!strncmp(product_id, "STAR64", 6)) {
spl_fdt_fixup_star64(spl_image->fdt_addr);
} else { } else {
pr_err("Unknown product %s\n", product_id); pr_err("Unknown product %s\n", product_id);
}; };

4
board/starfive/visionfive2/starfive_visionfive2.c
View file

@ -27,6 +27,8 @@ DECLARE_GLOBAL_DATA_PTR;
"starfive/jh7110-starfive-visionfive-2-v1.2a.dtb" "starfive/jh7110-starfive-visionfive-2-v1.2a.dtb"
#define FDTFILE_VISIONFIVE2_1_3B \ #define FDTFILE_VISIONFIVE2_1_3B \
"starfive/jh7110-starfive-visionfive-2-v1.3b.dtb" "starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"
#define FDTFILE_PINE64_STAR64 \
"starfive/jh7110-pine64-star64.dtb"
/* enable U74-mc hart1~hart4 prefetcher */ /* enable U74-mc hart1~hart4 prefetcher */
static void enable_prefetcher(void) static void enable_prefetcher(void)
@ -87,6 +89,8 @@ static void set_fdtfile(void)
fdtfile = FDTFILE_VISIONFIVE2_1_3B; fdtfile = FDTFILE_VISIONFIVE2_1_3B;
break; break;
} }
} else if (!strncmp(product_id, "STAR64", 6)) {
fdtfile = FDTFILE_PINE64_STAR64;
} else { } else {
log_err("Unknown product\n"); log_err("Unknown product\n");
return; return;