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u-boot-imx-20221024

Browse source 
-------------------
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/13916
 
 - for 2022.01
 - rework Kontron boards (mx6 and mx8)
 - fixes for Toradex
 - fixes (SPI, CAAM, )
 - sync DT with Linux
 - fixes for Gateworks GW7903 and GW7904 PMIC
 - Engicam i.Core MX8M Plus EDIMM2.2
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Merge tag 'u-boot-imx-20221024' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20221024
-------------------

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/13916

- for 2022.01
- rework Kontron boards (mx6 and mx8)
- fixes for Toradex
- fixes (SPI, CAAM, )
- sync DT with Linux
- fixes for Gateworks GW7903 and GW7904 PMIC
- Engicam i.Core MX8M Plus EDIMM2.2
This commit is contained in:
Tom Rini 2022-10-24 10:04:30 -04:00
commit 7d8ab3cd63
170 changed files with 9621 additions and 6450 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
Makefile
View file

@ -1516,7 +1516,7 @@ tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE
SPL: spl/u-boot-spl.bin FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
ifeq ($(CONFIG_ARCH_IMX8M)$(CONFIG_ARCH_IMX8), y)
#ifeq ($(CONFIG_ARCH_IMX8M)$(CONFIG_ARCH_IMX8), y)
ifeq ($(CONFIG_SPL_LOAD_IMX_CONTAINER), y)
u-boot.cnt: u-boot.bin FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
@ -1532,7 +1532,7 @@ flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
endif
endif
endif
#endif
u-boot.uim: u-boot.bin FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@

10
arch/arm/dts/Makefile
View file

@ -889,8 +889,8 @@ dtb-$(CONFIG_MX6UL) += \
imx6ul-phytec-segin-ff-rdk-nand.dtb \
imx6ul-pico-hobbit.dtb \
imx6ul-pico-pi.dtb \
imx6ul-kontron-n631x-s.dtb \
imx6ull-kontron-n641x-s.dtb
imx6ul-kontron-bl.dtb \
imx6ull-kontron-bl.dtb
dtb-$(CONFIG_MX6ULL) += \
imx6ull-14x14-evk.dtb \
@ -949,8 +949,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-evk.dtb \
imx8mm-icore-mx8mm-ctouch2.dtb \
imx8mm-icore-mx8mm-edimm2.2.dtb \
imx8mm-kontron-n801x-s.dtb \
imx8mm-kontron-n801x-s-lvds.dtb \
imx8mm-kontron-bl.dtb \
imx8mm-kontron-bl-osm-s.dtb \
imx8mm-mx8menlo.dtb \
imx8mm-venice.dtb \
imx8mm-venice-gw71xx-0x.dtb \
@ -959,6 +959,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-venice-gw7901.dtb \
imx8mm-venice-gw7902.dtb \
imx8mm-venice-gw7903.dtb \
imx8mm-venice-gw7904.dtb \
imx8mm-verdin-wifi-dev.dtb \
phycore-imx8mm.dtb \
imx8mn-bsh-smm-s2.dtb \
@ -976,6 +977,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-phanbell.dtb \
imx8mp-dhcom-pdk2.dtb \
imx8mp-evk.dtb \
imx8mp-icore-mx8mp-edimm2.2.dtb \
imx8mp-phyboard-pollux-rdk.dtb \
imx8mp-venice.dtb \
imx8mp-venice-gw74xx.dtb \

1
arch/arm/dts/imx23-evk.dts
View file

@ -79,7 +79,6 @@
MX23_PAD_LCD_RESET__GPIO_1_18
MX23_PAD_PWM3__GPIO_1_29
MX23_PAD_PWM4__GPIO_1_30
MX23_PAD_SSP1_DETECT__SSP1_DETECT
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;

8
arch/arm/dts/imx23-pinfunc.h
View file

@ -1,14 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Header providing constants for i.MX23 pinctrl bindings.
*
* Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __DT_BINDINGS_MX23_PINCTRL_H__

7
arch/arm/dts/imx23-u-boot.dtsi
View file

@ -1,14 +1,13 @@
// SPDX-License-Identifier: GPL-2.0+
&gpio0 {
gpio-ranges = <&pinctrl 0 0 32>;
gpio-ranges = <&{/apb@80000000/apbh@80000000/pinctrl@80018000} 0 0 32>;
};
&gpio1 {
gpio-ranges = <&pinctrl 0 32 31>;
gpio-ranges = <&{/apb@80000000/apbh@80000000/pinctrl@80018000} 0 32 31>;
};
&gpio2 {
gpio-ranges = <&pinctrl 0 63 32>;
gpio-ranges = <&{/apb@80000000/apbh@80000000/pinctrl@80018000} 0 63 32>;
};

2
arch/arm/dts/imx23.dtsi
View file

@ -105,7 +105,7 @@
status = "disabled";
};
pinctrl: pinctrl@80018000 {
pinctrl@80018000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx23-pinctrl", "simple-bus";

2
arch/arm/dts/imx28-evk.dts
View file

@ -129,7 +129,7 @@
pinctrl-0 = <&spi2_pins_a>;
status = "okay";
flash: m25p80@0 {
flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "sst,sst25vf016b", "jedec,spi-nor";

170
arch/arm/dts/imx28-lwe.dtsi Normal file
View file

@ -0,0 +1,170 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2021
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
*/
/dts-v1/;
#include "imx28.dtsi"
/ {
aliases {
spi2 = &ssp3;
};
chosen {
bootargs = "root=/dev/mmcblk0p2 rootfstype=ext4 ro rootwait console=ttyAMA0,115200 panic=1";
};
memory@40000000 {
reg = <0x40000000 0x08000000>;
};
reg_3v3: regulator-reg-3v3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_usb_5v: regulator-reg-usb-5v {
compatible = "regulator-fixed";
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_fec_3v3: regulator-reg-fec-3v3 {
compatible = "regulator-fixed";
regulator-name = "fec-phy";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&duart {
pinctrl-names = "default";
pinctrl-0 = <&duart_pins_a>;
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
};
&saif0 {
pinctrl-names = "default";
pinctrl-0 = <&saif0_pins_a>;
#sound-dai-cells = <0>;
assigned-clocks = <&clks 53>;
assigned-clock-rates = <12000000>;
status = "okay";
};
&saif1 {
pinctrl-names = "default";
pinctrl-0 = <&saif1_pins_a>;
fsl,saif-master = <&saif0>;
#sound-dai-cells = <0>;
status = "okay";
};
&spi3_pins_a {
fsl,pinmux-ids = <
MX28_PAD_AUART2_RX__SSP3_D4
MX28_PAD_AUART2_TX__SSP3_D5
MX28_PAD_SSP3_SCK__SSP3_SCK
MX28_PAD_SSP3_MOSI__SSP3_CMD
MX28_PAD_SSP3_MISO__SSP3_D0
MX28_PAD_SSP3_SS0__SSP3_D3
MX28_PAD_AUART2_TX__GPIO_3_9
>;
};
&ssp0 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_8bit_pins_a>;
bus-width = <8>;
vmmc-supply = <&reg_3v3>;
non-removable;
status = "okay";
};
&ssp2 {
compatible = "fsl,imx28-spi";
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins_a>;
status = "okay";
};
&ssp3 {
compatible = "fsl,imx28-spi";
pinctrl-names = "default";
pinctrl-0 = <&spi3_pins_a>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <40000000>;
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0 0x80000>;
read-only;
};
partition@80000 {
label = "env0";
reg = <0x80000 0x10000>;
};
partition@90000 {
label = "env1";
reg = <0x90000 0x10000>;
};
partition@100000 {
label = "kernel";
reg = <0x100000 0x400000>;
};
partition@500000 {
label = "swupdate";
reg = <0x500000 0x800000>;
};
};
};
};
&usb0 {
vbus-supply = <&reg_usb_5v>;
pinctrl-names = "default";
pinctrl-0 = <&usb0_pins_b>, <&usb0_id_pins_a>;
dr_mode = "host";
status = "okay";
};
&usbphy0 {
status = "okay";
};
&usb1 {
vbus-supply = <&reg_usb_5v>;
pinctrl-names = "default";
pinctrl-0 = <&usb1_pins_b>;
dr_mode = "host";
status = "okay";
};
&usbphy1 {
status = "okay";
};

8
arch/arm/dts/imx28-pinfunc.h
View file

@ -1,14 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Header providing constants for i.MX28 pinctrl bindings.
*
* Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __DT_BINDINGS_MX28_PINCTRL_H__

2
arch/arm/dts/imx28-xea-u-boot.dtsi
View file

@ -42,5 +42,7 @@
};
&ssp3 {
num-cs = <2>;
spi-max-frequency = <40000000>;
u-boot,dm-spl;
};

194
arch/arm/dts/imx28-xea.dts
View file

@ -1,143 +1,99 @@
// SPDX-License-Identifier: GPL-2.0+
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2019
* Copyright 2021
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
*
* SPDX-License-Identifier: GPL-2.0+ or X11
*
*/
/dts-v1/;
#include "imx28.dtsi"
#include "imx28-lwe.dtsi"
/ {
model = "Liebherr (LWE) XEA i.MX28 Board";
compatible = "lwe,xea", "fsl,imx28";
aliases {
spi3 = &ssp3;
};
memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x10000000>;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_fec_3v3: regulator-fec-3v3 {
compatible = "regulator-fixed";
regulator-name = "fec-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
};
reg_usb_5v: regulator-usb-5v {
compatible = "regulator-fixed";
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
compatible = "lwn,imx28-xea", "fsl,imx28";
};
&mac0 {
phy-mode = "rmii";
&can0 {
pinctrl-names = "default";
pinctrl-0 = <&mac0_pins_a>;
phy-supply = <&reg_fec_3v3>;
phy-reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
phy-reset-post-delay = <1>;
status = "okay";
fixed-link {
speed = <100>;
full-duplex;
};
};
&ssp0 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_8bit_pins_a>;
bus-width = <8>;
vmmc-supply = <&reg_3p3v>;
non-removable;
pinctrl-0 = <&can1_pins_a>;
status = "okay";
};
&ssp3 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx28-spi";
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&spi3_pins_b>;
pinctrl-0 = <&i2c1_pins_b>;
status = "okay";
spi-max-frequency = <40000000>;
num-cs = <2>;
};
flash0: s25fl256s@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <40000000>;
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a &hog_pins_tiva>;
hog_pins_a: hog@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_GPMI_D00__GPIO_0_0
MX28_PAD_GPMI_D02__GPIO_0_2
MX28_PAD_GPMI_D05__GPIO_0_5
MX28_PAD_GPMI_CE1N__GPIO_0_17
MX28_PAD_GPMI_RDY0__GPIO_0_20
MX28_PAD_GPMI_RDY1__GPIO_0_21
MX28_PAD_GPMI_RDY2__GPIO_0_22
MX28_PAD_GPMI_RDN__GPIO_0_24
MX28_PAD_GPMI_CLE__GPIO_0_27
MX28_PAD_LCD_VSYNC__GPIO_1_28
MX28_PAD_SSP1_SCK__GPIO_2_12
MX28_PAD_SSP1_CMD__GPIO_2_13
MX28_PAD_SSP2_SS1__GPIO_2_20
MX28_PAD_SSP2_SS2__GPIO_2_21
MX28_PAD_LCD_D00__GPIO_1_0
MX28_PAD_LCD_D01__GPIO_1_1
MX28_PAD_LCD_D02__GPIO_1_2
MX28_PAD_LCD_D03__GPIO_1_3
MX28_PAD_LCD_D04__GPIO_1_4
MX28_PAD_LCD_D05__GPIO_1_5
MX28_PAD_LCD_D06__GPIO_1_6
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SPL";
reg = <0x0 0x10000>;
read-only;
};
partition@10000 {
label = "u-boot";
reg = <0x10000 0x70000>;
read-only;
};
partition@80000 {
label = "uboot-env1";
reg = <0x80000 0x10000>;
};
partition@90000 {
label = "uboot-env2";
reg = <0x90000 0x10000>;
};
partition@A0000 {
label = "rescue";
reg = <0xA0000 0xF40000>;
};
partition@FE0000 {
label = "spl-boot-data1";
reg = <0xFE0000 0x10000>;
};
partition@FF0000 {
label = "spl-boot-data2";
reg = <0xFF0000 0x10000>;
};
};
hog_pins_tiva: hog@1 {
reg = <1>;
fsl,pinmux-ids = <
MX28_PAD_GPMI_RDY3__GPIO_0_23
MX28_PAD_GPMI_WRN__GPIO_0_25
>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
hog_pins_coding: hog@2 {
reg = <2>;
fsl,pinmux-ids = <
MX28_PAD_GPMI_D01__GPIO_0_1
MX28_PAD_GPMI_D03__GPIO_0_3
MX28_PAD_GPMI_D04__GPIO_0_4
MX28_PAD_GPMI_D06__GPIO_0_6
MX28_PAD_GPMI_D07__GPIO_0_7
>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
};
&usb0 {
vbus-supply = <&reg_usb_5v>;
status = "okay";
&reg_fec_3v3 {
gpio = <&gpio0 0 0>;
};
&usbphy0 {
status = "okay";
&reg_usb_5v {
gpio = <&gpio0 2 0>;
};
&spi2_pins_a {
fsl,pinmux-ids = <
MX28_PAD_SSP2_SCK__SSP2_SCK
MX28_PAD_SSP2_MOSI__SSP2_CMD
MX28_PAD_SSP2_MISO__SSP2_D0
MX28_PAD_SSP2_SS0__GPIO_2_19
>;
};

20
arch/arm/dts/imx28.dtsi
View file

@ -100,7 +100,7 @@
status = "disabled";
};
gpmi: gpmi-nand@8000c000 {
gpmi: nand-controller@8000c000 {
compatible = "fsl,imx28-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
@ -110,6 +110,8 @@
interrupt-names = "bch";
clocks = <&clks 50>;
clock-names = "gpmi_io";
assigned-clocks = <&clks 13>;
assigned-clock-parents = <&clks 10>;
dmas = <&dma_apbh 4>;
dma-names = "rx-tx";
status = "disabled";
@ -948,6 +950,16 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
usb1_pins_b: usb1@1 {
reg = <1>;
fsl,pinmux-ids = <
MX28_PAD_PWM2__USB1_OVERCURRENT
>;
fsl,drive-strength = <MXS_DRIVE_12mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
usb0_id_pins_a: usb0id@0 {
reg = <0>;
fsl,pinmux-ids = <
@ -998,7 +1010,7 @@
clocks = <&clks 26>;
};
dcp: dcp@80028000 {
dcp: crypto@80028000 {
compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
reg = <0x80028000 0x2000>;
interrupts = <52 53 54>;
@ -1011,7 +1023,7 @@
status = "disabled";
};
ocotp: ocotp@8002c000 {
ocotp: efuse@8002c000 {
compatible = "fsl,imx28-ocotp", "fsl,ocotp";
#address-cells = <1>;
#size-cells = <1>;
@ -1317,7 +1329,7 @@
status = "disabled";
};
etn_switch: switch@800f8000 {
eth_switch: switch@800f8000 {
reg = <0x800f8000 0x8000>;
status = "disabled";
};

24
arch/arm/dts/imx51.dtsi
View file

@ -48,25 +48,25 @@
clocks {
ckil {
compatible = "fsl,imx-ckil", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
ckih2 {
compatible = "fsl,imx-ckih2", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
osc {
compatible = "fsl,imx-osc", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
@ -114,7 +114,7 @@
ports = <&ipu_di0>, <&ipu_di1>;
};
soc {
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
@ -171,14 +171,14 @@
};
};
bus@70000000 { /* AIPS1 */
aips1: bus@70000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x70000000 0x10000000>;
ranges;
spba@70000000 {
spba-bus@70000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -215,6 +215,8 @@
clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
<&clks IMX5_CLK_UART3_PER_GATE>;
clock-names = "ipg", "per";
dmas = <&sdma 43 5 1>, <&sdma 44 5 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -426,6 +428,8 @@
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
<&clks IMX5_CLK_UART1_PER_GATE>;
clock-names = "ipg", "per";
dmas = <&sdma 18 4 1>, <&sdma 19 4 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -436,6 +440,8 @@
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
<&clks IMX5_CLK_UART2_PER_GATE>;
clock-names = "ipg", "per";
dmas = <&sdma 16 4 1>, <&sdma 17 4 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -454,7 +460,7 @@
};
};
bus@80000000 { /* AIPS2 */
aips2: bus@80000000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -467,7 +473,7 @@
};
iim: efuse@83f98000 {
compatible = "fsl,imx51-iim", "fsl,imx27-iim";
compatible = "fsl,imx51-iim", "fsl,imx27-iim", "syscon";
reg = <0x83f98000 0x4000>;
interrupts = <69>;
clocks = <&clks IMX5_CLK_IIM_GATE>;

420
arch/arm/dts/imx53-cx9020.dts
View file

@ -1,195 +1,133 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2016 Beckhoff Automation
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
* Copyright 2017 Beckhoff Automation GmbH & Co. KG
* based on imx53-qsb.dts
*/
/dts-v1/;
#include "imx53.dtsi"
#define MX53_PAD_EIM_D26__UART2_RXD_MUX 0x144 0x48c 0x880 0x2 0x0
#define MX53_PAD_EIM_D27__UART2_TXD_MUX 0x148 0x490 0x000 0x2 0x0
#define MX53_PAD_EIM_D28__UART2_RTS 0x14c 0x494 0x87c 0x2 0x0
#define MX53_PAD_EIM_D29__UART2_CTS 0x150 0x498 0x000 0x2 0x0
/ {
model = "Beckhoff CX9020-0100 i.MX53";
compatible = "fsl,imx53-qsb", "fsl,imx53";
model = "Beckhoff CX9020 Embedded PC";
compatible = "bhf,cx9020", "fsl,imx53";
chosen {
stdout-path = &uart2;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
memory@70000000 {
device_type = "memory";
reg = <0x70000000 0x20000000>,
<0xb0000000 0x20000000>;
};
imx53-qsb {
pinctrl_hog: hoggrp {
fsl,pins = <
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
MX53_PAD_GPIO_8__GPIO1_8 0x80000000
MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
MX53_PAD_GPIO_1__GPIO1_1 0x80000000
MX53_PAD_GPIO_4__GPIO1_4 0x80000000
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
MX53_PAD_GPIO_16__GPIO7_11 0x80000000
display-0 {
#address-cells =<1>;
#size-cells = <0>;
compatible = "fsl,imx-parallel-display";
interface-pix-fmt = "rgb24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp0>;
MX53_PAD_EIM_OE__EMI_WEIM_OE 0x80000000
MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT 0x80000000
MX53_PAD_EIM_LBA__EMI_WEIM_LBA 0x80000000
MX53_PAD_EIM_RW__EMI_WEIM_RW 0x80000000
MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 0x80000000
MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 0x80000000
MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 0x80000000
MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 0x80000000
MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 0x80000000
MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000
MX53_PAD_EIM_A16__EMI_WEIM_A_16 0x80000000
MX53_PAD_EIM_A17__EMI_WEIM_A_17 0x80000000
MX53_PAD_EIM_A18__EMI_WEIM_A_18 0x80000000
MX53_PAD_EIM_A19__EMI_WEIM_A_19 0x80000000
MX53_PAD_EIM_A20__EMI_WEIM_A_20 0x80000000
MX53_PAD_EIM_A21__EMI_WEIM_A_21 0x80000000
MX53_PAD_EIM_A22__EMI_WEIM_A_22 0x80000000
MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0xa4
MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0xa4
MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0xa4
MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0xa4
MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0xa4
MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0xa4
MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0xa4
MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0xa4
MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 0xa4
MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 0xa4
MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 0xa4
MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 0xa4
MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 0xa4
MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 0xa4
MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 0xa4
MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 0xa4
MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 0xa4
MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 0xa4
MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 0xa4
MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 0xa4
MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 0xa4
MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 0xa4
MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 0xa4
MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 0xa4
MX53_PAD_NANDF_CLE__GPIO6_7 0x00000001
MX53_PAD_NANDF_WP_B__GPIO6_9 0x00000001
MX53_PAD_NANDF_ALE__GPIO6_8 0x00000001
port@0 {
reg = <0>;
MX53_PAD_EIM_D23__GPIO3_23 0x80000000
MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec
MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x5
MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
>;
display0_in: endpoint {
remote-endpoint = <&ipu_di0_disp0>;
};
};
pinctrl_fec0: fec0grp {
fsl,pins = <
MX53_PAD_FEC_MDC__FEC_MDC 0x4
MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
>;
};
port@1 {
reg = <1>;
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
>;
};
pinctrl_esdhc2: esdhc2grp {
fsl,pins = <
MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX53_PAD_EIM_D26__UART2_RXD_MUX 0x1e4
MX53_PAD_EIM_D27__UART2_TXD_MUX 0x1e4
MX53_PAD_EIM_D28__UART2_RTS 0x1e4
MX53_PAD_EIM_D29__UART2_CTS 0x1e4
>;
display0_out: endpoint {
remote-endpoint = <&tfp410_in>;
};
};
};
};
&uart2 {
pinctrl-names = "default";
uart-has-rtscts;
fsl,dte-mode;
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
dvi-connector {
compatible = "dvi-connector";
ddc-i2c-bus = <&i2c2>;
digital;
port {
dvi_connector_in: endpoint {
remote-endpoint = <&tfp410_out>;
};
};
};
dvi-converter {
compatible = "ti,tfp410";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tfp410_in: endpoint {
remote-endpoint = <&display0_out>;
};
};
port@1 {
reg = <1>;
tfp410_out: endpoint {
remote-endpoint = <&dvi_connector_in>;
};
};
};
};
leds {
compatible = "gpio-leds";
pwr-r {
gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
pwr-g {
gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
pwr-b {
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
sd1-b {
linux,default-trigger = "mmc0";
gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
};
sd2-b {
linux,default-trigger = "mmc1";
gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
};
};
regulator-3p2v {
compatible = "regulator-fixed";
regulator-name = "3P2V";
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3200000>;
regulator-always-on;
};
reg_usb_vbus: regulator-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&esdhc1 {
@ -210,22 +148,148 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
pinctrl-0 = <&pinctrl_fec0>;
phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&ipu_di0_disp0 {
remote-endpoint = <&display0_in>;
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
fsl,dte-mode;
status = "okay";
fixed-link { /* RMII fixed link to KZ8863 */
speed = <100>;
full-duplex;
};
};
&usbh1 {
vbus-supply = <&reg_usb_vbus>;
phy_type = "utmi";
status = "okay";
};
&usbotg {
dr_mode = "host";
dr_mode = "peripheral";
status = "okay";
};
&vpu {
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX53_PAD_GPIO_0__CCM_CLKO 0x1c4
MX53_PAD_GPIO_16__I2C3_SDA 0x1c4
MX53_PAD_EIM_D22__GPIO3_22 0x1c4
MX53_PAD_EIM_D23__GPIO3_23 0x1e4
MX53_PAD_EIM_D24__GPIO3_24 0x1e4
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
MX53_PAD_GPIO_1__ESDHC1_CD 0x1c4
MX53_PAD_EIM_D17__GPIO3_17 0x1e4
MX53_PAD_GPIO_3__GPIO1_3 0x1c4
>;
};
pinctrl_esdhc2: esdhc2grp {
fsl,pins = <
MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
MX53_PAD_GPIO_4__ESDHC2_CD 0x1e4
MX53_PAD_EIM_D20__GPIO3_20 0x1e4
MX53_PAD_GPIO_8__GPIO1_8 0x1c4
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX53_PAD_FEC_MDC__FEC_MDC 0x4
MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
>;
};
pinctrl_ipu_disp0: ipudisp0grp {
fsl,pins = <
MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x5
MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX53_PAD_EIM_D26__UART2_RXD_MUX 0x1e4
MX53_PAD_EIM_D27__UART2_TXD_MUX 0x1e4
MX53_PAD_EIM_D28__UART2_RTS 0x1e4
MX53_PAD_EIM_D29__UART2_CTS 0x1e4
>;
};
};

2
arch/arm/dts/imx53-kp.dts
View file

@ -10,6 +10,8 @@
#include "imx53.dtsi"
#include "imx53-pinfunc.h"
#define IMX_PAD_SION 0x40000000
/ {
model = "K+P iMX53";
compatible = "kp,imx53-kp", "fsl,imx53";

306
arch/arm/dts/imx53-m53menlo.dts
View file

@ -5,12 +5,30 @@
/dts-v1/;
#include "imx53-m53.dtsi"
#include "imx53-m53menlo-u-boot.dtsi"
/ {
model = "MENLO M53 EMBEDDED DEVICE";
compatible = "menlo,m53menlo", "fsl,imx53";
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&pinctrl_power_button>;
pinctrl-names = "default";
power-button {
label = "Power button";
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
};
};
gpio-poweroff {
compatible = "gpio-poweroff";
pinctrl-0 = <&pinctrl_power_out>;
pinctrl-names = "default";
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@ -31,27 +49,60 @@
eth {
label = "EthLedYe";
gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
linux,default-trigger = "netdev";
};
};
lvds-decoder {
compatible = "ti,ds90cf364a", "lvds-decoder";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds_decoder_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@1 {
reg = <1>;
lvds_decoder_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
panel {
compatible = "edt,etm070080dh6";
compatible = "edt,etm0700g0dh6";
pinctrl-0 = <&pinctrl_display_gpio>;
pinctrl-names = "default";
enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>;
port {
panel_in: endpoint {
remote-endpoint = <&lvds0_out>;
remote-endpoint = <&lvds_decoder_out>;
};
};
};
beeper {
compatible = "gpio-beeper";
pinctrl-0 = <&pinctrl_beeper>;
gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>;
};
reg_usbh1_vbus: regulator-usbh1-vbus {
compatible = "regulator-fixed";
regulator-name = "vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
gpio = <&gpio1 2 0>;
};
};
@ -75,6 +126,25 @@
assigned-clock-rates = <133333334>, <33333334>, <33333334>;
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, <&gpio2 27 GPIO_ACTIVE_LOW>;
status = "okay";
spidev@0 {
compatible = "menlo,m53cpld";
spi-max-frequency = <25000000>;
reg = <0>;
};
spidev@1 {
compatible = "menlo,m53cpld";
spi-max-frequency = <25000000>;
reg = <1>;
};
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
@ -86,19 +156,81 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-handle = <&ethphy0>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 7 GPIO_ACTIVE_LOW>;
status = "okay";
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
&gpio1 {
gpio-line-names =
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "";
};
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
&gpio2 {
gpio-line-names =
"", "", "", "",
"", "", "", "",
"TestPin_SV2_3", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "";
};
&gpio3 {
gpio-line-names =
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"CPLD_JTAG_TDI", "CPLD_JTAG_TMS", "", "",
"", "CPLD_JTAG_TDO", "", "";
};
&gpio5 {
gpio-line-names =
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "CPLD_JTAG_TCK", "KBD_intK",
"CPLD_int", "CPLD_JTAG_internal", "CPLD_D[0]", "CPLD_D[1]",
"CPLD_D[2]", "CPLD_D[3]", "CPLD_D[4]", "CPLD_D[5]",
"CPLD_D[6]", "CPLD_D[7]", "DISP_reset", "KBD_intI";
};
&gpio6 {
gpio-line-names =
"", "", "", "",
"CPLD_reset", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "";
};
&gpio7 {
gpio-line-names =
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "USB-OTG_OverCurrent", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "";
};
&i2c1 {
@ -148,27 +280,37 @@
imx53-m53evk {
hoggrp {
fsl,pins = <
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4
MX53_PAD_EIM_EB3__GPIO2_31 0x1d5
MX53_PAD_PATA_DA_0__GPIO7_6 0x1d5
MX53_PAD_GPIO_19__CCM_CLKO 0x1d5
MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x1d5
MX53_PAD_CSI0_DAT4__GPIO5_22 0x1d5
MX53_PAD_CSI0_DAT5__GPIO5_23 0x1d5
MX53_PAD_CSI0_DAT6__GPIO5_24 0x1d5
MX53_PAD_CSI0_DAT7__GPIO5_25 0x1d5
MX53_PAD_CSI0_DAT8__GPIO5_26 0x1d5
MX53_PAD_CSI0_DAT9__GPIO5_27 0x1d5
MX53_PAD_CSI0_DAT10__GPIO5_28 0x1d5
MX53_PAD_CSI0_DAT11__GPIO5_29 0x1d5
MX53_PAD_CSI0_DAT14__GPIO6_0 0x1d5
MX53_PAD_GPIO_19__CCM_CLKO 0x1e4
MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1e4
MX53_PAD_CSI0_DAT4__GPIO5_22 0x1e4
MX53_PAD_CSI0_DAT5__GPIO5_23 0x1c4
MX53_PAD_CSI0_DAT6__GPIO5_24 0x1e4
MX53_PAD_CSI0_DAT7__GPIO5_25 0x1e4
MX53_PAD_CSI0_DAT8__GPIO5_26 0x1e4
MX53_PAD_CSI0_DAT9__GPIO5_27 0x1c4
MX53_PAD_CSI0_DAT10__GPIO5_28 0x1e4
MX53_PAD_CSI0_DAT11__GPIO5_29 0x1e4
MX53_PAD_PATA_DATA11__GPIO2_11 0x1e4
MX53_PAD_EIM_D24__GPIO3_24 0x1e4
MX53_PAD_EIM_D25__GPIO3_25 0x1e4
MX53_PAD_EIM_D29__GPIO3_29 0x1e4
MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1e4
MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1e4
MX53_PAD_CSI0_DAT18__GPIO6_4 0x1c4
MX53_PAD_PATA_DATA8__GPIO2_8 0x1e4
>;
};
pinctrl_led: ledgrp {
fsl,pins = <
MX53_PAD_CSI0_DAT15__GPIO6_1 0x1d5
MX53_PAD_CSI0_DAT16__GPIO6_2 0x1d5
MX53_PAD_CSI0_DAT15__GPIO6_1 0x1c4
MX53_PAD_CSI0_DAT16__GPIO6_2 0x1c4
>;
};
pinctrl_beeper: beepergrp {
fsl,pins = <
MX53_PAD_CSI0_DAT17__GPIO6_3 0x1c4
>;
};
@ -181,49 +323,66 @@
pinctrl_can2: can2grp {
fsl,pins = <
MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1c4
MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1e4
MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x1c4
>;
};
pinctrl_display_gpio: display-gpiogrp {
fsl,pins = <
MX53_PAD_CSI0_DAT12__GPIO5_30 0x1d5 /* Reset */
MX53_PAD_CSI0_DAT13__GPIO5_31 0x1d5 /* Interrupt */
MX53_PAD_CSI0_DAT12__GPIO5_30 0x1c4 /* Reset */
MX53_PAD_CSI0_MCLK__GPIO5_19 0x1e4 /* Int-K */
MX53_PAD_CSI0_DAT13__GPIO5_31 0x1c4 /* Int-I */
MX53_PAD_CSI0_DAT14__GPIO6_0 0x1c4 /* Power down */
>;
};
pinctrl_edt_ft5x06: edt-ft5x06grp {
fsl,pins = <
MX53_PAD_PATA_DATA9__GPIO2_9 0x1d5 /* Reset */
MX53_PAD_CSI0_DAT19__GPIO6_5 0x1d5 /* Interrupt */
MX53_PAD_PATA_DATA10__GPIO2_10 0x1d5 /* Wake */
MX53_PAD_PATA_DATA9__GPIO2_9 0x1e4 /* Reset */
MX53_PAD_CSI0_DAT19__GPIO6_5 0x1c4 /* Interrupt */
MX53_PAD_PATA_DATA10__GPIO2_10 0x1e4 /* Wake */
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX53_PAD_EIM_CS0__ECSPI2_SCLK 0xe4
MX53_PAD_EIM_OE__ECSPI2_MISO 0xe4
MX53_PAD_EIM_CS1__ECSPI2_MOSI 0xe4
MX53_PAD_EIM_RW__GPIO2_26 0xe4
MX53_PAD_EIM_LBA__GPIO2_27 0xe4
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1e4
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1e4
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1e4
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1e4
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1e4
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1e4
MX53_PAD_GPIO_1__GPIO1_1 0x1c4
MX53_PAD_GPIO_9__GPIO1_9 0x1e4
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX53_PAD_FEC_MDC__FEC_MDC 0x4
MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
MX53_PAD_FEC_MDC__FEC_MDC 0x1e4
MX53_PAD_FEC_MDIO__FEC_MDIO 0x1e4
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x1e4
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x1e4
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x1e4
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x1e4
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x1e4
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x1c4
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x1e4
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x1e4
MX53_PAD_PATA_DA_1__GPIO7_7 0x1e4
MX53_PAD_EIM_EB3__GPIO2_31 0x1e4
>;
};
@ -252,10 +411,24 @@
>;
};
pinctrl_power_button: powerbutgrp {
fsl,pins = <
MX53_PAD_SD2_DATA0__GPIO1_15 0x1e4
>;
};
pinctrl_power_out: poweroutgrp {
fsl,pins = <
MX53_PAD_SD2_DATA2__GPIO1_13 0x1e4
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
MX53_PAD_PATA_IORDY__UART1_RTS 0x1e4
MX53_PAD_PATA_RESET_B__UART1_CTS 0x1e4
>;
};
@ -263,13 +436,25 @@
fsl,pins = <
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
MX53_PAD_PATA_DIOR__UART2_RTS 0x1e4
MX53_PAD_PATA_INTRQ__UART2_CTS 0x1e4
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
>;
};
pinctrl_usb: usbgrp {
fsl,pins = <
MX53_PAD_GPIO_2__GPIO1_2 0x1d5
MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x1d5
MX53_PAD_GPIO_2__GPIO1_2 0x1c4
MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x1c4
MX53_PAD_GPIO_4__GPIO1_4 0x1c4
MX53_PAD_GPIO_18__GPIO7_13 0x1c4
>;
};
};
@ -290,7 +475,7 @@
reg = <2>;
lvds0_out: endpoint {
remote-endpoint = <&panel_in>;
remote-endpoint = <&lvds_decoder_in>;
};
};
};
@ -299,12 +484,21 @@
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
uart-has-rtscts;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
linux,rs485-enabled-at-boot-time;
status = "okay";
};
@ -313,7 +507,7 @@
pinctrl-0 = <&pinctrl_usb>;
vbus-supply = <&reg_usbh1_vbus>;
phy_type = "utmi";
dr_mode = "peripheral";
dr_mode = "host";
status = "okay";
};

11
arch/arm/dts/imx53-pinfunc.h
View file

@ -1,16 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DTS_IMX53_PINFUNC_H
#define __DTS_IMX53_PINFUNC_H
#define IMX_PAD_SION 0x40000000
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
@ -525,6 +520,7 @@
#define MX53_PAD_EIM_D25__UART1_DSR 0x140 0x488 0x000 0x7 0x0
#define MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x144 0x48c 0x000 0x0 0x0
#define MX53_PAD_EIM_D26__GPIO3_26 0x144 0x48c 0x000 0x1 0x0
#define MX53_PAD_EIM_D26__UART2_RXD_MUX 0x144 0x48c 0x880 0x2 0x0
#define MX53_PAD_EIM_D26__UART2_TXD_MUX 0x144 0x48c 0x000 0x2 0x0
#define MX53_PAD_EIM_D26__FIRI_RXD 0x144 0x48c 0x80c 0x3 0x0
#define MX53_PAD_EIM_D26__IPU_CSI0_D_1 0x144 0x48c 0x000 0x4 0x0
@ -534,6 +530,7 @@
#define MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x148 0x490 0x000 0x0 0x0
#define MX53_PAD_EIM_D27__GPIO3_27 0x148 0x490 0x000 0x1 0x0
#define MX53_PAD_EIM_D27__UART2_RXD_MUX 0x148 0x490 0x880 0x2 0x1
#define MX53_PAD_EIM_D27__UART2_TXD_MUX 0x148 0x490 0x000 0x2 0x0
#define MX53_PAD_EIM_D27__FIRI_TXD 0x148 0x490 0x000 0x3 0x0
#define MX53_PAD_EIM_D27__IPU_CSI0_D_0 0x148 0x490 0x000 0x4 0x0
#define MX53_PAD_EIM_D27__IPU_DI1_PIN13 0x148 0x490 0x000 0x5 0x0
@ -542,6 +539,7 @@
#define MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x14c 0x494 0x000 0x0 0x0
#define MX53_PAD_EIM_D28__GPIO3_28 0x14c 0x494 0x000 0x1 0x0
#define MX53_PAD_EIM_D28__UART2_CTS 0x14c 0x494 0x000 0x2 0x0
#define MX53_PAD_EIM_D28__UART2_RTS 0x14c 0x494 0x87c 0x2 0x0
#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO 0x14c 0x494 0x82c 0x3 0x1
#define MX53_PAD_EIM_D28__CSPI_MOSI 0x14c 0x494 0x788 0x4 0x1
#define MX53_PAD_EIM_D28__I2C1_SDA 0x14c 0x494 0x818 0x5 0x1
@ -549,6 +547,7 @@
#define MX53_PAD_EIM_D28__IPU_DI0_PIN13 0x14c 0x494 0x000 0x7 0x0
#define MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x150 0x498 0x000 0x0 0x0
#define MX53_PAD_EIM_D29__GPIO3_29 0x150 0x498 0x000 0x1 0x0
#define MX53_PAD_EIM_D29__UART2_CTS 0x150 0x498 0x000 0x2 0x0
#define MX53_PAD_EIM_D29__UART2_RTS 0x150 0x498 0x87c 0x2 0x1
#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS 0x150 0x498 0x000 0x3 0x0
#define MX53_PAD_EIM_D29__CSPI_SS0 0x150 0x498 0x78c 0x4 0x2

87
arch/arm/dts/imx53-ppd.dts
View file

@ -1,4 +1,3 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 General Electric Company
*
@ -71,6 +70,12 @@
clock-frequency = <11289600>;
};
achc_24M: achc-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
sgtlsound: sound {
compatible = "fsl,imx53-cpuvo-sgtl5000",
"fsl,imx-audio-sgtl5000";
@ -177,15 +182,42 @@
power-supply = <&reg_3v3_lcd>;
};
leds {
led-controller-1 {
compatible = "pwm-leds";
alarm-brightness {
led-1 {
label = "alarm-brightness";
pwms = <&pwm1 0 100000>;
max-brightness = <255>;
};
};
led-controller-2 {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_alarmled_pins>;
led-2 {
label = "alarm:red";
gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
};
led-3 {
label = "alarm:yellow";
gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>;
};
led-4 {
label = "alarm:blue";
gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
};
led-5 {
label = "alarm:silenced";
gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>;
};
};
gpio-poweroff {
compatible = "gpio-poweroff";
gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
@ -288,16 +320,13 @@
&gpio4 12 GPIO_ACTIVE_LOW>;
status = "okay";
spidev0: spi@0 {
compatible = "ge,achc";
reg = <0>;
spi-max-frequency = <1000000>;
};
spidev1: spi@1 {
compatible = "ge,achc";
reg = <1>;
spi-max-frequency = <1000000>;
spidev0: spi@1 {
compatible = "ge,achc", "nxp,kinetis-k20";
reg = <1>, <0>;
vdd-supply = <&reg_3v3>;
vdda-supply = <&reg_3v3>;
clocks = <&achc_24M>;
reset-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
};
gpioxra0: gpio@2 {
@ -439,7 +468,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc3>;
bus-width = <8>;
non-removable;
status = "okay";
};
@ -489,7 +517,7 @@
reg = <1>;
rtc@30 {
compatible = "sii,s35392a-rtc";
compatible = "sii,s35390a";
reg = <0x30>;
};
@ -565,7 +593,7 @@
touchscreen@4b {
compatible = "atmel,maxtouch";
reset-gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
reset-gpio = <&gpio5 19 GPIO_ACTIVE_LOW>;
reg = <0x4b>;
interrupt-parent = <&gpio5>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
@ -600,12 +628,14 @@
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm2 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
@ -624,6 +654,7 @@
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
fsl,dma-info = <24 20>;
status = "okay";
};
@ -643,6 +674,7 @@
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
fsl,dma-info = <4096 4>;
status = "okay";
};
@ -911,18 +943,10 @@
MX53_PAD_NANDF_CS3__GPIO6_16 0x0
/* POWER_AND_BOOT_STATUS_INDICATOR */
MX53_PAD_PATA_INTRQ__GPIO7_2 0x1e4
/* ACTIVATE_ALARM_LIGHT_RED */
MX53_PAD_PATA_DIOR__GPIO7_3 0x0
/* ACTIVATE_ALARM_LIGHT_YELLOW */
MX53_PAD_PATA_DA_1__GPIO7_7 0x0
/* ACTIVATE_ALARM_LIGHT_CYAN */
MX53_PAD_PATA_DA_2__GPIO7_8 0x0
/* RUNNING_ON_BATTERY_INDICATOR_GREEN */
MX53_PAD_GPIO_16__GPIO7_11 0x0
/* BATTERY_STATUS_INDICATOR_AMBER */
MX53_PAD_GPIO_17__GPIO7_12 0x0
/* AUDIO_ALARMS_SILENCED_INDICATOR */
MX53_PAD_GPIO_18__GPIO7_13 0x0
>;
};
@ -1082,6 +1106,17 @@
MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 0x180
>;
};
};
#include "imx53-ppd-uboot.dtsi"
pinctrl_alarmled_pins: qmx6alarmledgrp {
fsl,pins = <
/* ACTIVATE_ALARM_LIGHT_RED */
MX53_PAD_PATA_DIOR__GPIO7_3 0x0
/* ACTIVATE_ALARM_LIGHT_YELLOW */
MX53_PAD_PATA_DA_1__GPIO7_7 0x0
/* ACTIVATE_ALARM_LIGHT_CYAN */
MX53_PAD_PATA_DA_2__GPIO7_8 0x0
/* AUDIO_ALARMS_SILENCED_INDICATOR */
MX53_PAD_GPIO_18__GPIO7_13 0x0
>;
};
};

1
arch/arm/dts/imx53-usbarmory.dts
View file

@ -91,7 +91,6 @@
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
broken-cd;
status = "okay";
};

39
arch/arm/dts/imx53.dtsi
View file

@ -86,25 +86,25 @@
clocks {
ckil {
compatible = "fsl,imx-ckil", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <22579200>;
};
ckih2 {
compatible = "fsl,imx-ckih2", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
osc {
compatible = "fsl,imx-osc", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
@ -132,7 +132,7 @@
status = "okay";
};
soc {
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
@ -222,21 +222,21 @@
clock-names = "core_clk", "mem_iface_clk";
};
bus@50000000 { /* AIPS1 */
aips1: bus@50000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x50000000 0x10000000>;
ranges;
spba@50000000 {
spba-bus@50000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x50000000 0x40000>;
ranges;
esdhc1: esdhc@50004000 {
esdhc1: mmc@50004000 {
compatible = "fsl,imx53-esdhc";
reg = <0x50004000 0x4000>;
interrupts = <1>;
@ -248,7 +248,7 @@
status = "disabled";
};
esdhc2: esdhc@50008000 {
esdhc2: mmc@50008000 {
compatible = "fsl,imx53-esdhc";
reg = <0x50008000 0x4000>;
interrupts = <2>;
@ -301,7 +301,7 @@
status = "disabled";
};
esdhc3: esdhc@50020000 {
esdhc3: mmc@50020000 {
compatible = "fsl,imx53-esdhc";
reg = <0x50020000 0x4000>;
interrupts = <3>;
@ -313,7 +313,7 @@
status = "disabled";
};
esdhc4: esdhc@50024000 {
esdhc4: mmc@50024000 {
compatible = "fsl,imx53-esdhc";
reg = <0x50024000 0x4000>;
interrupts = <4>;
@ -427,14 +427,14 @@
status = "disabled";
};
wdog1: wdog@53f98000 {
wdog1: watchdog@53f98000 {
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
reg = <0x53f98000 0x4000>;
interrupts = <58>;
clocks = <&clks IMX5_CLK_DUMMY>;
};
wdog2: wdog@53f9c000 {
wdog2: watchdog@53f9c000 {
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
reg = <0x53f9c000 0x4000>;
interrupts = <59>;
@ -525,7 +525,7 @@
};
pwm1: pwm@53fb4000 {
#pwm-cells = <2>;
#pwm-cells = <3>;
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
reg = <0x53fb4000 0x4000>;
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
@ -535,7 +535,7 @@
};
pwm2: pwm@53fb8000 {
#pwm-cells = <2>;
#pwm-cells = <3>;
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
reg = <0x53fb8000 0x4000>;
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
@ -588,9 +588,10 @@
status = "disabled";
};
src: src@53fd0000 {
src: reset-controller@53fd0000 {
compatible = "fsl,imx53-src", "fsl,imx51-src";
reg = <0x53fd0000 0x4000>;
interrupts = <75>;
#reset-cells = <1>;
};
@ -654,7 +655,7 @@
};
};
bus@60000000 { /* AIPS2 */
aips2: bus@60000000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -666,8 +667,8 @@
reg = <0x63f00000 0x60>;
};
iim: iim@63f98000 {
compatible = "fsl,imx53-iim", "fsl,imx27-iim";
iim: efuse@63f98000 {
compatible = "fsl,imx53-iim", "fsl,imx27-iim", "syscon";
reg = <0x63f98000 0x4000>;
interrupts = <69>;
clocks = <&clks IMX5_CLK_IIM_GATE>;

11
arch/arm/dts/imx6q-sabrelite.dts
View file

@ -1,8 +1,9 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2013-2019 Boundary Devices, Inc.
// Copyright 2012 Freescale Semiconductor, Inc.
// Copyright 2011 Linaro Ltd.
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
*/
/dts-v1/;
#include "imx6q.dtsi"

11
arch/arm/dts/imx6qdl-sabrelite.dtsi
View file

@ -1,8 +1,9 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2013-2019 Boundary Devices, Inc.
// Copyright 2012 Freescale Semiconductor, Inc.
// Copyright 2011 Linaro Ltd.
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
*/
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/gpio/gpio.h>

7
arch/arm/dts/imx6qp-sabreauto.dts
View file

@ -47,7 +47,12 @@
};
&pcie {
status = "disabled";
reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>;
status = "okay";
};
&sata {
status = "okay";
};
&vgen3_reg {

12
arch/arm/dts/imx6qp-sabresd.dts
View file

@ -50,6 +50,14 @@
};
};
&pcie {
status = "disabled";
&vgen3_reg {
regulator-always-on;
};
&pcie {
status = "okay";
};
&sata {
status = "okay";
};

3
arch/arm/dts/imx6qp.dtsi
View file

@ -77,7 +77,6 @@
};
&fec {
/delete-property/interrupts-extended;
interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
<0 119 IRQ_TYPE_LEVEL_HIGH>;
};
@ -111,5 +110,5 @@
};
&pcie {
compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
compatible = "fsl,imx6qp-pcie";
};

181
arch/arm/dts/imx6sl-evk.dts
View file

@ -1,10 +1,6 @@
/*
* Copyright (C) 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
// SPDX-License-Identifier: GPL-2.0
//
//Copyright (C) 2013 Freescale Semiconductor, Inc.
/dts-v1/;
@ -16,11 +12,16 @@
model = "Freescale i.MX6 SoloLite EVK Board";
compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
memory {
chosen {
stdout-path = &uart1;
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};
backlight {
backlight_display: backlight_display {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@ -39,62 +40,62 @@
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&swbst_reg>;
};
reg_usb_otg1_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 0 0>;
enable-active-high;
vin-supply = <&swbst_reg>;
};
reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&swbst_reg>;
};
reg_usb_otg2_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "usb_otg2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 2 0>;
enable-active-high;
vin-supply = <&swbst_reg>;
};
reg_aud3v: regulator-aud3v {
compatible = "regulator-fixed";
regulator-name = "wm8962-supply-3v15";
regulator-min-microvolt = <3150000>;
regulator-max-microvolt = <3150000>;
regulator-boot-on;
};
reg_aud3v: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "wm8962-supply-3v15";
regulator-min-microvolt = <3150000>;
regulator-max-microvolt = <3150000>;
regulator-boot-on;
};
reg_aud4v: regulator-aud4v {
compatible = "regulator-fixed";
regulator-name = "wm8962-supply-4v2";
regulator-min-microvolt = <4325000>;
regulator-max-microvolt = <4325000>;
regulator-boot-on;
};
reg_aud4v: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "wm8962-supply-4v2";
regulator-min-microvolt = <4325000>;
regulator-max-microvolt = <4325000>;
regulator-boot-on;
};
reg_lcd_3v3: regulator-lcd-3v3 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_lcd_3v3>;
regulator-name = "lcd-3v3";
gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_lcd_3v3: regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "lcd-3v3";
gpio = <&gpio4 3 0>;
enable-active-high;
};
reg_lcd_5v: regulator-lcd-5v {
compatible = "regulator-fixed";
regulator-name = "lcd-5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
sound {
compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hp>;
model = "wm8962-audio";
ssi-controller = <&ssi2>;
audio-codec = <&codec>;
@ -107,6 +108,20 @@
"IN3R", "AMIC";
mux-int-port = <2>;
mux-ext-port = <3>;
hp-det-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>;
};
panel {
compatible = "sii,43wvf1g";
backlight = <&backlight_display>;
dvdd-supply = <&reg_lcd_3v3>;
avdd-supply = <&reg_lcd_5v>;
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
};
};
};
};
@ -117,12 +132,12 @@
};
&ecspi1 {
cs-gpios = <&gpio4 11 0>;
cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
flash: m25p80@0 {
flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p32", "jedec,spi-nor";
@ -145,7 +160,7 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pfuze100@08 {
pmic: pfuze100@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
@ -190,6 +205,7 @@
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
swbst_reg: swbst {
@ -330,6 +346,12 @@
>;
};
pinctrl_hp: hpgrp {
fsl,pins = <
MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
@ -401,6 +423,12 @@
>;
};
pinctrl_reg_lcd_3v3: reglcd3v3grp {
fsl,pins = <
MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x17059
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
@ -546,41 +574,30 @@
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd>;
lcd-supply = <&reg_lcd_3v3>;
display = <&display0>;
status = "okay";
display0: display0 {
bits-per-pixel = <32>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <33500000>;
hactive = <800>;
vactive = <480>;
hback-porch = <89>;
hfront-porch = <164>;
vback-porch = <23>;
vfront-porch = <10>;
hsync-len = <10>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
port {
display_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&reg_vdd1p1 {
vin-supply = <&sw2_reg>;
};
&reg_vdd2p5 {
vin-supply = <&sw2_reg>;
};
&snvs_poweroff {
status = "okay";
};

6
arch/arm/dts/imx6sl-pinfunc.h
View file

@ -1,10 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DTS_IMX6SL_PINFUNC_H

364
arch/arm/dts/imx6sl.dtsi
View file

@ -1,11 +1,6 @@
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2013 Freescale Semiconductor, Inc.
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6sl-pinfunc.h"
@ -18,10 +13,8 @@
* The decompressor and also some bootloaders rely on a
* pre-existing /chosen node to be available to insert the
* command line and merge other ATAGS info.
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
memory { device_type = "memory"; reg = <0 0>; };
aliases {
ethernet0 = &fec;
@ -30,6 +23,13 @@
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
mmc2 = &usdhc3;
mmc3 = &usdhc4;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
@ -39,6 +39,9 @@
spi1 = &ecspi2;
spi2 = &ecspi3;
spi3 = &ecspi4;
usb0 = &usbotg1;
usb1 = &usbotg2;
usb2 = &usbh;
usbphy0 = &usbphy1;
usbphy1 = &usbphy2;
};
@ -47,24 +50,23 @@
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x0>;
next-level-cache = <&L2>;
operating-points = <
operating-points =
/* kHz uV */
996000 1275000
792000 1175000
396000 975000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
996000 1225000
792000 1175000
396000 1175000
>;
<996000 1275000>,
<792000 1175000>,
<396000 975000>;
fsl,soc-operating-points =
/* ARM kHz SOC-PU uV */
<996000 1225000>,
<792000 1175000>,
<396000 1175000>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
<&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
<&clks IMX6SL_CLK_PLL1_SYS>;
@ -73,22 +75,12 @@
arm-supply = <&reg_arm>;
pu-supply = <&reg_pu>;
soc-supply = <&reg_soc>;
nvmem-cells = <&cpu_speed_grade>;
nvmem-cell-names = "speed_grade";
};
};
intc: interrupt-controller@00a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00a01000 0x1000>,
<0x00a00100 0x100>;
interrupt-parent = <&intc>;
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
ckil {
compatible = "fixed-clock";
#clock-cells = <0>;
@ -102,6 +94,17 @@
};
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupt-parent = <&gpc>;
interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
};
usbphynop1: usbphynop1 {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
@ -109,13 +112,22 @@
interrupt-parent = <&gpc>;
ranges;
ocram: sram@00900000 {
ocram: sram@900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x20000>;
clocks = <&clks IMX6SL_CLK_OCRAM>;
};
L2: l2-cache@00a02000 {
intc: interrupt-controller@a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00a01000 0x1000>,
<0x00a00100 0x100>;
interrupt-parent = <&intc>;
};
L2: cache-controller@a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
@ -125,26 +137,21 @@
arm,data-latency = <4 2 3>;
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
};
aips1: bus@02000000 {
aips1: bus@2000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02000000 0x100000>;
ranges;
spba: spba-bus@02000000 {
spba: spba-bus@2000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02000000 0x40000>;
ranges;
spdif: spdif@02004000 {
spdif: spdif@2004000 {
compatible = "fsl,imx6sl-spdif",
"fsl,imx35-spdif";
reg = <0x02004000 0x4000>;
@ -165,7 +172,7 @@
status = "disabled";
};
ecspi1: ecspi@02008000 {
ecspi1: spi@2008000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
@ -177,7 +184,7 @@
status = "disabled";
};
ecspi2: ecspi@0200c000 {
ecspi2: spi@200c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
@ -189,7 +196,7 @@
status = "disabled";
};
ecspi3: ecspi@02010000 {
ecspi3: spi@2010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
@ -201,7 +208,7 @@
status = "disabled";
};
ecspi4: ecspi@02014000 {
ecspi4: spi@2014000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
@ -213,9 +220,9 @@
status = "disabled";
};
uart5: serial@02018000 {
uart5: serial@2018000 {
compatible = "fsl,imx6sl-uart",
"fsl,imx6q-uart", "fsl,imx21-uart";
"fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02018000 0x4000>;
interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_UART>,
@ -226,9 +233,9 @@
status = "disabled";
};
uart1: serial@02020000 {
uart1: serial@2020000 {
compatible = "fsl,imx6sl-uart",
"fsl,imx6q-uart", "fsl,imx21-uart";
"fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_UART>,
@ -239,9 +246,9 @@
status = "disabled";
};
uart2: serial@02024000 {
uart2: serial@2024000 {
compatible = "fsl,imx6sl-uart",
"fsl,imx6q-uart", "fsl,imx21-uart";
"fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02024000 0x4000>;
interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_UART>,
@ -252,7 +259,7 @@
status = "disabled";
};
ssi1: ssi@02028000 {
ssi1: ssi@2028000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx6sl-ssi",
"fsl,imx51-ssi";
@ -268,7 +275,7 @@
status = "disabled";
};
ssi2: ssi@0202c000 {
ssi2: ssi@202c000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx6sl-ssi",
"fsl,imx51-ssi";
@ -284,7 +291,7 @@
status = "disabled";
};
ssi3: ssi@02030000 {
ssi3: ssi@2030000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx6sl-ssi",
"fsl,imx51-ssi";
@ -300,9 +307,9 @@
status = "disabled";
};
uart3: serial@02034000 {
uart3: serial@2034000 {
compatible = "fsl,imx6sl-uart",
"fsl,imx6q-uart", "fsl,imx21-uart";
"fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02034000 0x4000>;
interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_UART>,
@ -313,9 +320,9 @@
status = "disabled";
};
uart4: serial@02038000 {
uart4: serial@2038000 {
compatible = "fsl,imx6sl-uart",
"fsl,imx6q-uart", "fsl,imx21-uart";
"fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02038000 0x4000>;
interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_UART>,
@ -327,47 +334,47 @@
};
};
pwm1: pwm@02080000 {
#pwm-cells = <2>;
pwm1: pwm@2080000 {
#pwm-cells = <3>;
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
reg = <0x02080000 0x4000>;
interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_PWM1>,
clocks = <&clks IMX6SL_CLK_PERCLK>,
<&clks IMX6SL_CLK_PWM1>;
clock-names = "ipg", "per";
};
pwm2: pwm@02084000 {
#pwm-cells = <2>;
pwm2: pwm@2084000 {
#pwm-cells = <3>;
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
reg = <0x02084000 0x4000>;
interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_PWM2>,
clocks = <&clks IMX6SL_CLK_PERCLK>,
<&clks IMX6SL_CLK_PWM2>;
clock-names = "ipg", "per";
};
pwm3: pwm@02088000 {
#pwm-cells = <2>;
pwm3: pwm@2088000 {
#pwm-cells = <3>;
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
reg = <0x02088000 0x4000>;
interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_PWM3>,
clocks = <&clks IMX6SL_CLK_PERCLK>,
<&clks IMX6SL_CLK_PWM3>;
clock-names = "ipg", "per";
};
pwm4: pwm@0208c000 {
#pwm-cells = <2>;
pwm4: pwm@208c000 {
#pwm-cells = <3>;
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
reg = <0x0208c000 0x4000>;
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_PWM4>,
clocks = <&clks IMX6SL_CLK_PERCLK>,
<&clks IMX6SL_CLK_PWM4>;
clock-names = "ipg", "per";
};
gpt: gpt@02098000 {
gpt: timer@2098000 {
compatible = "fsl,imx6sl-gpt";
reg = <0x02098000 0x4000>;
interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
@ -376,7 +383,7 @@
clock-names = "ipg", "per";
};
gpio1: gpio@0209c000 {
gpio1: gpio@209c000 {
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
reg = <0x0209c000 0x4000>;
interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
@ -393,7 +400,7 @@
<&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
};
gpio2: gpio@020a0000 {
gpio2: gpio@20a0000 {
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
reg = <0x020a0000 0x4000>;
interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
@ -411,7 +418,7 @@
<&iomuxc 23 125 7>, <&iomuxc 30 110 2>;
};
gpio3: gpio@020a4000 {
gpio3: gpio@20a4000 {
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
reg = <0x020a4000 0x4000>;
interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
@ -430,7 +437,7 @@
<&iomuxc 31 102 1>;
};
gpio4: gpio@020a8000 {
gpio4: gpio@20a8000 {
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
reg = <0x020a8000 0x4000>;
interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
@ -456,7 +463,7 @@
<&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
};
gpio5: gpio@020ac000 {
gpio5: gpio@20ac000 {
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
reg = <0x020ac000 0x4000>;
interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
@ -478,30 +485,30 @@
<&iomuxc 21 161 1>;
};
kpp: kpp@020b8000 {
kpp: keypad@20b8000 {
compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
reg = <0x020b8000 0x4000>;
interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_DUMMY>;
clocks = <&clks IMX6SL_CLK_IPG>;
status = "disabled";
};
wdog1: wdog@020bc000 {
wdog1: watchdog@20bc000 {
compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
reg = <0x020bc000 0x4000>;
interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_DUMMY>;
clocks = <&clks IMX6SL_CLK_IPG>;
};
wdog2: wdog@020c0000 {
wdog2: watchdog@20c0000 {
compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
reg = <0x020c0000 0x4000>;
interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_DUMMY>;
clocks = <&clks IMX6SL_CLK_IPG>;
status = "disabled";
};
clks: ccm@020c4000 {
clks: clock-controller@20c4000 {
compatible = "fsl,imx6sl-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
@ -509,20 +516,20 @@
#clock-cells = <1>;
};
anatop: anatop@020c8000 {
anatop: anatop@20c8000 {
compatible = "fsl,imx6sl-anatop",
"fsl,imx6q-anatop",
"syscon", "simple-bus";
"syscon", "simple-mfd";
reg = <0x020c8000 0x1000>;
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
<0 54 IRQ_TYPE_LEVEL_HIGH>,
<0 127 IRQ_TYPE_LEVEL_HIGH>;
regulator-1p1 {
reg_vdd1p1: regulator-1p1 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p1";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1375000>;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
anatop-reg-offset = <0x110>;
anatop-vol-bit-shift = <8>;
@ -530,9 +537,10 @@
anatop-min-bit-val = <4>;
anatop-min-voltage = <800000>;
anatop-max-voltage = <1375000>;
anatop-enable-bit = <0>;
};
regulator-3p0 {
reg_vdd3p0: regulator-3p0 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2800000>;
@ -544,13 +552,14 @@
anatop-min-bit-val = <0>;
anatop-min-voltage = <2625000>;
anatop-max-voltage = <3400000>;
anatop-enable-bit = <0>;
};
regulator-2p5 {
reg_vdd2p5: regulator-2p5 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd2p5";
regulator-min-microvolt = <2100000>;
regulator-max-microvolt = <2850000>;
regulator-min-microvolt = <2250000>;
regulator-max-microvolt = <2750000>;
regulator-always-on;
anatop-reg-offset = <0x130>;
anatop-vol-bit-shift = <8>;
@ -558,6 +567,7 @@
anatop-min-bit-val = <0>;
anatop-min-voltage = <2100000>;
anatop-max-voltage = <2850000>;
anatop-enable-bit = <0>;
};
reg_arm: regulator-vddcore {
@ -582,7 +592,6 @@
regulator-name = "vddpu";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <9>;
anatop-vol-bit-width = <5>;
@ -610,17 +619,19 @@
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
tempmon: tempmon {
compatible = "fsl,imx6q-tempmon";
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gpc>;
fsl,tempmon = <&anatop>;
nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
};
};
tempmon: tempmon {
compatible = "fsl,imx6q-tempmon";
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
fsl,tempmon = <&anatop>;
fsl,tempmon-data = <&ocotp>;
clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
};
usbphy1: usbphy@020c9000 {
usbphy1: usbphy@20c9000 {
compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
reg = <0x020c9000 0x1000>;
interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
@ -628,7 +639,7 @@
fsl,anatop = <&anatop>;
};
usbphy2: usbphy@020ca000 {
usbphy2: usbphy@20ca000 {
compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
reg = <0x020ca000 0x1000>;
interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
@ -636,7 +647,7 @@
fsl,anatop = <&anatop>;
};
snvs: snvs@020cc000 {
snvs: snvs@20cc000 {
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
reg = <0x020cc000 0x4000>;
@ -652,22 +663,23 @@
compatible = "syscon-poweroff";
regmap = <&snvs>;
offset = <0x38>;
value = <0x60>;
mask = <0x60>;
status = "disabled";
};
};
epit1: epit@020d0000 {
epit1: epit@20d0000 {
reg = <0x020d0000 0x4000>;
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
};
epit2: epit@020d4000 {
epit2: epit@20d4000 {
reg = <0x020d4000 0x4000>;
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
};
src: src@020d8000 {
src: reset-controller@20d8000 {
compatible = "fsl,imx6sl-src", "fsl,imx51-src";
reg = <0x020d8000 0x4000>;
interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
@ -675,63 +687,89 @@
#reset-cells = <1>;
};
gpc: gpc@020dc000 {
gpc: gpc@20dc000 {
compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
reg = <0x020dc000 0x4000>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
pu-supply = <&reg_pu>;
clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
<&clks IMX6SL_CLK_GPU2D_PODF>;
#power-domain-cells = <1>;
clocks = <&clks IMX6SL_CLK_IPG>;
clock-names = "ipg";
pgc {
#address-cells = <1>;
#size-cells = <0>;
power-domain@0 {
reg = <0>;
#power-domain-cells = <0>;
};
pd_pu: power-domain@1 {
reg = <1>;
#power-domain-cells = <0>;
power-supply = <&reg_pu>;
clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
<&clks IMX6SL_CLK_GPU2D_PODF>;
};
pd_disp: power-domain@2 {
reg = <2>;
#power-domain-cells = <0>;
clocks = <&clks IMX6SL_CLK_LCDIF_AXI>,
<&clks IMX6SL_CLK_LCDIF_PIX>,
<&clks IMX6SL_CLK_EPDC_AXI>,
<&clks IMX6SL_CLK_EPDC_PIX>,
<&clks IMX6SL_CLK_PXP_AXI>;
};
};
};
gpr: iomuxc-gpr@020e0000 {
gpr: iomuxc-gpr@20e0000 {
compatible = "fsl,imx6sl-iomuxc-gpr",
"fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x020e0000 0x38>;
};
iomuxc: iomuxc@020e0000 {
iomuxc: pinctrl@20e0000 {
compatible = "fsl,imx6sl-iomuxc";
reg = <0x020e0000 0x4000>;
};
csi: csi@020e4000 {
csi: csi@20e4000 {
reg = <0x020e4000 0x4000>;
interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
};
spdc: spdc@020e8000 {
spdc: spdc@20e8000 {
reg = <0x020e8000 0x4000>;
interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
};
sdma: sdma@020ec000 {
sdma: sdma@20ec000 {
compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
reg = <0x020ec000 0x4000>;
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_SDMA>,
<&clks IMX6SL_CLK_SDMA>;
<&clks IMX6SL_CLK_AHB>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
/* imx6sl reuses imx6q sdma firmware */
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
};
pxp: pxp@020f0000 {
pxp: pxp@20f0000 {
reg = <0x020f0000 0x4000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
};
epdc: epdc@020f4000 {
epdc: epdc@20f4000 {
reg = <0x020f4000 0x4000>;
interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
};
lcdif: lcdif@020f8000 {
lcdif: lcdif@20f8000 {
compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
reg = <0x020f8000 0x4000>;
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
@ -740,9 +778,10 @@
<&clks IMX6SL_CLK_DUMMY>;
clock-names = "pix", "axi", "disp_axi";
status = "disabled";
power-domains = <&pd_disp>;
};
dcp: dcp@020fc000 {
dcp: crypto@20fc000 {
compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
reg = <0x020fc000 0x4000>;
interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
@ -751,14 +790,14 @@
};
};
aips2: bus@02100000 {
aips2: bus@2100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02100000 0x100000>;
ranges;
usbotg1: usb@02184000 {
usbotg1: usb@2184000 {
compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
reg = <0x02184000 0x200>;
interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
@ -771,7 +810,7 @@
status = "disabled";
};
usbotg2: usb@02184200 {
usbotg2: usb@2184200 {
compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
reg = <0x02184200 0x200>;
interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
@ -784,11 +823,13 @@
status = "disabled";
};
usbh: usb@02184400 {
usbh: usb@2184400 {
compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
reg = <0x02184400 0x200>;
interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_USBOH3>;
fsl,usbphy = <&usbphynop1>;
phy_type = "hsic";
fsl,usbmisc = <&usbmisc 2>;
dr_mode = "host";
ahb-burst-config = <0x0>;
@ -797,14 +838,14 @@
status = "disabled";
};
usbmisc: usbmisc@02184800 {
usbmisc: usbmisc@2184800 {
#index-cells = <1>;
compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
reg = <0x02184800 0x200>;
clocks = <&clks IMX6SL_CLK_USBOH3>;
};
fec: ethernet@02188000 {
fec: ethernet@2188000 {
compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
reg = <0x02188000 0x4000>;
interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
@ -814,7 +855,7 @@
status = "disabled";
};
usdhc1: usdhc@02190000 {
usdhc1: mmc@2190000 {
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
reg = <0x02190000 0x4000>;
interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
@ -826,7 +867,7 @@
status = "disabled";
};
usdhc2: usdhc@02194000 {
usdhc2: mmc@2194000 {
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
reg = <0x02194000 0x4000>;
interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
@ -838,7 +879,7 @@
status = "disabled";
};
usdhc3: usdhc@02198000 {
usdhc3: mmc@2198000 {
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
reg = <0x02198000 0x4000>;
interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
@ -850,7 +891,7 @@
status = "disabled";
};
usdhc4: usdhc@0219c000 {
usdhc4: mmc@219c000 {
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
reg = <0x0219c000 0x4000>;
interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
@ -862,7 +903,7 @@
status = "disabled";
};
i2c1: i2c@021a0000 {
i2c1: i2c@21a0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
@ -872,7 +913,7 @@
status = "disabled";
};
i2c2: i2c@021a4000 {
i2c2: i2c@21a4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
@ -882,7 +923,7 @@
status = "disabled";
};
i2c3: i2c@021a8000 {
i2c3: i2c@21a8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
@ -892,17 +933,20 @@
status = "disabled";
};
mmdc: mmdc@021b0000 {
memory-controller@21b0000 {
compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>;
};
rngb: rngb@021b4000 {
rngb: rngb@21b4000 {
compatible = "fsl,imx6sl-rngb", "fsl,imx25-rngb";
reg = <0x021b4000 0x4000>;
interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_DUMMY>;
};
weim: weim@021b8000 {
weim: weim@21b8000 {
#address-cells = <2>;
#size-cells = <1>;
reg = <0x021b8000 0x4000>;
@ -911,17 +955,51 @@
status = "disabled";
};
ocotp: ocotp@021bc000 {
ocotp: efuse@21bc000 {
compatible = "fsl,imx6sl-ocotp", "syscon";
reg = <0x021bc000 0x4000>;
clocks = <&clks IMX6SL_CLK_OCOTP>;
#address-cells = <1>;
#size-cells = <1>;
cpu_speed_grade: speed-grade@10 {
reg = <0x10 4>;
};
tempmon_calib: calib@38 {
reg = <0x38 4>;
};
tempmon_temp_grade: temp-grade@20 {
reg = <0x20 4>;
};
};
audmux: audmux@021d8000 {
audmux: audmux@21d8000 {
compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
reg = <0x021d8000 0x4000>;
status = "disabled";
};
};
gpu_2d: gpu@2200000 {
compatible = "vivante,gc";
reg = <0x02200000 0x4000>;
interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
<&clks IMX6SL_CLK_GPU2D_OVG>;
clock-names = "bus", "core";
power-domains = <&pd_pu>;
};
gpu_vg: gpu@2204000 {
compatible = "vivante,gc";
reg = <0x02204000 0x4000>;
interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
<&clks IMX6SL_CLK_GPU2D_OVG>;
clock-names = "bus", "core";
power-domains = <&pd_pu>;
};
};
};

899
arch/arm/dts/imx6sll-evk.dts
View file

File diff suppressed because it is too large Load diff

6
arch/arm/dts/imx6sll-pinfunc.h
View file

@ -1,9 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright 2016 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
* Copyright 2017-2018 NXP.
*
*/

447
arch/arm/dts/imx6sll.dtsi
View file

@ -1,18 +1,19 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <dt-bindings/clock/imx6sll-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "imx6sll-pinfunc.h"
#include "skeleton.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
@ -35,6 +36,8 @@
spi1 = &ecspi2;
spi3 = &ecspi3;
spi4 = &ecspi4;
usb0 = &usbotg1;
usb1 = &usbotg2;
usbphy0 = &usbphy1;
usbphy1 = &usbphy2;
};
@ -48,80 +51,58 @@
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
operating-points = <
operating-points =
/* kHz uV */
996000 1225000
792000 1175000
396000 1075000
198000 975000
>;
fsl,soc-operating-points = <
<996000 1275000>,
<792000 1175000>,
<396000 1075000>,
<198000 975000>;
fsl,soc-operating-points =
/* ARM kHz SOC-PU uV */
996000 1225000
792000 1175000
396000 1175000
198000 1175000
>;
<996000 1175000>,
<792000 1175000>,
<396000 1175000>,
<198000 1175000>;
clock-latency = <61036>; /* two CLK32 periods */
fsl,low-power-run;
#cooling-cells = <2>;
clocks = <&clks IMX6SLL_CLK_ARM>,
<&clks IMX6SLL_CLK_PLL2_PFD2>,
<&clks IMX6SLL_CLK_STEP>,
<&clks IMX6SLL_CLK_PLL1_SW>,
<&clks IMX6SLL_CLK_PLL1_SYS>,
<&clks IMX6SLL_CLK_PLL1>,
<&clks IMX6SLL_PLL1_BYPASS>,
<&clks IMX6SLL_PLL1_BYPASS_SRC>;
<&clks IMX6SLL_CLK_PLL1_SYS>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys", "pll1", "pll1_bypass",
"pll1_bypass_src";
"pll1_sw", "pll1_sys";
nvmem-cells = <&cpu_speed_grade>;
nvmem-cell-names = "speed_grade";
};
};
intc: interrupt-controller@00a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00a01000 0x1000>,
<0x00a00100 0x100>;
interrupt-parent = <&intc>;
ckil: clock-ckil {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "ckil";
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
osc: clock-osc-24m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "osc";
};
ckil: clock@0 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "ckil";
};
ipp_di0: clock-ipp-di0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "ipp_di0";
};
osc: clock@1 {
compatible = "fixed-clock";
reg = <1>;
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "osc";
};
ipp_di0: clock@2 {
compatible = "fixed-clock";
reg = <2>;
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "ipp_di0";
};
ipp_di1: clock@3 {
compatible = "fixed-clock";
reg = <3>;
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "ipp_di1";
};
ipp_di1: clock-ipp-di1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "ipp_di1";
};
soc {
@ -131,42 +112,21 @@
interrupt-parent = <&gpc>;
ranges;
busfreq {
compatible = "fsl,imx_busfreq";
clocks = <&clks IMX6SLL_CLK_PLL2_PFD2>, <&clks IMX6SLL_CLK_PLL2_198M>,
<&clks IMX6SLL_CLK_PLL2_BUS>, <&clks IMX6SLL_CLK_ARM>,
<&clks IMX6SLL_CLK_PLL3_USB_OTG>, <&clks IMX6SLL_CLK_PERIPH>,
<&clks IMX6SLL_CLK_PERIPH_PRE>, <&clks IMX6SLL_CLK_PERIPH_CLK2>,
<&clks IMX6SLL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SLL_CLK_OSC>,
<&clks IMX6SLL_CLK_AHB>, <&clks IMX6SLL_CLK_AXI_PODF>,
<&clks IMX6SLL_CLK_PERIPH2>, <&clks IMX6SLL_CLK_PERIPH2_PRE>,
<&clks IMX6SLL_CLK_PERIPH2_CLK2>, <&clks IMX6SLL_CLK_PERIPH2_CLK2_SEL>,
<&clks IMX6SLL_CLK_STEP>, <&clks IMX6SLL_CLK_MMDC_P0_FAST>, <&clks IMX6SLL_PLL1_BYPASS_SRC>,
<&clks IMX6SLL_PLL1_BYPASS>, <&clks IMX6SLL_CLK_PLL1_SYS>, <&clks IMX6SLL_CLK_PLL1_SW>,
<&clks IMX6SLL_CLK_PLL1>;
clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg",
"periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc",
"ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel",
"step", "mmdc", "pll1_bypass_src", "pll1_bypass", "pll1_sys", "pll1_sw", "pll1";
fsl,max_ddr_freq = <400000000>;
};
ocrams: sram@00900000 {
compatible = "fsl,lpm-sram";
reg = <0x00900000 0x4000>;
};
ocrams_ddr: sram@00904000 {
compatible = "fsl,ddr-lpm-sram";
reg = <0x00904000 0x1000>;
};
ocram: sram@00905000 {
ocram: sram@900000 {
compatible = "mmio-sram";
reg = <0x00905000 0x1B000>;
reg = <0x00900000 0x20000>;
};
L2: l2-cache@00a02000 {
intc: interrupt-controller@a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00a01000 0x1000>,
<0x00a00100 0x100>;
interrupt-parent = <&intc>;
};
L2: cache-controller@a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
@ -176,21 +136,21 @@
arm,data-latency = <4 2 3>;
};
aips1: bus@02000000 {
aips1: bus@2000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02000000 0x100000>;
ranges;
spba: spba-bus@02000000 {
spba: spba-bus@2000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02000000 0x40000>;
ranges;
spdif: spdif@02004000 {
spdif: spdif@2004000 {
compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif";
reg = <0x02004000 0x4000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
@ -214,7 +174,7 @@
status = "disabled";
};
ecspi1: ecspi@02008000 {
ecspi1: spi@2008000 {
compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
reg = <0x02008000 0x4000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
@ -226,7 +186,7 @@
status = "disabled";
};
ecspi2: ecspi@0200c000 {
ecspi2: spi@200c000 {
compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
reg = <0x0200c000 0x4000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
@ -238,7 +198,7 @@
status = "disabled";
};
ecspi3: ecspi@02010000 {
ecspi3: spi@2010000 {
compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
reg = <0x02010000 0x4000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
@ -250,7 +210,7 @@
status = "disabled";
};
ecspi4: ecspi@02014000 {
ecspi4: spi@2014000 {
compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
reg = <0x02014000 0x4000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
@ -262,10 +222,11 @@
status = "disabled";
};
uart4: serial@02018000 {
compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
uart4: serial@2018000 {
compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
"fsl,imx21-uart";
reg = <0x02018000 0x4000>;
interrupts =<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
dma-names = "rx", "tx";
clocks = <&clks IMX6SLL_CLK_UART4_IPG>,
@ -274,8 +235,9 @@
status = "disabled";
};
uart1: serial@02020000 {
compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
uart1: serial@2020000 {
compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
"fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
@ -286,8 +248,9 @@
status = "disabled";
};
uart2: serial@02024000 {
compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
uart2: serial@2024000 {
compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
"fsl,imx21-uart";
reg = <0x02024000 0x4000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
@ -298,8 +261,8 @@
status = "disabled";
};
ssi1: ssi@02028000 {
compatible = "fsl,imx6sll-ssi", "fsl,imx51-ssi";
ssi1: ssi@2028000 {
compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
reg = <0x02028000 0x4000>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 37 22 0>, <&sdma 38 22 0>;
@ -311,8 +274,8 @@
status = "disabled";
};
ssi2: ssi2@0202c000 {
compatible = "fsl,imx6sll-ssi", "fsl,imx51-ssi";
ssi2: ssi@202c000 {
compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
reg = <0x0202c000 0x4000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 41 22 0>, <&sdma 42 22 0>;
@ -324,8 +287,8 @@
status = "disabled";
};
ssi3: ssi@02030000 {
compatible = "fsl,imx6sll-ssi", "fsl,imx51-ssi";
ssi3: ssi@2030000 {
compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
reg = <0x02030000 0x4000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 45 22 0>, <&sdma 46 22 0>;
@ -337,8 +300,9 @@
status = "disabled";
};
uart3: serial@02034000 {
compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
uart3: serial@2034000 {
compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
"fsl,imx21-uart";
reg = <0x02034000 0x4000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
@ -350,48 +314,48 @@
};
};
pwm1: pwm@02080000 {
pwm1: pwm@2080000 {
compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
reg = <0x02080000 0x4000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_PWM1>,
<&clks IMX6SLL_CLK_PWM1>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
};
pwm2: pwm@02084000 {
pwm2: pwm@2084000 {
compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
reg = <0x02084000 0x4000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_PWM2>,
<&clks IMX6SLL_CLK_PWM2>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
};
pwm3: pwm@02088000 {
pwm3: pwm@2088000 {
compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
reg = <0x02088000 0x4000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_PWM3>,
<&clks IMX6SLL_CLK_PWM3>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
};
pwm4: pwm@0208c000 {
pwm4: pwm@208c000 {
compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
reg = <0x0208c000 0x4000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_PWM4>,
<&clks IMX6SLL_CLK_PWM4>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
};
gpt1: gpt@02098000 {
compatible = "fsl,imx6sll-gpt";
gpt1: timer@2098000 {
compatible = "fsl,imx6sl-gpt";
reg = <0x02098000 0x4000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_GPT_BUS>,
@ -399,73 +363,104 @@
clock-names = "ipg", "per";
};
gpio1: gpio@0209c000 {
gpio1: gpio@209c000 {
compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
reg = <0x0209c000 0x4000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 94 7>, <&iomuxc 7 25 25>;
};
gpio2: gpio@020a0000 {
gpio2: gpio@20a0000 {
compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
reg = <0x020a0000 0x4000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 50 32>;
};
gpio3: gpio@020a4000 {
gpio3: gpio@20a4000 {
compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
reg = <0x020a4000 0x4000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 82 12>, <&iomuxc 12 103 4>,
<&iomuxc 16 101 2>, <&iomuxc 18 5 1>,
<&iomuxc 21 6 11>;
};
gpio4: gpio@020a8000 {
gpio4: gpio@20a8000 {
compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
reg = <0x020a8000 0x4000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_GPIO4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 17 8>, <&iomuxc 8 107 8>,
<&iomuxc 16 151 1>, <&iomuxc 17 149 1>,
<&iomuxc 18 146 1>, <&iomuxc 19 144 1>,
<&iomuxc 20 142 1>, <&iomuxc 21 143 1>,
<&iomuxc 22 150 1>, <&iomuxc 23 148 1>,
<&iomuxc 24 147 1>, <&iomuxc 25 145 1>,
<&iomuxc 26 152 1>, <&iomuxc 27 125 1>,
<&iomuxc 28 131 1>, <&iomuxc 29 134 1>,
<&iomuxc 30 129 1>, <&iomuxc 31 133 1>;
};
gpio5: gpio@020ac000 {
gpio5: gpio@20ac000 {
compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
reg = <0x020ac000 0x4000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_GPIO5>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 135 1>, <&iomuxc 1 128 1>,
<&iomuxc 2 132 1>, <&iomuxc 3 130 1>,
<&iomuxc 4 127 1>, <&iomuxc 5 126 1>,
<&iomuxc 6 120 1>, <&iomuxc 7 123 1>,
<&iomuxc 8 118 1>, <&iomuxc 9 122 1>,
<&iomuxc 10 124 1>, <&iomuxc 11 117 1>,
<&iomuxc 12 121 1>, <&iomuxc 13 119 1>,
<&iomuxc 14 116 1>, <&iomuxc 15 115 1>,
<&iomuxc 16 140 2>, <&iomuxc 18 136 1>,
<&iomuxc 19 138 1>, <&iomuxc 20 139 1>,
<&iomuxc 21 137 1>;
};
gpio6: gpio@020b0000 {
gpio6: gpio@20b0000 {
compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
reg = <0x020b0000 0x4000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_GPIO6>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
kpp: kpp@020b8000 {
kpp: keypad@20b8000 {
compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp";
reg = <0x020b8000 0x4000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
@ -473,14 +468,14 @@
status = "disabled";
};
wdog1: wdog@020bc000 {
wdog1: watchdog@20bc000 {
compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
reg = <0x020bc000 0x4000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_WDOG1>;
};
wdog2: wdog@020c0000 {
wdog2: watchdog@20c0000 {
compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
reg = <0x020c0000 0x4000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
@ -488,7 +483,7 @@
status = "disabled";
};
clks: ccm@020c4000 {
clks: clock-controller@20c4000 {
compatible = "fsl,imx6sll-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
@ -496,19 +491,25 @@
#clock-cells = <1>;
clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>;
assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>;
};
anatop: anatop@020c8000 {
anatop: anatop@20c8000 {
compatible = "fsl,imx6sll-anatop",
"fsl,imx6q-anatop",
"syscon", "simple-bus";
"syscon", "simple-mfd";
reg = <0x020c8000 0x4000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg_3p0: regulator-3p0@120 {
reg_3p0: regulator-3p0@20c8120 {
compatible = "fsl,anatop-regulator";
reg = <0x20c8120>;
regulator-name = "vdd3p0";
regulator-min-microvolt = <2625000>;
regulator-max-microvolt = <3400000>;
@ -520,18 +521,19 @@
anatop-max-voltage = <3400000>;
anatop-enable-bit = <0>;
};
tempmon: temperature-sensor {
compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon";
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gpc>;
fsl,tempmon = <&anatop>;
nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
};
};
tempmon: tempmon {
compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon";
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
fsl,tempmon = <&anatop>;
fsl,tempmon-data = <&ocotp>;
clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
status = "disabled";
};
usbphy1: usbphy@020c9000 {
usbphy1: usb-phy@20c9000 {
compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
"fsl,imx23-usbphy";
reg = <0x020c9000 0x1000>;
@ -541,7 +543,7 @@
fsl,anatop = <&anatop>;
};
usbphy2: usbphy@020ca000 {
usbphy2: usb-phy@20ca000 {
compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
"fsl,imx23-usbphy";
reg = <0x020ca000 0x1000>;
@ -551,7 +553,7 @@
fsl,anatop = <&anatop>;
};
snvs: snvs@020cc000 {
snvs: snvs@20cc000 {
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
reg = <0x020cc000 0x4000>;
@ -559,7 +561,8 @@
compatible = "fsl,sec-v4.0-mon-rtc-lp";
regmap = <&snvs>;
offset = <0x34>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
};
snvs_poweroff: snvs-poweroff {
@ -567,6 +570,7 @@
regmap = <&snvs>;
offset = <0x38>;
mask = <0x61>;
status = "disabled";
};
snvs_pwrkey: snvs-powerkey {
@ -574,21 +578,12 @@
regmap = <&snvs>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
linux,keycode = <KEY_POWER>;
wakeup;
wakeup-source;
status = "disabled";
};
};
epit1: epit@020d0000 {
reg = <0x020d0000 0x4000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
};
epit2: epit@020d4000 {
reg = <0x020d4000 0x4000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
};
src: src@020d8000 {
src: reset-controller@20d8000 {
compatible = "fsl,imx6sll-src", "fsl,imx51-src";
reg = <0x020d8000 0x4000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
@ -596,28 +591,27 @@
#reset-cells = <1>;
};
gpc: gpc@020dc000 {
gpc: interrupt-controller@20dc000 {
compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc";
reg = <0x020dc000 0x4000>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00 0x0 0x1400640>;
};
iomuxc: iomuxc@020e0000 {
iomuxc: pinctrl@20e0000 {
compatible = "fsl,imx6sll-iomuxc";
reg = <0x020e0000 0x4000>;
};
gpr: iomuxc-gpr@020e4000 {
gpr: iomuxc-gpr@20e4000 {
compatible = "fsl,imx6sll-iomuxc-gpr",
"fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x020e4000 0x4000>;
};
csi: csi@020e8000 {
csi: csi@20e8000 {
compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi";
reg = <0x020e8000 0x4000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
@ -628,11 +622,11 @@
status = "disabled";
};
sdma: sdma@020ec000 {
compatible = "fsl,imx6sll-sdma", "fsl,imx35-sdma";
sdma: dma-controller@20ec000 {
compatible = "fsl,imx6sll-sdma", "fsl,imx6ul-sdma";
reg = <0x020ec000 0x4000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_SDMA>,
clocks = <&clks IMX6SLL_CLK_IPG>,
<&clks IMX6SLL_CLK_SDMA>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
@ -640,27 +634,16 @@
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
};
pxp: pxp@020f0000 {
compatible = "fsl,imx6ull-pxp-dma", "fsl,imx7d-pxp-dma";
reg = <0x020f0000 0x4000>;
pxp: pxp@20f0000 {
compatible = "fsl,imx6sll-pxp", "fsl,imx6ull-pxp";
reg = <0x20f0000 0x4000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_DUMMY>,
<&clks IMX6SLL_CLK_PXP>;
clock-names = "pxp_ipg", "pxp_axi";
status = "disabled";
clocks = <&clks IMX6SLL_CLK_PXP>;
clock-names = "axi";
};
epdc: epdc@020f4000 {
compatible = "fsl,imx6sll-epdc", "fsl,imx7d-epdc";
reg = <0x020f4000 0x4000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_EPDC_AXI>, <&clks IMX6SLL_CLK_EPDC_PIX>;
clock-names = "epdc_axi", "epdc_pix";
status = "disabled";
};
lcdif: lcdif@020f8000 {
lcdif: lcd-controller@20f8000 {
compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif";
reg = <0x020f8000 0x4000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
@ -671,8 +654,8 @@
status = "disabled";
};
dcp: dcp@020fc000 {
compatible = "fsl,imx6sl-dcp";
dcp: crypto@20fc000 {
compatible = "fsl,imx28-dcp";
reg = <0x020fc000 0x4000>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
@ -682,14 +665,14 @@
};
};
aips2: bus@02100000 {
aips2: bus@2100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02100000 0x100000>;
ranges;
usbotg1: usb@02184000 {
usbotg1: usb@2184000 {
compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
"fsl,imx27-usb";
reg = <0x02184000 0x200>;
@ -704,7 +687,7 @@
status = "disabled";
};
usbotg2: usb@02184200 {
usbotg2: usb@2184200 {
compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
"fsl,imx27-usb";
reg = <0x02184200 0x200>;
@ -718,14 +701,14 @@
status = "disabled";
};
usbmisc: usbmisc@02184800 {
usbmisc: usbmisc@2184800 {
#index-cells = <1>;
compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc",
"fsl,imx6q-usbmisc";
reg = <0x02184800 0x200>;
};
usdhc1: usdhc@02190000 {
usdhc1: mmc@2190000 {
compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
reg = <0x02190000 0x4000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
@ -739,7 +722,7 @@
status = "disabled";
};
usdhc2: usdhc@02194000 {
usdhc2: mmc@2194000 {
compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
reg = <0x02194000 0x4000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
@ -753,7 +736,7 @@
status = "disabled";
};
usdhc3: usdhc@02198000 {
usdhc3: mmc@2198000 {
compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
reg = <0x02198000 0x4000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
@ -767,17 +750,17 @@
status = "disabled";
};
i2c1: i2c@021a0000 {
i2c1: i2c@21a0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fs,imx6sll-i2c", "fsl,imx21-i2c";
compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
reg = <0x021a0000 0x4000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_I2C1>;
status = "disabled";
};
i2c2: i2c@021a4000 {
i2c2: i2c@21a4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
@ -787,7 +770,7 @@
status = "disabled";
};
i2c3: i2c@021a8000 {
i2c3: i2c@21a8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
@ -797,56 +780,50 @@
status = "disabled";
};
romcp@021ac000 {
compatible = "fsl,imx6sll-romcp", "syscon";
reg = <0x021ac000 0x4000>;
};
mmdc: mmdc@021b0000 {
mmdc: memory-controller@21b0000 {
compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>;
};
rngb: rngb@021b4000 {
compatible = "fsl,imx6sl-rng", "fsl,imx-rng", "imx-rng";
rngb: rng@21b4000 {
compatible = "fsl,imx6sll-rngb", "fsl,imx25-rngb";
reg = <0x021b4000 0x4000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_DUMMY>;
clocks = <&clks IMX6SLL_CLK_DUMMY>;
};
ocotp: ocotp-ctrl@021bc000 {
ocotp: efuse@21bc000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,imx6sll-ocotp", "syscon";
reg = <0x021bc000 0x4000>;
clocks = <&clks IMX6SLL_CLK_OCOTP>;
cpu_speed_grade: speed-grade@10 {
reg = <0x10 4>;
};
tempmon_calib: calib@38 {
reg = <0x38 4>;
};
tempmon_temp_grade: temp-grade@20 {
reg = <0x20 4>;
};
};
csu: csu@021c0000 {
compatible = "fsl,imx6sll-csu";
reg = <0x021c0000 0x4000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
snvs_gpr: snvs-gpr@0x021c4000 {
compatible = "fsl, imx6sll-snvs-gpr";
reg = <0x021c4000 0x10000>;
};
iomuxc_snvs: iomuxc-snvs@021c8000 {
compatible = "fsl,imx6sll-iomuxc-snvs";
reg = <0x021c80000 0x10000>;
};
audmux: audmux@021d8000 {
audmux: audmux@21d8000 {
compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux";
reg = <0x021d8000 0x4000>;
status = "disabled";
};
uart5: serial@021f4000 {
compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
uart5: serial@21f4000 {
compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart",
"fsl,imx21-uart";
reg = <0x021f4000 0x4000>;
interrupts =<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
dma-names = "rx", "tx";
clocks = <&clks IMX6SLL_CLK_UART5_IPG>,

623
arch/arm/dts/imx6sx-sabreauto.dts
View file

@ -1,10 +1,6 @@
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2014 Freescale Semiconductor, Inc.
/dts-v1/;
@ -14,29 +10,171 @@
model = "Freescale i.MX6 SoloX Sabre Auto Board";
compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
memory {
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
regulators {
compatible = "simple-bus";
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
user {
label = "debug";
gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
vcc_sd3: regulator-vcc-sd3 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_vcc_sd3>;
regulator-name = "VCC_SD3";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_can_wake: regulator-can-wake {
compatible = "regulator-fixed";
regulator-name = "can-wake";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_can_en: regulator-can-en {
compatible = "regulator-fixed";
regulator-name = "can-en";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_can_wake>;
};
reg_can_stby: regulator-can-stby {
compatible = "regulator-fixed";
regulator-name = "can-stby";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&max7310_b 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_can_en>;
};
reg_cs42888: cs42888_supply {
compatible = "regulator-fixed";
regulator-name = "cs42888_supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
sound-cs42888 {
compatible = "fsl,imx6-sabreauto-cs42888",
"fsl,imx-audio-cs42888";
model = "imx-cs42888";
audio-cpu = <&esai>;
audio-asrc = <&asrc>;
audio-codec = <&cs42888>;
audio-routing =
"Line Out Jack", "AOUT1L",
"Line Out Jack", "AOUT1R",
"Line Out Jack", "AOUT2L",
"Line Out Jack", "AOUT2R",
"Line Out Jack", "AOUT3L",
"Line Out Jack", "AOUT3R",
"Line Out Jack", "AOUT4L",
"Line Out Jack", "AOUT4R",
"AIN1L", "Line In Jack",
"AIN1R", "Line In Jack",
"AIN2L", "Line In Jack",
"AIN2R", "Line In Jack";
};
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "imx-spdif";
spdif-controller = <&spdif>;
spdif-in;
};
};
&anaclk2 {
clock-frequency = <24576000>;
};
&clks {
assigned-clocks = <&clks IMX6SX_PLL4_BYPASS_SRC>,
<&clks IMX6SX_PLL4_BYPASS>,
<&clks IMX6SX_CLK_PLL4_POST_DIV>;
assigned-clock-parents = <&clks IMX6SX_CLK_LVDS2_IN>,
<&clks IMX6SX_PLL4_BYPASS_SRC>;
assigned-clock-rates = <0>, <0>, <24576000>;
};
&esai {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esai>;
assigned-clocks = <&clks IMX6SX_CLK_ESAI_SEL>,
<&clks IMX6SX_CLK_ESAI_EXTAL>;
assigned-clock-parents = <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <0>, <24576000>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy1>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
vcc_sd3: regulator@0 {
compatible = "regulator-fixed";
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_vcc_sd3>;
regulator-name = "VCC_SD3";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_can_stby>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_can_stby>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
@ -68,17 +206,325 @@
status = "okay";
};
&iomuxc {
pinctrl_egalax_int: egalax-intgrp {
fsl,pins = <
MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x10b0
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9
MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
>;
};
pinctrl_esai: esaigrp {
fsl,pins = <
MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030
MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030
MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030
MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030
MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030
MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030
MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030
MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030
MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030
MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020
MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020
MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
>;
};
pinctrl_led: ledgrp {
fsl,pins = <
MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x17059
>;
};
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1
MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
fsl,pins = <
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
fsl,pins = <
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
>;
};
pinctrl_vcc_sd3: vccsd3grp {
fsl,pins = <
MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0
>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
cs42888: cs42888@48 {
compatible = "cirrus,cs42888";
reg = <0x48>;
clocks = <&anaclk2 0>;
clock-names = "mclk";
VA-supply = <&reg_cs42888>;
VD-supply = <&reg_cs42888>;
VLS-supply = <&reg_cs42888>;
VLC-supply = <&reg_cs42888>;
};
touchscreen@4 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_egalax_int>;
interrupt-parent = <&gpio6>;
interrupts = <22 IRQ_TYPE_EDGE_FALLING>;
wakeup-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>;
};
pfuze100: pmic@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
regulators {
sw1a_reg: sw1ab {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw1c_reg: sw1c {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
sw3a_reg: sw3a {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
sw3b_reg: sw3b {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen4_reg: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
max7322: gpio@68 {
compatible = "maxim,max7322";
reg = <0x68>;
gpio-controller;
#gpio-cells = <2>;
};
};
&i2c3 {
clock-frequency = <100000>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_2>;
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
max7310_a: gpio@30 {
@ -96,133 +542,16 @@
};
};
&qspi1 {
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi1_1>;
pinctrl-0 = <&pinctrl_spdif>;
assigned-clocks = <&clks IMX6SX_CLK_SPDIF_PODF>;
assigned-clock-rates = <24576000>;
status = "okay";
ddrsmp=<2>;
flash0: n25q256a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a";
spi-max-frequency = <29000000>;
reg = <0>;
};
flash1: n25q256a@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a";
spi-max-frequency = <29000000>;
reg = <1>;
};
};
&iomuxc {
imx6x-sabreauto {
pinctrl_i2c2_1: i2c2grp-1 {
fsl,pins = <
MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
>;
};
pinctrl_i2c3_2: i2c3grp-2 {
fsl,pins = <
MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
>;
};
pinctrl_qspi1_1: qspi1grp_1 {
fsl,pins = <
MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x70a1
MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x70a1
MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x70a1
MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x70a1
MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x70a1
MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x70a1
MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x70a1
MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x70a1
MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x70a1
MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x70a1
MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x70a1
MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x70a1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
fsl,pins = <
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
fsl,pins = <
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
>;
};
pinctrl_vcc_sd3: vccsd3grp {
fsl,pins = <
MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
>;
};
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
};

8
arch/arm/dts/imx6sx-sdb.dts
View file

@ -108,23 +108,23 @@
pinctrl-0 = <&pinctrl_qspi2>;
status = "okay";
flash0: n25q256a@0 {
flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a", "jedec,spi-nor";
spi-max-frequency = <29000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
spi-tx-bus-width = <1>;
reg = <0>;
};
flash1: n25q256a@2 {
flash1: flash@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a", "jedec,spi-nor";
spi-max-frequency = <29000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
spi-tx-bus-width = <1>;
reg = <2>;
};
};

56
arch/arm/dts/imx6sx-sdb.dtsi
View file

@ -153,6 +153,8 @@
sound {
compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hp>;
model = "wm8962-audio";
ssi-controller = <&ssi2>;
audio-codec = <&codec>;
@ -165,6 +167,7 @@
"IN3R", "AMIC";
mux-int-port = <2>;
mux-ext-port = <6>;
hp-det-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>;
};
panel {
@ -179,6 +182,15 @@
};
};
};
sound-spdif {
compatible = "fsl,imx-audio-spdif",
"fsl,imx6sx-sdb-spdif";
model = "imx-spdif";
spdif-controller = <&spdif>;
spdif-out;
};
};
&audmux {
@ -194,6 +206,7 @@
phy-mode = "rgmii-id";
phy-handle = <&ethphy1>;
phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
fsl,magic-packet;
status = "okay";
mdio {
@ -213,8 +226,9 @@
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rgmii";
phy-mode = "rgmii-id";
phy-handle = <&ethphy2>;
fsl,magic-packet;
status = "okay";
};
@ -281,6 +295,7 @@
};
&pwm3 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
@ -296,6 +311,14 @@
status = "disabled";
};
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif>;
assigned-clocks = <&clks IMX6SX_CLK_SPDIF_PODF>;
assigned-clock-rates = <24576000>;
status = "okay";
};
&ssi2 {
status = "okay";
};
@ -450,6 +473,12 @@
>;
};
pinctrl_hp: hpgrp {
fsl,pins = <
MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
@ -505,6 +534,13 @@
>;
};
pinctrl_mqs: mqsgrp {
fsl,pins = <
MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x120b0
MX6SX_PAD_SD2_CMD__MQS_LEFT 0x120b0
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0
@ -562,19 +598,25 @@
>;
};
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1
MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x1b0b1
MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x1b0b1
MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS 0x1b0b1
MX6SX_PAD_KEY_COL2__UART5_DCE_RTS 0x1b0b1
>;
};

50
arch/arm/dts/imx6sx-softing-vining-2000.dts
View file

@ -1,9 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2016 Christoph Fritz <chf.fritz@googlemail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
@ -16,11 +13,6 @@
model = "Softing VIN|ING 2000";
compatible = "samtec,imx6sx-vining-2000", "fsl,imx6sx";
aliases {
mmc0 = &usdhc4;
mmc1 = &usdhc2;
};
chosen {
stdout-path = &uart1;
};
@ -48,22 +40,22 @@
regulator-max-microvolt = <3300000>;
};
pwmleds {
led-controller {
compatible = "pwm-leds";
red {
led-1 {
label = "red";
max-brightness = <255>;
pwms = <&pwm6 0 50000>;
};
green {
led-2 {
label = "green";
max-brightness = <255>;
pwms = <&pwm2 0 50000>;
};
blue {
led-3 {
label = "blue";
max-brightness = <255>;
pwms = <&pwm1 0 50000>;
@ -101,7 +93,7 @@
&ecspi4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
cs-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
status = "okay";
};
@ -270,17 +262,6 @@
status = "okay";
};
&reg_pcie {
regulator-always-on;
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpios>;
@ -409,15 +390,15 @@
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1
MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1
MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1
>;
};
@ -515,19 +496,30 @@
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>;
reset-gpio-active-high;
status = "okay";
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm2 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&pwm6 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm6>;
status = "okay";

86
arch/arm/dts/imx6sx-udoo-neo.dtsi
View file

@ -183,6 +183,27 @@
status = "okay";
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clock-frequency = <100000>;
status = "okay";
hdmi-transmitter@70 {
compatible = "nxp,tda998x";
reg = <0x70>;
interrupts-extended = <&gpio3 27 IRQ_TYPE_LEVEL_LOW>;
ports {
port {
hdmi: endpoint {
remote-endpoint = <&lcdc>;
};
};
};
};
};
&i2c4 { /* Onboard Motion sensors */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
@ -190,10 +211,22 @@
status = "disabled";
};
&lcdif1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd>;
status = "okay";
port {
lcdc: endpoint {
remote-endpoint = <&hdmi>;
};
};
};
&iomuxc {
pinctrl_bt_reg: btreggrp {
fsl,pins =
<MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x15059>;
<MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x15059>;
};
pinctrl_enet1: enet1grp {
@ -227,12 +260,52 @@
<MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins =
<MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1>,
<MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins =
<MX6SX_PAD_USB_H_DATA__I2C4_SDA 0x4001b8b1>,
<MX6SX_PAD_USB_H_STROBE__I2C4_SCL 0x4001b8b1>;
};
pinctrl_lcd: lcdgrp {
fsl,pins = <
MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins =
<MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1>,
@ -273,24 +346,23 @@
pinctrl_otg1_reg: otg1grp {
fsl,pins =
<MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0>;
<MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0>;
};
pinctrl_otg2_reg: otg2grp {
fsl,pins =
<MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x10b0>;
<MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x10b0>;
};
pinctrl_usb_otg1: usbotg1grp {
fsl,pins =
<MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059>,
<MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x10b0>;
<MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059>,
<MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x10b0>;
};
pinctrl_usb_otg2: usbot2ggrp {
fsl,pins =
<MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC 0x10b0>;
<MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC 0x10b0>;
};
pinctrl_usdhc2: usdhc2grp {

129
arch/arm/dts/imx6sx.dtsi
View file

@ -49,6 +49,9 @@
spi2 = &ecspi3;
spi3 = &ecspi4;
spi4 = &ecspi5;
usb0 = &usbotg1;
usb1 = &usbotg2;
usb2 = &usbh;
usbphy0 = &usbphy1;
usbphy1 = &usbphy2;
};
@ -87,6 +90,8 @@
"pll1_sw", "pll1_sys";
arm-supply = <&reg_arm>;
soc-supply = <&reg_soc>;
nvmem-cells = <&cpu_speed_grade>;
nvmem-cell-names = "speed_grade";
};
};
@ -132,14 +137,10 @@
clock-output-names = "anaclk2";
};
tempmon: tempmon {
compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
interrupt-parent = <&gpc>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
fsl,tempmon = <&anatop>;
nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
mqs: mqs {
compatible = "fsl,imx6sx-mqs";
gpr = <&gpr>;
status = "disabled";
};
pmu {
@ -153,7 +154,7 @@
#phy-cells = <0>;
};
soc {
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
@ -181,7 +182,7 @@
interrupt-parent = <&intc>;
};
L2: l2-cache@a02000 {
L2: cache-controller@a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
@ -215,7 +216,7 @@
clocks = <&clks IMX6SX_CLK_APBH_DMA>;
};
gpmi: gpmi-nand@1806000{
gpmi: nand-controller@1806000{
compatible = "fsl,imx6sx-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
@ -333,6 +334,7 @@
};
esai: esai@2024000 {
compatible = "fsl,imx6sx-esai", "fsl,imx35-esai";
reg = <0x02024000 0x4000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
@ -342,6 +344,9 @@
<&clks IMX6SX_CLK_SPBA>;
clock-names = "core", "mem", "extal",
"fsys", "spba";
dmas = <&sdma 23 21 0>,
<&sdma 24 21 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -388,18 +393,28 @@
};
asrc: asrc@2034000 {
compatible = "fsl,imx6sx-asrc", "fsl,imx53-asrc";
reg = <0x02034000 0x4000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
<&clks IMX6SX_CLK_ASRC_IPG>,
<&clks IMX6SX_CLK_SPDIF>,
<&clks IMX6SX_CLK_SPBA>;
clock-names = "mem", "ipg", "asrck", "spba";
dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
<&sdma 19 20 1>, <&sdma 20 20 1>,
<&sdma 21 20 1>, <&sdma 22 20 1>;
clocks = <&clks IMX6SX_CLK_ASRC_IPG>,
<&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
<&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
<&clks IMX6SX_CLK_SPBA>;
clock-names = "mem", "ipg", "asrck_0",
"asrck_1", "asrck_2", "asrck_3", "asrck_4",
"asrck_5", "asrck_6", "asrck_7", "asrck_8",
"asrck_9", "asrck_a", "asrck_b", "asrck_c",
"asrck_d", "asrck_e", "asrck_f", "spba";
dmas = <&sdma 17 23 1>, <&sdma 18 23 1>,
<&sdma 19 23 1>, <&sdma 20 23 1>,
<&sdma 21 23 1>, <&sdma 22 23 1>;
dma-names = "rxa", "rxb", "rxc",
"txa", "txb", "txc";
fsl,asrc-rate = <48000>;
fsl,asrc-width = <16>;
status = "okay";
};
};
@ -411,7 +426,7 @@
clocks = <&clks IMX6SX_CLK_PWM1>,
<&clks IMX6SX_CLK_PWM1>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
};
pwm2: pwm@2084000 {
@ -421,7 +436,7 @@
clocks = <&clks IMX6SX_CLK_PWM2>,
<&clks IMX6SX_CLK_PWM2>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
};
pwm3: pwm@2088000 {
@ -431,7 +446,7 @@
clocks = <&clks IMX6SX_CLK_PWM3>,
<&clks IMX6SX_CLK_PWM3>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
};
pwm4: pwm@208c000 {
@ -441,7 +456,7 @@
clocks = <&clks IMX6SX_CLK_PWM4>,
<&clks IMX6SX_CLK_PWM4>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
};
flexcan1: can@2090000 {
@ -451,7 +466,7 @@
clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
<&clks IMX6SX_CLK_CAN1_SERIAL>;
clock-names = "ipg", "per";
fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
fsl,stop-mode = <&gpr 0x10 1>;
status = "disabled";
};
@ -462,11 +477,11 @@
clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
<&clks IMX6SX_CLK_CAN2_SERIAL>;
clock-names = "ipg", "per";
fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
fsl,stop-mode = <&gpr 0x10 2>;
status = "disabled";
};
gpt: gpt@2098000 {
gpt: timer@2098000 {
compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
reg = <0x02098000 0x4000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
@ -559,7 +574,7 @@
gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
};
kpp: kpp@20b8000 {
kpp: keypad@20b8000 {
compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
reg = <0x020b8000 0x4000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
@ -567,14 +582,14 @@
status = "disabled";
};
wdog1: wdog@20bc000 {
wdog1: watchdog@20bc000 {
compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
reg = <0x020bc000 0x4000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_IPG>;
};
wdog2: wdog@20c0000 {
wdog2: watchdog@20c0000 {
compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
reg = <0x020c0000 0x4000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
@ -582,7 +597,7 @@
status = "disabled";
};
clks: ccm@20c4000 {
clks: clock-controller@20c4000 {
compatible = "fsl,imx6sx-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
@ -594,7 +609,7 @@
anatop: anatop@20c8000 {
compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
"syscon", "simple-bus";
"syscon", "simple-mfd";
reg = <0x020c8000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
@ -694,6 +709,16 @@
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
tempmon: tempmon {
compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
interrupt-parent = <&gpc>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
fsl,tempmon = <&anatop>;
nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
};
};
usbphy1: usbphy@20c9000 {
@ -752,7 +777,7 @@
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
};
src: src@20d8000 {
src: reset-controller@20d8000 {
compatible = "fsl,imx6sx-src", "fsl,imx51-src";
reg = <0x020d8000 0x4000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
@ -806,7 +831,7 @@
};
};
iomuxc: iomuxc@20e0000 {
iomuxc: pinctrl@20e0000 {
compatible = "fsl,imx6sx-iomuxc";
reg = <0x020e0000 0x4000>;
};
@ -837,7 +862,7 @@
reg = <0x02100000 0x100000>;
ranges;
crypto: caam@2100000 {
crypto: crypto@2100000 {
compatible = "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
@ -850,13 +875,13 @@
<&clks IMX6SX_CLK_EIM_SLOW>;
clock-names = "mem", "aclk", "ipg", "emi_slow";
sec_jr0: jr0@1000 {
sec_jr0: jr@1000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr1@2000 {
sec_jr1: jr@2000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
@ -928,6 +953,7 @@
"enet_clk_ref", "enet_out";
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
fsl,stop-mode = <&gpr 0x10 3>;
status = "disabled";
};
@ -940,7 +966,7 @@
status = "disabled";
};
usdhc1: usdhc@2190000 {
usdhc1: mmc@2190000 {
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
reg = <0x02190000 0x4000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
@ -952,7 +978,7 @@
status = "disabled";
};
usdhc2: usdhc@2194000 {
usdhc2: mmc@2194000 {
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
reg = <0x02194000 0x4000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
@ -964,7 +990,7 @@
status = "disabled";
};
usdhc3: usdhc@2198000 {
usdhc3: mmc@2198000 {
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
reg = <0x02198000 0x4000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
@ -976,7 +1002,7 @@
status = "disabled";
};
usdhc4: usdhc@219c000 {
usdhc4: mmc@219c000 {
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
reg = <0x0219c000 0x4000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
@ -1037,6 +1063,7 @@
<&clks IMX6SX_CLK_ENET_PTP>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
fsl,stop-mode = <&gpr 0x10 4>;
status = "disabled";
};
@ -1051,13 +1078,17 @@
status = "disabled";
};
ocotp: ocotp@21bc000 {
ocotp: efuse@21bc000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,imx6sx-ocotp", "syscon";
reg = <0x021bc000 0x4000>;
clocks = <&clks IMX6SX_CLK_OCOTP>;
cpu_speed_grade: speed-grade@10 {
reg = <0x10 4>;
};
tempmon_calib: calib@38 {
reg = <0x38 4>;
};
@ -1289,7 +1320,7 @@
status = "disabled";
};
wdog3: wdog@2288000 {
wdog3: watchdog@2288000 {
compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
reg = <0x02288000 0x4000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
@ -1329,7 +1360,7 @@
clocks = <&clks IMX6SX_CLK_PWM5>,
<&clks IMX6SX_CLK_PWM5>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
};
pwm6: pwm@22a8000 {
@ -1339,7 +1370,7 @@
clocks = <&clks IMX6SX_CLK_PWM6>,
<&clks IMX6SX_CLK_PWM6>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
};
pwm7: pwm@22ac000 {
@ -1349,7 +1380,7 @@
clocks = <&clks IMX6SX_CLK_PWM7>,
<&clks IMX6SX_CLK_PWM7>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
};
pwm8: pwm@22b0000 {
@ -1359,20 +1390,20 @@
clocks = <&clks IMX6SX_CLK_PWM8>,
<&clks IMX6SX_CLK_PWM8>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
};
};
pcie: pcie@8ffc000 {
compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
compatible = "fsl,imx6sx-pcie";
reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
ranges = <0x81000000 0 0 0x08f80000 0 0x00010000>, /* downstream I/O */
<0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
num-lanes = <1>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";

2
arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi
View file

@ -8,7 +8,7 @@
display0 = &lcdif;
};
&{/soc} {
&soc {
u-boot,dm-pre-reloc;
};

103
arch/arm/dts/imx6ul-kontron-bl-43.dts Normal file
View file

@ -0,0 +1,103 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
*/
#include "imx6ul-kontron-bl.dts"
/ {
model = "Kontron BL i.MX6UL 43 (N631X S 43)";
compatible = "kontron,bl-imx6ul-43", "kontron,bl-imx6ul",
"kontron,sl-imx6ul", "fsl,imx6ul";
backlight {
compatible = "pwm-backlight";
pwms = <&pwm7 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
status = "okay";
};
};
&i2c4 {
touchscreen@5d {
compatible = "goodix,gt928";
reg = <0x5d>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cap_touch>;
interrupt-parent = <&gpio5>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
irq-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
};
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
/* Leave status disabled because of missing display panel node */
};
&pwm7 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm7>;
status = "okay";
};
&iomuxc {
pinctrl_cap_touch: captouchgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* Touch Interrupt */
MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 /* Touch Reset */
MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Touch Wake */
>;
};
pinctrl_lcdif_ctrl: lcdifctrlgrp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79
>;
};
pinctrl_lcdif_dat: lcdifdatgrp {
fsl,pins = <
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
>;
};
pinctrl_pwm7: pwm7grp {
fsl,pins = <
MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x110b0
>;
};
};

0
arch/arm/dts/imx6ul-kontron-n6x1x-s-u-boot.dtsi → arch/arm/dts/imx6ul-kontron-bl-common-u-boot.dtsi
View file

0
arch/arm/dts/imx6ul-kontron-n6x1x-s.dtsi → arch/arm/dts/imx6ul-kontron-bl-common.dtsi
View file

2
arch/arm/dts/imx6ul-kontron-n631x-s-u-boot.dtsi → arch/arm/dts/imx6ul-kontron-bl-u-boot.dtsi
View file

@ -4,4 +4,4 @@
* Copyright (C) 2018 Kontron Electronics GmbH
*/
#include "imx6ul-kontron-n6x1x-s-u-boot.dtsi"
#include "imx6ul-kontron-bl-common-u-boot.dtsi"

9
arch/arm/dts/imx6ul-kontron-n631x-s.dts → arch/arm/dts/imx6ul-kontron-bl.dts
View file

@ -7,11 +7,10 @@
/dts-v1/;
#include "imx6ul-kontron-n631x-som.dtsi"
#include "imx6ul-kontron-n6x1x-s.dtsi"
#include "imx6ul-kontron-sl.dtsi"
#include "imx6ul-kontron-bl-common.dtsi"
/ {
model = "Kontron N631X S";
compatible = "kontron,imx6ul-n631x-s", "kontron,imx6ul-n631x-som",
"fsl,imx6ul";
model = "Kontron BL i.MX6UL (N631X S)";
compatible = "kontron,bl-imx6ul", "kontron,sl-imx6ul", "fsl,imx6ul";
};

423
arch/arm/dts/imx6ul-kontron-n6x1x-s.dts
View file

@ -1,423 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6ul-kontron-n6x1x-som.dtsi"
/ {
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led1 {
label = "debug-led1";
gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
default-state = "off";
linux,default-trigger = "heartbeat";
};
led2 {
label = "debug-led2";
gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led3 {
label = "debug-led3";
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
pwm-beeper {
compatible = "pwm-beeper";
pwms = <&pwm8 0 5000>;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vref_adc: regulator-vref-adc {
compatible = "regulator-fixed";
regulator-name = "vref-adc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&adc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc1>;
num-channels = <3>;
vref-supply = <&reg_vref_adc>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
&ecspi1 {
cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
eeprom@0 {
compatible = "anvo,anv32e61w", "atmel,at25";
reg = <0>;
spi-max-frequency = <20000000>;
spi-cpha;
spi-cpol;
pagesize = <1>;
size = <8192>;
address-width = <16>;
};
};
&fec1 {
pinctrl-0 = <&pinctrl_enet1>;
/delete-node/ mdio;
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
phy-mode = "rmii";
phy-handle = <&ethphy2>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
reg = <1>;
micrel,led-mode = <0>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
};
ethphy2: ethernet-phy@2 {
reg = <2>;
micrel,led-mode = <0>;
clocks = <&clks IMX6UL_CLK_ENET2_REF>;
clock-names = "rmii-ref";
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
rtc@32 {
compatible = "epson,rx8900";
reg = <0x32>;
};
};
&pwm8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm8>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
linux,rs485-enabled-at-boot-time;
rs485-rx-during-tx;
rs485-rts-active-low;
uart-has-rtscts;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
dr_mode = "otg";
srp-disable;
hnp-disable;
adp-disable;
over-current-active-low;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
vbus-supply = <&reg_5v>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
keep-power-in-suspend;
wakeup-source;
vmmc-supply = <&reg_3v3>;
voltage-ranges = <3300 3300>;
bus-width = <4>;
no-1-8-v;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
non-removable;
keep-power-in-suspend;
wakeup-source;
vmmc-supply = <&reg_3v3>;
voltage-ranges = <3300 3300>;
bus-width = <4>;
no-1-8-v;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
pinctrl_adc1: adc1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1
MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1
MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1
MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009
>;
};
pinctrl_enet2_mdio: enet2mdiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
>;
};
pinctrl_flexcan2: flexcan2grp{
fsl,pins = <
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
>;
};
pinctrl_gpio: gpiogrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */
MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */
MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */
MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0
MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0
>;
};
pinctrl_pwm8: pwm8grp {
fsl,pins = <
MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1
MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1
/*
* mux unused RTS to make sure it doesn't cause
* any interrupts when it is undefined
*/
MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
>;
};
pinctrl_usbotg1: usbotg1 {
fsl,pins = <
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0
>;
};
};

15
arch/arm/dts/imx6ul-kontron-n6x1x-som-common.dtsi → arch/arm/dts/imx6ul-kontron-sl-common.dtsi
View file

@ -11,6 +11,11 @@
chosen {
stdout-path = &uart4;
};
memory@80000000 {
reg = <0x80000000 0x10000000>;
device_type = "memory";
};
};
&ecspi2 {
@ -55,6 +60,16 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
spi-max-frequency = <104000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
reg = <0>;
};
};
&wdog1 {

6
arch/arm/dts/imx6ul-kontron-n631x-som.dtsi → arch/arm/dts/imx6ul-kontron-sl.dtsi
View file

@ -6,9 +6,9 @@
*/
#include "imx6ul.dtsi"
#include "imx6ul-kontron-n6x1x-som-common.dtsi"
#include "imx6ul-kontron-sl-common.dtsi"
/ {
model = "Kontron N631X SOM";
compatible = "kontron,imx6ul-n631x-som", "fsl,imx6ul";
model = "Kontron SL i.MX6UL (N631X SOM)";
compatible = "kontron,sl-imx6ul", "fsl,imx6ul";
};

5
arch/arm/dts/imx6ul-phytec-segin.dtsi
View file

@ -83,11 +83,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc1>;
vref-supply = <&reg_adc1_vref_3v3>;
/*
* driver can not separate a specific channel so we request 4 channels
* here - we need only the fourth channel
*/
num-channels = <4>;
status = "disabled";
};

36
arch/arm/dts/imx6ul.dtsi
View file

@ -64,20 +64,18 @@
clock-frequency = <696000000>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
operating-points = <
operating-points =
/* kHz uV */
696000 1275000
528000 1175000
396000 1025000
198000 950000
>;
fsl,soc-operating-points = <
<696000 1275000>,
<528000 1175000>,
<396000 1025000>,
<198000 950000>;
fsl,soc-operating-points =
/* KHz uV */
696000 1275000
528000 1175000
396000 1175000
198000 1175000
>;
<696000 1275000>,
<528000 1175000>,
<396000 1175000>,
<198000 1175000>;
clocks = <&clks IMX6UL_CLK_ARM>,
<&clks IMX6UL_CLK_PLL2_BUS>,
<&clks IMX6UL_CLK_PLL2_PFD2>,
@ -139,7 +137,7 @@
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
};
soc {
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
@ -149,6 +147,9 @@
ocram: sram@900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x20000>;
ranges = <0 0x00900000 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
};
intc: interrupt-controller@a01000 {
@ -543,7 +544,7 @@
};
kpp: keypad@20b8000 {
compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp";
reg = <0x020b8000 0x4000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_KPP>;
@ -923,7 +924,6 @@
reg = <0x02198000 0x4000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_ADC1>;
num-channels = <2>;
clock-names = "adc";
fsl,adck-max-frequency = <30000000>, <40000000>,
<20000000>;
@ -998,7 +998,7 @@
};
csi: csi@21c4000 {
compatible = "fsl,imx6ul-csi", "fsl,imx7-csi";
compatible = "fsl,imx6ul-csi";
reg = <0x021c4000 0x4000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_CSI>;
@ -1007,7 +1007,7 @@
};
lcdif: lcdif@21c8000 {
compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
compatible = "fsl,imx6ul-lcdif", "fsl,imx6sx-lcdif";
reg = <0x021c8000 0x4000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
@ -1028,7 +1028,7 @@
qspi: spi@21e0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
compatible = "fsl,imx6ul-qspi";
reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;

10
arch/arm/dts/imx6ull-colibri.dtsi
View file

@ -94,7 +94,6 @@
};
&adc1 {
num-channels = <10>;
vref-supply = <&reg_module_3v3_avdd>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc1>;
@ -166,7 +165,7 @@
atmel_mxt_ts: touchscreen@4a {
compatible = "atmel,maxtouch";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_atmel_conn>;
pinctrl-0 = <&pinctrl_atmel_conn &pinctrl_atmel_snvs_conn>;
reg = <0x4a>;
interrupt-parent = <&gpio5>;
interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */
@ -331,7 +330,6 @@
pinctrl_atmel_conn: atmelconngrp {
fsl,pins = <
MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */
MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */
>;
};
@ -684,6 +682,12 @@
};
&iomuxc_snvs {
pinctrl_atmel_snvs_conn: atmelsnvsconngrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */
>;
};
pinctrl_snvs_gpio1: snvsgpio1grp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */

2
arch/arm/dts/imx6ull-kontron-n641x-s-u-boot.dtsi → arch/arm/dts/imx6ull-kontron-bl-u-boot.dtsi
View file

@ -4,4 +4,4 @@
* Copyright (C) 2018 Kontron Electronics GmbH
*/
#include "imx6ul-kontron-n6x1x-s-u-boot.dtsi"
#include "imx6ul-kontron-bl-common-u-boot.dtsi"

15
arch/arm/dts/imx6ull-kontron-bl.dts Normal file
View file

@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2019 Kontron Electronics GmbH
*/
/dts-v1/;
#include "imx6ull-kontron-sl.dtsi"
#include "imx6ul-kontron-bl-common.dtsi"
/ {
model = "Kontron BL i.MX6ULL (N641X S)";
compatible = "kontron,bl-imx6ull", "kontron,sl-imx6ull", "fsl,imx6ull";
};

16
arch/arm/dts/imx6ull-kontron-n641x-s.dts
View file

@ -1,16 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2019 Kontron Electronics GmbH
*/
/dts-v1/;
#include "imx6ull-kontron-n641x-som.dtsi"
#include "imx6ul-kontron-n6x1x-s.dtsi"
/ {
model = "Kontron N641X S";
compatible = "kontron,imx6ull-n641x-s", "kontron,imx6ull-n641x-som",
"fsl,imx6ull";
};

6
arch/arm/dts/imx6ull-kontron-n641x-som.dtsi → arch/arm/dts/imx6ull-kontron-sl.dtsi
View file

@ -5,9 +5,9 @@
*/
#include "imx6ull.dtsi"
#include "imx6ul-kontron-n6x1x-som-common.dtsi"
#include "imx6ul-kontron-sl-common.dtsi"
/ {
model = "Kontron N641X SOM";
compatible = "kontron,imx6ull-n641x-som", "fsl,imx6ull";
model = "Kontron SL i.MX6ULL (N641X SOM)";
compatible = "kontron,sl-imx6ull", "fsl,imx6ull";
};

2
arch/arm/dts/imx6ull.dtsi
View file

@ -50,7 +50,7 @@
};
/ {
soc {
soc: soc {
aips3: bus@2200000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;

1
arch/arm/dts/imx6ulz.dtsi
View file

@ -16,7 +16,6 @@
/delete-property/ serial7;
/delete-property/ spi2;
/delete-property/ spi3;
/delete-property/ spi4;
};
};

2
arch/arm/dts/imx7ulp-com-u-boot.dtsi
View file

@ -32,6 +32,6 @@
u-boot,dm-spl;
};
&gpio0 {
&gpio_ptc {
u-boot,dm-spl;
};

34
arch/arm/dts/imx7ulp-com.dts
View file

@ -1,12 +1,11 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2019 NXP
// Author: Fabio Estevam <fabio.estevam@nxp.com>
/dts-v1/;
#include "imx7ulp.dtsi"
#include "imx7ulp-com-u-boot.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Embedded Artists i.MX7ULP COM";
@ -16,9 +15,9 @@
stdout-path = &lpuart4;
};
memory {
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x8000000>;
reg = <0x60000000 0x4000000>;
};
};
@ -37,11 +36,9 @@
status = "okay";
};
&usbphy1 {
fsl,tx-d-cal = <88>;
};
&usdhc0 {
assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc0>;
non-removable;
@ -51,15 +48,6 @@
};
&iomuxc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog_1>;
pinctrl_hog_1: hoggrp-1 {
fsl,pins = <
IMX7ULP_PAD_PTC1__PTC1 0x20000
>;
};
pinctrl_lpuart4: lpuart4grp {
fsl,pins = <
IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
@ -67,6 +55,12 @@
>;
};
pinctrl_usbotg1_id: otg1idgrp {
fsl,pins = <
IMX7ULP_PAD_PTC13__USB0_ID 0x10003
>;
};
pinctrl_usdhc0: usdhc0grp {
fsl,pins = <
IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
@ -82,10 +76,4 @@
IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42
>;
};
pinctrl_usbotg1_id: otg1idgrp {
fsl,pins = <
IMX7ULP_PAD_PTC13__USB0_ID 0x10003
>;
};
};

430
arch/arm/dts/imx7ulp-evk.dts
View file

@ -1,9 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
* Copyright 2017-2018 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
/dts-v1/;
@ -12,365 +11,57 @@
/ {
model = "NXP i.MX7ULP EVK";
compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system";
compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";
chosen {
bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0000,115200";
stdout-path = &lpuart4;
};
bcmdhd_wlan_0: bcmdhd_wlan@0 {
compatible = "android,bcmdhd_wlan";
wlreg_on-supply = <&wlreg_on>;
bcmdhd_fw = "/lib/firmware/bcm/1DX_BCM4343W/fw_bcmdhd.bin";
bcmdhd_nv = "/lib/firmware/bcm/1DX_BCM4343W/bcmdhd.1DX.SDIO.cal";
};
memory {
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
backlight {
compatible = "gpio-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight>;
gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>;
default-on;
compatible = "pwm-backlight";
pwms = <&tpm4 1 50000 0>;
brightness-levels = <0 20 25 30 35 40 100>;
default-brightness-level = <6>;
status = "okay";
};
mipi_dsi_reset: mipi-dsi-reset {
compatible = "gpio-reset";
reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
reset-delay-us = <1000>;
#reset-cells = <0>;
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1_vbus>;
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio_ptc 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
wlreg_on: fixedregulator@100 {
compatible = "regulator-fixed";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "wlreg_on";
gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
startup-delay-us = <100>;
enable-active-high;
};
reg_usb_otg1_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1_vbus>;
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vsd_3v3: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
pf1550-rpmsg {
compatible = "fsl,pf1550-rpmsg";
sw1_reg: SW1 {
regulator-name = "SW1";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1387500>;
regulator-boot-on;
regulator-always-on;
};
sw2_reg: SW2 {
regulator-name = "SW2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1387500>;
regulator-boot-on;
regulator-always-on;
};
sw3_reg: SW3 {
regulator-name = "SW3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: VREFDDR {
regulator-name = "VREFDDR";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
vldo1_reg: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vldo2_reg: LDO2 {
regulator-name = "LDO2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vldo3_reg: LDO3 {
regulator-name = "LDO3";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vsd_3v3: regulator-vsd-3v3 {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc0_rst>;
gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&iomuxc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog_1>;
imx7ulp-evk {
pinctrl_hog_1: hoggrp-1 {
fsl,pins = <
IMX7ULP_PAD_PTC1__PTC1 0x20000
>;
};
pinctrl_backlight: backlight_grp {
fsl,pins = <
IMX7ULP_PAD_PTF2__PTF2 0x20000
>;
};
pinctrl_lpi2c5: lpi2c5grp {
fsl,pins = <
IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x27
IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x27
>;
};
pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp {
fsl,pins = <
IMX7ULP_PAD_PTC19__PTC19 0x20003
>;
};
pinctrl_lpuart4: lpuart4grp {
fsl,pins = <
IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
IMX7ULP_PAD_PTC2__LPUART4_TX 0x3
>;
};
pinctrl_lpuart6: lpuart6grp {
fsl,pins = <
IMX7ULP_PAD_PTE10__LPUART6_TX 0x3
IMX7ULP_PAD_PTE11__LPUART6_RX 0x3
IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x3
IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x3
IMX7ULP_PAD_PTE7__PTE7 0x20000 /* BT_REG_ON */
>;
};
pinctrl_lpuart7: lpuart7grp {
fsl,pins = <
IMX7ULP_PAD_PTF14__LPUART7_TX 0x3
IMX7ULP_PAD_PTF15__LPUART7_RX 0x3
IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x3
IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x3
>;
};
pinctrl_usdhc0: usdhc0grp {
fsl,pins = <
IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042
IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
IMX7ULP_PAD_PTC10__PTC10 0x10000 /* USDHC0 CD */
IMX7ULP_PAD_PTD0__PTD0 0x20000 /* USDHC0 RST */
>;
};
pinctrl_usdhc0_8bit: usdhc0grp_8bit {
fsl,pins = <
IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042
IMX7ULP_PAD_PTD3__SDHC0_D7 0x43
IMX7ULP_PAD_PTD4__SDHC0_D6 0x43
IMX7ULP_PAD_PTD5__SDHC0_D5 0x43
IMX7ULP_PAD_PTD6__SDHC0_D4 0x43
IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42
>;
};
pinctrl_lpi2c7: lpi2c7grp {
fsl,pins = <
IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x27
IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x27
>;
};
pinctrl_lpspi3: lpspi3grp {
fsl,pins = <
IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x0
IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x0
IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x0
IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x0
>;
};
pinctrl_usbotg1_vbus: otg1vbusgrp {
fsl,pins = <
IMX7ULP_PAD_PTC0__PTC0 0x20000
>;
};
pinctrl_usbotg1_id: otg1idgrp {
fsl,pins = <
IMX7ULP_PAD_PTC13__USB0_ID 0x10003
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX7ULP_PAD_PTE3__SDHC1_CMD 0x43
IMX7ULP_PAD_PTE2__SDHC1_CLK 0x10042
IMX7ULP_PAD_PTE1__SDHC1_D0 0x43
IMX7ULP_PAD_PTE0__SDHC1_D1 0x43
IMX7ULP_PAD_PTE5__SDHC1_D2 0x43
IMX7ULP_PAD_PTE4__SDHC1_D3 0x43
>;
};
pinctrl_usdhc1_rst: usdhc1grp_rst {
fsl,pins = <
IMX7ULP_PAD_PTE11__PTE11 0x20000 /* USDHC1 RST */
IMX7ULP_PAD_PTE13__PTE13 0x10003 /* USDHC1 CD */
IMX7ULP_PAD_PTE12__PTE12 0x10003 /* USDHC1 WP */
IMX7ULP_PAD_PTE14__SDHC1_VS 0x43 /* USDHC1 VSEL */
>;
};
pinctrl_dsi_hdmi: dsi_hdmi_grp {
fsl,pins = <
IMX7ULP_PAD_PTC18__PTC18 0x10003 /* DSI_HDMI_INT */
>;
};
};
};
&lcdif {
status = "okay";
disp-dev = "mipi_dsi_northwest";
display = <&display0>;
display0: display@0 {
bits-per-pixel = <16>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <9200000>;
hactive = <480>;
vactive = <272>;
hfront-porch = <8>;
hback-porch = <4>;
hsync-len = <41>;
vback-porch = <2>;
vfront-porch = <4>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&lpi2c7 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c7>;
};
&lpi2c5 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c5>;
status = "okay";
};
&lpspi3 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi3>;
status = "okay";
spidev0: spi@0 {
reg = <0>;
compatible = "rohm,dh2228fv";
spi-max-frequency = <1000000>;
};
};
&mipi_dsi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mipi_dsi_reset>;
lcd_panel = "TRULY-WVGA-TFT3P5581E";
resets = <&mipi_dsi_reset>;
status = "okay";
};
&lpuart4 { /* console */
&lpuart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart4>;
status = "okay";
};
&lpuart6 { /* BT */
&tpm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart6>;
status = "okay";
};
&lpuart7 { /* Uart test */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart7>;
status = "disabled";
};
&rpmsg{
pinctrl-0 = <&pinctrl_pwm0>;
status = "okay";
};
@ -381,21 +72,62 @@
srp-disable;
hnp-disable;
adp-disable;
disable-over-current;
status = "okay";
};
&usbphy1 {
fsl,tx-d-cal = <88>;
};
&usdhc0 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc0>;
pinctrl-1 = <&pinctrl_usdhc0>;
pinctrl-2 = <&pinctrl_usdhc0>;
pinctrl-3 = <&pinctrl_usdhc0>;
cd-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_vsd_3v3>;
vqmmc-supply = <&vldo2_reg>;
status = "okay";
};
&iomuxc1 {
pinctrl_lpuart4: lpuart4grp {
fsl,pins = <
IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
IMX7ULP_PAD_PTC2__LPUART4_TX 0x3
>;
bias-pull-up;
};
pinctrl_pwm0: pwm0grp {
fsl,pins = <
IMX7ULP_PAD_PTF2__TPM4_CH1 0x2
>;
};
pinctrl_usbotg1_vbus: otg1vbusgrp {
fsl,pins = <
IMX7ULP_PAD_PTC0__PTC0 0x20000
>;
};
pinctrl_usbotg1_id: otg1idgrp {
fsl,pins = <
IMX7ULP_PAD_PTC13__USB0_ID 0x10003
>;
};
pinctrl_usdhc0: usdhc0grp {
fsl,pins = <
IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
IMX7ULP_PAD_PTD2__SDHC0_CLK 0x40
IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
IMX7ULP_PAD_PTC10__PTC10 0x3 /* CD */
>;
};
pinctrl_usdhc0_rst: usdhc0-gpio-rst-grp {
fsl,pins = <
IMX7ULP_PAD_PTD0__PTD0 0x3
>;
};
};

1004
arch/arm/dts/imx7ulp-pinfunc.h
View file

File diff suppressed because it is too large Load diff

685
arch/arm/dts/imx7ulp.dtsi
View file

@ -1,28 +1,29 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015-2016 Freescale Semiconductor, Inc.
* Copyright 2021 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <dt-bindings/clock/imx7ulp-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "imx7ulp-pinfunc.h"
/ {
interrupt-parent = <&intc>;
#address-cells = <1>;
#size-cells = <1>;
aliases {
gpio0 = &gpio4;
gpio1 = &gpio5;
gpio2 = &gpio0;
gpio3 = &gpio1;
gpio4 = &gpio2;
gpio5 = &gpio3;
gpio0 = &gpio_ptc;
gpio1 = &gpio_ptd;
gpio2 = &gpio_pte;
gpio3 = &gpio_ptf;
i2c0 = &lpi2c6;
i2c1 = &lpi2c7;
mmc0 = &usdhc0;
mmc1 = &usdhc1;
serial0 = &lpuart4;
@ -30,173 +31,95 @@
serial2 = &lpuart6;
serial3 = &lpuart7;
usbphy0 = &usbphy1;
usb0 = &usbotg1;
i2c4 = &lpi2c4;
i2c5 = &lpi2c5;
i2c6 = &lpi2c6;
i2c7 = &lpi2c7;
spi0 = &qspi1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
cpu0: cpu@f00 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
reg = <0xf00>;
};
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0xC000000>;
alignment = <0x2000>;
linux,cma-default;
};
rpmsg_reserved: rpmsg@9FFF0000 {
no-map;
reg = <0x9FF00000 0x100000>;
};
};
intc: interrupt-controller@40021000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x40021000 0x1000>,
<0x40022000 0x100>;
<0x40022000 0x1000>;
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
ckil: clock@0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "ckil";
};
osc: clock@1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "osc";
};
sirc: clock@2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <16000000>;
clock-output-names = "sirc";
};
firc: clock@3 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
clock-output-names = "firc";
};
upll: clock@4 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <480000000>;
clock-output-names = "upll";
};
mpll: clock@5 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <480000000>;
clock-output-names = "mpll";
};
rosc: clock-rosc {
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "rosc";
#clock-cells = <0>;
};
sram: sram@20000000 {
compatible = "fsl,lpm-sram";
reg = <0x1fffc000 0x4000>;
sosc: clock-sosc {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "sosc";
#clock-cells = <0>;
};
ahbbridge0: ahb-bridge0@40000000 {
compatible = "fsl,aips-bus", "simple-bus";
sirc: clock-sirc {
compatible = "fixed-clock";
clock-frequency = <16000000>;
clock-output-names = "sirc";
#clock-cells = <0>;
};
firc: clock-firc {
compatible = "fixed-clock";
clock-frequency = <48000000>;
clock-output-names = "firc";
#clock-cells = <0>;
};
upll: clock-upll {
compatible = "fixed-clock";
clock-frequency = <480000000>;
clock-output-names = "upll";
#clock-cells = <0>;
};
ahbbridge0: bus@40000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40000000 0x800000>;
ranges;
edma0: dma-controller@40080000 {
edma1: dma-controller@40080000 {
#dma-cells = <2>;
compatible = "nxp,imx7ulp-edma";
compatible = "fsl,imx7ulp-edma";
reg = <0x40080000 0x2000>,
<0x40210000 0x1000>;
dma-channels = <32>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dma", "dmamux0";
clocks = <&clks IMX7ULP_CLK_DMA1>, <&clks IMX7ULP_CLK_DMA_MUX1>;
};
mu: mu@40220000 {
compatible = "fsl,imx7ulp-mu", "fsl,imx6sx-mu";
reg = <0x40220000 0x1000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
nmi: nmi@40220000 {
compatible = "fsl,imx7ulp-nmi";
reg = <0x40220000 0x1000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
rpmsg: rpmsg{
compatible = "fsl,imx7ulp-rpmsg";
memory-region = <&rpmsg_reserved>;
status = "disabled";
};
snvs: snvs@40230000 {
compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
reg = <0x40230000 0x10000>;
snvs_rtc: snvs-rtc-lp{
compatible = "fsl,sec-v4.0-mon-rtc-lp";
regmap =<&snvs>;
offset = <0x34>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "snvs-rtc";
clocks = <&clks IMX7ULP_CLK_SNVS>;
};
clocks = <&pcc2 IMX7ULP_CLK_DMA1>,
<&pcc2 IMX7ULP_CLK_DMA_MUX1>;
};
crypto: crypto@40240000 {
@ -205,8 +128,8 @@
#size-cells = <1>;
reg = <0x40240000 0x10000>;
ranges = <0 0x40240000 0x10000>;
clocks = <&clks IMX7ULP_CLK_CAAM>,
<&clks IMX7ULP_CLK_NIC1_BUS_DIV>;
clocks = <&pcc2 IMX7ULP_CLK_CAAM>,
<&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
clock-names = "aclk", "ipg";
sec_jr0: jr@1000 {
@ -222,105 +145,55 @@
};
};
tpm5: tpm@40260000 {
compatible = "fsl,imx7ulp-tpm";
reg = <0x40260000 0x1000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_LPTPM5>;
};
lpit: 1@40270000 {
compatible = "fsl,imx-lpit";
reg = <0x40270000 0x1000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
/* clocks = <&lpclk>;*/
clocks = <&clks IMX7ULP_CLK_LPIT1>;
assigned-clock-rates = <48000000>;
assigned-clocks = <&clks IMX7ULP_CLK_LPIT1>;
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
};
lpi2c4: lpi2c4@402B0000 {
compatible = "fsl,imx7ulp-lpi2c";
reg = <0x402B0000 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_LPI2C4>;
clock-names = "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPI2C4>;
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
lpi2c5: lpi2c4@402C0000 {
compatible = "fsl,imx7ulp-lpi2c";
reg = <0x402C0000 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_LPI2C5>;
clock-names = "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPI2C5>;
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
lpspi2: lpspi@40290000 {
compatible = "fsl,imx7ulp-spi";
reg = <0x40290000 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_LPSPI2>;
clock-names = "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPSPI2>;
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
lpspi3: lpspi@402A0000 {
compatible = "fsl,imx7ulp-spi";
reg = <0x402A0000 0x10000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_LPSPI3>;
clock-names = "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPSPI3>;
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
lpuart4: serial@402D0000 {
lpuart4: serial@402d0000 {
compatible = "fsl,imx7ulp-lpuart";
reg = <0x402D0000 0x1000>;
reg = <0x402d0000 0x1000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_LPUART4>;
clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
clock-names = "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPUART4>;
assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>;
assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
assigned-clock-rates = <24000000>;
status = "disabled";
};
lpuart5: serial@402E0000 {
lpuart5: serial@402e0000 {
compatible = "fsl,imx7ulp-lpuart";
reg = <0x402E0000 0x1000>;
reg = <0x402e0000 0x1000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_LPUART5>;
clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
clock-names = "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPUART5>;
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
assigned-clock-rates = <48000000>;
dmas = <&edma0 0 20>, <&edma0 0 19>;
dma-names = "tx","rx";
status = "disabled";
};
tpm4: pwm@40250000 {
compatible = "fsl,imx7ulp-pwm";
reg = <0x40250000 0x1000>;
assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
#pwm-cells = <3>;
status = "disabled";
};
tpm5: tpm@40260000 {
compatible = "fsl,imx7ulp-tpm";
reg = <0x40260000 0x1000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
<&pcc2 IMX7ULP_CLK_LPTPM5>;
clock-names = "ipg", "per";
};
usbotg1: usb@40330000 {
compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb",
"fsl,imx27-usb";
compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
reg = <0x40330000 0x200>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_USB0>;
fsl,usbphy = <&usbphy1>;
clocks = <&pcc2 IMX7ULP_CLK_USB0>;
phys = <&usbphy1>;
fsl,usbmisc = <&usbmisc1 0>;
ahb-burst-config = <0x0>;
tx-burst-size-dword = <0x8>;
@ -329,314 +202,260 @@
};
usbmisc1: usbmisc@40330200 {
compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc";
#index-cells = <1>;
compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc",
"fsl,imx6q-usbmisc";
reg = <0x40330200 0x200>;
};
usbphy1: usbphy@0x40350000 {
compatible = "fsl,imx7ulp-usbphy",
"fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
usbphy1: usb-phy@40350000 {
compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy";
reg = <0x40350000 0x1000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_USB_PHY>;
nxp,sim = <&sim>;
clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>;
#phy-cells = <0>;
};
usdhc0: usdhc@40370000 {
compatible = "fsl,imx7ulp-usdhc";
usdhc0: mmc@40370000 {
compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
reg = <0x40370000 0x10000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
<&clks IMX7ULP_CLK_NIC1_DIV>,
<&clks IMX7ULP_CLK_USDHC0>;
clock-names ="ipg", "ahb", "per";
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
<&pcc2 IMX7ULP_CLK_USDHC0>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
status = "disabled";
};
usdhc1: usdhc@40380000 {
compatible = "fsl,imx7ulp-usdhc";
usdhc1: mmc@40380000 {
compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
reg = <0x40380000 0x10000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
<&clks IMX7ULP_CLK_NIC1_DIV>,
<&clks IMX7ULP_CLK_USDHC1>;
clock-names ="ipg", "ahb", "per";
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
<&pcc2 IMX7ULP_CLK_USDHC1>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
status = "disabled";
};
wdog1: wdog@403D0000 {
compatible = "fsl,imx7ulp-wdt";
reg = <0x403D0000 0x10000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_WDG1>;
assigned-clocks = <&clks IMX7ULP_CLK_WDG1>;
assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>;
/*
* As the 1KHz LPO clock rate is not trimed,the actually clock
* is about 667Hz, so the init timeout 60s should set 40*1000
* in the TOVAL register.
*/
timeout-sec = <40>;
};
wdog2: wdog@40430000 {
compatible = "fsl,imx7ulp-wdt";
reg = <0x40430000 0x10000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_WDG2>;
assigned-clocks = <&clks IMX7ULP_CLK_WDG2>;
assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>;
timeout-sec = <40>;
};
clks: scg1@403E0000 {
scg1: clock-controller@403e0000 {
compatible = "fsl,imx7ulp-scg1";
reg = <0x403E0000 0x10000>;
clocks = <&ckil>, <&osc>, <&sirc>,
<&firc>, <&upll>, <&mpll>;
clock-names = "ckil", "osc", "sirc",
"firc", "upll", "mpll";
reg = <0x403e0000 0x10000>;
clocks = <&rosc>, <&sosc>, <&sirc>,
<&firc>, <&upll>;
clock-names = "rosc", "sosc", "sirc",
"firc", "upll";
#clock-cells = <1>;
assigned-clocks = <&clks IMX7ULP_CLK_LPTPM5>,
<&clks IMX7ULP_CLK_USDHC1>;
assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>,
<&clks IMX7ULP_CLK_NIC1_DIV>;
};
pcc2: pcc2@403F0000 {
compatible = "fsl,imx7ulp-pcc2";
reg = <0x403F0000 0x10000>;
wdog1: watchdog@403d0000 {
compatible = "fsl,imx7ulp-wdt";
reg = <0x403d0000 0x10000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
timeout-sec = <40>;
};
pmc1: pmc1@40400000 {
compatible = "fsl,imx7ulp-pmc1";
reg = <0x40400000 0x1000>;
pcc2: clock-controller@403f0000 {
compatible = "fsl,imx7ulp-pcc2";
reg = <0x403f0000 0x10000>;
#clock-cells = <1>;
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
<&scg1 IMX7ULP_CLK_DDR_DIV>,
<&scg1 IMX7ULP_CLK_APLL_PFD2>,
<&scg1 IMX7ULP_CLK_APLL_PFD1>,
<&scg1 IMX7ULP_CLK_APLL_PFD0>,
<&scg1 IMX7ULP_CLK_UPLL>,
<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
<&scg1 IMX7ULP_CLK_ROSC>,
<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
"apll_pfd2", "apll_pfd1", "apll_pfd0",
"upll", "sosc_bus_clk",
"firc_bus_clk", "rosc", "spll_bus_clk";
assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
};
smc1: smc1@40410000 {
smc1: clock-controller@40410000 {
compatible = "fsl,imx7ulp-smc1";
reg = <0x40410000 0x1000>;
#clock-cells = <1>;
clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
<&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
clock-names = "divcore", "hsrun_divcore";
};
pcc3: clock-controller@40b30000 {
compatible = "fsl,imx7ulp-pcc3";
reg = <0x40b30000 0x10000>;
#clock-cells = <1>;
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
<&scg1 IMX7ULP_CLK_DDR_DIV>,
<&scg1 IMX7ULP_CLK_APLL_PFD2>,
<&scg1 IMX7ULP_CLK_APLL_PFD1>,
<&scg1 IMX7ULP_CLK_APLL_PFD0>,
<&scg1 IMX7ULP_CLK_UPLL>,
<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
<&scg1 IMX7ULP_CLK_ROSC>,
<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
"apll_pfd2", "apll_pfd1", "apll_pfd0",
"upll", "sosc_bus_clk",
"firc_bus_clk", "rosc", "spll_bus_clk";
};
};
ahbbridge1: ahb-bridge1@40800000 {
compatible = "fsl,aips-bus", "simple-bus";
ahbbridge1: bus@40800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40800000 0x800000>;
ranges;
lpi2c6: lpi2c6@40A40000 {
lpi2c6: i2c@40a40000 {
compatible = "fsl,imx7ulp-lpi2c";
reg = <0x40A40000 0x10000>;
reg = <0x40a40000 0x10000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_LPI2C6>;
clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
clock-names = "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPI2C6>;
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
lpi2c7: lpi2c7@40A50000 {
lpi2c7: i2c@40a50000 {
compatible = "fsl,imx7ulp-lpi2c";
reg = <0x40A50000 0x10000>;
reg = <0x40a50000 0x10000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_LPI2C7>;
clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
clock-names = "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPI2C7>;
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
lpuart6: serial@40A60000 {
lpuart6: serial@40a60000 {
compatible = "fsl,imx7ulp-lpuart";
reg = <0x40A60000 0x1000>;
reg = <0x40a60000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_LPUART6>;
clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
clock-names = "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPUART6>;
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
assigned-clock-rates = <48000000>;
dmas = <&edma0 0 22>, <&edma0 0 21>;
dma-names = "tx","rx";
status = "disabled";
};
lpuart7: serial@40A70000 {
lpuart7: serial@40a70000 {
compatible = "fsl,imx7ulp-lpuart";
reg = <0x40A70000 0x1000>;
reg = <0x40a70000 0x1000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_LPUART7>;
clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
clock-names = "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPUART7>;
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
assigned-clock-rates = <50000000>;
dmas = <&edma0 0 24>, <&edma0 0 23>;
dma-names = "tx","rx";
assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
lcdif: lcdif@40AA0000 {
compatible = "fsl,imx7ulp-lcdif";
reg = <0x40aa0000 0x10000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_DUMMY>,
<&clks IMX7ULP_CLK_LCDIF>,
<&clks IMX7ULP_CLK_DUMMY>;
clock-names = "axi", "pix", "disp_axi";
status = "disabled";
memory-controller@40ab0000 {
compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
reg = <0x40ab0000 0x1000>;
clocks = <&pcc3 IMX7ULP_CLK_MMDC>;
};
mipi_dsi: mipi_dsi@40A90000 {
compatible = "fsl,imx7ulp-mipi-dsi";
reg = <0x40A90000 0x10000>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_DSI>;
clock-names = "mipi_dsi_clk";
sim = <&sim>;
status = "disabled";
};
mmdc: mmdc@40ab0000 {
compatible = "fsl,imx7ulp-mmdc";
reg = <0x40ab0000 0x4000>;
};
pcc3: pcc3@40B30000 {
compatible = "fsl,imx7ulp-pcc3";
reg = <0x40B30000 0x10000>;
};
iomuxc: iomuxc@4103D000 {
compatible = "fsl,imx7ulp-iomuxc-0";
reg = <0x4103D000 0x1000>;
fsl,mux_mask = <0xf00>;
status = "disabled";
};
iomuxc1: iomuxc1@40ac0000 {
compatible = "fsl,imx7ulp-iomuxc-1";
iomuxc1: pinctrl@40ac0000 {
compatible = "fsl,imx7ulp-iomuxc1";
reg = <0x40ac0000 0x1000>;
fsl,mux_mask = <0xf00>;
};
gpio4: gpio@4103f000 {
compatible = "fsl,imx7ulp-gpio";
reg = <0x4103f000 0x1000 0x4100F000 0x40>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&iomuxc 0 0 32>;
};
gpio5: gpio@41040000 {
compatible = "fsl,imx7ulp-gpio";
reg = <0x41040000 0x1000 0x4100F040 0x40>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&iomuxc 0 32 32>;
};
gpio0: gpio@40ae0000 {
compatible = "fsl,imx7ulp-gpio";
reg = <0x40ae0000 0x1000 0x400F0000 0x40>;
gpio_ptc: gpio@40ae0000 {
compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc1 0 0 32>;
clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
<&pcc3 IMX7ULP_CLK_PCTLC>;
clock-names = "gpio", "port";
gpio-ranges = <&iomuxc1 0 0 20>;
};
gpio1: gpio@40af0000 {
compatible = "fsl,imx7ulp-gpio";
reg = <0x40af0000 0x1000 0x400F0040 0x40>;
gpio_ptd: gpio@40af0000 {
compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
reg = <0x40af0000 0x1000 0x400f0040 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc1 0 32 32>;
clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
<&pcc3 IMX7ULP_CLK_PCTLD>;
clock-names = "gpio", "port";
gpio-ranges = <&iomuxc1 0 32 12>;
};
gpio2: gpio@40b00000 {
compatible = "fsl,imx7ulp-gpio";
reg = <0x40b00000 0x1000 0x400F0080 0x40>;
gpio_pte: gpio@40b00000 {
compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
reg = <0x40b00000 0x1000 0x400f0080 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc1 0 64 32>;
clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
<&pcc3 IMX7ULP_CLK_PCTLE>;
clock-names = "gpio", "port";
gpio-ranges = <&iomuxc1 0 64 16>;
};
gpio3: gpio@40b10000 {
compatible = "fsl,imx7ulp-gpio";
reg = <0x40b10000 0x1000 0x400F00c0 0x40>;
gpio_ptf: gpio@40b10000 {
compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc1 0 96 32>;
clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
<&pcc3 IMX7ULP_CLK_PCTLF>;
clock-names = "gpio", "port";
gpio-ranges = <&iomuxc1 0 96 20>;
};
};
pmc0: pmc0@410a1000 {
compatible = "fsl,imx7ulp-pmc0";
reg = <0x410a1000 0x1000>;
};
m4aips1: bus@41080000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x41080000 0x80000>;
ranges;
sim: sim@410a3000 {
compatible = "fsl,imx7ulp-sim", "syscon";
reg = <0x410a3000 0x1000>;
};
qspi1: qspi@410A5000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx7ulp-qspi";
reg = <0x410A5000 0x10000>, <0xC0000000 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_DUMMY>,
<&clks IMX7ULP_CLK_DUMMY>;
clock-names = "qspi_en", "qspi";
status = "disabled";
};
gpu: gpu@41800000 {
compatible = "fsl,imx6q-gpu";
reg = <0x41800000 0x80000>, <0x41880000 0x80000>,
<0x60000000 0x40000000>, <0x0 0x4000000>;
reg-names = "iobase_3d", "iobase_2d",
"phys_baseaddr", "contiguous_mem";
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_3d", "irq_2d";
clocks = <&clks IMX7ULP_CLK_GPU3D>,
<&clks IMX7ULP_CLK_NIC1_DIV>,
<&clks IMX7ULP_CLK_GPU_DIV>,
<&clks IMX7ULP_CLK_GPU2D>,
<&clks IMX7ULP_CLK_NIC1_DIV>,
<&clks IMX7ULP_CLK_NIC1_DIV>;
clock-names = "gpu3d_clk", "gpu3d_shader_clk",
"gpu3d_axi_clk", "gpu2d_clk",
"gpu2d_shader_clk", "gpu2d_axi_clk";
ocotp: efuse@410a6000 {
compatible = "fsl,imx7ulp-ocotp", "syscon";
reg = <0x410a6000 0x4000>;
clocks = <&scg1 IMX7ULP_CLK_DUMMY>;
};
};
imx_ion {
compatible = "fsl,mxc-ion";
fsl,heap-id = <0>;
};
};

16
arch/arm/dts/imx8mm-evk-u-boot.dtsi
View file

@ -20,6 +20,10 @@
};
};
&aips4 {
u-boot,dm-spl;
};
&reg_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
};
@ -84,6 +88,18 @@
u-boot,dm-spl;
};
&usbmisc1 {
u-boot,dm-spl;
};
&usbphynop1 {
u-boot,dm-spl;
};
&usbotg1 {
u-boot,dm-spl;
};
&usdhc1 {
u-boot,dm-spl;
};

21
arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi → arch/arm/dts/imx8mm-kontron-bl-common-u-boot.dtsi
View file

@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0+
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2019 Kontron Electronics GmbH
*/
@ -41,7 +41,6 @@
u-boot,dm-spl;
};
&i2c1 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
@ -49,8 +48,17 @@
&i2c2 {
status = "okay";
u-boot,dm-spl;
u-boot,dm-pre-reloc;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
};
&iomuxc {
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
};
&pinctrl_ecspi1 {
@ -63,11 +71,6 @@
&pinctrl_pmic {
u-boot,dm-spl;
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
/* Disable Pullup for SD_VSEL */
MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x41
>;
};
&pinctrl_uart3 {

14
arch/arm/dts/imx8mm-kontron-bl-osm-s-u-boot.dtsi Normal file
View file

@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2022 Kontron Electronics GmbH
*/
#include "imx8mm-kontron-bl-common-u-boot.dtsi"
&iomuxc {
pinctrl_touch: touchgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 /* Touch Reset */
>;
};
};

376
arch/arm/dts/imx8mm-kontron-bl-osm-s.dts Normal file
View file

@ -0,0 +1,376 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2022 Kontron Electronics GmbH
*/
/dts-v1/;
#include "imx8mm-kontron-osm-s.dtsi"
/ {
model = "Kontron BL i.MX8MM OSM-S (N802X S)";
compatible = "kontron,imx8mm-bl-osm-s", "kontron,imx8mm-osm-s", "fsl,imx8mm";
aliases {
ethernet1 = &usbnet;
};
/* fixed crystal dedicated to mcp2542fd */
osc_can: clock-osc-can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <40000000>;
clock-output-names = "osc-can";
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led>;
led1 {
label = "led1";
gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
led2 {
label = "led2";
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
};
led3 {
label = "led3";
gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
};
};
pwm-beeper {
compatible = "pwm-beeper";
pwms = <&pwm2 0 5000 0>;
};
reg_rst_eth2: regulator-rst-eth2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_eth2>;
gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
regulator-name = "rst-usb-eth2";
};
reg_usb1_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb1_vbus>;
gpio = <&gpio3 25 GPIO_ACTIVE_LOW>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "usb1-vbus";
};
reg_vdd_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "vdd-5v";
};
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
can@0 {
compatible = "microchip,mcp251xfd";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can>;
clocks = <&osc_can>;
interrupts-extended = <&gpio4 28 IRQ_TYPE_LEVEL_LOW>;
/*
* Limit the SPI clock to 15 MHz to prevent issues
* with corrupted data due to chip errata.
*/
spi-max-frequency = <15000000>;
vdd-supply = <&reg_vdd_3v3>;
xceiver-supply = <&reg_vdd_5v>;
};
};
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
status = "okay";
eeram@0 {
compatible = "microchip,48l640";
reg = <0>;
spi-max-frequency = <20000000>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-connection-type = "rgmii-rxid";
phy-handle = <&ethphy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@0 {
reg = <0>;
reset-assert-us = <1>;
reset-deassert-us = <15000>;
reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
};
};
};
&gpio1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1>;
gpio-line-names = "", "", "", "dio1-out", "", "", "dio1-in", "dio2-out",
"dio2-in", "dio3-out", "dio3-in", "dio4-out", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio5>;
gpio-line-names = "", "", "dio4-in", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
linux,rs485-enabled-at-boot-time;
uart-has-rtscts;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
disable-over-current;
vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
usb1@1 {
compatible = "usb424,9514";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
usbnet: ethernet@1 {
compatible = "usb424,ec00";
reg = <1>;
local-mac-address = [ 00 00 00 00 00 00 ];
};
};
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
vmmc-supply = <&reg_vdd_3v3>;
vqmmc-supply = <&reg_nvcc_sd>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
status = "okay";
};
&iomuxc {
pinctrl_can: cangrp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19
>;
};
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82
MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82
MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82
MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 /* PHY RST */
MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* ETH IRQ */
>;
};
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19
MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19
>;
};
pinctrl_gpio1: gpio1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19
>;
};
pinctrl_gpio5: gpio5grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19
>;
};
pinctrl_reg_usb1_vbus: regusb1vbusgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140
MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140
MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140
MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
>;
};
pinctrl_usb_eth2: usbeth2grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
};

14
arch/arm/dts/imx8mm-kontron-bl-u-boot.dtsi Normal file
View file

@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2022 Kontron Electronics GmbH
*/
#include "imx8mm-kontron-bl-common-u-boot.dtsi"
&iomuxc {
pinctrl_touch: touchgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* Touch Reset */
>;
};
};

9
arch/arm/dts/imx8mm-kontron-n801x-s.dts → arch/arm/dts/imx8mm-kontron-bl.dts
View file

@ -5,11 +5,11 @@
/dts-v1/;
#include "imx8mm-kontron-n801x-som.dtsi"
#include "imx8mm-kontron-sl.dtsi"
/ {
model = "Kontron i.MX8MM N801X S";
compatible = "kontron,imx8mm-n801x-s", "kontron,imx8mm-n801x-som", "fsl,imx8mm";
model = "Kontron BL i.MX8MM (N801X S)";
compatible = "kontron,imx8mm-bl", "kontron,imx8mm-sl", "fsl,imx8mm";
aliases {
ethernet1 = &usbnet;
@ -321,6 +321,7 @@
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
@ -333,6 +334,7 @@
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
@ -345,6 +347,7 @@
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
};

6
arch/arm/dts/imx8mm-kontron-n801x-s-lvds-u-boot.dtsi
View file

@ -1,6 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Kontron Electronics GmbH
*/
#include "imx8mm-kontron-n801x-u-boot.dtsi"

117
arch/arm/dts/imx8mm-kontron-n801x-s-lvds.dts
View file

@ -1,117 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Kontron Electronics GmbH
*/
#include "imx8mm-kontron-n801x-s.dts"
/ {
model = "Kontron i.MX8MM N801X S LVDS";
compatible = "kontron,imx8mm-n801x-s-lvds", "fsl,imx8mm";
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 50000>; /* period = 5000000 ns => f = 200 Hz */
power-supply = <&reg_vdd_24v>;
brightness-levels = <0 100>;
num-interpolated-steps = <100>;
default-brightness-level = <100>;
status = "okay";
};
reg_panel_pwr: regpanel-pwr {
compatible = "regulator-fixed";
regulator-name = "reg_panel_pwr";
regulator-always-on;
gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_panel_rst: regpanel-rst {
compatible = "regulator-fixed";
regulator-name = "reg_panel_rst";
regulator-always-on;
gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_panel_stby: regpanel-stby {
compatible = "regulator-fixed";
regulator-name = "reg_panel_stby";
regulator-always-on;
gpio = <&gpio3 21 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_panel_hinv: regpanel-hinv {
compatible = "regulator-fixed";
regulator-name = "reg_panel_hinv";
regulator-always-on;
gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_panel_vinv: regpanel-vinv {
compatible = "regulator-fixed";
regulator-name = "reg_panel_vinv";
gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vdd_24v: regulator-24v {
compatible = "regulator-fixed";
regulator-name = "reg-vdd-24v";
regulator-min-microvolt = <24000000>;
regulator-max-microvolt = <24000000>;
regulator-boot-on;
regulator-always-on;
status = "okay";
};
};
&i2c2 {
status = "okay";
gt911@5d {
compatible = "goodix,gt928";
reg = <0x5d>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touch>;
interrupt-parent = <&gpio3>;
interrupts = <22 8>;
reset-gpios = <&gpio3 23 0>;
irq-gpios = <&gpio3 22 0>;
};
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
#pwm-cells = <2>;
status = "okay";
};
&iomuxc {
pinctrl_panel: panelgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 /* TFT-PWR - family */
MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 /* RESET family */
MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 /* STBY family */
MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x19 /* HINV panel */
MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 /* VINV panel */
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x6
>;
};
pinctrl_touch: touchgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 /* Touch Interrupt */
MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 /* Touch Reset */
>;
};
};

6
arch/arm/dts/imx8mm-kontron-n801x-s-u-boot.dtsi
View file

@ -1,6 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Kontron Electronics GmbH
*/
#include "imx8mm-kontron-n801x-u-boot.dtsi"

330
arch/arm/dts/imx8mm-kontron-osm-s.dtsi Normal file
View file

@ -0,0 +1,330 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2022 Kontron Electronics GmbH
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx8mm.dtsi"
/ {
model = "Kontron OSM-S i.MX8MM (N802X SOM)";
compatible = "kontron,imx8mm-osm-s", "fsl,imx8mm";
memory@40000000 {
device_type = "memory";
/*
* There are multiple SoM flavors with different DDR sizes.
* The smallest is 1GB. For larger sizes the bootloader will
* update the reg property.
*/
reg = <0x0 0x40000000 0 0x80000000>;
};
chosen {
stdout-path = &uart3;
};
};
&A53_0 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_1 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_2 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_3 {
cpu-supply = <&reg_vdd_arm>;
};
&ddrc {
operating-points-v2 = <&ddrc_opp_table>;
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-100M {
opp-hz = /bits/ 64 <100000000>;
};
opp-750M {
opp-hz = /bits/ 64 <750000000>;
};
};
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
flash@0 {
compatible = "mxicy,mx25r1635f", "jedec,spi-nor";
spi-max-frequency = <80000000>;
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0x1e0000>;
};
partition@1e0000 {
label = "env";
reg = <0x1e0000 0x10000>;
};
partition@1f0000 {
label = "env_redundant";
reg = <0x1f0000 0x10000>;
};
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pca9450: pmic@25 {
compatible = "nxp,pca9450a";
reg = <0x25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
regulators {
reg_vdd_soc: BUCK1 {
regulator-name = "+0V8_VDD_SOC (BUCK1)";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <850000>;
nxp,dvs-standby-voltage = <800000>;
};
reg_vdd_arm: BUCK2 {
regulator-name = "+0V9_VDD_ARM (BUCK2)";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <950000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
};
reg_vdd_dram: BUCK3 {
regulator-name = "+0V9_VDD_DRAM&PU (BUCK3)";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <950000>;
regulator-boot-on;
regulator-always-on;
};
reg_vdd_3v3: BUCK4 {
regulator-name = "+3V3 (BUCK4)";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_vdd_1v8: BUCK5 {
regulator-name = "+1V8 (BUCK5)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_nvcc_dram: BUCK6 {
regulator-name = "+1V1_NVCC_DRAM (BUCK6)";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
reg_nvcc_snvs: LDO1 {
regulator-name = "+1V8_NVCC_SNVS (LDO1)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_vdd_snvs: LDO2 {
regulator-name = "+0V8_VDD_SNVS (LDO2)";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
reg_vdda: LDO3 {
regulator-name = "+1V8_VDDA (LDO3)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_vdd_phy: LDO4 {
regulator-name = "+0V9_VDD_PHY (LDO4)";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
reg_nvcc_sd: LDO5 {
regulator-name = "NVCC_SD (LDO5)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
};
};
rtc@52 {
compatible = "microcrystal,rv3028";
reg = <0x52>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
interrupts-extended = <&gpio4 1 IRQ_TYPE_LEVEL_HIGH>;
trickle-diode-disable;
};
};
&uart3 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
vmmc-supply = <&reg_vdd_3v3>;
vqmmc-supply = <&reg_vdd_1v8>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};

53
arch/arm/dts/imx8mm-kontron-n801x-som.dtsi → arch/arm/dts/imx8mm-kontron-sl.dtsi
View file

@ -6,8 +6,8 @@
#include "imx8mm.dtsi"
/ {
model = "Kontron i.MX8MM N801X SoM";
compatible = "kontron,imx8mm-n801x-som", "fsl,imx8mm";
model = "Kontron SL i.MX8MM (N801X SOM)";
compatible = "kontron,imx8mm-sl", "fsl,imx8mm";
memory@40000000 {
device_type = "memory";
@ -46,10 +46,6 @@
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-hz = /bits/ 64 <100000000>;
};
@ -70,6 +66,27 @@
compatible = "mxicy,mx25r1635f", "jedec,spi-nor";
spi-max-frequency = <80000000>;
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0x1e0000>;
};
partition@1e0000 {
label = "env";
reg = <0x1e0000 0x10000>;
};
partition@1f0000 {
label = "env_redundant";
reg = <0x1f0000 0x10000>;
};
};
};
};
@ -86,11 +103,10 @@
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
regulators {
reg_vdd_soc: BUCK1 {
regulator-name = "buck1";
regulator-name = "+0V8_VDD_SOC (BUCK1)";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
@ -101,7 +117,7 @@
};
reg_vdd_arm: BUCK2 {
regulator-name = "buck2";
regulator-name = "+0V9_VDD_ARM (BUCK2)";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <950000>;
regulator-boot-on;
@ -112,7 +128,7 @@
};
reg_vdd_dram: BUCK3 {
regulator-name = "buck3";
regulator-name = "+0V9_VDD_DRAM&PU (BUCK3)";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <950000>;
regulator-boot-on;
@ -120,7 +136,7 @@
};
reg_vdd_3v3: BUCK4 {
regulator-name = "buck4";
regulator-name = "+3V3 (BUCK4)";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
@ -128,7 +144,7 @@
};
reg_vdd_1v8: BUCK5 {
regulator-name = "buck5";
regulator-name = "+1V8 (BUCK5)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
@ -136,7 +152,7 @@
};
reg_nvcc_dram: BUCK6 {
regulator-name = "buck6";
regulator-name = "+1V1_NVCC_DRAM (BUCK6)";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
@ -144,7 +160,7 @@
};
reg_nvcc_snvs: LDO1 {
regulator-name = "ldo1";
regulator-name = "+1V8_NVCC_SNVS (LDO1)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
@ -152,7 +168,7 @@
};
reg_vdd_snvs: LDO2 {
regulator-name = "ldo2";
regulator-name = "+0V8_VDD_SNVS (LDO2)";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
@ -160,7 +176,7 @@
};
reg_vdda: LDO3 {
regulator-name = "ldo3";
regulator-name = "+1V8_VDDA (LDO3)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
@ -168,7 +184,7 @@
};
reg_vdd_phy: LDO4 {
regulator-name = "ldo4";
regulator-name = "+0V9_VDD_PHY (LDO4)";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
@ -176,7 +192,7 @@
};
reg_nvcc_sd: LDO5 {
regulator-name = "ldo5";
regulator-name = "NVCC_SD (LDO5)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
@ -229,7 +245,6 @@
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x141
>;
};

26
arch/arm/dts/imx8mm-mx8menlo-u-boot.dtsi
View file

@ -6,7 +6,7 @@
/ {
chosen {
stdout-path = &uart2;
stdout-path = &uart1;
};
aliases {
@ -17,22 +17,26 @@
};
};
&aips4 {
u-boot,dm-spl;
};
&i2c4 {
/delete-node/ codec@1a;
};
&pinctrl_uart1 {
/delete-property/ u-boot,dm-spl;
};
&pinctrl_uart2 {
&reg_usb_otg1_vbus {
u-boot,dm-spl;
};
&uart1 {
/delete-property/ u-boot,dm-spl;
};
&uart2 {
&usbmisc1 {
u-boot,dm-spl;
};
&usbphynop1 {
u-boot,dm-spl;
};
&usbotg1 {
u-boot,dm-spl;
};

3
arch/arm/dts/imx8mm-venice-gw7902.dts
View file

@ -742,6 +742,9 @@
MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */
MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000041 /* LTE_INT */
MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000041 /* LTE_RST# */
MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000041 /* LTE_PWR */
MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */
MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */
MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */

14
arch/arm/dts/imx8mm-venice-gw7903-u-boot.dtsi
View file

@ -43,6 +43,20 @@
line-name = "dig2_out#";
};
dig2ctl {
gpio-hog;
output-low;
gpios = <2 GPIO_ACTIVE_HIGH>;
line-name = "dig2_ctl";
};
dig1ctl {
gpio-hog;
output-low;
gpios = <6 GPIO_ACTIVE_HIGH>;
line-name = "dig1_ctl";
};
dig1out {
gpio-hog;
output-high;

4
arch/arm/dts/imx8mm-venice-gw7903.dts
View file

@ -250,7 +250,7 @@
};
&gpio2 {
gpio-line-names = "dig2_in", "dig2_out#", "", "", "", "", "", "",
gpio-line-names = "dig2_in", "dig2_out#", "dig2_ctl", "", "", "", "dig1_ctl", "",
"dig1_out#", "dig1_in", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
@ -630,6 +630,8 @@
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */
MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x40000041 /* DIG1_IN */
MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* DIG1_OUT */
MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40000041 /* DIG1_CTL */
MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x40000041 /* DIG2_CTL */
MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000041 /* DIG2_IN */
MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000041 /* DIG2_OUT */
MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x40000041 /* SIM1DET# */

46
arch/arm/dts/imx8mm-venice-gw7904-u-boot.dtsi Normal file
View file

@ -0,0 +1,46 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2022 Gateworks Corporation
*/
#include "imx8mm-venice-u-boot.dtsi"
&gpio1 {
rs232en {
gpio-hog;
output-low;
gpios = <12 GPIO_ACTIVE_HIGH>;
line-name = "rs232_en#";
};
};
&gpio5 {
pci_wdis {
gpio-hog;
output-high;
gpios = <12 GPIO_ACTIVE_HIGH>;
line-name = "pci_wdis#";
};
};
&fec1 {
phy-reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
phy-reset-post-delay = <300>;
};
&pinctrl_fec1 {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
u-boot,dm-spl;
};
&pinctrl_pmic {
u-boot,dm-spl;
};

884
arch/arm/dts/imx8mm-venice-gw7904.dts Normal file
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Gateworks Corporation
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mm.dtsi"
/ {
model = "Gateworks Venice GW7904 i.MX8MM board";
compatible = "gateworks,imx8mm-gw7904", "fsl,imx8mm";
chosen {
stdout-path = &uart2;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
gpio-keys {
compatible = "gpio-keys";
key-0 {
label = "user_pb";
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
key-1 {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-2 {
label = "key_erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
key-3 {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
key-4 {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
led-controller {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led-0 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
label = "led01_grn";
gpios = <&gpioled 0 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led-1 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_YELLOW>;
label = "led01_yel";
gpios = <&gpioled 1 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led-2 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
label = "led02_grn";
gpios = <&gpioled 2 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led-3 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_YELLOW>;
label = "led02_yel";
gpios = <&gpioled 3 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led-4 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
label = "led03_grn";
gpios = <&gpioled 4 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led-5 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_YELLOW>;
label = "led03_yel";
gpios = <&gpioled 5 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led-6 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
label = "led04_grn";
gpios = <&gpioled 6 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led-7 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_YELLOW>;
label = "led04_yel";
gpios = <&gpioled 7 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led-8 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
label = "led05_grn";
gpios = <&gpioled 8 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led-9 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_YELLOW>;
label = "led05_yel";
gpios = <&gpioled 9 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led-10 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
label = "led06_grn";
gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led-11 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
label = "led06_red";
gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led-12 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
label = "led07_grn";
gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led-13 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
label = "led07_red";
gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led-14 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
label = "led08_grn";
gpios = <&gpioled 10 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led-15 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_YELLOW>;
label = "led08_yel";
gpios = <&gpioled 11 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led-16 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
label = "led09_grn";
gpios = <&gpioled 12 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led-17 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_YELLOW>;
label = "led09_yel";
gpios = <&gpioled 13 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led-18 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
label = "led10_grn";
gpios = <&gpioled 14 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led-19 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_YELLOW>;
label = "led10_yel";
gpios = <&gpioled 15 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
&A53_0 {
cpu-supply = <&buck2>;
};
&A53_1 {
cpu-supply = <&buck2>;
};
&A53_2 {
cpu-supply = <&buck2>;
};
&A53_3 {
cpu-supply = <&buck2>;
};
&ddrc {
operating-points-v2 = <&ddrc_opp_table>;
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-hz = /bits/ 64 <100000000>;
};
opp-750M {
opp-hz = /bits/ 64 <750000000>;
};
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
local-mac-address = [00 00 00 00 00 00];
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
};
&gpio1 {
gpio-line-names = "", "", "", "", "", "", "", "",
"", "", "", "", "rs232_en#", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio5 {
gpio-line-names = "", "", "", "", "", "", "", "",
"", "", "", "", "pci_wdis#", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
pinctrl-0 = <&pinctrl_gsc>;
interrupt-parent = <&gpio4>;
interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <1>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@6 {
gw,mode = <0>;
reg = <0x06>;
label = "temp";
};
channel@82 {
gw,mode = <2>;
reg = <0x82>;
label = "vin";
gw,voltage-divider-ohms = <22100 1000>;
gw,voltage-offset-microvolt = <700000>;
};
channel@84 {
gw,mode = <2>;
reg = <0x84>;
label = "vdd_5p0";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@86 {
gw,mode = <2>;
reg = <0x86>;
label = "vdd_3p3";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@88 {
gw,mode = <2>;
reg = <0x88>;
label = "vdd_0p9";
};
channel@8c {
gw,mode = <2>;
reg = <0x8c>;
label = "vdd_soc";
};
channel@8e {
gw,mode = <2>;
reg = <0x8e>;
label = "vdd_arm";
};
channel@90 {
gw,mode = <2>;
reg = <0x90>;
label = "vdd_1p8";
};
channel@92 {
gw,mode = <2>;
reg = <0x92>;
label = "vdd_dram";
};
channel@a2 {
gw,mode = <2>;
reg = <0xa2>;
label = "vdd_gsc";
gw,voltage-divider-ohms = <10000 10000>;
};
};
};
gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
};
eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
rtc@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
pmic@4b {
compatible = "rohm,bd71847";
reg = <0x4b>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio3>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
rohm,reset-snvs-powered;
#clock-cells = <0>;
clocks = <&osc_32k 0>;
clock-output-names = "clk-32k-out";
regulators {
/* vdd_soc: 0.805-0.900V (typ=0.8V) */
BUCK1 {
regulator-name = "buck1";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
};
/* vdd_arm: 0.805-1.0V (typ=0.9V) */
buck2: BUCK2 {
regulator-name = "buck2";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <1000000>;
rohm,dvs-idle-voltage = <900000>;
};
/* vdd_0p9: 0.805-1.0V (typ=0.9V) */
BUCK3 {
regulator-name = "buck3";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
/* vdd_3p3 */
BUCK4 {
regulator-name = "buck4";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
/* vdd_1p8 */
BUCK5 {
regulator-name = "buck5";
regulator-min-microvolt = <1605000>;
regulator-max-microvolt = <1995000>;
regulator-boot-on;
regulator-always-on;
};
/* vdd_dram */
BUCK6 {
regulator-name = "buck6";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
regulator-always-on;
};
/* nvcc_snvs_1p8 */
LDO1 {
regulator-name = "ldo1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1900000>;
regulator-boot-on;
regulator-always-on;
};
/* vdd_snvs_0p8 */
LDO2 {
regulator-name = "ldo2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
/* vdda_1p8 */
LDO3 {
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
LDO4 {
regulator-name = "ldo4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
LDO6 {
regulator-name = "ldo6";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
accelerometer@19 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_accel>;
compatible = "st,lis2de12";
reg = <0x19>;
st,drdy-int-pin = <1>;
interrupt-parent = <&gpio1>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "INT1";
};
};
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
gpioled: gpio@27 {
compatible = "nxp,pca9555";
reg = <0x27>;
gpio-controller;
#gpio-cells = <2>;
};
};
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,clkreq-unsupported;
clocks = <&pcie0_refclk>;
clock-names = "ref";
status = "okay";
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
status = "okay";
};
/* off-board RS232 */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* console */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
/* off-board RS232 */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usbotg1 {
dr_mode = "host";
disable-over-current;
status = "okay";
};
/* microSD */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
/* eMMC */
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */
MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */
>;
};
pinctrl_accel: accelgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x159
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x19 /* IRQ# */
MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* RST# */
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000019
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000019
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000019
MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000019
>;
};
pinctrl_gsc: gscgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x159
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
>;
};
pinctrl_pcie0: pciegrp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
>;
};
pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};

180
arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
View file

@ -1,24 +1,9 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2020 Compass Electronics Group, LLC
* Copyright 2022 Logic PD, Inc. dba Beacon EmbeddedWorks
*/
/ {
binman: binman {
multiple-images;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
u-boot,dm-spl;
};
};
&{/soc@0} {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
#include "imx8mn-u-boot.dtsi"
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
u-boot,dm-spl;
@ -28,27 +13,6 @@
u-boot,dm-spl;
};
&aips1 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&aips2 {
u-boot,dm-spl;
};
&aips3 {
u-boot,dm-spl;
};
&clk {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&gpio1 {
u-boot,dm-spl;
};
@ -61,15 +25,6 @@
u-boot,dm-spl;
};
&iomuxc {
u-boot,dm-spl;
};
&osc_24m {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&pca6416_0 {
compatible = "ti,tca6416";
};
@ -106,10 +61,6 @@
u-boot,off-on-delay-us = <20000>;
};
&spba1 {
u-boot,dm-spl;
};
&uart2 {
u-boot,dm-spl;
};
@ -132,133 +83,6 @@
mmc-hs400-enhanced-strobe;
};
&wdog1 {
u-boot,dm-spl;
};
&pinctrl_wdog {
u-boot,dm-spl;
};
&binman {
u-boot-spl-ddr {
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
align-size = <4>;
align = <4>;
u-boot-spl {
align-end = <4>;
};
ddr-1d-imem-fw {
filename = "lpddr4_pmu_train_1d_imem.bin";
type = "blob-ext";
align-end = <4>;
};
ddr-1d-dmem-fw {
filename = "lpddr4_pmu_train_1d_dmem.bin";
type = "blob-ext";
align-end = <4>;
};
ddr-2d-imem-fw {
filename = "lpddr4_pmu_train_2d_imem.bin";
type = "blob-ext";
align-end = <4>;
};
ddr-2d-dmem-fw {
filename = "lpddr4_pmu_train_2d_dmem.bin";
type = "blob-ext";
align-end = <4>;
};
};
spl {
filename = "spl.bin";
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";
blob {
filename = "u-boot-spl-ddr.bin";
};
};
};
itb {
filename = "u-boot.itb";
fit {
description = "Configuration to load ATF before U-Boot";
#address-cells = <1>;
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
images {
uboot {
description = "U-Boot (64-bit)";
type = "standalone";
arch = "arm64";
compression = "none";
load = <CONFIG_SYS_TEXT_BASE>;
uboot_blob: blob-ext {
filename = "u-boot-nodtb.bin";
};
};
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
load = <0x960000>;
entry = <0x960000>;
atf_blob: blob-ext {
filename = "bl31.bin";
};
};
fdt {
description = "NAME";
type = "flat_dt";
compression = "none";
uboot_fdt_blob: blob-ext {
filename = "u-boot.dtb";
};
};
};
configurations {
default = "conf";
conf {
description = "NAME";
firmware = "uboot";
loadables = "atf";
fdt = "fdt";
};
};
};
};
imx-boot {
filename = "flash.bin";
pad-byte = <0x00>;
spl: blob-ext@1 {
offset = <0x0>;
filename = "spl.bin";
};
uboot: blob-ext@2 {
offset = <0x58000>;
filename = "u-boot.itb";
};
};
};

172
arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
View file

@ -4,22 +4,7 @@
* Copyright 2021 BSH Hausgeraete GmbH
*/
/ {
binman: binman {
multiple-images;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
u-boot,dm-spl;
};
};
&{/soc@0} {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
#include "imx8mn-u-boot.dtsi"
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
u-boot,dm-spl;
@ -29,27 +14,6 @@
u-boot,dm-spl;
};
&aips1 {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&aips3 {
u-boot,dm-spl;
};
&aips4 {
u-boot,dm-spl;
};
&clk {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&gpio1 {
u-boot,dm-spl;
};
@ -66,15 +30,6 @@
u-boot,dm-spl;
};
&iomuxc {
u-boot,dm-spl;
};
&osc_24m {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&pinctrl_i2c1 {
u-boot,dm-spl;
};
@ -98,128 +53,3 @@
&wdog1 {
u-boot,dm-spl;
};
&binman {
u-boot-spl-ddr {
align = <4>;
align-size = <4>;
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
u-boot-spl {
align-end = <4>;
filename = "u-boot-spl.bin";
};
ddr-1d-imem-fw {
filename = "ddr3_imem_1d.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-1d-dmem-fw {
filename = "ddr3_dmem_1d.bin";
align-end = <4>;
type = "blob-ext";
};
};
spl {
filename = "spl.bin";
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";
blob {
filename = "u-boot-spl-ddr.bin";
};
};
};
itb {
filename = "u-boot.itb";
fit {
description = "Configuration to load ATF before U-Boot";
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
fit,fdt-list = "of-list";
#address-cells = <1>;
images {
uboot {
arch = "arm64";
compression = "none";
description = "U-Boot (64-bit)";
load = <CONFIG_SYS_TEXT_BASE>;
type = "standalone";
uboot_blob {
filename = "u-boot-nodtb.bin";
type = "blob-ext";
};
};
atf {
arch = "arm64";
compression = "none";
description = "ARM Trusted Firmware";
entry = <0x960000>;
load = <0x960000>;
type = "firmware";
atf_blob {
filename = "bl31.bin";
type = "atf-bl31";
};
};
binman_fip: fip {
arch = "arm64";
compression = "none";
description = "Trusted Firmware FIP";
load = <0x40310000>;
type = "firmware";
};
@fdt-SEQ {
compression = "none";
description = "NAME";
type = "flat_dt";
uboot_fdt_blob {
filename = "u-boot.dtb";
type = "blob-ext";
};
};
};
configurations {
default = "@config-DEFAULT-SEQ";
binman_configuration: @config-SEQ {
description = "NAME";
fdt = "fdt-SEQ";
firmware = "uboot";
loadables = "atf";
};
};
};
};
imx-boot {
filename = "flash.bin";
pad-byte = <0x00>;
spl {
filename = "spl.bin";
offset = <0x0>;
type = "blob-ext";
};
binman_uboot: uboot {
filename = "u-boot.itb";
offset = <0x58000>;
type = "blob-ext";
};
};
};

184
arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
View file

@ -3,62 +3,7 @@
* Copyright 2019, 2021 NXP
*/
/ {
binman: binman {
multiple-images;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
u-boot,dm-spl;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
};
&{/soc@0} {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&spba1 {
u-boot,dm-spl;
};
&clk {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&osc_24m {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&aips1 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&aips2 {
u-boot,dm-spl;
};
&aips3 {
u-boot,dm-spl;
};
&iomuxc {
u-boot,dm-spl;
};
#include "imx8mn-u-boot.dtsi"
&pinctrl_reg_usdhc2_vmmc {
u-boot,dm-spl;
@ -143,130 +88,3 @@
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
};
&wdog1 {
u-boot,dm-spl;
};
&binman {
u-boot-spl-ddr {
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
align-size = <4>;
align = <4>;
u-boot-spl {
align-end = <4>;
};
ddr-1d-imem-fw {
filename = "ddr4_imem_1d_201810.bin";
type = "blob-ext";
align-end = <4>;
};
ddr-1d-dmem-fw {
filename = "ddr4_dmem_1d_201810.bin";
type = "blob-ext";
align-end = <4>;
};
ddr-2d-imem-fw {
filename = "ddr4_imem_2d_201810.bin";
type = "blob-ext";
align-end = <4>;
};
ddr-2d-dmem-fw {
filename = "ddr4_dmem_2d_201810.bin";
type = "blob-ext";
align-end = <4>;
};
};
spl {
filename = "spl.bin";
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";
blob {
filename = "u-boot-spl-ddr.bin";
};
};
};
itb {
filename = "u-boot.itb";
fit {
description = "Configuration to load ATF before U-Boot";
#address-cells = <1>;
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
images {
uboot {
description = "U-Boot (64-bit)";
type = "standalone";
arch = "arm64";
compression = "none";
load = <CONFIG_SYS_TEXT_BASE>;
uboot_blob: blob-ext {
filename = "u-boot-nodtb.bin";
};
};
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
load = <0x960000>;
entry = <0x960000>;
atf_blob: blob-ext {
filename = "bl31.bin";
};
};
fdt {
description = "NAME";
type = "flat_dt";
compression = "none";
uboot_fdt_blob: blob-ext {
filename = "u-boot.dtb";
};
};
};
configurations {
default = "conf";
conf {
description = "NAME";
firmware = "uboot";
loadables = "atf";
fdt = "fdt";
};
};
};
};
imx-boot {
filename = "flash.bin";
pad-byte = <0x00>;
spl: blob-ext@1 {
offset = <0x0>;
filename = "spl.bin";
};
uboot: blob-ext@2 {
offset = <0x58000>;
filename = "u-boot.itb";
};
};
};

108
arch/arm/dts/imx8mn-evk-u-boot.dtsi
View file

@ -24,111 +24,3 @@
&pinctrl_pmic {
u-boot,dm-spl;
};
&binman {
u-boot-spl-ddr {
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
align-size = <4>;
align = <4>;
u-boot-spl {
align-end = <4>;
};
ddr-1d-imem-fw {
filename = "lpddr4_pmu_train_1d_imem.bin";
type = "blob-ext";
align-end = <4>;
};
ddr-1d-dmem-fw {
filename = "lpddr4_pmu_train_1d_dmem.bin";
type = "blob-ext";
align-end = <4>;
};
ddr-2d-imem-fw {
filename = "lpddr4_pmu_train_2d_imem.bin";
type = "blob-ext";
align-end = <4>;
};
ddr-2d-dmem-fw {
filename = "lpddr4_pmu_train_2d_dmem.bin";
type = "blob-ext";
align-end = <4>;
};
};
spl {
filename = "spl.bin";
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";
blob {
filename = "u-boot-spl-ddr.bin";
};
};
};
itb {
filename = "u-boot.itb";
fit {
description = "Configuration to load ATF before U-Boot";
#address-cells = <1>;
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
images {
uboot {
description = "U-Boot (64-bit)";
type = "standalone";
arch = "arm64";
compression = "none";
load = <CONFIG_SYS_TEXT_BASE>;
uboot_blob: blob-ext {
filename = "u-boot-nodtb.bin";
};
};
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
load = <0x960000>;
entry = <0x960000>;
atf_blob: blob-ext {
filename = "bl31.bin";
};
};
fdt {
description = "NAME";
type = "flat_dt";
compression = "none";
uboot_fdt_blob: blob-ext {
filename = "u-boot.dtb";
};
};
};
configurations {
default = "conf";
conf {
description = "NAME";
firmware = "uboot";
loadables = "atf";
fdt = "fdt";
};
};
};
};
};

248
arch/arm/dts/imx8mn-u-boot.dtsi Normal file
View file

@ -0,0 +1,248 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2022 Logic PD, Inc dba Beacon EmbeddedWorks
*/
/ {
binman: binman {
multiple-images;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
u-boot,dm-spl;
};
};
&{/soc@0} {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&aips1 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&aips2 {
u-boot,dm-spl;
};
&aips3 {
u-boot,dm-spl;
};
&aips4 {
u-boot,dm-spl;
};
&clk {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&iomuxc {
u-boot,dm-spl;
};
&osc_24m {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&spba1 {
u-boot,dm-spl;
};
&wdog1 {
u-boot,dm-spl;
};
&binman {
u-boot-spl-ddr {
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
align-size = <4>;
align = <4>;
u-boot-spl {
align-end = <4>;
filename = "u-boot-spl.bin";
};
ddr-1d-imem-fw {
#ifdef CONFIG_IMX8M_LPDDR4
filename = "lpddr4_pmu_train_1d_imem.bin";
#elif CONFIG_IMX8M_DDR4
filename = "ddr4_imem_1d.bin";
#else
filename = "ddr3_imem_1d.bin";
#endif
type = "blob-ext";
align-end = <4>;
};
ddr-1d-dmem-fw {
#ifdef CONFIG_IMX8M_LPDDR4
filename = "lpddr4_pmu_train_1d_dmem.bin";
#elif CONFIG_IMX8M_DDR4
filename = "ddr4_dmem_1d.bin";
#else
filename = "ddr3_dmem_1d.bin";
#endif
type = "blob-ext";
align-end = <4>;
};
ddr-2d-imem-fw {
#ifdef CONFIG_IMX8M_LPDDR4
filename = "lpddr4_pmu_train_2d_imem.bin";
#elif CONFIG_IMX8M_DDR4
filename = "ddr4_imem_2d.bin";
#endif
type = "blob-ext";
align-end = <4>;
};
ddr-2d-dmem-fw {
#ifdef CONFIG_IMX8M_LPDDR4
filename = "lpddr4_pmu_train_2d_dmem.bin";
#elif CONFIG_IMX8M_DDR4
filename = "ddr4_dmem_2d.bin";
#endif
type = "blob-ext";
align-end = <4>;
};
};
spl {
filename = "spl.bin";
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";
blob {
filename = "u-boot-spl-ddr.bin";
};
};
};
itb {
filename = "u-boot.itb";
fit {
description = "Configuration to load ATF before U-Boot";
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
fit,fdt-list = "of-list";
#address-cells = <1>;
images {
uboot {
arch = "arm64";
compression = "none";
description = "U-Boot (64-bit)";
load = <CONFIG_SYS_TEXT_BASE>;
type = "standalone";
uboot-blob {
filename = "u-boot-nodtb.bin";
type = "blob-ext";
};
};
atf {
arch = "arm64";
compression = "none";
description = "ARM Trusted Firmware";
entry = <0x960000>;
load = <0x960000>;
type = "firmware";
atf-blob {
filename = "bl31.bin";
type = "atf-bl31";
};
};
binman_fip: fip {
arch = "arm64";
compression = "none";
description = "Trusted Firmware FIP";
load = <0x40310000>;
type = "firmware";
};
@fdt-SEQ {
compression = "none";
description = "NAME";
type = "flat_dt";
uboot-fdt-blob {
filename = "u-boot.dtb";
type = "blob-ext";
};
};
};
configurations {
default = "@config-DEFAULT-SEQ";
binman_configuration: @config-SEQ {
description = "NAME";
fdt = "fdt-SEQ";
firmware = "uboot";
loadables = "atf";
};
};
};
};
imx-boot {
filename = "flash.bin";
pad-byte = <0x00>;
#ifdef CONFIG_FSPI_CONF_HEADER
fspi_conf_block {
filename = CONFIG_FSPI_CONF_FILE;
type = "blob-ext";
offset = <0x400>;
};
spl {
filename = "spl.bin";
offset = <0x1000>;
type = "blob-ext";
};
binman_uboot: uboot {
filename = "u-boot.itb";
offset = <0x59000>;
type = "blob-ext";
};
#else
spl {
offset = <0x0>;
filename = "spl.bin";
type = "blob-ext";
};
binman_uboot: uboot {
offset = <0x58000>;
filename = "u-boot.itb";
type = "blob-ext";
};
#endif
};
};

188
arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
View file

@ -3,22 +3,7 @@
* Copyright 2021 Collabora Ltd.
*/
/ {
binman: binman {
multiple-images;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
u-boot,dm-spl;
};
};
&{/soc@0} {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
#include "imx8mn-u-boot.dtsi"
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
u-boot,dm-spl;
@ -28,27 +13,6 @@
u-boot,dm-spl;
};
&aips1 {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&aips3 {
u-boot,dm-spl;
};
&aips4 {
u-boot,dm-spl;
};
&clk {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&gpio1 {
u-boot,dm-spl;
};
@ -65,15 +29,6 @@
u-boot,dm-spl;
};
&iomuxc {
u-boot,dm-spl;
};
&osc_24m {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&pinctrl_i2c1 {
u-boot,dm-spl;
};
@ -113,144 +68,3 @@
&usdhc3 {
u-boot,dm-spl;
};
&wdog1 {
u-boot,dm-spl;
};
&binman {
u-boot-spl-ddr {
align = <4>;
align-size = <4>;
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
u-boot-spl {
align-end = <4>;
filename = "u-boot-spl.bin";
};
ddr-1d-imem-fw {
filename = "ddr4_imem_1d.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-1d-dmem-fw {
filename = "ddr4_dmem_1d.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-2d-imem-fw {
filename = "ddr4_imem_2d.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-2d-dmem-fw {
filename = "ddr4_dmem_2d.bin";
align-end = <4>;
type = "blob-ext";
};
};
spl {
filename = "spl.bin";
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";
blob {
filename = "u-boot-spl-ddr.bin";
};
};
};
itb {
filename = "u-boot.itb";
fit {
description = "Configuration to load ATF before U-Boot";
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
fit,fdt-list = "of-list";
#address-cells = <1>;
images {
uboot {
arch = "arm64";
compression = "none";
description = "U-Boot (64-bit)";
load = <CONFIG_SYS_TEXT_BASE>;
type = "standalone";
uboot_blob {
filename = "u-boot-nodtb.bin";
type = "blob-ext";
};
};
atf {
arch = "arm64";
compression = "none";
description = "ARM Trusted Firmware";
entry = <0x960000>;
load = <0x960000>;
type = "firmware";
atf_blob {
filename = "bl31.bin";
type = "atf-bl31";
};
};
binman_fip: fip {
arch = "arm64";
compression = "none";
description = "Trusted Firmware FIP";
load = <0x40310000>;
type = "firmware";
};
@fdt-SEQ {
compression = "none";
description = "NAME";
type = "flat_dt";
uboot_fdt_blob {
filename = "u-boot.dtb";
type = "blob-ext";
};
};
};
configurations {
default = "@config-DEFAULT-SEQ";
binman_configuration: @config-SEQ {
description = "NAME";
fdt = "fdt-SEQ";
firmware = "uboot";
loadables = "atf";
};
};
};
};
imx-boot {
filename = "flash.bin";
pad-byte = <0x00>;
spl {
filename = "spl.bin";
offset = <0x0>;
type = "blob-ext";
};
binman_uboot: uboot {
filename = "u-boot.itb";
offset = <0x58000>;
type = "blob-ext";
};
};
};

192
arch/arm/dts/imx8mn-venice-u-boot.dtsi
View file

@ -3,56 +3,7 @@
* Copyright 2022 Gateworks Corporation
*/
/ {
binman: binman {
multiple-images;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
u-boot,dm-spl;
};
};
&{/soc@0} {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&spba1 {
u-boot,dm-spl;
};
&clk {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&osc_24m {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&aips1 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&aips2 {
u-boot,dm-spl;
};
&aips3 {
u-boot,dm-spl;
};
&iomuxc {
u-boot,dm-spl;
};
#include "imx8mn-u-boot.dtsi"
&gpio1 {
u-boot,dm-spl;
@ -110,147 +61,6 @@
u-boot,dm-spl;
};
&wdog1 {
u-boot,dm-spl;
};
&pinctrl_wdog {
u-boot,dm-spl;
};
&binman {
u-boot-spl-ddr {
align = <4>;
align-size = <4>;
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
u-boot-spl {
align-end = <4>;
filename = "u-boot-spl.bin";
};
ddr-1d-imem-fw {
filename = "lpddr4_pmu_train_1d_imem.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-1d-dmem-fw {
filename = "lpddr4_pmu_train_1d_dmem.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-2d-imem-fw {
filename = "lpddr4_pmu_train_2d_imem.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-2d-dmem-fw {
filename = "lpddr4_pmu_train_2d_dmem.bin";
align-end = <4>;
type = "blob-ext";
};
};
spl {
filename = "spl.bin";
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";
blob {
filename = "u-boot-spl-ddr.bin";
};
};
};
itb {
filename = "u-boot.itb";
fit {
description = "Configuration to load ATF before U-Boot";
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
fit,fdt-list = "of-list";
#address-cells = <1>;
images {
uboot {
arch = "arm64";
compression = "none";
description = "U-Boot (64-bit)";
load = <CONFIG_SYS_TEXT_BASE>;
type = "standalone";
uboot_blob {
filename = "u-boot-nodtb.bin";
type = "blob-ext";
};
};
atf {
arch = "arm64";
compression = "none";
description = "ARM Trusted Firmware";
entry = <0x960000>;
load = <0x960000>;
type = "firmware";
atf_blob {
filename = "bl31.bin";
type = "blob-ext";
};
};
binman_fip: fip {
arch = "arm64";
compression = "none";
description = "Trusted Firmware FIP";
load = <0x40310000>;
type = "firmware";
};
@fdt-SEQ {
compression = "none";
description = "NAME";
type = "flat_dt";
uboot_fdt_blob {
filename = "u-boot.dtb";
type = "blob-ext";
};
};
};
configurations {
default = "@config-DEFAULT-SEQ";
binman_configuration: @config-SEQ {
description = "NAME";
fdt = "fdt-SEQ";
firmware = "uboot";
loadables = "atf";
};
};
};
};
imx-boot {
filename = "flash.bin";
pad-byte = <0x00>;
spl {
filename = "spl.bin";
offset = <0x0>;
type = "blob-ext";
};
binman_uboot: uboot {
filename = "u-boot.itb";
offset = <0x58000>;
type = "blob-ext";
};
};
};

149
arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi Normal file
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@ -0,0 +1,149 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
* Copyright (c) 2020 Amarula Solutons(India)
*/
#include "imx8mp-u-boot.dtsi"
/ {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
u-boot,dm-spl;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
};
&reg_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
};
&reg_usdhc2_vmmc {
u-boot,dm-spl;
};
&pinctrl_uart2 {
u-boot,dm-spl;
};
&pinctrl_usdhc2_gpio {
u-boot,dm-spl;
};
&pinctrl_usdhc2 {
u-boot,dm-spl;
};
&pinctrl_usdhc3 {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&uart2 {
u-boot,dm-spl;
};
&crypto {
u-boot,dm-spl;
};
&sec_jr0 {
u-boot,dm-spl;
};
&sec_jr1 {
u-boot,dm-spl;
};
&sec_jr2 {
u-boot,dm-spl;
};
&i2c1 {
u-boot,dm-spl;
};
&i2c2 {
u-boot,dm-spl;
};
&i2c3 {
u-boot,dm-spl;
};
&i2c4 {
u-boot,dm-spl;
};
&i2c5 {
u-boot,dm-spl;
};
&i2c6 {
u-boot,dm-spl;
};
&usdhc1 {
u-boot,dm-spl;
};
&usdhc2 {
u-boot,dm-spl;
sd-uhs-sdr104;
sd-uhs-ddr50;
no-1-8-v;
};
&usdhc3 {
u-boot,dm-spl;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
};
&wdog1 {
u-boot,dm-spl;
};
&eqos {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&ethphy0 {
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
reset-delay-us = <15000>;
reset-post-delay-us = <100000>;
};
&fec {
phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
phy-reset-duration = <15>;
phy-reset-post-delay = <100>;
};

175
arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2.dts Normal file
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@ -0,0 +1,175 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 NXP
* Copyright (c) 2019 Engicam srl
* Copyright (c) 2020 Amarula Solutons(India)
*/
/dts-v1/;
#include "imx8mp.dtsi"
#include "imx8mp-icore-mx8mp.dtsi"
#include <dt-bindings/usb/pd.h>
/ {
model = "Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit";
compatible = "engicam,icore-mx8mp-edimm2.2", "engicam,icore-mx8mp",
"fsl,imx8mp";
chosen {
stdout-path = &uart2;
};
reg_usb1_vbus: regulator-usb1 {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb1>;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "usb1_host_vbus";
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VSD_3V3";
};
};
/* Ethernet */
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-handle = <&ethphy0>;
phy-mode = "rgmii-id";
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c22";
micrel,led-mode = <0>;
reg = <7>;
};
};
};
/* console */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "host";
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
/* SDCARD */
&usdhc2 {
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
pinctrl-names = "default" ;
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x10
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x140
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
>;
};
pinctrl_reg_usb1: regusb1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x10
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
>;
};
};

186
arch/arm/dts/imx8mp-icore-mx8mp.dtsi Normal file
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@ -0,0 +1,186 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 NXP
* Copyright (c) 2019 Engicam srl
* Copyright (c) 2020 Amarula Solutons(India)
*/
/ {
compatible = "engicam,icore-mx8mp", "fsl,imx8mp";
};
&A53_0 {
cpu-supply = <&buck2>;
};
&A53_1 {
cpu-supply = <&buck2>;
};
&A53_2 {
cpu-supply = <&buck2>;
};
&A53_3 {
cpu-supply = <&buck2>;
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pca9450: pmic@25 {
compatible = "nxp,pca9450c";
interrupt-parent = <&gpio3>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
reg = <0x25>;
regulators {
buck1: BUCK1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <1000000>;
regulator-name = "BUCK1";
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1025000>;
regulator-min-microvolt = <720000>;
regulator-name = "BUCK2";
regulator-ramp-delay = <3125>;
};
buck4: BUCK4 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3600000>;
regulator-min-microvolt = <3000000>;
regulator-name = "BUCK4";
};
buck5: BUCK5 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1950000>;
regulator-min-microvolt = <1650000>;
regulator-name = "BUCK5";
};
buck6: BUCK6 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1155000>;
regulator-min-microvolt = <1045000>;
regulator-name = "BUCK6";
};
ldo1: LDO1 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1950000>;
regulator-min-microvolt = <1650000>;
regulator-name = "LDO1";
};
ldo3: LDO3 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1890000>;
regulator-min-microvolt = <1710000>;
regulator-name = "LDO3";
};
ldo5: LDO5 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
regulator-name = "LDO5";
};
};
};
};
/* EMMC */
&usdhc3 {
bus-width = <8>;
non-removable;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
status = "okay";
};
&iomuxc {
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x41
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
>;
};
};

28
arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi
View file

@ -86,21 +86,21 @@
m2_dis2_hog {
gpio-hog;
gpios = <0 GPIO_ACTIVE_LOW>;
gpios = <0 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "m2_gdis#";
};
m2rst_hog {
gpio-hog;
gpios = <6 GPIO_ACTIVE_LOW>;
gpios = <6 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "m2_rst#";
};
m2_off_hog {
gpio-hog;
gpios = <14 GPIO_ACTIVE_LOW>;
gpios = <14 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "m2_off#";
};
@ -111,34 +111,34 @@
m2_dis1_hog {
gpio-hog;
gpios = <18 GPIO_ACTIVE_LOW>;
gpios = <18 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "m2_wdis#";
};
uart_rs485_hog {
rs485_en {
gpio-hog;
gpios = <31 GPIO_ACTIVE_LOW>;
gpios = <31 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "uart_rs485";
line-name = "rs485_en";
};
};
&gpio5 {
u-boot,dm-spl;
uart_half_hog {
rs485_half {
gpio-hog;
gpios = <0 GPIO_ACTIVE_LOW>;
output-high;
line-name = "uart_half";
gpios = <0 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "rs485_hd";
};
uart_term_hog {
rs485_term {
gpio-hog;
gpios = <1 GPIO_ACTIVE_LOW>;
gpios = <1 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "uart_term";
line-name = "rs485_term";
};
};

16
arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
View file

@ -35,6 +35,10 @@
};
&crypto {
u-boot,dm-spl;
};
&eqos {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
@ -141,6 +145,18 @@
u-boot,dm-spl;
};
&sec_jr0 {
u-boot,dm-spl;
};
&sec_jr1 {
u-boot,dm-spl;
};
&sec_jr2 {
u-boot,dm-spl;
};
&uart3 {
u-boot,dm-spl;
};

8
arch/arm/dts/mxs-pinfunc.h
View file

@ -1,14 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Header providing constants for i.MX28 pinctrl bindings.
*
* Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __DT_BINDINGS_MXS_PINCTRL_H__

15
arch/arm/mach-imx/imx8m/Kconfig
View file

@ -160,6 +160,20 @@ config TARGET_IMX8MP_DH_DHCOM_PDK2
select IMX8M_LPDDR4
select SUPPORT_SPL
config TARGET_IMX8MP_ICORE_MX8MP
bool "Engicam i.Core MX8M Plus SOM"
select BINMAN
select IMX8MP
select IMX8M_LPDDR4
select SUPPORT_SPL
help
i.Core MX8M Plus is an EDIMM SOM based on NXP i.MX8MP.
i.Core MX8M Plus EDIMM2.2:
* EDIMM2.2 is a Form Factor Capacitive Evaluation Board.
* i.Core MX8M Plus needs to mount on top of EDIMM2.2 for
creating complete i.Core MX8M Plus EDIMM2.2 Starter Kit.
config TARGET_IMX8MP_EVK
bool "imx8mp LPDDR4 EVK board"
select BINMAN
@ -287,6 +301,7 @@ source "board/compulab/imx8mm-cl-iot-gate/Kconfig"
source "board/data_modul/imx8mm_edm_sbc/Kconfig"
source "board/dhelectronics/dh_imx8mp/Kconfig"
source "board/engicam/imx8mm/Kconfig"
source "board/engicam/imx8mp/Kconfig"
source "board/freescale/imx8mq_evk/Kconfig"
source "board/freescale/imx8mm_evk/Kconfig"
source "board/freescale/imx8mn_evk/Kconfig"

15
board/engicam/imx8mp/Kconfig Normal file
View file

@ -0,0 +1,15 @@
if TARGET_IMX8MP_ICORE_MX8MP
config SYS_BOARD
default "imx8mp"
config SYS_VENDOR
default "engicam"
config SYS_CONFIG_NAME
default "imx8mp_icore_mx8mp"
config IMX_CONFIG
default "board/engicam/imx8mp/imximage-lpddr4.cfg"
endif

7
board/engicam/imx8mp/MAINTAINERS Normal file
View file

@ -0,0 +1,7 @@
i.Core-MX8M-Plus-EDIMM2.2
M: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
M: Matteo Lisi <matteo.lisi@engicam.com>
S: Maintained
F: board/engicam/imx8mp
F: include/configs/imx8mp_icore_mx8mp.h
F: configs/imx8mp-icore-mx8mp-edimm2.2_defconfig

12
board/engicam/imx8mp/Makefile Normal file
View file

@ -0,0 +1,12 @@
#
# Copyright (C) 2020 Amarula Solutions(India)
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += icore_mx8mp.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
endif

73
board/engicam/imx8mp/icore_mx8mp.c Normal file
View file

@ -0,0 +1,73 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Engicam S.r.l.
* Copyright (C) 2022 Amarula Solutions(India)
*
* Authors:
* Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
* Jagan Teki <jagan@amarulasolutions.com>
*/
#include <common.h>
#include <env.h>
#include <errno.h>
#include <init.h>
#include <miiphy.h>
#include <netdev.h>
#include <linux/delay.h>
#include <asm/global_data.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm-generic/gpio.h>
#include <asm/arch/imx8mp_pins.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
static void setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
/* Enable RGMII TX clk output */
setbits_le32(&gpr->gpr[1], BIT(22));
}
static int setup_eqos(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
/* set INTF as RGMII, enable RGMII TXC clock */
clrsetbits_le32(&gpr->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
return set_clk_eqos(ENET_125MHZ);
}
#if CONFIG_IS_ENABLED(NET)
int board_phy_config(struct phy_device *phydev)
{
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#endif
int board_init(void)
{
if (CONFIG_IS_ENABLED(FEC_MXC))
setup_fec();
if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
setup_eqos();
return 0;
}
int board_late_init(void)
{
return 0;
}

8
board/engicam/imx8mp/imximage-lpddr4.cfg Normal file
View file

@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2021 NXP
*/
ROM_VERSION v2
BOOT_FROM sd
LOADER u-boot-spl-ddr.bin 0x920000

1850
board/engicam/imx8mp/lpddr4_timing.c Normal file
View file

File diff suppressed because it is too large Load diff

152
board/engicam/imx8mp/spl.c Normal file
View file

@ -0,0 +1,152 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2022 Amarula Solutions(India)
* Copyright (C) 2016 Engicam S.r.l.
*
* Authors:
* Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
* Jagan Teki <jagan@amarulasolutions.com>
*/
#include <common.h>
#include <hang.h>
#include <init.h>
#include <log.h>
#include <spl.h>
#include <asm/global_data.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx8mp_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch/ddr.h>
#include <power/pmic.h>
#include <power/pca9450.h>
DECLARE_GLOBAL_DATA_PTR;
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
return BOOT_DEVICE_BOOTROM;
}
void spl_dram_init(void)
{
ddr_init(&dram_timing);
}
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
.gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
.gp = IMX_GPIO_NR(5, 14),
},
.sda = {
.i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
.gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
.gp = IMX_GPIO_NR(5, 15),
},
};
#if CONFIG_IS_ENABLED(POWER_LEGACY)
#define I2C_PMIC 0
int power_init_board(void)
{
struct pmic *p;
int ret;
ret = power_pca9450_init(I2C_PMIC, 0x25);
if (ret)
printf("power init failed");
p = pmic_get("PCA9450");
pmic_probe(p);
/* BUCKxOUT_DVS0/1 control BUCK123 output */
pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
#ifdef CONFIG_IMX8M_LPDDR4
/*
* increase VDD_SOC to typical value 0.95V before first
* DRAM access, set DVS1 to 0.85v for suspend.
* Enable DVS control through PMIC_STBY_REQ and
* set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
*/
#ifdef CONFIG_IMX8M_VDD_SOC_850MV
/* set DVS0 to 0.85v for special case*/
pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14);
#else
pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
#endif
pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
/* Kernel uses OD/OD freq for SOC */
/* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
#elif defined(CONFIG_IMX8M_DDR4)
/* DDR4 runs at 3200MTS, uses default ND 0.85v for VDD_SOC and VDD_ARM */
pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
/* Set NVCC_DRAM to 1.2v for DDR4 */
pmic_reg_write(p, PCA9450_BUCK6OUT, 0x18);
#endif
/* set WDOG_B_CFG to cold reset */
pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
return 0;
}
#endif
void spl_board_init(void)
{
/* Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does not allow to change it.
* Should set the clock after PMIC setting done.
* Default is 400Mhz (system_pll1_800m with div = 2) set by ROM for ND VDD_SOC
*/
clock_enable(CCGR_GIC, 0);
clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
clock_enable(CCGR_GIC, 1);
puts("Normal Boot\n");
}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);
return 0;
}
#endif
void board_init_f(ulong dummy)
{
int ret;
arch_cpu_init();
init_uart_clk(1);
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
hang();
}
preloader_console_init();
enable_tzc380();
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
power_init_board();
/* DDR initialization */
spl_dram_init();
}

12
board/freescale/imx8mm_evk/spl.c
View file

@ -33,6 +33,8 @@ DECLARE_GLOBAL_DATA_PTR;
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
switch (boot_dev_spl) {
case USB_BOOT:
return BOOT_DEVICE_BOARD;
case SD2_BOOT:
case MMC2_BOOT:
return BOOT_DEVICE_MMC1;
@ -53,15 +55,7 @@ static void spl_dram_init(void)
void spl_board_init(void)
{
if (IS_ENABLED(CONFIG_FSL_CAAM)) {
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
printf("Failed to initialize caam_jr: %d\n", ret);
}
puts("Normal Boot\n");
arch_misc_init();
}
#ifdef CONFIG_SPL_LOAD_FIT

7
board/freescale/imx8mn_evk/spl.c
View file

@ -49,11 +49,8 @@ void spl_board_init(void)
struct udevice *dev;
int ret;
if (IS_ENABLED(CONFIG_FSL_CAAM)) {
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
printf("Failed to initialize caam_jr: %d\n", ret);
}
arch_misc_init();
puts("Normal Boot\n");
ret = uclass_get_device_by_name(UCLASS_CLK,

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