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global_data: Remove pci_ram_top

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This field is set but not used. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2024-08-21 10:19:05 -06:00 • committed by Tom Rini
parent f44fded236
commit 7d08262ec3
4 changed files with 0 additions and 26 deletions
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4
arch/arm/mach-tegra/board2.c
View file

@ -423,10 +423,6 @@ int dram_init_banksize(void)
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = usable_ram_size_below_4g(); gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
#ifdef CONFIG_PCI
gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
#endif
#ifdef CONFIG_PHYS_64BIT #ifdef CONFIG_PHYS_64BIT
if (gd->ram_size > SZ_2G) { if (gd->ram_size > SZ_2G) {
gd->bd->bi_dram[1].start = 0x100000000; gd->bd->bi_dram[1].start = 0x100000000;

4
arch/arm/mach-tegra/cboot.c
View file

@ -189,10 +189,6 @@ int cboot_dram_init_banksize(void)
gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size; gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size;
} }
#ifdef CONFIG_PCI
gd->pci_ram_top = ram_top;
#endif
return 0; return 0;
} }

8
arch/x86/cpu/i386/cpu.c
View file

@ -412,12 +412,6 @@ int cpu_phys_address_size(void)
return 32; return 32;
} }
/* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
static void setup_pci_ram_top(void)
{
gd_set_pci_ram_top(0x80000000U);
}
static void setup_mtrr(void) static void setup_mtrr(void)
{ {
u64 mtrr_cap; u64 mtrr_cap;
@ -469,7 +463,6 @@ int x86_cpu_init_f(void)
setup_cpu_features(); setup_cpu_features();
setup_identity(); setup_identity();
setup_mtrr(); setup_mtrr();
setup_pci_ram_top();
/* Set up the i8254 timer if required */ /* Set up the i8254 timer if required */
if (IS_ENABLED(CONFIG_I8254_TIMER)) if (IS_ENABLED(CONFIG_I8254_TIMER))
@ -483,7 +476,6 @@ int x86_cpu_reinit_f(void)
long addr; long addr;
setup_identity(); setup_identity();
setup_pci_ram_top();
addr = locate_coreboot_table(); addr = locate_coreboot_table();
if (addr >= 0) { if (addr >= 0) {
gd->arch.coreboot_table = addr; gd->arch.coreboot_table = addr;

10
include/asm-generic/global_data.h
View file

@ -303,10 +303,6 @@ struct global_data {
* @hose: PCI hose for early use * @hose: PCI hose for early use
*/ */
struct pci_controller *hose; struct pci_controller *hose;
/**
* @pci_ram_top: top of region accessible to PCI
*/
phys_addr_t pci_ram_top;
#endif #endif
#ifdef CONFIG_PCI_BOOTDELAY #ifdef CONFIG_PCI_BOOTDELAY
/** /**
@ -565,12 +561,6 @@ static_assert(sizeof(struct global_data) == GD_SIZE);
#define gd_set_malloc_start(val) #define gd_set_malloc_start(val)
#endif #endif
#if CONFIG_IS_ENABLED(PCI)
#define gd_set_pci_ram_top(val) gd->pci_ram_top = val
#else
#define gd_set_pci_ram_top(val)
#endif
#if CONFIG_VAL(SYS_MALLOC_F_LEN) #if CONFIG_VAL(SYS_MALLOC_F_LEN)
#define gd_malloc_ptr() gd->malloc_ptr #define gd_malloc_ptr() gd->malloc_ptr
#else #else