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* Patch by Hans-Joerg Frieden, 06 Dec 2002
Fix misc problems with AmigaOne support * Patch by Chris Hallinan, 3 Dec 2002: minor cleanup to the MPC8245 EPIC driver * Patch by Pierre Aubert , 28 Nov 2002 Add support for external (SIU) interrupts on MPC8xx * Patch by Pierre Aubert , 28 Nov 2002 Fix nested syscalls bug in standalone applications * Patch by David Mller, 27 Nov 2002: fix output of "pciinfo" command for CardBus bridge devices. * Fix bug in TQM8260 board detection - boards got stuck when board ID was not readable
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wdenk
parent
1f53a41603
commit
7c7a23bd5a
30 changed files with 589 additions and 262 deletions
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@ -22,10 +22,10 @@
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/* CPM Command register.
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*/
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#define CPM_CR_RST ((ushort)0x8000)
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#define CPM_CR_OPCODE ((ushort)0x0f00)
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#define CPM_CR_CHAN ((ushort)0x00f0)
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#define CPM_CR_FLG ((ushort)0x0001)
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#define CPM_CR_RST ((ushort)0x8000)
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#define CPM_CR_OPCODE ((ushort)0x0f00)
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#define CPM_CR_CHAN ((ushort)0x00f0)
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#define CPM_CR_FLG ((ushort)0x0001)
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/* Some commands (there are more...later)
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*/
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@ -39,14 +39,14 @@
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/* Channel numbers.
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*/
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#define CPM_CR_CH_SCC1 ((ushort)0x0000)
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#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
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#define CPM_CR_CH_SCC2 ((ushort)0x0004)
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#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */
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#define CPM_CR_CH_SCC3 ((ushort)0x0008)
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#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
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#define CPM_CR_CH_SCC4 ((ushort)0x000c)
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#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
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#define CPM_CR_CH_SCC1 ((ushort)0x0000)
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#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
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#define CPM_CR_CH_SCC2 ((ushort)0x0004)
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#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI/IDMA2/Timers */
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#define CPM_CR_CH_SCC3 ((ushort)0x0008)
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#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
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#define CPM_CR_CH_SCC4 ((ushort)0x000c)
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#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
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#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
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@ -523,8 +523,8 @@ typedef struct scc_enet {
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#define PROFF_ENET PROFF_SCC2
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#define CPM_CR_ENET CPM_CR_CH_SCC2
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#define SCC_ENET 1
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#define PA_ENET_RXD ((ushort)0x0004)
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#define PA_ENET_TXD ((ushort)0x0008)
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#define PA_ENET_RXD ((ushort)0x0004)
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#define PA_ENET_TXD ((ushort)0x0008)
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#define PA_ENET_TCLK ((ushort)0x0100)
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#define PA_ENET_RCLK ((ushort)0x0400)
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#define PB_ENET_TENA ((uint)0x00002000)
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@ -1034,21 +1034,21 @@ typedef struct scc_enet {
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#define PROFF_ENET PROFF_SCC2
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#define CPM_CR_ENET CPM_CR_CH_SCC2
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#define SCC_ENET 1
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#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
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#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
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#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
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#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
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#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
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#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
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#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
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#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
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#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
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#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
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#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
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#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
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#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
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#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
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/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
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* SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
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*/
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#define SICR_ENET_MASK ((uint)0x0000ff00)
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#define SICR_ENET_CLKRT ((uint)0x00002f00)
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#define SICR_ENET_MASK ((uint)0x0000ff00)
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#define SICR_ENET_CLKRT ((uint)0x00002f00)
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#endif /* CONFIG_NX823 */
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@ -1583,35 +1583,36 @@ typedef struct hdlc_pram_s {
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* priority and SCC1 == SCCa, etc...).
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*/
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#define CPMVEC_NR 32
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#define CPMVEC_PIO_PC15 ((ushort)0x1f)
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#define CPMVEC_SCC1 ((ushort)0x1e)
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#define CPMVEC_SCC2 ((ushort)0x1d)
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#define CPMVEC_SCC3 ((ushort)0x1c)
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#define CPMVEC_SCC4 ((ushort)0x1b)
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#define CPMVEC_PIO_PC14 ((ushort)0x1a)
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#define CPMVEC_TIMER1 ((ushort)0x19)
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#define CPMVEC_PIO_PC13 ((ushort)0x18)
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#define CPMVEC_PIO_PC12 ((ushort)0x17)
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#define CPMVEC_SDMA_CB_ERR ((ushort)0x16)
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#define CPMVEC_IDMA1 ((ushort)0x15)
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#define CPMVEC_IDMA2 ((ushort)0x14)
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#define CPMVEC_TIMER2 ((ushort)0x12)
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#define CPMVEC_RISCTIMER ((ushort)0x11)
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#define CPMVEC_I2C ((ushort)0x10)
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#define CPMVEC_PIO_PC11 ((ushort)0x0f)
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#define CPMVEC_PIO_PC10 ((ushort)0x0e)
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#define CPMVEC_TIMER3 ((ushort)0x0c)
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#define CPMVEC_PIO_PC9 ((ushort)0x0b)
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#define CPMVEC_PIO_PC8 ((ushort)0x0a)
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#define CPMVEC_PIO_PC7 ((ushort)0x09)
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#define CPMVEC_TIMER4 ((ushort)0x07)
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#define CPMVEC_PIO_PC6 ((ushort)0x06)
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#define CPMVEC_SPI ((ushort)0x05)
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#define CPMVEC_SMC1 ((ushort)0x04)
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#define CPMVEC_SMC2 ((ushort)0x03)
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#define CPMVEC_PIO_PC5 ((ushort)0x02)
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#define CPMVEC_PIO_PC4 ((ushort)0x01)
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#define CPMVEC_ERROR ((ushort)0x00)
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#define CPMVEC_OFFSET 0x00010000
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#define CPMVEC_PIO_PC15 ((ushort)0x1f | CPMVEC_OFFSET)
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#define CPMVEC_SCC1 ((ushort)0x1e | CPMVEC_OFFSET)
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#define CPMVEC_SCC2 ((ushort)0x1d | CPMVEC_OFFSET)
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#define CPMVEC_SCC3 ((ushort)0x1c | CPMVEC_OFFSET)
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#define CPMVEC_SCC4 ((ushort)0x1b | CPMVEC_OFFSET)
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#define CPMVEC_PIO_PC14 ((ushort)0x1a | CPMVEC_OFFSET)
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#define CPMVEC_TIMER1 ((ushort)0x19 | CPMVEC_OFFSET)
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#define CPMVEC_PIO_PC13 ((ushort)0x18 | CPMVEC_OFFSET)
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#define CPMVEC_PIO_PC12 ((ushort)0x17 | CPMVEC_OFFSET)
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#define CPMVEC_SDMA_CB_ERR ((ushort)0x16 | CPMVEC_OFFSET)
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#define CPMVEC_IDMA1 ((ushort)0x15 | CPMVEC_OFFSET)
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#define CPMVEC_IDMA2 ((ushort)0x14 | CPMVEC_OFFSET)
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#define CPMVEC_TIMER2 ((ushort)0x12 | CPMVEC_OFFSET)
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#define CPMVEC_RISCTIMER ((ushort)0x11 | CPMVEC_OFFSET)
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#define CPMVEC_I2C ((ushort)0x10 | CPMVEC_OFFSET)
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#define CPMVEC_PIO_PC11 ((ushort)0x0f | CPMVEC_OFFSET)
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#define CPMVEC_PIO_PC10 ((ushort)0x0e | CPMVEC_OFFSET)
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#define CPMVEC_TIMER3 ((ushort)0x0c | CPMVEC_OFFSET)
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#define CPMVEC_PIO_PC9 ((ushort)0x0b | CPMVEC_OFFSET)
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#define CPMVEC_PIO_PC8 ((ushort)0x0a | CPMVEC_OFFSET)
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#define CPMVEC_PIO_PC7 ((ushort)0x09 | CPMVEC_OFFSET)
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#define CPMVEC_TIMER4 ((ushort)0x07 | CPMVEC_OFFSET)
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#define CPMVEC_PIO_PC6 ((ushort)0x06 | CPMVEC_OFFSET)
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#define CPMVEC_SPI ((ushort)0x05 | CPMVEC_OFFSET)
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#define CPMVEC_SMC1 ((ushort)0x04 | CPMVEC_OFFSET)
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#define CPMVEC_SMC2 ((ushort)0x03 | CPMVEC_OFFSET)
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#define CPMVEC_PIO_PC5 ((ushort)0x02 | CPMVEC_OFFSET)
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#define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET)
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#define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET)
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extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
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