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board: phytec: phycore_imx8mm: Update lpddr4_timing

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Update RAM Timings for 2GB RAM based on DDR Controller Configuration
Spreadsheet revision 22. Including the update of the refresh
rate to workaround errata ERR050805.

Signed-off-by: Cem Tenruh <c.tenruh@phytec.de>
This commit is contained in:
Cem Tenruh 2023-06-16 10:28:13 +02:00 • committed by Stefano Babic
parent ff1dd52024
commit 7a478c836a
1 changed files with 742 additions and 744 deletions
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44
board/phytec/phycore_imx8mm/lpddr4_timing.c
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@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-or-later // SPDX-License-Identifier: GPL-2.0-or-later
/* /*
* Copyright (C) 2020 PHYTEC Messtechnik GmbH * Copyright 2019 NXP
* Copyright (C) 2023 PHYTEC Messtechnik GmbH
* *
* Generated code from MX8M_DDR_tool * Generated code from MX8M_DDR_tool
*/ */
@ -13,22 +14,22 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d400304, 0x1}, {0x3d400304, 0x1},
{0x3d400030, 0x1}, {0x3d400030, 0x1},
{0x3d400000, 0xa1080020}, {0x3d400000, 0xa1080020},
{0x3d400020, 0x223}, {0x3d400020, 0x222},
{0x3d400024, 0x3a980}, {0x3d400024, 0x3a980},
{0x3d400064, 0x5b00d2}, {0x3d400064, 0x2d00d2},
{0x3d4000d0, 0xc00305ba}, {0x3d4000d0, 0xc00305ba},
{0x3d4000d4, 0x940000}, {0x3d4000d4, 0x940000},
{0x3d4000dc, 0xd4002d}, {0x3d4000dc, 0xd4002d},
{0x3d4000e0, 0x310000}, {0x3d4000e0, 0x310000},
{0x3d4000e8, 0x66004d}, {0x3d4000e8, 0x66004d},
{0x3d4000ec, 0x16004d}, {0x3d4000ec, 0x16004d},
{0x3d400100, 0x191e1920}, {0x3d400100, 0x191e0c20},
{0x3d400104, 0x60630}, {0x3d400104, 0x60630},
{0x3d40010c, 0xb0b000}, {0x3d40010c, 0xb0b000},
{0x3d400110, 0xe04080e}, {0x3d400110, 0xe04080e},
{0x3d400114, 0x2040c0c}, {0x3d400114, 0x2040c0c},
{0x3d400118, 0x1010007}, {0x3d400118, 0x1010007},
{0x3d40011c, 0x401}, {0x3d40011c, 0x402},
{0x3d400130, 0x20600}, {0x3d400130, 0x20600},
{0x3d400134, 0xc100002}, {0x3d400134, 0xc100002},
{0x3d400138, 0xd8}, {0x3d400138, 0xd8},
@ -45,7 +46,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d4001b0, 0x11}, {0x3d4001b0, 0x11},
{0x3d4001c0, 0x1}, {0x3d4001c0, 0x1},
{0x3d4001c4, 0x1}, {0x3d4001c4, 0x1},
{0x3d4000f4, 0xc99}, {0x3d4000f4, 0x699},
{0x3d400108, 0x70e1617}, {0x3d400108, 0x70e1617},
{0x3d400200, 0x1f}, {0x3d400200, 0x1f},
{0x3d40020c, 0x0}, {0x3d40020c, 0x0},
@ -53,6 +54,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d400204, 0x80808}, {0x3d400204, 0x80808},
{0x3d400214, 0x7070707}, {0x3d400214, 0x7070707},
{0x3d400218, 0x7070707}, {0x3d400218, 0x7070707},
{0x3d40021c, 0xf0f},
{0x3d400250, 0x29001701}, {0x3d400250, 0x29001701},
{0x3d400254, 0x2c}, {0x3d400254, 0x2c},
{0x3d40025c, 0x4000030}, {0x3d40025c, 0x4000030},
@ -64,22 +66,22 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d400498, 0x620096}, {0x3d400498, 0x620096},
{0x3d40049c, 0x1100e07}, {0x3d40049c, 0x1100e07},
{0x3d4004a0, 0xc8012c}, {0x3d4004a0, 0xc8012c},
{0x3d402020, 0x21}, {0x3d402020, 0x20},
{0x3d402024, 0x7d00}, {0x3d402024, 0x7d00},
{0x3d402050, 0x20d040}, {0x3d402050, 0x20d040},
{0x3d402064, 0xc001c}, {0x3d402064, 0x6001c},
{0x3d4020dc, 0x840000}, {0x3d4020dc, 0x840000},
{0x3d4020e0, 0x310000}, {0x3d4020e0, 0x310000},
{0x3d4020e8, 0x66004d}, {0x3d4020e8, 0x66004d},
{0x3d4020ec, 0x16004d}, {0x3d4020ec, 0x16004d},
{0x3d402100, 0xa040305}, {0x3d402100, 0xa040105},
{0x3d402104, 0x30407}, {0x3d402104, 0x30407},
{0x3d402108, 0x203060b}, {0x3d402108, 0x203060b},
{0x3d40210c, 0x505000}, {0x3d40210c, 0x505000},
{0x3d402110, 0x2040202}, {0x3d402110, 0x2040202},
{0x3d402114, 0x2030202}, {0x3d402114, 0x2030202},
{0x3d402118, 0x1010004}, {0x3d402118, 0x1010004},
{0x3d40211c, 0x301}, {0x3d40211c, 0x302},
{0x3d402130, 0x20300}, {0x3d402130, 0x20300},
{0x3d402134, 0xa100002}, {0x3d402134, 0xa100002},
{0x3d402138, 0x1d}, {0x3d402138, 0x1d},
@ -88,8 +90,8 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d402190, 0x3818200}, {0x3d402190, 0x3818200},
{0x3d402194, 0x80303}, {0x3d402194, 0x80303},
{0x3d4021b4, 0x100}, {0x3d4021b4, 0x100},
{0x3d4020f4, 0xc99}, {0x3d4020f4, 0x599},
{0x3d403020, 0x21}, {0x3d403020, 0x20},
{0x3d403024, 0x1f40}, {0x3d403024, 0x1f40},
{0x3d403050, 0x20d040}, {0x3d403050, 0x20d040},
{0x3d403064, 0x30007}, {0x3d403064, 0x30007},
@ -104,7 +106,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d403110, 0x2040202}, {0x3d403110, 0x2040202},
{0x3d403114, 0x2030202}, {0x3d403114, 0x2030202},
{0x3d403118, 0x1010004}, {0x3d403118, 0x1010004},
{0x3d40311c, 0x301}, {0x3d40311c, 0x302},
{0x3d403130, 0x20300}, {0x3d403130, 0x20300},
{0x3d403134, 0xa100002}, {0x3d403134, 0xa100002},
{0x3d403138, 0x8}, {0x3d403138, 0x8},
@ -113,7 +115,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d403190, 0x3818200}, {0x3d403190, 0x3818200},
{0x3d403194, 0x80303}, {0x3d403194, 0x80303},
{0x3d4031b4, 0x100}, {0x3d4031b4, 0x100},
{0x3d4030f4, 0xc99}, {0x3d4030f4, 0x599},
{0x3d400028, 0x0}, {0x3d400028, 0x0},
}; };
@ -201,8 +203,8 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
{0x220024, 0x1ab}, {0x220024, 0x1ab},
{0x2003a, 0x0}, {0x2003a, 0x0},
{0x20056, 0x3}, {0x20056, 0x3},
{0x120056, 0xa}, {0x120056, 0x3},
{0x220056, 0xa}, {0x220056, 0x3},
{0x1004d, 0xe00}, {0x1004d, 0xe00},
{0x1014d, 0xe00}, {0x1014d, 0xe00},
{0x1104d, 0xe00}, {0x1104d, 0xe00},
@ -1043,7 +1045,6 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
{0x13730, 0x0}, {0x13730, 0x0},
{0x13830, 0x0}, {0x13830, 0x0},
}; };
/* P0 message block paremeter for training firmware */ /* P0 message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp0_cfg[] = { struct dram_cfg_param ddr_fsp0_cfg[] = {
{0xd0000, 0x0}, {0xd0000, 0x0},
@ -1054,7 +1055,6 @@ struct dram_cfg_param ddr_fsp0_cfg[] = {
{0x54008, 0x131f}, {0x54008, 0x131f},
{0x54009, 0xc8}, {0x54009, 0xc8},
{0x5400b, 0x2}, {0x5400b, 0x2},
{0x5400d, 0x100},
{0x54012, 0x110}, {0x54012, 0x110},
{0x54019, 0x2dd4}, {0x54019, 0x2dd4},
{0x5401a, 0x31}, {0x5401a, 0x31},
@ -1094,7 +1094,6 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = {
{0x54008, 0x121f}, {0x54008, 0x121f},
{0x54009, 0xc8}, {0x54009, 0xc8},
{0x5400b, 0x2}, {0x5400b, 0x2},
{0x5400d, 0x100},
{0x54012, 0x110}, {0x54012, 0x110},
{0x54019, 0x84}, {0x54019, 0x84},
{0x5401a, 0x31}, {0x5401a, 0x31},
@ -1134,7 +1133,6 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = {
{0x54008, 0x121f}, {0x54008, 0x121f},
{0x54009, 0xc8}, {0x54009, 0xc8},
{0x5400b, 0x2}, {0x5400b, 0x2},
{0x5400d, 0x100},
{0x54012, 0x110}, {0x54012, 0x110},
{0x54019, 0x84}, {0x54019, 0x84},
{0x5401a, 0x31}, {0x5401a, 0x31},
@ -1693,15 +1691,15 @@ static struct dram_cfg_param ddr_phy_pie[] = {
{0x400d6, 0x20a}, {0x400d6, 0x20a},
{0x400d7, 0x20b}, {0x400d7, 0x20b},
{0x2003a, 0x2}, {0x2003a, 0x2},
{0x2000b, 0x5d}, {0x2000b, 0x34b},
{0x2000c, 0xbb}, {0x2000c, 0xbb},
{0x2000d, 0x753}, {0x2000d, 0x753},
{0x2000e, 0x2c}, {0x2000e, 0x2c},
{0x12000b, 0xc}, {0x12000b, 0x70},
{0x12000c, 0x19}, {0x12000c, 0x19},
{0x12000d, 0xfa}, {0x12000d, 0xfa},
{0x12000e, 0x10}, {0x12000e, 0x10},
{0x22000b, 0x3}, {0x22000b, 0x1c},
{0x22000c, 0x6}, {0x22000c, 0x6},
{0x22000d, 0x3e}, {0x22000d, 0x3e},
{0x22000e, 0x10}, {0x22000e, 0x10},