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gpio: npcm: Add persist feature to sgpio module
Base on GPIO hog to support sgpio persist enable feature. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
This commit is contained in:
Jim Liu
Tom Rini
parent
3437624b2e
commit
787d389350
1 changed files with 134 additions and 17 deletions
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@ -4,31 +4,47 @@
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*/
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#include <dm.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/gpio.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <asm/arch/rst.h>
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#define MAX_NR_HW_SGPIO 64
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#define NPCM_CLK_MHZ 8000000
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#define NPCM_IOXCFG1 0x2A
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#define NPCM_SIOX1 24
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#define NPCM_SIOX2 25
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#define NPCM_IOXCTS 0x28
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#define NPCM_IOXCTS_IOXIF_EN BIT(7)
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#define NPCM_IOXCTS_RD_MODE GENMASK(2, 1)
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#define NPCM_IOXCTS_RD_MODE_PERIODIC BIT(2)
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#define NPCM_IOXCFG1 0x2A
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#define NPCM_IOXCFG2 0x2B
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#define NPCM_IOXCFG2_PORT GENMASK(3, 0)
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#define GPIO_BANK(x) ((x) / 8)
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#define GPIO_BIT(x) ((x) % 8)
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#define WD0RCR 0x38
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#define WD1RCR 0x3c
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#define WD2RCR 0x40
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#define SWRSTC1 0x44
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#define SWRSTC2 0x48
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#define SWRSTC3 0x4c
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#define TIPRSTC 0x50
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#define CORSTC 0x5c
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struct npcm_sgpio_priv {
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void __iomem *base;
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struct regmap *rst_regmap;
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u32 nin_sgpio;
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u32 nout_sgpio;
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u32 in_port;
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u32 out_port;
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u8 persist[8];
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u8 siox_num;
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};
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struct npcm_sgpio_bank {
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@ -185,7 +201,13 @@ static int npcm_sgpio_get_value(struct udevice *dev, unsigned int offset)
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static int npcm_sgpio_set_value(struct udevice *dev, unsigned int offset,
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int value)
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{
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struct npcm_sgpio_priv *priv = dev_get_priv(dev);
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u8 check = priv->persist[GPIO_BANK(offset)];
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if (!!(check & BIT(GPIO_BIT(offset))) == 0)
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return npcm_sgpio_direction_output(dev, offset, value);
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else
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return -EINVAL;
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}
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static int npcm_sgpio_get_function(struct udevice *dev, unsigned int offset)
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@ -213,12 +235,10 @@ static void npcm_sgpio_setup_enable(struct npcm_sgpio_priv *gpio, bool enable)
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iowrite8(reg, gpio->base + NPCM_IOXCTS);
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}
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static int npcm_sgpio_init_port(struct udevice *dev)
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static void npcm_sgpio_set_port(struct udevice *dev)
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{
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struct npcm_sgpio_priv *priv = dev_get_priv(dev);
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u8 in_port, out_port, set_port, reg, set_clk;
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npcm_sgpio_setup_enable(priv, false);
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u8 in_port, out_port;
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in_port = GPIO_BANK(priv->nin_sgpio);
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if (GPIO_BIT(priv->nin_sgpio) > 0)
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@ -230,8 +250,16 @@ static int npcm_sgpio_init_port(struct udevice *dev)
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priv->in_port = in_port;
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priv->out_port = out_port;
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}
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set_port = (out_port & NPCM_IOXCFG2_PORT) << 4 | (in_port & NPCM_IOXCFG2_PORT);
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static int npcm_sgpio_init_port(struct udevice *dev)
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{
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struct npcm_sgpio_priv *priv = dev_get_priv(dev);
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u8 set_port, reg, set_clk;
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npcm_sgpio_setup_enable(priv, false);
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set_port = (priv->out_port & NPCM_IOXCFG2_PORT) << 4 | (priv->in_port & NPCM_IOXCFG2_PORT);
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set_clk = 0x07;
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iowrite8(set_port, priv->base + NPCM_IOXCFG2);
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@ -242,6 +270,61 @@ static int npcm_sgpio_init_port(struct udevice *dev)
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return reg == set_port ? 0 : -EINVAL;
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}
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static void npcm_sgpio_reset_persist(struct udevice *dev, uint enable)
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{
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struct npcm_sgpio_priv *priv = dev_get_priv(dev);
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u8 num;
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if (priv->siox_num == 1)
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num = NPCM_SIOX2;
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else
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num = NPCM_SIOX1;
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if (enable) {
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regmap_update_bits(priv->rst_regmap, WD0RCR, BIT(num), 0);
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regmap_update_bits(priv->rst_regmap, WD1RCR, BIT(num), 0);
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regmap_update_bits(priv->rst_regmap, WD2RCR, BIT(num), 0);
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regmap_update_bits(priv->rst_regmap, CORSTC, BIT(num), 0);
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regmap_update_bits(priv->rst_regmap, SWRSTC1, BIT(num), 0);
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regmap_update_bits(priv->rst_regmap, SWRSTC2, BIT(num), 0);
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regmap_update_bits(priv->rst_regmap, SWRSTC3, BIT(num), 0);
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regmap_update_bits(priv->rst_regmap, TIPRSTC, BIT(num), 0);
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}
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}
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static bool is_gpio_persist(struct udevice *dev)
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{
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struct npcm_sgpio_priv *priv = dev_get_priv(dev);
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u32 val;
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int status;
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status = npcm_get_reset_status();
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if (status & PORST)
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return false;
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if (status & CORST)
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regmap_read(priv->rst_regmap, CORSTC, &val);
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else if (status & WD0RST)
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regmap_read(priv->rst_regmap, WD0RCR, &val);
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else if (status & WD1RST)
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regmap_read(priv->rst_regmap, WD1RCR, &val);
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else if (status & WD2RST)
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regmap_read(priv->rst_regmap, WD2RCR, &val);
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else if (status & SW1RST)
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regmap_read(priv->rst_regmap, SWRSTC1, &val);
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else if (status & SW2RST)
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regmap_read(priv->rst_regmap, SWRSTC2, &val);
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else if (status & SW3RST)
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regmap_read(priv->rst_regmap, SWRSTC3, &val);
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else if (status & TIPRST)
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regmap_read(priv->rst_regmap, TIPRSTC, &val);
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if (priv->siox_num == 1)
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return (val && BIT(NPCM_SIOX2));
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else
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return (val && BIT(NPCM_SIOX1));
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}
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static const struct dm_gpio_ops npcm_sgpio_ops = {
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.direction_input = npcm_sgpio_direction_input,
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.direction_output = npcm_sgpio_direction_output,
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@ -254,23 +337,57 @@ static int npcm_sgpio_probe(struct udevice *dev)
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{
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struct npcm_sgpio_priv *priv = dev_get_priv(dev);
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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int rc;
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int rc, i;
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ofnode node;
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u32 val[2];
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priv->base = dev_read_addr_ptr(dev);
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priv->rst_regmap = syscon_regmap_lookup_by_phandle(dev, "syscon-rst");
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if (IS_ERR(priv->rst_regmap))
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return -EINVAL;
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ofnode_read_u32(dev_ofnode(dev), "nuvoton,input-ngpios", &priv->nin_sgpio);
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ofnode_read_u32(dev_ofnode(dev), "nuvoton,output-ngpios", &priv->nout_sgpio);
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if (priv->nin_sgpio > MAX_NR_HW_SGPIO || priv->nout_sgpio > MAX_NR_HW_SGPIO)
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return -EINVAL;
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if (!strcmp(ofnode_get_name(dev_ofnode(dev)), "sgpio2@102000"))
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priv->siox_num = 1;
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else if (!strcmp(ofnode_get_name(dev_ofnode(dev)), "sgpio1@101000"))
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priv->siox_num = 0;
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else
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return -EINVAL;
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npcm_sgpio_set_port(dev);
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uc_priv->gpio_count = priv->nin_sgpio + priv->nout_sgpio;
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uc_priv->bank_name = dev->name;
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if (is_gpio_persist(dev)) {
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ofnode_for_each_subnode(node, dev_ofnode(dev)) {
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if (ofnode_read_bool(node, "persist-enable")) {
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rc = ofnode_read_u32_array(node, "gpios", val, 2);
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if (rc == 0)
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priv->persist[GPIO_BANK(val[0])] = priv->persist[GPIO_BANK(val[0])] | BIT(GPIO_BIT(val[0]));
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}
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}
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for (i = 0; i < priv->nout_sgpio; i++)
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npcm_sgpio_set_value(dev, i, 0);
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} else {
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rc = npcm_sgpio_init_port(dev);
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if (rc < 0)
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return rc;
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uc_priv->gpio_count = priv->nin_sgpio + priv->nout_sgpio;
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uc_priv->bank_name = dev->name;
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ofnode_for_each_subnode(node, dev_ofnode(dev)) {
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if (ofnode_read_bool(node, "persist-enable"))
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npcm_sgpio_reset_persist(dev, 1);
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}
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for (i = 0; i < priv->nout_sgpio; i++)
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npcm_sgpio_set_value(dev, i, 0);
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npcm_sgpio_setup_enable(priv, true);
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}
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return 0;
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}
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