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starfive: pci: Add StarFive JH7110 pcie driver
Add pcie driver for StarFive JH7110, Also add PLDA PCIe controller common driver functions. Several devices are tested: a) M.2 NVMe SSD b) Realtek 8169 Ethernet adapter. Signed-off-by: Mason Huo <mason.huo@starfivetech.com> Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Acked-by: Pali Rohár <pali@kernel.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Mason Huo
Leo Yu-Chi Liang
parent
7eb62cb716
commit
7870a05581
5 changed files with 566 additions and 0 deletions
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@ -393,4 +393,17 @@ config PCIE_XILINX_NWL
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Say 'Y' here if you want support for Xilinx / AMD NWL PCIe
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controller as Root Port.
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config PCIE_PLDA_COMMON
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bool
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config PCIE_STARFIVE_JH7110
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bool "Enable Starfive JH7110 PCIe driver"
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select PCIE_PLDA_COMMON
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imply STARFIVE_JH7110
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imply CLK_JH7110
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imply RESET_JH7110
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help
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Say Y here if you want to enable PLDA XpressRich PCIe controller
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support on StarFive JH7110 SoC.
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endif
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@ -50,3 +50,5 @@ obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
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obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
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obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
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obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
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obj-$(CONFIG_PCIE_PLDA_COMMON) += pcie_plda_common.o
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obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
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116
drivers/pci/pcie_plda_common.c
Normal file
116
drivers/pci/pcie_plda_common.c
Normal file
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@ -0,0 +1,116 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* PLDA XpressRich PCIe host controller common functions.
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*
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* Copyright (C) 2023 StarFive Technology Co., Ltd.
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*
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <pci.h>
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#include <pci_ids.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#include "pcie_plda_common.h"
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static bool plda_pcie_addr_valid(struct pcie_plda *plda, pci_dev_t bdf)
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{
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/*
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* Single device limitation.
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* PCIe controller contain HW issue that secondary bus of
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* host bridge emumerate duplicate devices.
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* Only can access device 0 in secondary bus.
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*/
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if (PCI_BUS(bdf) == plda->sec_busno && PCI_DEV(bdf) > 0)
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return false;
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return true;
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}
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static int plda_pcie_conf_address(const struct udevice *udev, pci_dev_t bdf,
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uint offset, void **paddr)
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{
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struct pcie_plda *priv = dev_get_priv(udev);
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int where = PCIE_ECAM_OFFSET(PCI_BUS(bdf), PCI_DEV(bdf),
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PCI_FUNC(bdf), offset);
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if (!plda_pcie_addr_valid(priv, bdf))
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return -ENODEV;
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*paddr = (void *)(priv->cfg_base + where);
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return 0;
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}
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int plda_pcie_config_read(const struct udevice *udev, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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return pci_generic_mmap_read_config(udev, plda_pcie_conf_address,
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bdf, offset, valuep, size);
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}
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int plda_pcie_config_write(struct udevice *udev, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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struct pcie_plda *priv = dev_get_priv(udev);
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int ret;
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ret = pci_generic_mmap_write_config(udev, plda_pcie_conf_address,
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bdf, offset, value, size);
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/* record secondary bus number */
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if (!ret && PCI_BUS(bdf) == dev_seq(udev) &&
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PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
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(offset == PCI_SECONDARY_BUS ||
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(offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8))) {
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priv->sec_busno =
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((offset == PCI_PRIMARY_BUS) ? (value >> 8) : value) & 0xff;
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debug("Secondary bus number was changed to %d\n",
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priv->sec_busno);
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}
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return ret;
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}
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int plda_pcie_set_atr_entry(struct pcie_plda *plda, phys_addr_t src_addr,
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phys_addr_t trsl_addr, phys_size_t window_size,
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int trsl_param)
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{
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void __iomem *base =
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plda->reg_base + XR3PCI_ATR_AXI4_SLV0;
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/* Support AXI4 Slave 0 Address Translation Tables 0-7. */
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if (plda->atr_table_num >= XR3PCI_ATR_MAX_TABLE_NUM) {
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dev_err(plda->dev, "ATR table number %d exceeds max num\n",
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plda->atr_table_num);
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return -EINVAL;
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}
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base += XR3PCI_ATR_TABLE_OFFSET * plda->atr_table_num;
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plda->atr_table_num++;
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/*
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* X3PCI_ATR_SRC_ADDR_LOW:
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* - bit 0: enable entry,
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* - bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1)
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* - bits 7-11: reserved
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* - bits 12-31: start of source address
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*/
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writel((lower_32_bits(src_addr) & XR3PCI_ATR_SRC_ADDR_MASK) |
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(fls(window_size) - 1) << XR3PCI_ATR_SRC_WIN_SIZE_SHIFT | 1,
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base + XR3PCI_ATR_SRC_ADDR_LOW);
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writel(upper_32_bits(src_addr), base + XR3PCI_ATR_SRC_ADDR_HIGH);
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writel((lower_32_bits(trsl_addr) & XR3PCI_ATR_TRSL_ADDR_MASK),
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base + XR3PCI_ATR_TRSL_ADDR_LOW);
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writel(upper_32_bits(trsl_addr), base + XR3PCI_ATR_TRSL_ADDR_HIGH);
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writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
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dev_dbg(plda->dev, "ATR entry: 0x%010llx %s 0x%010llx [0x%010llx] (param: 0x%06x)\n",
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src_addr, (trsl_param & XR3PCI_ATR_TRSL_DIR) ? "<-" : "->",
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trsl_addr, (u64)window_size, trsl_param);
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return 0;
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}
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118
drivers/pci/pcie_plda_common.h
Normal file
118
drivers/pci/pcie_plda_common.h
Normal file
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@ -0,0 +1,118 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2023 StarFive Technology Co., Ltd.
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* Author: Minda Chen <minda.chen@starfivetech.com>
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*
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*/
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#ifndef PCIE_PLDA_COMMON_H
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#define PCIE_PLDA_COMMON_H
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#define GEN_SETTINGS 0x80
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#define PCIE_PCI_IDS 0x9C
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#define PCIE_WINROM 0xFC
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#define PMSG_SUPPORT_RX 0x3F0
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#define PCI_MISC 0xB4
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#define PLDA_EP_ENABLE 0
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#define PLDA_RP_ENABLE 1
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#define IDS_CLASS_CODE_SHIFT 8
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#define PREF_MEM_WIN_64_SUPPORT BIT(3)
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#define PMSG_LTR_SUPPORT BIT(2)
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#define PLDA_FUNCTION_DIS BIT(15)
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#define PLDA_FUNC_NUM 4
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#define PLDA_PHY_FUNC_SHIFT 9
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#define XR3PCI_ATR_AXI4_SLV0 0x800
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#define XR3PCI_ATR_SRC_ADDR_LOW 0x0
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#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
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#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
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#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
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#define XR3PCI_ATR_TRSL_PARAM 0x10
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#define XR3PCI_ATR_TABLE_OFFSET 0x20
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#define XR3PCI_ATR_MAX_TABLE_NUM 8
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#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1
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#define XR3PCI_ATR_SRC_ADDR_MASK GENMASK(31, 12)
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#define XR3PCI_ATR_TRSL_ADDR_MASK GENMASK(31, 12)
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#define XR3PCI_ATR_TRSL_DIR BIT(22)
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/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
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#define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0
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#define XR3PCI_ATR_TRSLID_PCIE_CONFIG 0x1
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/**
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* struct pcie_plda - PLDA PCIe controller state
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*
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* @reg_base: The base address of controller register space
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* @cfg_base: The base address of configuration space
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* @cfg_size: The size of configuration space
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* @sec_busno: Secondary bus number.
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* @atr_table_num: Total ATR table numbers.
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*/
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struct pcie_plda {
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struct udevice *dev;
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void __iomem *reg_base;
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void __iomem *cfg_base;
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phys_size_t cfg_size;
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int sec_busno;
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int atr_table_num;
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};
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int plda_pcie_config_read(const struct udevice *udev, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size);
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int plda_pcie_config_write(struct udevice *udev, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size);
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int plda_pcie_set_atr_entry(struct pcie_plda *plda, phys_addr_t src_addr,
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phys_addr_t trsl_addr, phys_size_t window_size,
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int trsl_param);
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static inline void plda_pcie_enable_root_port(struct pcie_plda *plda)
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{
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u32 value;
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value = readl(plda->reg_base + GEN_SETTINGS);
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value |= PLDA_RP_ENABLE;
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writel(value, plda->reg_base + GEN_SETTINGS);
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}
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static inline void plda_pcie_set_standard_class(struct pcie_plda *plda)
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{
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u32 value;
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value = readl(plda->reg_base + PCIE_PCI_IDS);
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value &= 0xff;
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value |= (PCI_CLASS_BRIDGE_PCI_NORMAL << IDS_CLASS_CODE_SHIFT);
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writel(value, plda->reg_base + PCIE_PCI_IDS);
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}
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static inline void plda_pcie_set_pref_win_64bit(struct pcie_plda *plda)
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{
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u32 value;
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value = readl(plda->reg_base + PCIE_WINROM);
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value |= PREF_MEM_WIN_64_SUPPORT;
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writel(value, plda->reg_base + PCIE_WINROM);
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}
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static inline void plda_pcie_disable_ltr(struct pcie_plda *plda)
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{
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u32 value;
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value = readl(plda->reg_base + PMSG_SUPPORT_RX);
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value &= ~PMSG_LTR_SUPPORT;
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writel(value, plda->reg_base + PMSG_SUPPORT_RX);
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}
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static inline void plda_pcie_disable_func(struct pcie_plda *plda)
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{
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u32 value;
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value = readl(plda->reg_base + PCI_MISC);
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value |= PLDA_FUNCTION_DIS;
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writel(value, plda->reg_base + PCI_MISC);
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}
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#endif
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317
drivers/pci/pcie_starfive_jh7110.c
Normal file
317
drivers/pci/pcie_starfive_jh7110.c
Normal file
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@ -0,0 +1,317 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* StarFive PLDA PCIe host controller driver
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*
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* Copyright (C) 2023 StarFive Technology Co., Ltd.
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* Author: Mason Huo <mason.huo@starfivetech.com>
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*
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <pci.h>
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#include <pci_ids.h>
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#include <power-domain.h>
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#include <regmap.h>
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#include <reset.h>
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#include <syscon.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm-generic/gpio.h>
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#include <dm/device_compat.h>
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#include <dm/pinctrl.h>
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#include "pcie_plda_common.h"
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/* system control */
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#define STG_SYSCON_K_RP_NEP_MASK BIT(8)
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#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK GENMASK(22, 8)
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#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 8
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#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK GENMASK(14, 0)
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#define STG_SYSCON_CLKREQ_MASK BIT(22)
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#define STG_SYSCON_CKREF_SRC_SHIFT 18
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#define STG_SYSCON_CKREF_SRC_MASK GENMASK(19, 18)
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DECLARE_GLOBAL_DATA_PTR;
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struct starfive_pcie {
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struct pcie_plda plda;
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struct clk_bulk clks;
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struct reset_ctl_bulk rsts;
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struct gpio_desc reset_gpio;
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struct regmap *regmap;
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u32 stg_arfun;
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u32 stg_awfun;
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u32 stg_rp_nep;
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};
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static int starfive_pcie_atr_init(struct starfive_pcie *priv)
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{
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struct udevice *ctlr = pci_get_controller(priv->plda.dev);
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struct pci_controller *hose = dev_get_uclass_priv(ctlr);
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int i, ret;
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/*
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* As the two host bridges in JH7110 soc have the same default
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* address translation table, this cause the second root port can't
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* access it's host bridge config space correctly.
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* To workaround, config the ATR of host bridge config space by SW.
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*/
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ret = plda_pcie_set_atr_entry(&priv->plda,
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(phys_addr_t)priv->plda.cfg_base, 0,
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priv->plda.cfg_size,
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XR3PCI_ATR_TRSLID_PCIE_CONFIG);
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if (ret)
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return ret;
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for (i = 0; i < hose->region_count; i++) {
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if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY)
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continue;
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/* Only support identity mappings. */
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if (hose->regions[i].bus_start !=
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hose->regions[i].phys_start)
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return -EINVAL;
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ret = plda_pcie_set_atr_entry(&priv->plda,
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hose->regions[i].phys_start,
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hose->regions[i].bus_start,
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hose->regions[i].size,
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XR3PCI_ATR_TRSLID_PCIE_MEMORY);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int starfive_pcie_get_syscon(struct udevice *dev)
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{
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struct starfive_pcie *priv = dev_get_priv(dev);
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struct udevice *syscon;
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struct ofnode_phandle_args syscfg_phandle;
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u32 cells[4];
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int ret;
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/* get corresponding syscon phandle */
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ret = dev_read_phandle_with_args(dev, "starfive,stg-syscon", NULL, 0, 0,
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&syscfg_phandle);
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if (ret < 0) {
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dev_err(dev, "Can't get syscfg phandle: %d\n", ret);
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return ret;
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}
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ret = uclass_get_device_by_ofnode(UCLASS_SYSCON, syscfg_phandle.node,
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&syscon);
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if (ret) {
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dev_err(dev, "Unable to find syscon device (%d)\n", ret);
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return ret;
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}
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priv->regmap = syscon_get_regmap(syscon);
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if (!priv->regmap) {
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dev_err(dev, "Unable to find regmap\n");
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return -ENODEV;
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}
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/* get syscon register offset */
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ret = dev_read_u32_array(dev, "starfive,stg-syscon",
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cells, ARRAY_SIZE(cells));
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if (ret) {
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dev_err(dev, "Get syscon register err %d\n", ret);
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return -EINVAL;
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}
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dev_dbg(dev, "Get syscon values: %x, %x, %x\n",
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cells[1], cells[2], cells[3]);
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priv->stg_arfun = cells[1];
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priv->stg_awfun = cells[2];
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priv->stg_rp_nep = cells[3];
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return 0;
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}
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static int starfive_pcie_parse_dt(struct udevice *dev)
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{
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struct starfive_pcie *priv = dev_get_priv(dev);
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int ret;
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priv->plda.reg_base = (void *)dev_read_addr_name(dev, "reg");
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if (priv->plda.reg_base == (void __iomem *)FDT_ADDR_T_NONE) {
|
||||
dev_err(dev, "Missing required reg address range\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
priv->plda.cfg_base =
|
||||
(void *)dev_read_addr_size_name(dev,
|
||||
"config",
|
||||
&priv->plda.cfg_size);
|
||||
if (priv->plda.cfg_base == (void __iomem *)FDT_ADDR_T_NONE) {
|
||||
dev_err(dev, "Missing required config address range");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = starfive_pcie_get_syscon(dev);
|
||||
if (ret) {
|
||||
dev_err(dev, "Can't get syscon: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = reset_get_bulk(dev, &priv->rsts);
|
||||
if (ret) {
|
||||
dev_err(dev, "Can't get reset: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_get_bulk(dev, &priv->clks);
|
||||
if (ret) {
|
||||
dev_err(dev, "Can't get clock: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio,
|
||||
GPIOD_IS_OUT);
|
||||
if (ret) {
|
||||
dev_err(dev, "Can't get reset-gpio: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (!dm_gpio_is_valid(&priv->reset_gpio)) {
|
||||
dev_err(dev, "reset-gpio is not valid\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int starfive_pcie_init_port(struct udevice *dev)
|
||||
{
|
||||
int ret, i;
|
||||
struct starfive_pcie *priv = dev_get_priv(dev);
|
||||
struct pcie_plda *plda = &priv->plda;
|
||||
|
||||
ret = clk_enable_bulk(&priv->clks);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to enable clks (ret=%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = reset_deassert_bulk(&priv->rsts);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to deassert resets (ret=%d)\n", ret);
|
||||
goto err_deassert_clk;
|
||||
}
|
||||
|
||||
dm_gpio_set_value(&priv->reset_gpio, 1);
|
||||
/* Disable physical functions except #0 */
|
||||
for (i = 1; i < PLDA_FUNC_NUM; i++) {
|
||||
regmap_update_bits(priv->regmap,
|
||||
priv->stg_arfun,
|
||||
STG_SYSCON_AXI4_SLVL_ARFUNC_MASK,
|
||||
(i << PLDA_PHY_FUNC_SHIFT) <<
|
||||
STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT);
|
||||
regmap_update_bits(priv->regmap,
|
||||
priv->stg_awfun,
|
||||
STG_SYSCON_AXI4_SLVL_AWFUNC_MASK,
|
||||
i << PLDA_PHY_FUNC_SHIFT);
|
||||
|
||||
plda_pcie_disable_func(plda);
|
||||
}
|
||||
|
||||
/* Disable physical functions */
|
||||
regmap_update_bits(priv->regmap,
|
||||
priv->stg_arfun,
|
||||
STG_SYSCON_AXI4_SLVL_ARFUNC_MASK,
|
||||
0);
|
||||
regmap_update_bits(priv->regmap,
|
||||
priv->stg_awfun,
|
||||
STG_SYSCON_AXI4_SLVL_AWFUNC_MASK,
|
||||
0);
|
||||
|
||||
plda_pcie_enable_root_port(plda);
|
||||
|
||||
/* PCIe PCI Standard Configuration Identification Settings. */
|
||||
plda_pcie_set_standard_class(plda);
|
||||
|
||||
/*
|
||||
* The LTR message forwarding of PCIe Message Reception was set by core
|
||||
* as default, but the forward id & addr are also need to be reset.
|
||||
* If we do not disable LTR message forwarding here, or set a legal
|
||||
* forwarding address, the kernel will get stuck after this driver probe.
|
||||
* To workaround, disable the LTR message forwarding support on
|
||||
* PCIe Message Reception.
|
||||
*/
|
||||
plda_pcie_disable_ltr(plda);
|
||||
|
||||
/* Prefetchable memory window 64-bit addressing support */
|
||||
plda_pcie_set_pref_win_64bit(plda);
|
||||
starfive_pcie_atr_init(priv);
|
||||
|
||||
dm_gpio_set_value(&priv->reset_gpio, 0);
|
||||
/* Ensure that PERST in default at least 300 ms */
|
||||
mdelay(300);
|
||||
|
||||
return 0;
|
||||
|
||||
err_deassert_clk:
|
||||
clk_disable_bulk(&priv->clks);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int starfive_pcie_probe(struct udevice *dev)
|
||||
{
|
||||
struct starfive_pcie *priv = dev_get_priv(dev);
|
||||
int ret;
|
||||
|
||||
priv->plda.atr_table_num = 0;
|
||||
priv->plda.dev = dev;
|
||||
|
||||
ret = starfive_pcie_parse_dt(dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
regmap_update_bits(priv->regmap,
|
||||
priv->stg_rp_nep,
|
||||
STG_SYSCON_K_RP_NEP_MASK,
|
||||
STG_SYSCON_K_RP_NEP_MASK);
|
||||
|
||||
regmap_update_bits(priv->regmap,
|
||||
priv->stg_awfun,
|
||||
STG_SYSCON_CKREF_SRC_MASK,
|
||||
2 << STG_SYSCON_CKREF_SRC_SHIFT);
|
||||
|
||||
regmap_update_bits(priv->regmap,
|
||||
priv->stg_awfun,
|
||||
STG_SYSCON_CLKREQ_MASK,
|
||||
STG_SYSCON_CLKREQ_MASK);
|
||||
|
||||
ret = starfive_pcie_init_port(dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
dev_err(dev, "Starfive PCIe bus probed.\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dm_pci_ops starfive_pcie_ops = {
|
||||
.read_config = plda_pcie_config_read,
|
||||
.write_config = plda_pcie_config_write,
|
||||
};
|
||||
|
||||
static const struct udevice_id starfive_pcie_ids[] = {
|
||||
{ .compatible = "starfive,jh7110-pcie" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(starfive_pcie_drv) = {
|
||||
.name = "starfive_7110_pcie",
|
||||
.id = UCLASS_PCI,
|
||||
.of_match = starfive_pcie_ids,
|
||||
.ops = &starfive_pcie_ops,
|
||||
.probe = starfive_pcie_probe,
|
||||
.priv_auto = sizeof(struct starfive_pcie),
|
||||
};
|
||||
Loading…
Add table
Reference in a new issue