Convert CONFIG_SYS_PCI_64BIT to Kconfig

This converts the following to Kconfig:
   CONFIG_SYS_PCI_64BIT

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2021-12-12 22:12:32 -05:00
parent d06e4b7e25
commit 7856cd5a6d
29 changed files with 14 additions and 33 deletions

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@ -1909,6 +1909,7 @@ config ARCH_OCTEONTX
select OF_LIVE select OF_LIVE
select BOARD_LATE_INIT select BOARD_LATE_INIT
select SYS_CACHE_SHIFT_7 select SYS_CACHE_SHIFT_7
select SYS_PCI_64BIT if PCI
imply OF_HAS_PRIOR_STAGE imply OF_HAS_PRIOR_STAGE
config ARCH_OCTEONTX2 config ARCH_OCTEONTX2
@ -1921,6 +1922,7 @@ config ARCH_OCTEONTX2
select OF_LIVE select OF_LIVE
select BOARD_LATE_INIT select BOARD_LATE_INIT
select SYS_CACHE_SHIFT_7 select SYS_CACHE_SHIFT_7
select SYS_PCI_64BIT if PCI
imply OF_HAS_PRIOR_STAGE imply OF_HAS_PRIOR_STAGE
config TARGET_THUNDERX_88XX config TARGET_THUNDERX_88XX

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@ -262,6 +262,7 @@ config ARCH_LX2162A
select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_DDR4
select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE select SYS_FSL_SEC_LE
select SYS_PCI_64BIT if PCI
select ARCH_EARLY_INIT_R select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F select BOARD_EARLY_INIT_F
select SYS_I2C_MXC select SYS_I2C_MXC
@ -301,6 +302,7 @@ config ARCH_LX2160A
select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_DDR4
select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE select SYS_FSL_SEC_LE
select SYS_PCI_64BIT if PCI
select ARCH_EARLY_INIT_R select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F select BOARD_EARLY_INIT_F
select SYS_I2C_MXC select SYS_I2C_MXC

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@ -16,8 +16,4 @@ config SYS_SOC
string string
default "octeontx" default "octeontx"
config SYS_PCI_64BIT
bool
default y
endif endif

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@ -16,8 +16,4 @@ config SYS_SOC
string string
default "octeontx2" default "octeontx2"
config SYS_PCI_64BIT
bool
default y
endif endif

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@ -5,6 +5,7 @@ CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="mpc8379erdb" CONFIG_DEFAULT_DEVICE_TREE="mpc8379erdb"
CONFIG_SYS_CLK_FREQ=66666667 CONFIG_SYS_CLK_FREQ=66666667
# CONFIG_SYS_PCI_64BIT is not set
CONFIG_MPC83xx=y CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC837XERDB=y CONFIG_TARGET_MPC837XERDB=y

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@ -7,6 +7,7 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="phytium-durian" CONFIG_DEFAULT_DEVICE_TREE="phytium-durian"
# CONFIG_PSCI_RESET is not set # CONFIG_PSCI_RESET is not set
CONFIG_SYS_PCI_64BIT=y
CONFIG_AHCI=y CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x90000000 CONFIG_SYS_LOAD_ADDR=0x90000000

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@ -10,6 +10,7 @@ CONFIG_SPL_MMC=y
CONFIG_SPL=y CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y CONFIG_SPL_SPI=y
CONFIG_SYS_PCI_64BIT=y
CONFIG_AHCI=y CONFIG_AHCI=y
CONFIG_TARGET_SIFIVE_UNMATCHED=y CONFIG_TARGET_SIFIVE_UNMATCHED=y
CONFIG_ARCH_RV64I=y CONFIG_ARCH_RV64I=y

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@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xfff80000
CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="socrates" CONFIG_DEFAULT_DEVICE_TREE="socrates"
# CONFIG_SYS_PCI_64BIT is not set
CONFIG_MPC85xx=y CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set # CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_SOCRATES=y CONFIG_TARGET_SOCRATES=y

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@ -19,6 +19,12 @@ config DM_PCI_COMPAT
measure when porting a board to use driver model for PCI. Once the measure when porting a board to use driver model for PCI. Once the
board is fully supported, this option should be disabled. board is fully supported, this option should be disabled.
config SYS_PCI_64BIT
bool "Enable 64-bit PCI resources"
default y if PPC
help
Enable 64-bit PCI resource access.
config PCI_AARDVARK config PCI_AARDVARK
bool "Enable Aardvark PCIe driver" bool "Enable Aardvark PCIe driver"
depends on DM_GPIO depends on DM_GPIO

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@ -26,8 +26,6 @@
#define CONFIG_HAS_FEC 1 /* 8540 has FEC */ #define CONFIG_HAS_FEC 1 /* 8540 has FEC */
#endif #endif
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
/* /*
* sysclk for MPC85xx * sysclk for MPC85xx
* *

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@ -19,7 +19,6 @@
#define CONFIG_PCI1 /* PCI controller 1 */ #define CONFIG_PCI1 /* PCI controller 1 */
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#undef CONFIG_PCI2 #undef CONFIG_PCI2
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */

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@ -27,7 +27,6 @@
* assume U-Boot is less than 0.5MB * assume U-Boot is less than 0.5MB
*/ */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
/* /*

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@ -114,7 +114,6 @@
#if defined(CONFIG_PCI) #if defined(CONFIG_PCI)
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/* /*
* PCI Windows * PCI Windows

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@ -36,7 +36,6 @@
#define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_SYS_SRIO #define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO1 /* SRIO port 1 */

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@ -416,7 +416,6 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
/* controller 1, direct to uli, tgtid 3, Base address 20000 */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */

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@ -85,8 +85,6 @@
#define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_PCIE4 /* PCIE controller 4 */ #define CONFIG_PCIE4 /* PCIE controller 4 */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#if defined(CONFIG_SPIFLASH) #if defined(CONFIG_SPIFLASH)
#elif defined(CONFIG_MTD_RAW_NAND) #elif defined(CONFIG_MTD_RAW_NAND)
#ifdef CONFIG_NXP_ESBC #ifdef CONFIG_NXP_ESBC

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@ -414,7 +414,6 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_PCIE4 /* PCIE controller 4 */ #define CONFIG_PCIE4 /* PCIE controller 4 */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/* controller 1, direct to uli, tgtid 3, Base address 20000 */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull

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@ -366,7 +366,6 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_PCIE4 /* PCIE controller 4 */ #define CONFIG_PCIE4 /* PCIE controller 4 */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/* controller 1, direct to uli, tgtid 3, Base address 20000 */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull

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@ -60,7 +60,6 @@
#define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/* /*
* These can be toggled for performance analysis, otherwise use default. * These can be toggled for performance analysis, otherwise use default.

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@ -44,7 +44,6 @@
/* Access eMMC Boot_1 and Boot_2 partitions */ /* Access eMMC Boot_1 and Boot_2 partitions */
/* enable 64-bit PCI resources */ /* enable 64-bit PCI resources */
#define CONFIG_SYS_PCI_64BIT 1
#define CONSOLE_ARGS "console_args=console=ttyS0,115200n8\0" #define CONSOLE_ARGS "console_args=console=ttyS0,115200n8\0"
#define MAX_CPUS "max_cpus=maxcpus=8\0" #define MAX_CPUS "max_cpus=maxcpus=8\0"

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@ -47,7 +47,6 @@
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#if defined(CONFIG_SPIFLASH) #if defined(CONFIG_SPIFLASH)
#elif defined(CONFIG_SDCARD) #elif defined(CONFIG_SDCARD)

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@ -16,7 +16,6 @@
#define CONFIG_SYS_INIT_SP_ADDR (0x88000000 - 0x100000) #define CONFIG_SYS_INIT_SP_ADDR (0x88000000 - 0x100000)
/* PCI CONFIG */ /* PCI CONFIG */
#define CONFIG_SYS_PCI_64BIT 1
#define CONFIG_PCI_SCAN_SHOW #define CONFIG_PCI_SCAN_SHOW
/* SCSI */ /* SCSI */

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@ -141,7 +141,6 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/* Environment in parallel NOR-Flash */ /* Environment in parallel NOR-Flash */
#define CONFIG_ENV_TOTAL_SIZE 0x040000 #define CONFIG_ENV_TOTAL_SIZE 0x040000

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@ -104,7 +104,6 @@
/* PCI */ /* PCI */
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
#define CONFIG_SYS_PCI_64BIT
#define CONFIG_PCI_SCAN_SHOW #define CONFIG_PCI_SCAN_SHOW
#endif #endif

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@ -140,7 +140,6 @@
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_LBA48 #define CONFIG_LBA48

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@ -13,8 +13,6 @@
#define CONFIG_SYS_RAMBOOT #define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_ENABLE_36BIT_PHYS #define CONFIG_ENABLE_36BIT_PHYS
/* Needed to fill the ccsrbar pointer */ /* Needed to fill the ccsrbar pointer */

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@ -32,8 +32,6 @@
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit resources */
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
/* Environment options */ /* Environment options */

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@ -46,7 +46,6 @@
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */ /* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
/* #define CONFIG_SYS_PCI_64BIT 1 */
#define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \ #define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \
"mtd nor1=u-boot.bin raw 200000 100000;" \ "mtd nor1=u-boot.bin raw 200000 100000;" \

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@ -198,6 +198,4 @@
#define CONFIG_SPL_PAD_TO 0x20000 #define CONFIG_SPL_PAD_TO 0x20000
#define CONFIG_SYS_PCI_64BIT
#endif /* __CONFIG_UNIPHIER_H__ */ #endif /* __CONFIG_UNIPHIER_H__ */