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rockchip: jaguar-rk3588: enable SARADC and derivatives

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The SARADC is used on Jaguar for multiple things:
- channel 0 is used (at runtime) as a BIOS button,
- channel 2 is exposed on the Mezzanine connector for customer specific
  logic,
- channel 5 and 6 are used for identification,

Since the SARADC requires a vref-supply provided by the RK806 PMIC, its
support and the support for its regulators are also enabled.

The button, adc, pmic and regulator commands are also enabled for CLI
use in U-Boot for debugging and scripting purposes.

The RK806 PMIC on Jaguar being routed on the SPI bus, let's enable
Rockchip SPI controller driver.

Finally, the SARADC channel 1 on Jaguar is hardwired so will never
change in the lifetime of a unit, for that reason, disable the Rockchip
Download Mode check by setting ROCKCHIP_BOOT_MODE_REG symbol to 0.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
This commit is contained in:
Quentin Schulz 2024-03-14 10:36:26 +01:00 • committed by Kever Yang
parent 1fb75f7ee4
commit 768636c371
1 changed files with 9 additions and 1 deletions
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10
configs/jaguar-rk3588_defconfig
View file

@ -9,6 +9,7 @@ CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_ENV_SIZE=0x1f000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-jaguar"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0
CONFIG_SPL_SERIAL=y
CONFIG_TARGET_JAGUAR_RK3588=y
CONFIG_DEBUG_UART_BASE=0xfeb50000
@ -34,6 +35,7 @@ CONFIG_SPL_ATF=y
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
# CONFIG_CMD_ELF is not set
CONFIG_CMD_ADC=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
@ -46,6 +48,7 @@ CONFIG_CMD_USB=y
# CONFIG_CMD_MII is not set
# CONFIG_CMD_BLOCK_CACHE is not set
# CONFIG_CMD_EFICONFIG is not set
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EROFS=y
CONFIG_CMD_SQUASHFS=y
@ -60,7 +63,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
# CONFIG_SARADC_ROCKCHIP is not set
CONFIG_BUTTON=y
CONFIG_BUTTON_ADC=y
CONFIG_SPL_CLK=y
CONFIG_CLK_GPIO=y
CONFIG_ROCKCHIP_GPIO=y
@ -88,10 +92,14 @@ CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_SPL_RAM=y
CONFIG_SCSI=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y