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board/bsc9131rdb: Add DSP side tlb and laws
BSC9131RDB is a Freescale Reference Design Board for BSC9131 SoC which is a integrated device that contains one powerpc e500v2 core and one DSP starcore. To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 memory Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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6 changed files with 29 additions and 0 deletions
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@ -494,6 +494,8 @@
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#define CONFIG_TSECV2
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
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#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_NAND_FSL_IFC
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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@ -82,11 +82,16 @@ enum law_trgt_if {
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#ifndef CONFIG_MPC8641
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LAW_TRGT_IF_PCIE_1 = 0x02,
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#endif
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#if defined(CONFIG_BSC9131)
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LAW_TRGT_IF_OCN_DSP = 0x03,
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#else
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#if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020)
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LAW_TRGT_IF_PCIE_3 = 0x03,
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#endif
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#endif
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LAW_TRGT_IF_LBC = 0x04,
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LAW_TRGT_IF_CCSR = 0x08,
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LAW_TRGT_IF_DSP_CCSR = 0x09,
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LAW_TRGT_IF_DDR_INTRLV = 0x0b,
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LAW_TRGT_IF_RIO = 0x0c,
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LAW_TRGT_IF_RIO_2 = 0x0d,
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