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mmc: fsl_esdhc_imx: Enable AHB/IPG clk with clk bulk API

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With partition reset supported for i.MX8QM/QXP/95 and etc, when linux
mmc runtime suspended, the mmc clks are gated off. While at same time
system controller reset Cortex-A cores because of various reasons(
WDOG timeout and etc), with SPL run again, only enable PER clk is not
enough, also need to enable AHB/IPG clk, here use clk bulk API to enable
all the clocks.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan 2024-10-01 21:07:53 +08:00 • committed by Fabio Estevam
parent dd95eefb3a
commit 76332fae76
1 changed files with 13 additions and 5 deletions
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18
drivers/mmc/fsl_esdhc_imx.c
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@ -148,6 +148,7 @@ struct fsl_esdhc_priv {
struct fsl_esdhc *esdhc_regs;
unsigned int sdhc_clk;
struct clk per_clk;
struct clk_bulk clk_bulk;
unsigned int clock;
unsigned int mode;
#if !CONFIG_IS_ENABLED(DM_MMC)
@ -1521,16 +1522,23 @@ static int fsl_esdhc_probe(struct udevice *dev)
#if CONFIG_IS_ENABLED(CLK)
/* Assigned clock already set clock */
ret = clk_get_bulk(dev, &priv->clk_bulk);
if (ret) {
dev_err(dev, "Failed to get clks: %d\n", ret);
return ret;
}
ret = clk_enable_bulk(&priv->clk_bulk);
if (ret) {
dev_err(dev, "Failed to enable clks: %d\n", ret);
return ret;
}
ret = clk_get_by_name(dev, "per", &priv->per_clk);
if (ret) {
printf("Failed to get per_clk\n");
return ret;
}
ret = clk_enable(&priv->per_clk);
if (ret) {
printf("Failed to enable per_clk\n");
return ret;
}
priv->sdhc_clk = clk_get_rate(&priv->per_clk);
#else