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video: tegra20: dsi: add ganged mode support
Implement ganged mode support for the Tegra DSI driver. The DSI host controller to gang up with is specified via a phandle in the device tree and the resolved DSI host controller used for the programming of the ganged-mode registers. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
This commit is contained in:
Svyatoslav Ryhel
parent
68ebc7c86b
commit
744bce5123
2 changed files with 104 additions and 6 deletions
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@ -20,6 +20,7 @@
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include "tegra-dc.h"
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#include "tegra-dsi.h"
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@ -50,6 +51,10 @@ struct tegra_dsi_priv {
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int host_fifo_depth;
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u32 version;
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/* for ganged-mode support */
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struct udevice *master;
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struct udevice *slave;
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};
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static void tegra_dc_enable_controller(struct udevice *dev)
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@ -595,6 +600,17 @@ static void tegra_dsi_set_phy_timing(struct dsi_timing_reg *ptiming,
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writel(value, &ptiming->dsi_bta_timing);
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}
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static void tegra_dsi_ganged_enable(struct udevice *dev, unsigned int start,
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unsigned int size)
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{
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struct tegra_dsi_priv *priv = dev_get_priv(dev);
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struct dsi_ganged_mode_reg *ganged = &priv->dsi->ganged;
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writel(start, &ganged->ganged_mode_start);
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writel(size << 16 | size, &ganged->ganged_mode_size);
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writel(DSI_GANGED_MODE_CONTROL_ENABLE, &ganged->ganged_mode_ctrl);
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}
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static void tegra_dsi_configure(struct udevice *dev,
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unsigned long mode_flags)
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{
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@ -679,9 +695,19 @@ static void tegra_dsi_configure(struct udevice *dev,
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writel(hact << 16 | hbp, &len->dsi_pkt_len_2_3);
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writel(hfp, &len->dsi_pkt_len_4_5);
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writel(0x0f0f << 16, &len->dsi_pkt_len_6_7);
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/* set SOL delay (for non-burst mode only) */
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writel(8 * mul / div, &misc->dsi_sol_delay);
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} else {
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/* 1 byte (DCS command) + pixel data */
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value = 1 + timing->hactive.typ * mul / div;
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if (priv->master || priv->slave) {
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/*
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* For ganged mode, assume symmetric left-right mode.
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*/
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value = 1 + (timing->hactive.typ / 2) * mul / div;
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} else {
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/* 1 byte (DCS command) + pixel data */
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value = 1 + timing->hactive.typ * mul / div;
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}
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writel(0, &len->dsi_pkt_len_0_1);
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writel(value << 16, &len->dsi_pkt_len_2_3);
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@ -691,10 +717,40 @@ static void tegra_dsi_configure(struct udevice *dev,
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value = MIPI_DCS_WRITE_MEMORY_START << 8 |
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MIPI_DCS_WRITE_MEMORY_CONTINUE;
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writel(value, &len->dsi_dcs_cmds);
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/* set SOL delay */
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if (priv->master || priv->slave) {
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unsigned long delay, bclk, bclk_ganged;
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unsigned int lanes = device->lanes;
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unsigned long htotal = timing->hactive.typ + timing->hfront_porch.typ +
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timing->hback_porch.typ + timing->hsync_len.typ;
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/* SOL to valid, valid to FIFO and FIFO write delay */
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delay = 4 + 4 + 2;
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delay = DIV_ROUND_UP(delay * mul, div * lanes);
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/* FIFO read delay */
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delay = delay + 6;
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bclk = DIV_ROUND_UP(htotal * mul, div * lanes);
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bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
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value = bclk - bclk_ganged + delay + 20;
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} else {
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/* TODO: revisit for non-ganged mode */
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value = 8 * mul / div;
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}
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writel(value, &misc->dsi_sol_delay);
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}
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/* set SOL delay (for non-burst mode only) */
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writel(8 * mul / div, &misc->dsi_sol_delay);
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if (priv->slave) {
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/*
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* TODO: Support modes other than symmetrical left-right
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* split.
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*/
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tegra_dsi_ganged_enable(dev, 0, timing->hactive.typ / 2);
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tegra_dsi_ganged_enable(priv->slave, timing->hactive.typ / 2,
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timing->hactive.typ / 2);
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}
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}
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static int tegra_dsi_encoder_enable(struct udevice *dev)
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@ -774,6 +830,9 @@ static int tegra_dsi_encoder_enable(struct udevice *dev)
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value |= DSI_POWER_CONTROL_ENABLE;
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writel(value, &misc->dsi_pwr_ctrl);
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if (priv->slave)
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tegra_dsi_encoder_enable(priv->slave);
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return 0;
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}
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@ -803,6 +862,14 @@ static void tegra_dsi_init_clocks(struct udevice *dev)
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unsigned int mul, div;
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unsigned long bclk, plld;
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if (!priv->slave) {
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/* Change DSIB clock parent to match DSIA */
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struct clk_rst_ctlr *clkrst =
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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clrbits_le32(&clkrst->plld2.pll_base, BIT(25)); /* DSIB_CLK_SRC */
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}
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tegra_dsi_get_muldiv(device->format, &mul, &div);
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bclk = (priv->timing.pixelclock.typ * mul) /
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@ -854,6 +921,24 @@ static void tegra_dsi_init_clocks(struct udevice *dev)
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reset_set_enable(priv->dsi_clk, 0);
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}
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static int tegra_dsi_ganged_probe(struct udevice *dev)
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{
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struct tegra_dsi_priv *mpriv = dev_get_priv(dev);
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struct udevice *gangster;
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uclass_get_device_by_phandle(UCLASS_PANEL, dev,
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"nvidia,ganged-mode", &gangster);
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if (gangster) {
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/* Ganged mode is set */
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struct tegra_dsi_priv *spriv = dev_get_priv(gangster);
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mpriv->slave = gangster;
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spriv->master = dev;
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}
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return 0;
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}
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static int tegra_dsi_bridge_probe(struct udevice *dev)
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{
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struct tegra_dsi_priv *priv = dev_get_priv(dev);
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@ -873,6 +958,8 @@ static int tegra_dsi_bridge_probe(struct udevice *dev)
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priv->video_fifo_depth = 1920;
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priv->host_fifo_depth = 64;
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tegra_dsi_ganged_probe(dev);
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ret = reset_get_by_name(dev, "dsi", &reset_ctl);
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if (ret) {
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log_debug("%s: reset_get_by_name() failed: %d\n",
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@ -98,9 +98,9 @@ struct dsi_timeout_reg {
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uint dsi_to_tally; /* _DSI_TO_TALLY_0 */
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};
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/* DSI PAD control register 0x04b ~ 0x04e */
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/* DSI PAD control register 0x04b ~ 0x052 */
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struct dsi_pad_ctrl_reg {
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/* Address 0x04b ~ 0x04e */
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/* Address 0x04b ~ 0x052 */
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uint pad_ctrl; /* _PAD_CONTROL_0 */
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uint pad_ctrl_cd; /* _PAD_CONTROL_CD_0 */
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uint pad_cd_status; /* _PAD_CD_STATUS_0 */
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@ -111,6 +111,14 @@ struct dsi_pad_ctrl_reg {
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uint pad_ctrl_4; /* _PAD_CONTROL_4 */
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};
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/* DSI ganged mode register 0x053 ~ 0x04e */
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struct dsi_ganged_mode_reg {
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/* Address 0x053 ~ 0x055 */
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uint ganged_mode_ctrl; /* _DSI_GANGED_MODE_CONTROL_0 */
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uint ganged_mode_start; /* _DSI_GANGED_MODE_START_0 */
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uint ganged_mode_size; /* _DSI_GANGED_MODE_SIZE_0 */
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};
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/* Display Serial Interface (DSI_) regs */
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struct dsi_ctlr {
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struct dsi_syncpt_reg syncpt; /* SYNCPT register 0x000 ~ 0x002 */
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@ -133,6 +141,7 @@ struct dsi_ctlr {
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uint reserved5[4]; /* reserved_5[4] */
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struct dsi_pad_ctrl_reg pad; /* PAD registers 0x04b ~ 0x04e */
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struct dsi_ganged_mode_reg ganged; /* GANGED registers 0x053 ~ 0x055 */
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};
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#define DSI_POWER_CONTROL_ENABLE BIT(0)
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@ -202,6 +211,8 @@ struct dsi_ctlr {
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#define DSI_PAD_PREEMP_PD(x) (((x) & 0x3) << 4)
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#define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0)
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#define DSI_GANGED_MODE_CONTROL_ENABLE BIT(0)
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/*
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* pixel format as used in the DSI_CONTROL_FORMAT field
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*/
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