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clk: renesas: Synchronize Gen3 tables with Linux 5.0

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Synchronize R-Car Gen3 clock tables with Linux 5.0,
commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Marek Vasut 2019-03-04 21:38:10 +01:00 • committed by Marek Vasut
parent a3c31e98a1
commit 72242e5439
11 changed files with 226 additions and 152 deletions
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4
drivers/clk/renesas/clk-rcar-gen3.c
View file

@ -96,7 +96,7 @@ static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk,
if (ret) if (ret)
return ret; return ret;
if (core->type == CLK_TYPE_GEN3_PE) { if (core->type == CLK_TYPE_GEN3_MDSEL) {
parent->dev = clk->dev; parent->dev = clk->dev;
parent->id = core->parent >> (priv->sscg ? 16 : 0); parent->id = core->parent >> (priv->sscg ? 16 : 0);
parent->id &= 0xffff; parent->id &= 0xffff;
@ -257,7 +257,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
core->parent, core->mult, core->div, rate); core->parent, core->mult, core->div, rate);
return rate; return rate;
case CLK_TYPE_GEN3_PE: case CLK_TYPE_GEN3_MDSEL:
div = (core->div >> (priv->sscg ? 16 : 0)) & 0xffff; div = (core->div >> (priv->sscg ? 16 : 0)) & 0xffff;
rate = gen3_clk_get_rate64(&parent) / div; rate = gen3_clk_get_rate64(&parent) / div;
debug("%s[%i] PE clk: parent=%i div=%u => rate=%llu\n", debug("%s[%i] PE clk: parent=%i div=%u => rate=%llu\n",

81
drivers/clk/renesas/r8a7795-cpg-mssr.c
View file

@ -1,13 +1,12 @@
// SPDX-License-Identifier: GPL-2.0+ // SPDX-License-Identifier: GPL-2.0
/* /*
* Renesas R8A7795 CPG MSSR driver * r8a7795 Clock Pulse Generator / Module Standby and Software Reset
* *
* Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com> * Copyright (C) 2015 Glider bvba
* *
* Based on the following driver from Linux kernel: * Based on clk-rcar-gen3.c
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
* *
* Copyright (C) 2016 Glider bvba * Copyright (C) 2015 Renesas Electronics Corp.
*/ */
#include <common.h> #include <common.h>
@ -71,7 +70,11 @@ static const struct cpg_core_clk r8a7795_core_clks[] = {
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1), DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
/* Core Clock Outputs */ /* Core Clock Outputs */
DEF_BASE("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
DEF_BASE("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1), DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@ -101,9 +104,16 @@ static const struct cpg_core_clk r8a7795_core_clks[] = {
DEF_GEN3_RPC("rpc", R8A7795_CLK_RPC, CLK_RPCSRC, 0x238), DEF_GEN3_RPC("rpc", R8A7795_CLK_RPC, CLK_RPCSRC, 0x238),
DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cr", R8A7795_CLK_CR, CLK_PLL1_DIV4, 2, 1),
DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1), DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("cpex", R8A7795_CLK_CPEX, CLK_EXTAL, 2, 1),
/* NOTE: HDMI, CSI, CAN etc. clock are missing */ DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
DEF_GEN3_OSC("osc", R8A7795_CLK_OSC, CLK_EXTAL, 8),
DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
}; };
@ -124,6 +134,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3), DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3),
DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3), DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3),
DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3), DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3),
DEF_MOD("sceg-pub", 229, R8A7795_CLK_CR),
DEF_MOD("cmt3", 300, R8A7795_CLK_R), DEF_MOD("cmt3", 300, R8A7795_CLK_R),
DEF_MOD("cmt2", 301, R8A7795_CLK_R), DEF_MOD("cmt2", 301, R8A7795_CLK_R),
DEF_MOD("cmt1", 302, R8A7795_CLK_R), DEF_MOD("cmt1", 302, R8A7795_CLK_R),
@ -143,7 +154,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1), DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1),
DEF_MOD("rwdt", 402, R8A7795_CLK_R), DEF_MOD("rwdt", 402, R8A7795_CLK_R),
DEF_MOD("intc-ex", 407, R8A7795_CLK_CP), DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1), DEF_MOD("intc-ap", 408, R8A7795_CLK_S0D3),
DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3), DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3),
DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3), DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3),
DEF_MOD("drif7", 508, R8A7795_CLK_S3D2), DEF_MOD("drif7", 508, R8A7795_CLK_S3D2),
@ -269,25 +280,25 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
*/ */
/* /*
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
* 14 13 19 17 (MHz) * 14 13 19 17 (MHz)
*------------------------------------------------------------------- *-------------------------------------------------------------------------
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
* 0 0 1 0 Prohibited setting * 0 0 1 0 Prohibited setting
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
* 0 1 1 0 Prohibited setting * 0 1 1 0 Prohibited setting
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
* 1 0 1 0 Prohibited setting * 1 0 1 0 Prohibited setting
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
* 1 1 1 0 Prohibited setting * 1 1 1 0 Prohibited setting
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
*/ */
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
(((md) & BIT(13)) >> 11) | \ (((md) & BIT(13)) >> 11) | \
@ -295,23 +306,23 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
(((md) & BIT(17)) >> 17)) (((md) & BIT(17)) >> 17))
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = { static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
/* EXTAL div PLL1 mult/div PLL3 mult/div */ /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
{ 1, 192, 1, 192, 1, }, { 1, 192, 1, 192, 1, 16, },
{ 1, 192, 1, 128, 1, }, { 1, 192, 1, 128, 1, 16, },
{ 0, /* Prohibited setting */ }, { 0, /* Prohibited setting */ },
{ 1, 192, 1, 192, 1, }, { 1, 192, 1, 192, 1, 16, },
{ 1, 160, 1, 160, 1, }, { 1, 160, 1, 160, 1, 19, },
{ 1, 160, 1, 106, 1, }, { 1, 160, 1, 106, 1, 19, },
{ 0, /* Prohibited setting */ }, { 0, /* Prohibited setting */ },
{ 1, 160, 1, 160, 1, }, { 1, 160, 1, 160, 1, 19, },
{ 1, 128, 1, 128, 1, }, { 1, 128, 1, 128, 1, 24, },
{ 1, 128, 1, 84, 1, }, { 1, 128, 1, 84, 1, 24, },
{ 0, /* Prohibited setting */ }, { 0, /* Prohibited setting */ },
{ 1, 128, 1, 128, 1, }, { 1, 128, 1, 128, 1, 24, },
{ 2, 192, 1, 192, 1, }, { 2, 192, 1, 192, 1, 32, },
{ 2, 192, 1, 128, 1, }, { 2, 192, 1, 128, 1, 32, },
{ 0, /* Prohibited setting */ }, { 0, /* Prohibited setting */ },
{ 2, 192, 1, 192, 1, }, { 2, 192, 1, 192, 1, 32, },
}; };
static const struct mstp_stop_table r8a7795_mstp_table[] = { static const struct mstp_stop_table r8a7795_mstp_table[] = {

76
drivers/clk/renesas/r8a7796-cpg-mssr.c
View file

@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0+ // SPDX-License-Identifier: GPL-2.0
/* /*
* Renesas R8A7796 CPG MSSR driver * Renesas R8A7796 CPG MSSR driver
* *
@ -8,6 +8,11 @@
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
* *
* Copyright (C) 2016 Glider bvba * Copyright (C) 2016 Glider bvba
*
* Based on r8a7795-cpg-mssr.c
*
* Copyright (C) 2015 Glider bvba
* Copyright (C) 2015 Renesas Electronics Corp.
*/ */
#include <common.h> #include <common.h>
@ -71,7 +76,11 @@ static const struct cpg_core_clk r8a7796_core_clks[] = {
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1), DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
/* Core Clock Outputs */ /* Core Clock Outputs */
DEF_BASE("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
DEF_BASE("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1), DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@ -102,13 +111,20 @@ static const struct cpg_core_clk r8a7796_core_clks[] = {
DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1), DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("cpex", R8A7796_CLK_CPEX, CLK_EXTAL, 2, 1),
/* NOTE: HDMI, CSI, CAN etc. clock are missing */ DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
DEF_DIV6P1("csi0", R8A7796_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
DEF_DIV6P1("mso", R8A7796_CLK_MSO, CLK_PLL1_DIV4, 0x014),
DEF_DIV6P1("hdmi", R8A7796_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
DEF_GEN3_OSC("osc", R8A7796_CLK_OSC, CLK_EXTAL, 8),
DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
}; };
static const struct mssr_mod_clk r8a7796_mod_clks[] = { static const struct mssr_mod_clk r8a7796_mod_clks[] = {
DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
DEF_MOD("scif5", 202, R8A7796_CLK_S3D4), DEF_MOD("scif5", 202, R8A7796_CLK_S3D4),
DEF_MOD("scif4", 203, R8A7796_CLK_S3D4), DEF_MOD("scif4", 203, R8A7796_CLK_S3D4),
DEF_MOD("scif3", 204, R8A7796_CLK_S3D4), DEF_MOD("scif3", 204, R8A7796_CLK_S3D4),
@ -137,7 +153,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = {
DEF_MOD("usb-dmac1", 331, R8A7796_CLK_S3D1), DEF_MOD("usb-dmac1", 331, R8A7796_CLK_S3D1),
DEF_MOD("rwdt", 402, R8A7796_CLK_R), DEF_MOD("rwdt", 402, R8A7796_CLK_R),
DEF_MOD("intc-ex", 407, R8A7796_CLK_CP), DEF_MOD("intc-ex", 407, R8A7796_CLK_CP),
DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1), DEF_MOD("intc-ap", 408, R8A7796_CLK_S0D3),
DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3), DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3),
DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3), DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3),
DEF_MOD("drif7", 508, R8A7796_CLK_S3D2), DEF_MOD("drif7", 508, R8A7796_CLK_S3D2),
@ -242,25 +258,25 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = {
*/ */
/* /*
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
* 14 13 19 17 (MHz) * 14 13 19 17 (MHz)
*------------------------------------------------------------------- *-------------------------------------------------------------------------
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
* 0 0 1 0 Prohibited setting * 0 0 1 0 Prohibited setting
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
* 0 1 1 0 Prohibited setting * 0 1 1 0 Prohibited setting
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
* 1 0 1 0 Prohibited setting * 1 0 1 0 Prohibited setting
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
* 1 1 1 0 Prohibited setting * 1 1 1 0 Prohibited setting
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
*/ */
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
(((md) & BIT(13)) >> 11) | \ (((md) & BIT(13)) >> 11) | \
@ -268,23 +284,23 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = {
(((md) & BIT(17)) >> 17)) (((md) & BIT(17)) >> 17))
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = { static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
/* EXTAL div PLL1 mult/div PLL3 mult/div */ /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
{ 1, 192, 1, 192, 1, }, { 1, 192, 1, 192, 1, 16, },
{ 1, 192, 1, 128, 1, }, { 1, 192, 1, 128, 1, 16, },
{ 0, /* Prohibited setting */ }, { 0, /* Prohibited setting */ },
{ 1, 192, 1, 192, 1, }, { 1, 192, 1, 192, 1, 16, },
{ 1, 160, 1, 160, 1, }, { 1, 160, 1, 160, 1, 19, },
{ 1, 160, 1, 106, 1, }, { 1, 160, 1, 106, 1, 19, },
{ 0, /* Prohibited setting */ }, { 0, /* Prohibited setting */ },
{ 1, 160, 1, 160, 1, }, { 1, 160, 1, 160, 1, 19, },
{ 1, 128, 1, 128, 1, }, { 1, 128, 1, 128, 1, 24, },
{ 1, 128, 1, 84, 1, }, { 1, 128, 1, 84, 1, 24, },
{ 0, /* Prohibited setting */ }, { 0, /* Prohibited setting */ },
{ 1, 128, 1, 128, 1, }, { 1, 128, 1, 128, 1, 24, },
{ 2, 192, 1, 192, 1, }, { 2, 192, 1, 192, 1, 32, },
{ 2, 192, 1, 128, 1, }, { 2, 192, 1, 128, 1, 32, },
{ 0, /* Prohibited setting */ }, { 0, /* Prohibited setting */ },
{ 2, 192, 1, 192, 1, }, { 2, 192, 1, 192, 1, 32, },
}; };
static const struct mstp_stop_table r8a7796_mstp_table[] = { static const struct mstp_stop_table r8a7796_mstp_table[] = {

42
drivers/clk/renesas/r8a77965-cpg-mssr.c
View file

@ -69,7 +69,14 @@ static const struct cpg_core_clk r8a77965_core_clks[] = {
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1), DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
/* Core Clock Outputs */ /* Core Clock Outputs */
DEF_BASE("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED("zx", R8A77965_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED("s0d1", R8A77965_CLK_S0D1, CLK_S0, 1, 1), DEF_FIXED("s0d1", R8A77965_CLK_S0D1, CLK_S0, 1, 1),
DEF_FIXED("s0d2", R8A77965_CLK_S0D2, CLK_S0, 2, 1), DEF_FIXED("s0d2", R8A77965_CLK_S0D2, CLK_S0, 2, 1),
DEF_FIXED("s0d3", R8A77965_CLK_S0D3, CLK_S0, 3, 1), DEF_FIXED("s0d3", R8A77965_CLK_S0D3, CLK_S0, 3, 1),
@ -102,6 +109,10 @@ static const struct cpg_core_clk r8a77965_core_clks[] = {
DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
DEF_DIV6P1("mso", R8A77965_CLK_MSO, CLK_PLL1_DIV4, 0x014), DEF_DIV6P1("mso", R8A77965_CLK_MSO, CLK_PLL1_DIV4, 0x014),
DEF_DIV6P1("hdmi", R8A77965_CLK_HDMI, CLK_PLL1_DIV4, 0x250), DEF_DIV6P1("hdmi", R8A77965_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
DEF_GEN3_OSC("osc", R8A77965_CLK_OSC, CLK_EXTAL, 8),
DEF_BASE("r", R8A77965_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
}; };
static const struct mssr_mod_clk r8a77965_mod_clks[] = { static const struct mssr_mod_clk r8a77965_mod_clks[] = {
@ -119,6 +130,10 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] = {
DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S0D3), DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S0D3),
DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3), DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3),
DEF_MOD("cmt3", 300, R8A77965_CLK_R),
DEF_MOD("cmt2", 301, R8A77965_CLK_R),
DEF_MOD("cmt1", 302, R8A77965_CLK_R),
DEF_MOD("cmt0", 303, R8A77965_CLK_R),
DEF_MOD("scif2", 310, R8A77965_CLK_S3D4), DEF_MOD("scif2", 310, R8A77965_CLK_S3D4),
DEF_MOD("sdif3", 311, R8A77965_CLK_SD3), DEF_MOD("sdif3", 311, R8A77965_CLK_SD3),
DEF_MOD("sdif2", 312, R8A77965_CLK_SD2), DEF_MOD("sdif2", 312, R8A77965_CLK_SD2),
@ -130,6 +145,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] = {
DEF_MOD("usb-dmac0", 330, R8A77965_CLK_S3D1), DEF_MOD("usb-dmac0", 330, R8A77965_CLK_S3D1),
DEF_MOD("usb-dmac1", 331, R8A77965_CLK_S3D1), DEF_MOD("usb-dmac1", 331, R8A77965_CLK_S3D1),
DEF_MOD("rwdt", 402, R8A77965_CLK_R),
DEF_MOD("intc-ex", 407, R8A77965_CLK_CP), DEF_MOD("intc-ex", 407, R8A77965_CLK_CP),
DEF_MOD("intc-ap", 408, R8A77965_CLK_S0D3), DEF_MOD("intc-ap", 408, R8A77965_CLK_S0D3),
@ -266,23 +282,23 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] = {
(((md) & BIT(17)) >> 17)) (((md) & BIT(17)) >> 17))
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = { static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
/* EXTAL div PLL1 mult/div PLL3 mult/div */ /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
{ 1, 192, 1, 192, 1, }, { 1, 192, 1, 192, 1, 16, },
{ 1, 192, 1, 128, 1, }, { 1, 192, 1, 128, 1, 16, },
{ 0, /* Prohibited setting */ }, { 0, /* Prohibited setting */ },
{ 1, 192, 1, 192, 1, }, { 1, 192, 1, 192, 1, 16, },
{ 1, 160, 1, 160, 1, }, { 1, 160, 1, 160, 1, 19, },
{ 1, 160, 1, 106, 1, }, { 1, 160, 1, 106, 1, 19, },
{ 0, /* Prohibited setting */ }, { 0, /* Prohibited setting */ },
{ 1, 160, 1, 160, 1, }, { 1, 160, 1, 160, 1, 19, },
{ 1, 128, 1, 128, 1, }, { 1, 128, 1, 128, 1, 24, },
{ 1, 128, 1, 84, 1, }, { 1, 128, 1, 84, 1, 24, },
{ 0, /* Prohibited setting */ }, { 0, /* Prohibited setting */ },
{ 1, 128, 1, 128, 1, }, { 1, 128, 1, 128, 1, 24, },
{ 2, 192, 1, 192, 1, }, { 2, 192, 1, 192, 1, 32, },
{ 2, 192, 1, 128, 1, }, { 2, 192, 1, 128, 1, 32, },
{ 0, /* Prohibited setting */ }, { 0, /* Prohibited setting */ },
{ 2, 192, 1, 192, 1, }, { 2, 192, 1, 192, 1, 32, },
}; };
static const struct mstp_stop_table r8a77965_mstp_table[] = { static const struct mstp_stop_table r8a77965_mstp_table[] = {

37
drivers/clk/renesas/r8a77990-cpg-mssr.c
View file

@ -1,13 +1,13 @@
// SPDX-License-Identifier: GPL-2.0+ // SPDX-License-Identifier: GPL-2.0
/* /*
* Renesas R8A77990 CPG MSSR driver * r8a77990 Clock Pulse Generator / Module Standby and Software Reset
* *
* Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com> * Copyright (C) 2018 Renesas Electronics Corp.
* *
* Based on the following driver from Linux kernel: * Based on r8a7795-cpg-mssr.c
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
* *
* Copyright (C) 2016 Glider bvba * Copyright (C) 2015 Glider bvba
* Copyright (C) 2015 Renesas Electronics Corp.
*/ */
#include <common.h> #include <common.h>
@ -44,6 +44,8 @@ enum clk_ids {
CLK_S3, CLK_S3,
CLK_SDSRC, CLK_SDSRC,
CLK_RPCSRC, CLK_RPCSRC,
CLK_RINT,
CLK_OCO,
/* Module Clocks */ /* Module Clocks */
MOD_CLK_BASE MOD_CLK_BASE
@ -73,6 +75,10 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1), DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
/* Core Clock Outputs */ /* Core Clock Outputs */
DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1), DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1),
DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1), DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1),
@ -103,10 +109,10 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1), DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1),
DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1), DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("cpex", R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1), DEF_FIXED("cpex", R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1),
DEF_FIXED("osc", R8A77990_CLK_OSC, CLK_EXTAL, 384, 1),
DEF_FIXED("r", R8A77990_CLK_R, CLK_EXTAL, 1536, 1),
DEF_GEN3_PE("s0d6c", R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 6), DEF_DIV6_RO("osc", R8A77990_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
DEF_GEN3_PE("s0d6c", R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2),
DEF_GEN3_PE("s3d1c", R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1), DEF_GEN3_PE("s3d1c", R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
DEF_GEN3_PE("s3d2c", R8A77990_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2), DEF_GEN3_PE("s3d2c", R8A77990_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
DEF_GEN3_PE("s3d4c", R8A77990_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4), DEF_GEN3_PE("s3d4c", R8A77990_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
@ -114,6 +120,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
DEF_DIV6P1("canfd", R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244), DEF_DIV6P1("canfd", R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244),
DEF_DIV6P1("csi0", R8A77990_CLK_CSI0, CLK_PLL1D2, 0x00c), DEF_DIV6P1("csi0", R8A77990_CLK_CSI0, CLK_PLL1D2, 0x00c),
DEF_DIV6P1("mso", R8A77990_CLK_MSO, CLK_PLL1D2, 0x014), DEF_DIV6P1("mso", R8A77990_CLK_MSO, CLK_PLL1D2, 0x014),
DEF_GEN3_RCKSEL("r", R8A77990_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
}; };
static const struct mssr_mod_clk r8a77990_mod_clks[] = { static const struct mssr_mod_clk r8a77990_mod_clks[] = {
@ -178,12 +186,10 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
DEF_MOD("ehci0", 703, R8A77990_CLK_S3D4), DEF_MOD("ehci0", 703, R8A77990_CLK_S3D4),
DEF_MOD("hsusb", 704, R8A77990_CLK_S3D4), DEF_MOD("hsusb", 704, R8A77990_CLK_S3D4),
DEF_MOD("csi40", 716, R8A77990_CLK_CSI0), DEF_MOD("csi40", 716, R8A77990_CLK_CSI0),
DEF_MOD("du1", 723, R8A77990_CLK_S2D1), DEF_MOD("du1", 723, R8A77990_CLK_S1D1),
DEF_MOD("du0", 724, R8A77990_CLK_S2D1), DEF_MOD("du0", 724, R8A77990_CLK_S1D1),
DEF_MOD("lvds", 727, R8A77990_CLK_S2D1), DEF_MOD("lvds", 727, R8A77990_CLK_S2D1),
DEF_MOD("vin7", 804, R8A77990_CLK_S1D2),
DEF_MOD("vin6", 805, R8A77990_CLK_S1D2),
DEF_MOD("vin5", 806, R8A77990_CLK_S1D2), DEF_MOD("vin5", 806, R8A77990_CLK_S1D2),
DEF_MOD("vin4", 807, R8A77990_CLK_S1D2), DEF_MOD("vin4", 807, R8A77990_CLK_S1D2),
DEF_MOD("etheravb", 812, R8A77990_CLK_S3D2), DEF_MOD("etheravb", 812, R8A77990_CLK_S3D2),
@ -208,6 +214,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
DEF_MOD("i2c1", 930, R8A77990_CLK_S3D2), DEF_MOD("i2c1", 930, R8A77990_CLK_S3D2),
DEF_MOD("i2c0", 931, R8A77990_CLK_S3D2), DEF_MOD("i2c0", 931, R8A77990_CLK_S3D2),
DEF_MOD("i2c7", 1003, R8A77990_CLK_S3D2),
DEF_MOD("ssi-all", 1005, R8A77990_CLK_S3D4), DEF_MOD("ssi-all", 1005, R8A77990_CLK_S3D4),
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
@ -243,8 +250,8 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
/* /*
* MD19 EXTAL (MHz) PLL0 PLL1 PLL3 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
*-------------------------------------------------------------------- *--------------------------------------------------------------------
* 0 48 x 1 x100/4 x100/3 x100/3 * 0 48 x 1 x100/1 x100/3 x100/3
* 1 48 x 1 x100/4 x100/3 x58/3 * 1 48 x 1 x100/1 x100/3 x58/3
*/ */
#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19) #define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)

44
drivers/clk/renesas/r8a77995-cpg-mssr.c
View file

@ -1,13 +1,13 @@
// SPDX-License-Identifier: GPL-2.0+ // SPDX-License-Identifier: GPL-2.0
/* /*
* Renesas R8A77995 CPG MSSR driver * r8a77995 Clock Pulse Generator / Module Standby and Software Reset
* *
* Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com> * Copyright (C) 2017 Glider bvba
* *
* Based on the following driver from Linux kernel: * Based on r8a7795-cpg-mssr.c
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
* *
* Copyright (C) 2016 Glider bvba * Copyright (C) 2015 Glider bvba
* Copyright (C) 2015 Renesas Electronics Corp.
*/ */
#include <common.h> #include <common.h>
@ -21,7 +21,7 @@
enum clk_ids { enum clk_ids {
/* Core Clock Outputs exported to DT */ /* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A77995_CLK_CP, LAST_DT_CORE_CLK = R8A77995_CLK_CPEX,
/* External Input Clocks */ /* External Input Clocks */
CLK_EXTAL, CLK_EXTAL,
@ -42,7 +42,8 @@ enum clk_ids {
CLK_S3, CLK_S3,
CLK_SDSRC, CLK_SDSRC,
CLK_RPCSRC, CLK_RPCSRC,
CLK_SSPSRC, CLK_RINT,
CLK_OCO,
/* Module Clocks */ /* Module Clocks */
MOD_CLK_BASE MOD_CLK_BASE
@ -70,6 +71,10 @@ static const struct cpg_core_clk r8a77995_core_clks[] = {
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1), DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
/* Core Clock Outputs */ /* Core Clock Outputs */
DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1), DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1), DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
@ -88,8 +93,9 @@ static const struct cpg_core_clk r8a77995_core_clks[] = {
DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1), DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1), DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("osc", R8A77995_CLK_OSC, CLK_EXTAL, 384, 1), DEF_FIXED("cpex", R8A77995_CLK_CPEX, CLK_EXTAL, 4, 1),
DEF_FIXED("r", R8A77995_CLK_R, CLK_EXTAL, 1536, 1),
DEF_DIV6_RO("osc", R8A77995_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
DEF_GEN3_RPC("rpc", R8A77995_CLK_RPC, CLK_RPCSRC, 0x238), DEF_GEN3_RPC("rpc", R8A77995_CLK_RPC, CLK_RPCSRC, 0x238),
@ -99,6 +105,11 @@ static const struct cpg_core_clk r8a77995_core_clks[] = {
DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4), DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, CLK_SDSRC, 0x268), DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, CLK_SDSRC, 0x268),
DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244),
DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014),
DEF_GEN3_RCKSEL("r", R8A77995_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
}; };
static const struct mssr_mod_clk r8a77995_mod_clks[] = { static const struct mssr_mod_clk r8a77995_mod_clks[] = {
@ -124,7 +135,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = {
DEF_MOD("usb-dmac1", 331, R8A77995_CLK_S3D1), DEF_MOD("usb-dmac1", 331, R8A77995_CLK_S3D1),
DEF_MOD("rwdt", 402, R8A77995_CLK_R), DEF_MOD("rwdt", 402, R8A77995_CLK_R),
DEF_MOD("intc-ex", 407, R8A77995_CLK_CP), DEF_MOD("intc-ex", 407, R8A77995_CLK_CP),
DEF_MOD("intc-ap", 408, R8A77995_CLK_S3D1), DEF_MOD("intc-ap", 408, R8A77995_CLK_S1D2),
DEF_MOD("audmac0", 502, R8A77995_CLK_S3D1), DEF_MOD("audmac0", 502, R8A77995_CLK_S3D1),
DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C), DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C),
DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C), DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C),
@ -138,12 +149,9 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = {
DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1), DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1),
DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2), DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2),
DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2), DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2),
DEF_MOD("du1", 723, R8A77995_CLK_S2D1), DEF_MOD("du1", 723, R8A77995_CLK_S1D1),
DEF_MOD("du0", 724, R8A77995_CLK_S2D1), DEF_MOD("du0", 724, R8A77995_CLK_S1D1),
DEF_MOD("lvds", 727, R8A77995_CLK_S2D1), DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
DEF_MOD("vin7", 804, R8A77995_CLK_S1D2),
DEF_MOD("vin6", 805, R8A77995_CLK_S1D2),
DEF_MOD("vin5", 806, R8A77995_CLK_S1D2),
DEF_MOD("vin4", 807, R8A77995_CLK_S1D2), DEF_MOD("vin4", 807, R8A77995_CLK_S1D2),
DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2), DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
DEF_MOD("imr0", 823, R8A77995_CLK_S1D2), DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
@ -182,14 +190,14 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = {
* MD19 EXTAL (MHz) PLL0 PLL1 PLL3 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
*-------------------------------------------------------------------- *--------------------------------------------------------------------
* 0 48 x 1 x250/4 x100/3 x100/3 * 0 48 x 1 x250/4 x100/3 x100/3
* 1 48 x 1 x250/4 x100/3 x116/6 * 1 48 x 1 x250/4 x100/3 x58/3
*/ */
#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19) #define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = { static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = {
/* EXTAL div PLL1 mult/div PLL3 mult/div */ /* EXTAL div PLL1 mult/div PLL3 mult/div */
{ 1, 100, 3, 100, 3, }, { 1, 100, 3, 100, 3, },
{ 1, 100, 3, 116, 6, }, { 1, 100, 3, 58, 3, },
}; };
static const struct mstp_stop_table r8a77995_mstp_table[] = { static const struct mstp_stop_table r8a77995_mstp_table[] = {

34
drivers/clk/renesas/rcar-gen3-cpg.h
View file

@ -19,21 +19,43 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN3_PLL3, CLK_TYPE_GEN3_PLL3,
CLK_TYPE_GEN3_PLL4, CLK_TYPE_GEN3_PLL4,
CLK_TYPE_GEN3_SD, CLK_TYPE_GEN3_SD,
CLK_TYPE_GEN3_RPC,
CLK_TYPE_GEN3_R, CLK_TYPE_GEN3_R,
CLK_TYPE_GEN3_PE, CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
CLK_TYPE_GEN3_Z,
CLK_TYPE_GEN3_Z2, CLK_TYPE_GEN3_Z2,
CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
CLK_TYPE_GEN3_RPCSRC,
CLK_TYPE_GEN3_RPC,
CLK_TYPE_GEN3_RPCD2,
/* SoC specific definitions start here */
CLK_TYPE_GEN3_SOC_BASE,
}; };
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \ #define DEF_GEN3_SD(_name, _id, _parent, _offset) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
#define DEF_GEN3_RPC(_name, _id, _parent, _offset) \ #define DEF_GEN3_RPC(_name, _id, _parent, _offset) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset) DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
#define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
(_parent0) << 16 | (_parent1), \
.div = (_div0) << 16 | (_div1), .offset = _md)
#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \ #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
_div_clean) \ _div_clean) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE, \ DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
(_parent_sscg) << 16 | (_parent_clean), \ _parent_clean, _div_clean)
.div = (_div_sscg) << 16 | (_div_clean))
#define DEF_GEN3_OSC(_name, _id, _parent, _div) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
#define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \
(_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1))
struct rcar_gen3_cpg_pll_config { struct rcar_gen3_cpg_pll_config {
u8 extal_div; u8 extal_div;
@ -41,8 +63,10 @@ struct rcar_gen3_cpg_pll_config {
u8 pll1_div; u8 pll1_div;
u8 pll3_mult; u8 pll3_mult;
u8 pll3_div; u8 pll3_div;
u8 osc_prediv;
}; };
#define CPG_RPCCKCR 0x238
#define CPG_RCKCR 0x240 #define CPG_RCKCR 0x240
struct gen3_clk_priv { struct gen3_clk_priv {

3
drivers/clk/renesas/renesas-cpg-mssr.h
View file

@ -57,6 +57,7 @@ enum clk_types {
CLK_TYPE_FF, /* Fixed Factor Clock */ CLK_TYPE_FF, /* Fixed Factor Clock */
CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */ CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */ CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
CLK_TYPE_FR, /* Fixed Rate Clock */
/* Custom definitions start here */ /* Custom definitions start here */
CLK_TYPE_CUSTOM, CLK_TYPE_CUSTOM,
@ -75,6 +76,8 @@ enum clk_types {
DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset) DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1) DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
#define DEF_RATE(_name, _id, _rate) \
DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)
/* /*
* Definitions of Module Clocks * Definitions of Module Clocks

10
include/dt-bindings/clock/r8a7795-cpg-mssr.h
View file

@ -1,10 +1,6 @@
/* /* SPDX-License-Identifier: GPL-2.0+
* Copyright (C) 2015 Renesas Electronics Corp.
* *
* This program is free software; you can redistribute it and/or modify * Copyright (C) 2015 Renesas Electronics Corp.
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/ */
#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ #ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ #define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
@ -54,7 +50,7 @@
#define R8A7795_CLK_CANFD 39 #define R8A7795_CLK_CANFD 39
#define R8A7795_CLK_HDMI 40 #define R8A7795_CLK_HDMI 40
#define R8A7795_CLK_CSI0 41 #define R8A7795_CLK_CSI0 41
#define R8A7795_CLK_CSIREF 42 /* CLK_CSIREF was removed */
#define R8A7795_CLK_CP 43 #define R8A7795_CLK_CP 43
#define R8A7795_CLK_CPEX 44 #define R8A7795_CLK_CPEX 44
#define R8A7795_CLK_R 45 #define R8A7795_CLK_R 45

10
include/dt-bindings/clock/r8a7796-cpg-mssr.h
View file

@ -1,10 +1,6 @@
/* /* SPDX-License-Identifier: GPL-2.0+
* Copyright (C) 2016 Renesas Electronics Corp.
* *
* This program is free software; you can redistribute it and/or modify * Copyright (C) 2016 Renesas Electronics Corp.
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/ */
#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ #ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ #define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
@ -60,7 +56,7 @@
#define R8A7796_CLK_CANFD 45 #define R8A7796_CLK_CANFD 45
#define R8A7796_CLK_HDMI 46 #define R8A7796_CLK_HDMI 46
#define R8A7796_CLK_CSI0 47 #define R8A7796_CLK_CSI0 47
#define R8A7796_CLK_CSIREF 48 /* CLK_CSIREF was removed */
#define R8A7796_CLK_CP 49 #define R8A7796_CLK_CP 49
#define R8A7796_CLK_CPEX 50 #define R8A7796_CLK_CPEX 50
#define R8A7796_CLK_R 51 #define R8A7796_CLK_R 51

13
include/dt-bindings/clock/r8a77995-cpg-mssr.h
View file

@ -1,10 +1,6 @@
/* /* SPDX-License-Identifier: GPL-2.0+
* Copyright (C) 2017 Glider bvba
* *
* This program is free software; you can redistribute it and/or modify * Copyright (C) 2017 Glider bvba
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/ */
#ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ #ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ #define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
@ -39,8 +35,8 @@
#define R8A77995_CLK_CRD2 24 #define R8A77995_CLK_CRD2 24
#define R8A77995_CLK_SD0H 25 #define R8A77995_CLK_SD0H 25
#define R8A77995_CLK_SD0 26 #define R8A77995_CLK_SD0 26
#define R8A77995_CLK_SSP2 27 /* CLK_SSP2 was removed */
#define R8A77995_CLK_SSP1 28 /* CLK_SSP1 was removed */
#define R8A77995_CLK_RPC 29 #define R8A77995_CLK_RPC 29
#define R8A77995_CLK_RPCD2 30 #define R8A77995_CLK_RPCD2 30
#define R8A77995_CLK_ZA2 31 #define R8A77995_CLK_ZA2 31
@ -53,5 +49,6 @@
#define R8A77995_CLK_LV0 38 #define R8A77995_CLK_LV0 38
#define R8A77995_CLK_LV1 39 #define R8A77995_CLK_LV1 39
#define R8A77995_CLK_CP 40 #define R8A77995_CLK_CP 40
#define R8A77995_CLK_CPEX 41
#endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */ #endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */