Prepare v2021.01-rc5

2025-04-17 02:15:02 +00:00 · 2021-01-05 16:20:26 -05:00 · 2021-01-05 16:20:26 -05:00 · 720620e691
commit 720620e691
parent c86b18074c 62b07b5173
445 changed files with 8260 additions and 4561 deletions
--- a/.mailmap
+++ b/.mailmap
@ -30,7 +30,10 @@ Jagan Teki <jaganna@xilinx.com>
 Jagan Teki <jagannadh.teki@gmail.com>
 Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
 Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@linaro.org>
+Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@toradex.com>
 Markus Klotzbuecher <mk@denx.de>
+Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com>
+Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com>
 Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
 Prabhakar Kushwaha <prabhakar@freescale.com>
 Rajeshwari Shinde <rajeshwari.s@samsung.com>
--- a/.travis.yml
+++ b/.travis.yml
@ -1,698 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-# Copyright Roger Meier <r.meier@siemens.com>
-
-# build U-Boot on Travis CI - https://travis-ci.org/
-
-sudo: required
-dist: bionic
-
-language: c
-
-addons:
-  apt:
-    update: true
-    sources:
-    - sourceline: 'deb http://apt.llvm.org/bionic/ llvm-toolchain-bionic-10 main'
-      key_url: 'https://apt.llvm.org/llvm-snapshot.gpg.key'
-    packages:
-    - autopoint
-    - cppcheck
-    - sloccount
-    - sparse
-    - bc
-    - build-essential
-    - libsdl2-dev
-    - python
-    - python3-sphinx
-    - python3-virtualenv
-    - python3-pip
-    - python3-pygit2
-    - swig
-    - libpython-dev
-    - iasl
-    - grub-efi-ia32-bin
-    - grub-efi-amd64-bin
-    - rpm2cpio
-    - wget
-    - device-tree-compiler
-    - lzop
-    - liblz4-tool
-    - lzma-alone
-    - libisl15
-    - clang-10
-    - srecord
-    - graphviz
-    - coreutils
-    - util-linux
-    - dosfstools
-    - gdisk
-    - mount
-    - mtools
-    - openssl
-    - sbsigntool
-    - fakeroot
-    - mtd-utils
-    - squashfs-tools
-
-install:
- # Clone uboot-test-hooks
- - git clone --depth=1 git://github.com/swarren/uboot-test-hooks.git /tmp/uboot-test-hooks
- - ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
- - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
- # prepare buildman environment
- - echo -e "[toolchain]\nroot = /usr" > ~/.buildman
- - echo -e "arc = /tmp/arc_gnu_2019.09_prebuilt_uclibc_le_archs_linux_install" >> ~/.buildman
- - echo -e "\n[toolchain-alias]\nsh = sh2" >> ~/.buildman
- - echo -e "x86 = i386" >> ~/.buildman;
- - echo -e "riscv = riscv64" >> ~/.buildman;
- - cat ~/.buildman
- - grub-mkimage --prefix="" -o ~/grub_x86.efi -O i386-efi normal  echo lsefimmap lsefi lsefisystab efinet tftp minicmd
- - grub-mkimage --prefix="" -o ~/grub_x64.efi -O x86_64-efi normal  echo lsefimmap lsefi lsefisystab efinet tftp minicmd
- - wget http://mirrors.kernel.org/ubuntu/pool/main/m/mpfr4/libmpfr4_3.1.4-1_amd64.deb && sudo dpkg -i libmpfr4_3.1.4-1_amd64.deb && rm libmpfr4_3.1.4-1_amd64.deb
- - wget http://mirrors.kernel.org/ubuntu/pool/universe/e/efitools/efitools_1.8.1-0ubuntu2_amd64.deb && sudo dpkg -i efitools_1.8.1-0ubuntu2_amd64.deb && rm efitools_1.8.1-0ubuntu2_amd64.deb
-
-env:
-  global:
-    - PATH=/tmp/qemu-install/bin:/tmp/uboot-test-hooks/bin:/sbin:/usr/bin:/bin:/usr/local/bin
-    - PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci
-    - BUILD_DIR=build
-    - HOSTCC="cc"
-    - HOSTCXX="c++"
-    - QEMU_VERSION="v4.2.0"
-
-before_script:
-  # install toolchains based on TOOLCHAIN} variable
-  - if [[ "${TOOLCHAIN}" == *m68k* ]]; then ./tools/buildman/buildman --fetch-arch m68k ; fi
-  - if [[ "${TOOLCHAIN}" == *microblaze* ]]; then ./tools/buildman/buildman --fetch-arch microblaze ; fi
-  - if [[ "${TOOLCHAIN}" == *mips* ]]; then ./tools/buildman/buildman --fetch-arch mips ; fi
-  - if [[ "${TOOLCHAIN}" == *sh* ]]; then ./tools/buildman/buildman --fetch-arch sh2 ; fi
-  - if [[ "${TOOLCHAIN}" == *i386* ]]; then
-      ./tools/buildman/buildman --fetch-arch i386;
-    fi
-  - if [[ "${TOOLCHAIN}" == arc ]]; then
-       wget https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2019.09-release/arc_gnu_2019.09_prebuilt_uclibc_le_archs_linux_install.tar.gz &&
-       tar -C /tmp -xf arc_gnu_2019.09_prebuilt_uclibc_le_archs_linux_install.tar.gz;
-    fi
-  - if [[ "${TOOLCHAIN}" == "nds32" ]]; then
-       wget https://github.com/vincentzwc/prebuilt-nds32-toolchain/releases/download/20180521/nds32le-linux-glibc-v3-upstream.tar.gz &&
-       tar -C /tmp -xf nds32le-linux-glibc-v3-upstream.tar.gz &&
-       echo -e "\n[toolchain-prefix]\nnds32 = /tmp/nds32le-linux-glibc-v3-upstream/bin/nds32le-linux-" >> ~/.buildman;
-    fi
-  - if [[ "${TOOLCHAIN}" == *xtensa* ]]; then
-       wget https://github.com/foss-xtensa/toolchain/releases/download/2018.02/x86_64-2018.02-${TOOLCHAIN}.tar.gz &&
-       tar -C /tmp -xf x86_64-2018.02-${TOOLCHAIN}.tar.gz &&
-       echo -e "\n[toolchain-prefix]\nxtensa = /tmp/2018.02/${TOOLCHAIN}/bin/${TOOLCHAIN}-" >> ~/.buildman;
-    fi
-  # If TOOLCHAIN is unset, we're on some flavour of ARM.
-  - if [[ "${TOOLCHAIN}" == "" ]]; then
-       ./tools/buildman/buildman --fetch-arch arm &&
-       ./tools/buildman/buildman --fetch-arch aarch64;
-    fi
-  - if [[ "${TOOLCHAIN}" == "powerpc" ]]; then ./tools/buildman/buildman --fetch-arch powerpc; fi
-  - if [[ "${TOOLCHAIN}" == "riscv" ]]; then
-       ./tools/buildman/buildman --fetch-arch riscv32 &&
-       ./tools/buildman/buildman --fetch-arch riscv64;
-    fi
-  - if [[ "${QEMU_TARGET}" != "" ]]; then
-       git clone git://git.qemu.org/qemu.git /tmp/qemu;
-       pushd /tmp/qemu;
-       git submodule update --init dtc &&
-       git checkout ${QEMU_VERSION} &&
-       ./configure --prefix=/tmp/qemu-install --target-list=${QEMU_TARGET} &&
-       make -j4 all install;
-       popd;
-    fi
-
-  # Build GRUB UEFI targets
-  - if [[ "${QEMU_TARGET}" == "arm-softmmu" ]]; then
-       git clone git://git.savannah.gnu.org/grub.git /tmp/grub &&
-       pushd /tmp/grub &&
-       git checkout grub-2.04 &&
-       ./bootstrap &&
-       ./configure --target=arm --with-platform=efi
-       CC=gcc
-       TARGET_CC=~/.buildman-toolchains/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc
-       TARGET_OBJCOPY=~/.buildman-toolchains/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-objcopy
-       TARGET_STRIP=~/.buildman-toolchains/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-strip
-       TARGET_NM=~/.buildman-toolchains/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-nm
-       TARGET_RANLIB=~/.buildman-toolchains/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-ranlib &&
-       make -j4 &&
-       ./grub-mkimage -O arm-efi -o ~/grub_arm.efi --prefix= -d
-       grub-core cat chain configfile echo efinet ext2 fat halt help linux
-       lsefisystab loadenv lvm minicmd normal part_msdos part_gpt reboot
-       search search_fs_file search_fs_uuid search_label serial sleep test
-       true &&
-       popd;
-    fi
-  - if [[ "${QEMU_TARGET}" == "aarch64-softmmu" ]]; then
-       git clone git://git.savannah.gnu.org/grub.git /tmp/grub &&
-       pushd /tmp/grub &&
-       git checkout grub-2.04 &&
-       ./bootstrap &&
-       ./configure --target=aarch64 --with-platform=efi
-       CC=gcc
-       TARGET_CC=~/.buildman-toolchains/gcc-9.2.0-nolibc/aarch64-linux/bin/aarch64-linux-gcc
-       TARGET_OBJCOPY=~/.buildman-toolchains/gcc-9.2.0-nolibc/aarch64-linux/bin/aarch64-linux-objcopy
-       TARGET_STRIP=~/.buildman-toolchains/gcc-9.2.0-nolibc/aarch64-linux/bin/aarch64-linux-strip
-       TARGET_NM=~/.buildman-toolchains/gcc-9.2.0-nolibc/aarch64-linux/bin/aarch64-linux-nm
-       TARGET_RANLIB=~/.buildman-toolchains/gcc-9.2.0-nolibc/aarch64-linux/bin/aarch64-linux-ranlib &&
-       make -j4 &&
-       ./grub-mkimage -O arm64-efi -o ~/grub_arm64.efi --prefix= -d
-       grub-core cat chain configfile echo efinet ext2 fat halt help linux
-       lsefisystab loadenv lvm minicmd normal part_msdos part_gpt reboot
-       search search_fs_file search_fs_uuid search_label serial sleep test
-       true &&
-       popd;
-    fi
-  - if [[ "${QEMU_TARGET}" == "riscv32-softmmu" ]]; then
-       git clone git://git.savannah.gnu.org/grub.git /tmp/grub &&
-       pushd /tmp/grub &&
-       git checkout grub-2.04 &&
-       ./bootstrap &&
-       ./configure --target=riscv32 --with-platform=efi
-       CC=gcc
-       TARGET_CC=~/.buildman-toolchains/gcc-9.2.0-nolibc/riscv32-linux/bin/riscv32-linux-gcc
-       TARGET_OBJCOPY=~/.buildman-toolchains/gcc-9.2.0-nolibc/riscv32-linux/bin/riscv32-linux-objcopy
-       TARGET_STRIP=~/.buildman-toolchains/gcc-9.2.0-nolibc/riscv32-linux/bin/riscv32-linux-strip
-       TARGET_NM=~/.buildman-toolchains/gcc-9.2.0-nolibc/riscv32-linux/bin/riscv32-linux-nm
-       TARGET_RANLIB=~/.buildman-toolchains/gcc-9.2.0-nolibc/riscv32-linux/bin/riscv32-linux-ranlib &&
-       make -j4 &&
-       ./grub-mkimage -O riscv32-efi -o ~/grub_riscv32.efi --prefix= -d
-       grub-core cat chain configfile echo efinet ext2 fat halt help linux
-       lsefisystab loadenv lvm minicmd normal part_msdos part_gpt reboot
-       search search_fs_file search_fs_uuid search_label serial sleep test
-       true &&
-       popd;
-    fi
-  - if [[ "${QEMU_TARGET}" == "riscv64-softmmu" ]]; then
-       git clone git://git.savannah.gnu.org/grub.git /tmp/grub &&
-       pushd /tmp/grub &&
-       git checkout grub-2.04 &&
-       ./bootstrap &&
-       ./configure --target=riscv64 --with-platform=efi
-       CC=gcc
-       TARGET_CC=~/.buildman-toolchains/gcc-9.2.0-nolibc/riscv64-linux/bin/riscv64-linux-gcc
-       TARGET_OBJCOPY=~/.buildman-toolchains/gcc-9.2.0-nolibc/riscv64-linux/bin/riscv64-linux-objcopy
-       TARGET_STRIP=~/.buildman-toolchains/gcc-9.2.0-nolibc/riscv64-linux/bin/riscv64-linux-strip
-       TARGET_NM=~/.buildman-toolchains/gcc-9.2.0-nolibc/riscv64-linux/bin/riscv64-linux-nm
-       TARGET_RANLIB=~/.buildman-toolchains/gcc-9.2.0-nolibc/riscv64-linux/bin/riscv64-linux-ranlib &&
-       make -j4 &&
-       ./grub-mkimage -O riscv64-efi -o ~/grub_riscv64.efi --prefix= -d
-       grub-core cat chain configfile echo efinet ext2 fat halt help linux
-       lsefisystab loadenv lvm minicmd normal part_msdos part_gpt reboot
-       search search_fs_file search_fs_uuid search_label serial sleep test
-       true &&
-       popd;
-    fi
-  - if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
-       wget -O - https://github.com/riscv/opensbi/releases/download/v0.8/opensbi-0.8-rv-bin.tar.xz | tar -C /tmp -xJ;
-       export OPENSBI=/tmp/opensbi-0.8-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
-    fi
-  - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]]; then
-       wget -O - https://github.com/riscv/opensbi/releases/download/v0.8/opensbi-0.8-rv-bin.tar.xz | tar -C /tmp -xJ;
-       export OPENSBI=/tmp/opensbi-0.8-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
-    fi
-
-script:
- # Comments must be outside the command strings below, or the Travis parser
- # will get confused.
- #
- # If we've been asked to use clang only do one configuration.
- #
- # Build a selection of boards if TEST_PY_BD is empty
- - if [[ "${BUILDMAN}" != "" ]]; then
-     ret=0
-     tools/buildman/buildman -P -E -W ${BUILDMAN} ${OVERRIDE} || ret=$?;
-     if [[ $ret -ne 0 ]]; then
-       tools/buildman/buildman -seP ${BUILDMAN};
-       exit $ret;
-     fi;
-   fi
- # Build just the one board needed for testing, if TEST_PY_BD is non-empty
- # Note: "${var:+"-k $var"}" expands to "" if $var is empty, "-k $var" if not
- - if [[ "${TEST_PY_BD}" != "" ]]; then
-     export UBOOT_TRAVIS_BUILD_DIR=`cd .. && pwd`/${TEST_PY_BD};
-     cp ~/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/;
-     cp ~/grub_x64.efi $UBOOT_TRAVIS_BUILD_DIR/;
-     if [[ -e ~/grub_arm.efi ]]; then
-       cp ~/grub_arm.efi $UBOOT_TRAVIS_BUILD_DIR/;
-     fi;
-     if [[ -e ~/grub_arm64.efi ]]; then
-       cp ~/grub_arm64.efi $UBOOT_TRAVIS_BUILD_DIR/;
-     fi;
-     if [[ -e ~/grub_riscv32.efi ]]; then
-       cp ~/grub_riscv32.efi $UBOOT_TRAVIS_BUILD_DIR/;
-     fi;
-     if [[ -e ~/grub_riscv64.efi ]]; then
-       cp ~/grub_riscv64.efi $UBOOT_TRAVIS_BUILD_DIR/;
-     fi;
-     tools/buildman/buildman -o ${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e
-       --board ${TEST_PY_BD} ${OVERRIDE} || exit;
-     virtualenv -p /usr/bin/python3 /tmp/venv;
-     . /tmp/venv/bin/activate;
-     pip install -r test/py/requirements.txt;
-     ./test/py/test.py -ra --bd ${TEST_PY_BD} ${TEST_PY_ID}
-       ${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"}
-       --build-dir "$UBOOT_TRAVIS_BUILD_DIR" || exit;
-     if [[ -n "${TEST_PY_TOOLS}" ]]; then
-       export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt";
-       export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}";
-       pip install pyelftools &&
-       ./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test &&
-       ./tools/patman/patman test &&
-       ./tools/buildman/buildman -t &&
-       ./tools/dtoc/dtoc -t &&
-       make testconfig;
-     fi;
-   fi
-
-matrix:
-  include:
-  # we need to build by vendor due to 50min time limit for builds
-  # each env setting here is a dedicated build
-    - name: "buildman arc"
-      env:
-        - BUILDMAN="arc"
-          TOOLCHAIN="arc"
-    - name: "buildman arm11 arm7 arm920t arm946es"
-      env:
-        - BUILDMAN="arm11 arm7 arm920t arm946es"
-    - name: "buildman arm926ejs (non-NXP,siemens,at91,kirkwood,spear)"
-      env:
-        - JOB="arm926ejs"
-          BUILDMAN="arm926ejs -x freescale,siemens,at91,kirkwood,spear,omap"
-    - name: "buildman at91 (non arm v7)"
-      env:
-        - BUILDMAN="at91 -x armv7"
-    - name: "buildman at91 (non arm926ejs)"
-      env:
-        - BUILDMAN="at91 -x arm926ejs"
-    - name: "buildman boundary engicam toradex"
-      env:
-        - BUILDMAN="boundary engicam toradex"
-    - name: "buildman ARM bcm"
-      env:
-        - BUILDMAN="bcm -x mips"
-    - name: "buildman NXP ARM32 (catch-all)"
-      env:
-        - BUILDMAN="freescale -x powerpc,m68k,aarch64,ls101,ls102,ls104,ls108,ls20,lx216"
-    - name: "buildman NXP LS101x"
-      env:
-        - BUILDMAN="freescale&ls101"
-    - name: "buildman NXP LS102x"
-      env:
-        - BUILDMAN="freescale&ls102"
-    - name: "buildman NXP LS104x"
-      env:
-        - BUILDMAN="freescale&ls104"
-    - name: "buildman NXP LS108x"
-      env:
-        - BUILDMAN="freescale&ls108"
-    - name: "buildman NXP LS20xx"
-      env:
-        - BUILDMAN="freescale&ls20"
-    - name: "buildman NXP LX216x"
-      env:
-        - BUILDMAN="freescale&lx216"
-    - name: "buildman i.MX6 tqc"
-      env:
-        - BUILDMAN="mx6&tqc"
-    - name: "buildman i.MX6 (catch-all)"
-      env:
-        - BUILDMAN="mx6 -x boundary,engicam,freescale,technexion,toradex,tqc"
-    - name: "buildman i.MX (non-i.MX6 catch-all)"
-      env:
-        - BUILDMAN="mx -x freescale,mx6,toradex,technexion"
-    - name: "buildman keystone 2/3"
-      env:
-        - BUILDMAN="k2 k3"
-    - name: "buildman samsung socfpga"
-      env:
-        - BUILDMAN="samsung socfpga"
-    - name: "buildman spear"
-      env:
-        - BUILDMAN="spear"
-    - name: "buildman sun4i"
-      env:
-        - BUILDMAN="sun4i"
-    - name: "buildman sun5i"
-      env:
-        - BUILDMAN="sun5i"
-    - name: "buildman sun6i"
-      env:
-        - BUILDMAN="sun6i"
-    - name: "buildman sun7i"
-      env:
-        - BUILDMAN="sun7i"
-    - name: "buildman 64bit sun8i"
-      env:
-        - BUILDMAN="sun8i&aarch64 -x orangepi"
-    - name: "buildman 32bit sun8i"
-      env:
-        - BUILDMAN="sun8i&armv7 -x orangepi"
-    - name: "buildman sun9i"
-      env:
-        - BUILDMAN="sun9i"
-    - name: "buildman sun50i"
-      env:
-        - BUILDMAN="sun50i -x orangepi"
-    - name: "buildman catch-all ARM"
-      env:
-        - BUILDMAN="arm -x arm11,arm7,arm9,aarch64,at91,bcm,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,rk,toradex,socfpga,k2,k3,zynq"
-    - name: "buildman sandbox x86"
-      env:
-        - BUILDMAN="sandbox x86"
-          TOOLCHAIN="i386"
-    - name: "buildman technexion"
-      env:
-        - BUILDMAN="technexion"
-    - name: "buildman kirkwood"
-      env:
-        - BUILDMAN="kirkwood"
-    - name: "buildman mvebu"
-      env:
-        - BUILDMAN="mvebu"
-    - name: "buildman m68k"
-      env:
-        - BUILDMAN="m68k"
-          TOOLCHAIN="m68k"
-    - name: "buildman microblaze"
-      env:
-        - BUILDMAN="microblaze"
-          TOOLCHAIN="microblaze"
-    - name: "buildman mips"
-      env:
-        - BUILDMAN="mips"
-          TOOLCHAIN="mips"
-    - name: "buildman non-Freescale PowerPC"
-      env:
-        - BUILDMAN="powerpc -x freescale"
-          TOOLCHAIN="powerpc"
-    - name: "buildman mpc85xx&freescale (excluding many)"
-      env:
-        - BUILDMAN="mpc85xx&freescale -x t208xrdb -x t4qds -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x b4860qds -x bsc91*"
-          TOOLCHAIN="powerpc"
-    - name: "buildman t208xrdb corenet_ds"
-      env:
-        - BUILDMAN="t208xrdb corenet_ds"
-          TOOLCHAIN="powerpc"
-    - name: "buildman Freescale PowerPC"
-      env:
-        - BUILDMAN="t4qds b4860qds mpc83xx&freescale mpc86xx&freescale"
-          TOOLCHAIN="powerpc"
-    - name: "buildman t102*"
-      env:
-        - BUILDMAN="t102*"
-          TOOLCHAIN="powerpc"
-    - name: "buildman p1_p2_rdb_pc"
-      env:
-        - BUILDMAN="p1_p2_rdb_pc"
-          TOOLCHAIN="powerpc"
-    - name: "buildman p1010rdb bsc91"
-      env:
-        - BUILDMAN="p1010rdb bsc91"
-          TOOLCHAIN="powerpc"
-    - name: "buildman siemens"
-      env:
-        - BUILDMAN="siemens"
-    - name: "buildman tegra"
-      env:
-        - BUILDMAN="tegra -x toradex"
-    - name: "buildman am33xx (no siemens)"
-      env:
-        - BUILDMAN="am33xx -x siemens"
-    - name: "buildman omap"
-      env:
-        - BUILDMAN="omap"
-    - name: "buildman orangepi"
-      env:
-        - BUILDMAN="orangepi"
-    - name: "buildman uniphier"
-      env:
-        - BUILDMAN="uniphier"
-    - name: "buildman catch-all AArch64"
-      env:
-        - BUILDMAN="aarch64 -x bcm,k3,tegra,ls1,ls2,lx216,mvebu,uniphier,sunxi,samsung,socfpga,rk,versal,zynq"
-    - name: "buildman rockchip"
-      env:
-        - BUILDMAN="rk -x orangepi"
-    - name: "buildman sh"
-      env:
-        - BUILDMAN="sh -x arm"
-          TOOLCHAIN="sh"
-    - name: "buildman Zynq* (ARMv7)"
-      env:
-        - BUILDMAN="zynq&armv7"
-    - name: "buildman ZynqMP and Versal"
-      env:
-        - BUILDMAN="versal|zynqmp&aarch64"
-    - name: "buildman xtensa"
-      env:
-        - BUILDMAN="xtensa"
-          TOOLCHAIN="xtensa-dc233c-elf"
-    - name: "buildman riscv"
-      env:
-        - BUILDMAN="riscv"
-          TOOLCHAIN="riscv"
-    - name: "buildman nds32"
-      env:
-        - BUILDMAN="nds32"
-          TOOLCHAIN="nds32"
-
-    # QA jobs for code analytics
-    # static code analysis with cppcheck (we can add --enable=all later)
-    - name: "cppcheck"
-      script:
-        - cppcheck -j$(nproc) --force --quiet --inline-suppr .
-    # build HTML documentation
-    - name: "htmldocs"
-      script:
-        - make htmldocs
-    # search for TODO within source tree
-    - name: "grep TODO"
-      script:
-        - grep -r TODO .
-    # search for FIXME within source tree
-    - name: "grep FIXME HACK"
-      script:
-        - grep -r FIXME .
-    # search for HACK within source tree and ignore HACKKIT board
-      script:
-        - grep -r HACK . | grep -v HACKKIT
-    # some statistics about the code base
-    - name: "sloccount"
-      script:
-        - sloccount .
-    # ensure all configs have MAINTAINERS entries
-    - name: "Check for configs without MAINTAINERS entry"
-      script:
-        - if [ `./tools/genboardscfg.py -f 2>&1 | wc -l` -ne 0 ]; then exit 1; fi
-    # Ensure host tools build
-    - name: "Build tools-only"
-      script:
-        - make tools-only_config tools-only -j$(nproc)
-    # Ensure env tools build
-    - name: "Build envtools"
-      script:
-        - make tools-only_config envtools -j$(nproc)
-
-    - name: "Run tests for Nokia RX-51 (aka N900)"
-      script:
-        - export PATH=~/.buildman-toolchains/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/:$PATH
-        - test/nokia_rx51_test.sh
-
-    # test/py
-    - name: "test/py sandbox"
-      env:
-        - TEST_PY_BD="sandbox"
-          TOOLCHAIN="i386"
-    - name: "test/py sandbox with clang"
-      env:
-        - TEST_PY_BD="sandbox"
-          OVERRIDE="-O clang-10"
-    - name: "test/py sandbox_spl"
-      env:
-        - TEST_PY_BD="sandbox_spl"
-          TEST_PY_TEST_SPEC="test_ofplatdata or test_handoff or test_spl"
-          TOOLCHAIN="i386"
-          TEST_PY_TOOLS="yes"
-    - name: "test/py sandbox_flattree"
-      env:
-        - TEST_PY_BD="sandbox_flattree"
-          TOOLCHAIN="i386"
-    - name: "test/py evb-ast2500"
-      env:
-        - TEST_PY_BD="evb-ast2500"
-          TEST_PY_ID="--id qemu"
-          QEMU_TARGET="arm-softmmu"
-    - name: "test/py vexpress_ca15_tc2"
-      env:
-        - TEST_PY_BD="vexpress_ca15_tc2"
-          TEST_PY_ID="--id qemu"
-          QEMU_TARGET="arm-softmmu"
-    - name: "test/py vexpress_ca9x4"
-      env:
-        - TEST_PY_BD="vexpress_ca9x4"
-          TEST_PY_ID="--id qemu"
-          QEMU_TARGET="arm-softmmu"
-    - name: "test/py integratorcp_cm926ejs"
-      env:
-        - TEST_PY_BD="integratorcp_cm926ejs"
-          TEST_PY_TEST_SPEC="not sleep"
-          TEST_PY_ID="--id qemu"
-          QEMU_TARGET="arm-softmmu"
-    - name: "test/py qemu_arm"
-      env:
-        - TEST_PY_BD="qemu_arm"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="arm-softmmu"
-    - name: "test/py qemu_arm64"
-      env:
-        - TEST_PY_BD="qemu_arm64"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="aarch64-softmmu"
-    - name: "test/py qemu_mips"
-      env:
-        - TEST_PY_BD="qemu_mips"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="mips-softmmu"
-          TOOLCHAIN="mips"
-    - name: "test/py qemu_mipsel"
-      env:
-        - TEST_PY_BD="qemu_mipsel"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="mipsel-softmmu"
-          TOOLCHAIN="mips"
-    - name: "test/py qemu_mips64"
-      env:
-        - TEST_PY_BD="qemu_mips64"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="mips64-softmmu"
-          TOOLCHAIN="mips"
-    - name: "test/py qemu_mips64el"
-      env:
-        - TEST_PY_BD="qemu_mips64el"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="mips64el-softmmu"
-          TOOLCHAIN="mips"
-    - name: "test/py qemu-malta"
-      env:
-        - TEST_PY_BD="malta"
-          TEST_PY_TEST_SPEC="not sleep and not efi"
-          TEST_PY_ID="--id qemu"
-          QEMU_TARGET="mips-softmmu"
-          TOOLCHAIN="mips"
-    - name: "test/py qemu-maltael"
-      env:
-        - TEST_PY_BD="maltael"
-          TEST_PY_TEST_SPEC="not sleep and not efi"
-          TEST_PY_ID="--id qemu"
-          QEMU_TARGET="mipsel-softmmu"
-          TOOLCHAIN="mips"
-    - name: "test/py qemu-malta64"
-      env:
-        - TEST_PY_BD="malta64"
-          TEST_PY_TEST_SPEC="not sleep and not efi"
-          TEST_PY_ID="--id qemu"
-          QEMU_TARGET="mips64-softmmu"
-          TOOLCHAIN="mips"
-    - name: "test/py qemu-malta64el"
-      env:
-        - TEST_PY_BD="malta64el"
-          TEST_PY_TEST_SPEC="not sleep and not efi"
-          TEST_PY_ID="--id qemu"
-          QEMU_TARGET="mips64el-softmmu"
-          TOOLCHAIN="mips"
-    - name: "test/py qemu-ppce500"
-      env:
-        - TEST_PY_BD="qemu-ppce500"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="ppc-softmmu"
-          TOOLCHAIN="powerpc"
-    - name: "test/py qemu-riscv32"
-      env:
-        - TEST_PY_BD="qemu-riscv32"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="riscv32-softmmu"
-          TOOLCHAIN="riscv"
-    - name: "test/py qemu-riscv64"
-      env:
-        - TEST_PY_BD="qemu-riscv64"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="riscv64-softmmu"
-          TOOLCHAIN="riscv"
-    - name: "test/py qemu-riscv32_spl"
-      env:
-        - TEST_PY_BD="qemu-riscv32_spl"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="riscv32-softmmu"
-          TOOLCHAIN="riscv"
-    - name: "test/py qemu-riscv64_spl"
-      env:
-        - TEST_PY_BD="qemu-riscv64_spl"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="riscv64-softmmu"
-          TOOLCHAIN="riscv"
-    - name: "test/py qemu-x86"
-      env:
-        - TEST_PY_BD="qemu-x86"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="i386-softmmu"
-          TOOLCHAIN="i386"
-          BUILD_ROM="yes"
-    - name: "test/py qemu-x86_64"
-      env:
-        - TEST_PY_BD="qemu-x86_64"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="x86_64-softmmu"
-          TOOLCHAIN="i386"
-          BUILD_ROM="yes"
-    - name: "test/py r2dplus_i82557c"
-      env:
-        - TEST_PY_BD="r2dplus"
-          TEST_PY_ID="--id i82557c_qemu"
-          QEMU_TARGET="sh4-softmmu"
-          BUILDMAN="sh -x arm"
-          TOOLCHAIN="sh"
-    - name: "test/py r2dplus_pcnet"
-      env:
-        - TEST_PY_BD="r2dplus"
-          TEST_PY_ID="--id pcnet_qemu"
-          QEMU_TARGET="sh4-softmmu"
-          BUILDMAN="sh -x arm"
-          TOOLCHAIN="sh"
-    - name: "test/py r2dplus_rtl8139"
-      env:
-        - TEST_PY_BD="r2dplus"
-          TEST_PY_ID="--id rtl8139_qemu"
-          QEMU_TARGET="sh4-softmmu"
-          BUILDMAN="sh -x arm"
-          TOOLCHAIN="sh"
-    - name: "test/py r2dplus_tulip"
-      env:
-        - TEST_PY_BD="r2dplus"
-          TEST_PY_ID="--id tulip_qemu"
-          QEMU_TARGET="sh4-softmmu"
-          BUILDMAN="sh -x arm"
-          TOOLCHAIN="sh"
-    - name: "test/py xilinx_zynq_virt"
-      env:
-        - TEST_PY_BD="xilinx_zynq_virt"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="arm-softmmu"
-          TEST_PY_ID="--id qemu"
-    - name: "test/py xilinx_versal_virt"
-      env:
-        - TEST_PY_BD="xilinx_versal_virt"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="aarch64-softmmu"
-          TEST_PY_ID="--id qemu"
-    - name: "test/py xtfpga"
-      env:
-        - TEST_PY_BD="xtfpga"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="xtensa-softmmu"
-          TEST_PY_ID="--id qemu"
-          TOOLCHAIN="xtensa-dc233c-elf"
-
-# TODO make it perfect ;-r
--- a/11
+++ b/11
@ -195,6 +195,7 @@ F:	drivers/watchdog/cortina_wdt.c
 F:	drivers/serial/serial_cortina.c
 F:	drivers/led/led_cortina.c
 F:	drivers/mmc/ca_dw_mmc.c
+F:	drivers/spi/ca_sflash.c
 F:	drivers/i2c/i2c-cortina.c
 F:	drivers/i2c/i2c-cortina.h

@ -385,7 +386,7 @@ F:	drivers/smem/msm_smem.c
 F:	drivers/usb/host/ehci-msm.c

 ARM STI
-M:	Patrice Chotard <patrice.chotard@st.com>
+M:	Patrice Chotard <patrice.chotard@foss.st.com>
 S:	Maintained
 T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git
 F:	arch/arm/mach-sti/
@ -411,8 +412,8 @@ F:	arch/arm/cpu/arm926ejs/spear/
 F:	arch/arm/include/asm/arch-spear/

 ARM STM STM32MP
-M:	Patrick Delaunay <patrick.delaunay@st.com>
-M:	Patrice Chotard <patrice.chotard@st.com>
+M:	Patrick Delaunay <patrick.delaunay@foss.st.com>
+M:	Patrice Chotard <patrice.chotard@foss.st.com>
 L:	uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
 T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git
 S:	Maintained
@ -679,6 +680,7 @@ S:	Maintained
 T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git
 F:	doc/api/efi.rst
 F:	doc/uefi/*
+F:	doc/usage/bootefi.rst
 F:	drivers/rtc/emul_rtc.c
 F:	include/capitalization.h
 F:	include/charset.h
@ -696,6 +698,7 @@ F:	test/unicode_ut.c
 F:	cmd/bootefi.c
 F:	cmd/efidebug.c
 F:	cmd/nvedit_efi.c
+F:	tools/efivar.py
 F:	tools/file2include.c

 EFI VARIABLES VIA OP-TEE
@ -758,6 +761,7 @@ T:	git https://gitlab.denx.de/u-boot/u-boot.git
 F:	common/log*
 F:	cmd/log.c
 F:	doc/develop/logging.rst
+F:	include/log.h
 F:	lib/getopt.c
 F:	test/log/
 F:	test/py/tests/test_log.py
@ -799,6 +803,7 @@ F:	drivers/watchdog/cortina_wdt.c
 F:	drivers/serial/serial_cortina.c
 F:	drivers/led/led_cortina.c
 F:	drivers/mmc/ca_dw_mmc.c
+F:	drivers/spi/ca_sflash.c
 F:	drivers/i2c/i2c-cortina.c
 F:	drivers/i2c/i2c-cortina.h

--- a/2
+++ b/2
@ -3,7 +3,7 @@
 VERSION = 2021
 PATCHLEVEL = 01
 SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION = -rc5
 NAME =

 # *DOCUMENTATION*
--- a/arch/arc/dts/axs10x_mb.dtsi
+++ b/arch/arc/dts/axs10x_mb.dtsi
@ -90,14 +90,15 @@
 		};

 		spi0: spi@0 {
-			compatible = "snps,dw-apb-ssi";
+			compatible = "snps,axs10x-spi", "snps,dw-apb-ssi";
 			reg = <0x0 0x100>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			spi-max-frequency = <4000000>;
 			clocks = <&apbclk>;
 			clock-names = "spi_clk";
-			cs-gpio = <&cs_gpio 0>;
+			num-cs = <1>;
+			cs-gpios = <&cs_gpio 0>;
 			spi_flash@0 {
 				compatible = "jedec,spi-nor";
 				reg = <0>;
--- a/arch/arc/dts/hsdk-common.dtsi
+++ b/arch/arc/dts/hsdk-common.dtsi
@ -128,14 +128,15 @@
 	};

 	spi0: spi@f0020000 {
-		compatible = "snps,dw-apb-ssi";
+		compatible = "snps,hsdk-spi", "snps,dw-apb-ssi";
 		reg = <0xf0020000 0x1000>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		spi-max-frequency = <4000000>;
 		clocks = <&cgu_clk CLK_SYS_SPI_REF>;
 		clock-names = "spi_clk";
-		cs-gpio = <&cs_gpio 0>;
+		num-cs = <1>;
+		cs-gpios = <&cs_gpio 0>;
 		spi_flash@0 {
 			compatible = "jedec,spi-nor";
 			reg = <0>;
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@ -1326,6 +1326,18 @@ config TARGET_LX2160AQDS
 	  is a high-performance development platform that supports the
 	  QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.

+config TARGET_LX2162AQDS
+	bool "Support lx2162aqds"
+	select ARCH_LX2162A
+	select ARCH_MISC_INIT
+	select ARM64
+	select ARMV8_MULTIENTRY
+	select ARCH_SUPPORT_TFABOOT
+	select BOARD_LATE_INIT
+	help
+	  Support for NXP LX2162AQDS platform.
+	  The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
+
 config TARGET_HIKEY
 	bool "Support HiKey 96boards Consumer Edition Platform"
 	select ARM64
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@ -5,11 +5,11 @@ config ARCH_LS1021A
 	select SYS_FSL_ERRATUM_A008378
 	select SYS_FSL_ERRATUM_A008407
 	select SYS_FSL_ERRATUM_A008850
-	select SYS_FSL_ERRATUM_A008997
-	select SYS_FSL_ERRATUM_A009007
-	select SYS_FSL_ERRATUM_A009008
+	select SYS_FSL_ERRATUM_A008997 if USB
+	select SYS_FSL_ERRATUM_A009007 if USB
+	select SYS_FSL_ERRATUM_A009008 if USB
 	select SYS_FSL_ERRATUM_A009663
-	select SYS_FSL_ERRATUM_A009798
+	select SYS_FSL_ERRATUM_A009798 if USB
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_ERRATUM_A010315
 	select SYS_FSL_HAS_CCI400
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@ -115,7 +115,7 @@ config PSCI_RESET
 		   !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
 		   !TARGET_LS1046AFRWY && \
 		   !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
-		   !TARGET_LX2160AQDS && \
+		   !TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \
 		   !ARCH_UNIPHIER && !TARGET_S32V234EVB
 	help
 	  Most armv8 systems have PSCI support enabled in EL3, either through
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@ -208,6 +208,35 @@ config ARCH_LS2080A
 	imply DISTRO_DEFAULTS
 	imply PANIC_HANG

+config ARCH_LX2162A
+	bool
+	select ARMV8_SET_SMPEN
+	select FSL_LSCH3
+	select NXP_LSCH3_2
+	select SYS_HAS_SERDES
+	select SYS_FSL_SRDS_1
+	select SYS_FSL_SRDS_2
+	select SYS_FSL_DDR
+	select SYS_FSL_DDR_LE
+	select SYS_FSL_DDR_VER_50
+	select SYS_FSL_EC1
+	select SYS_FSL_EC2
+	select SYS_FSL_ERRATUM_A050106
+	select SYS_FSL_HAS_RGMII
+	select SYS_FSL_HAS_SEC
+	select SYS_FSL_HAS_CCN508
+	select SYS_FSL_HAS_DDR4
+	select SYS_FSL_SEC_COMPAT_5
+	select SYS_FSL_SEC_LE
+	select ARCH_EARLY_INIT_R
+	select BOARD_EARLY_INIT_F
+	select SYS_I2C_MXC
+	select RESV_RAM if GIC_V3_ITS
+	imply DISTRO_DEFAULTS
+	imply PANIC_HANG
+	imply SCSI
+	imply SCSI_AHCI
+
 config ARCH_LX2160A
 	bool
 	select ARMV8_SET_SMPEN
@ -345,7 +374,7 @@ config SYS_FSL_ERRATUM_A050106
 	help
 	  USB3.0 Receiver needs to enable fixed equalization
 	  for each of PHY instances in an SOC. This is similar
-	  to erratum A-009007, but this one is for LX2160A,
+	  to erratum A-009007, but this one is for LX2160A and LX2162A,
 	  and the register value is different.

 config SYS_FSL_ERRATUM_A010315
@ -362,6 +391,7 @@ config MAX_CPUS
 	default 16 if ARCH_LS2080A
 	default 8 if ARCH_LS1088A
 	default 16 if ARCH_LX2160A
+	default 16 if ARCH_LX2162A
 	default 1
 	help
 	  Set this number to the maximum number of possible CPUs in the SoC.
@ -491,6 +521,7 @@ config SYS_FSL_DUART_CLK_DIV
 	int "DUART clock divider"
 	default 1 if ARCH_LS1043A
 	default 4 if ARCH_LX2160A
+	default 4 if ARCH_LX2162A
 	default 2
 	help
 	  This is the divider that is used to derive DUART clock from Platform
@ -502,6 +533,7 @@ config SYS_FSL_I2C_CLK_DIV
 	default 4 if ARCH_LS1012A
 	default 4 if ARCH_LS1028A
 	default 8 if ARCH_LX2160A
+	default 8 if ARCH_LX2162A
 	default 8 if ARCH_LS1088A
 	default 2
 	help
@ -514,6 +546,7 @@ config SYS_FSL_IFC_CLK_DIV
 	default 4 if ARCH_LS1012A
 	default 4 if ARCH_LS1028A
 	default 8 if ARCH_LX2160A
+	default 8 if ARCH_LX2162A
 	default 8 if ARCH_LS1088A
 	default 2
 	help
@ -560,14 +593,14 @@ config SYS_FSL_EC1
 	bool
 	help
 	  Ethernet controller 1, this is connected to
-	  MAC17 for LX2160A or to MAC3 for other SoCs
+	  MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs
 	  Provides DPAA2 capabilities

 config SYS_FSL_EC2
 	bool
 	help
 	  Ethernet controller 2, this is connected to
-	  MAC18 for LX2160A or to MAC4 for other SoCs
+	  MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs
 	  Provides DPAA2 capabilities

 config SYS_FSL_ERRATUM_A008336
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@ -27,6 +27,11 @@ obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o
 obj-y += icid.o lx2160_ids.o
 endif

+ifneq ($(CONFIG_ARCH_LX2162A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o
+obj-y += icid.o lx2160_ids.o
+endif
+
 ifneq ($(CONFIG_ARCH_LS2080A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
 obj-y += icid.o ls2088_ids.o
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@ -79,6 +79,9 @@ static struct cpu_type cpu_type_list[] = {
 	CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
 	CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
 	CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
+	CPU_TYPE_ENTRY(LX2162A, LX2162A, 16),
+	CPU_TYPE_ENTRY(LX2122A, LX2122A, 12),
+	CPU_TYPE_ENTRY(LX2082A, LX2082A, 8),
 };

 #define EARLY_PGTABLE_SIZE 0x5000
@ -403,7 +406,7 @@ void cpu_name(char *name)
 	for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
 		if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
 			strcpy(name, cpu_type_list[i].name);
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 			if (IS_C_PROCESSOR(svr))
 				strcat(name, "C");
 #endif
@ -1229,7 +1232,7 @@ __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;

 void __efi_runtime reset_cpu(ulong addr)
 {
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 	/* clear the RST_REQ_MSK and SW_RST_REQ */
 	out_le32(rstcr, 0x0);

--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
@ -9,6 +9,7 @@ SoC overview
 	7. LS2081A
 	8. LX2160A
 	9. LS1028A
+	10. LX2162A

 LS1043A
 ---------
@ -379,3 +380,58 @@ The LS1028A SoC includes the following function and features:
  - Layerscape Trust Architecture
  - Service Processor (SP) provides pre-boot initialization and secure-boot
    capabilities
+
+LX2162A
+--------
+The QorIQ LX2162A processor is built on the Layerscape architecture
+combining sixteen ARM A72 processor cores with advanced, high-performance
+datapath acceleration and network, peripheral interfaces required for
+networking, wireless infrastructure, storage, and general-purpose embedded
+applications.
+
+LX2162A is compliant with the Layerscape Chassis Generation 3.2.
+
+The LX2162A SoC includes the following function and features:
+  Sixteen 32-bit / 64-bit ARM v8 A72 CPUs
+  Cache Coherent Interconnect Fabric (CCN508)
+  One 64-bit 2.9GT/s DDR4 SDRAM memory controllers with ECC.
+  Data path acceleration architecture (DPAA2)
+  12 Serdes lanes at up to 25 GHz
+  Ethernet interfaces
+  Support for 10G-SXGMII (aka USXGMII).
+  Support for SGMII (and 1000Base-KX)
+  Support for XFI (and 10GBase-KR)
+  Support for CAUI2 (50G) and 25G-AUI(25G).
+  Support for XLAUI (and 40GBase-KR4) for 40G.
+  Support for two RGMII parallel interfaces.
+  Energy efficient Ethernet support (802.3az)
+  IEEE 1588 support.
+  High-speed peripheral interfaces
+	One PCIe Gen 3.0 8-lane controllers supporting SR-IOV,
+	Two PCIe Gen 3.0 4-lane controllers.
+	Four serial ATA (SATA 3.0) controllers.
+	One USB 3.0 controllers with integrated PHY
+	Two Enhanced secure digital host controllers
+	Two Controller Area Network (CAN) modules
+	Flexible Serial peripheral interface (FlexSPI) controller.
+	Three Serial peripheral interface (SPI) controllers.
+	Eight I2C Controllers.
+	Four PL011 UARTs supporting two 4-pin UART ports or four 2-pin UART ports.
+	General Purpose IO (GPIO)
+  Support for hardware virtualization and partitioning (ARM MMU-500)
+  Support for GIC (ARM GIC-500)
+  QorIQ platform Trust Architecture 3.0
+  One Secure WatchDog timer and one Non-Secure Watchdog timer.
+  ARM Generic Timer
+  Two Flextimers
+  Debug supporting run control, data acquisition, high-speed trace,
+  performance/event monitoring
+  Thermal Monitor Unit (TMU) with +/- 2C accuracy
+  Support for Voltage ID (VID) for yield improvement
+
+LX2162A SoC has 2 more similar SoC personalities
+1)LX2122A, few difference w.r.t. LX2162A:
+       a) Twelve 64-bit ARM v8 Cortex-A72 CPUs
+
+2)LX2082A, few difference w.r.t. LX2162A:
+       a) Eight 64-bit ARM v8 Cortex-A72 CPUs
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@ -400,10 +400,12 @@ void fdt_fixup_remove_jr(void *blob)

 	while (jr_node != -FDT_ERR_NOTFOUND) {
 		reg = (fdt32_t *)fdt_getprop(blob, jr_node, "reg", &len);
-		jr_offset = fdt_read_number(reg, addr_cells);
-		if (jr_offset == used_jr) {
-			fdt_del_node(blob, jr_node);
-			break;
+		if (reg) {
+			jr_offset = fdt_read_number(reg, addr_cells);
+			if (jr_offset == used_jr) {
+				fdt_del_node(blob, jr_node);
+				break;
+			}
 		}
 		jr_node = fdt_node_offset_by_compatible(blob, jr_node,
 							"fsl,sec-v4.0-job-ring");
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2016-2018 NXP
+ * Copyright 2016-2018, 2020 NXP
 * Copyright 2014-2015 Freescale Semiconductor, Inc.
 */

@ -26,7 +26,7 @@ static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
 #endif

 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 int xfi_dpmac[XFI14 + 1];
 int sgmii_dpmac[SGMII18 + 1];
 int a25gaui_dpmac[_25GE10 + 1];
@ -159,7 +159,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
 		else {
 			serdes_prtcl_map[lane_prtcl] = 1;
 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 			if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
 				wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl],
 						 (int)lane_prtcl);
@ -552,7 +552,7 @@ void fsl_serdes_init(void)
 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 	int i , j;

-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 	for (i = XFI1, j = 1; i <= XFI14; i++, j++)
 		xfi_dpmac[i] = j;

--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
 * Copyright 2014-2015, Freescale Semiconductor, Inc.
- * Copyright 2019 NXP Semiconductors
+ * Copyright 2019-2020 NXP
 *
 * Derived from arch/power/cpu/mpc85xx/speed.c
 */
@ -180,7 +180,7 @@ int get_clocks(void)
 #ifdef CONFIG_FSL_ESDHC
 #if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
 	clock = sys_info.freq_cga_m2;
-#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A)
+#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2162A)
 	clock = sys_info.freq_systembus;
 #endif
 	gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV;
--- a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c
@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018 NXP
+ * Copyright 2018, 2020 NXP
 */

 #include <common.h>
@ -11,6 +11,22 @@ struct serdes_config {
 	u8 lanes[SRDS_MAX_LANES];
 };

+#if defined(CONFIG_ARCH_LX2162A)
+static struct serdes_config serdes1_cfg_tbl[] = {
+	/* SerDes 1 */
+	{0x01, {PCIE1, PCIE1, PCIE1, PCIE1 } },
+	{0x02, {SGMII6, SGMII5, SGMII4, SGMII3 } },
+	{0x03, {XFI6, XFI5, XFI4, XFI3 } },
+	{0x09, {SGMII6, SGMII5, SGMII4, PCIE1 } },
+	{0x0B, {SGMII6, SGMII5, PCIE1, PCIE1 } },
+	{0x0F, {_50GE2, _50GE2, _50GE1, _50GE1 } },
+	{0x10, {_25GE6, _25GE5, _50GE1, _50GE1 } },
+	{0x11, {_25GE6, _25GE5, _25GE4, _25GE3 } },
+	{0x12, {_25GE6, _25GE5, XFI4, XFI3 } },
+	{0x14, {_40GE1, _40GE1, _40GE1, _40GE1 } },
+	{}
+};
+#else
 static struct serdes_config serdes1_cfg_tbl[] = {
 	/* SerDes 1 */
 	{0x01, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } },
@ -48,6 +64,7 @@ static struct serdes_config serdes1_cfg_tbl[] = {
 	{0x16, {XFI10, XFI9, PCIE2, PCIE2, XFI6, XFI5, XFI4, XFI3 } },
 	{}
 };
+#endif

 static struct serdes_config serdes2_cfg_tbl[] = {
 	/* SerDes 2 */
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
 * Copyright 2014-2015 Freescale Semiconductor
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
 */

 #include <common.h>
@ -33,13 +33,10 @@
 #include <fsl_validate.h>
 #endif
 #include <fsl_immap.h>
-#ifdef CONFIG_TFABOOT
-#include <env_internal.h>
-#endif
 #include <dm.h>
 #include <dm/device_compat.h>
 #include <linux/err.h>
-#if defined(CONFIG_TFABOOT) || defined(CONFIG_GIC_V3_ITS)
+#ifdef CONFIG_GIC_V3_ITS
 DECLARE_GLOBAL_DATA_PTR;
 #endif

@ -186,7 +183,8 @@ static void erratum_a008997(void)
 	out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)

 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
-	defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A)
+	defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A) || \
+	defined(CONFIG_ARCH_LX2162A)

 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy)	\
 	out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
@ -222,7 +220,7 @@ static void erratum_a009007(void)
 #if defined(CONFIG_FSL_LSCH3)
 static void erratum_a050106(void)
 {
-#if defined(CONFIG_ARCH_LX2160A)
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 	void __iomem *dcsr = (void __iomem *)DCSR_BASE;

 	PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
@ -392,7 +390,8 @@ void fsl_lsch3_early_init_f(void)
 #endif

 #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
-	defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
+	defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \
+	defined(CONFIG_ARCH_LX2162A)
 	set_icids();
 #endif
 }
@ -954,28 +953,12 @@ int board_late_init(void)
 #endif
 #ifdef CONFIG_TFABOOT
 	/*
-	 * check if gd->env_addr is default_environment; then setenv bootcmd
-	 * and mcinitcmd.
+	 * Set bootcmd and mcinitcmd if they don't exist in the environment.
 	 */
-#ifdef CONFIG_SYS_RELOC_GD_ENV_ADDR
-	if (gd->env_addr == (ulong)&default_environment[0]) {
-#else
-	if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) {
-#endif
+	if (!env_get("bootcmd"))
 		fsl_setenv_bootcmd();
+	if (!env_get("mcinitcmd"))
 		fsl_setenv_mcinitcmd();
-	}
-
-	/*
-	 * If the boot mode is secure, default environment is not present then
-	 * setenv command needs to be run by default
-	 */
-#ifdef CONFIG_CHAIN_OF_TRUST
-	if ((fsl_check_boot_mode_secure() == 1)) {
-		fsl_setenv_bootcmd();
-		fsl_setenv_mcinitcmd();
-	}
-#endif
 #endif
 #ifdef CONFIG_QSPI_AHB_INIT
 	qspi_ahb_init();
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@ -204,7 +204,6 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
 dtb-$(CONFIG_ARCH_MVEBU) +=			\
 	armada-3720-db.dtb			\
 	armada-3720-espressobin.dtb		\
-	armada-3720-espressobin-emmc.dtb	\
 	armada-3720-turris-mox.dtb		\
 	armada-3720-uDPU.dtb			\
 	armada-375-db.dtb			\
@ -415,7 +414,11 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 	fsl-lx2160a-qds-19-x-x.dtb \
 	fsl-lx2160a-qds-19-11-x.dtb \
 	fsl-lx2160a-qds-20-x-x.dtb \
-	fsl-lx2160a-qds-20-11-x.dtb
+	fsl-lx2160a-qds-20-11-x.dtb \
+	fsl-lx2162a-qds.dtb\
+	fsl-lx2162a-qds-17-x.dtb\
+	fsl-lx2162a-qds-18-x.dtb\
+	fsl-lx2162a-qds-20-x.dtb
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
 	fsl-ls1043a-qds-lpuart.dtb \
 	fsl-ls1043a-rdb.dtb \
@ -643,14 +646,8 @@ dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \

 ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),)
 dtb-y += \
-	imx6dl-aristainetos2_4.dtb \
-	imx6dl-aristainetos2_7.dtb \
-	imx6dl-aristainetos2b_4.dtb \
-	imx6dl-aristainetos2b_7.dtb \
-	imx6dl-aristainetos2b_csl_4.dtb \
-	imx6dl-aristainetos2b_csl_7.dtb \
-	imx6dl-aristainetos2c_4.dtb \
 	imx6dl-aristainetos2c_7.dtb \
+	imx6dl-aristainetos2c_cslb_7.dtb \
 	imx6dl-brppt2.dtb \
 	imx6dl-cubox-i.dtb \
 	imx6dl-cubox-i-emmc-som-v15.dtb \
@ -768,6 +765,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \
 	imx8qm-rom7720-a1.dtb \
 	fsl-imx8qxp-ai_ml.dtb \
 	fsl-imx8qxp-colibri.dtb \
+	fsl-imx8qxp-apalis.dtb \
 	fsl-imx8qxp-mek.dtb \
 	imx8-deneb.dtb \
 	imx8-giedi.dtb
--- a/arch/arm/dts/armada-3720-espressobin-emmc.dts
+++ b/arch/arm/dts/armada-3720-espressobin-emmc.dts
@ -1,44 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Device Tree file for Globalscale Marvell ESPRESSOBin Board with eMMC
- * Copyright (C) 2018 Marvell
- *
- * Romain Perier <romain.perier@free-electrons.com>
- * Konstantin Porotchkin <kostap@marvell.com>
- *
- */
-/*
- * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf
- */
-
-/dts-v1/;
-
-#include "armada-3720-espressobin.dtsi"
-
-/ {
-	model = "Globalscale Marvell ESPRESSOBin Board (eMMC)";
-	compatible = "globalscale,espressobin-emmc", "globalscale,espressobin",
-		     "marvell,armada3720", "marvell,armada3710";
-};
-
-/* U11 */
-&sdhci1 {
-	non-removable;
-	bus-width = <8>;
-	mmc-ddr-1_8v;
-	mmc-hs400-1_8v;
-	marvell,xenon-emmc;
-	marvell,xenon-tun-count = <9>;
-	marvell,pad-type = "fixed-1-8v";
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc_pins>;
-	status = "okay";
-
-	#address-cells = <1>;
-	#size-cells = <0>;
-	mmccard: mmccard@0 {
-		compatible = "mmc-card";
-		reg = <0>;
-	};
-};
--- a/arch/arm/dts/armada-3720-espressobin.dts
+++ b/arch/arm/dts/armada-3720-espressobin.dts
@ -1,20 +1,192 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
- * Device Tree file for Globalscale Marvell ESPRESSOBin Board
+ * Device Tree file for Marvell Armada 3720 community board
+ * (ESPRESSOBin)
 * Copyright (C) 2016 Marvell
 *
- * Romain Perier <romain.perier@free-electrons.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Konstantin Porotchkin <kostap@marvell.com>
 *
- */
-/*
- * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */

 /dts-v1/;

-#include "armada-3720-espressobin.dtsi"
+#include "armada-372x.dtsi"

 / {
 	model = "Globalscale Marvell ESPRESSOBin Board";
 	compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		ethernet0 = &eth0;
+		i2c0 = &i2c0;
+		spi0 = &spi0;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
+	};
+
+	vcc_sd_reg0: regulator@0 {
+		compatible = "regulator-gpio";
+		regulator-name = "vcc_sd0";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-type = "voltage";
+		states = <1800000 0x1
+			  3300000 0x0>;
+		gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&comphy {
+	max-lanes = <3>;
+	phy0 {
+		phy-type = <PHY_TYPE_USB3_HOST0>;
+		phy-speed = <PHY_SPEED_5G>;
+	};
+
+	phy1 {
+		phy-type = <PHY_TYPE_PEX0>;
+		phy-speed = <PHY_SPEED_2_5G>;
+	};
+
+	phy2 {
+		phy-type = <PHY_TYPE_SATA0>;
+		phy-speed = <PHY_SPEED_5G>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
+	phy-mode = "rgmii";
+	phy_addr = <0x1>;
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+	status = "okay";
+};
+
+/* CON3 */
+&sata {
+	status = "okay";
+};
+
+&sdhci0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio_pins>;
+	bus-width = <4>;
+	cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
+	vqmmc-supply = <&vcc_sd_reg0>;
+	status = "okay";
+};
+
+/* U11 */
+&sdhci1 {
+	non-removable;
+	bus-width = <8>;
+	mmc-ddr-1_8v;
+	mmc-hs400-1_8v;
+	marvell,xenon-emmc;
+	marvell,xenon-tun-count = <9>;
+	marvell,pad-type = "fixed-1-8v";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc_pins>;
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+	mmccard: mmccard@0 {
+		compatible = "mmc-card";
+		reg = <0>;
+	};
+};
+
+&spi0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi_quad_pins>;
+
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,m25p128", "jedec,spi-nor";
+		reg = <0>; /* Chip select 0 */
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+	};
+};
+
+/* Exported on the micro USB connector CON32 through an FTDI */
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
+	status = "okay";
+};
+
+/* CON29 */
+&usb2 {
+	status = "okay";
+};
+
+/* CON31 */
+&usb3 {
+	status = "okay";
+};
+
+&pcie0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_pins>;
+	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
+	status = "okay";
 };
--- a/arch/arm/dts/armada-3720-espressobin.dtsi
+++ b/arch/arm/dts/armada-3720-espressobin.dtsi
@ -1,167 +0,0 @@
-/*
- * Device Tree file for Marvell Armada 3720 community board
- * (ESPRESSOBin)
- * Copyright (C) 2016 Marvell
- *
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- * Konstantin Porotchkin <kostap@marvell.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-
-#include "armada-372x.dtsi"
-
-/ {
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	aliases {
-		ethernet0 = &eth0;
-		i2c0 = &i2c0;
-		spi0 = &spi0;
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
-	};
-
-	vcc_sd_reg0: regulator@0 {
-		compatible = "regulator-gpio";
-		regulator-name = "vcc_sd0";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-type = "voltage";
-		states = <1800000 0x1
-			  3300000 0x0>;
-		gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&comphy {
-	max-lanes = <3>;
-	phy0 {
-		phy-type = <PHY_TYPE_USB3_HOST0>;
-		phy-speed = <PHY_SPEED_5G>;
-	};
-
-	phy1 {
-		phy-type = <PHY_TYPE_PEX0>;
-		phy-speed = <PHY_SPEED_2_5G>;
-	};
-
-	phy2 {
-		phy-type = <PHY_TYPE_SATA0>;
-		phy-speed = <PHY_SPEED_5G>;
-	};
-};
-
-&eth0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
-	phy-mode = "rgmii";
-	phy_addr = <0x1>;
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins>;
-	status = "okay";
-};
-
-/* CON3 */
-&sata {
-	status = "okay";
-};
-
-&sdhci0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdio_pins>;
-	bus-width = <4>;
-	cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
-	vqmmc-supply = <&vcc_sd_reg0>;
-	status = "okay";
-};
-
-&spi0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi_quad_pins>;
-
-	spi-flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "st,m25p128", "jedec,spi-nor";
-		reg = <0>; /* Chip select 0 */
-		spi-max-frequency = <50000000>;
-		m25p,fast-read;
-	};
-};
-
-/* Exported on the micro USB connector CON32 through an FTDI */
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart1_pins>;
-	status = "okay";
-};
-
-/* CON29 */
-&usb2 {
-	status = "okay";
-};
-
-/* CON31 */
-&usb3 {
-	status = "okay";
-};
-
-&pcie0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie_pins>;
-	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
-	status = "okay";
-};
--- a/arch/arm/dts/armada-xp-gp-u-boot.dtsi
+++ b/arch/arm/dts/armada-xp-gp-u-boot.dtsi
@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/ {
+	soc {
+		internal-regs {
+			serial@12000 {
+				u-boot,dm-pre-reloc;
+			};
+		};
+	};
+};
+
+&spi0 {
+	u-boot,dm-pre-reloc;
+
+	spi-flash@0 {
+		u-boot,dm-pre-reloc;
+	};
+};
--- a/arch/arm/dts/armada-xp-gp.dts
+++ b/arch/arm/dts/armada-xp-gp.dts
@ -31,6 +31,10 @@
 		stdout-path = "serial0:115200n8";
 	};

+	aliases {
+		spi0 = &spi0;
+	};
+
 	memory@0 {
 		device_type = "memory";
 		/*
--- a/arch/arm/dts/at91-sama5d2_icp.dts
+++ b/arch/arm/dts/at91-sama5d2_icp.dts
@ -53,19 +53,19 @@
 				status = "okay";

 				eeprom@50 {
-					compatible = "atmel,24c32";
+					compatible = "microchip,24aa02e48";
 					reg = <0x50>;
 					pagesize = <16>;
 				};

 				eeprom@52 {
-					compatible = "atmel,24c32";
+					compatible = "microchip,24aa02e48";
 					reg = <0x52>;
 					pagesize = <16>;
 				};

 				eeprom@53 {
-					compatible = "atmel,24c32";
+					compatible = "microchip,24aa02e48";
 					reg = <0x53>;
 					pagesize = <16>;
 				};
--- a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
@ -118,8 +118,11 @@

 &usdhc1 {
 	u-boot,dm-spl;
+	mmc-hs400-1_8v;
 };

 &usdhc2 {
 	u-boot,dm-spl;
+	sd-uhs-sdr104;
+	sd-uhs-ddr50;
 };
--- a/arch/arm/dts/fsl-imx8qxp-apalis-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qxp-apalis-u-boot.dtsi
@ -0,0 +1,139 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright 2020 Toradex
+ */
+
+&{/imx8qx-pm} {
+
+	u-boot,dm-pre-proper;
+};
+
+&mu {
+	u-boot,dm-pre-proper;
+};
+
+&clk {
+	u-boot,dm-pre-proper;
+};
+
+&iomuxc {
+	u-boot,dm-pre-proper;
+};
+
+&pd_lsio {
+	u-boot,dm-pre-proper;
+};
+
+&pd_lsio_gpio0 {
+	u-boot,dm-pre-proper;
+};
+
+&pd_lsio_gpio1 {
+	u-boot,dm-pre-proper;
+};
+
+&pd_lsio_gpio2 {
+	u-boot,dm-pre-proper;
+};
+
+&pd_lsio_gpio3 {
+	u-boot,dm-pre-proper;
+};
+
+&pd_lsio_gpio4 {
+	u-boot,dm-pre-proper;
+};
+
+&pd_lsio_gpio5 {
+	u-boot,dm-pre-proper;
+};
+
+&pd_lsio_gpio6 {
+	u-boot,dm-pre-proper;
+};
+
+&pd_lsio_gpio7 {
+	u-boot,dm-pre-proper;
+};
+
+&pd_dma {
+	u-boot,dm-pre-proper;
+};
+
+&pd_dma_lpuart0 {
+	u-boot,dm-pre-proper;
+};
+
+&pd_dma_lpuart3 {
+	u-boot,dm-pre-proper;
+};
+
+&pd_conn {
+	u-boot,dm-pre-proper;
+};
+
+&pd_conn_sdch0 {
+	u-boot,dm-pre-proper;
+};
+
+&pd_conn_sdch1 {
+	u-boot,dm-pre-proper;
+};
+
+&pd_conn_sdch2 {
+	u-boot,dm-pre-proper;
+};
+
+&pd_conn_enet0 {
+	u-boot,dm-pre-proper;
+};
+
+&gpio0 {
+	u-boot,dm-pre-proper;
+};
+
+&gpio1 {
+	u-boot,dm-pre-proper;
+};
+
+&gpio2 {
+	u-boot,dm-pre-proper;
+};
+
+&gpio3 {
+	u-boot,dm-pre-proper;
+};
+
+&gpio4 {
+	u-boot,dm-pre-proper;
+};
+
+&gpio5 {
+	u-boot,dm-pre-proper;
+};
+
+&gpio6 {
+	u-boot,dm-pre-proper;
+};
+
+&gpio7 {
+	u-boot,dm-pre-proper;
+};
+
+&lpuart3 {
+	u-boot,dm-pre-proper;
+};
+
+&lpuart0 {
+	u-boot,dm-pre-proper;
+};
+
+&usdhc1 {
+	u-boot,dm-pre-proper;
+	/delete-property/ assigned-clock-parents;
+};
+
+&usdhc2 {
+	u-boot,dm-pre-proper;
+	/delete-property/ assigned-clock-parents;
+};
--- a/arch/arm/dts/fsl-imx8qxp-apalis.dts
+++ b/arch/arm/dts/fsl-imx8qxp-apalis.dts
@ -0,0 +1,278 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright 2020 Toradex
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8qxp.dtsi"
+#include "fsl-imx8qxp-apalis-u-boot.dtsi"
+
+/ {
+	model = "Toradex Apalis iMX8X";
+	compatible = "toradex,apalis-imx8x", "fsl,imx8qxp";
+
+	chosen {
+		bootargs = "console=ttyLP1,115200";
+		stdout-path = &lpuart1;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usb_otg1_vbus: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_reset_moci>;
+
+	apalis-imx8x {
+		/* Apalis UART1 */
+		pinctrl_lpuart1: lpuart1grp {
+			fsl,pins = <
+				SC_P_UART1_RX_ADMA_UART1_RX		0x06000020	/* SODIMM 118 */
+				SC_P_UART1_TX_ADMA_UART1_TX		0x06000020	/* SODIMM 112 */
+			>;
+		};
+
+		/* On-module Gigabit Ethernet PHY Micrel KSZ9031 */
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD	0x14a0
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD	0x14a0
+				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
+				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
+				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x61
+				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x61
+				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x61
+				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x61
+				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x61
+				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x61
+				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x61
+				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x61
+				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x61
+				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x61
+				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x61
+				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x61
+				/* On-module ETH_RESET# */
+				SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04		0x06000020
+				/* On-module ETH_INT# */
+				SC_P_ADC_IN2_LSIO_GPIO1_IO12			0x21
+			>;
+		};
+
+		/* Apalis BKL_ON */
+		pinctrl_gpio_bkl_on: gpio-bkl-on {
+			fsl,pins = <
+				SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13			0x40		/* SODIMM 286 */
+			>;
+		};
+
+		pinctrl_hog0: hog0grp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD		0x000514a0
+			>;
+		};
+
+		pinctrl_hog1: hog1grp {
+			fsl,pins = <
+				/* Apalis USBO1_EN */
+				SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16		0x41		/* SODIMM 274 */
+			>;
+		};
+
+		/* Apalis RESET_MOCI# */
+		pinctrl_reset_moci: gpioresetmocigrp {
+			fsl,pins = <
+				SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01	0x21
+			>;
+		};
+
+		/* On-module eMMC */
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD			0x21
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x21
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD			0x21
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x21
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD			0x21
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x21
+			>;
+		};
+
+		/* Apalis MMC1_CD# */
+		pinctrl_usdhc2_gpio: mmc1gpiogrp {
+			fsl,pins = <
+				SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22		0x06000021	/* SODIMM 164 */
+			>;
+		};
+
+		pinctrl_usdhc2_gpio_sleep: usdhc1gpioslpgrp {
+			fsl,pins = <
+				SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22		0x60		/* SODIMM 164 */
+			>;
+		};
+
+		/* Apalis USBH_EN */
+		pinctrl_usbh_en: usbhen {
+			fsl,pins = <
+				SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04		0x40		/* SODIMM 84 */
+			>;
+		};
+
+		/* Apalis MMC1 */
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041	/* SODIMM 154 */
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD			0x21		/* SODIMM 150 */
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21		/* SODIMM 160 */
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21		/* SODIMM 162 */
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21		/* SODIMM 144 */
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21		/* SODIMM 146 */
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x21
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041	/* SODIMM 154 */
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD			0x21		/* SODIMM 150 */
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21		/* SODIMM 160 */
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21		/* SODIMM 162 */
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21		/* SODIMM 144 */
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21		/* SODIMM 146 */
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x21
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041	/* SODIMM 154 */
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD			0x21		/* SODIMM 150 */
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21		/* SODIMM 160 */
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21		/* SODIMM 162 */
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21		/* SODIMM 144 */
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21		/* SODIMM 146 */
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x21
+			>;
+		};
+
+		pinctrl_usdhc2_sleep: usdhc2slpgrp {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_LSIO_GPIO4_IO23			0x60		/* SODIMM 154 */
+				SC_P_USDHC1_CMD_LSIO_GPIO4_IO24			0x60		/* SODIMM 150 */
+				SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25		0x60		/* SODIMM 160 */
+				SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26		0x60		/* SODIMM 162 */
+				SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27		0x60		/* SODIMM 144 */
+				SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28		0x60		/* SODIMM 146 */
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x21
+			>;
+		};
+	};
+};
+
+/* Apalis Gigabit LAN */
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	fsl,magic-packet;
+	phy-handle = <&ethphy0>;
+	phy-mode = "rgmii";
+	phy-reset-duration = <10>;
+	phy-reset-post-delay = <150>;
+	phy-reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@4 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <4>;
+		};
+	};
+};
+
+/* Apalis UART1 */
+&lpuart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart1>;
+	status = "okay";
+};
+
+/* On-module eMMC */
+&usdhc1 {
+	bus-width = <8>;
+	non-removable;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	status = "okay";
+};
+
+/* Apalis MMC1 */
+&usdhc2 {
+	bus-width = <4>;
+	cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
+	disable-wp;
+	status = "okay";
+};
--- a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
@ -118,8 +118,11 @@

 &usdhc1 {
 	u-boot,dm-spl;
+	mmc-hs400-1_8v;
 };

 &usdhc2 {
 	u-boot,dm-spl;
+	sd-uhs-sdr104;
+	sd-uhs-ddr50;
 };
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@ -1,5 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
+ * Copyright 2020 NXP
 * Copyright 2016 Freescale Semiconductor
 */

@ -116,7 +117,7 @@
 			status = "disabled";
 		};

-		pcie@3400000 {
+		pcie1: pcie@3400000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
 			       0x00 0x03480000 0x0 0x40000   /* lut registers */
--- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
@ -4,8 +4,8 @@

 / {
 	aliases {
-		mmc0 = &esdhc0;
-		mmc1 = &esdhc1;
+		mmc0 = &esdhc1;
+		mmc1 = &esdhc0;
 		i2c0 = &i2c0;
 		i2c1 = &i2c3;
 		i2c2 = &i2c4;
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@ -2,7 +2,7 @@
 /*
 * NXP ls1028a SOC common device tree source
 *
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
 *
 */

@ -91,7 +91,7 @@
 		status = "disabled";
 	};

-	pcie@3400000 {
+	pcie1: pcie@3400000 {
 	       compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
 	       reg = <0x00 0x03400000 0x0 0x80000
 		       0x00 0x03480000 0x0 0x40000   /* lut registers */
@ -107,7 +107,7 @@
 		       0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};

-	pcie@3500000 {
+	pcie2: pcie@3500000 {
 	       compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
 	       reg = <0x00 0x03500000 0x0 0x80000
 		       0x00 0x03580000 0x0 0x40000   /* lut registers */
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@ -1,7 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
- * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ * Device Tree Include file for NXP Layerscape-1043A family SoC.
 *
+ * Copyright 2020 NXP
 * Copyright (C) 2014-2015, Freescale Semiconductor
 *
 * Mingkai Hu <Mingkai.hu@freescale.com>
@ -240,7 +241,7 @@
 			dr_mode = "host";
 		};

-		pcie@3400000 {
+		pcie1: pcie@3400000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03400000 0x0 0x10000   /* dbi registers */
 			       0x00 0x03410000 0x0 0x10000   /* lut registers */
@ -255,7 +256,7 @@
 				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 		};

-		pcie@3500000 {
+		pcie2: pcie@3500000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03500000 0x0 0x10000   /* dbi registers */
 			       0x00 0x03510000 0x0 0x10000   /* lut registers */
@ -271,7 +272,7 @@
 				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 		};

-		pcie@3600000 {
+		pcie3: pcie@3600000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03600000 0x0 0x10000   /* dbi registers */
 			       0x00 0x03610000 0x0 0x10000   /* lut registers */
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@ -241,7 +241,7 @@
 			dr_mode = "host";
 		};

-		pcie@3400000 {
+		pcie1: pcie@3400000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
 			       0x00 0x03480000 0x0 0x40000   /* lut registers */
@ -257,7 +257,7 @@
 				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 		};

-		pcie_ep@3400000 {
+		pcie_ep1: pcie_ep@3400000 {
 			compatible = "fsl,ls-pcie-ep";
 			reg = <0x00 0x03400000 0x0 0x80000
 			       0x00 0x034c0000 0x0 0x40000
@ -268,7 +268,7 @@
 			big-endian;
 		};

-		pcie@3500000 {
+		pcie2: pcie@3500000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
 			       0x00 0x03580000 0x0 0x40000   /* lut registers */
@ -285,7 +285,7 @@
 				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 		};

-		pcie_ep@3500000 {
+		pcie_ep2: pcie_ep@3500000 {
 			compatible = "fsl,ls-pcie-ep";
 			reg = <0x00 0x03500000 0x0 0x80000
 			       0x00 0x035c0000 0x0 0x40000
@ -296,7 +296,7 @@
 			big-endian;
 		};

-		pcie@3600000 {
+		pcie3: pcie@3600000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
 			       0x00 0x03680000 0x0 0x40000   /* lut registers */
@ -312,7 +312,7 @@
 				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 		};

-		pcie_ep@3600000 {
+		pcie_ep3: pcie_ep@3600000 {
 			compatible = "fsl,ls-pcie-ep";
 			reg = <0x00 0x03600000 0x0 0x80000
 			       0x00 0x036c0000 0x0 0x40000
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@ -2,7 +2,7 @@
 /*
 * NXP ls1088a SOC common device tree source
 *
- * Copyright 2017 NXP
+ * Copyright 2017, 2020 NXP
 */

 / {
@ -135,7 +135,7 @@
 		dr_mode = "host";
 	};

-	pcie@3400000 {
+	pcie1: pcie@3400000 {
 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
 		reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
 		       0x00 0x03480000 0x0 0x80000   /* lut registers */
@ -151,7 +151,7 @@
 			  0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};

-	pcie@3500000 {
+	pcie2: pcie@3500000 {
 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
 		reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
 		       0x00 0x03580000 0x0 0x80000   /* lut registers */
@ -167,7 +167,7 @@
 			  0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};

-	pcie@3600000 {
+	pcie3: pcie@3600000 {
 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
 		reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
 		       0x00 0x03680000 0x0 0x80000   /* lut registers */
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@ -1,7 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
- * Freescale ls2080a SOC common device tree source
+ * NXP ls2080a SOC common device tree source
 *
+ * Copyright 2020 NXP
 * Copyright 2013-2015 Freescale Semiconductor, Inc.
 */

@ -133,7 +134,7 @@
 		dr_mode = "host";
 	};

-	pcie@3400000 {
+	pcie1: pcie@3400000 {
 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
 		reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
 		       0x00 0x03480000 0x0 0x80000   /* lut registers */
@ -148,7 +149,7 @@
 			  0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};

-	pcie@3500000 {
+	pcie2: pcie@3500000 {
 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
 		reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
 		       0x00 0x03580000 0x0 0x80000   /* lut registers */
@ -163,7 +164,7 @@
 			  0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};

-	pcie@3600000 {
+	pcie3: pcie@3600000 {
 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
 		reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
 		       0x00 0x03680000 0x0 0x80000   /* lut registers */
@ -178,7 +179,7 @@
 			  0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};

-	pcie@3700000 {
+	pcie4: pcie@3700000 {
 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
 		reg = <0x00 0x03700000 0x0 0x80000   /* dbi registers */
 		       0x00 0x03780000 0x0 0x80000   /* lut registers */
--- a/arch/arm/dts/fsl-lx2160a-qds.dts
+++ b/arch/arm/dts/fsl-lx2160a-qds.dts
@ -13,7 +13,4 @@
 / {
 	model = "NXP Layerscape LX2160AQDS Board";
 	compatible = "fsl,lx2160aqds", "fsl,lx2160a";
-	aliases {
-		spi0 = &fspi;
-	};
 };
--- a/arch/arm/dts/fsl-lx2160a-qds.dtsi
+++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi
@ -2,12 +2,18 @@
 /*
 * NXP LX2160AQDS common device tree source
 *
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2020 NXP
 *
 */

 #include "fsl-lx2160a.dtsi"

+/ {
+	aliases {
+		spi0 = &fspi;
+	};
+};
+
 &dpmac17 {
 	status = "okay";
 	phy-handle = <&rgmii_phy1>;
@ -251,6 +257,20 @@
 	};
 };

+&fspi {
+	status = "okay";
+
+	mt35xu512aba0: flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <50000000>;
+		reg = <0>;
+		spi-rx-bus-width = <8>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
 &sata0 {
 	status = "okay";
 };
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@ -325,7 +325,7 @@

 	};

-	pcie@3400000 {
+	pcie1: pcie@3400000 {
 		compatible = "fsl,lx2160a-pcie";
 		reg = <0x00 0x03400000 0x0 0x80000   /* PAB registers */
 		       0x00 0x03480000 0x0 0x40000   /* LUT registers */
@ -340,7 +340,7 @@
 			  0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};

-	pcie@3500000 {
+	pcie2: pcie@3500000 {
 		compatible = "fsl,lx2160a-pcie";
 		reg = <0x00 0x03500000 0x0 0x80000   /* PAB registers */
 		       0x00 0x03580000 0x0 0x40000   /* LUT registers */
@ -356,7 +356,7 @@
 			  0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};

-	pcie@3600000 {
+	pcie3: pcie@3600000 {
 		compatible = "fsl,lx2160a-pcie";
 		reg = <0x00 0x03600000 0x0 0x80000   /* PAB registers */
 		       0x00 0x03680000 0x0 0x40000   /* LUT registers */
@ -371,7 +371,7 @@
 			  0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};

-	pcie@3700000 {
+	pcie4: pcie@3700000 {
 		compatible = "fsl,lx2160a-pcie";
 		reg = <0x00 0x03700000 0x0 0x80000   /* PAB registers */
 		       0x00 0x03780000 0x0 0x40000   /* LUT registers */
@ -386,7 +386,7 @@
 			  0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};

-	pcie@3800000 {
+	pcie5: pcie@3800000 {
 		compatible = "fsl,lx2160a-pcie";
 		reg = <0x00 0x03800000 0x0 0x80000   /* PAB registers */
 		       0x00 0x03880000 0x0 0x40000   /* LUT registers */
@ -401,7 +401,7 @@
 			  0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};

-	pcie@3900000 {
+	pcie6: pcie@3900000 {
 		compatible = "fsl,lx2160a-pcie";
 		reg = <0x00 0x03900000 0x0 0x80000   /* PAB registers */
 		       0x00 0x03980000 0x0 0x40000   /* LUT registers */
--- a/arch/arm/dts/fsl-lx2162a-qds-17-x.dts
+++ b/arch/arm/dts/fsl-lx2162a-qds-17-x.dts
@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2162AQDS device tree source for SERDES protocol 17.x
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2162a-qds-sd1-17.dtsi"
+
+/ {
+	model = "NXP Layerscape LX2160AQDS Board (DTS 17.x)";
+	compatible = "fsl,lx2162aqds", "fsl,lx2160a";
+
+};
--- a/arch/arm/dts/fsl-lx2162a-qds-18-x.dts
+++ b/arch/arm/dts/fsl-lx2162a-qds-18-x.dts
@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2162AQDS device tree source for SERDES protocol 18.x
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2162a-qds-sd1-18.dtsi"
+
+/ {
+	model = "NXP Layerscape LX2160AQDS Board (DTS 18.x)";
+	compatible = "fsl,lx2162aqds", "fsl,lx2160a";
+
+};
--- a/arch/arm/dts/fsl-lx2162a-qds-20-x.dts
+++ b/arch/arm/dts/fsl-lx2162a-qds-20-x.dts
@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2162AQDS device tree source for SERDES protocol 20.x
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2162a-qds-sd1-20.dtsi"
+
+/ {
+	model = "NXP Layerscape LX2160AQDS Board (DTS 20.x)";
+	compatible = "fsl,lx2162aqds", "fsl,lx2160a";
+
+};
--- a/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
+++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2162AQDS device tree source for the SERDES block #1 - protocol 17
+ *
+ * Some assumptions are made:
+ *    * mezzanine card M8 is connected to IO SLOT1 (25g-aui for DPMAC 3,4,5,6)
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+#include "fsl-lx2160a-qds.dtsi"
+
+&dpmac3 {
+	status = "okay";
+	phy-handle = <&inphi_phy0>;
+	phy-connection-type = "25g-aui";
+};
+
+&dpmac4 {
+	status = "okay";
+	phy-handle = <&inphi_phy1>;
+	phy-connection-type = "25g-aui";
+};
+
+&dpmac5 {
+	status = "okay";
+	phy-handle = <&inphi_phy2>;
+	phy-connection-type = "25g-aui";
+};
+
+&dpmac6 {
+	status = "okay";
+	phy-handle = <&inphi_phy3>;
+	phy-connection-type = "25g-aui";
+};
+
+&emdio1_slot1 {
+	inphi_phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-id0210.7440";
+		reg = <0x0>;
+	};
+
+	inphi_phy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-id0210.7440";
+		reg = <0x1>;
+	};
+
+	inphi_phy2: ethernet-phy@2 {
+		compatible = "ethernet-phy-id0210.7440";
+		reg = <0x2>;
+	};
+
+	inphi_phy3: ethernet-phy@3 {
+		compatible = "ethernet-phy-id0210.7440";
+		reg = <0x3>;
+	};
+};
--- a/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
+++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2162AQDS device tree source for the SERDES block #1 - protocol 18
+ *
+ * Some assumptions are made:
+ *    * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4)
+ *    * mezzanine card M13/M8 is connected to IO SLOT6 (25g-aui for DPMAC 5,6)
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+#include "fsl-lx2160a-qds.dtsi"
+
+&dpmac3 {
+	status = "okay";
+	phy-handle = <&aquantia_phy1>;
+	phy-connection-type = "usxgmii";
+};
+
+&dpmac4 {
+	status = "okay";
+	phy-handle = <&aquantia_phy2>;
+	phy-connection-type = "usxgmii";
+};
+
+&dpmac5 {
+	status = "okay";
+	phy-handle = <&inphi_phy0>;
+	phy-connection-type = "25g-aui";
+};
+
+&dpmac6 {
+	status = "okay";
+	phy-handle = <&inphi_phy1>;
+	phy-connection-type = "25g-aui";
+};
+
+&emdio1_slot1 {
+	aquantia_phy1: ethernet-phy@4 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <0x0>;
+	};
+
+	aquantia_phy2: ethernet-phy@5 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <0x1>;
+	};
+};
+
+&emdio1_slot6 {
+	inphi_phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-id0210.7440";
+		reg = <0x0>;
+	};
+
+	inphi_phy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-id0210.7440";
+		reg = <0x1>;
+	};
+};
--- a/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
+++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2162AQDS device tree source for the SERDES block #1 - protocol 20
+ *
+ * Some assumptions are made:
+ *    * Mezzanine card M8 is connected to IO SLOT1
+ *        (xlaui4 for DPMAC 1)
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+#include "fsl-lx2160a-qds.dtsi"
+
+&dpmac1 {
+	status = "okay";
+	phy-handle = <&cortina_phy1_0>;
+	phy-connection-type = "xlaui4";
+};
+
+&emdio1_slot1 {
+	cortina_phy1_0: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <0x0>;
+	};
+};
--- a/arch/arm/dts/fsl-lx2162a-qds.dts
+++ b/arch/arm/dts/fsl-lx2162a-qds.dts
@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2162AQDS device tree source
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2160a-qds.dtsi"
+
+/ {
+	model = "NXP Layerscape LX2162AQDS Board";
+	compatible = "fsl,lx2162aqds", "fsl,lx2160a";
+
+	aliases {
+		pcie@3500000 {
+			status = "disabled";
+		};
+
+		pcie@3800000 {
+			status = "disabled";
+		};
+
+		pcie@3900000 {
+			status = "disabled";
+		};
+	};
+};
+
+&usb1 {
+	status = "disabled";
+};
--- a/arch/arm/dts/imx53-ppd-uboot.dtsi
+++ b/arch/arm/dts/imx53-ppd-uboot.dtsi
@ -28,7 +28,7 @@
 		#size-cells = <1>;

 		vpd@0 {
-			reg = <0 1022>;
+			reg = <0 800>;
 		};

 		bootcount: bootcount@1022 {
--- a/arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi
+++ b/arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi
@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- */
-
-#include <imx6qdl-aristainetos2-u-boot.dtsi>
-
-&lcd_panel {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ipu_disp>;
-	enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
-	backlight = <&backlight>;
-};
--- a/arch/arm/dts/imx6dl-aristainetos2_4.dts
+++ b/arch/arm/dts/imx6dl-aristainetos2_4.dts
@ -1,51 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0)
-/*
- * support for the imx6 based aristainetos2 board
- * parts for 4.3 inch LG display on spi1 port0
- *
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
- *
- */
-/dts-v1/;
-
-#include "imx6dl-aristainetos2_4.dtsi"
-#include "imx6qdl-aristainetos2.dtsi"
-
-/ {
-	model = "aristainetos2 i.MX6 Dual Lite Board 4";
-	compatible = "fsl,imx6dl";
-
-};
-
-&ecspi1 {
-	lcd_panel: display@0 {
-		compatible = "lg,lg4573";
-		spi-max-frequency = <10000000>;
-		reg = <0>;
-		power-on-delay = <10>;
-
-		display-timings {
-			480x800p57 {
-				native-mode;
-				clock-frequency = <27000027>;
-				hactive = <480>;
-				vactive = <800>;
-				hfront-porch = <10>;
-				hback-porch = <59>;
-				hsync-len = <10>;
-				vback-porch = <15>;
-				vfront-porch = <15>;
-				vsync-len = <15>;
-				hsync-active = <1>;
-				vsync-active = <1>;
-			};
-		};
-
-		port {
-			panel_in: endpoint {
-				remote-endpoint = <&display_out>;
-			};
-		};
-	};
-};
--- a/arch/arm/dts/imx6dl-aristainetos2_4.dtsi
+++ b/arch/arm/dts/imx6dl-aristainetos2_4.dtsi
@ -1,84 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0)
-/*
- * support for the imx6 based aristainetos2 board
- * parts for 4.3 inch LG display on the parallel port and atmel maxtouch
- *
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
- *
- */
-/dts-v1/;
-#include "imx6dl.dtsi"
-
-/ {
-	display0: disp0 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "fsl,imx-parallel-display";
-		interface-pix-fmt = "rgb24";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_ipu_disp>;
-
-		port@0 {
-			reg = <0>;
-			display0_in: endpoint {
-				remote-endpoint = <&ipu1_di0_disp0>;
-			};
-		};
-
-		port@1 {
-			reg = <1>;
-			display_out: endpoint {
-				remote-endpoint = <&panel_in>;
-			};
-		};
-	};
-};
-
-&i2c3 {
-	touch: touch@4b {
-		compatible = "atmel,maxtouch";
-		reg = <0x4b>;
-		interrupt-parent = <&gpio2>;
-		interrupts = <9 8>;
-	};
-};
-
-&ipu1_di0_disp0 {
-	remote-endpoint = <&display0_in>;
-};
-
-&iomuxc {
-	pinctrl_ipu_disp: ipudisp1grp {
-		fsl,pins = <
-			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x31
-			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0xE1
-			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
-			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
-			MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0xE1
-			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0xE1
-			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0xE1
-			MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0xE1
-			MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0xE1
-			MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0xE1
-			MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0xE1
-			MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0xE1
-			MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0xE1
-			MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0xE1
-			MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0xE1
-			MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0xE1
-			MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0xE1
-			MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0xE1
-			MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0xe1
-			MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0xE1
-			MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0xE1
-			MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0xE1
-			MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0xE1
-			MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0xE1
-			MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0xE1
-			MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0xE1
-			MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0xE1
-			MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0xE1
-		>;
-	};
-};
--- a/arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi
+++ b/arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi
@ -1,19 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- */
-
-#include <imx6qdl-aristainetos2-u-boot.dtsi>
-/ {
-	vdd_panel_reg: regulator-panel {
-		compatible = "regulator-fixed";
-		regulator-name = "panel_regulator";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-always-on;
-	};
-};
-
-&panel0 {
-	power-supply = <&vdd_panel_reg>;
-};
--- a/arch/arm/dts/imx6dl-aristainetos2_7.dts
+++ b/arch/arm/dts/imx6dl-aristainetos2_7.dts
@ -1,16 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0)
-/*
- * support for the imx6 based aristainetos2 board
- *
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
- *
- */
-/dts-v1/;
-#include "imx6dl-aristainetos2_7.dtsi"
-#include "imx6qdl-aristainetos2.dtsi"
-
-/ {
-	model = "aristainetos2 i.MX6 Dual Lite Board 7";
-	compatible = "fsl,imx6dl";
-};
--- a/arch/arm/dts/imx6dl-aristainetos2_7.dtsi
+++ b/arch/arm/dts/imx6dl-aristainetos2_7.dtsi
@ -1,7 +1,7 @@
 // SPDX-License-Identifier: (GPL-2.0)
 /*
 * support for the imx6 based aristainetos2 board
- * parts for 7 inch LG display connected to the LVDS port and atmel maxtouch
+ * parts for 7 inch LG display connected to the LVDS port
 *
 * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
 * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
@ -26,15 +26,6 @@
 	};
 };

-&i2c3 {
-	touch: touch@4d {
-		compatible = "atmel,maxtouch";
-		reg = <0x4d>;
-		interrupt-parent = <&gpio2>;
-		interrupts = <9 8>;
-	};
-};
-
 &ldb {
 	status = "okay";

--- a/arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi
+++ b/arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi
@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ or X11
-/*
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- */
-
-#include <imx6qdl-aristainetos2b-u-boot.dtsi>
-
-&lcd_panel {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ipu_disp>;
-	enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
-	backlight = <&backlight>;
-};
--- a/arch/arm/dts/imx6dl-aristainetos2b_4.dts
+++ b/arch/arm/dts/imx6dl-aristainetos2b_4.dts
@ -1,50 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0)
-/*
- * support for the imx6 based aristainetos2b board
- * parts for 4.3 inch LG display on spi1 port1
- *
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- *
- */
-/dts-v1/;
-
-#include "imx6dl-aristainetos2_4.dtsi"
-#include "imx6qdl-aristainetos2b.dtsi"
-
-/ {
-	model = "aristainetos2b i.MX6 Dual Lite Board 4";
-	compatible = "fsl,imx6dl";
-
-};
-
-&ecspi1 {
-	lcd_panel: display@0 {
-		compatible = "lg,lg4573";
-		spi-max-frequency = <10000000>;
-		reg = <1>;
-		power-on-delay = <10>;
-
-		display-timings {
-			480x800p57 {
-				native-mode;
-				clock-frequency = <27000027>;
-				hactive = <480>;
-				vactive = <800>;
-				hfront-porch = <10>;
-				hback-porch = <59>;
-				hsync-len = <10>;
-				vback-porch = <15>;
-				vfront-porch = <15>;
-				vsync-len = <15>;
-				hsync-active = <1>;
-				vsync-active = <1>;
-			};
-		};
-
-		port {
-			panel_in: endpoint {
-				remote-endpoint = <&display_out>;
-			};
-		};
-	};
-};
--- a/arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi
+++ b/arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi
@ -1,19 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ or X11
-/*
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- */
-
-#include <imx6qdl-aristainetos2b-u-boot.dtsi>
-/ {
-	vdd_panel_reg: regulator-panel {
-		compatible = "regulator-fixed";
-		regulator-name = "panel_regulator";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-always-on;
-	};
-};
-
-&panel0 {
-	power-supply = <&vdd_panel_reg>;
-};
--- a/arch/arm/dts/imx6dl-aristainetos2b_7.dts
+++ b/arch/arm/dts/imx6dl-aristainetos2b_7.dts
@ -1,16 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0)
-/*
- * support for the imx6 based aristainetos2 board
- *
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
- *
- */
-/dts-v1/;
-#include "imx6dl-aristainetos2_7.dtsi"
-#include "imx6qdl-aristainetos2b.dtsi"
-
-/ {
-	model = "aristainetos2b i.MX6 Dual Lite Board 7";
-	compatible = "fsl,imx6dl";
-};
--- a/arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi
+++ b/arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi
@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ or X11
-/*
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- */
-
-#include <imx6qdl-aristainetos2b_csl-u-boot.dtsi>
-
-&lcd_panel {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ipu_disp>;
-	enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
-	backlight = <&backlight>;
-};
--- a/arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts
+++ b/arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts
@ -1,50 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0)
-/*
- * support for the imx6 based aristainetos2b csl board
- * parts for 4.3 inch LG display on spi1 port1
- *
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- *
- */
-/dts-v1/;
-
-#include "imx6dl-aristainetos2_4.dtsi"
-#include "imx6qdl-aristainetos2b_csl.dtsi"
-
-/ {
-	model = "aristainetos2b csl i.MX6 Dual Lite Board 4";
-	compatible = "fsl,imx6dl";
-
-};
-
-&ecspi1 {
-	lcd_panel: display@0 {
-		compatible = "lg,lg4573";
-		spi-max-frequency = <10000000>;
-		reg = <1>;
-		power-on-delay = <10>;
-
-		display-timings {
-			480x800p57 {
-				native-mode;
-				clock-frequency = <27000027>;
-				hactive = <480>;
-				vactive = <800>;
-				hfront-porch = <10>;
-				hback-porch = <59>;
-				hsync-len = <10>;
-				vback-porch = <15>;
-				vfront-porch = <15>;
-				vsync-len = <15>;
-				hsync-active = <1>;
-				vsync-active = <1>;
-			};
-		};
-
-		port {
-			panel_in: endpoint {
-				remote-endpoint = <&display_out>;
-			};
-		};
-	};
-};
--- a/arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts
+++ b/arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts
@ -1,16 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0)
-/*
- * support for the imx6 based aristainetos2 board
- *
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
- *
- */
-/dts-v1/;
-#include "imx6dl-aristainetos2_7.dtsi"
-#include "imx6qdl-aristainetos2b_csl.dtsi"
-
-/ {
-	model = "aristainetos2b csl i.MX6 Dual Lite Board 7";
-	compatible = "fsl,imx6dl";
-};
--- a/arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi
+++ b/arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi
@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ or X11
-/*
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- */
-
-#include <imx6qdl-aristainetos2c-u-boot.dtsi>
-
-&lcd_panel {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ipu_disp>;
-	enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
-	backlight = <&backlight>;
-};
--- a/arch/arm/dts/imx6dl-aristainetos2c_4.dts
+++ b/arch/arm/dts/imx6dl-aristainetos2c_4.dts
@ -1,50 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0)
-/*
- * support for the imx6 based aristainetos2c board
- * parts for 4.3 inch LG display on spi1 port1
- *
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- *
- */
-/dts-v1/;
-
-#include "imx6dl-aristainetos2_4.dtsi"
-#include "imx6qdl-aristainetos2c.dtsi"
-
-/ {
-	model = "aristainetos2c i.MX6 Dual Lite Board 4";
-	compatible = "fsl,imx6dl";
-
-};
-
-&ecspi1 {
-	lcd_panel: display@0 {
-		compatible = "lg,lg4573";
-		spi-max-frequency = <10000000>;
-		reg = <1>;
-		power-on-delay = <10>;
-
-		display-timings {
-			480x800p57 {
-				native-mode;
-				clock-frequency = <27000027>;
-				hactive = <480>;
-				vactive = <800>;
-				hfront-porch = <10>;
-				hback-porch = <59>;
-				hsync-len = <10>;
-				vback-porch = <15>;
-				vfront-porch = <15>;
-				vsync-len = <15>;
-				hsync-active = <1>;
-				vsync-active = <1>;
-			};
-		};
-
-		port {
-			panel_in: endpoint {
-				remote-endpoint = <&display_out>;
-			};
-		};
-	};
-};
--- a/arch/arm/dts/imx6dl-aristainetos2c_7.dts
+++ b/arch/arm/dts/imx6dl-aristainetos2c_7.dts
@ -11,6 +11,6 @@
 #include "imx6qdl-aristainetos2c.dtsi"

 / {
-	model = "aristainetos2c i.MX6 Dual Lite Board 7";
-	compatible = "fsl,imx6dl";
+	model = "aristainetos2c+2d i.MX6 Dual Lite Boards 7";
+	compatible = "abb,aristainetos2-imx6dl-7", "fsl,imx6dl";
 };
--- a/arch/arm/dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi
+++ b/arch/arm/dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi
@ -3,7 +3,7 @@
 * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
 */

-#include <imx6qdl-aristainetos2b_csl-u-boot.dtsi>
+#include <imx6qdl-aristainetos2c_cslb-u-boot.dtsi>
 / {
 	vdd_panel_reg: regulator-panel {
 		compatible = "regulator-fixed";
--- a/arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts
+++ b/arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts
@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/*
+ * support for the imx6 based aristainetos2c cslb board
+ *
+ * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
+ * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
+ *
+ */
+/dts-v1/;
+#include "imx6dl-aristainetos2_7.dtsi"
+#include "imx6qdl-aristainetos2c_cslb.dtsi"
+
+/ {
+	model = "aristainetos2c cslb i.MX6 Dual Lite Board 7";
+	compatible = "abb,aristainetos2-imx6dl-7", "fsl,imx6dl";
+};
--- a/arch/arm/dts/imx6q-ba16.dtsi
+++ b/arch/arm/dts/imx6q-ba16.dtsi
@ -174,6 +174,17 @@
 	pinctrl-0 = <&pinctrl_enet>;
 	phy-mode = "rgmii-id";
 	status = "okay";
+	phy-handle = <&phy0>;
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy0: ethernet-phy@4 {
+			reg = <4>;
+			qca,clk-out-frequency = <125000000>;
+		};
+	};
 };

 &hdmi {
--- a/arch/arm/dts/imx6q-bx50v3-uboot.dtsi
+++ b/arch/arm/dts/imx6q-bx50v3-uboot.dtsi
@ -27,7 +27,7 @@
 		#size-cells = <1>;

 		vpd@0 {
-			reg = <0 1022>;
+			reg = <0 800>;
 		};

 		bootcount: bootcount {
--- a/arch/arm/dts/imx6qdl-aristainetos2-common.dtsi
+++ b/arch/arm/dts/imx6qdl-aristainetos2-common.dtsi
@ -1,6 +1,6 @@
 // SPDX-License-Identifier: (GPL-2.0)
 /*
- * support for the imx6 based aristainetos2 board
+ * support for the imx6 based aristainetos2 boards
 * parts common to all versions
 *
 * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
@ -13,6 +13,8 @@
 / {
 	aliases {
 		eeprom0 = &i2c_eeprom0;
+		eeprom1 = &i2c_eeprom1;
+		eeprom2 = &i2c_eeprom2;
 		pmic0 = &i2c_pmic0;
 	};

@ -250,6 +252,12 @@
 		};
 	};

+	i2c_eeprom2: eeprom@57{
+		compatible = "atmel,24c64";
+		reg = <0x57>;
+		pagesize = <32>;
+	};
+
 	rtc@68 {
 		compatible = "st,m41t11";
 		reg = <0x68>;
@ -274,6 +282,19 @@
 	};
 };

+&gpio2 {
+	tpm_pp {
+		gpio-hog;
+		output-low;
+		gpios = <17 GPIO_ACTIVE_HIGH>;
+	};
+	tpm_reset {
+		gpio-hog;
+		output-high;
+		gpios = <18 GPIO_ACTIVE_HIGH>;
+	};
+};
+
 &gpio6 {
 	spi_bus_ena {
 		gpio-hog;
--- a/arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi
+++ b/arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi
@ -50,28 +50,6 @@
 	};
 };

-&iomuxc {
-	pinctrl-0 = <&pinctrl_gpio &pinctrl_gpio_fix>;
-	u-boot,dm-pre-reloc;
-
-	pinctrl_gpio_fix: gpiofixgrp {
-		/*
-		 * usdhc2 has a levelshifter on the carrier board Rev. DV1,
-		 * that will automatically detect the driving direction.
-		 * During initialisation this isn't working correctly,
-		 * which causes DAT3 to be driven low towards the SD-card.
-		 * This causes a SD-card enetring the SPI-Mode
-		 * and therefore getting inaccessible until next power cycle.
-		 * As workaround we drive the DAT3 line as GPIO and set it high.
-		 * This makes usdhc2 unusable in u-boot, but works for the
-		 * initialisation in Linux
-		 */
-		fsl,pins = <
-			MX6QDL_PAD_SD2_DAT3__GPIO1_IO12	0x20000
-		>;
-	};
-};
-
 &gpio1 {
 	usdhc_fix {
 		gpio-hog;
--- a/arch/arm/dts/imx6qdl-aristainetos2.dtsi
+++ b/arch/arm/dts/imx6qdl-aristainetos2.dtsi
@ -1,244 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0)
-/*
- * support for the imx6 based aristainetos2 board
- *
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
- *
- */
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/clock/imx6qdl-clock.h>
-
-#include "imx6qdl-aristainetos2-common.dtsi"
-
-/ {
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_gpio>;
-
-		LED_blue {
-			label = "led_blue";
-			gpios = <&gpio2 29 GPIO_ACTIVE_LOW>;
-		};
-
-		LED_green {
-			label = "led_green";
-			gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
-		};
-
-		LED_red {
-			label = "led_red";
-			gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
-		};
-
-		LED_yellow {
-			label = "led_yellow";
-			gpios = <&gpio6 16 GPIO_ACTIVE_LOW>;
-		};
-
-		LED_ena {
-			label = "led_ena";
-			gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-&ecspi1 {
-	fsl,spi-num-chipselects = <3>;
-	cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH
-		    &gpio4 10 GPIO_ACTIVE_HIGH
-		    &gpio4 11 GPIO_ACTIVE_HIGH>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi1>;
-	status = "okay";
-};
-
-&ecspi4 {
-	fsl,spi-num-chipselects = <2>;
-	cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi4>;
-	status = "okay";
-	pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
-
-	flash: m25p80@1 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "micron,n25q128a11", "jedec,spi-nor";
-		spi-max-frequency = <20000000>;
-		reg = <1>;
-	};
-};
-
-&gpio7 {
-	sd2_driver_ena {
-		gpio-hog;
-		output-high;
-		gpios = <8 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&gpmi {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_gpmi_nand>;
-	status = "okay";
-};
-
-&can1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_flexcan1>;
-	status = "okay";
-};
-
-&can2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_flexcan2>;
-	status = "okay";
-};
-
-&usdhc1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc1>;
-	cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
-	no-1-8-v;
-	status = "okay";
-};
-
-&usdhc2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc2>;
-	cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
-	wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
-	no-1-8-v;
-	status = "okay";
-};
-
-&iomuxc {
-	pinctrl_ecspi1: ecspi1grp {
-		fsl,pins = <
-			MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
-			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
-			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
-			MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x100b1 /* SS0# */
-			MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 /* SS1# */
-			MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 /* SS2# */
-		>;
-	};
-
-	pinctrl_ecspi4: ecspi4grp {
-		fsl,pins = <
-			MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
-			MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
-			MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
-			MX6QDL_PAD_EIM_D29__GPIO3_IO29  0x100b1 /* SS0# */
-			MX6QDL_PAD_EIM_A25__GPIO5_IO02  0x100b1 /* SS1# */
-			MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0 /* WP pin */
-		>;
-	};
-
-	pinctrl_gpio: gpiogrp {
-		fsl,pins = <
-			/* led enable */
-			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25	0x4001b0b0
-			/* LCD power enable */
-			MX6QDL_PAD_NANDF_CS2__GPIO6_IO15	0x4001b0b0
-			/* led yellow */
-			MX6QDL_PAD_NANDF_CS3__GPIO6_IO16	0x4001b0b0
-			/* led red */
-			MX6QDL_PAD_EIM_EB0__GPIO2_IO28		0x4001b0b0
-			/* led green */
-			MX6QDL_PAD_EIM_A24__GPIO5_IO04		0x4001b0b0
-			/* led blue */
-			MX6QDL_PAD_EIM_EB1__GPIO2_IO29		0x4001b0b0
-			/* Profibus IRQ */
-			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x1b0b0
-			/* FPGA IRQ currently unused*/
-			MX6QDL_PAD_SD3_DAT6__GPIO6_IO18		0x1b0b0
-			/* Display reset because of clock failure */
-			MX6QDL_PAD_SD4_DAT3__GPIO2_IO11		0x4001b0b0
-			/* spi bus #2 SS driver enable */
-			MX6QDL_PAD_EIM_A23__GPIO6_IO06		0x4001b0b0
-			/* RST_LOC# PHY reset input (has pull-down!)*/
-			MX6QDL_PAD_GPIO_18__GPIO7_IO13		0x4001b0b0
-			/* USB_OTG_ID = GPIO1_24*/
-			MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID	0x4001b0b0
-			/* Touchscreen IRQ */
-			MX6QDL_PAD_SD4_DAT1__GPIO2_IO09		0x1b0b0
-			/* PCIe reset */
-			MX6QDL_PAD_EIM_A22__GPIO2_IO16		0x4001b0b0
-		>;
-	};
-
-	pinctrl_gpmi_nand: gpmi-nand {
-		fsl,pins = <
-			MX6QDL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
-			MX6QDL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
-			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
-			MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
-			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
-			MX6QDL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
-			MX6QDL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
-			MX6QDL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
-			MX6QDL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
-			MX6QDL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
-			MX6QDL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
-			MX6QDL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
-			MX6QDL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
-			MX6QDL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
-			MX6QDL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
-		>;
-	};
-
-	pinctrl_flexcan1: flexcan1grp {
-		fsl,pins = <
-			MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0
-			MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0
-		>;
-	};
-
-	pinctrl_flexcan2: flexcan2grp {
-		fsl,pins = <
-			MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
-			MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
-		>;
-	};
-
-	pinctrl_usbotg: usbotggrp {
-		fsl,pins = <
-			MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
-		>;
-	};
-
-	pinctrl_usdhc1: usdhc1grp {
-		fsl,pins = <
-			MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17059
-			MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10059
-			MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
-			MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
-			MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
-			MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
-			/* SD1 card detect input */
-			MX6QDL_PAD_ENET_RXD0__GPIO1_IO27	0x1b0b0
-			/* SD1 write protect input */
-			MX6QDL_PAD_DI0_PIN4__GPIO4_IO20		0x1b0b0
-		>;
-	};
-
-	pinctrl_usdhc2: usdhc2grp {
-		fsl,pins = <
-			MX6QDL_PAD_SD2_CMD__SD2_CMD    0x71
-			MX6QDL_PAD_SD2_CLK__SD2_CLK    0x71
-			MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71
-			MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71
-			MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71
-			MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71
-			/* SD2 level shifter output enable */
-			MX6QDL_PAD_SD3_RST__GPIO7_IO08		0x4001b0b0
-			/* SD2 card detect input */
-			MX6QDL_PAD_GPIO_19__GPIO4_IO05		0x1b0b0
-			/* SD2 write protect input */
-			MX6QDL_PAD_SD4_DAT2__GPIO2_IO10		0x1b0b0
-		>;
-	};
-};
--- a/arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi
+++ b/arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi
@ -1,77 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ or X11
-/*
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- */
-
-/ {
-	chosen {
-		u-boot,dm-pre-reloc;
-		stdout-path = &uart2;
-	};
-
-	wdt-reboot {
-		compatible = "wdt-reboot";
-		wdt = <&wdog1>;
-	};
-};
-
-&uart2 {
-	u-boot,dm-pre-reloc;
-};
-
-&pinctrl_gpio {
-	u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart2 {
-	u-boot,dm-pre-reloc;
-};
-
-&iomuxc {
-	u-boot,dm-pre-reloc;
-};
-
-&aips2 {
-	u-boot,dm-pre-reloc;
-};
-
-&backlight {
-	pwms = <&pwm1 0 300000>;
-	default-brightness-level = <2>;
-};
-
-/*
- * allow switching write protect / reset pin by gpio,
- * because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot
- */
-&gpio2 {
-	u-boot,dm-pre-reloc;
-
-	wp_spi_nor {
-		gpio-hog;
-		output-high;
-		gpios = <15 GPIO_ACTIVE_HIGH>;
-	};
-
-	reset_spi_nor {
-		gpio-hog;
-		output-high;
-		gpios = <28 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&gpio4 {
-	u-boot,dm-pre-reloc;
-};
-
-&ecspi1 {
-	u-boot,dm-pre-reloc;
-};
-
-&flash {
-	u-boot,dm-pre-reloc;
-};
-
-&pinctrl_ecspi1 {
-	u-boot,dm-pre-reloc;
-};
--- a/arch/arm/dts/imx6qdl-aristainetos2b.dtsi
+++ b/arch/arm/dts/imx6qdl-aristainetos2b.dtsi
@ -1,266 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0)
-/*
- * support for the imx6 based aristainetos2b board
- *
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
- *
- */
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/clock/imx6qdl-clock.h>
-
-#include "imx6qdl-aristainetos2-common.dtsi"
-
-/ {
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_gpio>;
-
-		LED_blue {
-			label = "led_blue";
-			gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
-		};
-
-		LED_green {
-			label = "led_green";
-			gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
-		};
-
-		LED_red {
-			label = "led_red";
-			gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
-		};
-
-		LED_yellow {
-			label = "led_yellow";
-			gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
-		};
-
-		LED_ena {
-			label = "led_ena";
-			gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-&ecspi1 {
-	fsl,spi-num-chipselects = <3>;
-	cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH
-		    &gpio4 10 GPIO_ACTIVE_HIGH
-		    &gpio4 11 GPIO_ACTIVE_HIGH>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi1>;
-	status = "okay";
-	pinctrl-assert-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
-	pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
-
-	flash: m25p80@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "micron,n25q128a11", "jedec,spi-nor";
-		spi-max-frequency = <20000000>;
-		reg = <0>;
-	};
-};
-
-&ecspi4 {
-	fsl,spi-num-chipselects = <2>;
-	cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi4>;
-	status = "okay";
-};
-
-&i2c1 {
-	tpm@20 {
-		compatible = "infineon,slb9645tt";
-		reg = <0x20>;
-	};
-};
-
-&gpio7 {
-	sd2_driver_ena {
-		gpio-hog;
-		output-high;
-		gpios = <8 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&gpmi {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_gpmi_nand>;
-	status = "okay";
-};
-
-&can1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_flexcan1>;
-	status = "okay";
-};
-
-&can2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_flexcan2>;
-	status = "okay";
-};
-
-&usdhc1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc1>;
-	cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
-	wp-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>;
-	no-1-8-v;
-	status = "okay";
-};
-
-&usdhc2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc2>;
-	/*
-	 * comment out this line to make the WiFi Eval-Module work in
-	 * SD-Slot2, and add line:
-	 * broken-cd;
-	 * causes 6% CPU load if no WiFi module installed (polling)
-	 */
-	cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
-	wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
-	no-1-8-v;
-	status = "okay";
-};
-
-&iomuxc {
-	pinctrl_ecspi1: ecspi1grp {
-		fsl,pins = <
-			MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
-			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
-			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
-			/* SS0# */
-			MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1
-			/* SS1# */
-			MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1
-			/* SS2# */
-			MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1
-			/* WP pin NOR Flash */
-			MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0
-			/* Flash nReset */
-			MX6QDL_PAD_EIM_EB0__GPIO2_IO28  0x4001b0b0
-		>;
-	};
-
-	pinctrl_ecspi4: ecspi4grp {
-		fsl,pins = <
-			MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
-			MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
-			MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
-			MX6QDL_PAD_EIM_D29__GPIO3_IO29  0x100b1 /* SS0# */
-			MX6QDL_PAD_EIM_A25__GPIO5_IO02  0x100b1 /* SS1# */
-		>;
-	};
-
-	pinctrl_gpio: gpiogrp {
-		fsl,pins = <
-			/* led enable */
-			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25	0x4001b0b0
-			/* LCD power enable */
-			MX6QDL_PAD_NANDF_CS2__GPIO6_IO15	0x4001b0b0
-			/* led yellow */
-			MX6QDL_PAD_NANDF_CS3__GPIO6_IO16	0x4001b0b0
-			/* led red */
-			MX6QDL_PAD_EIM_WAIT__GPIO5_IO00		0x4001b0b0
-			/* led green */
-			MX6QDL_PAD_EIM_A24__GPIO5_IO04		0x4001b0b0
-			/* led blue */
-			MX6QDL_PAD_EIM_EB1__GPIO2_IO29		0x4001b0b0
-			/* Profibus IRQ */
-			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x1b0b0
-			/* FPGA IRQ currently unused*/
-			MX6QDL_PAD_SD3_DAT6__GPIO6_IO18		0x1b0b0
-			/* Display reset because of clock failure */
-			MX6QDL_PAD_SD4_DAT3__GPIO2_IO11		0x4001b0b0
-			/* spi bus #2 SS driver enable */
-			MX6QDL_PAD_EIM_A23__GPIO6_IO06		0x4001b0b0
-			/* RST_LOC# PHY reset input (has pull-down!)*/
-			MX6QDL_PAD_GPIO_18__GPIO7_IO13		0x4001b0b0
-			/* Touchscreen IRQ */
-			MX6QDL_PAD_SD4_DAT1__GPIO2_IO09		0x1b0b0
-			/* PCIe reset */
-			MX6QDL_PAD_EIM_A22__GPIO2_IO16		0x4001b0b0
-			/* make sure pin is GPIO and not ENET_REF_CLK */
-			MX6QDL_PAD_GPIO_16__GPIO7_IO11		0x4001a0b0
-			/* SD2 level shifter output enable / SD2 Reset# */
-			MX6QDL_PAD_SD3_RST__GPIO7_IO08		0x4001b0b0
-		>;
-	};
-
-	pinctrl_gpmi_nand: gpmi-nand {
-		fsl,pins = <
-			MX6QDL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
-			MX6QDL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
-			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
-			MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
-			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
-			MX6QDL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
-			MX6QDL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
-			MX6QDL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
-			MX6QDL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
-			MX6QDL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
-			MX6QDL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
-			MX6QDL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
-			MX6QDL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
-			MX6QDL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
-			MX6QDL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
-		>;
-	};
-
-	pinctrl_flexcan1: flexcan1grp {
-		fsl,pins = <
-			MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0
-			MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0
-		>;
-	};
-
-	pinctrl_flexcan2: flexcan2grp {
-		fsl,pins = <
-			MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
-			MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
-		>;
-	};
-
-	pinctrl_usbotg: usbotggrp {
-		fsl,pins = <
-			MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID  0x17059
-			MX6QDL_PAD_KEY_COL4__USB_OTG_OC    0x1b0b0
-		>;
-	};
-
-	pinctrl_usdhc1: usdhc1grp {
-		fsl,pins = <
-			MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17059
-			MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10059
-			MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
-			MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
-			MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
-			MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
-			/* SD1 card detect input */
-			MX6QDL_PAD_ENET_RXD0__GPIO1_IO27	0x1b0b0
-			/* SD1 write protect input */
-			MX6QDL_PAD_DI0_PIN4__GPIO4_IO20		0x1b0b0
-		>;
-	};
-
-	pinctrl_usdhc2: usdhc2grp {
-		fsl,pins = <
-			MX6QDL_PAD_SD2_CMD__SD2_CMD    0x71
-			MX6QDL_PAD_SD2_CLK__SD2_CLK    0x71
-			MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71
-			MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71
-			MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71
-			MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71
-			/* SD2 card detect input */
-			MX6QDL_PAD_GPIO_19__GPIO4_IO05		0x1b0b0
-			/* SD2 write protect input */
-			MX6QDL_PAD_SD4_DAT2__GPIO2_IO10		0x1b0b0
-		>;
-	};
-};
--- a/arch/arm/dts/imx6qdl-aristainetos2c.dtsi
+++ b/arch/arm/dts/imx6qdl-aristainetos2c.dtsi
@ -1,6 +1,6 @@
 // SPDX-License-Identifier: (GPL-2.0)
 /*
- * support for the imx6 based aristainetos2c board
+ * support for the imx6 based aristainetos2c+2d boards
 *
 * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
 * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
@ -79,6 +79,14 @@
 	};
 };

+&gpio7 {
+	eMMC_reset {
+		gpio-hog;
+		output-high;
+		gpios = <8 GPIO_ACTIVE_HIGH>;
+	};
+};
+
 &can1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_flexcan1>;
@ -172,6 +180,8 @@
 			MX6QDL_PAD_EIM_A21__GPIO2_IO17		0x4001b0b0
 			/* TPM Reset */
 			MX6QDL_PAD_EIM_A20__GPIO2_IO18		0x4001b0b0
+			/* eMMC Reset# */
+			MX6QDL_PAD_SD3_RST__GPIO7_IO08		0x4001b0b0
 		>;
 	};

--- a/arch/arm/dts/imx6qdl-aristainetos2c_cslb-u-boot.dtsi
+++ b/arch/arm/dts/imx6qdl-aristainetos2c_cslb-u-boot.dtsi
--- a/arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi
+++ b/arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi
@ -1,6 +1,6 @@
 // SPDX-License-Identifier: (GPL-2.0)
 /*
- * support for the imx6 based aristainetos2b-csl board
+ * support for the imx6 based aristainetos2c-cslb board
 *
 * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
 * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
@ -104,19 +104,13 @@
 };

 &gpio7 {
-	wlan_reset {
+	eMMC_reset {
 		gpio-hog;
 		output-high;
 		gpios = <8 GPIO_ACTIVE_HIGH>;
 	};
 };

-&gpmi {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_gpmi_nand>;
-	status = "okay";
-};
-
 &usdhc1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc1>;
@ -127,7 +121,9 @@
 &usdhc2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc2>;
+	bus-width = <8>;
 	no-1-8-v;
+	non-removable;
 	status = "okay";
 };

@ -190,31 +186,15 @@
 			MX6QDL_PAD_EIM_A22__GPIO2_IO16		0x4001b0b0
 			/* make sure pin is GPIO and not ENET_REF_CLK */
 			MX6QDL_PAD_GPIO_16__GPIO7_IO11		0x4001a0b0
-			/* WLAN Module Reset# */
+			/* TPM PP */
+			MX6QDL_PAD_EIM_A21__GPIO2_IO17		0x4001b0b0
+			/* TPM Reset */
+			MX6QDL_PAD_EIM_A20__GPIO2_IO18		0x4001b0b0
+			/* eMMC Reset# */
 			MX6QDL_PAD_SD3_RST__GPIO7_IO08		0x4001b0b0
 		>;
 	};

-	pinctrl_gpmi_nand: gpmi-nand {
-		fsl,pins = <
-			MX6QDL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
-			MX6QDL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
-			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
-			MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
-			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
-			MX6QDL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
-			MX6QDL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
-			MX6QDL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
-			MX6QDL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
-			MX6QDL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
-			MX6QDL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
-			MX6QDL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
-			MX6QDL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
-			MX6QDL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
-			MX6QDL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
-		>;
-	};
-
 	pinctrl_usbotg: usbotggrp {
 		fsl,pins = <
 			MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID  0x17059
@ -237,12 +217,16 @@

 	pinctrl_usdhc2: usdhc2grp {
 		fsl,pins = <
-			MX6QDL_PAD_SD2_CMD__SD2_CMD    0x71
-			MX6QDL_PAD_SD2_CLK__SD2_CLK    0x71
-			MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71
-			MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71
-			MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71
-			MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71
+			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
+			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
+			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
+			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
+			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
+			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
+			MX6QDL_PAD_NANDF_D4__SD2_DATA4		0x17059
+			MX6QDL_PAD_NANDF_D5__SD2_DATA5		0x17059
+			MX6QDL_PAD_NANDF_D6__SD2_DATA6		0x17059
+			MX6QDL_PAD_NANDF_D7__SD2_DATA7		0x17059
 		>;
 	};
 };
--- a/arch/arm/dts/imx6ull-dart-6ul.dtsi
+++ b/arch/arm/dts/imx6ull-dart-6ul.dtsi
@ -14,6 +14,10 @@
 	chosen {
 		stdout-path = &uart1;
 	};
+
+	aliases {
+		eeprom0 = &eeprom_som;
+	};
 };

 &fec1 {
@ -52,6 +56,10 @@
 	};
 };

+&gpio1 {
+	u-boot,dm-pre-reloc;
+};
+
 &gpmi {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gpmi_nand>;
@ -96,10 +104,13 @@
 	scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
 	sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
 	status = "okay";
+	u-boot,dm-pre-reloc;

-	eeprom@50 {
-		compatible = "cat,24c32";
+	eeprom_som: eeprom@50 {
+		u-boot,dm-pre-reloc;
+		compatible = "atmel,24c04";
 		reg = <0x50>;
+		status = "okay";
 	};
 };

@ -205,6 +216,7 @@
 	};

 	pinctrl_i2c2: i2cgrp {
+		u-boot,dm-pre-reloc;
 		fsl,pins = <
 			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL       0x4001b8b0
 			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA       0x4001b8b0
@ -212,6 +224,7 @@
 	};

 	pinctrl_i2c2_gpio: i2c2grp_gpio {
+		u-boot,dm-pre-reloc;
 		fsl,pins = <
 			MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30	0x1b8b0
 			MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31	0x1b8b0
--- a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
+++ b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
@ -10,19 +10,19 @@
 		led0 {
 			label = "gen_led0";
 			gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
-			default-state = "none";
+			default-state = "off";
 		};

 		led1 {
 			label = "gen_led1";
 			gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
-			default-state = "none";
+			default-state = "off";
 		};

 		led2 {
 			label = "gen_led2";
 			gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
-			default-state = "none";
+			default-state = "off";
 		};

 		led3 {
@ -70,7 +70,7 @@
 &ecspi2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_espi2>;
-	cs-gpios = <&gpio5 9 0>;
+	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
 	status = "okay";

 	eeprom@0 {
@ -210,7 +210,7 @@
 		>;
 	};

-	pinctrl_pcal6414: pcal6414-gpio {
+	pinctrl_pcal6414: pcal6414-gpiogrp {
 		fsl,pins = <
 			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27		0x19
 		>;
@ -240,7 +240,7 @@
 		>;
 	};

-	pinctrl_usdhc2_gpio: usdhc2grpgpio {
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 		fsl,pins = <
 			MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B	0x41
 			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
@ -259,7 +259,7 @@
 		>;
 	};

-	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 		fsl,pins = <
 			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x194
 			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d4
@ -271,7 +271,7 @@
 		>;
 	};

-	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 		fsl,pins = <
 			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x196
 			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d6
--- a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
@ -37,6 +37,10 @@
 	/delete-property/ assigned-clock-rates;
 };

+&reg_usdhc2_vmmc {
+	u-boot,off-on-delay-us = <20000>;
+};
+
 &fec1 {
 	phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
 };
--- a/arch/arm/dts/imx8mm-beacon-som.dtsi
+++ b/arch/arm/dts/imx8mm-beacon-som.dtsi
@ -24,6 +24,26 @@
 	cpu-supply = <&buck2_reg>;
 };

+&ddrc {
+	operating-points-v2 = <&ddrc_opp_table>;
+
+	ddrc_opp_table: opp-table {
+		compatible = "operating-points-v2";
+
+		opp-25M {
+			opp-hz = /bits/ 64 <25000000>;
+		};
+
+		opp-100M {
+			opp-hz = /bits/ 64 <100000000>;
+		};
+
+		opp-750M {
+			opp-hz = /bits/ 64 <750000000>;
+		};
+	};
+};
+
 &fec1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec1>;
@ -52,9 +72,10 @@
 	pmic@4b {
 		compatible = "rohm,bd71847";
 		reg = <0x4b>;
+		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_pmic>;
 		interrupt-parent = <&gpio1>;
-		interrupts = <3 GPIO_ACTIVE_LOW>;
+		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 		rohm,reset-snvs-powered;

 		regulators {
@ -116,7 +137,7 @@

 			ldo1_reg: LDO1 {
 				regulator-name = "ldo1";
-				regulator-min-microvolt = <3000000>;
+				regulator-min-microvolt = <1600000>;
 				regulator-max-microvolt = <3300000>;
 				regulator-boot-on;
 				regulator-always-on;
@ -124,7 +145,7 @@

 			ldo2_reg: LDO2 {
 				regulator-name = "ldo2";
-				regulator-min-microvolt = <900000>;
+				regulator-min-microvolt = <800000>;
 				regulator-max-microvolt = <900000>;
 				regulator-boot-on;
 				regulator-always-on;
@ -164,7 +185,7 @@
 	status = "okay";

 	eeprom@50 {
-		compatible = "microchip, at24c64d", "atmel,24c64";
+		compatible = "microchip,24c64", "atmel,24c64";
 		pagesize = <32>;
 		read-only;	/* Manufacturing EEPROM programmed at factory */
 		reg = <0x50>;
@ -190,6 +211,7 @@
 		host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
 		device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
 		clocks = <&osc_32k>;
+		max-speed = <4000000>;
 		clock-names = "extclk";
 	};
 };
@ -270,9 +292,9 @@
 			>;
 		};

-		pinctrl_pmic: pmicirq {
+		pinctrl_pmic: pmicirqgrp {
 			fsl,pins = <
-				MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x41
+				MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x141
 			>;
 		};

@ -289,7 +311,7 @@
 			>;
 		};

-		pinctrl_usdhc1_gpio: usdhc1grpgpio {
+		pinctrl_usdhc1_gpio: usdhc1gpiogrp {
 			fsl,pins = <
 				MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x41
 			>;
@ -306,7 +328,7 @@
 			>;
 		};

-		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+		pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
 			fsl,pins = <
 				MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
 				MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
@ -317,7 +339,7 @@
 			>;
 		};

-		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+		pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
 			fsl,pins = <
 				MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
 				MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
@ -344,7 +366,7 @@
 			>;
 		};

-		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+		pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 			fsl,pins = <
 				MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
 				MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
@ -360,7 +382,7 @@
 			>;
 		};

-		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+		pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 			fsl,pins = <
 				MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
 				MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
--- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
@ -46,6 +46,10 @@
 	u-boot,dm-spl;
 };

+&reg_usdhc2_vmmc {
+	u-boot,off-on-delay-us = <20000>;
+};
+
 &pinctrl_reg_usdhc2_vmmc {
 	u-boot,dm-spl;
 };
@ -96,10 +100,14 @@

 &usdhc2 {
 	u-boot,dm-spl;
+	sd-uhs-sdr104;
+	sd-uhs-ddr50;
 };

 &usdhc3 {
 	u-boot,dm-spl;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
 };

 &i2c1 {
--- a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi
@ -2,7 +2,6 @@
 /*
 * Copyright 2020 Toradex
 */
-
 / {
 	wdt-reboot {
 		compatible = "wdt-reboot";
@ -90,11 +89,11 @@
 	u-boot,dm-spl;
 };

-&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
+&{/soc@0/bus@30800000/i2c@30a20000/pmic} {
 	u-boot,dm-spl;
 };

-&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
+&{/soc@0/bus@30800000/i2c@30a20000/pmic/regulators} {
 	u-boot,dm-spl;
 };

--- a/arch/arm/dts/imx8mm-verdin.dts
+++ b/arch/arm/dts/imx8mm-verdin.dts
@ -203,115 +203,123 @@
 	pinctrl-0 = <&pinctrl_i2c1>;
 	status = "okay";

-	pmic@4b {
-		compatible = "rohm,bd71840", "rohm,bd71837";
-		bd71837,pmic-buck2-uses-i2c-dvs;
-		bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */
-		gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
-		/* PMIC BD71837 PMIC_nINT GPIO1_IO3 */
+	/* Assembled on V1.1 HW and later */
+	pmic {
+		reg = <0x25>;
+		u-boot,dm-spl;
+		compatible = "nxp,pca9450a";
+		/* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
 		pinctrl-0 = <&pinctrl_pmic>;
-		reg = <0x4b>;
-
-		gpo {
-			rohm,drv = <0x0C>;	/* 0b0000_1100 all gpos with cmos output mode */
-		};
+		gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;

 		regulators {
-			buck1_reg: BUCK1 {
-				regulator-always-on;
-				regulator-boot-on;
+			u-boot,dm-spl;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pca9450,pmic-buck2-uses-i2c-dvs;
+			/* Run/Standby voltage */
+			pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;
+
+			buck1_reg: regulator@0 {
+				reg = <0>;
 				regulator-compatible = "buck1";
-				regulator-max-microvolt = <1300000>;
-				regulator-min-microvolt = <700000>;
-				regulator-ramp-delay = <1250>;
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
 			};

-			buck2_reg: BUCK2 {
-				regulator-always-on;
-				regulator-boot-on;
+			buck2_reg: regulator@1 {
+				reg = <1>;
 				regulator-compatible = "buck2";
-				regulator-max-microvolt = <1300000>;
-				regulator-min-microvolt = <700000>;
-				regulator-ramp-delay = <1250>;
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
 			};

-			buck5_reg: BUCK5 {
-				regulator-always-on;
+			buck3_reg: regulator@2 {
+				reg = <2>;
+				regulator-compatible = "buck3";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
 				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck4_reg: regulator@3 {
+				reg = <3>;
+				regulator-compatible = "buck4";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck5_reg: regulator@4 {
+				reg = <4>;
 				regulator-compatible = "buck5";
-				regulator-max-microvolt = <1350000>;
-				regulator-min-microvolt = <700000>;
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
 			};

-			buck6_reg: BUCK6 {
-				regulator-always-on;
-				regulator-boot-on;
+			buck6_reg: regulator@5 {
+				reg = <5>;
 				regulator-compatible = "buck6";
-				regulator-max-microvolt = <3300000>;
-				regulator-min-microvolt = <3000000>;
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
 			};

-			buck7_reg: BUCK7 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-compatible = "buck7";
-				regulator-max-microvolt = <1995000>;
-				regulator-min-microvolt = <1605000>;
-			};
-
-			buck8_reg: BUCK8 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-compatible = "buck8";
-				regulator-max-microvolt = <1400000>;
-				regulator-min-microvolt = <800000>;
-			};
-
-			ldo1_reg: LDO1 {
-				regulator-always-on;
-				regulator-boot-on;
+			ldo1_reg: regulator@6 {
+				reg = <6>;
 				regulator-compatible = "ldo1";
+				regulator-min-microvolt = <1600000>;
 				regulator-max-microvolt = <3300000>;
-				regulator-min-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
 			};

-			ldo2_reg: LDO2 {
-				regulator-always-on;
-				regulator-boot-on;
+			ldo2_reg: regulator@7 {
+				reg = <7>;
 				regulator-compatible = "ldo2";
-				regulator-max-microvolt = <900000>;
-				regulator-min-microvolt = <900000>;
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1150000>;
+				regulator-boot-on;
+				regulator-always-on;
 			};

-			ldo3_reg: LDO3 {
-				regulator-always-on;
-				regulator-boot-on;
+			ldo3_reg: regulator@8 {
+				reg = <8>;
 				regulator-compatible = "ldo3";
+				regulator-min-microvolt = <800000>;
 				regulator-max-microvolt = <3300000>;
-				regulator-min-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
 			};

-			ldo4_reg: LDO4 {
-				regulator-always-on;
-				regulator-boot-on;
+			ldo4_reg: regulator@9 {
+				reg = <9>;
 				regulator-compatible = "ldo4";
-				regulator-max-microvolt = <1800000>;
-				regulator-min-microvolt = <900000>;
-			};
-
-			ldo5_reg: LDO5 {
-				regulator-compatible = "ldo5";
+				regulator-min-microvolt = <800000>;
 				regulator-max-microvolt = <3300000>;
-				regulator-min-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
 			};

-			ldo6_reg: LDO6 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-compatible = "ldo6";
-				regulator-max-microvolt = <1800000>;
-				regulator-min-microvolt = <900000>;
+			ldo5_reg: regulator@10 {
+				reg = <10>;
+				regulator-compatible = "ldo5";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
 			};
+
 		};
 	};

@ -321,12 +329,6 @@
 		reg = <0x32>;
 	};

-	adc@34 {
-		compatible = "maxim,max11607";
-		reg = <0x34>;
-		vcc-supply = <&ldo5_reg>;
-	};
-
 	eeprom_module: eeprom@50 {
 		compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
 		pagesize = <16>;
--- a/arch/arm/dts/imx8mm.dtsi
+++ b/arch/arm/dts/imx8mm.dtsi
@ -18,10 +18,18 @@

 	aliases {
 		ethernet0 = &fec1;
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
 		i2c0 = &i2c1;
 		i2c1 = &i2c2;
 		i2c2 = &i2c3;
 		i2c3 = &i2c4;
+		mmc0 = &usdhc1;
+		mmc1 = &usdhc2;
+		mmc2 = &usdhc3;
 		serial0 = &uart1;
 		serial1 = &uart2;
 		serial2 = &uart3;
@ -29,14 +37,6 @@
 		spi0 = &ecspi1;
 		spi1 = &ecspi2;
 		spi2 = &ecspi3;
-		mmc0 = &usdhc1;
-		mmc1 = &usdhc2;
-		mmc2 = &usdhc3;
-		gpio0 = &gpio1;
-		gpio1 = &gpio2;
-		gpio2 = &gpio3;
-		gpio3 = &gpio4;
-		gpio4 = &gpio5;
 	};

 	cpus {
@ -68,6 +68,7 @@
 			nvmem-cells = <&cpu_speed_grade>;
 			nvmem-cell-names = "speed_grade";
 			cpu-idle-states = <&cpu_pd_wait>;
+			#cooling-cells = <2>;
 		};

 		A53_1: cpu@1 {
@ -80,6 +81,7 @@
 			next-level-cache = <&A53_L2>;
 			operating-points-v2 = <&a53_opp_table>;
 			cpu-idle-states = <&cpu_pd_wait>;
+			#cooling-cells = <2>;
 		};

 		A53_2: cpu@2 {
@ -92,6 +94,7 @@
 			next-level-cache = <&A53_L2>;
 			operating-points-v2 = <&a53_opp_table>;
 			cpu-idle-states = <&cpu_pd_wait>;
+			#cooling-cells = <2>;
 		};

 		A53_3: cpu@3 {
@ -104,6 +107,7 @@
 			next-level-cache = <&A53_L2>;
 			operating-points-v2 = <&a53_opp_table>;
 			cpu-idle-states = <&cpu_pd_wait>;
+			#cooling-cells = <2>;
 		};

 		A53_L2: l2-cache0 {
@ -125,7 +129,7 @@

 		opp-1600000000 {
 			opp-hz = /bits/ 64 <1600000000>;
-			opp-microvolt = <900000>;
+			opp-microvolt = <950000>;
 			opp-supported-hw = <0xc>, <0x7>;
 			clock-latency-ns = <150000>;
 			opp-suspend;
@ -204,6 +208,38 @@
 		arm,no-tick-in-suspend;
 	};

+	thermal-zones {
+		cpu-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <2000>;
+			thermal-sensors = <&tmu>;
+			trips {
+				cpu_alert0: trip0 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu_crit0: trip1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert0>;
+					cooling-device =
+						<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+	};
+
 	usbphynop1: usbphynop1 {
 		compatible = "usb-nop-xceiv";
 		clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
@ -227,12 +263,14 @@
 		ranges = <0x0 0x0 0x0 0x3e000000>;

 		aips1: bus@30000000 {
-			compatible = "simple-bus";
+			compatible = "fsl,aips-bus", "simple-bus";
+			reg = <0x30000000 0x400000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges = <0x30000000 0x30000000 0x400000>;

 			sai1: sai@30010000 {
+				#sound-dai-cells = <0>;
 				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 				reg = <0x30010000 0x10000>;
 				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
@ -246,6 +284,7 @@
 			};

 			sai2: sai@30020000 {
+				#sound-dai-cells = <0>;
 				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 				reg = <0x30020000 0x10000>;
 				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
@ -273,6 +312,7 @@
 			};

 			sai5: sai@30050000 {
+				#sound-dai-cells = <0>;
 				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 				reg = <0x30050000 0x10000>;
 				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
@ -286,6 +326,7 @@
 			};

 			sai6: sai@30060000 {
+				#sound-dai-cells = <0>;
 				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 				reg = <0x30060000 0x10000>;
 				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
@ -363,6 +404,13 @@
 				gpio-ranges = <&iomuxc 0 119 30>;
 			};

+			tmu: tmu@30260000 {
+				compatible = "fsl,imx8mm-tmu";
+				reg = <0x30260000 0x10000>;
+				clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
+				#thermal-sensor-cells = <0>;
+			};
+
 			wdog1: watchdog@30280000 {
 				compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
 				reg = <0x30280000 0x10000>;
@ -419,7 +467,7 @@
 				reg = <0x30340000 0x10000>;
 			};

-			ocotp: ocotp-ctrl@30350000 {
+			ocotp: efuse@30350000 {
 				compatible = "fsl,imx8mm-ocotp", "syscon";
 				reg = <0x30350000 0x10000>;
 				clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
@ -455,6 +503,8 @@
 					compatible = "fsl,sec-v4.0-pwrkey";
 					regmap = <&snvs>;
 					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
+					clock-names = "snvs-pwrkey";
 					linux,keycode = <KEY_POWER>;
 					wakeup-source;
 					status = "disabled";
@ -469,16 +519,20 @@
 					 <&clk_ext3>, <&clk_ext4>;
 				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
 					      "clk_ext3", "clk_ext4";
-				assigned-clocks = <&clk IMX8MM_CLK_NOC>,
+				assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
+						<&clk IMX8MM_CLK_A53_CORE>,
+						<&clk IMX8MM_CLK_NOC>,
 						<&clk IMX8MM_CLK_AUDIO_AHB>,
 						<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
 						<&clk IMX8MM_SYS_PLL3>,
 						<&clk IMX8MM_VIDEO_PLL1>,
 						<&clk IMX8MM_AUDIO_PLL1>,
 						<&clk IMX8MM_AUDIO_PLL2>;
-				assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
+				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
+							 <&clk IMX8MM_ARM_PLL_OUT>,
+							 <&clk IMX8MM_SYS_PLL3_OUT>,
 							 <&clk IMX8MM_SYS_PLL1_800M>;
-				assigned-clock-rates = <0>,
+				assigned-clock-rates = <0>, <0>, <0>,
 							<400000000>,
 							<400000000>,
 							<750000000>,
@ -496,7 +550,8 @@
 		};

 		aips2: bus@30400000 {
-			compatible = "simple-bus";
+			compatible = "fsl,aips-bus", "simple-bus";
+			reg = <0x30400000 0x400000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges = <0x30400000 0x30400000 0x400000>;
@ -555,10 +610,12 @@
 		};

 		aips3: bus@30800000 {
-			compatible = "simple-bus";
+			compatible = "fsl,aips-bus", "simple-bus";
+			reg = <0x30800000 0x400000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
-			ranges = <0x30800000 0x30800000 0x400000>;
+			ranges = <0x30800000 0x30800000 0x400000>,
+				 <0x8000000 0x8000000 0x10000000>;

 			ecspi1: spi@30820000 {
 				compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
@ -718,6 +775,14 @@
 				status = "disabled";
 			};

+			mu: mailbox@30aa0000 {
+				compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
+				reg = <0x30aa0000 0x10000>;
+				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_MU_ROOT>;
+				#mbox-cells = <2>;
+			};
+
 			usdhc1: mmc@30b40000 {
 				compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
 				reg = <0x30b40000 0x10000>;
@ -760,6 +825,19 @@
 				status = "disabled";
 			};

+			flexspi: spi@30bb0000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "nxp,imx8mm-fspi";
+				reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
+				reg-names = "fspi_base", "fspi_mmap";
+				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_QSPI_ROOT>,
+					 <&clk IMX8MM_CLK_QSPI_ROOT>;
+				clock-names = "fspi", "fspi_en";
+				status = "disabled";
+			};
+
 			sdma1: dma-controller@30bd0000 {
 				compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
 				reg = <0x30bd0000 0x10000>;
@ -776,7 +854,8 @@
 				reg = <0x30be0000 0x10000>;
 				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
 					 <&clk IMX8MM_CLK_ENET1_ROOT>,
 					 <&clk IMX8MM_CLK_ENET_TIMER>,
@ -800,7 +879,8 @@
 		};

 		aips4: bus@32c00000 {
-			compatible = "simple-bus";
+			compatible = "fsl,aips-bus", "simple-bus";
+			reg = <0x32c00000 0x400000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges = <0x32c00000 0x32c00000 0x400000>;
@ -896,7 +976,6 @@
 		ddr-pmu@3d800000 {
 			compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
 			reg = <0x3d800000 0x400000>;
-			interrupt-parent = <&gic>;
 			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 		};
 	};
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@ -47,6 +47,10 @@
 	u-boot,dm-spl;
 };

+&reg_usdhc2_vmmc {
+	u-boot,off-on-delay-us = <20000>;
+};
+
 &pinctrl_uart2 {
 	u-boot,dm-spl;
 };
@ -93,10 +97,14 @@

 &usdhc2 {
 	u-boot,dm-spl;
+	sd-uhs-sdr104;
+	sd-uhs-ddr50;
 };

 &usdhc3 {
 	u-boot,dm-spl;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
 };

 &wdog1 {
--- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
@ -48,6 +48,10 @@
 	u-boot,dm-spl;
 };

+&reg_usdhc2_vmmc {
+	u-boot,off-on-delay-us = <20000>;
+};
+
 &reg_usdhc2_vmmc {
 	u-boot,dm-spl;
 };
@ -122,10 +126,14 @@

 &usdhc2 {
 	u-boot,dm-spl;
+	sd-uhs-sdr104;
+	sd-uhs-ddr50;
 };

 &usdhc3 {
 	u-boot,dm-spl;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
 };

 &wdog1 {
--- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi
@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+&reg_usdhc2_vmmc {
+	u-boot,off-on-delay-us = <20000>;
+};
+
+&usdhc1 {
+	mmc-hs400-1_8v;
+};
+
+&usdhc2 {
+	sd-uhs-sdr104;
+	sd-uhs-ddr50;
+};
--- a/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi
@ -0,0 +1,5 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+&reg_usdhc2_vmmc {
+	u-boot,off-on-delay-us = <20000>;
+};
--- a/arch/arm/dts/imx8qm-rom7720-a1.dts
+++ b/arch/arm/dts/imx8qm-rom7720-a1.dts
@ -293,7 +293,7 @@
 &fec1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec1>;
-	phy-mode = "rgmii";
+	phy-mode = "rgmii-id";
 	phy-handle = <&ethphy0>;
 	fsl,ar8031-phy-fixup;
 	fsl,magic-packet;
@ -318,7 +318,7 @@
 &fec2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec2>;
-	phy-mode = "rgmii";
+	phy-mode = "rgmii-id";
 	phy-handle = <&ethphy1>;
 	fsl,ar8031-phy-fixup;
 	fsl,magic-packet;
--- a/arch/arm/dts/meson-sm1-odroid-c4-u-boot.dtsi
+++ b/arch/arm/dts/meson-sm1-odroid-c4-u-boot.dtsi
@ -11,3 +11,7 @@
 	snps,reset-delays-us = <0 10000 1000000>;
 	snps,reset-active-low;
 };
+
+&tflash_vdd {
+	gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>;
+};
--- a/arch/arm/dts/sam9x60.dtsi
+++ b/arch/arm/dts/sam9x60.dtsi
@ -153,12 +153,18 @@
 				sdhci0 {
 					pinctrl_sdhci0: sdhci0 {
 						atmel,pins =
-							<AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT	/* PA17 CK  periph A with pullup */
-							 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP		/* PA16 CMD periph A with pullup */
-							 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP		/* PA15 DAT0 periph A */
-							 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP		/* PA18 DAT1 periph A with pullup */
-							 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP		/* PA19 DAT2 periph A with pullup */
-							 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;		/* PA20 DAT3 periph A with pullup */
+							<AT91_PIOA 17 AT91_PERIPH_A
+							 (AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)	/* PA17 CK  periph A with pullup */
+							 AT91_PIOA 16 AT91_PERIPH_A
+							 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)	/* PA16 CMD periph A with pullup */
+							 AT91_PIOA 15 AT91_PERIPH_A
+							 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)	/* PA15 DAT0 periph A */
+							 AT91_PIOA 18 AT91_PERIPH_A
+							 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)	/* PA18 DAT1 periph A with pullup */
+							 AT91_PIOA 19 AT91_PERIPH_A
+							 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)	/* PA19 DAT2 periph A with pullup */
+							 AT91_PIOA 20 AT91_PERIPH_A
+							 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>;	/* PA20 DAT3 periph A with pullup */
 					};
 				};
 			};
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@ -804,7 +804,8 @@
 		};

 		spi0: spi@fff00000 {
-			compatible = "snps,dw-apb-ssi";
+			compatible = "altr,socfpga-spi", "snps,dw-apb-ssi-3.20",
+				     "snps,dw-apb-ssi";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0xfff00000 0x1000>;
@ -816,7 +817,8 @@
 		};

 		spi1: spi@fff01000 {
-			compatible = "snps,dw-apb-ssi";
+			compatible = "altr,socfpga-spi", "snps,dw-apb-ssi-3.20",
+				     "snps,dw-apb-ssi";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0xfff01000 0x1000>;
--- a/arch/arm/dts/socfpga_agilex.dtsi
+++ b/arch/arm/dts/socfpga_agilex.dtsi
@ -366,7 +366,8 @@
 		};

 		spi0: spi@ffda4000 {
-			compatible = "snps,dw-apb-ssi";
+			compatible = "intel,agilex-spi",
+				     "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0xffda4000 0x1000>;
@ -379,7 +380,8 @@
 		};

 		spi1: spi@ffda5000 {
-			compatible = "snps,dw-apb-ssi";
+			compatible = "intel,agilex-spi",
+				     "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0xffda5000 0x1000>;
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@ -604,7 +604,8 @@
 		};

 		spi0: spi@ffda4000 {
-			compatible = "snps,dw-apb-ssi";
+			compatible = "altr,socfpga-arria10-spi",
+				     "snps,dw-apb-ssi-3.22a", "snps,dw-apb-ssi";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0xffda4000 0x100>;
@ -617,7 +618,8 @@
 		};

 		spi1: spi@ffda5000 {
-			compatible = "snps,dw-apb-ssi";
+			compatible = "altr,socfpga-arria10-spi",
+				     "snps,dw-apb-ssi-3.22a", "snps,dw-apb-ssi";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0xffda5000 0x100>;
--- a/arch/arm/dts/socfpga_stratix10.dtsi
+++ b/arch/arm/dts/socfpga_stratix10.dtsi
@ -268,7 +268,8 @@
 		 };

 		spi0: spi@ffda4000 {
-			compatible = "snps,dw-apb-ssi";
+			compatible = "intel,stratix10-spi",
+				     "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0xffda4000 0x1000>;
@ -281,7 +282,8 @@
 		};

 		spi1: spi@ffda5000 {
-			compatible = "snps,dw-apb-ssi";
+			compatible = "intel,stratix10-spi",
+				     "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0xffda5000 0x1000>;
--- a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
+++ b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
@ -105,9 +105,18 @@
 	 * On DRC02, the SoM does not have SDIO WiFi. The pins
 	 * are used for on-board microSD slot instead.
 	 */
-	/delete-property/broken-cd;
-	cd-gpios = <&gpioi 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+	pinctrl-names = "default", "opendrain", "sleep";
+	pinctrl-0 = <&sdmmc3_b4_pins_a>;
+	pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
+	pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
+	cd-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>;
 	disable-wp;
+	st,neg-edge;
+	bus-width = <4>;
+	vmmc-supply = <&v3v3>;
+	vqmmc-supply = <&v3v3>;
+	mmc-ddr-3_3v;
+	status = "okay";
 };

 &spi1 {
--- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
@ -333,12 +333,25 @@
 	disable-wp;
 	st,sig-dir;
 	st,neg-edge;
-	st,use-ckin;
 	bus-width = <4>;
 	vmmc-supply = <&vdd_sd>;
 	status = "okay";
 };

+&sdmmc1_b4_pins_a {
+	/*
+	 * SD bus pull-up resistors:
+	 * - optional on SoMs with SD voltage translator
+	 * - mandatory on SoMs without SD voltage translator
+	 */
+	pins1 {
+		bias-pull-up;
+	};
+	pins2 {
+		bias-pull-up;
+	};
+};
+
 &sdmmc2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
--- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
+++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
@ -192,7 +192,8 @@
 };

 &usbotg_hs {
-	dr_mode = "peripheral";
+	pinctrl-0 = <&usbotg_hs_pins_a>;
+	pinctrl-names = "default";
 	phys = <&usbphyc_port1 0>;
 	phy-names = "usb2-phy";
 	status = "okay";
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2016-2018 NXP
+ * Copyright 2016-2018, 2020 NXP
 * Copyright 2015, Freescale Semiconductor
 */

@ -179,8 +179,8 @@
 #define SYS_FSL_OCRAM_SPACE_SIZE	0x00200000 /* 2M space */
 #define CONFIG_SYS_FSL_OCRAM_SIZE	0x00020000 /* Real size 128K */

-/* LX2160A Soc Support */
-#elif defined(CONFIG_ARCH_LX2160A)
+/* LX2160A/LX2162A Soc Support */
+#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define TZPC_BASE				0x02200000
 #define TZPCDECPROT_0_SET_BASE			(TZPC_BASE + 0x804)
 #if !defined(CONFIG_DM_I2C)
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2018, 2020 NXP
 * Copyright 2014-2015, Freescale Semiconductor
 */

@ -53,7 +53,7 @@
 #define CONFIG_SYS_FSL_WRIOP1_SIZE	0x100000000
 #define CONFIG_SYS_FSL_AIOP1_BASE	0x4b00000000
 #define CONFIG_SYS_FSL_AIOP1_SIZE	0x100000000
-#ifndef CONFIG_ARCH_LX2160A
+#if !defined(CONFIG_ARCH_LX2160A) || !defined(CONFIG_ARCH_LX2162)
 #define CONFIG_SYS_FSL_PEBUF_BASE	0x4c00000000
 #else
 #define CONFIG_SYS_FSL_PEBUF_BASE	0x1c00000000
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@ -2,7 +2,7 @@
 /*
 * LayerScape Internal Memory Map
 *
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2020 NXP
 * Copyright 2014 Freescale Semiconductor, Inc.
 */

@ -15,7 +15,7 @@
 #define CONFIG_SYS_FSL_DDR3_ADDR		0x08210000
 #define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00E00000)
 #define CONFIG_SYS_FSL_PMU_ADDR			(CONFIG_SYS_IMMR + 0x00E30000)
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define CONFIG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00e88180)
 #else
 #define CONFIG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00E60000)
@ -198,12 +198,12 @@
 #define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
 #define CONFIG_SYS_PCIE3_ADDR			(CONFIG_SYS_IMMR + 0x2600000)
 #define CONFIG_SYS_PCIE4_ADDR			(CONFIG_SYS_IMMR + 0x2700000)
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define SYS_PCIE5_ADDR				(CONFIG_SYS_IMMR + 0x2800000)
 #define SYS_PCIE6_ADDR				(CONFIG_SYS_IMMR + 0x2900000)
 #endif

-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define CONFIG_SYS_PCIE1_PHYS_ADDR		0x8000000000ULL
 #define CONFIG_SYS_PCIE2_PHYS_ADDR		0x8800000000ULL
 #define CONFIG_SYS_PCIE3_PHYS_ADDR		0x9000000000ULL
@ -267,7 +267,7 @@
 	defined(CONFIG_ARCH_LS1028A)
 #define USB_PHY_RX_EQ_VAL_3		0x0380
 #define USB_PHY_RX_EQ_VAL_4		0x0b80
-#elif defined(CONFIG_ARCH_LX2160A)
+#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define USB_PHY_RX_EQ_VAL_3		0x0080
 #define USB_PHY_RX_EQ_VAL_4		0x0880
 #endif
@ -391,7 +391,7 @@ struct ccsr_gur {
 #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT	FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
 #define FSL_CHASSIS3_SRDS1_REGSR	29
 #define FSL_CHASSIS3_SRDS2_REGSR	29
-#elif defined(CONFIG_ARCH_LX2160A)
+#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define FSL_CHASSIS3_EC1_REGSR  27
 #define FSL_CHASSIS3_EC2_REGSR  27
 #define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK	0x00000003
--- a/Show more
+++ b/Show more