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pwm: mediatek: add pwm3 support for mt7981

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This patch adds pwm channel 2 (pwm3) support for mt7981

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This commit is contained in:
Weijie Gao 2025-01-17 17:18:06 +08:00 • committed by Tom Rini
parent c7a6020286
commit 7071ba2658
5 changed files with 33 additions and 3 deletions
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8
arch/arm/dts/mt7981-emmc-rfb.dts
View file

@ -95,6 +95,14 @@
};
};
/* pin13 as pwm0, pin15 as pwm1, pin7 as pwm2 */
three_pwm_pins_1: three-pwm-pins {
mux {
function = "pwm";
groups = "pwm0_0", "pwm1_1", "pwm2";
};
};
mmc0_pins_default: mmc0default {
mux {
function = "flash";

8
arch/arm/dts/mt7981-rfb.dts
View file

@ -123,6 +123,14 @@
groups = "pwm0_1", "pwm1_0", "pwm2";
};
};
/* pin13 as pwm0, pin15 as pwm1, pin7 as pwm2 */
three_pwm_pins_1: three-pwm-pins {
mux {
function = "pwm";
groups = "pwm0_0", "pwm1_1", "pwm2";
};
};
};
&spi0 {

8
arch/arm/dts/mt7981-sd-rfb.dts
View file

@ -95,6 +95,14 @@
};
};
/* pin13 as pwm0, pin15 as pwm1, pin7 as pwm2 */
three_pwm_pins_1: three-pwm-pins {
mux {
function = "pwm";
groups = "pwm0_0", "pwm1_1", "pwm2";
};
};
mmc0_pins_default: mmc0default {
mux {
function = "flash";

10
arch/arm/dts/mt7981.dtsi
View file

@ -137,8 +137,14 @@
<&infracfg CLK_INFRA_PWM1_CK>,
<&infracfg CLK_INFRA_PWM2_CK>,
<&infracfg CLK_INFRA_PWM3_CK>;
assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>;
assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>,
<&infracfg CLK_INFRA_PWM1_SEL>,
<&infracfg CLK_INFRA_PWM2_SEL>,
<&infracfg CLK_INFRA_PWM3_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
<&topckgen CLK_TOP_PWM_SEL>,
<&topckgen CLK_TOP_PWM_SEL>,
<&topckgen CLK_TOP_PWM_SEL>;
clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
status = "disabled";
};

2
drivers/pwm/pwm-mtk.c
View file

@ -192,7 +192,7 @@ static const struct mtk_pwm_soc mt7629_data = {
};
static const struct mtk_pwm_soc mt7981_data = {
.num_pwms = 2,
.num_pwms = 3,
.pwm45_fixup = false,
.reg_ver = PWM_REG_V2,
};