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Merge branch 'master' of git://www.denx.de/git/u-boot-blackfin

Browse source 
Conflicts:

	Makefile
	doc/README.standalone

Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk 2008-02-15 00:06:18 +01:00
commit 6f99eec3dc
230 changed files with 61687 additions and 13128 deletions
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4
.gitignore vendored
View file

@ -18,9 +18,13 @@
/System.map
/u-boot
/u-boot.hex
/u-boot.map
/u-boot.bin
/u-boot.srec
/u-boot.ldr
/u-boot.ldr.hex
/u-boot.ldr.srec
#
# Generated files

47
Makefile
View file

@ -185,18 +185,6 @@ endif
ifeq ($(CPU),mpc85xx)
OBJS += cpu/$(CPU)/resetvec.o
endif
ifeq ($(CPU),bf533)
OBJS += cpu/$(CPU)/start1.o cpu/$(CPU)/interrupt.o cpu/$(CPU)/cache.o
OBJS += cpu/$(CPU)/flush.o cpu/$(CPU)/init_sdram.o
endif
ifeq ($(CPU),bf537)
OBJS += cpu/$(CPU)/start1.o cpu/$(CPU)/interrupt.o cpu/$(CPU)/cache.o
OBJS += cpu/$(CPU)/flush.o cpu/$(CPU)/init_sdram.o
endif
ifeq ($(CPU),bf561)
OBJS += cpu/$(CPU)/start1.o cpu/$(CPU)/interrupt.o cpu/$(CPU)/cache.o
OBJS += cpu/$(CPU)/flush.o cpu/$(CPU)/init_sdram.o
endif
OBJS := $(addprefix $(obj),$(OBJS))
@ -286,6 +274,9 @@ __LIBS := $(subst $(obj),,$(LIBS))
#########################################################################
ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) $(U_BOOT_ONENAND)
ifeq ($(ARCH),blackfin)
ALL += $(obj)u-boot.ldr
endif
all: $(ALL)
@ -298,6 +289,15 @@ $(obj)u-boot.srec: $(obj)u-boot
$(obj)u-boot.bin: $(obj)u-boot
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(obj)u-boot.ldr: $(obj)u-boot
$(LDR) -T $(CONFIG_BFIN_CPU) -f -c $@ $< $(LDR_FLAGS)
$(obj)u-boot.ldr.hex: $(obj)u-boot.ldr
$(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ -I binary
$(obj)u-boot.ldr.srec: $(obj)u-boot.ldr
$(OBJCOPY) ${OBJCFLAGS} -O srec $< $@ -I binary
$(obj)u-boot.img: $(obj)u-boot.bin
./tools/mkimage -A $(ARCH) -T firmware -C none \
-a $(TEXT_BASE) -e 0 \
@ -312,7 +312,7 @@ $(obj)u-boot.dis: $(obj)u-boot
$(OBJDUMP) -d $< > $@
$(obj)u-boot: depend $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT)
UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
--start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
-Map u-boot.map -o u-boot
@ -2824,20 +2824,19 @@ xupv2p_config: unconfig
@echo "#define CONFIG_XUPV2P 1" >> $(obj)include/config.h
@$(MKCONFIG) -a $(@:_config=) microblaze microblaze xupv2p xilinx
#########################################################################
## Blackfin
#########################################################################
bf533-ezkit_config: unconfig
@$(MKCONFIG) $(@:_config=) blackfin bf533 bf533-ezkit
#========================================================================
# Blackfin
#========================================================================
bf533-stamp_config: unconfig
@$(MKCONFIG) $(@:_config=) blackfin bf533 bf533-stamp
# Analog Devices boards
BFIN_BOARDS = bf533-ezkit bf533-stamp bf537-stamp bf561-ezkit
bf537-stamp_config: unconfig
@$(MKCONFIG) $(@:_config=) blackfin bf537 bf537-stamp
$(BFIN_BOARDS:%=%_config) : unconfig
@$(MKCONFIG) $(@:_config=) blackfin $(firstword $(subst -, ,$@)) $(@:_config=)
bf561-ezkit_config: unconfig
@$(MKCONFIG) $(@:_config=) blackfin bf561 bf561-ezkit
$(BFIN_BOARDS):
$(MAKE) $@_config
$(MAKE)
#========================================================================
# AVR32

5
README
View file

@ -3517,6 +3517,11 @@ For PowerPC, the following registers have specific use:
average for all boards 752 bytes for the whole U-Boot image,
624 text + 127 data).
On Blackfin, the normal C ABI (except for P5) is followed as documented here:
http://docs.blackfin.uclinux.org/doku.php?id=application_binary_interface
==> U-Boot will use P5 to hold a pointer to the global data
On ARM, the following registers are used:
R0: function argument word/integer result

10
blackfin_config.mk
View file

@ -21,4 +21,12 @@
# MA 02111-1307 USA
#
PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN -D__BLACKFIN__
PLATFORM_RELFLAGS += -ffixed-P5
PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN
SYM_PREFIX = _
LDR_FLAGS += --use-vmas
ifeq (,$(findstring s,$(MAKEFLAGS)))
LDR_FLAGS += --quiet
endif

1
board/bf533-ezkit/.gitignore vendored Normal file
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@ -0,0 +1 @@
/u-boot.lds

8
board/bf533-ezkit/flash.c
View file

@ -286,9 +286,9 @@ int write_flash(long nOffset, int nValue)
long addr;
addr = (CFG_FLASH_BASE + nOffset);
sync();
SSYNC();
*(unsigned volatile short *)addr = nValue;
sync();
SSYNC();
if (poll_toggle_bit(nOffset) < 0)
return FLASH_FAIL;
return FLASH_SUCCESS;
@ -301,9 +301,9 @@ int read_flash(long nOffset, int *pnValue)
if (nOffset != 0x2)
reset_flash();
sync();
SSYNC();
nValue = *(volatile unsigned short *)addr;
sync();
SSYNC();
*pnValue = nValue;
return TRUE;
}

1
board/bf533-stamp/.gitignore vendored Normal file
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@ -0,0 +1 @@
/u-boot.lds

32
board/bf533-stamp/bf533-stamp.c
View file

@ -76,9 +76,9 @@ void swap_to(int device_id)
if (device_id == ETHERNET) {
*pFIO_DIR = PF0;
sync();
SSYNC();
*pFIO_FLAG_S = PF0;
sync();
SSYNC();
} else if (device_id == FLASH) {
*pFIO_DIR = (PF4 | PF3 | PF2 | PF1 | PF0);
*pFIO_FLAG_S = (PF4 | PF3 | PF2);
@ -88,7 +88,7 @@ void swap_to(int device_id)
*pFIO_EDGE = (PF8 | PF7 | PF6 | PF5);
*pFIO_INEN = (PF8 | PF7 | PF6 | PF5);
*pFIO_FLAG_D = (PF4 | PF3 | PF2);
sync();
SSYNC();
} else {
printf("Unknown bank to switch\n");
}
@ -155,15 +155,15 @@ void cf_outb(unsigned char val, volatile unsigned char *addr)
*/
*pFIO_FLAG_S = CF_PF0;
*pFIO_FLAG_C = CF_PF1;
sync();
SSYNC();
*(addr) = val;
sync();
SSYNC();
/* Setback PF1 PF0 to 0 0 to address external
* memory banks */
*(volatile unsigned short *)pFIO_FLAG_C = CF_PF1_PF0;
sync();
SSYNC();
}
unsigned char cf_inb(volatile unsigned char *addr)
@ -172,13 +172,13 @@ unsigned char cf_inb(volatile unsigned char *addr)
*pFIO_FLAG_S = CF_PF0;
*pFIO_FLAG_C = CF_PF1;
sync();
SSYNC();
c = *(addr);
sync();
SSYNC();
*pFIO_FLAG_C = CF_PF1_PF0;
sync();
SSYNC();
return c;
}
@ -189,15 +189,15 @@ void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
*pFIO_FLAG_S = CF_PF0;
*pFIO_FLAG_C = CF_PF1;
sync();
SSYNC();
for (i = 0; i < words; i++) {
*(sect_buf + i) = *(addr);
sync();
SSYNC();
}
*pFIO_FLAG_C = CF_PF1_PF0;
sync();
SSYNC();
}
void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
@ -206,15 +206,15 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
*pFIO_FLAG_S = CF_PF0;
*pFIO_FLAG_C = CF_PF1;
sync();
SSYNC();
for (i = 0; i < words; i++) {
*(addr) = *(sect_buf + i);
sync();
SSYNC();
}
*pFIO_FLAG_C = CF_PF1_PF0;
sync();
SSYNC();
}
#endif
@ -235,7 +235,7 @@ void stamp_led_set(int LED1, int LED2, int LED3)
*pFIO_FLAG_S = PF4;
else
*pFIO_FLAG_C = PF4;
sync();
SSYNC();
}
void show_boot_progress(int status)

39
board/bf533-stamp/spi.c
View file

@ -4,6 +4,7 @@
#include <common.h>
#include <linux/ctype.h>
#include <asm/io.h>
#include <asm/mach-common/bits/spi.h>
#if defined(CONFIG_SPI)
@ -153,7 +154,7 @@ void SendSingleCommand(const int iCommand)
/*sends the actual command to the SPI TX register */
*pSPI_TDBR = iCommand;
sync();
SSYNC();
/*The SPI status register will be polled to check the SPIF bit */
Wait_For_SPIF();
@ -174,7 +175,7 @@ void SetupSPI(const int spi_setting)
*pSPI_FLG = 0xFB04;
*pSPI_BAUD = CONFIG_SPI_BAUD;
*pSPI_CTL = spi_setting;
sync();
SSYNC();
}
void SPI_OFF(void)
@ -183,7 +184,7 @@ void SPI_OFF(void)
*pSPI_CTL = 0x0400; /* disable SPI */
*pSPI_FLG = 0;
*pSPI_BAUD = 0;
sync();
SSYNC();
udelay(CONFIG_CCLK_HZ / 50000000);
}
@ -241,10 +242,10 @@ char ReadStatusRegister(void)
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); /* Turn on the SPI */
*pSPI_TDBR = SPI_RDSR; /* send instruction to read status register */
sync();
SSYNC();
Wait_For_SPIF(); /*wait until the instruction has been sent */
*pSPI_TDBR = 0; /*send dummy to receive the status register */
sync();
SSYNC();
Wait_For_SPIF(); /*wait until the data has been sent */
status_register = *pSPI_RDBR; /*read the status register */
@ -305,18 +306,18 @@ ERROR_CODE EraseBlock(int nBlock)
/* Send the erase block command to the flash followed by the 24 address */
/* to point to the start of a sector. */
*pSPI_TDBR = SPI_SE;
sync();
SSYNC();
Wait_For_SPIF();
ShiftValue = (ulSectorOff >> 16); /* Send the highest byte of the 24 bit address at first */
*pSPI_TDBR = ShiftValue;
sync();
SSYNC();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
ShiftValue = (ulSectorOff >> 8); /* Send the middle byte of the 24 bit address at second */
*pSPI_TDBR = ShiftValue;
sync();
SSYNC();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
*pSPI_TDBR = ulSectorOff; /* Send the lowest byte of the 24 bit address finally */
sync();
SSYNC();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
/*Turns off the SPI */
@ -351,25 +352,25 @@ ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData)
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
*pSPI_TDBR = SPI_READ; /* Send the read command to SPI device */
sync();
SSYNC();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
ShiftValue = (ulStart >> 16); /* Send the highest byte of the 24 bit address at first */
*pSPI_TDBR = ShiftValue; /* Send the byte to the SPI device */
sync();
SSYNC();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
ShiftValue = (ulStart >> 8); /* Send the middle byte of the 24 bit address at second */
*pSPI_TDBR = ShiftValue; /* Send the byte to the SPI device */
sync();
SSYNC();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
*pSPI_TDBR = ulStart; /* Send the lowest byte of the 24 bit address finally */
sync();
SSYNC();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
/* After the SPI device address has been placed on the MOSI pin the data can be */
/* received on the MISO pin. */
for (i = 0; i < lCount; i++) {
*pSPI_TDBR = 0; /*send dummy */
sync();
SSYNC();
while (!(*pSPI_STAT & RXS)) ;
*cnData++ = *pSPI_RDBR; /*read */
@ -406,26 +407,26 @@ ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount,
/* Third, the 24 bit address will be shifted out the SPI MOSI bytewise. */
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); /* Turns the SPI on */
*pSPI_TDBR = SPI_PP;
sync();
SSYNC();
Wait_For_SPIF(); /*wait until the instruction has been sent */
ulWAddr = (ulStartAddr >> 16);
*pSPI_TDBR = ulWAddr;
sync();
SSYNC();
Wait_For_SPIF(); /*wait until the instruction has been sent */
ulWAddr = (ulStartAddr >> 8);
*pSPI_TDBR = ulWAddr;
sync();
SSYNC();
Wait_For_SPIF(); /*wait until the instruction has been sent */
ulWAddr = ulStartAddr;
*pSPI_TDBR = ulWAddr;
sync();
SSYNC();
Wait_For_SPIF(); /*wait until the instruction has been sent */
/* Fourth, maximum number of 256 bytes will be taken from the Buffer */
/* and sent to the SPI device. */
for (i = 0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++) {
iData = *temp;
*pSPI_TDBR = iData;
sync();
SSYNC();
Wait_For_SPIF(); /*wait until the instruction has been sent */
temp++;
}

1
board/bf537-stamp/.gitignore vendored Normal file
View file

@ -0,0 +1 @@
/u-boot.lds

9
board/bf537-stamp/bf537-stamp.c
View file

@ -32,6 +32,7 @@
#include <asm/io.h>
#include <net.h>
#include "ether_bf537.h"
#include <asm/mach-common/bits/bootrom.h>
/**
* is_valid_ether_addr - Determine if the given Ethernet address is valid
@ -117,7 +118,7 @@ int checkboard(void)
void cf_outb(unsigned char val, volatile unsigned char *addr)
{
*(addr) = val;
sync();
SSYNC();
}
unsigned char cf_inb(volatile unsigned char *addr)
@ -125,7 +126,7 @@ unsigned char cf_inb(volatile unsigned char *addr)
volatile unsigned char c;
c = *(addr);
sync();
SSYNC();
return c;
}
@ -136,7 +137,7 @@ void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
for (i = 0; i < words; i++)
*(sect_buf + i) = *(addr);
sync();
SSYNC();
}
void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
@ -145,7 +146,7 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
for (i = 0; i < words; i++)
*(addr) = *(sect_buf + i);
sync();
SSYNC();
}
#endif /* CONFIG_BFIN_IDE */

6
board/bf537-stamp/ether_bf537.c
View file

@ -30,6 +30,10 @@
#include <malloc.h>
#include "ether_bf537.h"
#include <asm/mach-common/bits/dma.h>
#include <asm/mach-common/bits/emac.h>
#include <asm/mach-common/bits/pll.h>
#ifdef CONFIG_POST
#include <post.h>
#endif
@ -364,7 +368,7 @@ int SetupSystemRegs(int *opmode)
u16 sysctl, phydat;
int count = 0;
/* Enable PHY output */
*pVR_CTL |= PHYCLKOE;
*pVR_CTL |= CLKBUFOE;
/* MDC = 2.5 MHz */
sysctl = SET_MDCDIV(24);
/* Odd word alignment for Receive Frame DMA word */

2
board/bf537-stamp/flash.c
View file

@ -255,7 +255,7 @@ int write_flash(long nOffset, int nValue)
addr = (CFG_FLASH_BASE + nOffset);
*(unsigned volatile short *)addr = nValue;
sync();
SSYNC();
#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
if (icache_status())
udelay(CONFIG_CCLK_HZ / 1000000);

4
board/bf537-stamp/nand.c
View file

@ -64,13 +64,13 @@ static void bfin_hwcontrol(struct mtd_info *mtd, int cmd)
this->IO_ADDR_R = this->IO_ADDR_W;
/* Drain the writebuffer */
sync();
SSYNC();
}
int bfin_device_ready(struct mtd_info *mtd)
{
int ret = (*PORT(CONFIG_NAND_GPIO_PORT, IO) & BFIN_NAND_READY) ? 1 : 0;
sync();
SSYNC();
return ret;
}

18
board/bf537-stamp/post-memory.c
View file

@ -104,15 +104,15 @@ void post_init_uart(int sclk)
*pUART_GCTL = 0x00;
*pUART_LCR = 0x83;
sync();
SSYNC();
*pUART_DLL = (divisor & 0xFF);
sync();
SSYNC();
*pUART_DLH = ((divisor >> 8) & 0xFF);
sync();
SSYNC();
*pUART_LCR = 0x03;
sync();
SSYNC();
*pUART_GCTL = 0x01;
sync();
SSYNC();
}
void post_out_buff(char *buff)
@ -124,7 +124,7 @@ void post_out_buff(char *buff)
while ((buff[i] != '\0') && (i != 100)) {
while (!(*pUART_LSR & 0x20)) ;
*pUART_THR = buff[i];
sync();
SSYNC();
i++;
}
for (i = 0; i < 0x80000; i++) ;
@ -141,7 +141,7 @@ int post_key_pressed(void)
*pPORTF_FER &= ~PF5;
*pPORTFIO_DIR &= ~PF5;
*pPORTFIO_INEN |= PF5;
sync();
SSYNC();
post_out_buff("########Press SW10 to enter Memory POST########: 3\0");
for (i = 0; i < KEY_LOOP; i++) {
@ -303,7 +303,7 @@ int post_init_sdram(int sclk)
(SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR
| PSS);
sync();
SSYNC();
*pEBIU_SDGCTL |= 0x1000000;
/* Set the SDRAM Refresh Rate control register based on SSCLK value */
@ -314,7 +314,7 @@ int post_init_sdram(int sclk)
/* SDRAM Memory Global Control Register */
*pEBIU_SDGCTL = mem_SDGCTL;
sync();
SSYNC();
return mem_SDRRC;
}

43
board/bf537-stamp/stm_m25p64.c
View file

@ -4,6 +4,7 @@
#include <common.h>
#include <linux/ctype.h>
#include <asm/io.h>
#include <asm/mach-common/bits/spi.h>
#if defined(CONFIG_SPI)
@ -142,7 +143,7 @@ void SendSingleCommand(const int iCommand)
/* sends the actual command to the SPI TX register */
*pSPI_TDBR = iCommand;
sync();
SSYNC();
/* The SPI status register will be polled to check the SPIF bit */
Wait_For_SPIF();
@ -164,10 +165,10 @@ void SetupSPI(const int spi_setting)
*pSPI_FLG = 0xFF02;
*pSPI_BAUD = CONFIG_SPI_BAUD;
*pSPI_CTL = spi_setting;
sync();
SSYNC();
*pSPI_FLG = 0xFD02;
sync();
SSYNC();
}
void SPI_OFF(void)
@ -176,7 +177,7 @@ void SPI_OFF(void)
*pSPI_CTL = 0x0400; /* disable SPI */
*pSPI_FLG = 0;
*pSPI_BAUD = 0;
sync();
SSYNC();
udelay(CONFIG_CCLK_HZ / 50000000);
}
@ -234,10 +235,10 @@ char ReadStatusRegister(void)
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); /* Turn on the SPI */
*pSPI_TDBR = SPI_RDSR; /* send instruction to read status register */
sync();
SSYNC();
Wait_For_SPIF(); /*wait until the instruction has been sent */
*pSPI_TDBR = 0; /*send dummy to receive the status register */
sync();
SSYNC();
Wait_For_SPIF(); /*wait until the data has been sent */
status_register = *pSPI_RDBR; /*read the status register */
@ -300,23 +301,23 @@ ERROR_CODE EraseBlock(int nBlock)
* to point to the start of a sector
*/
*pSPI_TDBR = SPI_SE;
sync();
SSYNC();
Wait_For_SPIF();
/* Send the highest byte of the 24 bit address at first */
ShiftValue = (ulSectorOff >> 16);
*pSPI_TDBR = ShiftValue;
sync();
SSYNC();
/* Wait until the instruction has been sent */
Wait_For_SPIF();
/* Send the middle byte of the 24 bit address at second */
ShiftValue = (ulSectorOff >> 8);
*pSPI_TDBR = ShiftValue;
sync();
SSYNC();
/* Wait until the instruction has been sent */
Wait_For_SPIF();
/* Send the lowest byte of the 24 bit address finally */
*pSPI_TDBR = ulSectorOff;
sync();
SSYNC();
/* Wait until the instruction has been sent */
Wait_For_SPIF();
@ -357,33 +358,33 @@ ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData)
/* Send the read command to SPI device */
*pSPI_TDBR = SPI_READ;
#endif
sync();
SSYNC();
/* Wait until the instruction has been sent */
Wait_For_SPIF();
/* Send the highest byte of the 24 bit address at first */
ShiftValue = (ulStart >> 16);
/* Send the byte to the SPI device */
*pSPI_TDBR = ShiftValue;
sync();
SSYNC();
/* Wait until the instruction has been sent */
Wait_For_SPIF();
/* Send the middle byte of the 24 bit address at second */
ShiftValue = (ulStart >> 8);
/* Send the byte to the SPI device */
*pSPI_TDBR = ShiftValue;
sync();
SSYNC();
/* Wait until the instruction has been sent */
Wait_For_SPIF();
/* Send the lowest byte of the 24 bit address finally */
*pSPI_TDBR = ulStart;
sync();
SSYNC();
/* Wait until the instruction has been sent */
Wait_For_SPIF();
#ifdef CONFIG_SPI_FLASH_FAST_READ
/* Send dummy for FAST_READ */
*pSPI_TDBR = 0;
sync();
SSYNC();
/* Wait until the instruction has been sent */
Wait_For_SPIF();
#endif
@ -392,7 +393,7 @@ ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData)
/* received on the MISO pin. */
for (i = 0; i < lCount; i++) {
*pSPI_TDBR = 0;
sync();
SSYNC();
while (!(*pSPI_STAT & RXS)) ;
*cnData++ = *pSPI_RDBR;
@ -435,22 +436,22 @@ ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount,
*/
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
*pSPI_TDBR = SPI_PP;
sync();
SSYNC();
/*wait until the instruction has been sent */
Wait_For_SPIF();
ulWAddr = (ulStartAddr >> 16);
*pSPI_TDBR = ulWAddr;
sync();
SSYNC();
/*wait until the instruction has been sent */
Wait_For_SPIF();
ulWAddr = (ulStartAddr >> 8);
*pSPI_TDBR = ulWAddr;
sync();
SSYNC();
/*wait until the instruction has been sent */
Wait_For_SPIF();
ulWAddr = ulStartAddr;
*pSPI_TDBR = ulWAddr;
sync();
SSYNC();
/*wait until the instruction has been sent */
Wait_For_SPIF();
/*
@ -460,7 +461,7 @@ ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount,
for (i = 0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++) {
iData = *temp;
*pSPI_TDBR = iData;
sync();
SSYNC();
/*wait until the instruction has been sent */
Wait_For_SPIF();
temp++;

1
board/bf561-ezkit/.gitignore vendored Normal file
View file

@ -0,0 +1 @@
/u-boot.lds

4
board/bf561-ezkit/bf561-ezkit.c
View file

@ -65,9 +65,9 @@ int misc_init_r(void)
/* Keep PF12 low to be able to drive the USB-LAN Extender */
*pFIO0_DIR = 0x0000;
*pFIO0_FLAG_C = 0x1000; /* Clear PF12 */
sync();
SSYNC();
*pFIO0_POLAR = 0x0000;
sync();
SSYNC();
return 0;
}

2
common/Makefile
View file

@ -76,6 +76,7 @@ COBJS-y += cmd_nand.o
COBJS-$(CONFIG_CMD_NET) += cmd_net.o
COBJS-y += cmd_nvedit.o
COBJS-y += cmd_onenand.o
COBJS-$(CONFIG_CMD_OTP) += cmd_otp.o
ifdef CONFIG_PCI
COBJS-$(CONFIG_CMD_PCI) += cmd_pci.o
endif
@ -86,6 +87,7 @@ COBJS-$(CONFIG_CMD_REISER) += cmd_reiser.o
COBJS-y += cmd_sata.o
COBJS-$(CONFIG_CMD_SCSI) += cmd_scsi.o
COBJS-$(CONFIG_CMD_SPI) += cmd_spi.o
COBJS-$(CONFIG_CMD_STRINGS) += cmd_strings.o
COBJS-$(CONFIG_CMD_TERMINAL) += cmd_terminal.o
COBJS-$(CONFIG_CMD_UNIVERSE) += cmd_universe.o
COBJS-$(CONFIG_CMD_USB) += cmd_usb.o

31
common/cmd_bdinfo.c
View file

@ -273,6 +273,37 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 0;
}
#elif defined(CONFIG_BLACKFIN)
int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int i;
bd_t *bd = gd->bd;
printf("U-Boot = %s\n", bd->bi_r_version);
printf("CPU = %s\n", bd->bi_cpu);
printf("Board = %s\n", bd->bi_board_name);
printf("VCO = %lu MHz\n", bd->bi_vco / 1000000);
printf("CCLK = %lu MHz\n", bd->bi_cclk / 1000000);
printf("SCLK = %lu MHz\n", bd->bi_sclk / 1000000);
print_num("boot_params", (ulong)bd->bi_boot_params);
print_num("memstart", (ulong)bd->bi_memstart);
print_num("memsize", (ulong)bd->bi_memsize);
print_num("flashstart", (ulong)bd->bi_flashstart);
print_num("flashsize", (ulong)bd->bi_flashsize);
print_num("flashoffset", (ulong)bd->bi_flashoffset);
puts("ethaddr =");
for (i = 0; i < 6; ++i)
printf("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
puts("\nip_addr = ");
print_IPaddr(bd->bi_ip_addr);
printf("\nbaudrate = %d bps\n", bd->bi_baudrate);
return 0;
}
#else /* ! PPC, which leaves MIPS */
int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])

45
common/cmd_mem.c
View file

@ -154,9 +154,32 @@ int do_mem_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
} while (nbytes > 0);
#else
# if defined(CONFIG_BLACKFIN)
/* See if we're trying to display L1 inst */
if (addr_bfin_on_chip_mem(addr)) {
char linebuf[DISP_LINE_LEN];
ulong linebytes, nbytes = length * size;
do {
linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
memcpy(linebuf, (void *)addr, linebytes);
print_buffer(addr, linebuf, size, linebytes/size, DISP_LINE_LEN/size);
nbytes -= linebytes;
addr += linebytes;
if (ctrlc()) {
rc = 1;
break;
}
} while (nbytes > 0);
} else
# endif
{
/* Print the lines. */
print_buffer(addr, (void*)addr, size, length, DISP_LINE_LEN/size);
addr += size*length;
}
#endif
dp_last_addr = addr;
@ -308,6 +331,13 @@ int do_mem_cmp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
#endif
#ifdef CONFIG_BLACKFIN
if (addr_bfin_on_chip_mem(addr1) || addr_bfin_on_chip_mem(addr2)) {
puts ("Comparison with L1 instruction memory not supported.\n\r");
return 0;
}
#endif
ngood = 0;
while (count-- > 0) {
@ -478,6 +508,14 @@ int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
#endif
#ifdef CONFIG_BLACKFIN
/* See if we're copying to/from L1 inst */
if (addr_bfin_on_chip_mem(dest) || addr_bfin_on_chip_mem(addr)) {
memcpy((void *)dest, (void *)addr, count * size);
return 0;
}
#endif
while (count-- > 0) {
if (size == 4)
*((ulong *)dest) = *((ulong *)addr);
@ -1006,6 +1044,13 @@ mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[])
}
#endif
#ifdef CONFIG_BLACKFIN
if (addr_bfin_on_chip_mem(addr)) {
puts ("Can't modify L1 instruction in place. Use cp instead.\n\r");
return 0;
}
#endif
/* Print the address, followed by value. Then accept input for
* the next value. A non-converted value exits.
*/

163
common/cmd_otp.c Normal file
View file

@ -0,0 +1,163 @@
/*
* cmd_otp.c - interface to Blackfin on-chip One-Time-Programmable memory
*
* Copyright (c) 2007-2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
/* There are 512 128-bit "pages" (0x000 to 0x1FF).
* The pages are accessable as 64-bit "halfpages" (an upper and lower half).
* The pages are not part of the memory map. There is an OTP controller which
* handles scanning in/out of bits. While access is done through OTP MMRs,
* the bootrom provides C-callable helper functions to handle the interaction.
*/
#include <config.h>
#include <common.h>
#include <command.h>
#ifdef CONFIG_CMD_OTP
#include <asm/blackfin.h>
#include <asm/mach-common/bits/otp.h>
static const char *otp_strerror(uint32_t err)
{
switch (err) {
case 0: return "no error";
case OTP_WRITE_ERROR: return "OTP fuse write error";
case OTP_READ_ERROR: return "OTP fuse read error";
case OTP_ACC_VIO_ERROR: return "invalid OTP address";
case OTP_DATA_MULT_ERROR: return "multiple bad bits detected";
case OTP_ECC_MULT_ERROR: return "error in ECC bits";
case OTP_PREV_WR_ERROR: return "space already written";
case OTP_DATA_SB_WARN: return "single bad bit in half page";
case OTP_ECC_SB_WARN: return "single bad bit in ECC";
default: return "unknown error";
}
}
#define lowup(x) ((x) % 2 ? "upper" : "lower")
int do_otp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
bool force = false;
if (!strcmp(argv[1], "--force")) {
force = true;
argv[1] = argv[0];
argv++;
--argc;
}
uint32_t (*otp_func)(uint32_t page, uint32_t flags, uint64_t *page_content);
if (!strcmp(argv[1], "read"))
otp_func = otp_read;
else if (!strcmp(argv[1], "write"))
otp_func = otp_write;
else {
usage:
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
}
uint64_t *addr = (uint64_t *)simple_strtoul(argv[2], NULL, 16);
uint32_t page = simple_strtoul(argv[3], NULL, 16);
uint32_t flags, ret;
size_t i, count;
ulong half;
if (argc > 4)
count = simple_strtoul(argv[4], NULL, 16);
else
count = 2;
if (argc > 5) {
half = simple_strtoul(argv[5], NULL, 16);
if (half != 0 && half != 1) {
puts("Error: 'half' can only be '0' or '1'\n");
goto usage;
}
} else
half = 0;
/* do to the nature of OTP, make sure users are sure */
if (!force && otp_func == otp_write) {
printf(
"Writing one time programmable memory\n"
"Make sure your operating voltages and temperature are within spec\n"
" source address: 0x%p\n"
" OTP destination: %s page 0x%03X - %s page 0x%03X\n"
" number to write: %ld halfpages\n"
" type \"YES\" (no quotes) to confirm: ",
addr,
lowup(half), page,
lowup(half + count - 1), page + (half + count - 1) / 2,
half + count
);
i = 0;
while (1) {
if (tstc()) {
const char exp_ans[] = "YES\r";
char c;
putc(c = getc());
if (exp_ans[i++] != c) {
printf(" Aborting\n");
return 1;
} else if (!exp_ans[i]) {
puts("\n");
break;
}
}
}
/* Only supported in newer silicon ... enable writing */
#if (0)
otp_command(OTP_INIT, ...);
#else
*pOTP_TIMING = 0x32149485;
#endif
}
printf("OTP memory %s: addr 0x%08lx page 0x%03X count %ld ... ",
argv[1], addr, page, count);
ret = 0;
for (i = half; i < count + half; ++i) {
flags = (i % 2) ? OTP_UPPER_HALF : OTP_LOWER_HALF;
ret = otp_func(page, flags, addr);
if (ret & 0x1)
break;
else if (ret)
puts("W");
else
puts(".");
++addr;
if (i % 2)
++page;
}
if (ret & 0x1)
printf("\nERROR at page 0x%03X (%s-halfpage): 0x%03X: %s\n",
page, lowup(i), ret, otp_strerror(ret));
else
puts(" done\n");
if (otp_func == otp_write)
/* Only supported in newer silicon ... disable writing */
#if (0)
otp_command(OTP_INIT, ...);
#else
*pOTP_TIMING = 0x1485;
#endif
return ret;
}
U_BOOT_CMD(otp, 6, 0, do_otp,
"otp - One-Time-Programmable sub-system\n",
"read <addr> <page> [count] [half]\n"
"otp write [--force] <addr> <page> [count] [half]\n"
" - read/write 'count' half-pages starting at page 'page' (offset 'half')\n");
#endif

45
common/cmd_reginfo.c
View file

@ -329,16 +329,53 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
*(volatile ulong*)MPC5XXX_SDRAM_CS0CFG);
printf ("\tSDRAMCS1: %08X\n",
*(volatile ulong*)MPC5XXX_SDRAM_CS1CFG);
#elif defined(CONFIG_BLACKFIN)
puts("\nSystem Configuration registers\n");
puts("\nPLL Registers\n");
printf("\tPLL_DIV: 0x%04x PLL_CTL: 0x%04x\n",
bfin_read_PLL_DIV(), bfin_read_PLL_CTL());
printf("\tPLL_STAT: 0x%04x PLL_LOCKCNT: 0x%04x\n",
bfin_read_PLL_STAT(), bfin_read_PLL_LOCKCNT());
printf("\tVR_CTL: 0x%04x\n", bfin_read_VR_CTL());
puts("\nEBIU AMC Registers\n");
printf("\tEBIU_AMGCTL: 0x%04x\n", bfin_read_EBIU_AMGCTL());
printf("\tEBIU_AMBCTL0: 0x%08x EBIU_AMBCTL1: 0x%08x\n",
bfin_read_EBIU_AMBCTL0(), bfin_read_EBIU_AMBCTL1());
# ifdef EBIU_MODE
printf("\tEBIU_MBSCTL: 0x%08x EBIU_ARBSTAT: 0x%08x\n",
bfin_read_EBIU_MBSCTL(), bfin_read_EBIU_ARBSTAT());
printf("\tEBIU_MODE: 0x%08x EBIU_FCTL: 0x%08x\n",
bfin_read_EBIU_MODE(), bfin_read_EBIU_FCTL());
# endif
# ifdef EBIU_RSTCTL
puts("\nEBIU DDR Registers\n");
printf("\tEBIU_DDRCTL0: 0x%08x EBIU_DDRCTL1: 0x%08x\n",
bfin_read_EBIU_DDRCTL0(), bfin_read_EBIU_DDRCTL1());
printf("\tEBIU_DDRCTL2: 0x%08x EBIU_DDRCTL3: 0x%08x\n",
bfin_read_EBIU_DDRCTL2(), bfin_read_EBIU_DDRCTL3());
printf("\tEBIU_DDRQUE: 0x%08x EBIU_RSTCTL 0x%04x\n",
bfin_read_EBIU_DDRQUE(), bfin_read_EBIU_RSTCTL());
printf("\tEBIU_ERRADD: 0x%08x EBIU_ERRMST: 0x%04x\n",
bfin_read_EBIU_ERRADD(), bfin_read_EBIU_ERRMST());
# else
puts("\nEBIU SDC Registers\n");
printf("\tEBIU_SDRRC: 0x%04x EBIU_SDBCTL: 0x%04x\n",
bfin_read_EBIU_SDRRC(), bfin_read_EBIU_SDBCTL());
printf("\tEBIU_SDSTAT: 0x%04x EBIU_SDGCTL: 0x%08x\n",
bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL());
# endif
#endif /* CONFIG_MPC5200 */
return 0;
}
/**************************************************/
#if ( defined(CONFIG_8xx) || defined(CONFIG_405GP) || \
defined(CONFIG_405EP) || defined(CONFIG_MPC5200) ) && \
defined(CONFIG_CMD_REGINFO)
#if defined(CONFIG_CMD_REGINFO)
U_BOOT_CMD(
reginfo, 2, 1, do_reginfo,
"reginfo - print register information\n",

49
common/cmd_strings.c Normal file
View file

@ -0,0 +1,49 @@
/*
* cmd_strings.c - just like `strings` command
*
* Copyright (c) 2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#include <config.h>
#include <common.h>
#include <command.h>
#ifdef CONFIG_CFG_STRINGS
static char *start_addr, *last_addr;
int do_strings(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
if (argc == 1) {
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
}
if ((flag & CMD_FLAG_REPEAT) == 0) {
start_addr = (char *)simple_strtoul(argv[1], NULL, 16);
if (argc > 2)
last_addr = (char *)simple_strtoul(argv[2], NULL, 16);
else
last_addr = (char *)-1;
}
char *addr = start_addr;
do {
printf("%s\n", addr);
addr += strlen(addr) + 1;
} while (addr[0] && addr < last_addr);
last_addr = addr + (last_addr - start_addr);
start_addr = addr;
return 0;
}
U_BOOT_CMD(strings, 3, 1, do_strings,
"strings - display strings\n",
"<addr> [byte count]\n"
" - display strings at <addr> for at least [byte count] or first double NUL\n");
#endif

7
common/environment.c
View file

@ -70,11 +70,16 @@
/*
* Macros to generate global absolutes.
*/
#if defined(__bfin__)
# define GEN_SET_VALUE(name, value) asm (".set " GEN_SYMNAME(name) ", " GEN_VALUE(value))
#else
# define GEN_SET_VALUE(name, value) asm (GEN_SYMNAME(name) " = " GEN_VALUE(value))
#endif
#define GEN_SYMNAME(str) SYM_CHAR #str
#define GEN_VALUE(str) #str
#define GEN_ABS(name, value) \
asm (".globl " GEN_SYMNAME(name)); \
asm (GEN_SYMNAME(name) " = " GEN_VALUE(value))
GEN_SET_VALUE(name, value)
/*
* Macros to transform values

1
config.mk
View file

@ -121,6 +121,7 @@ CC = $(CROSS_COMPILE)gcc
CPP = $(CC) -E
AR = $(CROSS_COMPILE)ar
NM = $(CROSS_COMPILE)nm
LDR = $(CROSS_COMPILE)ldr
STRIP = $(CROSS_COMPILE)strip
OBJCOPY = $(CROSS_COMPILE)objcopy
OBJDUMP = $(CROSS_COMPILE)objdump

4
cpu/bf533/Makefile
View file

@ -28,12 +28,12 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
START = start.o start1.o interrupt.o cache.o flush.o init_sdram.o
SOBJS = start.o start1.o interrupt.o cache.o flush.o init_sdram.o
COBJS = cpu.o traps.o ints.o serial.o interrupts.o video.o
EXTRA = init_sdram_bootrom_initblock.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
START := $(addprefix $(obj),$(START))

4
cpu/bf533/bf533_serial.h
View file

@ -49,8 +49,8 @@
#include <asm/blackfin.h>
#define SYNC_ALL __asm__ __volatile__ ("ssync;\n")
#define ACCESS_LATCH *pUART_LCR |= UART_LCR_DLAB;
#define ACCESS_PORT_IER *pUART_LCR &= (~UART_LCR_DLAB);
#define ACCESS_LATCH *pUART_LCR |= DLAB;
#define ACCESS_PORT_IER *pUART_LCR &= (~DLAB);
void serial_setbrg(void);
static void local_put_char(char ch);

3
cpu/bf533/cache.S
View file

@ -2,6 +2,7 @@
#include <asm/linkage.h>
#include <config.h>
#include <asm/blackfin.h>
#include <asm/mach-common/bits/mpu.h>
.text
.align 2
@ -11,7 +12,7 @@ ENTRY(_blackfin_icache_flush_range)
P0 = R2;
P1 = R1;
CSYNC;
1:
1:
IFLUSH[P0++];
CC = P0 < P1(iu);
IF CC JUMP 1b(bp);

2
cpu/bf533/config.mk
View file

@ -24,4 +24,4 @@
# MA 02110-1301 USA
#
PLATFORM_RELFLAGS += -mcpu=bf533 -ffixed-P5
PLATFORM_RELFLAGS += -mcpu=bf533

26
cpu/bf533/cpu.c
View file

@ -40,7 +40,7 @@ extern unsigned int dcplb_table[page_descriptor_table_size][2];
int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
__asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM)
__asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_INST_SRAM)
);
return 0;
@ -100,22 +100,18 @@ void icache_enable(void)
}
cli();
sync();
SSYNC();
asm(" .align 8; ");
*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
sync();
sti();
SSYNC();
}
void icache_disable(void)
{
cli();
sync();
SSYNC();
asm(" .align 8; ");
*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
sync();
sti();
SSYNC();
}
int icache_status(void)
@ -175,14 +171,12 @@ void dcache_enable(void)
}
}
cli();
temp = *(unsigned int *)DMEM_CONTROL;
sync();
SSYNC();
asm(" .align 8; ");
*(unsigned int *)DMEM_CONTROL =
ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp;
sync();
sti();
SSYNC();
}
void dcache_disable(void)
@ -190,13 +184,11 @@ void dcache_disable(void)
unsigned int *I0, *I1;
int i;
cli();
sync();
SSYNC();
asm(" .align 8; ");
*(unsigned int *)DMEM_CONTROL &=
~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
sync();
sti();
SSYNC();
/* after disable dcache,
* clear it so we don't confuse the next application

4
cpu/bf533/init_sdram.S
View file

@ -4,6 +4,10 @@
#include <config.h>
#include <asm/blackfin.h>
#include <asm/mem_init.h>
#include <asm/mach-common/bits/bootrom.h>
#include <asm/mach-common/bits/ebiu.h>
#include <asm/mach-common/bits/pll.h>
#include <asm/mach-common/bits/uart.h>
.global init_sdram;
#if (CONFIG_CCLK_DIV == 1)

4
cpu/bf533/init_sdram_bootrom_initblock.S
View file

@ -4,6 +4,10 @@
#include <config.h>
#include <asm/blackfin.h>
#include <asm/mem_init.h>
#include <asm/mach-common/bits/bootrom.h>
#include <asm/mach-common/bits/ebiu.h>
#include <asm/mach-common/bits/pll.h>
#include <asm/mach-common/bits/uart.h>
.global init_sdram;
#if (CONFIG_CCLK_DIV == 1)

12
cpu/bf533/interrupt.S
View file

@ -42,9 +42,7 @@
#define ASSEMBLY
#include <config.h>
#include <asm/blackfin.h>
#include <asm/hw_irq.h>
#include <asm/entry.h>
#include <asm/blackfin_defs.h>
.global _blackfin_irq_panic;
@ -55,7 +53,7 @@
.global _evt_emulation
_evt_emulation:
SAVE_CONTEXT
r0 = IRQ_EMU;
r0 = 0;
r1 = seqstat;
sp += -12;
call _blackfin_irq_panic;
@ -66,7 +64,7 @@ _evt_emulation:
.global _evt_nmi
_evt_nmi:
SAVE_CONTEXT
r0 = IRQ_NMI;
r0 = 2;
r1 = RETN;
sp += -12;
call _blackfin_irq_panic;
@ -88,7 +86,7 @@ _trap:
.global _evt_rst
_evt_rst:
SAVE_CONTEXT
r0 = IRQ_RST;
r0 = 1;
r1 = RETN;
sp += -12;
call _do_reset;
@ -98,7 +96,7 @@ _evt_rst_exit:
rtn;
irq_panic:
r0 = IRQ_EVX;
r0 = 3;
r1 = sp;
sp += -12;
call _blackfin_irq_panic;
@ -115,7 +113,7 @@ _evt_ivhw_exit:
.global _evt_timer
_evt_timer:
SAVE_CONTEXT
r0 = IRQ_CORETMR;
r0 = 6;
sp += -12;
/* Polling method used now. */
/* call timer_int; */

4
cpu/bf533/interrupts.c
View file

@ -35,8 +35,6 @@
*/
#include <common.h>
#include <asm/machdep.h>
#include <asm/irq.h>
#include <config.h>
#include <asm/blackfin.h>
#include "cpu.h"
@ -72,12 +70,10 @@ ulong get_tbclk(void)
void enable_interrupts(void)
{
restore_flags(int_flag);
}
int disable_interrupts(void)
{
save_and_cli(int_flag);
return 1;
}

37
cpu/bf533/ints.c
View file

@ -39,12 +39,9 @@
#include <common.h>
#include <linux/stddef.h>
#include <asm/system.h>
#include <asm/irq.h>
#include <asm/traps.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/machdep.h>
#include <asm/setup.h>
#include <asm/blackfin.h>
#include "cpu.h"
@ -61,42 +58,40 @@ void blackfin_irq_panic(int reason, struct pt_regs *regs)
void blackfin_init_IRQ(void)
{
*(unsigned volatile long *)(SIC_IMASK) = SIC_UNMASK_ALL;
cli();
*(unsigned volatile long *)(SIC_IMASK) = 0;
#ifndef CONFIG_KGDB
*(unsigned volatile long *)(EVT_EMULATION_ADDR) = 0x0;
*(unsigned volatile long *)(EVT1) = 0x0;
#endif
*(unsigned volatile long *)(EVT_NMI_ADDR) =
*(unsigned volatile long *)(EVT2) =
(unsigned volatile long)evt_nmi;
*(unsigned volatile long *)(EVT_EXCEPTION_ADDR) =
*(unsigned volatile long *)(EVT3) =
(unsigned volatile long)trap;
*(unsigned volatile long *)(EVT_HARDWARE_ERROR_ADDR) =
*(unsigned volatile long *)(EVT5) =
(unsigned volatile long)evt_ivhw;
*(unsigned volatile long *)(EVT_RESET_ADDR) =
*(unsigned volatile long *)(EVT0) =
(unsigned volatile long)evt_rst;
*(unsigned volatile long *)(EVT_TIMER_ADDR) =
*(unsigned volatile long *)(EVT6) =
(unsigned volatile long)evt_timer;
*(unsigned volatile long *)(EVT_IVG7_ADDR) =
*(unsigned volatile long *)(EVT7) =
(unsigned volatile long)evt_evt7;
*(unsigned volatile long *)(EVT_IVG8_ADDR) =
*(unsigned volatile long *)(EVT8) =
(unsigned volatile long)evt_evt8;
*(unsigned volatile long *)(EVT_IVG9_ADDR) =
*(unsigned volatile long *)(EVT9) =
(unsigned volatile long)evt_evt9;
*(unsigned volatile long *)(EVT_IVG10_ADDR) =
*(unsigned volatile long *)(EVT10) =
(unsigned volatile long)evt_evt10;
*(unsigned volatile long *)(EVT_IVG11_ADDR) =
*(unsigned volatile long *)(EVT11) =
(unsigned volatile long)evt_evt11;
*(unsigned volatile long *)(EVT_IVG12_ADDR) =
*(unsigned volatile long *)(EVT12) =
(unsigned volatile long)evt_evt12;
*(unsigned volatile long *)(EVT_IVG13_ADDR) =
*(unsigned volatile long *)(EVT13) =
(unsigned volatile long)evt_evt13;
*(unsigned volatile long *)(EVT_IVG14_ADDR) =
*(unsigned volatile long *)(EVT14) =
(unsigned volatile long)evt_system_call;
*(unsigned volatile long *)(EVT_IVG15_ADDR) =
*(unsigned volatile long *)(EVT15) =
(unsigned volatile long)evt_soft_int1;
*(volatile unsigned long *)ILAT = 0;
asm("csync;");
sti();
*(volatile unsigned long *)IMASK = 0xffbf;
asm("csync;");
}

47
cpu/bf533/serial.c
View file

@ -43,14 +43,12 @@
*/
#include <common.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/segment.h>
#include <asm/bitops.h>
#include <asm/delay.h>
#include <asm/uaccess.h>
#include <asm/io.h>
#include "bf533_serial.h"
#include <asm/mach-common/bits/uart.h>
DECLARE_GLOBAL_DATA_PTR;
@ -85,30 +83,30 @@ void serial_setbrg(void)
}
/* Enable UART */
*pUART_GCTL |= UART_GCTL_UCEN;
sync();
*pUART_GCTL |= UCEN;
SSYNC();
/* Set DLAB in LCR to Access DLL and DLH */
ACCESS_LATCH;
sync();
SSYNC();
*pUART_DLL = hw_baud_table[i].dl_low;
sync();
SSYNC();
*pUART_DLH = hw_baud_table[i].dl_high;
sync();
SSYNC();
/* Clear DLAB in LCR to Access THR RBR IER */
ACCESS_PORT_IER;
sync();
SSYNC();
/* Enable ERBFI and ELSI interrupts
* to poll SIC_ISR register*/
*pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI;
sync();
*pUART_IER = ELSI | ERBFI | ETBEI;
SSYNC();
/* Set LCR to Word Lengh 8-bit word select */
*pUART_LCR = UART_LCR_WLS8;
sync();
*pUART_LCR = WLS_8;
SSYNC();
return;
}
@ -121,14 +119,14 @@ int serial_init(void)
void serial_putc(const char c)
{
if ((*pUART_LSR) & UART_LSR_TEMT) {
if ((*pUART_LSR) & TEMT) {
if (c == '\n')
serial_putc('\r');
local_put_char(c);
}
while (!((*pUART_LSR) & UART_LSR_TEMT))
while (!((*pUART_LSR) & TEMT))
SYNC_ALL;
return;
@ -136,7 +134,7 @@ void serial_putc(const char c)
int serial_tstc(void)
{
if (*pUART_LSR & UART_LSR_DR)
if (*pUART_LSR & DR)
return 1;
else
return 0;
@ -149,14 +147,14 @@ int serial_getc(void)
int ret;
/* Poll for RX Interrupt */
while (!((isr_val =
*(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT)) ;
while (!serial_tstc())
continue;
asm("csync;");
uart_lsr_val = *pUART_LSR; /* Clear status bit */
uart_rbr_val = *pUART_RBR; /* getc() */
if (isr_val & IRQ_UART_ERROR_BIT) {
if (uart_lsr_val & (OE|PE|FE|BI)) {
ret = -1;
} else {
ret = uart_rbr_val & 0xff;
@ -177,19 +175,12 @@ static void local_put_char(char ch)
int flags = 0;
unsigned long isr_val;
save_and_cli(flags);
/* Poll for TX Interruput */
while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)) ;
while (!(*pUART_LSR & THRE))
continue;
asm("csync;");
*pUART_THR = ch; /* putc() */
if (isr_val & IRQ_UART_ERROR_BIT) {
printf("?");
}
restore_flags(flags);
return;
}

27
cpu/bf533/start.S
View file

@ -41,19 +41,16 @@
#include <config.h>
#include <asm/blackfin.h>
#include <asm/mach-common/bits/core.h>
#include <asm/mach-common/bits/dma.h>
#include <asm/mach-common/bits/pll.h>
.global _stext;
.global __bss_start;
.global start;
.global _start;
.global _rambase;
.global _ramstart;
.global _ramend;
.global _bf533_data_dest;
.global _bf533_data_size;
.global edata;
.global _initialize;
.global _exit;
.global flashdataend;
.global init_sdram;
#if (CONFIG_CCLK_DIV == 1)
@ -143,8 +140,8 @@ no_soft_reset:
nop;
/* Clear EVT registers */
p0.h = (EVT_EMULATION_ADDR >> 16);
p0.l = (EVT_EMULATION_ADDR & 0xFFFF);
p0.h = (EVT0 >> 16);
p0.l = (EVT0 & 0xFFFF);
p0 += 8;
p1 = 14;
r1 = 0;
@ -200,8 +197,8 @@ loop1:
*/
/* To keep ourselves in the supervisor mode */
p0.l = (EVT_IVG15_ADDR & 0xFFFF);
p0.h = (EVT_IVG15_ADDR >> 16);
p0.l = (EVT15 & 0xFFFF);
p0.h = (EVT15 >> 16);
p1.l = _real_start;
p1.h = _real_start;
@ -209,8 +206,8 @@ loop1:
p0.l = (IMASK & 0xFFFF);
p0.h = (IMASK >> 16);
r0.l = LO(IVG15_POS);
r0.h = HI(IVG15_POS);
r0.l = LO(EVT_IVG15);
r0.h = HI(EVT_IVG15);
[p0] = r0;
raise 15;
p0.l = WAIT_HERE;
@ -236,8 +233,8 @@ copy:
R1.H = reset_end;
R1.L = reset_end;
R2 = R1 - R0; /* Count */
R1.H = hi(L1_ISRAM); /* Destination Address (high) */
R1.L = lo(L1_ISRAM); /* Destination Address (low) */
R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */
R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */
R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
/* Destination DMAConfig Value (8-bit words) */
R4.L = (DI_EN | WNR | DMAEN);

25
cpu/bf533/traps.c
View file

@ -36,14 +36,13 @@
#include <common.h>
#include <linux/types.h>
#include <asm/errno.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/traps.h>
#include <asm/machdep.h>
#include "cpu.h"
#include <asm/arch/anomaly.h>
#include <asm/cplb.h>
#include <asm/io.h>
#include <asm/mach-common/bits/core.h>
#include <asm/mach-common/bits/mpu.h>
void init_IRQ(void)
{
@ -68,7 +67,7 @@ static unsigned int cplb_sizes[4] =
void trap_c(struct pt_regs *regs)
{
unsigned int addr;
unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE;
unsigned long trapnr = (regs->seqstat) & EXCAUSE;
unsigned int i, j, size, *I0, *I1;
unsigned short data = 0;
@ -76,7 +75,7 @@ void trap_c(struct pt_regs *regs)
/* 0x26 - Data CPLB Miss */
case VEC_CPLB_M:
#ifdef ANOMALY_05000261
#if ANOMALY_05000261
/*
* Work around an anomaly: if we see a new DCPLB fault,
* return without doing anything. Then,
@ -118,16 +117,16 @@ void trap_c(struct pt_regs *regs)
/* Turn the cache off */
if (data) {
sync();
SSYNC();
asm(" .align 8; ");
*(unsigned int *)DMEM_CONTROL &=
~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
sync();
SSYNC();
} else {
sync();
SSYNC();
asm(" .align 8; ");
*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
sync();
SSYNC();
}
if (data) {
@ -173,16 +172,16 @@ void trap_c(struct pt_regs *regs)
/* Turn the cache back on */
if (data) {
j = *(unsigned int *)DMEM_CONTROL;
sync();
SSYNC();
asm(" .align 8; ");
*(unsigned int *)DMEM_CONTROL =
ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j;
sync();
SSYNC();
} else {
sync();
SSYNC();
asm(" .align 8; ");
*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
sync();
SSYNC();
}
break;

4
cpu/bf537/Makefile
View file

@ -28,12 +28,12 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
START = start.o start1.o interrupt.o cache.o flush.o init_sdram.o
SOBJS = start.o start1.o interrupt.o cache.o flush.o init_sdram.o
COBJS = cpu.o traps.o ints.o serial.o interrupts.o video.o i2c.o
EXTRA = init_sdram_bootrom_initblock.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
START := $(addprefix $(obj),$(START))

1
cpu/bf537/cache.S
View file

@ -2,6 +2,7 @@
#include <asm/linkage.h>
#include <config.h>
#include <asm/blackfin.h>
#include <asm/mach-common/bits/mpu.h>
.text
.align 2

2
cpu/bf537/config.mk
View file

@ -24,4 +24,4 @@
# MA 02110-1301 USA
#
PLATFORM_RELFLAGS += -mcpu=bf537 -ffixed-P5
PLATFORM_RELFLAGS += -mcpu=bf537

26
cpu/bf537/cpu.c
View file

@ -40,7 +40,7 @@ extern unsigned int dcplb_table[page_descriptor_table_size][2];
int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
__asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM)
__asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_INST_SRAM)
);
return 0;
@ -103,24 +103,20 @@ void icache_enable(void)
}
cli();
sync();
SSYNC();
asm(" .align 8; ");
*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
sync();
sti();
SSYNC();
}
void icache_disable(void)
{
if ((*pCHIPID >> 28) < 2)
return;
cli();
sync();
SSYNC();
asm(" .align 8; ");
*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
sync();
sti();
SSYNC();
}
int icache_status(void)
@ -180,14 +176,12 @@ void dcache_enable(void)
}
}
cli();
temp = *(unsigned int *)DMEM_CONTROL;
sync();
SSYNC();
asm(" .align 8; ");
*(unsigned int *)DMEM_CONTROL =
ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp;
sync();
sti();
SSYNC();
}
void dcache_disable(void)
@ -195,13 +189,11 @@ void dcache_disable(void)
unsigned int *I0, *I1;
int i;
cli();
sync();
SSYNC();
asm(" .align 8; ");
*(unsigned int *)DMEM_CONTROL &=
~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
sync();
sti();
SSYNC();
/* after disable dcache,
* clear it so we don't confuse the next application

45
cpu/bf537/i2c.c
View file

@ -21,53 +21,10 @@
#include <asm/blackfin.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/mach-common/bits/twi.h>
DECLARE_GLOBAL_DATA_PTR;
#define bfin_read16(addr) ({ unsigned __v; \
__asm__ __volatile__ (\
"%0 = w[%1] (z);\n\t"\
: "=d"(__v) : "a"(addr)); (unsigned short)__v; })
#define bfin_write16(addr,val) ({\
__asm__ __volatile__ (\
"w[%0] = %1;\n\t"\
: : "a"(addr) , "d"(val) : "memory");})
/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV)
#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV,val)
#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL)
#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL,val)
#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL)
#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL,val)
#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT)
#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT,val)
#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR)
#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR,val)
#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL)
#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL,val)
#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT)
#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT,val)
#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR)
#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR,val)
#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT)
#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT,val)
#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK)
#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK,val)
#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL)
#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL,val)
#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT)
#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT,val)
#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8)
#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8,val)
#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16)
#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16,val)
#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8)
#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8,val)
#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16)
#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16,val)
#ifdef DEBUG_I2C
#define PRINTD(fmt,args...) do { \
if (gd->have_console) \

4
cpu/bf537/init_sdram.S
View file

@ -4,6 +4,10 @@
#include <config.h>
#include <asm/blackfin.h>
#include <asm/mem_init.h>
#include <asm/mach-common/bits/bootrom.h>
#include <asm/mach-common/bits/ebiu.h>
#include <asm/mach-common/bits/pll.h>
#include <asm/mach-common/bits/uart.h>
.global init_sdram;
#if (BFIN_BOOT_MODE != BF537_UART_BOOT)

4
cpu/bf537/init_sdram_bootrom_initblock.S
View file

@ -4,6 +4,10 @@
#include <config.h>
#include <asm/blackfin.h>
#include <asm/mem_init.h>
#include <asm/mach-common/bits/bootrom.h>
#include <asm/mach-common/bits/ebiu.h>
#include <asm/mach-common/bits/pll.h>
#include <asm/mach-common/bits/uart.h>
.global init_sdram;
#if (BFIN_BOOT_MODE != BF537_UART_BOOT)

12
cpu/bf537/interrupt.S
View file

@ -42,9 +42,7 @@
#define ASSEMBLY
#include <config.h>
#include <asm/blackfin.h>
#include <asm/hw_irq.h>
#include <asm/entry.h>
#include <asm/blackfin_defs.h>
.global _blackfin_irq_panic;
@ -55,7 +53,7 @@
.global _evt_emulation
_evt_emulation:
SAVE_CONTEXT
r0 = IRQ_EMU;
r0 = 0;
r1 = seqstat;
sp += -12;
call _blackfin_irq_panic;
@ -66,7 +64,7 @@ _evt_emulation:
.global _evt_nmi
_evt_nmi:
SAVE_CONTEXT
r0 = IRQ_NMI;
r0 = 2;
r1 = RETN;
sp += -12;
call _blackfin_irq_panic;
@ -88,7 +86,7 @@ _trap:
.global _evt_rst
_evt_rst:
SAVE_CONTEXT
r0 = IRQ_RST;
r0 = 1;
r1 = RETN;
sp += -12;
call _do_reset;
@ -98,7 +96,7 @@ _evt_rst_exit:
rtn;
irq_panic:
r0 = IRQ_EVX;
r0 = 3;
r1 = sp;
sp += -12;
call _blackfin_irq_panic;
@ -115,7 +113,7 @@ _evt_ivhw_exit:
.global _evt_timer
_evt_timer:
SAVE_CONTEXT
r0 = IRQ_CORETMR;
r0 = 6;
sp += -12;
/* Polling method used now. */
/* call timer_int; */

4
cpu/bf537/interrupts.c
View file

@ -35,8 +35,6 @@
*/
#include <common.h>
#include <asm/machdep.h>
#include <asm/irq.h>
#include <config.h>
#include <asm/blackfin.h>
#include "cpu.h"
@ -72,12 +70,10 @@ ulong get_tbclk (void)
void enable_interrupts(void)
{
restore_flags(int_flag);
}
int disable_interrupts(void)
{
save_and_cli(int_flag);
return 1;
}

37
cpu/bf537/ints.c
View file

@ -39,12 +39,9 @@
#include <common.h>
#include <linux/stddef.h>
#include <asm/system.h>
#include <asm/irq.h>
#include <asm/traps.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/machdep.h>
#include <asm/setup.h>
#include <asm/blackfin.h>
#include "cpu.h"
@ -61,42 +58,40 @@ void blackfin_irq_panic(int reason, struct pt_regs *regs)
void blackfin_init_IRQ(void)
{
*(unsigned volatile long *)(SIC_IMASK) = SIC_UNMASK_ALL;
cli();
*(unsigned volatile long *)(SIC_IMASK) = 0;
#ifndef CONFIG_KGDB
*(unsigned volatile long *)(EVT_EMULATION_ADDR) = 0x0;
*(unsigned volatile long *)(EVT1) = 0x0;
#endif
*(unsigned volatile long *)(EVT_NMI_ADDR) =
*(unsigned volatile long *)(EVT2) =
(unsigned volatile long)evt_nmi;
*(unsigned volatile long *)(EVT_EXCEPTION_ADDR) =
*(unsigned volatile long *)(EVT3) =
(unsigned volatile long)trap;
*(unsigned volatile long *)(EVT_HARDWARE_ERROR_ADDR) =
*(unsigned volatile long *)(EVT5) =
(unsigned volatile long)evt_ivhw;
*(unsigned volatile long *)(EVT_RESET_ADDR) =
*(unsigned volatile long *)(EVT0) =
(unsigned volatile long)evt_rst;
*(unsigned volatile long *)(EVT_TIMER_ADDR) =
*(unsigned volatile long *)(EVT6) =
(unsigned volatile long)evt_timer;
*(unsigned volatile long *)(EVT_IVG7_ADDR) =
*(unsigned volatile long *)(EVT7) =
(unsigned volatile long)evt_evt7;
*(unsigned volatile long *)(EVT_IVG8_ADDR) =
*(unsigned volatile long *)(EVT8) =
(unsigned volatile long)evt_evt8;
*(unsigned volatile long *)(EVT_IVG9_ADDR) =
*(unsigned volatile long *)(EVT9) =
(unsigned volatile long)evt_evt9;
*(unsigned volatile long *)(EVT_IVG10_ADDR) =
*(unsigned volatile long *)(EVT10) =
(unsigned volatile long)evt_evt10;
*(unsigned volatile long *)(EVT_IVG11_ADDR) =
*(unsigned volatile long *)(EVT11) =
(unsigned volatile long)evt_evt11;
*(unsigned volatile long *)(EVT_IVG12_ADDR) =
*(unsigned volatile long *)(EVT12) =
(unsigned volatile long)evt_evt12;
*(unsigned volatile long *)(EVT_IVG13_ADDR) =
*(unsigned volatile long *)(EVT13) =
(unsigned volatile long)evt_evt13;
*(unsigned volatile long *)(EVT_IVG14_ADDR) =
*(unsigned volatile long *)(EVT14) =
(unsigned volatile long)evt_system_call;
*(unsigned volatile long *)(EVT_IVG15_ADDR) =
*(unsigned volatile long *)(EVT15) =
(unsigned volatile long)evt_soft_int1;
*(volatile unsigned long *)ILAT = 0;
asm("csync;");
sti();
*(volatile unsigned long *)IMASK = 0xffbf;
asm("csync;");
}

57
cpu/bf537/serial.c
View file

@ -43,14 +43,12 @@
*/
#include <common.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/segment.h>
#include <asm/bitops.h>
#include <asm/delay.h>
#include <asm/uaccess.h>
#include <asm/io.h>
#include "serial.h"
#include <asm/mach-common/bits/uart.h>
DECLARE_GLOBAL_DATA_PTR;
@ -85,30 +83,30 @@ void serial_setbrg(void)
}
/* Enable UART */
*pUART_GCTL |= UART_GCTL_UCEN;
sync();
*pUART0_GCTL |= UCEN;
SSYNC();
/* Set DLAB in LCR to Access DLL and DLH */
ACCESS_LATCH;
sync();
SSYNC();
*pUART_DLL = hw_baud_table[i].dl_low;
sync();
*pUART_DLH = hw_baud_table[i].dl_high;
sync();
*pUART0_DLL = hw_baud_table[i].dl_low;
SSYNC();
*pUART0_DLH = hw_baud_table[i].dl_high;
SSYNC();
/* Clear DLAB in LCR to Access THR RBR IER */
ACCESS_PORT_IER;
sync();
SSYNC();
/* Enable ERBFI and ELSI interrupts
* to poll SIC_ISR register*/
*pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI;
sync();
*pUART0_IER = ELSI | ERBFI | ETBEI;
SSYNC();
/* Set LCR to Word Lengh 8-bit word select */
*pUART_LCR = UART_LCR_WLS8;
sync();
*pUART0_LCR = WLS_8;
SSYNC();
return;
}
@ -121,14 +119,14 @@ int serial_init(void)
void serial_putc(const char c)
{
if ((*pUART_LSR) & UART_LSR_TEMT) {
if ((*pUART0_LSR) & TEMT) {
if (c == '\n')
serial_putc('\r');
local_put_char(c);
}
while (!((*pUART_LSR) & UART_LSR_TEMT))
while (!((*pUART0_LSR) & TEMT))
SYNC_ALL;
return;
@ -136,7 +134,7 @@ void serial_putc(const char c)
int serial_tstc(void)
{
if (*pUART_LSR & UART_LSR_DR)
if (*pUART0_LSR & DR)
return 1;
else
return 0;
@ -149,14 +147,14 @@ int serial_getc(void)
int ret;
/* Poll for RX Interrupt */
while (!((isr_val =
*(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT)) ;
while (!serial_tstc())
continue;
asm("csync;");
uart_lsr_val = *pUART_LSR; /* Clear status bit */
uart_rbr_val = *pUART_RBR; /* getc() */
uart_lsr_val = *pUART0_LSR; /* Clear status bit */
uart_rbr_val = *pUART0_RBR; /* getc() */
if (isr_val & IRQ_UART_ERROR_BIT) {
if (uart_lsr_val & (OE|PE|FE|BI)) {
ret = -1;
} else {
ret = uart_rbr_val & 0xff;
@ -177,19 +175,12 @@ static void local_put_char(char ch)
int flags = 0;
unsigned long isr_val;
save_and_cli(flags);
/* Poll for TX Interruput */
while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)) ;
while (!(*pUART0_LSR & THRE))
continue;
asm("csync;");
*pUART_THR = ch; /* putc() */
if (isr_val & IRQ_UART_ERROR_BIT) {
printf("?");
}
restore_flags(flags);
*pUART0_THR = ch; /* putc() */
return;
}

4
cpu/bf537/serial.h
View file

@ -49,8 +49,8 @@
#include <asm/blackfin.h>
#define SYNC_ALL __asm__ __volatile__ ("ssync;\n")
#define ACCESS_LATCH *pUART_LCR |= UART_LCR_DLAB;
#define ACCESS_PORT_IER *pUART_LCR &= (~UART_LCR_DLAB);
#define ACCESS_LATCH *pUART0_LCR |= DLAB;
#define ACCESS_PORT_IER *pUART0_LCR &= (~DLAB);
void serial_setbrg(void);
static void local_put_char(char ch);

31
cpu/bf537/start.S
View file

@ -41,19 +41,16 @@
#include <config.h>
#include <asm/blackfin.h>
#include <asm/mach-common/bits/core.h>
#include <asm/mach-common/bits/dma.h>
#include <asm/mach-common/bits/pll.h>
.global _stext;
.global __bss_start;
.global start;
.global _start;
.global _rambase;
.global _ramstart;
.global _ramend;
.global _bf533_data_dest;
.global _bf533_data_size;
.global edata;
.global _initialize;
.global _exit;
.global flashdataend;
.global init_sdram;
.global _icache_enable;
.global _dcache_enable;
@ -151,8 +148,8 @@ no_soft_reset:
nop;
/* Clear EVT registers */
p0.h = (EVT_EMULATION_ADDR >> 16);
p0.l = (EVT_EMULATION_ADDR & 0xFFFF);
p0.h = (EVT0 >> 16);
p0.l = (EVT0 & 0xFFFF);
p0 += 8;
p1 = 14;
r1 = 0;
@ -291,8 +288,8 @@ postcopy:
R1.H = (CFG_FLASH_BASE >> 16);
R1.L = (CFG_FLASH_BASE & 0xFFFF);
R0 = R0 + R1; /* Source Address */
R1.H = hi(L1_ISRAM); /* Destination Address (high) */
R1.L = lo(L1_ISRAM); /* Destination Address (low) */
R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */
R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */
R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
/* Destination DMAConfig Value (8-bit words) */
R4.L = (DI_EN | WNR | DMAEN);
@ -415,8 +412,8 @@ loop1:
*/
/* To keep ourselves in the supervisor mode */
p0.l = (EVT_IVG15_ADDR & 0xFFFF);
p0.h = (EVT_IVG15_ADDR >> 16);
p0.l = (EVT15 & 0xFFFF);
p0.h = (EVT15 >> 16);
p1.l = _real_start;
p1.h = _real_start;
@ -424,8 +421,8 @@ loop1:
p0.l = (IMASK & 0xFFFF);
p0.h = (IMASK >> 16);
r0.l = LO(IVG15_POS);
r0.h = HI(IVG15_POS);
r0.l = LO(EVT_IVG15);
r0.h = HI(EVT_IVG15);
[p0] = r0;
raise 15;
p0.l = WAIT_HERE;
@ -495,8 +492,8 @@ copy:
R1.H = reset_end;
R1.L = reset_end;
R2 = R1 - R0; /* Count */
R1.H = hi(L1_ISRAM); /* Destination Address (high) */
R1.L = lo(L1_ISRAM); /* Destination Address (low) */
R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */
R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */
R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */

25
cpu/bf537/traps.c
View file

@ -36,14 +36,13 @@
#include <common.h>
#include <linux/types.h>
#include <asm/errno.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/traps.h>
#include <asm/machdep.h>
#include "cpu.h"
#include <asm/arch/anomaly.h>
#include <asm/cplb.h>
#include <asm/io.h>
#include <asm/mach-common/bits/core.h>
#include <asm/mach-common/bits/mpu.h>
void init_IRQ(void)
{
@ -68,7 +67,7 @@ static unsigned int cplb_sizes[4] =
void trap_c(struct pt_regs *regs)
{
unsigned int addr;
unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE;
unsigned long trapnr = (regs->seqstat) & EXCAUSE;
unsigned int i, j, size, *I0, *I1;
unsigned short data = 0;
@ -76,7 +75,7 @@ void trap_c(struct pt_regs *regs)
/* 0x26 - Data CPLB Miss */
case VEC_CPLB_M:
#ifdef ANOMALY_05000261
#if ANOMALY_05000261
/*
* Work around an anomaly: if we see a new DCPLB fault,
* return without doing anything. Then,
@ -118,16 +117,16 @@ void trap_c(struct pt_regs *regs)
/* Turn the cache off */
if (data) {
sync();
SSYNC();
asm(" .align 8; ");
*(unsigned int *)DMEM_CONTROL &=
~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
sync();
SSYNC();
} else {
sync();
SSYNC();
asm(" .align 8; ");
*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
sync();
SSYNC();
}
if (data) {
@ -173,16 +172,16 @@ void trap_c(struct pt_regs *regs)
/* Turn the cache back on */
if (data) {
j = *(unsigned int *)DMEM_CONTROL;
sync();
SSYNC();
asm(" .align 8; ");
*(unsigned int *)DMEM_CONTROL =
ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j;
sync();
SSYNC();
} else {
sync();
SSYNC();
asm(" .align 8; ");
*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
sync();
SSYNC();
}
break;

4
cpu/bf561/Makefile
View file

@ -28,12 +28,12 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
START = start.o start1.o interrupt.o cache.o flush.o init_sdram.o
SOBJS = start.o start1.o interrupt.o cache.o flush.o init_sdram.o
COBJS = cpu.o traps.o ints.o serial.o interrupts.o video.o
EXTRA = init_sdram_bootrom_initblock.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
START := $(addprefix $(obj),$(START))

1
cpu/bf561/cache.S
View file

@ -2,6 +2,7 @@
#include <asm/linkage.h>
#include <config.h>
#include <asm/blackfin.h>
#include <asm/mach-common/bits/mpu.h>
.text
.align 2

2
cpu/bf561/config.mk
View file

@ -24,4 +24,4 @@
# MA 02110-1301 USA
#
PLATFORM_RELFLAGS += -mcpu=bf561 -ffixed-P5
PLATFORM_RELFLAGS += -mcpu=bf561

26
cpu/bf561/cpu.c
View file

@ -40,7 +40,7 @@ extern unsigned int dcplb_table[page_descriptor_table_size][2];
int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
__asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM)
__asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_INST_SRAM)
);
return 0;
@ -100,22 +100,18 @@ void icache_enable(void)
}
cli();
sync();
SSYNC();
asm(" .align 8; ");
*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
sync();
sti();
SSYNC();
}
void icache_disable(void)
{
cli();
sync();
SSYNC();
asm(" .align 8; ");
*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
sync();
sti();
SSYNC();
}
int icache_status(void)
@ -175,14 +171,12 @@ void dcache_enable(void)
}
}
cli();
temp = *(unsigned int *)DMEM_CONTROL;
sync();
SSYNC();
asm(" .align 8; ");
*(unsigned int *)DMEM_CONTROL =
ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp;
sync();
sti();
SSYNC();
}
void dcache_disable(void)
@ -191,13 +185,11 @@ void dcache_disable(void)
unsigned int *I0, *I1;
int i;
cli();
sync();
SSYNC();
asm(" .align 8; ");
*(unsigned int *)DMEM_CONTROL &=
~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
sync();
sti();
SSYNC();
/* after disable dcache, clear it so we don't confuse the next application */
I0 = (unsigned int *)DCPLB_ADDR0;

4
cpu/bf561/init_sdram.S
View file

@ -4,6 +4,10 @@
#include <config.h>
#include <asm/blackfin.h>
#include <asm/mem_init.h>
#include <asm/mach-common/bits/bootrom.h>
#include <asm/mach-common/bits/ebiu.h>
#include <asm/mach-common/bits/pll.h>
#include <asm/mach-common/bits/uart.h>
.global init_sdram;
#if (CONFIG_CCLK_DIV == 1)

4
cpu/bf561/init_sdram_bootrom_initblock.S
View file

@ -4,6 +4,10 @@
#include <config.h>
#include <asm/blackfin.h>
#include <asm/mem_init.h>
#include <asm/mach-common/bits/bootrom.h>
#include <asm/mach-common/bits/ebiu.h>
#include <asm/mach-common/bits/pll.h>
#include <asm/mach-common/bits/uart.h>
.global init_sdram;
#if (CONFIG_CCLK_DIV == 1)

12
cpu/bf561/interrupt.S
View file

@ -42,9 +42,7 @@
#define ASSEMBLY
#include <config.h>
#include <asm/blackfin.h>
#include <asm/hw_irq.h>
#include <asm/entry.h>
#include <asm/blackfin_defs.h>
.global _blackfin_irq_panic;
@ -55,7 +53,7 @@
.global _evt_emulation
_evt_emulation:
SAVE_CONTEXT
r0 = IRQ_EMU;
r0 = 0;
r1 = seqstat;
sp += -12;
call _blackfin_irq_panic;
@ -66,7 +64,7 @@ _evt_emulation:
.global _evt_nmi
_evt_nmi:
SAVE_CONTEXT
r0 = IRQ_NMI;
r0 = 2;
r1 = RETN;
sp += -12;
call _blackfin_irq_panic;
@ -88,7 +86,7 @@ _trap:
.global _evt_rst
_evt_rst:
SAVE_CONTEXT
r0 = IRQ_RST;
r0 = 1;
r1 = RETN;
sp += -12;
call _do_reset;
@ -98,7 +96,7 @@ _evt_rst_exit:
rtn;
irq_panic:
r0 = IRQ_EVX;
r0 = 3;
r1 = sp;
sp += -12;
call _blackfin_irq_panic;
@ -115,7 +113,7 @@ _evt_ivhw_exit:
.global _evt_timer
_evt_timer:
SAVE_CONTEXT
r0 = IRQ_CORETMR;
r0 = 6;
sp += -12;
/* Polling method used now. */
/* call timer_int; */

4
cpu/bf561/interrupts.c
View file

@ -35,8 +35,6 @@
*/
#include <common.h>
#include <asm/machdep.h>
#include <asm/irq.h>
#include <config.h>
#include <asm/blackfin.h>
#include "cpu.h"
@ -72,12 +70,10 @@ ulong get_tbclk(void)
void enable_interrupts(void)
{
restore_flags(int_flag);
}
int disable_interrupts(void)
{
save_and_cli(int_flag);
return 1;
}

37
cpu/bf561/ints.c
View file

@ -39,12 +39,9 @@
#include <common.h>
#include <linux/stddef.h>
#include <asm/system.h>
#include <asm/irq.h>
#include <asm/traps.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/machdep.h>
#include <asm/setup.h>
#include <asm/blackfin.h>
#include "cpu.h"
@ -61,42 +58,40 @@ void blackfin_irq_panic(int reason, struct pt_regs *regs)
void blackfin_init_IRQ(void)
{
*(unsigned volatile long *)(SIC_IMASK) = SIC_UNMASK_ALL;
cli();
*(unsigned volatile long *)(SICA_IMASK0) = 0;
#ifndef CONFIG_KGDB
*(unsigned volatile long *)(EVT_EMULATION_ADDR) = 0x0;
*(unsigned volatile long *)(EVT1) = 0x0;
#endif
*(unsigned volatile long *)(EVT_NMI_ADDR) =
*(unsigned volatile long *)(EVT2) =
(unsigned volatile long)evt_nmi;
*(unsigned volatile long *)(EVT_EXCEPTION_ADDR) =
*(unsigned volatile long *)(EVT3) =
(unsigned volatile long)trap;
*(unsigned volatile long *)(EVT_HARDWARE_ERROR_ADDR) =
*(unsigned volatile long *)(EVT5) =
(unsigned volatile long)evt_ivhw;
*(unsigned volatile long *)(EVT_RESET_ADDR) =
*(unsigned volatile long *)(EVT0) =
(unsigned volatile long)evt_rst;
*(unsigned volatile long *)(EVT_TIMER_ADDR) =
*(unsigned volatile long *)(EVT6) =
(unsigned volatile long)evt_timer;
*(unsigned volatile long *)(EVT_IVG7_ADDR) =
*(unsigned volatile long *)(EVT7) =
(unsigned volatile long)evt_evt7;
*(unsigned volatile long *)(EVT_IVG8_ADDR) =
*(unsigned volatile long *)(EVT8) =
(unsigned volatile long)evt_evt8;
*(unsigned volatile long *)(EVT_IVG9_ADDR) =
*(unsigned volatile long *)(EVT9) =
(unsigned volatile long)evt_evt9;
*(unsigned volatile long *)(EVT_IVG10_ADDR) =
*(unsigned volatile long *)(EVT10) =
(unsigned volatile long)evt_evt10;
*(unsigned volatile long *)(EVT_IVG11_ADDR) =
*(unsigned volatile long *)(EVT11) =
(unsigned volatile long)evt_evt11;
*(unsigned volatile long *)(EVT_IVG12_ADDR) =
*(unsigned volatile long *)(EVT12) =
(unsigned volatile long)evt_evt12;
*(unsigned volatile long *)(EVT_IVG13_ADDR) =
*(unsigned volatile long *)(EVT13) =
(unsigned volatile long)evt_evt13;
*(unsigned volatile long *)(EVT_IVG14_ADDR) =
*(unsigned volatile long *)(EVT14) =
(unsigned volatile long)evt_system_call;
*(unsigned volatile long *)(EVT_IVG15_ADDR) =
*(unsigned volatile long *)(EVT15) =
(unsigned volatile long)evt_soft_int1;
*(volatile unsigned long *)ILAT = 0;
asm("csync;");
sti();
*(volatile unsigned long *)IMASK = 0xffbf;
asm("csync;");
}

47
cpu/bf561/serial.c
View file

@ -43,14 +43,12 @@
*/
#include <common.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/segment.h>
#include <asm/bitops.h>
#include <asm/delay.h>
#include <asm/uaccess.h>
#include "serial.h"
#include <asm/io.h>
#include <asm/mach-common/bits/uart.h>
DECLARE_GLOBAL_DATA_PTR;
@ -85,32 +83,32 @@ void serial_setbrg(void)
}
/* Enable UART */
*pUART_GCTL |= UART_GCTL_UCEN;
sync();
*pUART_GCTL |= UCEN;
SSYNC();
/* Set DLAB in LCR to Access DLL and DLH */
ACCESS_LATCH;
sync();
SSYNC();
*pUART_DLL = hw_baud_table[i].dl_low;
sync();
SSYNC();
*pUART_DLH = hw_baud_table[i].dl_high;
sync();
SSYNC();
/* Clear DLAB in LCR to Access THR RBR IER */
ACCESS_PORT_IER;
sync();
SSYNC();
/*
* Enable ERBFI and ELSI interrupts
* to poll SIC_ISR register
*/
*pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI;
sync();
*pUART_IER = ELSI | ERBFI | ETBEI;
SSYNC();
/* Set LCR to Word Lengh 8-bit word select */
*pUART_LCR = UART_LCR_WLS8;
sync();
*pUART_LCR = WLS_8;
SSYNC();
return;
}
@ -123,14 +121,14 @@ int serial_init(void)
void serial_putc(const char c)
{
if ((*pUART_LSR) & UART_LSR_TEMT) {
if ((*pUART_LSR) & TEMT) {
if (c == '\n')
serial_putc('\r');
local_put_char(c);
}
while (!((*pUART_LSR) & UART_LSR_TEMT))
while (!((*pUART_LSR) & TEMT))
SYNC_ALL;
return;
@ -138,7 +136,7 @@ void serial_putc(const char c)
int serial_tstc(void)
{
if (*pUART_LSR & UART_LSR_DR)
if (*pUART_LSR & DR)
return 1;
else
return 0;
@ -151,14 +149,14 @@ int serial_getc(void)
int ret;
/* Poll for RX Interrupt */
while (!((isr_val =
*(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT)) ;
while (!serial_tstc())
continue;
asm("csync;");
uart_lsr_val = *pUART_LSR; /* Clear status bit */
uart_rbr_val = *pUART_RBR; /* getc() */
if (isr_val & IRQ_UART_ERROR_BIT) {
if (uart_lsr_val & (OE|PE|FE|BI)) {
ret = -1;
} else {
ret = uart_rbr_val & 0xff;
@ -179,19 +177,12 @@ static void local_put_char(char ch)
int flags = 0;
unsigned long isr_val;
save_and_cli(flags);
/* Poll for TX Interruput */
while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)) ;
while (!(*pUART_LSR & THRE))
continue;
asm("csync;");
*pUART_THR = ch; /* putc() */
if (isr_val & IRQ_UART_ERROR_BIT) {
printf("?");
}
restore_flags(flags);
return;
}

4
cpu/bf561/serial.h
View file

@ -49,8 +49,8 @@
#include <asm/blackfin.h>
#define SYNC_ALL __asm__ __volatile__ ("ssync;\n")
#define ACCESS_LATCH *pUART_LCR |= UART_LCR_DLAB;
#define ACCESS_PORT_IER *pUART_LCR &= (~UART_LCR_DLAB);
#define ACCESS_LATCH *pUART_LCR |= DLAB;
#define ACCESS_PORT_IER *pUART_LCR &= (~DLAB);
void serial_setbrg(void);
static void local_put_char(char ch);

58
cpu/bf561/start.S
View file

@ -41,17 +41,16 @@
#include <config.h>
#include <asm/blackfin.h>
#include <asm/mach-common/bits/core.h>
#include <asm/mach-common/bits/dma.h>
#include <asm/mach-common/bits/pll.h>
.global _stext;
.global __bss_start;
.global start;
.global _start;
.global _rambase;
.global _ramstart;
.global _ramend;
.global edata;
.global _initialize;
.global _exit;
.global flashdataend;
.global init_sdram;
.text
@ -127,16 +126,16 @@ no_soft_reset:
nop;
/* Clear EVT registers */
p0.h = (EVT_EMULATION_ADDR >> 16);
p0.l = (EVT_EMULATION_ADDR & 0xFFFF);
p0.h = (EVT0 >> 16);
p0.l = (EVT0 & 0xFFFF);
p0 += 8;
p1 = 14;
r1 = 0;
LSETUP(4,4) lc0 = p1;
[ p0 ++ ] = r1;
p0.h = hi(SIC_IWR);
p0.l = lo(SIC_IWR);
p0.h = hi(SICA_IWR0);
p0.l = lo(SICA_IWR0);
r0.l = 0x1;
w[p0] = r0.l;
SSYNC;
@ -193,8 +192,8 @@ loop1:
*/
/* To keep ourselves in the supervisor mode */
p0.l = (EVT_IVG15_ADDR & 0xFFFF);
p0.h = (EVT_IVG15_ADDR >> 16);
p0.l = (EVT15 & 0xFFFF);
p0.h = (EVT15 >> 16);
p1.l = _real_start;
p1.h = _real_start;
@ -202,8 +201,8 @@ loop1:
p0.l = (IMASK & 0xFFFF);
p0.h = (IMASK >> 16);
r0.l = LO(IVG15_POS);
r0.h = HI(IVG15_POS);
r0.l = LO(EVT_IVG15);
r0.h = HI(EVT_IVG15);
[p0] = r0;
raise 15;
p0.l = WAIT_HERE;
@ -218,13 +217,6 @@ WAIT_HERE:
_real_start:
[ -- sp ] = reti;
#ifdef CONFIG_EZKIT561
p0.l = (WDOG_CTL & 0xFFFF);
p0.h = (WDOG_CTL >> 16);
r0 = WATCHDOG_DISABLE(z);
w[p0] = r0;
#endif
/* DMA reset code to Hi of L1 SRAM */
copy:
P1.H = hi(SYSMMR_BASE); /* P1 Points to the beginning of SYSTEM MMR Space */
@ -235,37 +227,37 @@ copy:
R1.H = reset_end;
R1.L = reset_end;
R2 = R1 - R0; /* Count */
R1.H = hi(L1_ISRAM); /* Destination Address (high) */
R1.L = lo(L1_ISRAM); /* Destination Address (low) */
R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */
R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */
R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
DMA:
R6 = 0x1 (Z);
W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
W[P1+OFFSET_(IMDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
W[P1+OFFSET_(IMDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
[P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
[P1+OFFSET_(IMDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
W[P1+OFFSET_(IMDMA_S0_X_COUNT)] = R2; /* Set Source Count */
/* Set Source DMAConfig = DMA Enable,
Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
W[P1+OFFSET_(IMDMA_S0_CONFIG)] = R3;
[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
[P1+OFFSET_(IMDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
W[P1+OFFSET_(IMDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
/* Set Destination DMAConfig = DMA Enable,
Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
W[P1+OFFSET_(IMDMA_D0_CONFIG)] = R4;
WAIT_DMA_DONE:
p0.h = hi(MDMA_D0_IRQ_STATUS);
p0.l = lo(MDMA_D0_IRQ_STATUS);
p0.h = hi(IMDMA_D0_IRQ_STATUS);
p0.l = lo(IMDMA_D0_IRQ_STATUS);
R0 = W[P0](Z);
CC = BITTST(R0, 0);
if ! CC jump WAIT_DMA_DONE
R0 = 0x1;
W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
W[P1+OFFSET_(IMDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
/* Initialize BSS Section with 0 s */
p1.l = __bss_start;

25
cpu/bf561/traps.c
View file

@ -36,14 +36,13 @@
#include <common.h>
#include <linux/types.h>
#include <asm/errno.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/traps.h>
#include <asm/machdep.h>
#include "cpu.h"
#include <asm/arch/anomaly.h>
#include <asm/cplb.h>
#include <asm/io.h>
#include <asm/mach-common/bits/core.h>
#include <asm/mach-common/bits/mpu.h>
void init_IRQ(void)
{
@ -68,7 +67,7 @@ static unsigned int cplb_sizes[4] =
void trap_c(struct pt_regs *regs)
{
unsigned int addr;
unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE;
unsigned long trapnr = (regs->seqstat) & EXCAUSE;
unsigned int i, j, size, *I0, *I1;
unsigned short data = 0;
@ -76,7 +75,7 @@ void trap_c(struct pt_regs *regs)
/* 0x26 - Data CPLB Miss */
case VEC_CPLB_M:
#ifdef ANOMALY_05000261
#if ANOMALY_05000261
/*
* Work around an anomaly: if we see a new DCPLB fault, return
* without doing anything. Then, if we get the same fault again,
@ -118,16 +117,16 @@ void trap_c(struct pt_regs *regs)
/* Turn the cache off */
if (data) {
sync();
SSYNC();
asm(" .align 8; ");
*(unsigned int *)DMEM_CONTROL &=
~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
sync();
SSYNC();
} else {
sync();
SSYNC();
asm(" .align 8; ");
*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
sync();
SSYNC();
}
if (data) {
@ -173,16 +172,16 @@ void trap_c(struct pt_regs *regs)
/* Turn the cache back on */
if (data) {
j = *(unsigned int *)DMEM_CONTROL;
sync();
SSYNC();
asm(" .align 8; ");
*(unsigned int *)DMEM_CONTROL =
ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j;
sync();
SSYNC();
} else {
sync();
SSYNC();
asm(" .align 8; ");
*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
sync();
SSYNC();
}
break;

46
doc/README.blackfin Normal file
View file

@ -0,0 +1,46 @@
Notes for the Blackfin architecture port of Das U-Boot
=========
! ABOUT !
=========
<marketing blurb>
Blackfin Processors embody a new breed of 16/32-bit embedded processor, ideally
suited for products where a convergence of capabilities are necessary -
multi-format audio, video, voice and image processing; multi-mode baseband and
packet processing; control processing; and real-time security. The Blackfin's
unique combination of software flexibility and scalability has gained it
widespread adoption in convergent applications.
</marketing blurb>
The Blackfin processor is wholly developed by Analog Devices Inc.
===========
! SUPPORT !
===========
All open source code for the Blackfin processors are being handled via our
collaborative website:
http://blackfin.uclinux.org/
In particular, bug reports, feature requests, help etc... for Das U-Boot are
handled in the Das U-Boot sub project:
http://blackfin.uclinux.org/gf/project/u-boot
This website is backed both by an open source community as well as a dedicated
team from Analog Devices Inc.
=============
! TOOLCHAIN !
=============
To compile the Blackfin aspects, you'll need the GNU toolchain configured for
the Blackfin processor. You can obtain such a cross-compiler here:
http://blackfin.uclinux.org/gf/project/toolchain
=================
! DOCUMENTATION !
=================
For Blackfin specific documentation, you can visit our dedicated doc wiki:
http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot

12
doc/README.standalone
View file

@ -19,11 +19,12 @@ Design Notes on Exporting U-Boot Functions to Standalone Applications:
thus the compiler cannot perform type checks on these assignments.
2. The pointer to the jump table is passed to the application in a
machine-dependent way. PowerPC, ARM and MIPS architectures use a
dedicated register to hold the pointer to the 'global_data'
structure: r2 on PowerPC, r8 on ARM and k0 on MIPS. The x86
architecture does not use such a register; instead, the pointer to
the 'global_data' structure is passed as 'argv[-1]' pointer.
machine-dependent way. PowerPC, ARM, MIPS and Blackfin architectures
use a dedicated register to hold the pointer to the 'global_data'
structure: r2 on PowerPC, r8 on ARM, k0 on MIPS, and P5 on Blackfin.
The x86 architecture does not use such a register; instead, the
pointer to the 'global_data' structure is passed as 'argv[-1]'
pointer.
The application can access the 'global_data' structure in the same
way as U-Boot does:
@ -54,6 +55,7 @@ Design Notes on Exporting U-Boot Functions to Standalone Applications:
PowerPC 0x00040000 0x00040004
ARM 0x0c100000 0x0c100000
MIPS 0x80200000 0x80200000
Blackfin 0x00001000 0x00001000
For example, the "hello world" application may be loaded and
executed on a PowerPC board with the following commands:

2
drivers/rtc/Makefile
View file

@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)librtc.a
COBJS-y += date.o
COBJS-y += bf5xx_rtc.o
COBJS-y += bfin_rtc.o
COBJS-y += ds12887.o
COBJS-y += ds1302.o
COBJS-y += ds1306.o

143
drivers/rtc/bf5xx_rtc.c
View file

@ -1,143 +0,0 @@
/*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Real Time Clock interface of ADI21535 (Blackfin) for uCLinux
*
* Copyright (C) 2003 Motorola Corporation. All rights reserved.
* Richard Xiao (A2590C@email.mot.com)
*
* Copyright (C) 1996 Paul Gortmaker
*
*
* Based on other minimal char device drivers, like Alan's
* watchdog, Ted's random, etc. etc.
*
* 1.07 Paul Gortmaker.
* 1.08 Miquel van Smoorenburg: disallow certain things on the
* DEC Alpha as the CMOS clock is also used for other things.
* 1.09 Nikita Schmidt: epoch support and some Alpha cleanup.
* 1.09a Pete Zaitcev: Sun SPARC
* 1.09b Jeff Garzik: Modularize, init cleanup
* 1.09c Jeff Garzik: SMP cleanup
* 1.10 Paul Barton-Davis: add support for async I/O
* 1.10a Andrea Arcangeli: Alpha updates
* 1.10b Andrew Morton: SMP lock fix
* 1.10c Cesar Barros: SMP locking fixes and cleanup
* 1.10d Paul Gortmaker: delete paranoia check in rtc_exit
* 1.10e LG Soft India: Register access is different in BF533.
*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#if defined(CONFIG_RTC_BFIN) && defined(CONFIG_CMD_DATE)
#include <asm/blackfin.h>
#include <asm/arch/bf5xx_rtc.h>
void rtc_reset(void)
{
return; /* nothing to do */
}
/* Wait for pending writes to complete */
void wait_for_complete(void)
{
while (!(*(volatile unsigned short *)RTC_ISTAT & 0x8000)) {
printf("");
}
*(volatile unsigned short *)RTC_ISTAT = 0x8000;
}
/* Enable the RTC prescaler enable register */
void rtc_init()
{
*(volatile unsigned short *)RTC_PREN = 0x1;
wait_for_complete();
}
/* Set the time. Get the time_in_secs which is the number of seconds since Jan 1970 and set the RTC registers
* based on this value.
*/
void rtc_set(struct rtc_time *tmp)
{
unsigned long n_days_1970 = 0;
unsigned long n_secs_rem = 0;
unsigned long n_hrs = 0;
unsigned long n_mins = 0;
unsigned long n_secs = 0;
unsigned long time_in_secs;
if (tmp == NULL) {
printf("Error setting the date/time \n");
return;
}
time_in_secs =
mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_hour,
tmp->tm_min, tmp->tm_sec);
/* Compute no. of days since 1970 */
n_days_1970 = (unsigned long)(time_in_secs / (NUM_SECS_IN_DAY));
/* From the remining secs, compute the hrs(0-23), mins(0-59) and secs(0-59) */
n_secs_rem = (unsigned long)(time_in_secs % (NUM_SECS_IN_DAY));
n_hrs = n_secs_rem / (NUM_SECS_IN_HOUR);
n_secs_rem = n_secs_rem % (NUM_SECS_IN_HOUR);
n_mins = n_secs_rem / (NUM_SECS_IN_MIN);
n_secs = n_secs_rem % (NUM_SECS_IN_MIN);
/* Store the new time in the RTC_STAT register */
*(volatile unsigned long *)RTC_STAT =
((n_days_1970 << DAY_BITS_OFF) | (n_hrs << HOUR_BITS_OFF) |
(n_mins << MIN_BITS_OFF) | (n_secs << SEC_BITS_OFF));
wait_for_complete();
}
/* Read the time from the RTC_STAT. time_in_seconds is seconds since Jan 1970 */
void rtc_get(struct rtc_time *tmp)
{
unsigned long cur_rtc_stat = 0;
unsigned long time_in_sec;
unsigned long tm_sec = 0, tm_min = 0, tm_hour = 0, tm_day = 0;
if (tmp == NULL) {
printf("Error getting the date/time \n");
return;
}
/* Read the RTC_STAT register */
cur_rtc_stat = *(volatile unsigned long *)RTC_STAT;
/* Get the secs (0-59), mins (0-59), hrs (0-23) and the days since Jan 1970 */
tm_sec = (cur_rtc_stat >> SEC_BITS_OFF) & 0x3f;
tm_min = (cur_rtc_stat >> MIN_BITS_OFF) & 0x3f;
tm_hour = (cur_rtc_stat >> HOUR_BITS_OFF) & 0x1f;
tm_day = (cur_rtc_stat >> DAY_BITS_OFF) & 0x7fff;
/* Calculate the total number of seconds since Jan 1970 */
time_in_sec = (tm_sec) +
MIN_TO_SECS(tm_min) + HRS_TO_SECS(tm_hour) + DAYS_TO_SECS(tm_day);
to_tm(time_in_sec, tmp);
}
#endif

117
drivers/rtc/bfin_rtc.c Normal file
View file

@ -0,0 +1,117 @@
/*
* Copyright (c) 2004-2008 Analog Devices Inc.
*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Licensed under the GPL-2 or later.
*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#if defined(CONFIG_RTC_BFIN) && defined(CONFIG_CMD_DATE)
#include <asm/blackfin.h>
#include <asm/mach-common/bits/rtc.h>
#define pr_stamp() debug("%s:%s:%i: here i am\n", __FILE__, __func__, __LINE__)
#define MIN_TO_SECS(x) (60 * (x))
#define HRS_TO_SECS(x) (60 * MIN_TO_SECS(x))
#define DAYS_TO_SECS(x) (24 * HRS_TO_SECS(x))
#define NUM_SECS_IN_MIN MIN_TO_SECS(1)
#define NUM_SECS_IN_HR HRS_TO_SECS(1)
#define NUM_SECS_IN_DAY DAYS_TO_SECS(1)
/* Our on-chip RTC has no notion of "reset" */
void rtc_reset(void)
{
return;
}
/* Wait for pending writes to complete */
static void wait_for_complete(void)
{
pr_stamp();
while (!(bfin_read_RTC_ISTAT() & WRITE_COMPLETE))
if (!(bfin_read_RTC_ISTAT() & WRITE_PENDING))
break;
bfin_write_RTC_ISTAT(WRITE_COMPLETE);
}
/* Enable the RTC prescaler enable register */
int rtc_init(void)
{
pr_stamp();
bfin_write_RTC_PREN(0x1);
return 0;
}
/* Set the time. Get the time_in_secs which is the number of seconds since Jan 1970 and set the RTC registers
* based on this value.
*/
void rtc_set(struct rtc_time *tmp)
{
unsigned long remain, days, hrs, mins, secs;
pr_stamp();
if (tmp == NULL) {
puts("Error setting the date/time\n");
return;
}
wait_for_complete();
/* Calculate number of seconds this incoming time represents */
remain = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
/* Figure out how many days since epoch */
days = remain / NUM_SECS_IN_DAY;
/* From the remaining secs, compute the hrs(0-23), mins(0-59) and secs(0-59) */
remain = remain % NUM_SECS_IN_DAY;
hrs = remain / NUM_SECS_IN_HR;
remain = remain % NUM_SECS_IN_HR;
mins = remain / NUM_SECS_IN_MIN;
secs = remain % NUM_SECS_IN_MIN;
/* Encode these time values into our RTC_STAT register */
bfin_write_RTC_STAT(SET_ALARM(days, hrs, mins, secs));
}
/* Read the time from the RTC_STAT. time_in_seconds is seconds since Jan 1970 */
void rtc_get(struct rtc_time *tmp)
{
uint32_t cur_rtc_stat;
int time_in_sec;
int tm_sec, tm_min, tm_hr, tm_day;
pr_stamp();
if (tmp == NULL) {
puts("Error getting the date/time\n");
return;
}
wait_for_complete();
/* Read the RTC_STAT register */
cur_rtc_stat = bfin_read_RTC_STAT();
/* Convert our encoded format into actual time values */
tm_sec = (cur_rtc_stat & RTC_SEC) >> RTC_SEC_P;
tm_min = (cur_rtc_stat & RTC_MIN) >> RTC_MIN_P;
tm_hr = (cur_rtc_stat & RTC_HR ) >> RTC_HR_P;
tm_day = (cur_rtc_stat & RTC_DAY) >> RTC_DAY_P;
/* Calculate the total number of seconds since epoch */
time_in_sec = (tm_sec) + MIN_TO_SECS(tm_min) + HRS_TO_SECS(tm_hr) + DAYS_TO_SECS(tm_day);
to_tm(time_in_sec, tmp);
}
#endif

1
examples/.gitignore vendored
View file

@ -1,5 +1,6 @@
/hello_world
/interrupt
/sched
/smc91111_eeprom
*.bin
*.srec

6
examples/Makefile
View file

@ -91,14 +91,10 @@ BIN += sched.bin
endif
ifeq ($(ARCH),blackfin)
ifneq ($(BOARD),bf537-stamp)
ifneq ($(BOARD),bf537-pnav)
ELF += smc91111_eeprom
SREC += smc91111_eeprom.srec
BIN += smc91111_eeprom.bin
endif
endif
endif
# The following example is pretty 8xx specific...
ifeq ($(CPU),mpc8xx)
@ -166,7 +162,7 @@ $(LIB): $(obj).depend $(LIBOBJS)
$(ELF):
$(obj)%: $(obj)%.o $(LIB)
$(LD) -g $(EX_LDFLAGS) -Ttext $(LOAD_ADDR) \
-o $@ -e $(notdir $(<:.o=)) $< $(LIB) \
-o $@ -e $(SYM_PREFIX)$(notdir $(<:.o=)) $< $(LIB) \
-L$(gcclibdir) -lgcc
$(SREC):

BIN
examples/smc91111_eeprom Executable file
View file

Binary file not shown.

31
examples/smc91111_eeprom.c
View file

@ -31,6 +31,13 @@
#include <exports.h>
#include "../drivers/net/smc91111.h"
#ifdef CONFIG_DRIVER_SMC91111
#ifdef pFIO0_DIR
# define pFIO_DIR pFIO0_DIR
# define pFIO_FLAG_S pFIO0_FLAG_S
#endif
#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
#define EEPROM 0x1;
#define MAC 0x2;
@ -59,17 +66,9 @@ int smc91111_eeprom (int argc, char *argv[])
return (0);
}
asm ("p2.h = 0xFFC0;");
asm ("p2.l = 0x0730;");
asm ("r0 = 0x01;");
asm ("w[p2] = r0;");
asm ("ssync;");
asm ("p2.h = 0xffc0;");
asm ("p2.l = 0x0708;");
asm ("r0 = 0x01;");
asm ("w[p2] = r0;");
asm ("ssync;");
*pFIO_DIR = 0x01;
*pFIO_FLAG_S = 0x01;
SSYNC();
if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) {
printf ("Can't find SMSC91111\n");
@ -387,3 +386,13 @@ void dump_reg (void)
printf ("\n");
}
}
#else
int smc91111_eeprom (int argc, char *argv[])
{
printf("Not supported for this board\n");
return 1;
}
#endif

1
include/.gitignore vendored
View file

@ -1,5 +1,6 @@
/autoconf.mk*
/asm
/asm-blackfin/arch
/asm-ppc/arch
/bmp_logo.h
/config.h

172
include/asm-blackfin/arch-bf533/anomaly.h
View file

@ -1,172 +0,0 @@
/*
* File: include/asm-blackfin/arch-bf533/anomaly.h
* Based on:
* Author:
*
* Created:
* Description:
*
* Rev:
*
* Modified:
*
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING.
* If not, write to the Free Software Foundation,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/* This file shoule be up to date with:
* - Revision U, May 17, 2006; ADSP-BF533 Blackfin Processor Anomaly List
* - Revision Y, May 17, 2006; ADSP-BF532 Blackfin Processor Anomaly List
* - Revision T, May 17, 2006; ADSP-BF531 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_
/* We do not support 0.1 or 0.2 silicon - sorry */
#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2))
#error Kernel will not work on BF533 Version 0.1 or 0.2
#endif
/* Issues that are common to 0.5, 0.4, and 0.3 silicon */
#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
slot1 and store of a P register in slot 2 is not
supported */
#define ANOMALY_05000105 /* Watchpoint Status Register (WPSTAT) bits are set on
every corresponding match */
#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
Channel DMA stops */
#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
registers. */
#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
upper bits*/
#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */
#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
syncs */
#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not
functional */
#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
state */
#define ANOMALY_05000229 /* SPI Slave Boot Mode modifies registers */
#define ANOMALY_05000272 /* Certain data cache write through modes fail for
VDDint <=0.9V */
#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
an edge is detected may clear interrupt */
#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
DMA system instability */
#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
not restored */
#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
control */
#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
killed in a particular stage*/
#endif
/* These issues only occur on 0.3 or 0.4 BF533 */
#if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not
updated at the same time. */
#define ANOMALY_05000158 /* Boot fails when data cache enabled: Data from a Data
Cache Fill can be corrupted after or during
Instruction DMA if certain core stalls exist */
#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General
Purpose TX or RX modes */
#define ANOMALY_05000198 /* Failing SYSTEM MMR accesses when stalled by
preceding memory read */
#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during
inactive channels in certain conditions */
#define ANOMALY_05000202 /* Possible infinite stall with specific dual dag
situation */
#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */
#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */
#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect
data*/
#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate
Differences in certain Conditions */
#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */
#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to
hardware reset */
#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
IDLE around a Change of Control causes
unpredictable results */
#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the
shadow of a conditional branch */
#define ANOMALY_05000246 /* Data CPLB's should prevent spurious hardware
errors */
#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
interrupt not functional */
#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
loops may cause the instruction fetch unit to
malfunction */
#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
the ICPLB Data registers differ */
#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
#define ANOMALY_05000262 /* Stores to data cache may be lost */
#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
instruction will cause an infinite stall in the
second to last instruction in a hardware loop */
#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
SPORT external receive and transmit clocks. */
#define ANOMALY_05000269 /* High I/O activity causes the output voltage of the
internal voltage regulator (VDDint) to increase. */
#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
internal voltage regulator (VDDint) to decrease */
#endif
/* These issues are only on 0.4 silicon */
#if (defined(CONFIG_BF_REV_0_4))
#define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */
#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
(TDM) */
#endif
/* These issues are only on 0.3 silicon */
#if defined(CONFIG_BF_REV_0_3)
#define ANOMALY_05000183 /* Timer Pin limitations for PPI TX Modes with
External Frame Syncs */
#define ANOMALY_05000189 /* False Protection Exceptions caused by Speculative
Instruction or Data Fetches, or by Fetches at the
boundary of reserved memory space */
#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs
when polarity setting is changed */
#define ANOMALY_05000194 /* Sport Restarting in specific modes may cause data
corruption */
#define ANOMALY_05000199 /* DMA current address shows wrong value during carry
fix */
#define ANOMALY_05000201 /* Receive frame sync not ignored during active
frames in sport MCM */
#define ANOMALY_05000203 /* Specific sequence that can cause DMA error or DMA
stopping */
#if defined(CONFIG_BF533)
#define ANOMALY_05000204 /* Incorrect data read with write-through cache and
allocate cache lines on reads only mode */
#endif /* CONFIG_BF533 */
#define ANOMALY_05000207 /* Recovery from "brown-out" condition */
#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain
instructions */
#define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame
Sync Transmit Mode */
#define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */
#endif
#endif /* _MACH_ANOMALY_H_ */

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include/asm-blackfin/arch-bf533/bf533_serial.h
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/*
* U-boot bf533_serial.h
*
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BF533_SERIAL_H_
#define _BF533_SERIAL_H_
#define BYTE_REF(addr) (*((volatile char*)addr))
#define HALFWORD_REF(addr) (*((volatile short*)addr))
#define WORD_REF(addr) (*((volatile long*)addr))
#define UART_THR_LO HALFWORD_REF(UART_THR)
#define UART_RBR_LO HALFWORD_REF(UART_RBR)
#define UART_DLL_LO HALFWORD_REF(UART_DLL)
#define UART_IER_LO HALFWORD_REF(UART_IER)
#define UART_IER_ERBFI 0x01
#define UART_IER_ETBEI 0x02
#define UART_IER_ELSI 0x04
#define UART_IER_EDDSI 0x08
#define UART_DLH_LO HALFWORD_REF(UART_DLH)
#define UART_IIR_LO HALFWORD_REF(UART_IIR)
#define UART_IIR_NOINT 0x01
#define UART_IIR_STATUS 0x06
#define UART_IIR_LSR 0x06
#define UART_IIR_RBR 0x04
#define UART_IIR_THR 0x02
#define UART_IIR_MSR 0x00
#define UART_LCR_LO HALFWORD_REF(UART_LCR)
#define UART_LCR_WLS5 0
#define UART_LCR_WLS6 0x01
#define UART_LCR_WLS7 0x02
#define UART_LCR_WLS8 0x03
#define UART_LCR_STB 0x04
#define UART_LCR_PEN 0x08
#define UART_LCR_EPS 0x10
#define UART_LCR_SP 0x20
#define UART_LCR_SB 0x40
#define UART_LCR_DLAB 0x80
#define UART_MCR_LO HALFWORD_REF(UART_MCR)
#define UART_LSR_LO HALFWORD_REF(UART_LSR)
#define UART_LSR_DR 0x01
#define UART_LSR_OE 0x02
#define UART_LSR_PE 0x04
#define UART_LSR_FE 0x08
#define UART_LSR_BI 0x10
#define UART_LSR_THRE 0x20
#define UART_LSR_TEMT 0x40
#define UART_MSR_LO HALFWORD_REF(UART_MSR)
#define UART_SCR_LO HALFWORD_REF(UART_SCR)
#define UART_GCTL_LO HALFWORD_REF(UART_GCTL)
#define UART_GCTL_UCEN 0x01
#endif

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include/asm-blackfin/arch-bf533/bf5xx_rtc.h
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@ -1,46 +0,0 @@
/*
* U-boot - bf533_rtc.h
*
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BF533_RTC_H_
#define _BF533_RTC_H_
void rtc_init(void);
void wait_for_complete(void);
void rtc_reset(void);
#define MIN_TO_SECS(_x_) (60 * _x_)
#define HRS_TO_SECS(_x_) (60 * 60 * _x_)
#define DAYS_TO_SECS(_x_) (24 * 60 * 60 * _x_)
#define NUM_SECS_IN_DAY (24 * 3600)
#define NUM_SECS_IN_HOUR (3600)
#define NUM_SECS_IN_MIN (60)
/* Shift values for RTC_STAT register */
#define DAY_BITS_OFF 17
#define HOUR_BITS_OFF 12
#define MIN_BITS_OFF 6
#define SEC_BITS_OFF 0
#endif

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include/asm-blackfin/arch-bf533/cdefBF531.h
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/*
* cdefBF531.h
*
* This file is subject to the terms and conditions of the GNU Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Non-GPL License also available as part of VisualDSP++
*
* http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
*
* (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
*
* This file under source code control, please send bugs or changes to:
* dsptools.support@analog.com
*
*/
#ifndef _CDEFBF531_H
#define _CDEFBF531_H
#include <asm/arch-bf533/cdefBF532.h>
#endif /* _CDEFBF531_H */

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include/asm-blackfin/arch-bf533/cdefBF532.h
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/*
* cdefBF532.h
*
* This file is subject to the terms and conditions of the GNU Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Non-GPL License also available as part of VisualDSP++
*
* http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
*
* (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
*
* This file under source code control, please send bugs or changes to:
* dsptools.support@analog.com
*
*/
#ifndef _CDEF_BF532_H
#define _CDEF_BF532_H
/*
* #if !defined(__ADSPLPBLACKFIN__)
* #warning cdefBF532.h should only be included for 532 compatible chips.
* #endif
*/
/* include all Core registers and bit definitions */
#include <asm/arch-bf533/defBF532.h>
/* include core specific register pointer definitions */
#include <asm/arch-common/cdef_LPBlackfin.h>
/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
#define pPLL_CTL ((volatile unsigned short *)PLL_CTL)
#define pPLL_STAT ((volatile unsigned short *)PLL_STAT)
#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT)
#define pCHIPID ((volatile unsigned long *)CHIPID)
#define pSWRST ((volatile unsigned short *)SWRST)
#define pSYSCR ((volatile unsigned short *)SYSCR)
#define pPLL_DIV ((volatile unsigned short *)PLL_DIV)
#define pVR_CTL ((volatile unsigned short *)VR_CTL)
/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0)
#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1)
#define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2)
#define pSIC_IAR3 ((volatile unsigned long *)SIC_IAR3)
#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK)
#define pSIC_ISR ((volatile unsigned long *)SIC_ISR)
#define pSIC_IWR ((volatile unsigned long *)SIC_IWR)
/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */
#define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL)
#define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT)
#define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT)
/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */
#define pRTC_STAT ((volatile unsigned long *)RTC_STAT)
#define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL)
#define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT)
#define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT)
#define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM)
#define pRTC_FAST ((volatile unsigned short *)RTC_FAST)
#define pRTC_PREN ((volatile unsigned short *)RTC_PREN)
/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
#define pFIO_DIR ((volatile unsigned short *)FIO_DIR)
#define pFIO_FLAG_C ((volatile unsigned short *)FIO_FLAG_C)
#define pFIO_FLAG_S ((volatile unsigned short *)FIO_FLAG_S)
#define pFIO_MASKA_C ((volatile unsigned short *)FIO_MASKA_C)
#define pFIO_MASKA_S ((volatile unsigned short *)FIO_MASKA_S)
#define pFIO_MASKB_C ((volatile unsigned short *)FIO_MASKB_C)
#define pFIO_MASKB_S ((volatile unsigned short *)FIO_MASKB_S)
#define pFIO_POLAR ((volatile unsigned short *)FIO_POLAR)
#define pFIO_EDGE ((volatile unsigned short *)FIO_EDGE)
#define pFIO_BOTH ((volatile unsigned short *)FIO_BOTH)
#define pFIO_INEN ((volatile unsigned short *)FIO_INEN)
#define pFIO_FLAG_D ((volatile unsigned short *)FIO_FLAG_D)
#define pFIO_FLAG_T ((volatile unsigned short *)FIO_FLAG_T)
#define pFIO_MASKA_D ((volatile unsigned short *)FIO_MASKA_D)
#define pFIO_MASKA_T ((volatile unsigned short *)FIO_MASKA_T)
#define pFIO_MASKB_D ((volatile unsigned short *)FIO_MASKB_D)
#define pFIO_MASKB_T ((volatile unsigned short *)FIO_MASKB_T)
/* DMA Test Registers */
#define pDMA_CCOMP ((volatile unsigned long *)DMA_CCOMP)
#define pDMA_ACOMP ((volatile unsigned long *)DMA_ACOMP)
#define pDMA_MISR ((volatile unsigned long *)DMA_MISR)
#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER)
#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT)
#define pDMA_TMODE ((volatile unsigned short *)DMA_TMODE)
#define pDMA_TMCHAN ((volatile unsigned short *)DMA_TMCHAN)
#define pDMA_TMSTAT ((volatile unsigned short *)DMA_TMSTAT)
#define pDMA_TMBD ((volatile unsigned short *)DMA_TMBD)
#define pDMA_TMM0D ((volatile unsigned short *)DMA_TMM0D)
#define pDMA_TMM1D ((volatile unsigned short *)DMA_TMM1D)
#define pDMA_TMMA ((volatile void **)DMA_TMMA)
/* DMA Controller */
#define pDMA0_CONFIG ((volatile unsigned short *)DMA0_CONFIG)
#define pDMA0_NEXT_DESC_PTR ((volatile void **)DMA0_NEXT_DESC_PTR)
#define pDMA0_START_ADDR ((volatile void **)DMA0_START_ADDR)
#define pDMA0_X_COUNT ((volatile unsigned short *)DMA0_X_COUNT)
#define pDMA0_Y_COUNT ((volatile unsigned short *)DMA0_Y_COUNT)
#define pDMA0_X_MODIFY ((volatile signed short *)DMA0_X_MODIFY)
#define pDMA0_Y_MODIFY ((volatile signed short *)DMA0_Y_MODIFY)
#define pDMA0_CURR_DESC_PTR ((volatile void **)DMA0_CURR_DESC_PTR)
#define pDMA0_CURR_ADDR ((volatile void **)DMA0_CURR_ADDR)
#define pDMA0_CURR_X_COUNT ((volatile unsigned short *)DMA0_CURR_X_COUNT)
#define pDMA0_CURR_Y_COUNT ((volatile unsigned short *)DMA0_CURR_Y_COUNT)
#define pDMA0_IRQ_STATUS ((volatile unsigned short *)DMA0_IRQ_STATUS)
#define pDMA0_PERIPHERAL_MAP ((volatile unsigned short *)DMA0_PERIPHERAL_MAP)
#define pDMA1_CONFIG ((volatile unsigned short *)DMA1_CONFIG)
#define pDMA1_NEXT_DESC_PTR ((volatile void **)DMA1_NEXT_DESC_PTR)
#define pDMA1_START_ADDR ((volatile void **)DMA1_START_ADDR)
#define pDMA1_X_COUNT ((volatile unsigned short *)DMA1_X_COUNT)
#define pDMA1_Y_COUNT ((volatile unsigned short *)DMA1_Y_COUNT)
#define pDMA1_X_MODIFY ((volatile signed short *)DMA1_X_MODIFY)
#define pDMA1_Y_MODIFY ((volatile signed short *)DMA1_Y_MODIFY)
#define pDMA1_CURR_DESC_PTR ((volatile void **)DMA1_CURR_DESC_PTR)
#define pDMA1_CURR_ADDR ((volatile void **)DMA1_CURR_ADDR)
#define pDMA1_CURR_X_COUNT ((volatile unsigned short *)DMA1_CURR_X_COUNT)
#define pDMA1_CURR_Y_COUNT ((volatile unsigned short *)DMA1_CURR_Y_COUNT)
#define pDMA1_IRQ_STATUS ((volatile unsigned short *)DMA1_IRQ_STATUS)
#define pDMA1_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_PERIPHERAL_MAP)
#define pDMA2_CONFIG ((volatile unsigned short *)DMA2_CONFIG)
#define pDMA2_NEXT_DESC_PTR ((volatile void **)DMA2_NEXT_DESC_PTR)
#define pDMA2_START_ADDR ((volatile void **)DMA2_START_ADDR)
#define pDMA2_X_COUNT ((volatile unsigned short *)DMA2_X_COUNT)
#define pDMA2_Y_COUNT ((volatile unsigned short *)DMA2_Y_COUNT)
#define pDMA2_X_MODIFY ((volatile signed short *)DMA2_X_MODIFY)
#define pDMA2_Y_MODIFY ((volatile signed short *)DMA2_Y_MODIFY)
#define pDMA2_CURR_DESC_PTR ((volatile void **)DMA2_CURR_DESC_PTR)
#define pDMA2_CURR_ADDR ((volatile void **)DMA2_CURR_ADDR)
#define pDMA2_CURR_X_COUNT ((volatile unsigned short *)DMA2_CURR_X_COUNT)
#define pDMA2_CURR_Y_COUNT ((volatile unsigned short *)DMA2_CURR_Y_COUNT)
#define pDMA2_IRQ_STATUS ((volatile unsigned short *)DMA2_IRQ_STATUS)
#define pDMA2_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_PERIPHERAL_MAP)
#define pDMA3_CONFIG ((volatile unsigned short *)DMA3_CONFIG)
#define pDMA3_NEXT_DESC_PTR ((volatile void **)DMA3_NEXT_DESC_PTR)
#define pDMA3_START_ADDR ((volatile void **)DMA3_START_ADDR)
#define pDMA3_X_COUNT ((volatile unsigned short *)DMA3_X_COUNT)
#define pDMA3_Y_COUNT ((volatile unsigned short *)DMA3_Y_COUNT)
#define pDMA3_X_MODIFY ((volatile signed short *)DMA3_X_MODIFY)
#define pDMA3_Y_MODIFY ((volatile signed short *)DMA3_Y_MODIFY)
#define pDMA3_CURR_DESC_PTR ((volatile void **)DMA3_CURR_DESC_PTR)
#define pDMA3_CURR_ADDR ((volatile void **)DMA3_CURR_ADDR)
#define pDMA3_CURR_X_COUNT ((volatile unsigned short *)DMA3_CURR_X_COUNT)
#define pDMA3_CURR_Y_COUNT ((volatile unsigned short *)DMA3_CURR_Y_COUNT)
#define pDMA3_IRQ_STATUS ((volatile unsigned short *)DMA3_IRQ_STATUS)
#define pDMA3_PERIPHERAL_MAP ((volatile unsigned short *)DMA3_PERIPHERAL_MAP)
#define pDMA4_CONFIG ((volatile unsigned short *)DMA4_CONFIG)
#define pDMA4_NEXT_DESC_PTR ((volatile void **)DMA4_NEXT_DESC_PTR)
#define pDMA4_START_ADDR ((volatile void **)DMA4_START_ADDR)
#define pDMA4_X_COUNT ((volatile unsigned short *)DMA4_X_COUNT)
#define pDMA4_Y_COUNT ((volatile unsigned short *)DMA4_Y_COUNT)
#define pDMA4_X_MODIFY ((volatile signed short *)DMA4_X_MODIFY)
#define pDMA4_Y_MODIFY ((volatile signed short *)DMA4_Y_MODIFY)
#define pDMA4_CURR_DESC_PTR ((volatile void **)DMA4_CURR_DESC_PTR)
#define pDMA4_CURR_ADDR ((volatile void **)DMA4_CURR_ADDR)
#define pDMA4_CURR_X_COUNT ((volatile unsigned short *)DMA4_CURR_X_COUNT)
#define pDMA4_CURR_Y_COUNT ((volatile unsigned short *)DMA4_CURR_Y_COUNT)
#define pDMA4_IRQ_STATUS ((volatile unsigned short *)DMA4_IRQ_STATUS)
#define pDMA4_PERIPHERAL_MAP ((volatile unsigned short *)DMA4_PERIPHERAL_MAP)
#define pDMA5_CONFIG ((volatile unsigned short *)DMA5_CONFIG)
#define pDMA5_NEXT_DESC_PTR ((volatile void **)DMA5_NEXT_DESC_PTR)
#define pDMA5_START_ADDR ((volatile void **)DMA5_START_ADDR)
#define pDMA5_X_COUNT ((volatile unsigned short *)DMA5_X_COUNT)
#define pDMA5_Y_COUNT ((volatile unsigned short *)DMA5_Y_COUNT)
#define pDMA5_X_MODIFY ((volatile signed short *)DMA5_X_MODIFY)
#define pDMA5_Y_MODIFY ((volatile signed short *)DMA5_Y_MODIFY)
#define pDMA5_CURR_DESC_PTR ((volatile void **)DMA5_CURR_DESC_PTR)
#define pDMA5_CURR_ADDR ((volatile void **)DMA5_CURR_ADDR)
#define pDMA5_CURR_X_COUNT ((volatile unsigned short *)DMA5_CURR_X_COUNT)
#define pDMA5_CURR_Y_COUNT ((volatile unsigned short *)DMA5_CURR_Y_COUNT)
#define pDMA5_IRQ_STATUS ((volatile unsigned short *)DMA5_IRQ_STATUS)
#define pDMA5_PERIPHERAL_MAP ((volatile unsigned short *)DMA5_PERIPHERAL_MAP)
#define pDMA6_CONFIG ((volatile unsigned short *)DMA6_CONFIG)
#define pDMA6_NEXT_DESC_PTR ((volatile void **)DMA6_NEXT_DESC_PTR)
#define pDMA6_START_ADDR ((volatile void **)DMA6_START_ADDR)
#define pDMA6_X_COUNT ((volatile unsigned short *)DMA6_X_COUNT)
#define pDMA6_Y_COUNT ((volatile unsigned short *)DMA6_Y_COUNT)
#define pDMA6_X_MODIFY ((volatile signed short *)DMA6_X_MODIFY)
#define pDMA6_Y_MODIFY ((volatile signed short *)DMA6_Y_MODIFY)
#define pDMA6_CURR_DESC_PTR ((volatile void **)DMA6_CURR_DESC_PTR)
#define pDMA6_CURR_ADDR ((volatile void **)DMA6_CURR_ADDR)
#define pDMA6_CURR_X_COUNT ((volatile unsigned short *)DMA6_CURR_X_COUNT)
#define pDMA6_CURR_Y_COUNT ((volatile unsigned short *)DMA6_CURR_Y_COUNT)
#define pDMA6_IRQ_STATUS ((volatile unsigned short *)DMA6_IRQ_STATUS)
#define pDMA6_PERIPHERAL_MAP ((volatile unsigned short *)DMA6_PERIPHERAL_MAP)
#define pDMA7_CONFIG ((volatile unsigned short *)DMA7_CONFIG)
#define pDMA7_NEXT_DESC_PTR ((volatile void **)DMA7_NEXT_DESC_PTR)
#define pDMA7_START_ADDR ((volatile void **)DMA7_START_ADDR)
#define pDMA7_X_COUNT ((volatile unsigned short *)DMA7_X_COUNT)
#define pDMA7_Y_COUNT ((volatile unsigned short *)DMA7_Y_COUNT)
#define pDMA7_X_MODIFY ((volatile signed short *)DMA7_X_MODIFY)
#define pDMA7_Y_MODIFY ((volatile signed short *)DMA7_Y_MODIFY)
#define pDMA7_CURR_DESC_PTR ((volatile void **)DMA7_CURR_DESC_PTR)
#define pDMA7_CURR_ADDR ((volatile void **)DMA7_CURR_ADDR)
#define pDMA7_CURR_X_COUNT ((volatile unsigned short *)DMA7_CURR_X_COUNT)
#define pDMA7_CURR_Y_COUNT ((volatile unsigned short *)DMA7_CURR_Y_COUNT)
#define pDMA7_IRQ_STATUS ((volatile unsigned short *)DMA7_IRQ_STATUS)
#define pDMA7_PERIPHERAL_MAP ((volatile unsigned short *)DMA7_PERIPHERAL_MAP)
#define pMDMA_D1_CONFIG ((volatile unsigned short *)MDMA_D1_CONFIG)
#define pMDMA_D1_NEXT_DESC_PTR ((volatile void **)MDMA_D1_NEXT_DESC_PTR)
#define pMDMA_D1_START_ADDR ((volatile void **)MDMA_D1_START_ADDR)
#define pMDMA_D1_X_COUNT ((volatile unsigned short *)MDMA_D1_X_COUNT)
#define pMDMA_D1_Y_COUNT ((volatile unsigned short *)MDMA_D1_Y_COUNT)
#define pMDMA_D1_X_MODIFY ((volatile signed short *)MDMA_D1_X_MODIFY)
#define pMDMA_D1_Y_MODIFY ((volatile signed short *)MDMA_D1_Y_MODIFY)
#define pMDMA_D1_CURR_DESC_PTR ((volatile void **)MDMA_D1_CURR_DESC_PTR)
#define pMDMA_D1_CURR_ADDR ((volatile void **)MDMA_D1_CURR_ADDR)
#define pMDMA_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA_D1_CURR_X_COUNT)
#define pMDMA_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT)
#define pMDMA_D1_IRQ_STATUS ((volatile unsigned short *)MDMA_D1_IRQ_STATUS)
#define pMDMA_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP)
#define pMDMA_S1_CONFIG ((volatile unsigned short *)MDMA_S1_CONFIG)
#define pMDMA_S1_NEXT_DESC_PTR ((volatile void **)MDMA_S1_NEXT_DESC_PTR)
#define pMDMA_S1_START_ADDR ((volatile void **)MDMA_S1_START_ADDR)
#define pMDMA_S1_X_COUNT ((volatile unsigned short *)MDMA_S1_X_COUNT)
#define pMDMA_S1_Y_COUNT ((volatile unsigned short *)MDMA_S1_Y_COUNT)
#define pMDMA_S1_X_MODIFY ((volatile signed short *)MDMA_S1_X_MODIFY)
#define pMDMA_S1_Y_MODIFY ((volatile signed short *)MDMA_S1_Y_MODIFY)
#define pMDMA_S1_CURR_DESC_PTR ((volatile void **)MDMA_S1_CURR_DESC_PTR)
#define pMDMA_S1_CURR_ADDR ((volatile void **)MDMA_S1_CURR_ADDR)
#define pMDMA_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA_S1_CURR_X_COUNT)
#define pMDMA_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT)
#define pMDMA_S1_IRQ_STATUS ((volatile unsigned short *)MDMA_S1_IRQ_STATUS)
#define pMDMA_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP)
#define pMDMA_D0_CONFIG ((volatile unsigned short *)MDMA_D0_CONFIG)
#define pMDMA_D0_NEXT_DESC_PTR ((volatile void **)MDMA_D0_NEXT_DESC_PTR)
#define pMDMA_D0_START_ADDR ((volatile void **)MDMA_D0_START_ADDR)
#define pMDMA_D0_X_COUNT ((volatile unsigned short *)MDMA_D0_X_COUNT)
#define pMDMA_D0_Y_COUNT ((volatile unsigned short *)MDMA_D0_Y_COUNT)
#define pMDMA_D0_X_MODIFY ((volatile signed short *)MDMA_D0_X_MODIFY)
#define pMDMA_D0_Y_MODIFY ((volatile signed short *)MDMA_D0_Y_MODIFY)
#define pMDMA_D0_CURR_DESC_PTR ((volatile void **)MDMA_D0_CURR_DESC_PTR)
#define pMDMA_D0_CURR_ADDR ((volatile void **)MDMA_D0_CURR_ADDR)
#define pMDMA_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA_D0_CURR_X_COUNT)
#define pMDMA_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT)
#define pMDMA_D0_IRQ_STATUS ((volatile unsigned short *)MDMA_D0_IRQ_STATUS)
#define pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP)
#define pMDMA_S0_CONFIG ((volatile unsigned short *)MDMA_S0_CONFIG)
#define pMDMA_S0_NEXT_DESC_PTR ((volatile void **)MDMA_S0_NEXT_DESC_PTR)
#define pMDMA_S0_START_ADDR ((volatile void **)MDMA_S0_START_ADDR)
#define pMDMA_S0_X_COUNT ((volatile unsigned short *)MDMA_S0_X_COUNT)
#define pMDMA_S0_Y_COUNT ((volatile unsigned short *)MDMA_S0_Y_COUNT)
#define pMDMA_S0_X_MODIFY ((volatile signed short *)MDMA_S0_X_MODIFY)
#define pMDMA_S0_Y_MODIFY ((volatile signed short *)MDMA_S0_Y_MODIFY)
#define pMDMA_S0_CURR_DESC_PTR ((volatile void **)MDMA_S0_CURR_DESC_PTR)
#define pMDMA_S0_CURR_ADDR ((volatile void **)MDMA_S0_CURR_ADDR)
#define pMDMA_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA_S0_CURR_X_COUNT)
#define pMDMA_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT)
#define pMDMA_S0_IRQ_STATUS ((volatile unsigned short *)MDMA_S0_IRQ_STATUS)
#define pMDMA_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP)
/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */
#define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL)
#define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0)
#define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1)
/* System Bus Interface Unit (0xFFC0 4800-0xFFC0 4FFF) */
/* #define L1SBAR 0xFFC04840 */ /* L1 SRAM Base Address Register */
/* #define L1CSR 0xFFC04844 */ /* L1 SRAM Control Initialization Register */
/*
* #define pDB_ACOMP ((volatile void **)DB_ACOMP)
* #define pDB_CCOMP ((volatile unsigned long *)DB_CCOMP)
*/
/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */
#define pEBIU_SDGCTL ((volatile unsigned long *)EBIU_SDGCTL)
#define pEBIU_SDRRC ((volatile unsigned short *)EBIU_SDRRC)
#define pEBIU_SDSTAT ((volatile unsigned short *)EBIU_SDSTAT)
#define pEBIU_SDBCTL ((volatile unsigned short *)EBIU_SDBCTL)
/* UART Controller */
#define pUART_THR ((volatile unsigned short *)UART_THR)
#define pUART_RBR ((volatile unsigned short *)UART_RBR)
#define pUART_DLL ((volatile unsigned short *)UART_DLL)
#define pUART_IER ((volatile unsigned short *)UART_IER)
#define pUART_DLH ((volatile unsigned short *)UART_DLH)
#define pUART_IIR ((volatile unsigned short *)UART_IIR)
#define pUART_LCR ((volatile unsigned short *)UART_LCR)
#define pUART_MCR ((volatile unsigned short *)UART_MCR)
#define pUART_LSR ((volatile unsigned short *)UART_LSR)
/*
* #define UART_MSR
*/
#define pUART_SCR ((volatile unsigned short *)UART_SCR)
#define pUART_GCTL ((volatile unsigned short *)UART_GCTL)
/* SPI Controller */
#define pSPI_CTL ((volatile unsigned short *)SPI_CTL)
#define pSPI_FLG ((volatile unsigned short *)SPI_FLG)
#define pSPI_STAT ((volatile unsigned short *)SPI_STAT)
#define pSPI_TDBR ((volatile unsigned short *)SPI_TDBR)
#define pSPI_RDBR ((volatile unsigned short *)SPI_RDBR)
#define pSPI_BAUD ((volatile unsigned short *)SPI_BAUD)
#define pSPI_SHADOW ((volatile unsigned short *)SPI_SHADOW)
/* TIMER 0, 1, 2 Registers */
#define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG)
#define pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER)
#define pTIMER0_PERIOD ((volatile unsigned long *)TIMER0_PERIOD)
#define pTIMER0_WIDTH ((volatile unsigned long *)TIMER0_WIDTH)
#define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG)
#define pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER)
#define pTIMER1_PERIOD ((volatile unsigned long *)TIMER1_PERIOD)
#define pTIMER1_WIDTH ((volatile unsigned long *)TIMER1_WIDTH)
#define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG)
#define pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER)
#define pTIMER2_PERIOD ((volatile unsigned long *)TIMER2_PERIOD)
#define pTIMER2_WIDTH ((volatile unsigned long *)TIMER2_WIDTH)
#define pTIMER_ENABLE ((volatile unsigned short *)TIMER_ENABLE)
#define pTIMER_DISABLE ((volatile unsigned short *)TIMER_DISABLE)
#define pTIMER_STATUS ((volatile unsigned short *)TIMER_STATUS)
/* SPORT0 Controller */
#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1)
#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2)
#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV)
#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV)
#define pSPORT0_TX ((volatile long *)SPORT0_TX)
#define pSPORT0_RX ((volatile long *)SPORT0_RX)
#define pSPORT0_TX32 ((volatile long *)SPORT0_TX)
#define pSPORT0_RX32 ((volatile long *)SPORT0_RX)
#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX)
#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX)
#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1)
#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2)
#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV)
#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV)
#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT)
#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL)
#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1)
#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2)
#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0)
#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1)
#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2)
#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3)
#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0)
#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1)
#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2)
#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3)
/* SPORT1 Controller */
#define pSPORT1_TCR1 ((volatile unsigned short *)SPORT1_TCR1)
#define pSPORT1_TCR2 ((volatile unsigned short *)SPORT1_TCR2)
#define pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV)
#define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV)
#define pSPORT1_TX ((volatile long *)SPORT1_TX)
#define pSPORT1_RX ((volatile long *)SPORT1_RX)
#define pSPORT1_TX32 ((volatile long *)SPORT1_TX)
#define pSPORT1_RX32 ((volatile long *)SPORT1_RX)
#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX)
#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX)
#define pSPORT1_RCR1 ((volatile unsigned short *)SPORT1_RCR1)
#define pSPORT1_RCR2 ((volatile unsigned short *)SPORT1_RCR2)
#define pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV)
#define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV)
#define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT)
#define pSPORT1_CHNL ((volatile unsigned short *)SPORT1_CHNL)
#define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1)
#define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2)
#define pSPORT1_MTCS0 ((volatile unsigned long *)SPORT1_MTCS0)
#define pSPORT1_MTCS1 ((volatile unsigned long *)SPORT1_MTCS1)
#define pSPORT1_MTCS2 ((volatile unsigned long *)SPORT1_MTCS2)
#define pSPORT1_MTCS3 ((volatile unsigned long *)SPORT1_MTCS3)
#define pSPORT1_MRCS0 ((volatile unsigned long *)SPORT1_MRCS0)
#define pSPORT1_MRCS1 ((volatile unsigned long *)SPORT1_MRCS1)
#define pSPORT1_MRCS2 ((volatile unsigned long *)SPORT1_MRCS2)
#define pSPORT1_MRCS3 ((volatile unsigned long *)SPORT1_MRCS3)
/* Parallel Peripheral Interface (PPI) */
#define pPPI_CONTROL ((volatile unsigned short *)PPI_CONTROL)
#define pPPI_STATUS ((volatile unsigned short *)PPI_STATUS)
#define pPPI_DELAY ((volatile unsigned short *)PPI_DELAY)
#define pPPI_COUNT ((volatile unsigned short *)PPI_COUNT)
#define pPPI_FRAME ((volatile unsigned short *)PPI_FRAME)
#endif /* _CDEF_BF532_H */

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include/asm-blackfin/arch-bf533/cdefBF533.h
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/*
* cdefBF533.h
*
* This file is subject to the terms and conditions of the GNU Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Non-GPL License also available as part of VisualDSP++
*
* http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
*
* (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
*
* This file under source code control, please send bugs or changes to:
* dsptools.support@analog.com
*
*/
#ifndef _CDEFBF533_H
#define _CDEFBF533_H
#include <asm/arch-bf533/cdefBF532.h>
#endif /* _CDEFBF533_H */

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include/asm-blackfin/arch-bf533/defBF531.h
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/*
* defBF531.h
*
* This file is subject to the terms and conditions of the GNU Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Non-GPL License also available as part of VisualDSP++
*
* http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
*
* (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
*
* This file under source code control, please send bugs or changes to:
* dsptools.support@analog.com
*
*/
#ifndef _DEFBF531_H
#define _DEFBF531_H
#include <defBF532.h>
#endif /* _DEFBF531_H */

1159
include/asm-blackfin/arch-bf533/defBF532.h
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24
include/asm-blackfin/arch-bf533/defBF533.h
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/*
* defBF533.h
*
* This file is subject to the terms and conditions of the GNU Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Non-GPL License also available as part of VisualDSP++
*
* http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
*
* (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
*
* This file under source code control, please send bugs or changes to:
* dsptools.support@analog.com
*
*/
#ifndef _DEFBF533_H
#define _DEFBF533_H
#include <asm/cpu/defBF532.h>
#endif /* _DEFBF533_H */

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include/asm-blackfin/arch-bf533/defBF533_extn.h
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/*
* defBF533_extn.h
*
* This file is subject to the terms and conditions of the GNU Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Non-GPL License also available as part of VisualDSP++
*
* http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
*
* (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
*
* This file under source code control, please send bugs or changes to:
* dsptools.support@analog.com
*
*/
#ifndef _DEF_BF533_EXTN_H
#define _DEF_BF533_EXTN_H
/* define macro for offset */
#define OFFSET_( x ) ((x) & 0x0000FFFF)
/* Delay inserted for PLL transition */
#define PLL_DELAY 0x1000
#define L1_ISRAM 0xFFA00000
#define L1_ISRAM_END 0xFFA10000
#define DATA_BANKA_SRAM 0xFF800000
#define DATA_BANKA_SRAM_END 0xFF808000
#define DATA_BANKB_SRAM 0xFF900000
#define DATA_BANKB_SRAM_END 0xFF908000
#define SYSMMR_BASE 0xFFC00000
#define WDSIZE16 0x00000004
/* Event Vector Table Address */
#define EVT_EMULATION_ADDR 0xffe02000
#define EVT_RESET_ADDR 0xffe02004
#define EVT_NMI_ADDR 0xffe02008
#define EVT_EXCEPTION_ADDR 0xffe0200c
#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010
#define EVT_HARDWARE_ERROR_ADDR 0xffe02014
#define EVT_TIMER_ADDR 0xffe02018
#define EVT_IVG7_ADDR 0xffe0201c
#define EVT_IVG8_ADDR 0xffe02020
#define EVT_IVG9_ADDR 0xffe02024
#define EVT_IVG10_ADDR 0xffe02028
#define EVT_IVG11_ADDR 0xffe0202c
#define EVT_IVG12_ADDR 0xffe02030
#define EVT_IVG13_ADDR 0xffe02034
#define EVT_IVG14_ADDR 0xffe02038
#define EVT_IVG15_ADDR 0xffe0203c
#define EVT_OVERRIDE_ADDR 0xffe02100
/* IMASK Bit values */
#define IVG15_POS 0x00008000
#define IVG14_POS 0x00004000
#define IVG13_POS 0x00002000
#define IVG12_POS 0x00001000
#define IVG11_POS 0x00000800
#define IVG10_POS 0x00000400
#define IVG9_POS 0x00000200
#define IVG8_POS 0x00000100
#define IVG7_POS 0x00000080
#define IVGTMR_POS 0x00000040
#define IVGHW_POS 0x00000020
#define WDOG_TMR_DISABLE (0xAD << 4)
#define ICTL_RST 0x00000000
#define ICTL_NMI 0x00000002
#define ICTL_GP 0x00000004
#define ICTL_DISABLE 0x00000003
/* Watch Dog timer values setup */
#define WATCHDOG_DISABLE WDOG_TMR_DISABLE | ICTL_DISABLE
#endif /* _DEF_BF533_EXTN_H */

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include/asm-blackfin/arch-bf533/irq.h
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/*
* U-boot bf533_irq.h
*
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* This file is based on
* linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c
* Changed by HuTao Apr18, 2003
*
* Copyright was missing when I got the code so took from MIPS arch ...MaTed---
* Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
* Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle
*
* Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca>
* Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
* Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com>
*
* Adapted for BlackFin BF533 by Bas Vermeulen <bas@buyways.nl>
* Copyright (c) 2003 BuyWays B.V. (www.buyways.nl)
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BF533_IRQ_H_
#define _BF533_IRQ_H_
/*
* Interrupt source definitions
* Event Source Core Event Name Number
* EMU 0
* Reset RST 1
* NMI NMI 2
* Exception EVX 3
* Reserved -- 4
* Hardware Error IVHW 5
* Core Timer IVTMR 6
* PLL Wakeup Interrupt IVG7 7
* DMA Error (generic) IVG7 8
* PPI Error Interrupt IVG7 9
* SPORT0 Error Interrupt IVG7 10
* SPORT1 Error Interrupt IVG7 11
* SPI Error Interrupt IVG7 12
* UART Error Interrupt IVG7 13
* RTC Interrupt IVG8 14
* DMA0 Interrupt (PPI) IVG8 15
* DMA1 (SPORT0 RX) IVG9 16
* DMA2 (SPORT0 TX) IVG9 17
* DMA3 (SPORT1 RX) IVG9 18
* DMA4 (SPORT1 TX) IVG9 19
* DMA5 (PPI) IVG10 20
* DMA6 (UART RX) IVG10 21
* DMA7 (UART TX) IVG10 22
* Timer0 IVG11 23
* Timer1 IVG11 24
* Timer2 IVG11 25
* PF Interrupt A IVG12 26
* PF Interrupt B IVG12 27
* DMA8/9 Interrupt IVG13 28
* DMA10/11 Interrupt IVG13 29
* Watchdog Timer IVG13 30
* Software Interrupt 1 IVG14 31
* Software Interrupt 2 --
* (lowest priority) IVG15 32
*/
/* The ABSTRACT IRQ definitions */
/* The first seven of the following are fixed,
* the rest you change if you need to
*/
#define IRQ_EMU 0 /* Emulation */
#define IRQ_RST 1 /* reset */
#define IRQ_NMI 2 /* Non Maskable */
#define IRQ_EVX 3 /* Exception */
#define IRQ_UNUSED 4 /* - unused interrupt */
#define IRQ_HWERR 5 /* Hardware Error */
#define IRQ_CORETMR 6 /* Core timer */
#define IRQ_PLL_WAKEUP 7 /* PLL Wakeup Interrupt */
#define IRQ_DMA_ERROR 8 /* DMA Error (general) */
#define IRQ_PPI_ERROR 9 /* PPI Error Interrupt */
#define IRQ_SPORT0_ERROR 10 /* SPORT0 Error Interrupt */
#define IRQ_SPORT1_ERROR 11 /* SPORT1 Error Interrupt */
#define IRQ_SPI_ERROR 12 /* SPI Error Interrupt */
#define IRQ_UART_ERROR 13 /* UART Error Interrupt */
#define IRQ_RTC 14 /* RTC Interrupt */
#define IRQ_PPI 15 /* DMA0 Interrupt (PPI) */
#define IRQ_SPORT0 16 /* DMA1 Interrupt (SPORT0 RX) */
#define IRQ_SPARE1 17 /* DMA2 Interrupt (SPORT0 TX) */
#define IRQ_SPORT1 18 /* DMA3 Interrupt (SPORT1 RX) */
#define IRQ_SPARE2 19 /* DMA4 Interrupt (SPORT1 TX) */
#define IRQ_SPI 20 /* DMA5 Interrupt (SPI) */
#define IRQ_UART 21 /* DMA6 Interrupt (UART RX) */
#define IRQ_SPARE3 22 /* DMA7 Interrupt (UART TX) */
#define IRQ_TMR0 23 /* Timer 0 */
#define IRQ_TMR1 24 /* Timer 1 */
#define IRQ_TMR2 25 /* Timer 2 */
#define IRQ_PROG_INTA 26 /* Programmable Flags A (8) */
#define IRQ_PROG_INTB 27 /* Programmable Flags B (8) */
#define IRQ_MEM_DMA0 28 /* DMA8/9 Interrupt (Memory DMA Stream 0) */
#define IRQ_MEM_DMA1 29 /* DMA10/11 Interrupt (Memory DMA Stream 1) */
#define IRQ_WATCH 30 /* Watch Dog Timer */
#define IRQ_SW_INT1 31 /* Software Int 1 */
#define IRQ_SW_INT2 32 /* Software Int 2 (reserved for SYSCALL) */
#define IRQ_UART_RX_BIT 0x4000
#define IRQ_UART_TX_BIT 0x8000
#define IRQ_UART_ERROR_BIT 0x40
#define IVG7 7
#define IVG8 8
#define IVG9 9
#define IVG10 10
#define IVG11 11
#define IVG12 12
#define IVG13 13
#define IVG14 14
#define IVG15 15
#define SYS_IRQS 33
#endif

116
include/asm-blackfin/arch-bf537/anomaly.h
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/*
* File: include/asm-blackfin/arch-bf537/anomaly.h
* Based on:
* Author:
*
* Created:
* Description:
*
* Rev:
*
* Modified:
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING.
* If not, write to the Free Software Foundation,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/* This file shoule be up to date with:
* - Revision J, June 1, 2006; ADSP-BF537 Blackfin Processor Anomaly List
* - Revision I, June 1, 2006; ADSP-BF536 Blackfin Processor Anomaly List
* - Revision J, June 1, 2006; ADSP-BF534 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_
/* We do not support 0.1 silicon - sorry */
#if (defined(CONFIG_BF_REV_0_1))
#error Kernel will not work on BF537/6/4 Version 0.1
#endif
#if (defined(CONFIG_BF_REV_0_3) || defined(CONFIG_BF_REV_0_2))
#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
slot1 and store of a P register in slot 2 is not
supported */
#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
Channel DMA stops */
#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
registers. */
#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
upper bits */
#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
syncs */
#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
#define ANOMALY_05000247 /* CLKIN Buffer Output Enable Reset Behavior Is
Changed */
#endif
#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
SPORT external receive and transmit clocks. */
#define ANOMALY_05000272 /* Certain data cache write through modes fail for
VDDint <=0.9V */
#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
an edge is detected may clear interrupt */
#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
not restored */
#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
control */
#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
killed in a particular stage */
#endif
#if defined(CONFIG_BF_REV_0_2)
#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
IDLE around a Change of Control causes
unpredictable results */
#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
(TDM) */
#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
#define ANOMALY_05000252 /* EMAC Tx DMA error after an early frame abort */
#endif
#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
interrupt not functional */
#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
#define ANOMALY_05000256 /* EMAC MDIO input latched on wrong MDC edge */
#endif
#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
loops may cause the instruction fetch unit to
malfunction */
#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
the ICPLB Data registers differ */
#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
#define ANOMALY_05000262 /* Stores to data cache may be lost */
#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
instruction will cause an infinite stall in the
second to last instruction in a hardware loop */
#define ANOMALY_05000268 /* Memory DMA error when peripheral DMA is running
and non-zero DEB_TRAFFIC_PERIOD value */
#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
internal voltage regulator (VDDint) to decrease */
#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
an edge is detected may clear interrupt */
#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
DMA system instability */
#define ANOMALY_05000280 /* SPI Master boot mode does not work well with
Atmel Dataflash devices */
#endif /* CONFIG_BF_REV_0_2 */
#endif /* _MACH_ANOMALY_H_ */

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include/asm-blackfin/arch-bf537/bf537_serial.h
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/*
* U-boot bf537_serial.h
*
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BF537_SERIAL_H_
#define _BF537_SERIAL_H_
#define BYTE_REF(addr) (*((volatile char*)addr))
#define HALFWORD_REF(addr) (*((volatile short*)addr))
#define WORD_REF(addr) (*((volatile long*)addr))
#define UART_THR_LO HALFWORD_REF(UART_THR)
#define UART_RBR_LO HALFWORD_REF(UART_RBR)
#define UART_DLL_LO HALFWORD_REF(UART_DLL)
#define UART_IER_LO HALFWORD_REF(UART_IER)
#define UART_IER_ERBFI 0x01
#define UART_IER_ETBEI 0x02
#define UART_IER_ELSI 0x04
#define UART_IER_EDDSI 0x08
#define UART_DLH_LO HALFWORD_REF(UART_DLH)
#define UART_IIR_LO HALFWORD_REF(UART_IIR)
#define UART_IIR_NOINT 0x01
#define UART_IIR_STATUS 0x06
#define UART_IIR_LSR 0x06
#define UART_IIR_RBR 0x04
#define UART_IIR_THR 0x02
#define UART_IIR_MSR 0x00
#define UART_LCR_LO HALFWORD_REF(UART_LCR)
#define UART_LCR_WLS5 0
#define UART_LCR_WLS6 0x01
#define UART_LCR_WLS7 0x02
#define UART_LCR_WLS8 0x03
#define UART_LCR_STB 0x04
#define UART_LCR_PEN 0x08
#define UART_LCR_EPS 0x10
#define UART_LCR_SP 0x20
#define UART_LCR_SB 0x40
#define UART_LCR_DLAB 0x80
#define UART_MCR_LO HALFWORD_REF(UART_MCR)
#define UART_LSR_LO HALFWORD_REF(UART_LSR)
#define UART_LSR_DR 0x01
#define UART_LSR_OE 0x02
#define UART_LSR_PE 0x04
#define UART_LSR_FE 0x08
#define UART_LSR_BI 0x10
#define UART_LSR_THRE 0x20
#define UART_LSR_TEMT 0x40
#define UART_MSR_LO HALFWORD_REF(UART_MSR)
#define UART_SCR_LO HALFWORD_REF(UART_SCR)
#define UART_GCTL_LO HALFWORD_REF(UART_GCTL)
#define UART_GCTL_UCEN 0x01
#endif

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include/asm-blackfin/arch-bf537/bf5xx_rtc.h
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/*
* U-boot - bf537_rtc.h
*
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BF537_RTC_H_
#define _BF537_RTC_H_
void rtc_init(void);
void wait_for_complete(void);
void rtc_reset(void);
#define MIN_TO_SECS(_x_) (60 * _x_)
#define HRS_TO_SECS(_x_) (60 * 60 * _x_)
#define DAYS_TO_SECS(_x_) (24 * 60 * 60 * _x_)
#define NUM_SECS_IN_DAY (24 * 3600)
#define NUM_SECS_IN_HOUR (3600)
#define NUM_SECS_IN_MIN (60)
/* Shift values for RTC_STAT register */
#define DAY_BITS_OFF 17
#define HOUR_BITS_OFF 12
#define MIN_BITS_OFF 6
#define SEC_BITS_OFF 0
#endif

1009
include/asm-blackfin/arch-bf537/cdefBF534.h
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include/asm-blackfin/arch-bf537/cdefBF537.h
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/*
* Copyright (C) 2004 Analog Devices Inc., All Rights Reserved.
*
***********************************************************************************
*
* This include file contains a list of macro "defines" to enable the programmer
* to use symbolic names for register-access.
*
* ----------------------------
* revision 0.1
* date: 2004/03/01 21:23:01; author: joeb
* Initial revision
*
* ----------------------------
* revision 0.2
* date: 2004/05/15 16:30:00; author: joeb
* comments: removed I2C/IIC references to TWI, changed GPIO sections
*
* ----------------------------
* revision 0.3
* date: 2004/06/08 12:25:00; author: joeb
* comments: renamed some TWI and GPIO registers
*
* ----------------------------
* revision 0.4
* date: 2004/06/09 14:25:00; author: joeb
* comments: changed Timer status register to 32-bit, renamed EMAC count registers
*
* ----------------------------
* revision 0.5
* date: 2004/08/10 10:25:00; author: joeb
* comments: Renamed EMAC wake-up registers, changed bit-names in EMAC registers
*
* ----------------------------
* revision 0.6
* date: 2004/08/17 16:25:00; author: joeb
* comments: Renamed TWI_INT_ENABLE to TWI_INT_MASK
*
* ----------------------------
* revision 0.7
* date: 2004/08/18 13:21:00; author: joeb
* comments: Renamed GPIO registers to remove _D, _S, _C, _T suffixes
*
* ----------------------------
* revision 0.8
* date: 2004/08/20 10:27:00; author: joeb
* comments: Renamed External DMA to Handshake DMA
*
* ----------------------------
* revision 0.9
* date: 2004/08/23 13:42:00; author: joeb
* comments: Renamed Handshake DMA Register Set
*
* ----------------------------
* revision 0.10
* date: 2004/10/28 15:40:00; author: joeb
* comments: Shortened EMAC Count Register Names
*
* ----------------------------
* revision 0.11
* date: 2004/12/13 11:05:00; author: joeb
* comments: Fixed address pointers - (volatile void **) to (void * volatile *)
*
* ----------------------------
* revision 0.12
* date: 2004/12/17 14:25:00; author: joeb
* comments: Replaced C++ Single-Line Comments w/C-standard Comments
* Changed EMAC EQ1024 TX/RX References to GE1024
*
* ----------------------------
* revision 0.13
* date: 2005/01/05 10:50:00; author: joeb
* comments: Removed excess white space in CAN_AM section
* Added support for CAN Macros to Index AM and Mailbox Areas
*
* ----------------------------
* revision 0.14
* date: 2005/01/26 14:10:00; author: joeb
* comments: Fixed Typo In EMAC_RXC_PAUSE register
*
* ----------------------------
* revision 0.15
* date: 2005/01/27 14:41:00; author: joeb
* comments: Moved Common MMRs to cdefBF534.h
*/
/*
* System MMR Register Map
*/
#ifndef _CDEF_BF537_H
#define _CDEF_BF537_H
/* Include MMRs Common to BF534 */
#include <asm/arch-bf537/cdefBF534.h>
/* Include all Core registers and bit definitions */
#include <asm/arch-bf537/defBF537.h>
/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */
/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
#define pEMAC_OPMODE ((volatile unsigned long *)EMAC_OPMODE)
#define pEMAC_ADDRLO ((volatile unsigned long *)EMAC_ADDRLO)
#define pEMAC_ADDRHI ((volatile unsigned long *)EMAC_ADDRHI)
#define pEMAC_HASHLO ((volatile unsigned long *)EMAC_HASHLO)
#define pEMAC_HASHHI ((volatile unsigned long *)EMAC_HASHHI)
#define pEMAC_STAADD ((volatile unsigned long *)EMAC_STAADD)
#define pEMAC_STADAT ((volatile unsigned long *)EMAC_STADAT)
#define pEMAC_FLC ((volatile unsigned long *)EMAC_FLC)
#define pEMAC_VLAN1 ((volatile unsigned long *)EMAC_VLAN1)
#define pEMAC_VLAN2 ((volatile unsigned long *)EMAC_VLAN2)
#define pEMAC_WKUP_CTL ((volatile unsigned long *)EMAC_WKUP_CTL)
#define pEMAC_WKUP_FFMSK0 ((volatile unsigned long *)EMAC_WKUP_FFMSK0)
#define pEMAC_WKUP_FFMSK1 ((volatile unsigned long *)EMAC_WKUP_FFMSK1)
#define pEMAC_WKUP_FFMSK2 ((volatile unsigned long *)EMAC_WKUP_FFMSK2)
#define pEMAC_WKUP_FFMSK3 ((volatile unsigned long *)EMAC_WKUP_FFMSK3)
#define pEMAC_WKUP_FFCMD ((volatile unsigned long *)EMAC_WKUP_FFCMD)
#define pEMAC_WKUP_FFOFF ((volatile unsigned long *)EMAC_WKUP_FFOFF)
#define pEMAC_WKUP_FFCRC0 ((volatile unsigned long *)EMAC_WKUP_FFCRC0)
#define pEMAC_WKUP_FFCRC1 ((volatile unsigned long *)EMAC_WKUP_FFCRC1)
#define pEMAC_SYSCTL ((volatile unsigned long *)EMAC_SYSCTL)
#define pEMAC_SYSTAT ((volatile unsigned long *)EMAC_SYSTAT)
#define pEMAC_RX_STAT ((volatile unsigned long *)EMAC_RX_STAT)
#define pEMAC_RX_STKY ((volatile unsigned long *)EMAC_RX_STKY)
#define pEMAC_RX_IRQE ((volatile unsigned long *)EMAC_RX_IRQE)
#define pEMAC_TX_STAT ((volatile unsigned long *)EMAC_TX_STAT)
#define pEMAC_TX_STKY ((volatile unsigned long *)EMAC_TX_STKY)
#define pEMAC_TX_IRQE ((volatile unsigned long *)EMAC_TX_IRQE)
#define pEMAC_MMC_CTL ((volatile unsigned long *)EMAC_MMC_CTL)
#define pEMAC_MMC_RIRQS ((volatile unsigned long *)EMAC_MMC_RIRQS)
#define pEMAC_MMC_RIRQE ((volatile unsigned long *)EMAC_MMC_RIRQE)
#define pEMAC_MMC_TIRQS ((volatile unsigned long *)EMAC_MMC_TIRQS)
#define pEMAC_MMC_TIRQE ((volatile unsigned long *)EMAC_MMC_TIRQE)
#define pEMAC_RXC_OK ((volatile unsigned long *)EMAC_RXC_OK)
#define pEMAC_RXC_FCS ((volatile unsigned long *)EMAC_RXC_FCS)
#define pEMAC_RXC_ALIGN ((volatile unsigned long *)EMAC_RXC_ALIGN)
#define pEMAC_RXC_OCTET ((volatile unsigned long *)EMAC_RXC_OCTET)
#define pEMAC_RXC_DMAOVF ((volatile unsigned long *)EMAC_RXC_DMAOVF)
#define pEMAC_RXC_UNICST ((volatile unsigned long *)EMAC_RXC_UNICST)
#define pEMAC_RXC_MULTI ((volatile unsigned long *)EMAC_RXC_MULTI)
#define pEMAC_RXC_BROAD ((volatile unsigned long *)EMAC_RXC_BROAD)
#define pEMAC_RXC_LNERRI ((volatile unsigned long *)EMAC_RXC_LNERRI)
#define pEMAC_RXC_LNERRO ((volatile unsigned long *)EMAC_RXC_LNERRO)
#define pEMAC_RXC_LONG ((volatile unsigned long *)EMAC_RXC_LONG)
#define pEMAC_RXC_MACCTL ((volatile unsigned long *)EMAC_RXC_MACCTL)
#define pEMAC_RXC_OPCODE ((volatile unsigned long *)EMAC_RXC_OPCODE)
#define pEMAC_RXC_PAUSE ((volatile unsigned long *)EMAC_RXC_PAUSE)
#define pEMAC_RXC_ALLFRM ((volatile unsigned long *)EMAC_RXC_ALLFRM)
#define pEMAC_RXC_ALLOCT ((volatile unsigned long *)EMAC_RXC_ALLOCT)
#define pEMAC_RXC_TYPED ((volatile unsigned long *)EMAC_RXC_TYPED)
#define pEMAC_RXC_SHORT ((volatile unsigned long *)EMAC_RXC_SHORT)
#define pEMAC_RXC_EQ64 ((volatile unsigned long *)EMAC_RXC_EQ64)
#define pEMAC_RXC_LT128 ((volatile unsigned long *)EMAC_RXC_LT128)
#define pEMAC_RXC_LT256 ((volatile unsigned long *)EMAC_RXC_LT256)
#define pEMAC_RXC_LT512 ((volatile unsigned long *)EMAC_RXC_LT512)
#define pEMAC_RXC_LT1024 ((volatile unsigned long *)EMAC_RXC_LT1024)
#define pEMAC_RXC_GE1024 ((volatile unsigned long *)EMAC_RXC_GE1024)
#define pEMAC_TXC_OK ((volatile unsigned long *)EMAC_TXC_OK)
#define pEMAC_TXC_1COL ((volatile unsigned long *)EMAC_TXC_1COL)
#define pEMAC_TXC_GT1COL ((volatile unsigned long *)EMAC_TXC_GT1COL)
#define pEMAC_TXC_OCTET ((volatile unsigned long *)EMAC_TXC_OCTET)
#define pEMAC_TXC_DEFER ((volatile unsigned long *)EMAC_TXC_DEFER)
#define pEMAC_TXC_LATECL ((volatile unsigned long *)EMAC_TXC_LATECL)
#define pEMAC_TXC_XS_COL ((volatile unsigned long *)EMAC_TXC_XS_COL)
#define pEMAC_TXC_DMAUND ((volatile unsigned long *)EMAC_TXC_DMAUND)
#define pEMAC_TXC_CRSERR ((volatile unsigned long *)EMAC_TXC_CRSERR)
#define pEMAC_TXC_UNICST ((volatile unsigned long *)EMAC_TXC_UNICST)
#define pEMAC_TXC_MULTI ((volatile unsigned long *)EMAC_TXC_MULTI)
#define pEMAC_TXC_BROAD ((volatile unsigned long *)EMAC_TXC_BROAD)
#define pEMAC_TXC_XS_DFR ((volatile unsigned long *)EMAC_TXC_XS_DFR)
#define pEMAC_TXC_MACCTL ((volatile unsigned long *)EMAC_TXC_MACCTL)
#define pEMAC_TXC_ALLFRM ((volatile unsigned long *)EMAC_TXC_ALLFRM)
#define pEMAC_TXC_ALLOCT ((volatile unsigned long *)EMAC_TXC_ALLOCT)
#define pEMAC_TXC_EQ64 ((volatile unsigned long *)EMAC_TXC_EQ64)
#define pEMAC_TXC_LT128 ((volatile unsigned long *)EMAC_TXC_LT128)
#define pEMAC_TXC_LT256 ((volatile unsigned long *)EMAC_TXC_LT256)
#define pEMAC_TXC_LT512 ((volatile unsigned long *)EMAC_TXC_LT512)
#define pEMAC_TXC_LT1024 ((volatile unsigned long *)EMAC_TXC_LT1024)
#define pEMAC_TXC_GE1024 ((volatile unsigned long *)EMAC_TXC_GE1024)
#define pEMAC_TXC_ABORT ((volatile unsigned long *)EMAC_TXC_ABORT)
#endif /* _CDEF_BF537_H */

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include/asm-blackfin/arch-bf537/defBF534.h
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include/asm-blackfin/arch-bf537/defBF537.h
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/*
* Copyright (C) 2004-2005 Analog Devices Inc., All Rights Reserved.
*
***********************************************************************************
*
* This include file contains a list of macro "defines" to enable the programmer
* to use symbolic names for register-access and bit-manipulation.
*
* ----------------------------
* revision 0.1
* date: 2004/03/01 21:23:01; author: joeb
* Initial revision
*
* ----------------------------
* revision 0.2
* date: 2004/05/15 16:30:00; author: joeb
* comments: removed I2C/IIC references, changed GPIO sections
*
* ----------------------------
* revision 0.3
* date: 2004/06/08 12:25:00; author: joeb
* comments: fixed mis-mapped TIMER registers, changed TWI register names, fixed
* FLAG references in GPIO register names
*
* ----------------------------
* revision 0.4
* date: 2004/06/09 2:25:00; author: joeb
* comments: fixed bit-defines for EMAC section, renamed EMAC count registers,
* combined 2 Timer status registers into one
*
* ----------------------------
* revision 0.5
* date: 2004/08/10 10:25:00; author: joeb
* comments: Renamed EMAC wake-up registers, changed bit-names in EMAC registers
*
* ----------------------------
* revision 0.6
* date: 2004/08/17 16:25:00; author: joeb
* comments: Renamed TWI_INT_ENABLE to TWI_INT_MASK
*
* ----------------------------
* revision 0.7
* date: 2004/08/18 13:21:00; author: joeb
* comments: Renamed GPIO registers to remove _D, _S, _C, _T suffixes
*
* ----------------------------
* revision 0.8
* date: 2004/08/20 10:24:00; author: joeb
* comments: Renamed External DMA to Handshake MDMA
*
* ----------------------------
* revision 0.9
* date: 2004/08/23 13:42:00; author: joeb
* comments: Renamed Handshake DMA Register Set
*
* ----------------------------
* revision 0.10
* date: 2004/09/07 11:21:00; author: joeb
* comments: Fixed EMAC TX/RX DMA Priority (DMA and SIC Bit Names)
*
* ----------------------------
* revision 0.11
* date: 2004/09/28 15:14:00; author: joeb
* comments: Fixed CAN Mailbox Area
*
* ----------------------------
* revision 0.12
* date: 2004/10/27 13:18:00; author: joeb
* comments: Added IEEE EMAC Register Support
*
* ----------------------------
* revision 0.13
* date: 2004/10/28 15:40:00; author: joeb
* comments: Shortened EMAC Count Register Names
*
* ----------------------------
* revision 0.14
* date: 2004/11/09 10:45:00; author: joeb
* comments: Fixed WDSIZE macros
*
* ----------------------------
* revision 0.15
* date: 2004/11/18 07:45:00; author: joeb
* comments: Fixed TIMER_STATUS register, added EMAC macros
*
* ----------------------------
* revision 0.16
* date: 2004/12/13 11:05:00; author: joeb
* comments: Removed HI/LO macros (now Assembler mnemonics)
* Renamed enable bit for HMDMA from EN to HMDMAEN
*
* ----------------------------
* revision 0.17
* date: 2004/12/17 14:25:00; author: joeb
* comments: Replaced C++ Single-Line Comments w/C-standard Comments
* Changed EMAC EQ1024 TX/RX References to GE1024
*
* ----------------------------
* revision 0.18
* date: 2005/01/05 10:50:00; author: joeb
* comments: Added CAN Macros To Index Mailbox Area and Acceptance Masks
* Added mask values for field deposit protection
*
* ----------------------------
* revision 0.19
* date: 2005/01/10 10:30:00; author: joeb
* comments: Made all Macro argument syntax compliant to MISRA-C 2004 rule 19.10.
*
* ----------------------------
* revision 0.20
* date: 2005/01/27 14:25:15; author: joeb
* comments: Moved MMRs common to BF534 to BF534 header.
*/
#ifndef _DEF_BF537_H
#define _DEF_BF537_H
/* Include all Core registers and bit definitions */
#include <asm/arch-common/def_LPBlackfin.h>
/* Include all MMR and bit defines common to BF534 */
#include <asm/arch-bf537/defBF534.h>
/*
* Define EMAC Section Unique to BF536/BF537
*/
/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */
#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
/* Listing for IEEE-Supported Count Registers */
#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 <= x < 128 */
#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
/*
* System MMR Register Bits And Macros
*
* Disclaimer: All macros are intended to make C and Assembly code more readable.
* Use these macros carefully, as any that do left shifts for field
* depositing will result in the lower order bits being destroyed. Any
* macro that shifts left to properly position the bit-field should be
* used as part of an OR to initialize a register and NOT as a dynamic
* modifier UNLESS the lower order bits are saved and ORed back in when
* the macro is used.
*/
/*
* ETHERNET 10/100 CONTROLLER MASKS
*/
/* EMAC_OPMODE Masks */
#define RE 0x00000001 /* Receiver Enable */
#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
#define HU 0x00000010 /* Hash Filter Unicast Address */
#define HM 0x00000020 /* Hash Filter Multicast Address */
#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
#define PR 0x00000080 /* Promiscuous Mode Enable */
#define IFE 0x00000100 /* Inverse Filtering Enable */
#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
#define PBF 0x00000400 /* Pass Bad Frames Enable */
#define PSF 0x00000800 /* Pass Short Frames Enable */
#define RAF 0x00001000 /* Receive-All Mode */
#define TE 0x00010000 /* Transmitter Enable */
#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
#define DC 0x00080000 /* Deferral Check */
#define BOLMT 0x00300000 /* Back-Off Limit */
#define BOLMT_10 0x00000000 /* 10-bit range */
#define BOLMT_8 0x00100000 /* 8-bit range */
#define BOLMT_4 0x00200000 /* 4-bit range */
#define BOLMT_1 0x00300000 /* 1-bit range */
#define DRTY 0x00400000 /* Disable TX Retry On Collision */
#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
#define RMII 0x01000000 /* RMII/MII* Mode */
#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
#define LB 0x08000000 /* Internal Loopback Enable */
#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
/* EMAC_STAADD Masks */
#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
#define STADISPRE 0x00000004 /* Disable Preamble Generation */
#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
#define REGAD 0x000007C0 /* STA Register Address */
#define PHYAD 0x0000F800 /* PHY Device Address */
#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
/* EMAC_STADAT Mask */
#define STADATA 0x0000FFFF /* Station Management Data */
/* EMAC_FLC Masks */
#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
#define FLCE 0x00000002 /* Flow Control Enable */
#define PCF 0x00000004 /* Pass Control Frames */
#define BKPRSEN 0x00000008 /* Enable Backpressure */
#define FLCPAUSE 0xFFFF0000 /* Pause Time */
#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
/* EMAC_WKUP_CTL Masks */
#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
#define MPKE 0x00000002 /* Magic Packet Enable */
#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
#define MPKS 0x00000020 /* Magic Packet Received Status */
#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
/* EMAC_WKUP_FFCMD Masks */
#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
/* EMAC_WKUP_FFOFF Masks */
#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
/* Set ALL Offsets */
#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
/* EMAC_WKUP_FFCRC0 Masks */
#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0) /* Set Wake-Up Filter 0 Target CRC */
#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16) /* Set Wake-Up Filter 1 Target CRC */
/* EMAC_WKUP_FFCRC1 Masks */
#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0) /* Set Wake-Up Filter 2 Target CRC */
#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16) /* Set Wake-Up Filter 3 Target CRC */
/* EMAC_SYSCTL Masks */
#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
/* EMAC_SYSTAT Masks */
#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
#define RX_COMP 0x00001000 /* RX Frame Complete */
#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
#define RX_CRC 0x00010000 /* RX Frame CRC Error */
#define RX_LEN 0x00020000 /* RX Frame Length Error */
#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
#define RX_PHY 0x00200000 /* RX Frame PHY Error */
#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
#define TX_COMP 0x00000001 /* TX Frame Complete */
#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
/* EMAC_MMC_CTL Masks */
#define RSTC 0x00000001 /* Reset All Counters */
#define CROLL 0x00000002 /* Counter Roll-Over Enable */
#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
#define MMCE 0x00000008 /* Enable MMC Counter Operation */
/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
#endif /* _DEF_BF537_H */

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/*
* defBF537_extn.h
*
* This file is subject to the terms and conditions of the GNU Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Non-GPL License also available as part of VisualDSP++
*
* http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
*
* (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
*
* This file under source code control, please send bugs or changes to:
* dsptools.support@analog.com
*
*/
#ifndef _DEF_BF537_EXTN_H
#define _DEF_BF537_EXTN_H
#define OFFSET_( x ) ((x) & 0x0000FFFF) /* define macro for offset */
/* Delay inserted for PLL transition */
#define PLL_DELAY 0x1000
#define L1_ISRAM 0xFFA00000
#define L1_ISRAM_END 0xFFA10000
#define DATA_BANKA_SRAM 0xFF800000
#define DATA_BANKA_SRAM_END 0xFF808000
#define DATA_BANKB_SRAM 0xFF900000
#define DATA_BANKB_SRAM_END 0xFF908000
#define SYSMMR_BASE 0xFFC00000
#define WDSIZE16 0x00000004
/* Event Vector Table Address */
#define EVT_EMULATION_ADDR 0xffe02000
#define EVT_RESET_ADDR 0xffe02004
#define EVT_NMI_ADDR 0xffe02008
#define EVT_EXCEPTION_ADDR 0xffe0200c
#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010
#define EVT_HARDWARE_ERROR_ADDR 0xffe02014
#define EVT_TIMER_ADDR 0xffe02018
#define EVT_IVG7_ADDR 0xffe0201c
#define EVT_IVG8_ADDR 0xffe02020
#define EVT_IVG9_ADDR 0xffe02024
#define EVT_IVG10_ADDR 0xffe02028
#define EVT_IVG11_ADDR 0xffe0202c
#define EVT_IVG12_ADDR 0xffe02030
#define EVT_IVG13_ADDR 0xffe02034
#define EVT_IVG14_ADDR 0xffe02038
#define EVT_IVG15_ADDR 0xffe0203c
#define EVT_OVERRIDE_ADDR 0xffe02100
/* IMASK Bit values */
#define IVG15_POS 0x00008000
#define IVG14_POS 0x00004000
#define IVG13_POS 0x00002000
#define IVG12_POS 0x00001000
#define IVG11_POS 0x00000800
#define IVG10_POS 0x00000400
#define IVG9_POS 0x00000200
#define IVG8_POS 0x00000100
#define IVG7_POS 0x00000080
#define IVGTMR_POS 0x00000040
#define IVGHW_POS 0x00000020
#define WDOG_TMR_DISABLE (0xAD << 4)
#define ICTL_RST 0x00000000
#define ICTL_NMI 0x00000002
#define ICTL_GP 0x00000004
#define ICTL_DISABLE 0x00000003
/* Watch Dog timer values setup */
#define WATCHDOG_DISABLE WDOG_TMR_DISABLE | ICTL_DISABLE
#endif /* _DEF_BF537_EXTN_H */

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include/asm-blackfin/arch-bf537/irq.h
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/*
* U-boot bf537_irq.h
*
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* This file is based on
* linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c
* Changed by HuTao Apr18, 2003
*
* Copyright was missing when I got the code so took from MIPS arch ...MaTed---
* Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
* Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle
*
* Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca>
* Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
* Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com>
*
* Adapted for BlackFin BF537 by Bas Vermeulen <bas@buyways.nl>
* Copyright (c) 2003 BuyWays B.V. (www.buyways.nl)
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BF537_IRQ_H_
#define _BF537_IRQ_H_
/*
* Interrupt source definitions
* Event Source Core Event Name Number
* EMU 0
* Reset RST 1
* NMI NMI 2
* Exception EVX 3
* Reserved -- 4
* Hardware Error IVHW 5
* Core Timer IVTMR 6
* PLL Wakeup Interrupt IVG7 7
* DMA Error (generic) IVG7 8
* PPI Error Interrupt IVG7 9
* SPORT0 Error Interrupt IVG7 10
* SPORT1 Error Interrupt IVG7 11
* SPI Error Interrupt IVG7 12
* UART Error Interrupt IVG7 13
* RTC Interrupt IVG8 14
* DMA0 Interrupt (PPI) IVG8 15
* DMA1 (SPORT0 RX) IVG9 16
* DMA2 (SPORT0 TX) IVG9 17
* DMA3 (SPORT1 RX) IVG9 18
* DMA4 (SPORT1 TX) IVG9 19
* DMA5 (PPI) IVG10 20
* DMA6 (UART RX) IVG10 21
* DMA7 (UART TX) IVG10 22
* Timer0 IVG11 23
* Timer1 IVG11 24
* Timer2 IVG11 25
* PF Interrupt A IVG12 26
* PF Interrupt B IVG12 27
* DMA8/9 Interrupt IVG13 28
* DMA10/11 Interrupt IVG13 29
* Watchdog Timer IVG13 30
* Software Interrupt 1 IVG14 31
* Software Interrupt 2 --
* (lowest priority) IVG15 32
*/
#define IRQ_EMU 0 /* Emulation */
#define IRQ_RST 1 /* reset */
#define IRQ_NMI 2 /* Non Maskable */
#define IRQ_EVX 3 /* Exception */
#define IRQ_UNUSED 4 /* - unused interrupt */
#define IRQ_HWERR 5 /* Hardware Error */
#define IRQ_CORETMR 6 /* Core timer */
#define IRQ_UART_RX_BIT 0x0800
#define IRQ_UART_TX_BIT 0x1000
#define IRQ_UART_ERROR_BIT 0x40
#endif

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include/asm-blackfin/arch-bf561/anomaly.h
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/*
* File: include/asm-blackfin/arch-bf561/anomaly.h
* Based on:
* Author:
*
* Created:
* Description:
*
* Rev:
*
* Modified:
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING.
* If not, write to the Free Software Foundation,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
* This file shoule be up to date with:
* - Revision L, 10Aug2006; ADSP-BF561 Silicon Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_
/* We do not support 0.1 or 0.4 silicon - sorry */
#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2) || defined(CONFIG_BF_REV_0_4))
#error Kernel will not work on BF561 Version 0.1, 0.2, or 0.4
#endif
/* Issues that are common to 0.5 and 0.3 silicon */
#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3))
#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
slot1 and store of a P register in slot 2 is not
supported */
#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not
updated at the same time. */
#define ANOMALY_05000120 /* Testset instructions restricted to 32-bit aligned
memory locations */
#define ANOMALY_05000122 /* Rx.H cannot be used to access 16-bit System MMR
registers */
#define ANOMALY_05000127 /* Signbits instruction not functional under certain
conditions */
#define ANOMALY_05000149 /* IMDMA S1/D1 channel may stall */
#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
upper bits */
#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */
#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
syncs */
#define ANOMALY_05000182 /* IMDMA does not operate to full speed for 600MHz
and higher devices */
#define ANOMALY_05000187 /* IMDMA Corrupted Data after a Halt */
#define ANOMALY_05000190 /* PPI not functional at core voltage < 1Volt */
#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not
functional */
#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the
shadow of a conditional branch */
#define ANOMALY_05000257 /* Interrupt/Exception during short hardware loop
may cause bad instruction fetches */
#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
external SPORT TX and RX clocks */
#define ANOMALY_05000267 /* IMDMA may corrupt data under certain conditions */
#define ANOMALY_05000269 /* High I/O activity causes output voltage of internal
voltage regulator (VDDint) to increase */
#define ANOMALY_05000270 /* High I/O activity causes output voltage of internal
voltage regulator (VDDint) to decrease */
#define ANOMALY_05000272 /* Certain data cache write through modes fail for
VDDint <=0.9V */
#define ANOMALY_05000274 /* Data cache write back to external synchronous memory
may be lost */
#define ANOMALY_05000275 /* PPI Timing and sampling informaton updates */
#endif /* (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3)) */
#if (defined(CONFIG_BF_REV_0_5))
#define ANOMALY_05000254 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT
mode with external clock */
#define ANOMALY_05000266 /* IMDMA destination IRQ status must be read prior to
using IMDMA */
#endif
#if (defined(CONFIG_BF_REV_0_3))
#define ANOMALY_05000156 /* Timers in PWM-Out Mode with PPI GP Receive (Input)
Mode with 0 Frame Syncs */
#define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */
#define ANOMALY_05000169 /* DATA CPLB page miss can result in lost write-through
cache data writes */
#define ANOMALY_05000171 /* Boot-ROM code modifies SICA_IWRx wakeup registers */
#define ANOMALY_05000174 /* Cache Fill Buffer Data lost */
#define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */
#define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an
accumulator saturation */
#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General
Purpose TX or RX modes */
#define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration
registers */
#define ANOMALY_05000184 /* Timer Pin limitations for PPI TX Modes with
External Frame Syncs */
#define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */
#define ANOMALY_05000186 /* PPI packing with Data Length greater than 8 bits
(not a meaningful mode) */
#define ANOMALY_05000188 /* IMDMA Restrictions on Descriptor and Buffer
Placement in Memory */
#define ANOMALY_05000189 /* False Protection Exception */
#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs
when polarity setting is changed */
#define ANOMALY_05000194 /* Restarting SPORT in specific modes may cause data
corruption */
#define ANOMALY_05000198 /* Failing MMR accesses when stalled by preceding
memory read */
#define ANOMALY_05000199 /* DMA current address shows wrong value during carry
fix */
#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during
inactive channels in certain conditions */
#define ANOMALY_05000202 /* Possible infinite stall with specific dual-DAG
situation */
#define ANOMALY_05000204 /* Incorrect data read with write-through cache and
allocate cache lines on reads only mode */
#define ANOMALY_05000205 /* Specific sequence that can cause DMA error or DMA
stopping */
#define ANOMALY_05000207 /* Recovery from "brown-out" condition */
#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain
instructions */
#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */
#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
state */
#define ANOMALY_05000220 /* Data Corruption with Cached External Memory and
Non-Cached On-Chip L2 Memory */
#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */
#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect
data */
#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate
Differences in certain Conditions */
#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */
#define ANOMALY_05000232 /* SPORT data transmit lines are incorrectly driven in
multichannel mode */
#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to
hardware reset */
#define ANOMALY_05000244 /* If i-cache is on, CSYNC/SSYNC/IDLE around Change of
Control causes failures */
#define ANOMALY_05000248 /* TESTSET operation forces stall on the other core */
#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
(TDM) mode in certain conditions */
#define ANOMALY_05000251 /* Exception not generated for MMR accesses in
reserved region */
#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
#define ANOMALY_05000258 /* Instruction Cache is corrupted when bits 9 and 12
of the ICPLB Data registers differ */
#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
#define ANOMALY_05000262 /* Stores to data cache may be lost */
#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB
exception */
#define ANOMALY_05000264 /* CSYNC/SSYNC/IDLE causes infinite stall in second
to last instruction in hardware loop */
#define ANOMALY_05000276 /* Timing requirements change for External Frame
Sync PPI Modes with non-zero PPI_DELAY */
#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
DMA system instability */
#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
not restored */
#define ANOMALY_05000283 /* An MMR write is stalled indefinitely when killed
in a particular stage */
#define ANOMALY_05000287 /* A read will receive incorrect data under certain
conditions */
#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */
#endif
#endif /* _MACH_ANOMALY_H_ */

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include/asm-blackfin/arch-bf561/bf561_serial.h
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/*
* U-boot bf561_serial.h
*
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BF561_SERIAL_H_
#define _BF561_SERIAL_H_
#define BYTE_REF(addr) (*((volatile char*)addr))
#define HALFWORD_REF(addr) (*((volatile short*)addr))
#define WORD_REF(addr) (*((volatile long*)addr))
#define UART_THR_LO HALFWORD_REF(UART_THR)
#define UART_RBR_LO HALFWORD_REF(UART_RBR)
#define UART_DLL_LO HALFWORD_REF(UART_DLL)
#define UART_IER_LO HALFWORD_REF(UART_IER)
#define UART_IER_ERBFI 0x01
#define UART_IER_ETBEI 0x02
#define UART_IER_ELSI 0x04
#define UART_IER_EDDSI 0x08
#define UART_DLH_LO HALFWORD_REF(UART_DLH)
#define UART_IIR_LO HALFWORD_REF(UART_IIR)
#define UART_IIR_NOINT 0x01
#define UART_IIR_STATUS 0x06
#define UART_IIR_LSR 0x06
#define UART_IIR_RBR 0x04
#define UART_IIR_THR 0x02
#define UART_IIR_MSR 0x00
#define UART_LCR_LO HALFWORD_REF(UART_LCR)
#define UART_LCR_WLS5 0
#define UART_LCR_WLS6 0x01
#define UART_LCR_WLS7 0x02
#define UART_LCR_WLS8 0x03
#define UART_LCR_STB 0x04
#define UART_LCR_PEN 0x08
#define UART_LCR_EPS 0x10
#define UART_LCR_SP 0x20
#define UART_LCR_SB 0x40
#define UART_LCR_DLAB 0x80
#define UART_MCR_LO HALFWORD_REF(UART_MCR)
#define UART_LSR_LO HALFWORD_REF(UART_LSR)
#define UART_LSR_DR 0x01
#define UART_LSR_OE 0x02
#define UART_LSR_PE 0x04
#define UART_LSR_FE 0x08
#define UART_LSR_BI 0x10
#define UART_LSR_THRE 0x20
#define UART_LSR_TEMT 0x40
#define UART_MSR_LO HALFWORD_REF(UART_MSR)
#define UART_SCR_LO HALFWORD_REF(UART_SCR)
#define UART_GCTL_LO HALFWORD_REF(UART_GCTL)
#define UART_GCTL_UCEN 0x01
#endif

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include/asm-blackfin/arch-bf561/cdefBF561.h
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/*
* cdefBF561.h
*
* (c) Copyright 2001-2004 Analog Devices, Inc. All rights reserved.
*
*/
/* C POINTERS TO SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 */
#ifndef _CDEF_BF561_H
#define _CDEF_BF561_H
/*
* #if !defined(__ADSPBF561__)
* #warning cdefBF561.h should only be included for BF561 chip.
* #endif
*/
/* include all Core registers and bit definitions */
#include <asm/arch-bf561/defBF561.h>
#include <asm/arch-common/cdef_LPBlackfin.h>
/*
* System MMR Register Map
*/
/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
#define pPLL_CTL (volatile unsigned short *)PLL_CTL
#define pPLL_DIV (volatile unsigned short *)PLL_DIV
#define pVR_CTL (volatile unsigned short *)VR_CTL
#define pPLL_STAT (volatile unsigned short *)PLL_STAT
#define pPLL_LOCKCNT (volatile unsigned short *)PLL_LOCKCNT
/*
* System Reset and Interrupt Controller registers for
* core A (0xFFC0 0100-0xFFC0 01FF)
*/
#define pSICA_SWRST (volatile unsigned short *)SICA_SWRST
#define pSICA_SYSCR (volatile unsigned short *)SICA_SYSCR
#define pSICA_RVECT (volatile unsigned short *)SICA_RVECT
#define pSICA_IMASK (volatile unsigned long *)SICA_IMASK
#define pSICA_IMASK0 (volatile unsigned long *)SICA_IMASK0
#define pSICA_IMASK1 (volatile unsigned long *)SICA_IMASK1
#define pSICA_IAR0 (volatile unsigned long *)SICA_IAR0
#define pSICA_IAR1 (volatile unsigned long *)SICA_IAR1
#define pSICA_IAR2 (volatile unsigned long *)SICA_IAR2
#define pSICA_IAR3 (volatile unsigned long *)SICA_IAR3
#define pSICA_IAR4 (volatile unsigned long *)SICA_IAR4
#define pSICA_IAR5 (volatile unsigned long *)SICA_IAR5
#define pSICA_IAR6 (volatile unsigned long *)SICA_IAR6
#define pSICA_IAR7 (volatile unsigned long *)SICA_IAR7
#define pSICA_ISR0 (volatile unsigned long *)SICA_ISR0
#define pSICA_ISR1 (volatile unsigned long *)SICA_ISR1
#define pSICA_IWR0 (volatile unsigned long *)SICA_IWR0
#define pSICA_IWR1 (volatile unsigned long *)SICA_IWR1
/*
* System Reset and Interrupt Controller registers for
* Core B (0xFFC0 1100-0xFFC0 11FF)
*/
#define pSICB_SWRST (volatile unsigned short *)SICB_SWRST
#define pSICB_SYSCR (volatile unsigned short *)SICB_SYSCR
#define pSICB_RVECT (volatile unsigned short *)SICB_RVECT
#define pSICB_IMASK0 (volatile unsigned long *)SICB_IMASK0
#define pSICB_IMASK1 (volatile unsigned long *)SICB_IMASK1
#define pSICB_IAR0 (volatile unsigned long *)SICB_IAR0
#define pSICB_IAR1 (volatile unsigned long *)SICB_IAR1
#define pSICB_IAR2 (volatile unsigned long *)SICB_IAR2
#define pSICB_IAR3 (volatile unsigned long *)SICB_IAR3
#define pSICB_IAR4 (volatile unsigned long *)SICB_IAR4
#define pSICB_IAR5 (volatile unsigned long *)SICB_IAR5
#define pSICB_IAR6 (volatile unsigned long *)SICB_IAR6
#define pSICB_IAR7 (volatile unsigned long *)SICB_IAR7
#define pSICB_ISR0 (volatile unsigned long *)SICB_ISR0
#define pSICB_ISR1 (volatile unsigned long *)SICB_ISR1
#define pSICB_IWR0 (volatile unsigned long *)SICB_IWR0
#define pSICB_IWR1 (volatile unsigned long *)SICB_IWR1
/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
#define pWDOGA_CTL (volatile unsigned short *)WDOGA_CTL
#define pWDOGA_CNT (volatile unsigned long *)WDOGA_CNT
#define pWDOGA_STAT (volatile unsigned long *)WDOGA_STAT
/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
#define pWDOGB_CTL (volatile unsigned short *)WDOGB_CTL
#define pWDOGB_CNT (volatile unsigned long *)WDOGB_CNT
#define pWDOGB_STAT (volatile unsigned long *)WDOGB_STAT
/* UART Controller (0xFFC00400 - 0xFFC004FF) */
#define pUART_THR (volatile unsigned short *)UART_THR
#define pUART_RBR (volatile unsigned short *)UART_RBR
#define pUART_DLL (volatile unsigned short *)UART_DLL
#define pUART_IER (volatile unsigned short *)UART_IER
#define pUART_DLH (volatile unsigned short *)UART_DLH
#define pUART_IIR (volatile unsigned short *)UART_IIR
#define pUART_LCR (volatile unsigned short *)UART_LCR
#define pUART_MCR (volatile unsigned short *)UART_MCR
#define pUART_LSR (volatile unsigned short *)UART_LSR
#define pUART_MSR (volatile unsigned short *)UART_MSR
#define pUART_SCR (volatile unsigned short *)UART_SCR
#define pUART_GCTL (volatile unsigned short *)UART_GCTL
/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
#define pSPI_CTL (volatile unsigned short *)SPI_CTL
#define pSPI_FLG (volatile unsigned short *)SPI_FLG
#define pSPI_STAT (volatile unsigned short *)SPI_STAT
#define pSPI_TDBR (volatile unsigned short *)SPI_TDBR
#define pSPI_RDBR (volatile unsigned short *)SPI_RDBR
#define pSPI_BAUD (volatile unsigned short *)SPI_BAUD
#define pSPI_SHADOW (volatile unsigned short *)SPI_SHADOW
/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
#define pTIMER0_CONFIG (volatile unsigned short *)TIMER0_CONFIG
#define pTIMER0_COUNTER (volatile unsigned long *)TIMER0_COUNTER
#define pTIMER0_PERIOD (volatile unsigned long *)TIMER0_PERIOD
#define pTIMER0_WIDTH (volatile unsigned long *)TIMER0_WIDTH
#define pTIMER1_CONFIG (volatile unsigned short *)TIMER1_CONFIG
#define pTIMER1_COUNTER (volatile unsigned long *)TIMER1_COUNTER
#define pTIMER1_PERIOD (volatile unsigned long *)TIMER1_PERIOD
#define pTIMER1_WIDTH (volatile unsigned long *)TIMER1_WIDTH
#define pTIMER2_CONFIG (volatile unsigned short *)TIMER2_CONFIG
#define pTIMER2_COUNTER (volatile unsigned long *)TIMER2_COUNTER
#define pTIMER2_PERIOD (volatile unsigned long *)TIMER2_PERIOD
#define pTIMER2_WIDTH (volatile unsigned long *)TIMER2_WIDTH
#define pTIMER3_CONFIG (volatile unsigned short *)TIMER3_CONFIG
#define pTIMER3_COUNTER (volatile unsigned long *)TIMER3_COUNTER
#define pTIMER3_PERIOD (volatile unsigned long *)TIMER3_PERIOD
#define pTIMER3_WIDTH (volatile unsigned long *)TIMER3_WIDTH
#define pTIMER4_CONFIG (volatile unsigned short *)TIMER4_CONFIG
#define pTIMER4_COUNTER (volatile unsigned long *)TIMER4_COUNTER
#define pTIMER4_PERIOD (volatile unsigned long *)TIMER4_PERIOD
#define pTIMER4_WIDTH (volatile unsigned long *)TIMER4_WIDTH
#define pTIMER5_CONFIG (volatile unsigned short *)TIMER5_CONFIG
#define pTIMER5_COUNTER (volatile unsigned long *)TIMER5_COUNTER
#define pTIMER5_PERIOD (volatile unsigned long *)TIMER5_PERIOD
#define pTIMER5_WIDTH (volatile unsigned long *)TIMER5_WIDTH
#define pTIMER6_CONFIG (volatile unsigned short *)TIMER6_CONFIG
#define pTIMER6_COUNTER (volatile unsigned long *)TIMER6_COUNTER
#define pTIMER6_PERIOD (volatile unsigned long *)TIMER6_PERIOD
#define pTIMER6_WIDTH (volatile unsigned long *)TIMER6_WIDTH
#define pTIMER7_CONFIG (volatile unsigned short *)TIMER7_CONFIG
#define pTIMER7_COUNTER (volatile unsigned long *)TIMER7_COUNTER
#define pTIMER7_PERIOD (volatile unsigned long *)TIMER7_PERIOD
#define pTIMER7_WIDTH (volatile unsigned long *)TIMER7_WIDTH
/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
#define pTMRS8_ENABLE (volatile unsigned short *)TMRS8_ENABLE
#define pTMRS8_DISABLE (volatile unsigned short *)TMRS8_DISABLE
#define pTMRS8_STATUS (volatile unsigned long *)TMRS8_STATUS
#define pTIMER8_CONFIG (volatile unsigned short *)TIMER8_CONFIG
#define pTIMER8_COUNTER (volatile unsigned long *)TIMER8_COUNTER
#define pTIMER8_PERIOD (volatile unsigned long *)TIMER8_PERIOD
#define pTIMER8_WIDTH (volatile unsigned long *)TIMER8_WIDTH
#define pTIMER9_CONFIG (volatile unsigned short *)TIMER9_CONFIG
#define pTIMER9_COUNTER (volatile unsigned long *)TIMER9_COUNTER
#define pTIMER9_PERIOD (volatile unsigned long *)TIMER9_PERIOD
#define pTIMER9_WIDTH (volatile unsigned long *)TIMER9_WIDTH
#define pTIMER10_CONFIG (volatile unsigned short *)TIMER10_CONFIG
#define pTIMER10_COUNTER (volatile unsigned long *)TIMER10_COUNTER
#define pTIMER10_PERIOD (volatile unsigned long *)TIMER10_PERIOD
#define pTIMER10_WIDTH (volatile unsigned long *)TIMER10_WIDTH
#define pTIMER11_CONFIG (volatile unsigned short *)TIMER11_CONFIG
#define pTIMER11_COUNTER (volatile unsigned long *)TIMER11_COUNTER
#define pTIMER11_PERIOD (volatile unsigned long *)TIMER11_PERIOD
#define pTIMER11_WIDTH (volatile unsigned long *)TIMER11_WIDTH
#define pTMRS4_ENABLE (volatile unsigned short *)TMRS4_ENABLE
#define pTMRS4_DISABLE (volatile unsigned short *)TMRS4_DISABLE
#define pTMRS4_STATUS (volatile unsigned long *)TMRS4_STATUS
/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
#define pFIO0_FLAG_D (volatile unsigned short *)FIO0_FLAG_D
#define pFIO0_FLAG_C (volatile unsigned short *)FIO0_FLAG_C
#define pFIO0_FLAG_S (volatile unsigned short *)FIO0_FLAG_S
#define pFIO0_FLAG_T (volatile unsigned short *)FIO0_FLAG_T
#define pFIO0_MASKA_D (volatile unsigned short *)FIO0_MASKA_D
#define pFIO0_MASKA_C (volatile unsigned short *)FIO0_MASKA_C
#define pFIO0_MASKA_S (volatile unsigned short *)FIO0_MASKA_S
#define pFIO0_MASKA_T (volatile unsigned short *)FIO0_MASKA_T
#define pFIO0_MASKB_D (volatile unsigned short *)FIO0_MASKB_D
#define pFIO0_MASKB_C (volatile unsigned short *)FIO0_MASKB_C
#define pFIO0_MASKB_S (volatile unsigned short *)FIO0_MASKB_S
#define pFIO0_MASKB_T (volatile unsigned short *)FIO0_MASKB_T
#define pFIO0_DIR (volatile unsigned short *)FIO0_DIR
#define pFIO0_POLAR (volatile unsigned short *)FIO0_POLAR
#define pFIO0_EDGE (volatile unsigned short *)FIO0_EDGE
#define pFIO0_BOTH (volatile unsigned short *)FIO0_BOTH
#define pFIO0_INEN (volatile unsigned short *)FIO0_INEN
/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
#define pFIO1_FLAG_D (volatile unsigned short *)FIO1_FLAG_D
#define pFIO1_FLAG_C (volatile unsigned short *)FIO1_FLAG_C
#define pFIO1_FLAG_S (volatile unsigned short *)FIO1_FLAG_S
#define pFIO1_FLAG_T (volatile unsigned short *)FIO1_FLAG_T
#define pFIO1_MASKA_D (volatile unsigned short *)FIO1_MASKA_D
#define pFIO1_MASKA_C (volatile unsigned short *)FIO1_MASKA_C
#define pFIO1_MASKA_S (volatile unsigned short *)FIO1_MASKA_S
#define pFIO1_MASKA_T (volatile unsigned short *)FIO1_MASKA_T
#define pFIO1_MASKB_D (volatile unsigned short *)FIO1_MASKB_D
#define pFIO1_MASKB_C (volatile unsigned short *)FIO1_MASKB_C
#define pFIO1_MASKB_S (volatile unsigned short *)FIO1_MASKB_S
#define pFIO1_MASKB_T (volatile unsigned short *)FIO1_MASKB_T
#define pFIO1_DIR (volatile unsigned short *)FIO1_DIR
#define pFIO1_POLAR (volatile unsigned short *)FIO1_POLAR
#define pFIO1_EDGE (volatile unsigned short *)FIO1_EDGE
#define pFIO1_BOTH (volatile unsigned short *)FIO1_BOTH
#define pFIO1_INEN (volatile unsigned short *)FIO1_INEN
/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
#define pFIO2_FLAG_D (volatile unsigned short *)FIO2_FLAG_D
#define pFIO2_FLAG_C (volatile unsigned short *)FIO2_FLAG_C
#define pFIO2_FLAG_S (volatile unsigned short *)FIO2_FLAG_S
#define pFIO2_FLAG_T (volatile unsigned short *)FIO2_FLAG_T
#define pFIO2_MASKA_D (volatile unsigned short *)FIO2_MASKA_D
#define pFIO2_MASKA_C (volatile unsigned short *)FIO2_MASKA_C
#define pFIO2_MASKA_S (volatile unsigned short *)FIO2_MASKA_S
#define pFIO2_MASKA_T (volatile unsigned short *)FIO2_MASKA_T
#define pFIO2_MASKB_D (volatile unsigned short *)FIO2_MASKB_D
#define pFIO2_MASKB_C (volatile unsigned short *)FIO2_MASKB_C
#define pFIO2_MASKB_S (volatile unsigned short *)FIO2_MASKB_S
#define pFIO2_MASKB_T (volatile unsigned short *)FIO2_MASKB_T
#define pFIO2_DIR (volatile unsigned short *)FIO2_DIR
#define pFIO2_POLAR (volatile unsigned short *)FIO2_POLAR
#define pFIO2_EDGE (volatile unsigned short *)FIO2_EDGE
#define pFIO2_BOTH (volatile unsigned short *)FIO2_BOTH
#define pFIO2_INEN (volatile unsigned short *)FIO2_INEN
/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
#define pSPORT0_TCR1 (volatile unsigned short *)SPORT0_TCR1
#define pSPORT0_TCR2 (volatile unsigned short *)SPORT0_TCR2
#define pSPORT0_TCLKDIV (volatile unsigned short *)SPORT0_TCLKDIV
#define pSPORT0_TFSDIV (volatile unsigned short *)SPORT0_TFSDIV
#define pSPORT0_TX (volatile unsigned long *)SPORT0_TX
#define pSPORT0_RX (volatile unsigned long *)SPORT0_RX
#define pSPORT0_TX32 ((volatile long *)SPORT0_TX)
#define pSPORT0_RX32 ((volatile long *)SPORT0_RX)
#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX)
#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX)
#define pSPORT0_RCR1 (volatile unsigned short *)SPORT0_RCR1
#define pSPORT0_RCR2 (volatile unsigned short *)SPORT0_RCR2
#define pSPORT0_RCLKDIV (volatile unsigned short *)SPORT0_RCLKDIV
#define pSPORT0_RFSDIV (volatile unsigned short *)SPORT0_RFSDIV
#define pSPORT0_STAT (volatile unsigned short *)SPORT0_STAT
#define pSPORT0_CHNL (volatile unsigned short *)SPORT0_CHNL
#define pSPORT0_MCMC1 (volatile unsigned short *)SPORT0_MCMC1
#define pSPORT0_MCMC2 (volatile unsigned short *)SPORT0_MCMC2
#define pSPORT0_MTCS0 (volatile unsigned long *)SPORT0_MTCS0
#define pSPORT0_MTCS1 (volatile unsigned long *)SPORT0_MTCS1
#define pSPORT0_MTCS2 (volatile unsigned long *)SPORT0_MTCS2
#define pSPORT0_MTCS3 (volatile unsigned long *)SPORT0_MTCS3
#define pSPORT0_MRCS0 (volatile unsigned long *)SPORT0_MRCS0
#define pSPORT0_MRCS1 (volatile unsigned long *)SPORT0_MRCS1
#define pSPORT0_MRCS2 (volatile unsigned long *)SPORT0_MRCS2
#define pSPORT0_MRCS3 (volatile unsigned long *)SPORT0_MRCS3
/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
#define pSPORT1_TCR1 (volatile unsigned short *)SPORT1_TCR1
#define pSPORT1_TCR2 (volatile unsigned short *)SPORT1_TCR2
#define pSPORT1_TCLKDIV (volatile unsigned short *)SPORT1_TCLKDIV
#define pSPORT1_TFSDIV (volatile unsigned short *)SPORT1_TFSDIV
#define pSPORT1_TX (volatile unsigned long *)SPORT1_TX
#define pSPORT1_RX (volatile unsigned long *)SPORT1_RX
#define pSPORT1_TX32 ((volatile long *)SPORT1_TX)
#define pSPORT1_RX32 ((volatile long *)SPORT1_RX)
#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX)
#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX)
#define pSPORT1_RCR1 (volatile unsigned short *)SPORT1_RCR1
#define pSPORT1_RCR2 (volatile unsigned short *)SPORT1_RCR2
#define pSPORT1_RCLKDIV (volatile unsigned short *)SPORT1_RCLKDIV
#define pSPORT1_RFSDIV (volatile unsigned short *)SPORT1_RFSDIV
#define pSPORT1_STAT (volatile unsigned short *)SPORT1_STAT
#define pSPORT1_CHNL (volatile unsigned short *)SPORT1_CHNL
#define pSPORT1_MCMC1 (volatile unsigned short *)SPORT1_MCMC1
#define pSPORT1_MCMC2 (volatile unsigned short *)SPORT1_MCMC2
#define pSPORT1_MTCS0 (volatile unsigned long *)SPORT1_MTCS0
#define pSPORT1_MTCS1 (volatile unsigned long *)SPORT1_MTCS1
#define pSPORT1_MTCS2 (volatile unsigned long *)SPORT1_MTCS2
#define pSPORT1_MTCS3 (volatile unsigned long *)SPORT1_MTCS3
#define pSPORT1_MRCS0 (volatile unsigned long *)SPORT1_MRCS0
#define pSPORT1_MRCS1 (volatile unsigned long *)SPORT1_MRCS1
#define pSPORT1_MRCS2 (volatile unsigned long *)SPORT1_MRCS2
#define pSPORT1_MRCS3 (volatile unsigned long *)SPORT1_MRCS3
/* Asynchronous Memory Controller - External Bus Interface Unit */
#define pEBIU_AMGCTL (volatile unsigned short *)EBIU_AMGCTL
#define pEBIU_AMBCTL0 (volatile unsigned long *)EBIU_AMBCTL0
#define pEBIU_AMBCTL1 (volatile unsigned long *)EBIU_AMBCTL1
/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
#define pEBIU_SDGCTL (volatile unsigned long *)EBIU_SDGCTL
#define pEBIU_SDBCTL (volatile unsigned long *)EBIU_SDBCTL
#define pEBIU_SDRRC (volatile unsigned short *)EBIU_SDRRC
#define pEBIU_SDSTAT (volatile unsigned short *)EBIU_SDSTAT
/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF)*/
#define pPPI0_CONTROL (volatile unsigned short *)PPI0_CONTROL
#define pPPI0_STATUS (volatile unsigned short *)PPI0_STATUS
#define pPPI0_COUNT (volatile unsigned short *)PPI0_COUNT
#define pPPI0_DELAY (volatile unsigned short *)PPI0_DELAY
#define pPPI0_FRAME (volatile unsigned short *)PPI0_FRAME
/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF)*/
#define pPPI1_CONTROL (volatile unsigned short *)PPI1_CONTROL
#define pPPI1_STATUS (volatile unsigned short *)PPI1_STATUS
#define pPPI1_COUNT (volatile unsigned short *)PPI1_COUNT
#define pPPI1_DELAY (volatile unsigned short *)PPI1_DELAY
#define pPPI1_FRAME (volatile unsigned short *)PPI1_FRAME
/*DMA Traffic controls*/
#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER)
#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT)
#define pDMA_TC_PER ((volatile unsigned short *)DMA_TC_PER)
#define pDMA_TC_CNT ((volatile unsigned short *)DMA_TC_CNT)
/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
#define pDMA1_0_CONFIG (volatile unsigned short *)DMA1_0_CONFIG
#define pDMA1_0_NEXT_DESC_PTR (volatile void **)DMA1_0_NEXT_DESC_PTR
#define pDMA1_0_START_ADDR (volatile void **)DMA1_0_START_ADDR
#define pDMA1_0_X_COUNT (volatile unsigned short *)DMA1_0_X_COUNT
#define pDMA1_0_Y_COUNT (volatile unsigned short *)DMA1_0_Y_COUNT
#define pDMA1_0_X_MODIFY (volatile unsigned short *)DMA1_0_X_MODIFY
#define pDMA1_0_Y_MODIFY (volatile unsigned short *)DMA1_0_Y_MODIFY
#define pDMA1_0_CURR_DESC_PTR (volatile void **)DMA1_0_CURR_DESC_PTR
#define pDMA1_0_CURR_ADDR (volatile void **)DMA1_0_CURR_ADDR
#define pDMA1_0_CURR_X_COUNT (volatile unsigned short *)DMA1_0_CURR_X_COUNT
#define pDMA1_0_CURR_Y_COUNT (volatile unsigned short *)DMA1_0_CURR_Y_COUNT
#define pDMA1_0_IRQ_STATUS (volatile unsigned short *)DMA1_0_IRQ_STATUS
#define pDMA1_0_PERIPHERAL_MAP (volatile unsigned short *)DMA1_0_PERIPHERAL_MAP
#define pDMA1_1_CONFIG (volatile unsigned short *)DMA1_1_CONFIG
#define pDMA1_1_NEXT_DESC_PTR (volatile void **)DMA1_1_NEXT_DESC_PTR
#define pDMA1_1_START_ADDR (volatile void **)DMA1_1_START_ADDR
#define pDMA1_1_X_COUNT (volatile unsigned short *)DMA1_1_X_COUNT
#define pDMA1_1_Y_COUNT (volatile unsigned short *)DMA1_1_Y_COUNT
#define pDMA1_1_X_MODIFY (volatile unsigned short *)DMA1_1_X_MODIFY
#define pDMA1_1_Y_MODIFY (volatile unsigned short *)DMA1_1_Y_MODIFY
#define pDMA1_1_CURR_DESC_PTR (volatile void **)DMA1_1_CURR_DESC_PTR
#define pDMA1_1_CURR_ADDR (volatile void **)DMA1_1_CURR_ADDR
#define pDMA1_1_CURR_X_COUNT (volatile unsigned short *)DMA1_1_CURR_X_COUNT
#define pDMA1_1_CURR_Y_COUNT (volatile unsigned short *)DMA1_1_CURR_Y_COUNT
#define pDMA1_1_IRQ_STATUS (volatile unsigned short *)DMA1_1_IRQ_STATUS
#define pDMA1_1_PERIPHERAL_MAP (volatile unsigned short *)DMA1_1_PERIPHERAL_MAP
#define pDMA1_2_CONFIG (volatile unsigned short *)DMA1_2_CONFIG
#define pDMA1_2_NEXT_DESC_PTR (volatile void **)DMA1_2_NEXT_DESC_PTR
#define pDMA1_2_START_ADDR (volatile void **)DMA1_2_START_ADDR
#define pDMA1_2_X_COUNT (volatile unsigned short *)DMA1_2_X_COUNT
#define pDMA1_2_Y_COUNT (volatile unsigned short *)DMA1_2_Y_COUNT
#define pDMA1_2_X_MODIFY (volatile unsigned short *)DMA1_2_X_MODIFY
#define pDMA1_2_Y_MODIFY (volatile unsigned short *)DMA1_2_Y_MODIFY
#define pDMA1_2_CURR_DESC_PTR (volatile void **)DMA1_2_CURR_DESC_PTR
#define pDMA1_2_CURR_ADDR (volatile void **)DMA1_2_CURR_ADDR
#define pDMA1_2_CURR_X_COUNT (volatile unsigned short *)DMA1_2_CURR_X_COUNT
#define pDMA1_2_CURR_Y_COUNT (volatile unsigned short *)DMA1_2_CURR_Y_COUNT
#define pDMA1_2_IRQ_STATUS (volatile unsigned short *)DMA1_2_IRQ_STATUS
#define pDMA1_2_PERIPHERAL_MAP (volatile unsigned short *)DMA1_2_PERIPHERAL_MAP
#define pDMA1_3_CONFIG (volatile unsigned short *)DMA1_3_CONFIG
#define pDMA1_3_NEXT_DESC_PTR (volatile void **)DMA1_3_NEXT_DESC_PTR
#define pDMA1_3_START_ADDR (volatile void **)DMA1_3_START_ADDR
#define pDMA1_3_X_COUNT (volatile unsigned short *)DMA1_3_X_COUNT
#define pDMA1_3_Y_COUNT (volatile unsigned short *)DMA1_3_Y_COUNT
#define pDMA1_3_X_MODIFY (volatile unsigned short *)DMA1_3_X_MODIFY
#define pDMA1_3_Y_MODIFY (volatile unsigned short *)DMA1_3_Y_MODIFY
#define pDMA1_3_CURR_DESC_PTR (volatile void **)DMA1_3_CURR_DESC_PTR
#define pDMA1_3_CURR_ADDR (volatile void **)DMA1_3_CURR_ADDR
#define pDMA1_3_CURR_X_COUNT (volatile unsigned short *)DMA1_3_CURR_X_COUNT
#define pDMA1_3_CURR_Y_COUNT (volatile unsigned short *)DMA1_3_CURR_Y_COUNT
#define pDMA1_3_IRQ_STATUS (volatile unsigned short *)DMA1_3_IRQ_STATUS
#define pDMA1_3_PERIPHERAL_MAP (volatile unsigned short *)DMA1_3_PERIPHERAL_MAP
#define pDMA1_4_CONFIG (volatile unsigned short *)DMA1_4_CONFIG
#define pDMA1_4_NEXT_DESC_PTR (volatile void **)DMA1_4_NEXT_DESC_PTR
#define pDMA1_4_START_ADDR (volatile void **)DMA1_4_START_ADDR
#define pDMA1_4_X_COUNT (volatile unsigned short *)DMA1_4_X_COUNT
#define pDMA1_4_Y_COUNT (volatile unsigned short *)DMA1_4_Y_COUNT
#define pDMA1_4_X_MODIFY (volatile unsigned short *)DMA1_4_X_MODIFY
#define pDMA1_4_Y_MODIFY (volatile unsigned short *)DMA1_4_Y_MODIFY
#define pDMA1_4_CURR_DESC_PTR (volatile void **)DMA1_4_CURR_DESC_PTR
#define pDMA1_4_CURR_ADDR (volatile void **)DMA1_4_CURR_ADDR
#define pDMA1_4_CURR_X_COUNT (volatile unsigned short *)DMA1_4_CURR_X_COUNT
#define pDMA1_4_CURR_Y_COUNT (volatile unsigned short *)DMA1_4_CURR_Y_COUNT
#define pDMA1_4_IRQ_STATUS (volatile unsigned short *)DMA1_4_IRQ_STATUS
#define pDMA1_4_PERIPHERAL_MAP (volatile unsigned short *)DMA1_4_PERIPHERAL_MAP
#define pDMA1_5_CONFIG (volatile unsigned short *)DMA1_5_CONFIG
#define pDMA1_5_NEXT_DESC_PTR (volatile void **)DMA1_5_NEXT_DESC_PTR
#define pDMA1_5_START_ADDR (volatile void **)DMA1_5_START_ADDR
#define pDMA1_5_X_COUNT (volatile unsigned short *)DMA1_5_X_COUNT
#define pDMA1_5_Y_COUNT (volatile unsigned short *)DMA1_5_Y_COUNT
#define pDMA1_5_X_MODIFY (volatile unsigned short *)DMA1_5_X_MODIFY
#define pDMA1_5_Y_MODIFY (volatile unsigned short *)DMA1_5_Y_MODIFY
#define pDMA1_5_CURR_DESC_PTR (volatile void **)DMA1_5_CURR_DESC_PTR
#define pDMA1_5_CURR_ADDR (volatile void **)DMA1_5_CURR_ADDR
#define pDMA1_5_CURR_X_COUNT (volatile unsigned short *)DMA1_5_CURR_X_COUNT
#define pDMA1_5_CURR_Y_COUNT (volatile unsigned short *)DMA1_5_CURR_Y_COUNT
#define pDMA1_5_IRQ_STATUS (volatile unsigned short *)DMA1_5_IRQ_STATUS
#define pDMA1_5_PERIPHERAL_MAP (volatile unsigned short *)DMA1_5_PERIPHERAL_MAP
#define pDMA1_6_CONFIG (volatile unsigned short *)DMA1_6_CONFIG
#define pDMA1_6_NEXT_DESC_PTR (volatile void **)DMA1_6_NEXT_DESC_PTR
#define pDMA1_6_START_ADDR (volatile void **)DMA1_6_START_ADDR
#define pDMA1_6_X_COUNT (volatile unsigned short *)DMA1_6_X_COUNT
#define pDMA1_6_Y_COUNT (volatile unsigned short *)DMA1_6_Y_COUNT
#define pDMA1_6_X_MODIFY (volatile unsigned short *)DMA1_6_X_MODIFY
#define pDMA1_6_Y_MODIFY (volatile unsigned short *)DMA1_6_Y_MODIFY
#define pDMA1_6_CURR_DESC_PTR (volatile void **)DMA1_6_CURR_DESC_PTR
#define pDMA1_6_CURR_ADDR (volatile void **)DMA1_6_CURR_ADDR
#define pDMA1_6_CURR_X_COUNT (volatile unsigned short *)DMA1_6_CURR_X_COUNT
#define pDMA1_6_CURR_Y_COUNT (volatile unsigned short *)DMA1_6_CURR_Y_COUNT
#define pDMA1_6_IRQ_STATUS (volatile unsigned short *)DMA1_6_IRQ_STATUS
#define pDMA1_6_PERIPHERAL_MAP (volatile unsigned short *)DMA1_6_PERIPHERAL_MAP
#define pDMA1_7_CONFIG (volatile unsigned short *)DMA1_7_CONFIG
#define pDMA1_7_NEXT_DESC_PTR (volatile void **)DMA1_7_NEXT_DESC_PTR
#define pDMA1_7_START_ADDR (volatile void **)DMA1_7_START_ADDR
#define pDMA1_7_X_COUNT (volatile unsigned short *)DMA1_7_X_COUNT
#define pDMA1_7_Y_COUNT (volatile unsigned short *)DMA1_7_Y_COUNT
#define pDMA1_7_X_MODIFY (volatile unsigned short *)DMA1_7_X_MODIFY
#define pDMA1_7_Y_MODIFY (volatile unsigned short *)DMA1_7_Y_MODIFY
#define pDMA1_7_CURR_DESC_PTR (volatile void **)DMA1_7_CURR_DESC_PTR
#define pDMA1_7_CURR_ADDR (volatile void **)DMA1_7_CURR_ADDR
#define pDMA1_7_CURR_X_COUNT (volatile unsigned short *)DMA1_7_CURR_X_COUNT
#define pDMA1_7_CURR_Y_COUNT (volatile unsigned short *)DMA1_7_CURR_Y_COUNT
#define pDMA1_7_IRQ_STATUS (volatile unsigned short *)DMA1_7_IRQ_STATUS
#define pDMA1_7_PERIPHERAL_MAP (volatile unsigned short *)DMA1_7_PERIPHERAL_MAP
#define pDMA1_8_CONFIG (volatile unsigned short *)DMA1_8_CONFIG
#define pDMA1_8_NEXT_DESC_PTR (volatile void **)DMA1_8_NEXT_DESC_PTR
#define pDMA1_8_START_ADDR (volatile void **)DMA1_8_START_ADDR
#define pDMA1_8_X_COUNT (volatile unsigned short *)DMA1_8_X_COUNT
#define pDMA1_8_Y_COUNT (volatile unsigned short *)DMA1_8_Y_COUNT
#define pDMA1_8_X_MODIFY (volatile unsigned short *)DMA1_8_X_MODIFY
#define pDMA1_8_Y_MODIFY (volatile unsigned short *)DMA1_8_Y_MODIFY
#define pDMA1_8_CURR_DESC_PTR (volatile void **)DMA1_8_CURR_DESC_PTR
#define pDMA1_8_CURR_ADDR (volatile void **)DMA1_8_CURR_ADDR
#define pDMA1_8_CURR_X_COUNT (volatile unsigned short *)DMA1_8_CURR_X_COUNT
#define pDMA1_8_CURR_Y_COUNT (volatile unsigned short *)DMA1_8_CURR_Y_COUNT
#define pDMA1_8_IRQ_STATUS (volatile unsigned short *)DMA1_8_IRQ_STATUS
#define pDMA1_8_PERIPHERAL_MAP (volatile unsigned short *)DMA1_8_PERIPHERAL_MAP
#define pDMA1_9_CONFIG (volatile unsigned short *)DMA1_9_CONFIG
#define pDMA1_9_NEXT_DESC_PTR (volatile void **)DMA1_9_NEXT_DESC_PTR
#define pDMA1_9_START_ADDR (volatile void **)DMA1_9_START_ADDR
#define pDMA1_9_X_COUNT (volatile unsigned short *)DMA1_9_X_COUNT
#define pDMA1_9_Y_COUNT (volatile unsigned short *)DMA1_9_Y_COUNT
#define pDMA1_9_X_MODIFY (volatile unsigned short *)DMA1_9_X_MODIFY
#define pDMA1_9_Y_MODIFY (volatile unsigned short *)DMA1_9_Y_MODIFY
#define pDMA1_9_CURR_DESC_PTR (volatile void **)DMA1_9_CURR_DESC_PTR
#define pDMA1_9_CURR_ADDR (volatile void **)DMA1_9_CURR_ADDR
#define pDMA1_9_CURR_X_COUNT (volatile unsigned short *)DMA1_9_CURR_X_COUNT
#define pDMA1_9_CURR_Y_COUNT (volatile unsigned short *)DMA1_9_CURR_Y_COUNT
#define pDMA1_9_IRQ_STATUS (volatile unsigned short *)DMA1_9_IRQ_STATUS
#define pDMA1_9_PERIPHERAL_MAP (volatile unsigned short *)DMA1_9_PERIPHERAL_MAP
#define pDMA1_10_CONFIG (volatile unsigned short *)DMA1_10_CONFIG
#define pDMA1_10_NEXT_DESC_PTR (volatile void **)DMA1_10_NEXT_DESC_PTR
#define pDMA1_10_START_ADDR (volatile void **)DMA1_10_START_ADDR
#define pDMA1_10_X_COUNT (volatile unsigned short *)DMA1_10_X_COUNT
#define pDMA1_10_Y_COUNT (volatile unsigned short *)DMA1_10_Y_COUNT
#define pDMA1_10_X_MODIFY (volatile unsigned short *)DMA1_10_X_MODIFY
#define pDMA1_10_Y_MODIFY (volatile unsigned short *)DMA1_10_Y_MODIFY
#define pDMA1_10_CURR_DESC_PTR (volatile void **)DMA1_10_CURR_DESC_PTR
#define pDMA1_10_CURR_ADDR (volatile void **)DMA1_10_CURR_ADDR
#define pDMA1_10_CURR_X_COUNT (volatile unsigned short *)DMA1_10_CURR_X_COUNT
#define pDMA1_10_CURR_Y_COUNT (volatile unsigned short *)DMA1_10_CURR_Y_COUNT
#define pDMA1_10_IRQ_STATUS (volatile unsigned short *)DMA1_10_IRQ_STATUS
#define pDMA1_10_PERIPHERAL_MAP (volatile unsigned short *)DMA1_10_PERIPHERAL_MAP
#define pDMA1_11_CONFIG (volatile unsigned short *)DMA1_11_CONFIG
#define pDMA1_11_NEXT_DESC_PTR (volatile void **)DMA1_11_NEXT_DESC_PTR
#define pDMA1_11_START_ADDR (volatile void **)DMA1_11_START_ADDR
#define pDMA1_11_X_COUNT (volatile unsigned short *)DMA1_11_X_COUNT
#define pDMA1_11_Y_COUNT (volatile unsigned short *)DMA1_11_Y_COUNT
#define pDMA1_11_X_MODIFY (volatile signed short *)DMA1_11_X_MODIFY
#define pDMA1_11_Y_MODIFY (volatile signed short *)DMA1_11_Y_MODIFY
#define pDMA1_11_CURR_DESC_PTR (volatile void **)DMA1_11_CURR_DESC_PTR
#define pDMA1_11_CURR_ADDR (volatile void **)DMA1_11_CURR_ADDR
#define pDMA1_11_CURR_X_COUNT (volatile unsigned short *)DMA1_11_CURR_X_COUNT
#define pDMA1_11_CURR_Y_COUNT (volatile unsigned short *)DMA1_11_CURR_Y_COUNT
#define pDMA1_11_IRQ_STATUS (volatile unsigned short *)DMA1_11_IRQ_STATUS
#define pDMA1_11_PERIPHERAL_MAP (volatile unsigned short *)DMA1_11_PERIPHERAL_MAP
/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF)*/
#define pMDMA1_D0_CONFIG (volatile unsigned short *)MDMA1_D0_CONFIG
#define pMDMA1_D0_NEXT_DESC_PTR (volatile void **)MDMA1_D0_NEXT_DESC_PTR
#define pMDMA1_D0_START_ADDR (volatile void **)MDMA1_D0_START_ADDR
#define pMDMA1_D0_X_COUNT (volatile unsigned short *)MDMA1_D0_X_COUNT
#define pMDMA1_D0_Y_COUNT (volatile unsigned short *)MDMA1_D0_Y_COUNT
#define pMDMA1_D0_X_MODIFY (volatile signed short *)MDMA1_D0_X_MODIFY
#define pMDMA1_D0_Y_MODIFY (volatile signed short *)MDMA1_D0_Y_MODIFY
#define pMDMA1_D0_CURR_DESC_PTR (volatile void **)MDMA1_D0_CURR_DESC_PTR
#define pMDMA1_D0_CURR_ADDR (volatile void **)MDMA1_D0_CURR_ADDR
#define pMDMA1_D0_CURR_X_COUNT (volatile unsigned short *)MDMA1_D0_CURR_X_COUNT
#define pMDMA1_D0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D0_CURR_Y_COUNT
#define pMDMA1_D0_IRQ_STATUS (volatile unsigned short *)MDMA1_D0_IRQ_STATUS
#define pMDMA1_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D0_PERIPHERAL_MAP
#define pMDMA1_S0_CONFIG (volatile unsigned short *)MDMA1_S0_CONFIG
#define pMDMA1_S0_NEXT_DESC_PTR (volatile void **)MDMA1_S0_NEXT_DESC_PTR
#define pMDMA1_S0_START_ADDR (volatile void **)MDMA1_S0_START_ADDR
#define pMDMA1_S0_X_COUNT (volatile unsigned short *)MDMA1_S0_X_COUNT
#define pMDMA1_S0_Y_COUNT (volatile unsigned short *)MDMA1_S0_Y_COUNT
#define pMDMA1_S0_X_MODIFY (volatile signed short *)MDMA1_S0_X_MODIFY
#define pMDMA1_S0_Y_MODIFY (volatile signed short *)MDMA1_S0_Y_MODIFY
#define pMDMA1_S0_CURR_DESC_PTR (volatile void **)MDMA1_S0_CURR_DESC_PTR
#define pMDMA1_S0_CURR_ADDR (volatile void **)MDMA1_S0_CURR_ADDR
#define pMDMA1_S0_CURR_X_COUNT (volatile unsigned short *)MDMA1_S0_CURR_X_COUNT
#define pMDMA1_S0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S0_CURR_Y_COUNT
#define pMDMA1_S0_IRQ_STATUS (volatile unsigned short *)MDMA1_S0_IRQ_STATUS
#define pMDMA1_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S0_PERIPHERAL_MAP
#define pMDMA1_D1_CONFIG (volatile unsigned short *)MDMA1_D1_CONFIG
#define pMDMA1_D1_NEXT_DESC_PTR (volatile void **)MDMA1_D1_NEXT_DESC_PTR
#define pMDMA1_D1_START_ADDR (volatile void **)MDMA1_D1_START_ADDR
#define pMDMA1_D1_X_COUNT (volatile unsigned short *)MDMA1_D1_X_COUNT
#define pMDMA1_D1_Y_COUNT (volatile unsigned short *)MDMA1_D1_Y_COUNT
#define pMDMA1_D1_X_MODIFY (volatile signed short *)MDMA1_D1_X_MODIFY
#define pMDMA1_D1_Y_MODIFY (volatile signed short *)MDMA1_D1_Y_MODIFY
#define pMDMA1_D1_CURR_DESC_PTR (volatile void **)MDMA1_D1_CURR_DESC_PTR
#define pMDMA1_D1_CURR_ADDR (volatile void **)MDMA1_D1_CURR_ADDR
#define pMDMA1_D1_CURR_X_COUNT (volatile unsigned short *)MDMA1_D1_CURR_X_COUNT
#define pMDMA1_D1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D1_CURR_Y_COUNT
#define pMDMA1_D1_IRQ_STATUS (volatile unsigned short *)MDMA1_D1_IRQ_STATUS
#define pMDMA1_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D1_PERIPHERAL_MAP
#define pMDMA1_S1_CONFIG (volatile unsigned short *)MDMA1_S1_CONFIG
#define pMDMA1_S1_NEXT_DESC_PTR (volatile void **)MDMA1_S1_NEXT_DESC_PTR
#define pMDMA1_S1_START_ADDR (volatile void **)MDMA1_S1_START_ADDR
#define pMDMA1_S1_X_COUNT (volatile unsigned short *)MDMA1_S1_X_COUNT
#define pMDMA1_S1_Y_COUNT (volatile unsigned short *)MDMA1_S1_Y_COUNT
#define pMDMA1_S1_X_MODIFY (volatile signed short *)MDMA1_S1_X_MODIFY
#define pMDMA1_S1_Y_MODIFY (volatile signed short *)MDMA1_S1_Y_MODIFY
#define pMDMA1_S1_CURR_DESC_PTR (volatile void **)MDMA1_S1_CURR_DESC_PTR
#define pMDMA1_S1_CURR_ADDR (volatile void **)MDMA1_S1_CURR_ADDR
#define pMDMA1_S1_CURR_X_COUNT (volatile unsigned short *)MDMA1_S1_CURR_X_COUNT
#define pMDMA1_S1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S1_CURR_Y_COUNT
#define pMDMA1_S1_IRQ_STATUS (volatile unsigned short *)MDMA1_S1_IRQ_STATUS
#define pMDMA1_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S1_PERIPHERAL_MAP
/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
#define pDMA2_0_CONFIG (volatile unsigned short *)DMA2_0_CONFIG
#define pDMA2_0_NEXT_DESC_PTR (volatile void **)DMA2_0_NEXT_DESC_PTR
#define pDMA2_0_START_ADDR (volatile void **)DMA2_0_START_ADDR
#define pDMA2_0_X_COUNT (volatile unsigned short *)DMA2_0_X_COUNT
#define pDMA2_0_Y_COUNT (volatile unsigned short *)DMA2_0_Y_COUNT
#define pDMA2_0_X_MODIFY (volatile signed short *)DMA2_0_X_MODIFY
#define pDMA2_0_Y_MODIFY (volatile signed short *)DMA2_0_Y_MODIFY
#define pDMA2_0_CURR_DESC_PTR (volatile void **)DMA2_0_CURR_DESC_PTR
#define pDMA2_0_CURR_ADDR (volatile void **)DMA2_0_CURR_ADDR
#define pDMA2_0_CURR_X_COUNT (volatile unsigned short *)DMA2_0_CURR_X_COUNT
#define pDMA2_0_CURR_Y_COUNT (volatile unsigned short *)DMA2_0_CURR_Y_COUNT
#define pDMA2_0_IRQ_STATUS (volatile unsigned short *)DMA2_0_IRQ_STATUS
#define pDMA2_0_PERIPHERAL_MAP (volatile unsigned short *)DMA2_0_PERIPHERAL_MAP
#define pDMA2_1_CONFIG (volatile unsigned short *)DMA2_1_CONFIG
#define pDMA2_1_NEXT_DESC_PTR (volatile void **)DMA2_1_NEXT_DESC_PTR
#define pDMA2_1_START_ADDR (volatile void **)DMA2_1_START_ADDR
#define pDMA2_1_X_COUNT (volatile unsigned short *)DMA2_1_X_COUNT
#define pDMA2_1_Y_COUNT (volatile unsigned short *)DMA2_1_Y_COUNT
#define pDMA2_1_X_MODIFY (volatile signed short *)DMA2_1_X_MODIFY
#define pDMA2_1_Y_MODIFY (volatile signed short *)DMA2_1_Y_MODIFY
#define pDMA2_1_CURR_DESC_PTR (volatile void **)DMA2_1_CURR_DESC_PTR
#define pDMA2_1_CURR_ADDR (volatile void **)DMA2_1_CURR_ADDR
#define pDMA2_1_CURR_X_COUNT (volatile unsigned short *)DMA2_1_CURR_X_COUNT
#define pDMA2_1_CURR_Y_COUNT (volatile unsigned short *)DMA2_1_CURR_Y_COUNT
#define pDMA2_1_IRQ_STATUS (volatile unsigned short *)DMA2_1_IRQ_STATUS
#define pDMA2_1_PERIPHERAL_MAP (volatile unsigned short *)DMA2_1_PERIPHERAL_MAP
#define pDMA2_2_CONFIG (volatile unsigned short *)DMA2_2_CONFIG
#define pDMA2_2_NEXT_DESC_PTR (volatile void **)DMA2_2_NEXT_DESC_PTR
#define pDMA2_2_START_ADDR (volatile void **)DMA2_2_START_ADDR
#define pDMA2_2_X_COUNT (volatile unsigned short *)DMA2_2_X_COUNT
#define pDMA2_2_Y_COUNT (volatile unsigned short *)DMA2_2_Y_COUNT
#define pDMA2_2_X_MODIFY (volatile signed short *)DMA2_2_X_MODIFY
#define pDMA2_2_Y_MODIFY (volatile signed short *)DMA2_2_Y_MODIFY
#define pDMA2_2_CURR_DESC_PTR (volatile void **)DMA2_2_CURR_DESC_PTR
#define pDMA2_2_CURR_ADDR (volatile void **)DMA2_2_CURR_ADDR
#define pDMA2_2_CURR_X_COUNT (volatile unsigned short *)DMA2_2_CURR_X_COUNT
#define pDMA2_2_CURR_Y_COUNT (volatile unsigned short *)DMA2_2_CURR_Y_COUNT
#define pDMA2_2_IRQ_STATUS (volatile unsigned short *)DMA2_2_IRQ_STATUS
#define pDMA2_2_PERIPHERAL_MAP (volatile unsigned short *)DMA2_2_PERIPHERAL_MAP
#define pDMA2_3_CONFIG (volatile unsigned short *)DMA2_3_CONFIG
#define pDMA2_3_NEXT_DESC_PTR (volatile void **)DMA2_3_NEXT_DESC_PTR
#define pDMA2_3_START_ADDR (volatile void **)DMA2_3_START_ADDR
#define pDMA2_3_X_COUNT (volatile unsigned short *)DMA2_3_X_COUNT
#define pDMA2_3_Y_COUNT (volatile unsigned short *)DMA2_3_Y_COUNT
#define pDMA2_3_X_MODIFY (volatile signed short *)DMA2_3_X_MODIFY
#define pDMA2_3_Y_MODIFY (volatile signed short *)DMA2_3_Y_MODIFY
#define pDMA2_3_CURR_DESC_PTR (volatile void **)DMA2_3_CURR_DESC_PTR
#define pDMA2_3_CURR_ADDR (volatile void **)DMA2_3_CURR_ADDR
#define pDMA2_3_CURR_X_COUNT (volatile unsigned short *)DMA2_3_CURR_X_COUNT
#define pDMA2_3_CURR_Y_COUNT (volatile unsigned short *)DMA2_3_CURR_Y_COUNT
#define pDMA2_3_IRQ_STATUS (volatile unsigned short *)DMA2_3_IRQ_STATUS
#define pDMA2_3_PERIPHERAL_MAP (volatile unsigned short *)DMA2_3_PERIPHERAL_MAP
#define pDMA2_4_CONFIG (volatile unsigned short *)DMA2_4_CONFIG
#define pDMA2_4_NEXT_DESC_PTR (volatile void **)DMA2_4_NEXT_DESC_PTR
#define pDMA2_4_START_ADDR (volatile void **)DMA2_4_START_ADDR
#define pDMA2_4_X_COUNT (volatile unsigned short *)DMA2_4_X_COUNT
#define pDMA2_4_Y_COUNT (volatile unsigned short *)DMA2_4_Y_COUNT
#define pDMA2_4_X_MODIFY (volatile signed short *)DMA2_4_X_MODIFY
#define pDMA2_4_Y_MODIFY (volatile signed short *)DMA2_4_Y_MODIFY
#define pDMA2_4_CURR_DESC_PTR (volatile void **)DMA2_4_CURR_DESC_PTR
#define pDMA2_4_CURR_ADDR (volatile void **)DMA2_4_CURR_ADDR
#define pDMA2_4_CURR_X_COUNT (volatile unsigned short *)DMA2_4_CURR_X_COUNT
#define pDMA2_4_CURR_Y_COUNT (volatile unsigned short *)DMA2_4_CURR_Y_COUNT
#define pDMA2_4_IRQ_STATUS (volatile unsigned short *)DMA2_4_IRQ_STATUS
#define pDMA2_4_PERIPHERAL_MAP (volatile unsigned short *)DMA2_4_PERIPHERAL_MAP
#define pDMA2_5_CONFIG (volatile unsigned short *)DMA2_5_CONFIG
#define pDMA2_5_NEXT_DESC_PTR (volatile void **)DMA2_5_NEXT_DESC_PTR
#define pDMA2_5_START_ADDR (volatile void **)DMA2_5_START_ADDR
#define pDMA2_5_X_COUNT (volatile unsigned short *)DMA2_5_X_COUNT
#define pDMA2_5_Y_COUNT (volatile unsigned short *)DMA2_5_Y_COUNT
#define pDMA2_5_X_MODIFY (volatile signed short *)DMA2_5_X_MODIFY
#define pDMA2_5_Y_MODIFY (volatile signed short *)DMA2_5_Y_MODIFY
#define pDMA2_5_CURR_DESC_PTR (volatile void **)DMA2_5_CURR_DESC_PTR
#define pDMA2_5_CURR_ADDR (volatile void **)DMA2_5_CURR_ADDR
#define pDMA2_5_CURR_X_COUNT (volatile unsigned short *)DMA2_5_CURR_X_COUNT
#define pDMA2_5_CURR_Y_COUNT (volatile unsigned short *)DMA2_5_CURR_Y_COUNT
#define pDMA2_5_IRQ_STATUS (volatile unsigned short *)DMA2_5_IRQ_STATUS
#define pDMA2_5_PERIPHERAL_MAP (volatile unsigned short *)DMA2_5_PERIPHERAL_MAP
#define pDMA2_6_CONFIG (volatile unsigned short *)DMA2_6_CONFIG
#define pDMA2_6_NEXT_DESC_PTR (volatile void **)DMA2_6_NEXT_DESC_PTR
#define pDMA2_6_START_ADDR (volatile void **)DMA2_6_START_ADDR
#define pDMA2_6_X_COUNT (volatile unsigned short *)DMA2_6_X_COUNT
#define pDMA2_6_Y_COUNT (volatile unsigned short *)DMA2_6_Y_COUNT
#define pDMA2_6_X_MODIFY (volatile signed short *)DMA2_6_X_MODIFY
#define pDMA2_6_Y_MODIFY (volatile signed short *)DMA2_6_Y_MODIFY
#define pDMA2_6_CURR_DESC_PTR (volatile void **)DMA2_6_CURR_DESC_PTR
#define pDMA2_6_CURR_ADDR (volatile void **)DMA2_6_CURR_ADDR
#define pDMA2_6_CURR_X_COUNT (volatile unsigned short *)DMA2_6_CURR_X_COUNT
#define pDMA2_6_CURR_Y_COUNT (volatile unsigned short *)DMA2_6_CURR_Y_COUNT
#define pDMA2_6_IRQ_STATUS (volatile unsigned short *)DMA2_6_IRQ_STATUS
#define pDMA2_6_PERIPHERAL_MAP (volatile unsigned short *)DMA2_6_PERIPHERAL_MAP
#define pDMA2_7_CONFIG (volatile unsigned short *)DMA2_7_CONFIG
#define pDMA2_7_NEXT_DESC_PTR (volatile void **)DMA2_7_NEXT_DESC_PTR
#define pDMA2_7_START_ADDR (volatile void **)DMA2_7_START_ADDR
#define pDMA2_7_X_COUNT (volatile unsigned short *)DMA2_7_X_COUNT
#define pDMA2_7_Y_COUNT (volatile unsigned short *)DMA2_7_Y_COUNT
#define pDMA2_7_X_MODIFY (volatile signed short *)DMA2_7_X_MODIFY
#define pDMA2_7_Y_MODIFY (volatile signed short *)DMA2_7_Y_MODIFY
#define pDMA2_7_CURR_DESC_PTR (volatile void **)DMA2_7_CURR_DESC_PTR
#define pDMA2_7_CURR_ADDR (volatile void **)DMA2_7_CURR_ADDR
#define pDMA2_7_CURR_X_COUNT (volatile unsigned short *)DMA2_7_CURR_X_COUNT
#define pDMA2_7_CURR_Y_COUNT (volatile unsigned short *)DMA2_7_CURR_Y_COUNT
#define pDMA2_7_IRQ_STATUS (volatile unsigned short *)DMA2_7_IRQ_STATUS
#define pDMA2_7_PERIPHERAL_MAP (volatile unsigned short *)DMA2_7_PERIPHERAL_MAP
#define pDMA2_8_CONFIG (volatile unsigned short *)DMA2_8_CONFIG
#define pDMA2_8_NEXT_DESC_PTR (volatile void **)DMA2_8_NEXT_DESC_PTR
#define pDMA2_8_START_ADDR (volatile void **)DMA2_8_START_ADDR
#define pDMA2_8_X_COUNT (volatile unsigned short *)DMA2_8_X_COUNT
#define pDMA2_8_Y_COUNT (volatile unsigned short *)DMA2_8_Y_COUNT
#define pDMA2_8_X_MODIFY (volatile signed short *)DMA2_8_X_MODIFY
#define pDMA2_8_Y_MODIFY (volatile signed short *)DMA2_8_Y_MODIFY
#define pDMA2_8_CURR_DESC_PTR (volatile void **)DMA2_8_CURR_DESC_PTR
#define pDMA2_8_CURR_ADDR (volatile void **)DMA2_8_CURR_ADDR
#define pDMA2_8_CURR_X_COUNT (volatile unsigned short *)DMA2_8_CURR_X_COUNT
#define pDMA2_8_CURR_Y_COUNT (volatile unsigned short *)DMA2_8_CURR_Y_COUNT
#define pDMA2_8_IRQ_STATUS (volatile unsigned short *)DMA2_8_IRQ_STATUS
#define pDMA2_8_PERIPHERAL_MAP (volatile unsigned short *)DMA2_8_PERIPHERAL_MAP
#define pDMA2_9_CONFIG (volatile unsigned short *)DMA2_9_CONFIG
#define pDMA2_9_NEXT_DESC_PTR (volatile void **)DMA2_9_NEXT_DESC_PTR
#define pDMA2_9_START_ADDR (volatile void **)DMA2_9_START_ADDR
#define pDMA2_9_X_COUNT (volatile unsigned short *)DMA2_9_X_COUNT
#define pDMA2_9_Y_COUNT (volatile unsigned short *)DMA2_9_Y_COUNT
#define pDMA2_9_X_MODIFY (volatile signed short *)DMA2_9_X_MODIFY
#define pDMA2_9_Y_MODIFY (volatile signed short *)DMA2_9_Y_MODIFY
#define pDMA2_9_CURR_DESC_PTR (volatile void **)DMA2_9_CURR_DESC_PTR
#define pDMA2_9_CURR_ADDR (volatile void **)DMA2_9_CURR_ADDR
#define pDMA2_9_CURR_X_COUNT (volatile unsigned short *)DMA2_9_CURR_X_COUNT
#define pDMA2_9_CURR_Y_COUNT (volatile unsigned short *)DMA2_9_CURR_Y_COUNT
#define pDMA2_9_IRQ_STATUS (volatile unsigned short *)DMA2_9_IRQ_STATUS
#define pDMA2_9_PERIPHERAL_MAP (volatile unsigned short *)DMA2_9_PERIPHERAL_MAP
#define pDMA2_10_CONFIG (volatile unsigned short *)DMA2_10_CONFIG
#define pDMA2_10_NEXT_DESC_PTR (volatile void **)DMA2_10_NEXT_DESC_PTR
#define pDMA2_10_START_ADDR (volatile void **)DMA2_10_START_ADDR
#define pDMA2_10_X_COUNT (volatile unsigned short *)DMA2_10_X_COUNT
#define pDMA2_10_Y_COUNT (volatile unsigned short *)DMA2_10_Y_COUNT
#define pDMA2_10_X_MODIFY (volatile signed short *)DMA2_10_X_MODIFY
#define pDMA2_10_Y_MODIFY (volatile signed short *)DMA2_10_Y_MODIFY
#define pDMA2_10_CURR_DESC_PTR (volatile void **)DMA2_10_CURR_DESC_PTR
#define pDMA2_10_CURR_ADDR (volatile void **)DMA2_10_CURR_ADDR
#define pDMA2_10_CURR_X_COUNT (volatile unsigned short *)DMA2_10_CURR_X_COUNT
#define pDMA2_10_CURR_Y_COUNT (volatile unsigned short *)DMA2_10_CURR_Y_COUNT
#define pDMA2_10_IRQ_STATUS (volatile unsigned short *)DMA2_10_IRQ_STATUS
#define pDMA2_10_PERIPHERAL_MAP (volatile unsigned short *)DMA2_10_PERIPHERAL_MAP
#define pDMA2_11_CONFIG (volatile unsigned short *)DMA2_11_CONFIG
#define pDMA2_11_NEXT_DESC_PTR (volatile void **)DMA2_11_NEXT_DESC_PTR
#define pDMA2_11_START_ADDR (volatile void **)DMA2_11_START_ADDR
#define pDMA2_11_X_COUNT (volatile unsigned short *)DMA2_11_X_COUNT
#define pDMA2_11_Y_COUNT (volatile unsigned short *)DMA2_11_Y_COUNT
#define pDMA2_11_X_MODIFY (volatile signed short *)DMA2_11_X_MODIFY
#define pDMA2_11_Y_MODIFY (volatile signed short *)DMA2_11_Y_MODIFY
#define pDMA2_11_CURR_DESC_PTR (volatile void **)DMA2_11_CURR_DESC_PTR
#define pDMA2_11_CURR_ADDR (volatile void **)DMA2_11_CURR_ADDR
#define pDMA2_11_CURR_X_COUNT (volatile unsigned short *)DMA2_11_CURR_X_COUNT
#define pDMA2_11_CURR_Y_COUNT (volatile unsigned short *)DMA2_11_CURR_Y_COUNT
#define pDMA2_11_IRQ_STATUS (volatile unsigned short *)DMA2_11_IRQ_STATUS
#define pDMA2_11_PERIPHERAL_MAP (volatile unsigned short *)DMA2_11_PERIPHERAL_MAP
/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
#define pMDMA2_D0_CONFIG (volatile unsigned short *)MDMA2_D0_CONFIG
#define pMDMA2_D0_NEXT_DESC_PTR (volatile void **)MDMA2_D0_NEXT_DESC_PTR
#define pMDMA2_D0_START_ADDR (volatile void **)MDMA2_D0_START_ADDR
#define pMDMA2_D0_X_COUNT (volatile unsigned short *)MDMA2_D0_X_COUNT
#define pMDMA2_D0_Y_COUNT (volatile unsigned short *)MDMA2_D0_Y_COUNT
#define pMDMA2_D0_X_MODIFY (volatile signed short *)MDMA2_D0_X_MODIFY
#define pMDMA2_D0_Y_MODIFY (volatile signed short *)MDMA2_D0_Y_MODIFY
#define pMDMA2_D0_CURR_DESC_PTR (volatile void **)MDMA2_D0_CURR_DESC_PTR
#define pMDMA2_D0_CURR_ADDR (volatile void **)MDMA2_D0_CURR_ADDR
#define pMDMA2_D0_CURR_X_COUNT (volatile unsigned short *)MDMA2_D0_CURR_X_COUNT
#define pMDMA2_D0_CURR_Y_COUNT (volatile unsigned short *)MDMA2_D0_CURR_Y_COUNT
#define pMDMA2_D0_IRQ_STATUS (volatile unsigned short *)MDMA2_D0_IRQ_STATUS
#define pMDMA2_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_D0_PERIPHERAL_MAP
#define pMDMA2_S0_CONFIG (volatile unsigned short *)MDMA2_S0_CONFIG
#define pMDMA2_S0_NEXT_DESC_PTR (volatile void **)MDMA2_S0_NEXT_DESC_PTR
#define pMDMA2_S0_START_ADDR (volatile void **)MDMA2_S0_START_ADDR
#define pMDMA2_S0_X_COUNT (volatile unsigned short *)MDMA2_S0_X_COUNT
#define pMDMA2_S0_Y_COUNT (volatile unsigned short *)MDMA2_S0_Y_COUNT
#define pMDMA2_S0_X_MODIFY (volatile signed short *)MDMA2_S0_X_MODIFY
#define pMDMA2_S0_Y_MODIFY (volatile signed short *)MDMA2_S0_Y_MODIFY
#define pMDMA2_S0_CURR_DESC_PTR (volatile void **)MDMA2_S0_CURR_DESC_PTR
#define pMDMA2_S0_CURR_ADDR (volatile void **)MDMA2_S0_CURR_ADDR
#define pMDMA2_S0_CURR_X_COUNT (volatile unsigned short *)MDMA2_S0_CURR_X_COUNT
#define pMDMA2_S0_CURR_Y_COUNT (volatile unsigned short *)MDMA2_S0_CURR_Y_COUNT
#define pMDMA2_S0_IRQ_STATUS (volatile unsigned short *)MDMA2_S0_IRQ_STATUS
#define pMDMA2_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_S0_PERIPHERAL_MAP
#define pMDMA2_D1_CONFIG (volatile unsigned short *)MDMA2_D1_CONFIG
#define pMDMA2_D1_NEXT_DESC_PTR (volatile void **)MDMA2_D1_NEXT_DESC_PTR
#define pMDMA2_D1_START_ADDR (volatile void **)MDMA2_D1_START_ADDR
#define pMDMA2_D1_X_COUNT (volatile unsigned short *)MDMA2_D1_X_COUNT
#define pMDMA2_D1_Y_COUNT (volatile unsigned short *)MDMA2_D1_Y_COUNT
#define pMDMA2_D1_X_MODIFY (volatile signed short *)MDMA2_D1_X_MODIFY
#define pMDMA2_D1_Y_MODIFY (volatile signed short *)MDMA2_D1_Y_MODIFY
#define pMDMA2_D1_CURR_DESC_PTR (volatile void **)MDMA2_D1_CURR_DESC_PTR
#define pMDMA2_D1_CURR_ADDR (volatile void **)MDMA2_D1_CURR_ADDR
#define pMDMA2_D1_CURR_X_COUNT (volatile unsigned short *)MDMA2_D1_CURR_X_COUNT
#define pMDMA2_D1_CURR_Y_COUNT (volatile unsigned short *)MDMA2_D1_CURR_Y_COUNT
#define pMDMA2_D1_IRQ_STATUS (volatile unsigned short *)MDMA2_D1_IRQ_STATUS
#define pMDMA2_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_D1_PERIPHERAL_MAP
#define pMDMA2_S1_CONFIG (volatile unsigned short *)MDMA2_S1_CONFIG
#define pMDMA2_S1_NEXT_DESC_PTR (volatile void **)MDMA2_S1_NEXT_DESC_PTR
#define pMDMA2_S1_START_ADDR (volatile void **)MDMA2_S1_START_ADDR
#define pMDMA2_S1_X_COUNT (volatile unsigned short *)MDMA2_S1_X_COUNT
#define pMDMA2_S1_Y_COUNT (volatile unsigned short *)MDMA2_S1_Y_COUNT
#define pMDMA2_S1_X_MODIFY (volatile signed short *)MDMA2_S1_X_MODIFY
#define pMDMA2_S1_Y_MODIFY (volatile signed short *)MDMA2_S1_Y_MODIFY
#define pMDMA2_S1_CURR_DESC_PTR (volatile void **)MDMA2_S1_CURR_DESC_PTR
#define pMDMA2_S1_CURR_ADDR (volatile void **)MDMA2_S1_CURR_ADDR
#define pMDMA2_S1_CURR_X_COUNT (volatile unsigned short *)MDMA2_S1_CURR_X_COUNT
#define pMDMA2_S1_CURR_Y_COUNT (volatile unsigned short *)MDMA2_S1_CURR_Y_COUNT
#define pMDMA2_S1_IRQ_STATUS (volatile unsigned short *)MDMA2_S1_IRQ_STATUS
#define pMDMA2_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_S1_PERIPHERAL_MAP
/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
#define pIMDMA_D0_CONFIG (volatile unsigned short *)IMDMA_D0_CONFIG
#define pIMDMA_D0_NEXT_DESC_PTR (volatile void **)IMDMA_D0_NEXT_DESC_PTR
#define pIMDMA_D0_START_ADDR (volatile void **)IMDMA_D0_START_ADDR
#define pIMDMA_D0_X_COUNT (volatile unsigned short *)IMDMA_D0_X_COUNT
#define pIMDMA_D0_Y_COUNT (volatile unsigned short *)IMDMA_D0_Y_COUNT
#define pIMDMA_D0_X_MODIFY (volatile signed short *)IMDMA_D0_X_MODIFY
#define pIMDMA_D0_Y_MODIFY (volatile signed short *)IMDMA_D0_Y_MODIFY
#define pIMDMA_D0_CURR_DESC_PTR (volatile void **)IMDMA_D0_CURR_DESC_PTR
#define pIMDMA_D0_CURR_ADDR (volatile void **)IMDMA_D0_CURR_ADDR
#define pIMDMA_D0_CURR_X_COUNT (volatile unsigned short *)IMDMA_D0_CURR_X_COUNT
#define pIMDMA_D0_CURR_Y_COUNT (volatile unsigned short *)IMDMA_D0_CURR_Y_COUNT
#define pIMDMA_D0_IRQ_STATUS (volatile unsigned short *)IMDMA_D0_IRQ_STATUS
#define pIMDMA_S0_CONFIG (volatile unsigned short *)IMDMA_S0_CONFIG
#define pIMDMA_S0_NEXT_DESC_PTR (volatile void **)IMDMA_S0_NEXT_DESC_PTR
#define pIMDMA_S0_START_ADDR (volatile void **)IMDMA_S0_START_ADDR
#define pIMDMA_S0_X_COUNT (volatile unsigned short *)IMDMA_S0_X_COUNT
#define pIMDMA_S0_Y_COUNT (volatile unsigned short *)IMDMA_S0_Y_COUNT
#define pIMDMA_S0_X_MODIFY (volatile signed short *)IMDMA_S0_X_MODIFY
#define pIMDMA_S0_Y_MODIFY (volatile signed short *)IMDMA_S0_Y_MODIFY
#define pIMDMA_S0_CURR_DESC_PTR (volatile void **)IMDMA_S0_CURR_DESC_PTR
#define pIMDMA_S0_CURR_ADDR (volatile void **)IMDMA_S0_CURR_ADDR
#define pIMDMA_S0_CURR_X_COUNT (volatile unsigned short *)IMDMA_S0_CURR_X_COUNT
#define pIMDMA_S0_CURR_Y_COUNT (volatile unsigned short *)IMDMA_S0_CURR_Y_COUNT
#define pIMDMA_S0_IRQ_STATUS (volatile unsigned short *)IMDMA_S0_IRQ_STATUS
#define pIMDMA_D1_CONFIG (volatile unsigned short *)IMDMA_D1_CONFIG
#define pIMDMA_D1_NEXT_DESC_PTR (volatile void **)IMDMA_D1_NEXT_DESC_PTR
#define pIMDMA_D1_START_ADDR (volatile void **)IMDMA_D1_START_ADDR
#define pIMDMA_D1_X_COUNT (volatile unsigned short *)IMDMA_D1_X_COUNT
#define pIMDMA_D1_Y_COUNT (volatile unsigned short *)IMDMA_D1_Y_COUNT
#define pIMDMA_D1_X_MODIFY (volatile signed short *)IMDMA_D1_X_MODIFY
#define pIMDMA_D1_Y_MODIFY (volatile signed short *)IMDMA_D1_Y_MODIFY
#define pIMDMA_D1_CURR_DESC_PTR (volatile void **)IMDMA_D1_CURR_DESC_PTR
#define pIMDMA_D1_CURR_ADDR (volatile void **)IMDMA_D1_CURR_ADDR
#define pIMDMA_D1_CURR_X_COUNT (volatile unsigned short *)IMDMA_D1_CURR_X_COUNT
#define pIMDMA_D1_CURR_Y_COUNT (volatile unsigned short *)IMDMA_D1_CURR_Y_COUNT
#define pIMDMA_D1_IRQ_STATUS (volatile unsigned short *)IMDMA_D1_IRQ_STATUS
#define pIMDMA_S1_CONFIG (volatile unsigned short *)IMDMA_S1_CONFIG
#define pIMDMA_S1_NEXT_DESC_PTR (volatile void **)IMDMA_S1_NEXT_DESC_PTR
#define pIMDMA_S1_START_ADDR (volatile void **)IMDMA_S1_START_ADDR
#define pIMDMA_S1_X_COUNT (volatile unsigned short *)IMDMA_S1_X_COUNT
#define pIMDMA_S1_Y_COUNT (volatile unsigned short *)IMDMA_S1_Y_COUNT
#define pIMDMA_S1_X_MODIFY (volatile signed short *)IMDMA_S1_X_MODIFY
#define pIMDMA_S1_Y_MODIFY (volatile signed short *)IMDMA_S1_Y_MODIFY
#define pIMDMA_S1_CURR_DESC_PTR (volatile void **)IMDMA_S1_CURR_DESC_PTR
#define pIMDMA_S1_CURR_ADDR (volatile void **)IMDMA_S1_CURR_ADDR
#define pIMDMA_S1_CURR_X_COUNT (volatile unsigned short *)IMDMA_S1_CURR_X_COUNT
#define pIMDMA_S1_CURR_Y_COUNT (volatile unsigned short *)IMDMA_S1_CURR_Y_COUNT
#define pIMDMA_S1_IRQ_STATUS (volatile unsigned short *)IMDMA_S1_IRQ_STATUS
/*
* System Reset and Interrupt Controller registers for
* core A (0xFFC0 0100-0xFFC0 01FF)
*/
#define pSWRST (volatile unsigned short *)SICA_SWRST
#define pSYSCR (volatile unsigned short *)SICA_SYSCR
#define pRVECT (volatile unsigned short *)SICA_RVECT
#define pSIC_SWRST (volatile unsigned short *)SICA_SWRST
#define pSIC_SYSCR (volatile unsigned short *)SICA_SYSCR
#define pSIC_RVECT (volatile unsigned short *)SICA_RVECT
#define pSIC_IMASK (volatile unsigned long *)SICA_IMASK
#define pSIC_IAR0 ((volatile unsigned long *)SICA_IAR0)
#define pSIC_IAR1 (volatile unsigned long *)SICA_IAR1
#define pSIC_IAR2 (volatile unsigned long *)SICA_IAR2
#define pSIC_ISR (volatile unsigned long *)SICA_ISR0
#define pSIC_IWR (volatile unsigned long *)SICA_IWR0
/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
#define pWDOG_CTL (volatile unsigned short *)WDOGA_CTL
#define pWDOG_CNT (volatile unsigned long *)WDOGA_CNT
#define pWDOG_STAT (volatile unsigned long *)WDOGA_STAT
/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
#define pFIO_FLAG_D (volatile unsigned short *)FIO0_FLAG_D
#define pFIO_FLAG_C (volatile unsigned short *)FIO0_FLAG_C
#define pFIO_FLAG_S (volatile unsigned short *)FIO0_FLAG_S
#define pFIO_FLAG_T (volatile unsigned short *)FIO0_FLAG_T
#define pFIO_MASKA_D (volatile unsigned short *)FIO0_MASKA_D
#define pFIO_MASKA_C (volatile unsigned short *)FIO0_MASKA_C
#define pFIO_MASKA_S (volatile unsigned short *)FIO0_MASKA_S
#define pFIO_MASKA_T (volatile unsigned short *)FIO0_MASKA_T
#define pFIO_MASKB_D (volatile unsigned short *)FIO0_MASKB_D
#define pFIO_MASKB_C (volatile unsigned short *)FIO0_MASKB_C
#define pFIO_MASKB_S (volatile unsigned short *)FIO0_MASKB_S
#define pFIO_MASKB_T (volatile unsigned short *)FIO0_MASKB_T
#define pFIO_DIR (volatile unsigned short *)FIO0_DIR
#define pFIO_POLAR (volatile unsigned short *)FIO0_POLAR
#define pFIO_EDGE (volatile unsigned short *)FIO0_EDGE
#define pFIO_BOTH (volatile unsigned short *)FIO0_BOTH
#define pFIO_INEN (volatile unsigned short *)FIO0_INEN
/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF)*/
#define pPPI_CONTROL (volatile unsigned short *)PPI0_CONTROL
#define pPPI_STATUS (volatile unsigned short *)PPI0_STATUS
#define pPPI_COUNT (volatile unsigned short *)PPI0_COUNT
#define pPPI_DELAY (volatile unsigned short *)PPI0_DELAY
#define pPPI_FRAME (volatile unsigned short *)PPI0_FRAME
/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
#define pDMA0_CONFIG (volatile unsigned short *)DMA1_0_CONFIG
#define pDMA0_NEXT_DESC_PTR (volatile void **)DMA1_0_NEXT_DESC_PTR
#define pDMA0_START_ADDR (volatile void **)DMA1_0_START_ADDR
#define pDMA0_X_COUNT (volatile unsigned short *)DMA1_0_X_COUNT
#define pDMA0_Y_COUNT (volatile unsigned short *)DMA1_0_Y_COUNT
#define pDMA0_X_MODIFY (volatile unsigned short *)DMA1_0_X_MODIFY
#define pDMA0_Y_MODIFY (volatile unsigned short *)DMA1_0_Y_MODIFY
#define pDMA0_CURR_DESC_PTR (volatile void **)DMA1_0_CURR_DESC_PTR
#define pDMA0_CURR_ADDR (volatile void **)DMA1_0_CURR_ADDR
#define pDMA0_CURR_X_COUNT (volatile unsigned short *)DMA1_0_CURR_X_COUNT
#define pDMA0_CURR_Y_COUNT (volatile unsigned short *)DMA1_0_CURR_Y_COUNT
#define pDMA0_IRQ_STATUS (volatile unsigned short *)DMA1_0_IRQ_STATUS
#define pDMA0_PERIPHERAL_MAP (volatile unsigned short *)DMA1_0_PERIPHERAL_MAP
/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
#define pMDMA_D0_CONFIG (volatile unsigned short *)MDMA1_D0_CONFIG
#define pMDMA_D0_NEXT_DESC_PTR (volatile void **)MDMA1_D0_NEXT_DESC_PTR
#define pMDMA_D0_START_ADDR (volatile void **)MDMA1_D0_START_ADDR
#define pMDMA_D0_X_COUNT (volatile unsigned short *)MDMA1_D0_X_COUNT
#define pMDMA_D0_Y_COUNT (volatile unsigned short *)MDMA1_D0_Y_COUNT
#define pMDMA_D0_X_MODIFY (volatile unsigned short *)MDMA1_D0_X_MODIFY
#define pMDMA_D0_Y_MODIFY (volatile unsigned short *)MDMA1_D0_Y_MODIFY
#define pMDMA_D0_CURR_DESC_PTR (volatile void **)MDMA1_D0_CURR_DESC_PTR
#define pMDMA_D0_CURR_ADDR (volatile void **)MDMA1_D0_CURR_ADDR
#define pMDMA_D0_CURR_X_COUNT (volatile unsigned short *)MDMA1_D0_CURR_X_COUNT
#define pMDMA_D0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D0_CURR_Y_COUNT
#define pMDMA_D0_IRQ_STATUS (volatile unsigned short *)MDMA1_D0_IRQ_STATUS
#define pMDMA_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D0_PERIPHERAL_MAP
#define pMDMA_S0_CONFIG (volatile unsigned short *)MDMA1_S0_CONFIG
#define pMDMA_S0_NEXT_DESC_PTR (volatile void **)MDMA1_S0_NEXT_DESC_PTR
#define pMDMA_S0_START_ADDR (volatile void **)MDMA1_S0_START_ADDR
#define pMDMA_S0_X_COUNT (volatile unsigned short *)MDMA1_S0_X_COUNT
#define pMDMA_S0_Y_COUNT (volatile unsigned short *)MDMA1_S0_Y_COUNT
#define pMDMA_S0_X_MODIFY (volatile unsigned short *)MDMA1_S0_X_MODIFY
#define pMDMA_S0_Y_MODIFY (volatile unsigned short *)MDMA1_S0_Y_MODIFY
#define pMDMA_S0_CURR_DESC_PTR (volatile void **)MDMA1_S0_CURR_DESC_PTR
#define pMDMA_S0_CURR_ADDR (volatile void **)MDMA1_S0_CURR_ADDR
#define pMDMA_S0_CURR_X_COUNT (volatile unsigned short *)MDMA1_S0_CURR_X_COUNT
#define pMDMA_S0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S0_CURR_Y_COUNT
#define pMDMA_S0_IRQ_STATUS (volatile unsigned short *)MDMA1_S0_IRQ_STATUS
#define pMDMA_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S0_PERIPHERAL_MAP
#define pMDMA_D1_CONFIG (volatile unsigned short *)MDMA1_D1_CONFIG
#define pMDMA_D1_NEXT_DESC_PTR (volatile void **)MDMA1_D1_NEXT_DESC_PTR
#define pMDMA_D1_START_ADDR (volatile void **)MDMA1_D1_START_ADDR
#define pMDMA_D1_X_COUNT (volatile unsigned short *)MDMA1_D1_X_COUNT
#define pMDMA_D1_Y_COUNT (volatile unsigned short *)MDMA1_D1_Y_COUNT
#define pMDMA_D1_X_MODIFY (volatile unsigned short *)MDMA1_D1_X_MODIFY
#define pMDMA_D1_Y_MODIFY (volatile unsigned short *)MDMA1_D1_Y_MODIFY
#define pMDMA_D1_CURR_DESC_PTR (volatile void **)MDMA1_D1_CURR_DESC_PTR
#define pMDMA_D1_CURR_ADDR (volatile void **)MDMA1_D1_CURR_ADDR
#define pMDMA_D1_CURR_X_COUNT (volatile unsigned short *)MDMA1_D1_CURR_X_COUNT
#define pMDMA_D1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D1_CURR_Y_COUNT
#define pMDMA_D1_IRQ_STATUS (volatile unsigned short *)MDMA1_D1_IRQ_STATUS
#define pMDMA_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D1_PERIPHERAL_MAP
#define pMDMA_S1_CONFIG (volatile unsigned short *)MDMA1_S1_CONFIG
#define pMDMA_S1_NEXT_DESC_PTR (volatile void **)MDMA1_S1_NEXT_DESC_PTR
#define pMDMA_S1_START_ADDR (volatile void **)MDMA1_S1_START_ADDR
#define pMDMA_S1_X_COUNT (volatile unsigned short *)MDMA1_S1_X_COUNT
#define pMDMA_S1_Y_COUNT (volatile unsigned short *)MDMA1_S1_Y_COUNT
#define pMDMA_S1_X_MODIFY (volatile unsigned short *)MDMA1_S1_X_MODIFY
#define pMDMA_S1_Y_MODIFY (volatile unsigned short *)MDMA1_S1_Y_MODIFY
#define pMDMA_S1_CURR_DESC_PTR (volatile void **)MDMA1_S1_CURR_DESC_PTR
#define pMDMA_S1_CURR_ADDR (volatile void **)MDMA1_S1_CURR_ADDR
#define pMDMA_S1_CURR_X_COUNT (volatile unsigned short *)MDMA1_S1_CURR_X_COUNT
#define pMDMA_S1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S1_CURR_Y_COUNT
#define pMDMA_S1_IRQ_STATUS (volatile unsigned short *)MDMA1_S1_IRQ_STATUS
#define pMDMA_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S1_PERIPHERAL_MAP
/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
#define pDMA1_CONFIG (volatile unsigned short *)DMA2_0_CONFIG
#define pDMA1_NEXT_DESC_PTR (volatile void **)DMA2_0_NEXT_DESC_PTR
#define pDMA1_START_ADDR (volatile void **)DMA2_0_START_ADDR
#define pDMA1_X_COUNT (volatile unsigned short *)DMA2_0_X_COUNT
#define pDMA1_Y_COUNT (volatile unsigned short *)DMA2_0_Y_COUNT
#define pDMA1_X_MODIFY (volatile unsigned short *)DMA2_0_X_MODIFY
#define pDMA1_Y_MODIFY (volatile unsigned short *)DMA2_0_Y_MODIFY
#define pDMA1_CURR_DESC_PTR (volatile void **)DMA2_0_CURR_DESC_PTR
#define pDMA1_CURR_ADDR (volatile void **)DMA2_0_CURR_ADDR
#define pDMA1_CURR_X_COUNT (volatile unsigned short *)DMA2_0_CURR_X_COUNT
#define pDMA1_CURR_Y_COUNT (volatile unsigned short *)DMA2_0_CURR_Y_COUNT
#define pDMA1_IRQ_STATUS (volatile unsigned short *)DMA2_0_IRQ_STATUS
#define pDMA1_PERIPHERAL_MAP (volatile unsigned short *)DMA2_0_PERIPHERAL_MAP
#define pDMA2_CONFIG (volatile unsigned short *)DMA2_1_CONFIG
#define pDMA2_NEXT_DESC_PTR (volatile void **)DMA2_1_NEXT_DESC_PTR
#define pDMA2_START_ADDR (volatile void **)DMA2_1_START_ADDR
#define pDMA2_X_COUNT (volatile unsigned short *)DMA2_1_X_COUNT
#define pDMA2_Y_COUNT (volatile unsigned short *)DMA2_1_Y_COUNT
#define pDMA2_X_MODIFY (volatile unsigned short *)DMA2_1_X_MODIFY
#define pDMA2_Y_MODIFY (volatile unsigned short *)DMA2_1_Y_MODIFY
#define pDMA2_CURR_DESC_PTR (volatile void **)DMA2_1_CURR_DESC_PTR
#define pDMA2_CURR_ADDR (volatile void **)DMA2_1_CURR_ADDR
#define pDMA2_CURR_X_COUNT (volatile unsigned short *)DMA2_1_CURR_X_COUNT
#define pDMA2_CURR_Y_COUNT (volatile unsigned short *)DMA2_1_CURR_Y_COUNT
#define pDMA2_IRQ_STATUS (volatile unsigned short *)DMA2_1_IRQ_STATUS
#define pDMA2_PERIPHERAL_MAP (volatile unsigned short *)DMA2_1_PERIPHERAL_MAP
#define pDMA3_CONFIG (volatile unsigned short *)DMA2_2_CONFIG
#define pDMA3_NEXT_DESC_PTR (volatile void **)DMA2_2_NEXT_DESC_PTR
#define pDMA3_START_ADDR (volatile void **)DMA2_2_START_ADDR
#define pDMA3_X_COUNT (volatile unsigned short *)DMA2_2_X_COUNT
#define pDMA3_Y_COUNT (volatile unsigned short *)DMA2_2_Y_COUNT
#define pDMA3_X_MODIFY (volatile unsigned short *)DMA2_2_X_MODIFY
#define pDMA3_Y_MODIFY (volatile unsigned short *)DMA2_2_Y_MODIFY
#define pDMA3_CURR_DESC_PTR (volatile void **)DMA2_2_CURR_DESC_PTR
#define pDMA3_CURR_ADDR (volatile void **)DMA2_2_CURR_ADDR
#define pDMA3_CURR_X_COUNT (volatile unsigned short *)DMA2_2_CURR_X_COUNT
#define pDMA3_CURR_Y_COUNT (volatile unsigned short *)DMA2_2_CURR_Y_COUNT
#define pDMA3_IRQ_STATUS (volatile unsigned short *)DMA2_2_IRQ_STATUS
#define pDMA3_PERIPHERAL_MAP (volatile unsigned short *)DMA2_2_PERIPHERAL_MAP
#define pDMA4_CONFIG (volatile unsigned short *)DMA2_3_CONFIG
#define pDMA4_NEXT_DESC_PTR (volatile void **)DMA2_3_NEXT_DESC_PTR
#define pDMA4_START_ADDR (volatile void **)DMA2_3_START_ADDR
#define pDMA4_X_COUNT (volatile unsigned short *)DMA2_3_X_COUNT
#define pDMA4_Y_COUNT (volatile unsigned short *)DMA2_3_Y_COUNT
#define pDMA4_X_MODIFY (volatile unsigned short *)DMA2_3_X_MODIFY
#define pDMA4_Y_MODIFY (volatile unsigned short *)DMA2_3_Y_MODIFY
#define pDMA4_CURR_DESC_PTR (volatile void **)DMA2_3_CURR_DESC_PTR
#define pDMA4_CURR_ADDR (volatile void **)DMA2_3_CURR_ADDR
#define pDMA4_CURR_X_COUNT (volatile unsigned short *)DMA2_3_CURR_X_COUNT
#define pDMA4_CURR_Y_COUNT (volatile unsigned short *)DMA2_3_CURR_Y_COUNT
#define pDMA4_IRQ_STATUS (volatile unsigned short *)DMA2_3_IRQ_STATUS
#define pDMA4_PERIPHERAL_MAP (volatile unsigned short *)DMA2_3_PERIPHERAL_MAP
#define pDMA5_CONFIG (volatile unsigned short *)DMA2_4_CONFIG
#define pDMA5_NEXT_DESC_PTR (volatile void **)DMA2_4_NEXT_DESC_PTR
#define pDMA5_START_ADDR (volatile void **)DMA2_4_START_ADDR
#define pDMA5_X_COUNT (volatile unsigned short *)DMA2_4_X_COUNT
#define pDMA5_Y_COUNT (volatile unsigned short *)DMA2_4_Y_COUNT
#define pDMA5_X_MODIFY (volatile unsigned short *)DMA2_4_X_MODIFY
#define pDMA5_Y_MODIFY (volatile unsigned short *)DMA2_4_Y_MODIFY
#define pDMA5_CURR_DESC_PTR (volatile void **)DMA2_4_CURR_DESC_PTR
#define pDMA5_CURR_ADDR (volatile void **)DMA2_4_CURR_ADDR
#define pDMA5_CURR_X_COUNT (volatile unsigned short *)DMA2_4_CURR_X_COUNT
#define pDMA5_CURR_Y_COUNT (volatile unsigned short *)DMA2_4_CURR_Y_COUNT
#define pDMA5_IRQ_STATUS (volatile unsigned short *)DMA2_4_IRQ_STATUS
#define pDMA5_PERIPHERAL_MAP (volatile unsigned short *)DMA2_4_PERIPHERAL_MAP
#define pDMA6_CONFIG (volatile unsigned short *)DMA2_5_CONFIG
#define pDMA6_NEXT_DESC_PTR (volatile void **)DMA2_5_NEXT_DESC_PTR
#define pDMA6_START_ADDR (volatile void **)DMA2_5_START_ADDR
#define pDMA6_X_COUNT (volatile unsigned short *)DMA2_5_X_COUNT
#define pDMA6_Y_COUNT (volatile unsigned short *)DMA2_5_Y_COUNT
#define pDMA6_X_MODIFY (volatile unsigned short *)DMA2_5_X_MODIFY
#define pDMA6_Y_MODIFY (volatile unsigned short *)DMA2_5_Y_MODIFY
#define pDMA6_CURR_DESC_PTR (volatile void **)DMA2_5_CURR_DESC_PTR
#define pDMA6_CURR_ADDR (volatile void **)DMA2_5_CURR_ADDR
#define pDMA6_CURR_X_COUNT (volatile unsigned short *)DMA2_5_CURR_X_COUNT
#define pDMA6_CURR_Y_COUNT (volatile unsigned short *)DMA2_5_CURR_Y_COUNT
#define pDMA6_IRQ_STATUS (volatile unsigned short *)DMA2_5_IRQ_STATUS
#define pDMA6_PERIPHERAL_MAP (volatile unsigned short *)DMA2_5_PERIPHERAL_MAP
#define pDMA7_CONFIG (volatile unsigned short *)DMA2_6_CONFIG
#define pDMA7_NEXT_DESC_PTR (volatile void **)DMA2_6_NEXT_DESC_PTR
#define pDMA7_START_ADDR (volatile void **)DMA2_6_START_ADDR
#define pDMA7_X_COUNT (volatile unsigned short *)DMA2_6_X_COUNT
#define pDMA7_Y_COUNT (volatile unsigned short *)DMA2_6_Y_COUNT
#define pDMA7_X_MODIFY (volatile unsigned short *)DMA2_6_X_MODIFY
#define pDMA7_Y_MODIFY (volatile unsigned short *)DMA2_6_Y_MODIFY
#define pDMA7_CURR_DESC_PTR (volatile void **)DMA2_6_CURR_DESC_PTR
#define pDMA7_CURR_ADDR (volatile void **)DMA2_6_CURR_ADDR
#define pDMA7_CURR_X_COUNT (volatile unsigned short *)DMA2_6_CURR_X_COUNT
#define pDMA7_CURR_Y_COUNT (volatile unsigned short *)DMA2_6_CURR_Y_COUNT
#define pDMA7_IRQ_STATUS (volatile unsigned short *)DMA2_6_IRQ_STATUS
#define pDMA7_PERIPHERAL_MAP (volatile unsigned short *)DMA2_6_PERIPHERAL_MAP
#endif /* _CDEF_BF561_H */

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include/asm-blackfin/arch-bf561/defBF561.h
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