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driver/ddr: Add 256 byte interleaving support

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Freescale LayerScape SoCs support controller interleaving on 256 byte size.
This interleaving is mandoratory.

Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
York Sun 2014-02-10 13:59:44 -08:00 • committed by Tom Rini
parent 6b9e309a8a
commit 6b1e1254f3
6 changed files with 26 additions and 2 deletions
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1
include/fsl_ddr_sdram.h
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@ -76,6 +76,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#define FSL_DDR_PAGE_INTERLEAVING 0x1
#define FSL_DDR_BANK_INTERLEAVING 0x2
#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
#define FSL_DDR_256B_INTERLEAVING 0x8
#define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA
#define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC
#define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD