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driver/ddr: Add 256 byte interleaving support

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Freescale LayerScape SoCs support controller interleaving on 256 byte size.
This interleaving is mandoratory.

Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
York Sun 2014-02-10 13:59:44 -08:00 • committed by Tom Rini
parent 6b9e309a8a
commit 6b1e1254f3
6 changed files with 26 additions and 2 deletions
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3
drivers/ddr/fsl/util.c
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@ -228,6 +228,9 @@ void board_add_ram_info(int use_default)
puts(" DDR Controller Interleaving Mode: ");
switch ((cs0_config >> 24) & 0xf) {
case FSL_DDR_256B_INTERLEAVING:
puts("256B");
break;
case FSL_DDR_CACHE_LINE_INTERLEAVING:
puts("cache line");
break;