mirror of
https://github.com/u-boot/u-boot.git
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Subtree merge tag 'v6.12-dts' of dts repo [1] into dts/upstream
[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git Based on what "git diff" suggests, rename a device tree for imx8mm_venice_defconfig and imx8mp_venice_defconfig Signed-off-by: Tom Rini <trini@konsulko.com> --- Cc: Tim Harvey <tharvey@gateworks.com>
This commit is contained in:
Tom Rini
commit
6a042f830f
1212 changed files with 55613 additions and 12429 deletions
|
|
@ -81,7 +81,7 @@ CONFIG_CMD_EXT4_WRITE=y
|
|||
# CONFIG_SPL_EFI_PARTITION is not set
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIST="freescale/imx8mm-venice-gw71xx-0x freescale/imx8mm-venice-gw72xx-0x freescale/imx8mm-venice-gw73xx-0x freescale/imx8mm-venice-gw7901 freescale/imx8mm-venice-gw7902 freescale/imx8mm-venice-gw7903 freescale/imx8mm-venice-gw7904 freescale/imx8mm-venice-gw7905-0x"
|
||||
CONFIG_OF_LIST="freescale/imx8mm-venice-gw71xx-0x freescale/imx8mm-venice-gw72xx-0x freescale/imx8mm-venice-gw73xx-0x freescale/imx8mm-venice-gw7901 freescale/imx8mm-venice-gw7902 freescale/imx8mm-venice-gw7903 freescale/imx8mm-venice-gw7904 freescale/imx8mm-venice-gw75xx-0x"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_SYS_MMC_ENV_DEV=2
|
||||
|
|
|
|||
|
|
@ -83,7 +83,7 @@ CONFIG_CMD_EXT4_WRITE=y
|
|||
# CONFIG_SPL_EFI_PARTITION is not set
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIST="freescale/imx8mp-venice-gw71xx-2x freescale/imx8mp-venice-gw72xx-2x freescale/imx8mp-venice-gw73xx-2x freescale/imx8mp-venice-gw74xx freescale/imx8mp-venice-gw7905-2x"
|
||||
CONFIG_OF_LIST="freescale/imx8mp-venice-gw71xx-2x freescale/imx8mp-venice-gw72xx-2x freescale/imx8mp-venice-gw73xx-2x freescale/imx8mp-venice-gw74xx freescale/imx8mp-venice-gw75xx-2x"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_SYS_MMC_ENV_DEV=2
|
||||
|
|
|
|||
|
|
@ -1,17 +0,0 @@
|
|||
* ARC HS Performance Counters
|
||||
|
||||
The ARC HS can be configured with a pipeline performance monitor for counting
|
||||
CPU and cache events like cache misses and hits. Like conventional PCT there
|
||||
are 100+ hardware conditions dynamically mapped to up to 32 counters.
|
||||
It also supports overflow interrupts.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should contain
|
||||
"snps,archs-pct"
|
||||
|
||||
Example:
|
||||
|
||||
pmu {
|
||||
compatible = "snps,archs-pct";
|
||||
};
|
||||
33
dts/upstream/Bindings/arc/snps,archs-pct.yaml
Normal file
33
dts/upstream/Bindings/arc/snps,archs-pct.yaml
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arc/snps,archs-pct.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARC HS Performance Counters
|
||||
|
||||
maintainers:
|
||||
- Aryabhatta Dey <aryabhattadey35@gmail.com>
|
||||
|
||||
description:
|
||||
The ARC HS can be configured with a pipeline performance monitor for counting
|
||||
CPU and cache events like cache misses and hits. Like conventional PCT there
|
||||
are 100+ hardware conditions dynamically mapped to up to 32 counters.
|
||||
It also supports overflow interrupts.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: snps,archs-pct
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
|
@ -25,10 +25,18 @@ select:
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: amlogic,meson-gx-ao-secure
|
||||
- const: syscon
|
||||
|
||||
oneOf:
|
||||
- items:
|
||||
- const: amlogic,meson-gx-ao-secure
|
||||
- const: syscon
|
||||
- items:
|
||||
- enum:
|
||||
- amlogic,a4-ao-secure
|
||||
- amlogic,c3-ao-secure
|
||||
- amlogic,s4-ao-secure
|
||||
- amlogic,t7-ao-secure
|
||||
- const: amlogic,meson-gx-ao-secure
|
||||
- const: syscon
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ description: |
|
|||
The Coresight dummy source component is for the specific coresight source
|
||||
devices kernel don't have permission to access or configure. For some SOCs,
|
||||
there would be Coresight source trace components on sub-processor which
|
||||
are conneted to AP processor via debug bus. For these devices, a dummy driver
|
||||
are connected to AP processor via debug bus. For these devices, a dummy driver
|
||||
is needed to register them as Coresight source devices, so that paths can be
|
||||
created in the driver. It provides Coresight API for operations on dummy
|
||||
source devices, such as enabling and disabling them. It also provides the
|
||||
|
|
|
|||
|
|
@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: ARM Corstone1000
|
||||
|
||||
maintainers:
|
||||
- Vishnu Banavath <vishnu.banavath@arm.com>
|
||||
- Rui Miguel Silva <rui.silva@linaro.org>
|
||||
- Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
|
||||
- Hugues Kamba Mpiana <hugues.kambampiana@arm.com>
|
||||
|
||||
description: |+
|
||||
ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that
|
||||
|
|
|
|||
|
|
@ -79,6 +79,7 @@ properties:
|
|||
- aspeed,ast2600-evb-a1
|
||||
- asus,x4tf-bmc
|
||||
- facebook,bletchley-bmc
|
||||
- facebook,catalina-bmc
|
||||
- facebook,cloudripper-bmc
|
||||
- facebook,elbert-bmc
|
||||
- facebook,fuji-bmc
|
||||
|
|
@ -86,7 +87,9 @@ properties:
|
|||
- facebook,harma-bmc
|
||||
- facebook,minerva-cmc
|
||||
- facebook,yosemite4-bmc
|
||||
- ibm,blueridge-bmc
|
||||
- ibm,everest-bmc
|
||||
- ibm,fuji-bmc
|
||||
- ibm,rainier-bmc
|
||||
- ibm,system1-bmc
|
||||
- ibm,tacoma-bmc
|
||||
|
|
|
|||
|
|
@ -11,7 +11,8 @@ PIT Timer required properties:
|
|||
shared across all System Controller members.
|
||||
|
||||
PIT64B Timer required properties:
|
||||
- compatible: Should be "microchip,sam9x60-pit64b"
|
||||
- compatible: Should be "microchip,sam9x60-pit64b" or
|
||||
"microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"
|
||||
- reg: Should contain registers location and length
|
||||
- interrupts: Should contain interrupt for PIT64B timer
|
||||
- clocks: Should contain the available clock sources for PIT64B timer.
|
||||
|
|
@ -31,7 +32,8 @@ RAMC SDRAM/DDR Controller required properties:
|
|||
"atmel,at91sam9g45-ddramc",
|
||||
"atmel,sama5d3-ddramc",
|
||||
"microchip,sam9x60-ddramc",
|
||||
"microchip,sama7g5-uddrc"
|
||||
"microchip,sama7g5-uddrc",
|
||||
"microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc".
|
||||
- reg: Should contain registers location and length
|
||||
|
||||
Examples:
|
||||
|
|
|
|||
38
dts/upstream/Bindings/arm/cirrus/cirrus,ep9301.yaml
Normal file
38
dts/upstream/Bindings/arm/cirrus/cirrus,ep9301.yaml
Normal file
|
|
@ -0,0 +1,38 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/cirrus/cirrus,ep9301.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Cirrus Logic EP93xx platforms
|
||||
|
||||
description:
|
||||
The EP93xx SoC is a ARMv4T-based with 200 MHz ARM9 CPU.
|
||||
|
||||
maintainers:
|
||||
- Alexander Sverdlin <alexander.sverdlin@gmail.com>
|
||||
- Nikita Shubin <nikita.shubin@maquefel.me>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: The TS-7250 is a compact, full-featured Single Board
|
||||
Computer (SBC) based upon the Cirrus EP9302 ARM9 CPU
|
||||
items:
|
||||
- const: technologic,ts7250
|
||||
- const: cirrus,ep9301
|
||||
|
||||
- description: The Liebherr BK3 is a derivate from ts7250 board
|
||||
items:
|
||||
- const: liebherr,bk3
|
||||
- const: cirrus,ep9301
|
||||
|
||||
- description: EDB302 is an evaluation board by Cirrus Logic,
|
||||
based on a Cirrus Logic EP9302 CPU
|
||||
items:
|
||||
- const: cirrus,edb9302
|
||||
- const: cirrus,ep9301
|
||||
|
||||
additionalProperties: true
|
||||
|
|
@ -809,19 +809,19 @@ properties:
|
|||
- const: kontron,sl-imx6ull # Kontron SL i.MX6ULL SoM
|
||||
- const: fsl,imx6ull
|
||||
|
||||
- description: TQ Systems TQMa6ULLx SoM on MBa6ULx board
|
||||
- description: TQ-Systems TQMa6ULLx SoM on MBa6ULx board
|
||||
items:
|
||||
- enum:
|
||||
- tq,imx6ull-tqma6ull2-mba6ulx
|
||||
- const: tq,imx6ull-tqma6ull2 # MCIMX6Y2
|
||||
- tq,imx6ull-tqma6ull2-mba6ulx # TQMa6ULL socketable SoM with MCIMX6Y2 on MBa6ULx EVK
|
||||
- const: tq,imx6ull-tqma6ull2 # TQMa6ULL socketable SoM with MCIMX6Y2
|
||||
- const: fsl,imx6ull
|
||||
|
||||
- description: TQ Systems TQMa6ULLxL SoM on MBa6ULx[L] board
|
||||
- description: TQ-Systems TQMa6ULLxL SoM on MBa6ULx[L] board
|
||||
items:
|
||||
- enum:
|
||||
- tq,imx6ull-tqma6ull2l-mba6ulx # using LGA adapter
|
||||
- tq,imx6ull-tqma6ull2l-mba6ulxl
|
||||
- const: tq,imx6ull-tqma6ull2l # MCIMX6Y2, LGA SoM variant
|
||||
- tq,imx6ull-tqma6ull2l-mba6ulx # TQMa6ULLxL LGA SoM with socketable Adapter on MBa6ULx EVK
|
||||
- tq,imx6ull-tqma6ull2l-mba6ulxl # TQMa6ULLxL LGA SoM on MBa6ULxL gateway board
|
||||
- const: tq,imx6ull-tqma6ull2l # TQMa6ULLxL LGA SoM with MCIMX6Y2
|
||||
- const: fsl,imx6ull
|
||||
|
||||
- description: Seeed Stuido i.MX6ULL SoM on dev boards
|
||||
|
|
@ -939,8 +939,8 @@ properties:
|
|||
- fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board
|
||||
- fsl,imx8mm-evk # i.MX8MM EVK Board
|
||||
- fsl,imx8mm-evkb # i.MX8MM EVKB Board
|
||||
- gateworks,imx8mm-gw75xx-0x # i.MX8MM Gateworks Board
|
||||
- gateworks,imx8mm-gw7904
|
||||
- gateworks,imx8mm-gw7905-0x # i.MX8MM Gateworks Board
|
||||
- gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit
|
||||
- gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit
|
||||
- gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit
|
||||
|
|
@ -953,7 +953,6 @@ properties:
|
|||
- toradex,verdin-imx8mm # Verdin iMX8M Mini Modules
|
||||
- toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT
|
||||
- toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Modules
|
||||
- variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module
|
||||
- prt,prt8mm # i.MX8MM Protonic PRT8MM Board
|
||||
- const: fsl,imx8mm
|
||||
|
||||
|
|
@ -1082,7 +1081,7 @@ properties:
|
|||
- gateworks,imx8mp-gw72xx-2x # i.MX8MP Gateworks Board
|
||||
- gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board
|
||||
- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
|
||||
- gateworks,imx8mp-gw7905-2x # i.MX8MP Gateworks Board
|
||||
- gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board
|
||||
- skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel
|
||||
- skov,imx8mp-skov-revb-lt6 # SKOV i.MX8MP climate control with 7” panel
|
||||
- skov,imx8mp-skov-revb-mi1010ait-1cp1 # SKOV i.MX8MP climate control with 10.1" panel
|
||||
|
|
@ -1168,6 +1167,12 @@ properties:
|
|||
- const: tq,imx8mp-tqma8mpql # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: Variscite VAR-SOM-MX8M Plus based boards
|
||||
items:
|
||||
- const: variscite,var-som-mx8mp-symphony
|
||||
- const: variscite,var-som-mx8mp
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: i.MX8MQ based Boards
|
||||
items:
|
||||
- enum:
|
||||
|
|
@ -1293,6 +1298,7 @@ properties:
|
|||
- enum:
|
||||
- fsl,imx93-9x9-qsb # i.MX93 9x9 QSB Board
|
||||
- fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board
|
||||
- fsl,imx93-14x14-evk # i.MX93 14x14 EVK Board
|
||||
- const: fsl,imx93
|
||||
|
||||
- description: i.MX95 based Boards
|
||||
|
|
@ -1344,6 +1350,12 @@ properties:
|
|||
- const: variscite,var-som-mx93
|
||||
- const: fsl,imx93
|
||||
|
||||
- description: Kontron OSM-S i.MX93 SoM based boards
|
||||
items:
|
||||
- const: kontron,imx93-bl-osm-s # Kontron BL i.MX93 OSM-S board
|
||||
- const: kontron,imx93-osm-s # Kontron OSM-S i.MX93 SoM
|
||||
- const: fsl,imx93
|
||||
|
||||
- description:
|
||||
Freescale Vybrid Platform Device Tree Bindings
|
||||
|
||||
|
|
@ -1523,6 +1535,12 @@ properties:
|
|||
- fsl,ls2080a-rdb
|
||||
- const: fsl,ls2080a
|
||||
|
||||
- description: LS2081A based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,ls2081a-rdb
|
||||
- const: fsl,ls2081a
|
||||
|
||||
- description: LS2088A based Boards
|
||||
items:
|
||||
- enum:
|
||||
|
|
|
|||
|
|
@ -1,24 +0,0 @@
|
|||
Mediatek bdpsys controller
|
||||
============================
|
||||
|
||||
The Mediatek bdpsys controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be:
|
||||
- "mediatek,mt2701-bdpsys", "syscon"
|
||||
- "mediatek,mt2712-bdpsys", "syscon"
|
||||
- "mediatek,mt7623-bdpsys", "mediatek,mt2701-bdpsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The bdpsys controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
Example:
|
||||
|
||||
bdpsys: clock-controller@1c000000 {
|
||||
compatible = "mediatek,mt2701-bdpsys", "syscon";
|
||||
reg = <0 0x1c000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
MediaTek CAMSYS controller
|
||||
============================
|
||||
|
||||
The MediaTek camsys controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt6765-camsys", "syscon"
|
||||
- "mediatek,mt6779-camsys", "syscon"
|
||||
- "mediatek,mt8183-camsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The camsys controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
Example:
|
||||
|
||||
camsys: camsys@1a000000 {
|
||||
compatible = "mediatek,mt8183-camsys", "syscon";
|
||||
reg = <0 0x1a000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -1,30 +0,0 @@
|
|||
Mediatek imgsys controller
|
||||
============================
|
||||
|
||||
The Mediatek imgsys controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-imgsys", "syscon"
|
||||
- "mediatek,mt2712-imgsys", "syscon"
|
||||
- "mediatek,mt6765-imgsys", "syscon"
|
||||
- "mediatek,mt6779-imgsys", "syscon"
|
||||
- "mediatek,mt6797-imgsys", "syscon"
|
||||
- "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
|
||||
- "mediatek,mt8167-imgsys", "syscon"
|
||||
- "mediatek,mt8173-imgsys", "syscon"
|
||||
- "mediatek,mt8183-imgsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The imgsys controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
Example:
|
||||
|
||||
imgsys: clock-controller@15000000 {
|
||||
compatible = "mediatek,mt8173-imgsys", "syscon";
|
||||
reg = <0 0x15000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
Mediatek ipesys controller
|
||||
============================
|
||||
|
||||
The Mediatek ipesys controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt6779-ipesys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The ipesys controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
Example:
|
||||
|
||||
ipesys: clock-controller@1b000000 {
|
||||
compatible = "mediatek,mt6779-ipesys", "syscon";
|
||||
reg = <0 0x1b000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -1,43 +0,0 @@
|
|||
Mediatek IPU controller
|
||||
============================
|
||||
|
||||
The Mediatek ipu controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt8183-ipu_conn", "syscon"
|
||||
- "mediatek,mt8183-ipu_adl", "syscon"
|
||||
- "mediatek,mt8183-ipu_core0", "syscon"
|
||||
- "mediatek,mt8183-ipu_core1", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The ipu controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
Example:
|
||||
|
||||
ipu_conn: syscon@19000000 {
|
||||
compatible = "mediatek,mt8183-ipu_conn", "syscon";
|
||||
reg = <0 0x19000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
ipu_adl: syscon@19010000 {
|
||||
compatible = "mediatek,mt8183-ipu_adl", "syscon";
|
||||
reg = <0 0x19010000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
ipu_core0: syscon@19180000 {
|
||||
compatible = "mediatek,mt8183-ipu_core0", "syscon";
|
||||
reg = <0 0x19180000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
ipu_core1: syscon@19280000 {
|
||||
compatible = "mediatek,mt8183-ipu_core1", "syscon";
|
||||
reg = <0 0x19280000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
Mediatek jpgdecsys controller
|
||||
============================
|
||||
|
||||
The Mediatek jpgdecsys controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be:
|
||||
- "mediatek,mt2712-jpgdecsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The jpgdecsys controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
Example:
|
||||
|
||||
jpgdecsys: syscon@19000000 {
|
||||
compatible = "mediatek,mt2712-jpgdecsys", "syscon";
|
||||
reg = <0 0x19000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
Mediatek mcucfg controller
|
||||
============================
|
||||
|
||||
The Mediatek mcucfg controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2712-mcucfg", "syscon"
|
||||
- "mediatek,mt8183-mcucfg", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The mcucfg controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
Example:
|
||||
|
||||
mcucfg: syscon@10220000 {
|
||||
compatible = "mediatek,mt2712-mcucfg", "syscon";
|
||||
reg = <0 0x10220000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
Mediatek mfgcfg controller
|
||||
============================
|
||||
|
||||
The Mediatek mfgcfg controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2712-mfgcfg", "syscon"
|
||||
- "mediatek,mt6779-mfgcfg", "syscon"
|
||||
- "mediatek,mt8167-mfgcfg", "syscon"
|
||||
- "mediatek,mt8183-mfgcfg", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The mfgcfg controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
Example:
|
||||
|
||||
mfgcfg: syscon@13000000 {
|
||||
compatible = "mediatek,mt2712-mfgcfg", "syscon";
|
||||
reg = <0 0x13000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -1,28 +0,0 @@
|
|||
Mediatek mipi0a (mipi_rx_ana_csi0a) controller
|
||||
============================
|
||||
|
||||
The Mediatek mipi0a controller provides various clocks
|
||||
to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt6765-mipi0a", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The mipi0a controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
The mipi0a controller also uses the common power domain from
|
||||
Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
|
||||
The available power domains are defined in dt-bindings/power/mt*-power.h.
|
||||
|
||||
Example:
|
||||
|
||||
mipi0a: clock-controller@11c10000 {
|
||||
compatible = "mediatek,mt6765-mipi0a", "syscon";
|
||||
reg = <0 0x11c10000 0 0x1000>;
|
||||
power-domains = <&scpsys MT6765_POWER_DOMAIN_CAM>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
Mediatek vcodecsys controller
|
||||
============================
|
||||
|
||||
The Mediatek vcodecsys controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt6765-vcodecsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The vcodecsys controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
The vcodecsys controller also uses the common power domain from
|
||||
Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
|
||||
The available power domains are defined in dt-bindings/power/mt*-power.h.
|
||||
|
||||
Example:
|
||||
|
||||
venc_gcon: clock-controller@17000000 {
|
||||
compatible = "mediatek,mt6765-vcodecsys", "syscon";
|
||||
reg = <0 0x17000000 0 0x10000>;
|
||||
power-domains = <&scpsys MT6765_POWER_DOMAIN_VCODEC>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -1,29 +0,0 @@
|
|||
Mediatek vdecsys controller
|
||||
============================
|
||||
|
||||
The Mediatek vdecsys controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-vdecsys", "syscon"
|
||||
- "mediatek,mt2712-vdecsys", "syscon"
|
||||
- "mediatek,mt6779-vdecsys", "syscon"
|
||||
- "mediatek,mt6797-vdecsys", "syscon"
|
||||
- "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
|
||||
- "mediatek,mt8167-vdecsys", "syscon"
|
||||
- "mediatek,mt8173-vdecsys", "syscon"
|
||||
- "mediatek,mt8183-vdecsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The vdecsys controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
Example:
|
||||
|
||||
vdecsys: clock-controller@16000000 {
|
||||
compatible = "mediatek,mt8173-vdecsys", "syscon";
|
||||
reg = <0 0x16000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
Mediatek vencltsys controller
|
||||
============================
|
||||
|
||||
The Mediatek vencltsys controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be:
|
||||
- "mediatek,mt8173-vencltsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The vencltsys controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
Example:
|
||||
|
||||
vencltsys: clock-controller@19000000 {
|
||||
compatible = "mediatek,mt8173-vencltsys", "syscon";
|
||||
reg = <0 0x19000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
Mediatek vencsys controller
|
||||
============================
|
||||
|
||||
The Mediatek vencsys controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2712-vencsys", "syscon"
|
||||
- "mediatek,mt6779-vencsys", "syscon"
|
||||
- "mediatek,mt6797-vencsys", "syscon"
|
||||
- "mediatek,mt8173-vencsys", "syscon"
|
||||
- "mediatek,mt8183-vencsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The vencsys controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
Example:
|
||||
|
||||
vencsys: clock-controller@18000000 {
|
||||
compatible = "mediatek,mt8173-vencsys", "syscon";
|
||||
reg = <0 0x18000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -155,6 +155,11 @@ properties:
|
|||
- const: qcom,msm8926
|
||||
- const: qcom,msm8226
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- wingtech,wt82918hd
|
||||
- const: qcom,msm8929
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- huawei,kiwi
|
||||
|
|
@ -162,6 +167,8 @@ properties:
|
|||
- samsung,a7
|
||||
- sony,kanuti-tulip
|
||||
- square,apq8039-t2
|
||||
- wingtech,wt82918
|
||||
- wingtech,wt82918hdhw39
|
||||
- const: qcom,msm8939
|
||||
|
||||
- items:
|
||||
|
|
@ -228,12 +235,15 @@ properties:
|
|||
- samsung,grandprimelte
|
||||
- samsung,gt510
|
||||
- samsung,gt58
|
||||
- samsung,j3ltetw
|
||||
- samsung,j5
|
||||
- samsung,j5x
|
||||
- samsung,rossa
|
||||
- samsung,serranove
|
||||
- thwc,uf896
|
||||
- thwc,ufi001c
|
||||
- wingtech,wt86518
|
||||
- wingtech,wt86528
|
||||
- wingtech,wt88047
|
||||
- yiming,uz801-v3
|
||||
- const: qcom,msm8916
|
||||
|
|
@ -250,6 +260,7 @@ properties:
|
|||
- items:
|
||||
- enum:
|
||||
- lg,bullhead
|
||||
- lg,h815
|
||||
- microsoft,talkman
|
||||
- xiaomi,libra
|
||||
- const: qcom,msm8992
|
||||
|
|
@ -1038,10 +1049,18 @@ properties:
|
|||
- qcom,sm8650-qrd
|
||||
- const: qcom,sm8650
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- lenovo,thinkpad-t14s
|
||||
- const: qcom,x1e78100
|
||||
- const: qcom,x1e80100
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- asus,vivobook-s15
|
||||
- lenovo,yoga-slim7x
|
||||
- microsoft,romulus13
|
||||
- microsoft,romulus15
|
||||
- qcom,x1e80100-crd
|
||||
- qcom,x1e80100-qcp
|
||||
- const: qcom,x1e80100
|
||||
|
|
|
|||
|
|
@ -96,6 +96,13 @@ properties:
|
|||
- const: coolpi,pi-cm5
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Cool Pi CM5 GenBook
|
||||
items:
|
||||
- enum:
|
||||
- coolpi,pi-cm5-genbook
|
||||
- const: coolpi,pi-cm5
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Cool Pi 4 Model B
|
||||
items:
|
||||
- const: coolpi,pi-4b
|
||||
|
|
@ -148,6 +155,12 @@ properties:
|
|||
- const: engicam,px30-core
|
||||
- const: rockchip,px30
|
||||
|
||||
- description: Firefly Core-PX30-JD4 on MB-JD4-PX30 baseboard
|
||||
items:
|
||||
- const: firefly,px30-jd4-core-mb
|
||||
- const: firefly,px30-jd4-core
|
||||
- const: rockchip,px30
|
||||
|
||||
- description: Firefly Firefly-RK3288
|
||||
items:
|
||||
- enum:
|
||||
|
|
@ -216,6 +229,7 @@ properties:
|
|||
- friendlyarm,nanopi-r2c
|
||||
- friendlyarm,nanopi-r2c-plus
|
||||
- friendlyarm,nanopi-r2s
|
||||
- friendlyarm,nanopi-r2s-plus
|
||||
- const: rockchip,rk3328
|
||||
|
||||
- description: FriendlyElec NanoPi4 series boards
|
||||
|
|
@ -243,9 +257,11 @@ properties:
|
|||
- friendlyarm,nanopi-r6s
|
||||
- const: rockchip,rk3588s
|
||||
|
||||
- description: FriendlyElec NanoPC T6
|
||||
- description: FriendlyElec NanoPC T6 series boards
|
||||
items:
|
||||
- const: friendlyarm,nanopc-t6
|
||||
- enum:
|
||||
- friendlyarm,nanopc-t6
|
||||
- friendlyarm,nanopc-t6-lts
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: FriendlyElec CM3588-based boards
|
||||
|
|
@ -255,6 +271,11 @@ properties:
|
|||
- const: friendlyarm,cm3588
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: GameForce Ace
|
||||
items:
|
||||
- const: gameforce,ace
|
||||
- const: rockchip,rk3588s
|
||||
|
||||
- description: GameForce Chi
|
||||
items:
|
||||
- const: gameforce,chi
|
||||
|
|
@ -581,9 +602,19 @@ properties:
|
|||
|
||||
- description: Hardkernel Odroid M1
|
||||
items:
|
||||
- const: rockchip,rk3568-odroid-m1
|
||||
- const: hardkernel,odroid-m1
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Hardkernel Odroid M1S
|
||||
items:
|
||||
- const: hardkernel,odroid-m1s
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Hardkernel Odroid M2
|
||||
items:
|
||||
- const: hardkernel,odroid-m2
|
||||
- const: rockchip,rk3588s
|
||||
|
||||
- description: Hugsun X99 TV Box
|
||||
items:
|
||||
- const: hugsun,x99
|
||||
|
|
@ -622,6 +653,11 @@ properties:
|
|||
- const: leez,p710
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: LCKFB Taishan Pi RK3566
|
||||
items:
|
||||
- const: lckfb,tspi-rk3566
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Lunzn FastRhino R66S / R68S
|
||||
items:
|
||||
- enum:
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@ select:
|
|||
- rockchip,rk3368-pmu
|
||||
- rockchip,rk3399-pmu
|
||||
- rockchip,rk3568-pmu
|
||||
- rockchip,rk3576-pmu
|
||||
- rockchip,rk3588-pmu
|
||||
- rockchip,rv1126-pmu
|
||||
|
||||
|
|
@ -43,6 +44,7 @@ properties:
|
|||
- rockchip,rk3368-pmu
|
||||
- rockchip,rk3399-pmu
|
||||
- rockchip,rk3568-pmu
|
||||
- rockchip,rk3576-pmu
|
||||
- rockchip,rk3588-pmu
|
||||
- rockchip,rv1126-pmu
|
||||
- const: syscon
|
||||
|
|
|
|||
|
|
@ -54,6 +54,8 @@ properties:
|
|||
- description: ST STM32MP151 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- prt,mecio1r0 # Protonic MECIO1r0
|
||||
- prt,mect1s # Protonic MECT1S
|
||||
- prt,prtt1a # Protonic PRTT1A
|
||||
- prt,prtt1c # Protonic PRTT1C
|
||||
- prt,prtt1s # Protonic PRTT1S
|
||||
|
|
@ -71,6 +73,12 @@ properties:
|
|||
- const: dh,stm32mp151a-dhcor-som
|
||||
- const: st,stm32mp151
|
||||
|
||||
- description: ST STM32MP153 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- prt,mecio1r1 # Protonic MECIO1r1
|
||||
- const: st,stm32mp153
|
||||
|
||||
- description: DH STM32MP153 DHCOM SoM based Boards
|
||||
items:
|
||||
- const: dh,stm32mp153c-dhcom-drc02
|
||||
|
|
|
|||
|
|
@ -61,14 +61,19 @@ properties:
|
|||
- const: anbernic,rg35xx-2024
|
||||
- const: allwinner,sun50i-h700
|
||||
|
||||
- description: Anbernic RG35XX H
|
||||
items:
|
||||
- const: anbernic,rg35xx-h
|
||||
- const: allwinner,sun50i-h700
|
||||
|
||||
- description: Anbernic RG35XX Plus
|
||||
items:
|
||||
- const: anbernic,rg35xx-plus
|
||||
- const: allwinner,sun50i-h700
|
||||
|
||||
- description: Anbernic RG35XX H
|
||||
- description: Anbernic RG35XX SP
|
||||
items:
|
||||
- const: anbernic,rg35xx-h
|
||||
- const: anbernic,rg35xx-sp
|
||||
- const: allwinner,sun50i-h700
|
||||
|
||||
- description: Amarula A64 Relic
|
||||
|
|
|
|||
|
|
@ -127,6 +127,48 @@ properties:
|
|||
- nvidia,norrin
|
||||
- const: nvidia,tegra132
|
||||
- const: nvidia,tegra124
|
||||
- items:
|
||||
- const: google,nyan-blaze-rev10
|
||||
- const: google,nyan-blaze-rev9
|
||||
- const: google,nyan-blaze-rev8
|
||||
- const: google,nyan-blaze-rev7
|
||||
- const: google,nyan-blaze-rev6
|
||||
- const: google,nyan-blaze-rev5
|
||||
- const: google,nyan-blaze-rev4
|
||||
- const: google,nyan-blaze-rev3
|
||||
- const: google,nyan-blaze-rev2
|
||||
- const: google,nyan-blaze-rev1
|
||||
- const: google,nyan-blaze-rev0
|
||||
- const: google,nyan-blaze
|
||||
- const: google,nyan
|
||||
- const: nvidia,tegra124
|
||||
- items:
|
||||
- const: google,nyan-big-rev10
|
||||
- const: google,nyan-big-rev9
|
||||
- const: google,nyan-big-rev8
|
||||
- const: google,nyan-big-rev7
|
||||
- const: google,nyan-big-rev6
|
||||
- const: google,nyan-big-rev5
|
||||
- const: google,nyan-big-rev4
|
||||
- const: google,nyan-big-rev3
|
||||
- const: google,nyan-big-rev2
|
||||
- const: google,nyan-big-rev1
|
||||
- const: google,nyan-big-rev0
|
||||
- const: google,nyan-big
|
||||
- const: google,nyan
|
||||
- const: nvidia,tegra124
|
||||
- items:
|
||||
- const: google,nyan-big-rev7
|
||||
- const: google,nyan-big-rev6
|
||||
- const: google,nyan-big-rev5
|
||||
- const: google,nyan-big-rev4
|
||||
- const: google,nyan-big-rev3
|
||||
- const: google,nyan-big-rev2
|
||||
- const: google,nyan-big-rev1
|
||||
- const: google,nyan-big-rev0
|
||||
- const: google,nyan-big
|
||||
- const: google,nyan
|
||||
- const: nvidia,tegra124
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,darcy
|
||||
|
|
|
|||
|
|
@ -140,6 +140,7 @@ properties:
|
|||
- description: K3 J722S SoC and Boards
|
||||
items:
|
||||
- enum:
|
||||
- beagle,am67a-beagley-ai
|
||||
- ti,j722s-evm
|
||||
- const: ti,j722s
|
||||
|
||||
|
|
|
|||
|
|
@ -30,6 +30,8 @@ select:
|
|||
- marvell,armada-3700-ahci
|
||||
- marvell,armada-8k-ahci
|
||||
- marvell,berlin2q-ahci
|
||||
- qcom,apq8064-ahci
|
||||
- qcom,ipq806x-ahci
|
||||
- socionext,uniphier-pro4-ahci
|
||||
- socionext,uniphier-pxs2-ahci
|
||||
- socionext,uniphier-pxs3-ahci
|
||||
|
|
@ -45,6 +47,8 @@ properties:
|
|||
- marvell,armada-8k-ahci
|
||||
- marvell,berlin2-ahci
|
||||
- marvell,berlin2q-ahci
|
||||
- qcom,apq8064-ahci
|
||||
- qcom,ipq806x-ahci
|
||||
- socionext,uniphier-pro4-ahci
|
||||
- socionext,uniphier-pxs2-ahci
|
||||
- socionext,uniphier-pxs3-ahci
|
||||
|
|
@ -64,11 +68,11 @@ properties:
|
|||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
maxItems: 5
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
maxItems: 5
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
|
@ -97,6 +101,31 @@ required:
|
|||
|
||||
allOf:
|
||||
- $ref: ahci-common.yaml#
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,apq8064-ahci
|
||||
- qcom,ipq806x-ahci
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 5
|
||||
clock-names:
|
||||
items:
|
||||
- const: slave_iface
|
||||
- const: iface
|
||||
- const: core
|
||||
- const: rxoob
|
||||
- const: pmalive
|
||||
required:
|
||||
- phys
|
||||
- phy-names
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
42
dts/upstream/Bindings/ata/cirrus,ep9312-pata.yaml
Normal file
42
dts/upstream/Bindings/ata/cirrus,ep9312-pata.yaml
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/ata/cirrus,ep9312-pata.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Cirrus Logic EP9312 PATA controller
|
||||
|
||||
maintainers:
|
||||
- Damien Le Moal <dlemoal@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: cirrus,ep9312-pata
|
||||
- items:
|
||||
- const: cirrus,ep9315-pata
|
||||
- const: cirrus,ep9312-pata
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
ide@800a0000 {
|
||||
compatible = "cirrus,ep9312-pata";
|
||||
reg = <0x800a0000 0x38>;
|
||||
interrupt-parent = <&vic1>;
|
||||
interrupts = <8>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ide_default_pins>;
|
||||
};
|
||||
|
|
@ -19,6 +19,7 @@ properties:
|
|||
- fsl,imx53-ahci
|
||||
- fsl,imx6q-ahci
|
||||
- fsl,imx6qp-ahci
|
||||
- fsl,imx8qm-ahci
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
@ -27,12 +28,14 @@ properties:
|
|||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
items:
|
||||
- description: sata clock
|
||||
- description: sata reference clock
|
||||
- description: ahb clock
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: sata
|
||||
- const: sata_ref
|
||||
|
|
@ -58,6 +61,25 @@ properties:
|
|||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: if present, disable spread-spectrum clocking on the SATA link.
|
||||
|
||||
phys:
|
||||
items:
|
||||
- description: phandle to SATA PHY.
|
||||
Since "REXT" pin is only present for first lane of i.MX8QM PHY, it's
|
||||
calibration result will be stored, passed through second lane, and
|
||||
shared with all three lanes PHY. The first two lanes PHY are used as
|
||||
calibration PHYs, although only the third lane PHY is used by SATA.
|
||||
- description: phandle to the first lane PHY of i.MX8QM.
|
||||
- description: phandle to the second lane PHY of i.MX8QM.
|
||||
|
||||
phy-names:
|
||||
items:
|
||||
- const: sata-phy
|
||||
- const: cali-phy0
|
||||
- const: cali-phy1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
@ -65,6 +87,31 @@ required:
|
|||
- clocks
|
||||
- clock-names
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- fsl,imx53-ahci
|
||||
- fsl,imx6q-ahci
|
||||
- fsl,imx6qp-ahci
|
||||
then:
|
||||
properties:
|
||||
clock-names:
|
||||
minItems: 3
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- fsl,imx8qm-ahci
|
||||
then:
|
||||
properties:
|
||||
clock-names:
|
||||
minItems: 2
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
|
|
|||
|
|
@ -1,48 +0,0 @@
|
|||
* Qualcomm AHCI SATA Controller
|
||||
|
||||
SATA nodes are defined to describe on-chip Serial ATA controllers.
|
||||
Each SATA controller should have its own node.
|
||||
|
||||
Required properties:
|
||||
- compatible : compatible list, must contain "generic-ahci"
|
||||
- interrupts : <interrupt mapping for SATA IRQ>
|
||||
- reg : <registers mapping>
|
||||
- phys : Must contain exactly one entry as specified
|
||||
in phy-bindings.txt
|
||||
- phy-names : Must be "sata-phy"
|
||||
|
||||
Required properties for "qcom,ipq806x-ahci" compatible:
|
||||
- clocks : Must contain an entry for each entry in clock-names.
|
||||
- clock-names : Shall be:
|
||||
"slave_iface" - Fabric port AHB clock for SATA
|
||||
"iface" - AHB clock
|
||||
"core" - core clock
|
||||
"rxoob" - RX out-of-band clock
|
||||
"pmalive" - Power Module Alive clock
|
||||
- assigned-clocks : Shall be:
|
||||
SATA_RXOOB_CLK
|
||||
SATA_PMALIVE_CLK
|
||||
- assigned-clock-rates : Shall be:
|
||||
100Mhz (100000000) for SATA_RXOOB_CLK
|
||||
100Mhz (100000000) for SATA_PMALIVE_CLK
|
||||
|
||||
Example:
|
||||
sata@29000000 {
|
||||
compatible = "qcom,ipq806x-ahci", "generic-ahci";
|
||||
reg = <0x29000000 0x180>;
|
||||
|
||||
interrupts = <0 209 0x0>;
|
||||
|
||||
clocks = <&gcc SFAB_SATA_S_H_CLK>,
|
||||
<&gcc SATA_H_CLK>,
|
||||
<&gcc SATA_A_CLK>,
|
||||
<&gcc SATA_RXOOB_CLK>,
|
||||
<&gcc SATA_PMALIVE_CLK>;
|
||||
clock-names = "slave_iface", "iface", "core",
|
||||
"rxoob", "pmalive";
|
||||
assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
|
||||
assigned-clock-rates = <100000000>, <100000000>;
|
||||
|
||||
phys = <&sata_phy>;
|
||||
phy-names = "sata-phy";
|
||||
};
|
||||
32
dts/upstream/Bindings/board/fsl,bcsr.yaml
Normal file
32
dts/upstream/Bindings/board/fsl,bcsr.yaml
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/board/fsl,bcsr.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Board Control and Status
|
||||
|
||||
maintainers:
|
||||
- Frank Li <Frank.Li@nxp.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- fsl,mpc8360mds-bcsr
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
board@f8000000 {
|
||||
compatible = "fsl,mpc8360mds-bcsr";
|
||||
reg = <0xf8000000 0x8000>;
|
||||
};
|
||||
|
||||
70
dts/upstream/Bindings/board/fsl,fpga-qixis-i2c.yaml
Normal file
70
dts/upstream/Bindings/board/fsl,fpga-qixis-i2c.yaml
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/board/fsl,fpga-qixis-i2c.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale on-board FPGA connected on I2C bus
|
||||
|
||||
maintainers:
|
||||
- Frank Li <Frank.Li@nxp.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,bsc9132qds-fpga
|
||||
- const: fsl,fpga-qixis-i2c
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,ls1028aqds-fpga
|
||||
- fsl,lx2160aqds-fpga
|
||||
- const: fsl,fpga-qixis-i2c
|
||||
- const: simple-mfd
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
mux-controller:
|
||||
$ref: /schemas/mux/reg-mux.yaml
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
board-control@66 {
|
||||
compatible = "fsl,bsc9132qds-fpga", "fsl,fpga-qixis-i2c";
|
||||
reg = <0x66>;
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
board-control@66 {
|
||||
compatible = "fsl,ls1028aqds-fpga", "fsl,fpga-qixis-i2c",
|
||||
"simple-mfd";
|
||||
reg = <0x66>;
|
||||
|
||||
mux-controller {
|
||||
compatible = "reg-mux";
|
||||
#mux-control-cells = <1>;
|
||||
mux-reg-masks = <0x54 0xf0>; /* 0: reg 0x54, bits 7:4 */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
81
dts/upstream/Bindings/board/fsl,fpga-qixis.yaml
Normal file
81
dts/upstream/Bindings/board/fsl,fpga-qixis.yaml
Normal file
|
|
@ -0,0 +1,81 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/board/fsl,fpga-qixis.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale on-board FPGA/CPLD
|
||||
|
||||
maintainers:
|
||||
- Frank Li <Frank.Li@nxp.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: fsl,p1022ds-fpga
|
||||
- const: fsl,fpga-ngpixis
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,ls1088aqds-fpga
|
||||
- fsl,ls1088ardb-fpga
|
||||
- fsl,ls2080aqds-fpga
|
||||
- fsl,ls2080ardb-fpga
|
||||
- const: fsl,fpga-qixis
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,ls1043aqds-fpga
|
||||
- fsl,ls1043ardb-fpga
|
||||
- fsl,ls1046aqds-fpga
|
||||
- fsl,ls1046ardb-fpga
|
||||
- fsl,ls208xaqds-fpga
|
||||
- const: fsl,fpga-qixis
|
||||
- const: simple-mfd
|
||||
- enum:
|
||||
- fsl,ls1043ardb-cpld
|
||||
- fsl,ls1046ardb-cpld
|
||||
- fsl,t1040rdb-cpld
|
||||
- fsl,t1042rdb-cpld
|
||||
- fsl,t1042rdb_pi-cpld
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 1
|
||||
|
||||
ranges:
|
||||
maxItems: 1
|
||||
|
||||
patternProperties:
|
||||
'^mdio-mux@[a-f0-9,]+$':
|
||||
$ref: /schemas/net/mdio-mux-mmioreg.yaml
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
board-control@3 {
|
||||
compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
|
||||
reg = <3 0x30>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 IRQ_TYPE_LEVEL_LOW 0 0>;
|
||||
};
|
||||
|
||||
- |
|
||||
board-control@3 {
|
||||
compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis";
|
||||
reg = <0x3 0x10000>;
|
||||
};
|
||||
|
||||
|
|
@ -1,81 +0,0 @@
|
|||
Freescale Reference Board Bindings
|
||||
|
||||
This document describes device tree bindings for various devices that
|
||||
exist on some Freescale reference boards.
|
||||
|
||||
* Board Control and Status (BCSR)
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Should be "fsl,<board>-bcsr"
|
||||
- reg : Offset and length of the register set for the device
|
||||
|
||||
Example:
|
||||
|
||||
bcsr@f8000000 {
|
||||
compatible = "fsl,mpc8360mds-bcsr";
|
||||
reg = <f8000000 8000>;
|
||||
};
|
||||
|
||||
* Freescale on-board FPGA
|
||||
|
||||
This is the memory-mapped registers for on board FPGA.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be a board-specific string followed by a string
|
||||
indicating the type of FPGA. Example:
|
||||
"fsl,<board>-fpga", "fsl,fpga-pixis", or
|
||||
"fsl,<board>-fpga", "fsl,fpga-qixis"
|
||||
- reg: should contain the address and the length of the FPGA register set.
|
||||
|
||||
Optional properties:
|
||||
- interrupts: should specify event (wakeup) IRQ.
|
||||
|
||||
Example (P1022DS):
|
||||
|
||||
board-control@3,0 {
|
||||
compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
|
||||
reg = <3 0 0x30>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 8 0 0>;
|
||||
};
|
||||
|
||||
Example (LS2080A-RDB):
|
||||
|
||||
cpld@3,0 {
|
||||
compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis";
|
||||
reg = <0x3 0 0x10000>;
|
||||
};
|
||||
|
||||
* Freescale on-board FPGA connected on I2C bus
|
||||
|
||||
Some Freescale boards like BSC9132QDS have on board FPGA connected on
|
||||
the i2c bus.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be a board-specific string followed by a string
|
||||
indicating the type of FPGA. Example:
|
||||
"fsl,<board>-fpga", "fsl,fpga-qixis-i2c"
|
||||
- reg: Should contain the address of the FPGA
|
||||
|
||||
Example:
|
||||
fpga: fpga@66 {
|
||||
compatible = "fsl,bsc9132qds-fpga", "fsl,fpga-qixis-i2c";
|
||||
reg = <0x66>;
|
||||
};
|
||||
|
||||
* Freescale on-board CPLD
|
||||
|
||||
Some Freescale boards like T1040RDB have an on board CPLD connected.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be a board-specific string like "fsl,<board>-cpld"
|
||||
Example:
|
||||
"fsl,t1040rdb-cpld", "fsl,t1042rdb-cpld", "fsl,t1042rdb_pi-cpld"
|
||||
- reg: should describe CPLD registers
|
||||
|
||||
Example:
|
||||
cpld@3,0 {
|
||||
compatible = "fsl,t1040rdb-cpld";
|
||||
reg = <3 0 0x300>;
|
||||
};
|
||||
|
|
@ -1,138 +0,0 @@
|
|||
Qualcomm External Bus Interface 2 (EBI2)
|
||||
|
||||
The EBI2 contains two peripheral blocks: XMEM and LCDC. The XMEM handles any
|
||||
external memory (such as NAND or other memory-mapped peripherals) whereas
|
||||
LCDC handles LCD displays.
|
||||
|
||||
As it says it connects devices to an external bus interface, meaning address
|
||||
lines (up to 9 address lines so can only address 1KiB external memory space),
|
||||
data lines (16 bits), OE (output enable), ADV (address valid, used on some
|
||||
NOR flash memories), WE (write enable). This on top of 6 different chip selects
|
||||
(CS0 thru CS5) so that in theory 6 different devices can be connected.
|
||||
|
||||
Apparently this bus is clocked at 64MHz. It has dedicated pins on the package
|
||||
and the bus can only come out on these pins, however if some of the pins are
|
||||
unused they can be left unconnected or remuxed to be used as GPIO or in some
|
||||
cases other orthogonal functions as well.
|
||||
|
||||
Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
|
||||
|
||||
The chip selects have the following memory range assignments. This region of
|
||||
memory is referred to as "Chip Peripheral SS FPB0" and is 168MB big.
|
||||
|
||||
Chip Select Physical address base
|
||||
CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
|
||||
CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
|
||||
CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
|
||||
CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
|
||||
CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
|
||||
CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
|
||||
|
||||
The APQ8060 Qualcomm Application Processor User Guide, 80-N7150-14 Rev. A,
|
||||
August 6, 2012 contains some incomplete documentation of the EBI2.
|
||||
|
||||
FIXME: the manual mentions "write precharge cycles" and "precharge cycles".
|
||||
We have not been able to figure out which bit fields these correspond to
|
||||
in the hardware, or what valid values exist. The current hypothesis is that
|
||||
this is something just used on the FAST chip selects and that the SLOW
|
||||
chip selects are understood fully. There is also a "byte device enable"
|
||||
flag somewhere for 8bit memories.
|
||||
|
||||
FIXME: The chipselects have SLOW and FAST configuration registers. It's a bit
|
||||
unclear what this means, if they are mutually exclusive or can be used
|
||||
together, or if some chip selects are hardwired to be FAST and others are SLOW
|
||||
by design.
|
||||
|
||||
The XMEM registers are totally undocumented but could be partially decoded
|
||||
because the Cypress AN49576 Antioch Westbridge apparently has suspiciously
|
||||
similar register layout, see: http://www.cypress.com/file/105771/download
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of:
|
||||
"qcom,msm8660-ebi2"
|
||||
"qcom,apq8060-ebi2"
|
||||
- #address-cells: should be <2>: the first cell is the chipselect,
|
||||
the second cell is the offset inside the memory range
|
||||
- #size-cells: should be <1>
|
||||
- ranges: should be set to:
|
||||
ranges = <0 0x0 0x1a800000 0x00800000>,
|
||||
<1 0x0 0x1b000000 0x00800000>,
|
||||
<2 0x0 0x1b800000 0x00800000>,
|
||||
<3 0x0 0x1d000000 0x08000000>,
|
||||
<4 0x0 0x1c800000 0x00800000>,
|
||||
<5 0x0 0x1c000000 0x00800000>;
|
||||
- reg: two ranges of registers: EBI2 config and XMEM config areas
|
||||
- reg-names: should be "ebi2", "xmem"
|
||||
- clocks: two clocks, EBI_2X and EBI
|
||||
- clock-names: should be "ebi2x", "ebi2"
|
||||
|
||||
Optional subnodes:
|
||||
- Nodes inside the EBI2 will be considered device nodes.
|
||||
|
||||
The following optional properties are properties that can be tagged onto
|
||||
any device subnode. We are assuming that there can be only ONE device per
|
||||
chipselect subnode, else the properties will become ambiguous.
|
||||
|
||||
Optional properties arrays for SLOW chip selects:
|
||||
- qcom,xmem-recovery-cycles: recovery cycles is the time the memory continues to
|
||||
drive the data bus after OE is de-asserted, in order to avoid contention on
|
||||
the data bus. They are inserted when reading one CS and switching to another
|
||||
CS or read followed by write on the same CS. Valid values 0 thru 15. Minimum
|
||||
value is actually 1, so a value of 0 will still yield 1 recovery cycle.
|
||||
- qcom,xmem-write-hold-cycles: write hold cycles, these are extra cycles
|
||||
inserted after every write minimum 1. The data out is driven from the time
|
||||
WE is asserted until CS is asserted. With a hold of 1 (value = 0), the CS
|
||||
stays active for 1 extra cycle etc. Valid values 0 thru 15.
|
||||
- qcom,xmem-write-delta-cycles: initial latency for write cycles inserted for
|
||||
the first write to a page or burst memory. Valid values 0 thru 255.
|
||||
- qcom,xmem-read-delta-cycles: initial latency for read cycles inserted for the
|
||||
first read to a page or burst memory. Valid values 0 thru 255.
|
||||
- qcom,xmem-write-wait-cycles: number of wait cycles for every write access, 0=1
|
||||
cycle. Valid values 0 thru 15.
|
||||
- qcom,xmem-read-wait-cycles: number of wait cycles for every read access, 0=1
|
||||
cycle. Valid values 0 thru 15.
|
||||
|
||||
Optional properties arrays for FAST chip selects:
|
||||
- qcom,xmem-address-hold-enable: this is a boolean property stating that we
|
||||
shall hold the address for an extra cycle to meet hold time requirements
|
||||
with ADV assertion.
|
||||
- qcom,xmem-adv-to-oe-recovery-cycles: the number of cycles elapsed before an OE
|
||||
assertion, with respect to the cycle where ADV (address valid) is asserted.
|
||||
2 means 2 cycles between ADV and OE. Valid values 0, 1, 2 or 3.
|
||||
- qcom,xmem-read-hold-cycles: the length in cycles of the first segment of a
|
||||
read transfer. For a single read transfer this will be the time from CS
|
||||
assertion to OE assertion. Valid values 0 thru 15.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
ebi2@1a100000 {
|
||||
compatible = "qcom,apq8060-ebi2";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x0 0x1a800000 0x00800000>,
|
||||
<1 0x0 0x1b000000 0x00800000>,
|
||||
<2 0x0 0x1b800000 0x00800000>,
|
||||
<3 0x0 0x1d000000 0x08000000>,
|
||||
<4 0x0 0x1c800000 0x00800000>,
|
||||
<5 0x0 0x1c000000 0x00800000>;
|
||||
reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
|
||||
reg-names = "ebi2", "xmem";
|
||||
clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
|
||||
clock-names = "ebi2x", "ebi2";
|
||||
/* Make sure to set up the pin control for the EBI2 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&foo_ebi2_pins>;
|
||||
|
||||
foo-ebi2@2,0 {
|
||||
compatible = "foo";
|
||||
reg = <2 0x0 0x100>;
|
||||
(...)
|
||||
qcom,xmem-recovery-cycles = <0>;
|
||||
qcom,xmem-write-hold-cycles = <3>;
|
||||
qcom,xmem-write-delta-cycles = <31>;
|
||||
qcom,xmem-read-delta-cycles = <28>;
|
||||
qcom,xmem-write-wait-cycles = <9>;
|
||||
qcom,xmem-read-wait-cycles = <9>;
|
||||
};
|
||||
};
|
||||
239
dts/upstream/Bindings/bus/qcom,ebi2.yaml
Normal file
239
dts/upstream/Bindings/bus/qcom,ebi2.yaml
Normal file
|
|
@ -0,0 +1,239 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bus/qcom,ebi2.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm External Bus Interface 2 (EBI2)
|
||||
|
||||
description: |
|
||||
The EBI2 contains two peripheral blocks: XMEM and LCDC. The XMEM handles any
|
||||
external memory (such as NAND or other memory-mapped peripherals) whereas
|
||||
LCDC handles LCD displays.
|
||||
|
||||
As it says it connects devices to an external bus interface, meaning address
|
||||
lines (up to 9 address lines so can only address 1KiB external memory space),
|
||||
data lines (16 bits), OE (output enable), ADV (address valid, used on some
|
||||
NOR flash memories), WE (write enable). This on top of 6 different chip selects
|
||||
(CS0 thru CS5) so that in theory 6 different devices can be connected.
|
||||
|
||||
Apparently this bus is clocked at 64MHz. It has dedicated pins on the package
|
||||
and the bus can only come out on these pins, however if some of the pins are
|
||||
unused they can be left unconnected or remuxed to be used as GPIO or in some
|
||||
cases other orthogonal functions as well.
|
||||
|
||||
Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
|
||||
|
||||
The chip selects have the following memory range assignments. This region of
|
||||
memory is referred to as "Chip Peripheral SS FPB0" and is 168MB big.
|
||||
|
||||
Chip Select Physical address base
|
||||
CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
|
||||
CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
|
||||
CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
|
||||
CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
|
||||
CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
|
||||
CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
|
||||
|
||||
The APQ8060 Qualcomm Application Processor User Guide, 80-N7150-14 Rev. A,
|
||||
August 6, 2012 contains some incomplete documentation of the EBI2.
|
||||
|
||||
FIXME: the manual mentions "write precharge cycles" and "precharge cycles".
|
||||
We have not been able to figure out which bit fields these correspond to
|
||||
in the hardware, or what valid values exist. The current hypothesis is that
|
||||
this is something just used on the FAST chip selects and that the SLOW
|
||||
chip selects are understood fully. There is also a "byte device enable"
|
||||
flag somewhere for 8bit memories.
|
||||
|
||||
FIXME: The chipselects have SLOW and FAST configuration registers. It's a bit
|
||||
unclear what this means, if they are mutually exclusive or can be used
|
||||
together, or if some chip selects are hardwired to be FAST and others are SLOW
|
||||
by design.
|
||||
|
||||
The XMEM registers are totally undocumented but could be partially decoded
|
||||
because the Cypress AN49576 Antioch Westbridge apparently has suspiciously
|
||||
similar register layout, see: http://www.cypress.com/file/105771/download
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,apq8060-ebi2
|
||||
- qcom,msm8660-ebi2
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: EBI2 config region
|
||||
- description: XMEM config region
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: ebi2
|
||||
- const: xmem
|
||||
|
||||
ranges: true
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: EBI_2X clock
|
||||
- description: EBI clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ebi2x
|
||||
- const: ebi2
|
||||
|
||||
'#address-cells':
|
||||
const: 2
|
||||
|
||||
'#size-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- ranges
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#address-cells'
|
||||
- '#size-cells'
|
||||
|
||||
patternProperties:
|
||||
"^.*@[0-5],[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
# SLOW chip selects
|
||||
qcom,xmem-recovery-cycles:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: >
|
||||
The time the memory continues to drive the data bus after OE
|
||||
is de-asserted, in order to avoid contention on the data bus.
|
||||
They are inserted when reading one CS and switching to another
|
||||
CS or read followed by write on the same CS. Minimum value is
|
||||
actually 1, so a value of 0 will still yield 1 recovery cycle.
|
||||
minimum: 0
|
||||
maximum: 15
|
||||
|
||||
qcom,xmem-write-hold-cycles:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: >
|
||||
The extra cycles inserted after every write minimum 1. The
|
||||
data out is driven from the time WE is asserted until CS is
|
||||
asserted. With a hold of 1 (value = 0), the CS stays active
|
||||
for 1 extra cycle, etc.
|
||||
minimum: 0
|
||||
maximum: 15
|
||||
|
||||
qcom,xmem-write-delta-cycles:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: >
|
||||
The initial latency for write cycles inserted for the first
|
||||
write to a page or burst memory.
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
|
||||
qcom,xmem-read-delta-cycles:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: >
|
||||
The initial latency for read cycles inserted for the first
|
||||
read to a page or burst memory.
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
|
||||
qcom,xmem-write-wait-cycles:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: >
|
||||
The number of wait cycles for every write access.
|
||||
minimum: 0
|
||||
maximum: 15
|
||||
|
||||
qcom,xmem-read-wait-cycles:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: >
|
||||
The number of wait cycles for every read access.
|
||||
minimum: 0
|
||||
maximum: 15
|
||||
|
||||
|
||||
# FAST chip selects
|
||||
qcom,xmem-address-hold-enable:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: >
|
||||
Holds the address for an extra cycle to meet hold time
|
||||
requirements with ADV assertion, when set to 1.
|
||||
enum: [ 0, 1 ]
|
||||
|
||||
qcom,xmem-adv-to-oe-recovery-cycles:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: >
|
||||
The number of cycles elapsed before an OE assertion, with
|
||||
respect to the cycle where ADV (address valid) is asserted.
|
||||
minimum: 0
|
||||
maximum: 3
|
||||
|
||||
qcom,xmem-read-hold-cycles:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: >
|
||||
The length in cycles of the first segment of a read transfer.
|
||||
For a single read transfer this will be the time from CS
|
||||
assertion to OE assertion.
|
||||
minimum: 0
|
||||
maximum: 15
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-msm8660.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
external-bus@1a100000 {
|
||||
compatible = "qcom,msm8660-ebi2";
|
||||
reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
|
||||
reg-names = "ebi2", "xmem";
|
||||
ranges = <0 0x0 0x1a800000 0x00800000>,
|
||||
<1 0x0 0x1b000000 0x00800000>,
|
||||
<2 0x0 0x1b800000 0x00800000>,
|
||||
<3 0x0 0x1d000000 0x08000000>,
|
||||
<4 0x0 0x1c800000 0x00800000>,
|
||||
<5 0x0 0x1c000000 0x00800000>;
|
||||
|
||||
clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
|
||||
clock-names = "ebi2x", "ebi2";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
ethernet@2,0 {
|
||||
compatible = "smsc,lan9221", "smsc,lan9115";
|
||||
reg = <2 0x0 0x100>;
|
||||
|
||||
interrupts-extended = <&pm8058_gpio 7 IRQ_TYPE_EDGE_FALLING>,
|
||||
<&tlmm 29 IRQ_TYPE_EDGE_RISING>;
|
||||
reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
|
||||
|
||||
phy-mode = "mii";
|
||||
reg-io-width = <2>;
|
||||
smsc,force-external-phy;
|
||||
smsc,irq-push-pull;
|
||||
|
||||
/* SLOW chipselect config */
|
||||
qcom,xmem-recovery-cycles = <0>;
|
||||
qcom,xmem-write-hold-cycles = <3>;
|
||||
qcom,xmem-write-delta-cycles = <31>;
|
||||
qcom,xmem-read-delta-cycles = <28>;
|
||||
qcom,xmem-write-wait-cycles = <9>;
|
||||
qcom,xmem-read-wait-cycles = <9>;
|
||||
};
|
||||
};
|
||||
|
|
@ -24,11 +24,13 @@ properties:
|
|||
items:
|
||||
- description: input top pll
|
||||
- description: input mclk pll
|
||||
- description: input fix pll
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: top
|
||||
- const: mclk
|
||||
- const: fix
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
|
@ -52,8 +54,9 @@ examples:
|
|||
compatible = "amlogic,c3-pll-clkc";
|
||||
reg = <0x0 0x8000 0x0 0x1a4>;
|
||||
clocks = <&scmi_clk 2>,
|
||||
<&scmi_clk 5>;
|
||||
clock-names = "top", "mclk";
|
||||
<&scmi_clk 5>,
|
||||
<&scmi_clk 12>;
|
||||
clock-names = "top", "mclk", "fix";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -42,6 +42,7 @@ properties:
|
|||
- atmel,sama5d3-pmc
|
||||
- atmel,sama5d4-pmc
|
||||
- microchip,sam9x60-pmc
|
||||
- microchip,sam9x7-pmc
|
||||
- microchip,sama7g5-pmc
|
||||
- const: syscon
|
||||
|
||||
|
|
@ -88,6 +89,7 @@ allOf:
|
|||
contains:
|
||||
enum:
|
||||
- microchip,sam9x60-pmc
|
||||
- microchip,sam9x7-pmc
|
||||
- microchip,sama7g5-pmc
|
||||
then:
|
||||
properties:
|
||||
|
|
|
|||
|
|
@ -18,7 +18,9 @@ properties:
|
|||
- atmel,sama5d4-sckc
|
||||
- microchip,sam9x60-sckc
|
||||
- items:
|
||||
- const: microchip,sama7g5-sckc
|
||||
- enum:
|
||||
- microchip,sam9x7-sckc
|
||||
- microchip,sama7g5-sckc
|
||||
- const: microchip,sam9x60-sckc
|
||||
|
||||
reg:
|
||||
|
|
|
|||
|
|
@ -134,9 +134,13 @@ properties:
|
|||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks: true
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 4
|
||||
|
||||
clock-names: true
|
||||
clock-names:
|
||||
minItems: 3
|
||||
maxItems: 4
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
|
|
|||
|
|
@ -67,9 +67,9 @@ properties:
|
|||
minItems: 1
|
||||
maxItems: 19
|
||||
|
||||
clocks: true
|
||||
assigned-clocks: true
|
||||
assigned-clock-parents: true
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 19
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
|
|
|||
|
|
@ -126,8 +126,6 @@ required:
|
|||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- idt,shutdown
|
||||
- idt,output-enable-active
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
|
|
|
|||
|
|
@ -44,6 +44,9 @@ properties:
|
|||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mp-clock.h
|
||||
for the full list of i.MX8MP IMX8MP_CLK_AUDIOMIX_ clock IDs.
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ properties:
|
|||
- mediatek,mt2701-apmixedsys
|
||||
- mediatek,mt2712-apmixedsys
|
||||
- mediatek,mt6765-apmixedsys
|
||||
- mediatek,mt6779-apmixedsys
|
||||
- mediatek,mt6779-apmixed
|
||||
- mediatek,mt6795-apmixedsys
|
||||
- mediatek,mt7629-apmixedsys
|
||||
- mediatek,mt8167-apmixedsys
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,infracfg.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Infrastructure System Configuration Controller
|
||||
|
|
@ -1,54 +0,0 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt6795-sys-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek System Clock Controller for MT6795
|
||||
|
||||
maintainers:
|
||||
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
|
||||
|
||||
description:
|
||||
The Mediatek system clock controller provides various clocks and system
|
||||
configuration like reset and bus protection on MT6795.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- mediatek,mt6795-apmixedsys
|
||||
- mediatek,mt6795-infracfg
|
||||
- mediatek,mt6795-pericfg
|
||||
- mediatek,mt6795-topckgen
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
topckgen: clock-controller@10000000 {
|
||||
compatible = "mediatek,mt6795-topckgen", "syscon";
|
||||
reg = <0 0x10000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt8186-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Functional Clock Controller for MT8186
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt8186-sys-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek System Clock Controller for MT8186
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt8192-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Functional Clock Controller for MT8192
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-sys-clock.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt8192-sys-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek System Clock Controller for MT8192
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt8195-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Functional Clock Controller for MT8195
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt8195-sys-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek System Clock Controller for MT8195
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,pericfg.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,pericfg.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Peripheral Configuration Controller
|
||||
93
dts/upstream/Bindings/clock/mediatek,syscon.yaml
Normal file
93
dts/upstream/Bindings/clock/mediatek,syscon.yaml
Normal file
|
|
@ -0,0 +1,93 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,syscon.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Clock controller syscon's
|
||||
|
||||
maintainers:
|
||||
- Matthias Brugger <matthias.bgg@gmail.com>
|
||||
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
|
||||
description:
|
||||
The MediaTek clock controller syscon's provide various clocks to the system.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt2701-bdpsys
|
||||
- mediatek,mt2701-imgsys
|
||||
- mediatek,mt2701-vdecsys
|
||||
- mediatek,mt2712-bdpsys
|
||||
- mediatek,mt2712-imgsys
|
||||
- mediatek,mt2712-jpgdecsys
|
||||
- mediatek,mt2712-mcucfg
|
||||
- mediatek,mt2712-mfgcfg
|
||||
- mediatek,mt2712-vdecsys
|
||||
- mediatek,mt2712-vencsys
|
||||
- mediatek,mt6765-camsys
|
||||
- mediatek,mt6765-imgsys
|
||||
- mediatek,mt6765-mipi0a
|
||||
- mediatek,mt6765-vcodecsys
|
||||
- mediatek,mt6779-camsys
|
||||
- mediatek,mt6779-imgsys
|
||||
- mediatek,mt6779-ipesys
|
||||
- mediatek,mt6779-mfgcfg
|
||||
- mediatek,mt6779-vdecsys
|
||||
- mediatek,mt6779-vencsys
|
||||
- mediatek,mt6797-imgsys
|
||||
- mediatek,mt6797-vdecsys
|
||||
- mediatek,mt6797-vencsys
|
||||
- mediatek,mt8167-imgsys
|
||||
- mediatek,mt8167-mfgcfg
|
||||
- mediatek,mt8167-vdecsys
|
||||
- mediatek,mt8173-imgsys
|
||||
- mediatek,mt8173-vdecsys
|
||||
- mediatek,mt8173-vencltsys
|
||||
- mediatek,mt8173-vencsys
|
||||
- mediatek,mt8183-camsys
|
||||
- mediatek,mt8183-imgsys
|
||||
- mediatek,mt8183-ipu_conn
|
||||
- mediatek,mt8183-ipu_adl
|
||||
- mediatek,mt8183-ipu_core0
|
||||
- mediatek,mt8183-ipu_core1
|
||||
- mediatek,mt8183-mcucfg
|
||||
- mediatek,mt8183-mfgcfg
|
||||
- mediatek,mt8183-vdecsys
|
||||
- mediatek,mt8183-vencsys
|
||||
- const: syscon
|
||||
- items:
|
||||
- const: mediatek,mt7623-bdpsys
|
||||
- const: mediatek,mt2701-bdpsys
|
||||
- const: syscon
|
||||
- items:
|
||||
- const: mediatek,mt7623-imgsys
|
||||
- const: mediatek,mt2701-imgsys
|
||||
- const: syscon
|
||||
- items:
|
||||
- const: mediatek,mt7623-vdecsys
|
||||
- const: mediatek,mt2701-vdecsys
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@11220000 {
|
||||
compatible = "mediatek,mt2701-bdpsys", "syscon";
|
||||
reg = <0x11220000 0x2000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -16,6 +16,7 @@ properties:
|
|||
- nxp,imx95-lvds-csr
|
||||
- nxp,imx95-display-csr
|
||||
- nxp,imx95-camera-csr
|
||||
- nxp,imx95-netcmix-blk-ctrl
|
||||
- nxp,imx95-vpu-csr
|
||||
- const: syscon
|
||||
|
||||
|
|
|
|||
|
|
@ -1,30 +0,0 @@
|
|||
NXP LPC32xx Clock Controller
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "nxp,lpc3220-clk"
|
||||
- reg: should contain clock controller registers location and length
|
||||
- #clock-cells: must be 1, the cell holds id of a clock provided by the
|
||||
clock controller
|
||||
- clocks: phandles of external oscillators, the list must contain one
|
||||
32768 Hz oscillator and may have one optional high frequency oscillator
|
||||
- clock-names: list of external oscillator clock names, must contain
|
||||
"xtal_32k" and may have optional "xtal"
|
||||
|
||||
Examples:
|
||||
|
||||
/* System Control Block */
|
||||
scb {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x0 0x040004000 0x00001000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
clk: clock-controller@0 {
|
||||
compatible = "nxp,lpc3220-clk";
|
||||
reg = <0x00 0x114>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&xtal_32k>, <&xtal>;
|
||||
clock-names = "xtal_32k", "xtal";
|
||||
};
|
||||
};
|
||||
51
dts/upstream/Bindings/clock/nxp,lpc3220-clk.yaml
Normal file
51
dts/upstream/Bindings/clock/nxp,lpc3220-clk.yaml
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/nxp,lpc3220-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP LPC32xx Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Animesh Agarwal <animeshagarwal28@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: nxp,lpc3220-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: External 32768 Hz oscillator.
|
||||
- description: Optional high frequency oscillator.
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: xtal_32k
|
||||
- const: xtal
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@0 {
|
||||
compatible = "nxp,lpc3220-clk";
|
||||
reg = <0x00 0x114>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&xtal_32k>, <&xtal>;
|
||||
clock-names = "xtal_32k", "xtal";
|
||||
};
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
NXP LPC32xx USB Clock Controller
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "nxp,lpc3220-usb-clk"
|
||||
- reg: should contain clock controller registers location and length
|
||||
- #clock-cells: must be 1, the cell holds id of a clock provided by the
|
||||
USB clock controller
|
||||
|
||||
Examples:
|
||||
|
||||
usb {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x0 0x31020000 0x00001000>;
|
||||
|
||||
usbclk: clock-controller@f00 {
|
||||
compatible = "nxp,lpc3220-usb-clk";
|
||||
reg = <0xf00 0x100>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
35
dts/upstream/Bindings/clock/nxp,lpc3220-usb-clk.yaml
Normal file
35
dts/upstream/Bindings/clock/nxp,lpc3220-usb-clk.yaml
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/nxp,lpc3220-usb-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP LPC32xx USB Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Animesh Agarwal <animeshagarwal28@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: nxp,lpc3220-usb-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@f00 {
|
||||
compatible = "nxp,lpc3220-usb-clk";
|
||||
reg = <0xf00 0x100>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -21,6 +21,7 @@ properties:
|
|||
- qcom,ipq6018-a53pll
|
||||
- qcom,ipq8074-a53pll
|
||||
- qcom,ipq9574-a73pll
|
||||
- qcom,msm8226-a7pll
|
||||
- qcom,msm8916-a53pll
|
||||
- qcom,msm8939-a53pll
|
||||
|
||||
|
|
@ -40,6 +41,9 @@ properties:
|
|||
|
||||
operating-points-v2: true
|
||||
|
||||
opp-table:
|
||||
type: object
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -31,6 +31,8 @@ properties:
|
|||
- description: USB PCIE wrapper pipe clock source
|
||||
|
||||
'#power-domain-cells': false
|
||||
'#interconnect-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
|
|
|||
47
dts/upstream/Bindings/clock/qcom,qcs404-turingcc.yaml
Normal file
47
dts/upstream/Bindings/clock/qcom,qcs404-turingcc.yaml
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,qcs404-turingcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Turing Clock & Reset Controller on QCS404
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,qcs404-turingcc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-qcs404.h>
|
||||
clock-controller@800000 {
|
||||
compatible = "qcom,qcs404-turingcc";
|
||||
reg = <0x00800000 0x30000>;
|
||||
clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
|
@ -139,7 +139,7 @@ examples:
|
|||
- |
|
||||
rpm {
|
||||
rpm-requests {
|
||||
compatible = "qcom,rpm-msm8916";
|
||||
compatible = "qcom,rpm-msm8916", "qcom,smd-rpm";
|
||||
qcom,smd-channels = "rpm_requests";
|
||||
|
||||
clock-controller {
|
||||
|
|
|
|||
|
|
@ -18,9 +18,16 @@ description: |
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc8280xp-lpassaudiocc
|
||||
- qcom,sc8280xp-lpasscc
|
||||
oneOf:
|
||||
- enum:
|
||||
- qcom,sc8280xp-lpassaudiocc
|
||||
- qcom,sc8280xp-lpasscc
|
||||
- items:
|
||||
- const: qcom,x1e80100-lpassaudiocc
|
||||
- const: qcom,sc8280xp-lpassaudiocc
|
||||
- items:
|
||||
- const: qcom,x1e80100-lpasscc
|
||||
- const: qcom,sc8280xp-lpasscc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
63
dts/upstream/Bindings/clock/qcom,sm4450-camcc.yaml
Normal file
63
dts/upstream/Bindings/clock/qcom,sm4450-camcc.yaml
Normal file
|
|
@ -0,0 +1,63 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm4450-camcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Camera Clock & Reset Controller on SM4450
|
||||
|
||||
maintainers:
|
||||
- Ajit Pandey <quic_ajipan@quicinc.com>
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm camera clock control module provides the clocks, resets and power
|
||||
domains on SM4450
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm4450-camcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm4450-camcc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Camera AHB clock source from GCC
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
|
||||
clock-controller@ade0000 {
|
||||
compatible = "qcom,sm4450-camcc";
|
||||
reg = <0x0ade0000 0x20000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_CAMERA_AHB_CLK>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
71
dts/upstream/Bindings/clock/qcom,sm4450-dispcc.yaml
Normal file
71
dts/upstream/Bindings/clock/qcom,sm4450-dispcc.yaml
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm4450-dispcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller on SM4450
|
||||
|
||||
maintainers:
|
||||
- Ajit Pandey <quic_ajipan@quicinc.com>
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module provides the clocks, resets and power
|
||||
domains on SM4450
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm4450-dispcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm4450-dispcc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
- description: Display AHB clock source from GCC
|
||||
- description: sleep clock source
|
||||
- description: Byte clock from DSI PHY0
|
||||
- description: Pixel clock from DSI PHY0
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
|
||||
clock-controller@af00000 {
|
||||
compatible = "qcom,sm4450-dispcc";
|
||||
reg = <0x0af00000 0x20000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&gcc GCC_DISP_AHB_CLK>,
|
||||
<&sleep_clk>,
|
||||
<&dsi0_phy_pll_out_byteclk>,
|
||||
<&dsi0_phy_pll_out_dsiclk>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
77
dts/upstream/Bindings/clock/qcom,sm8150-camcc.yaml
Normal file
77
dts/upstream/Bindings/clock/qcom,sm8150-camcc.yaml
Normal file
|
|
@ -0,0 +1,77 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm8150-camcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Camera Clock & Reset Controller on SM8150
|
||||
|
||||
maintainers:
|
||||
- Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm camera clock control module provides the clocks, resets and
|
||||
power domains on SM8150.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm8150-camcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8150-camcc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Camera AHB clock from GCC
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
description:
|
||||
A phandle and PM domain specifier for the MMCX power domain.
|
||||
|
||||
required-opps:
|
||||
maxItems: 1
|
||||
description:
|
||||
A phandle to an OPP node describing required MMCX performance point.
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- power-domains
|
||||
- required-opps
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
clock-controller@ad00000 {
|
||||
compatible = "qcom,sm8150-camcc";
|
||||
reg = <0x0ad00000 0x10000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_CAMERA_AHB_CLK>;
|
||||
power-domains = <&rpmhpd SM8150_MMCX>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -21,9 +21,6 @@ description: |
|
|||
include/dt-bindings/clock/qcom,sm8650-camcc.h
|
||||
include/dt-bindings/clock/qcom,x1e80100-camcc.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
|
|
@ -57,7 +54,21 @@ required:
|
|||
- compatible
|
||||
- clocks
|
||||
- power-domains
|
||||
- required-opps
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sc8280xp-camcc
|
||||
- qcom,sm8450-camcc
|
||||
- qcom,sm8550-camcc
|
||||
- qcom,x1e80100-camcc
|
||||
then:
|
||||
required:
|
||||
- required-opps
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@ description: |
|
|||
domains on Qualcomm SoCs.
|
||||
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,sm4450-gpucc.h
|
||||
include/dt-bindings/clock/qcom,sm8450-gpucc.h
|
||||
include/dt-bindings/clock/qcom,sm8550-gpucc.h
|
||||
include/dt-bindings/reset/qcom,sm8450-gpucc.h
|
||||
|
|
@ -23,6 +24,7 @@ description: |
|
|||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm4450-gpucc
|
||||
- qcom,sm8450-gpucc
|
||||
- qcom,sm8550-gpucc
|
||||
- qcom,sm8650-gpucc
|
||||
|
|
|
|||
|
|
@ -44,11 +44,20 @@ required:
|
|||
- compatible
|
||||
- clocks
|
||||
- power-domains
|
||||
- required-opps
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sm8450-videocc
|
||||
- qcom,sm8550-videocc
|
||||
then:
|
||||
required:
|
||||
- required-opps
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
|
|
|
|||
|
|
@ -1,19 +0,0 @@
|
|||
Qualcomm Turing Clock & Reset Controller Binding
|
||||
------------------------------------------------
|
||||
|
||||
Required properties :
|
||||
- compatible: shall contain "qcom,qcs404-turingcc".
|
||||
- reg: shall contain base register location and length.
|
||||
- clocks: ahb clock for the TuringCC
|
||||
- #clock-cells: from common clock binding, shall contain 1.
|
||||
- #reset-cells: from common reset binding, shall contain 1.
|
||||
|
||||
Example:
|
||||
turingcc: clock-controller@800000 {
|
||||
compatible = "qcom,qcs404-turingcc";
|
||||
reg = <0x00800000 0x30000>;
|
||||
clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
|
@ -32,12 +32,16 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks: true
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
clock-output-names: true
|
||||
clock-output-names:
|
||||
minItems: 3
|
||||
maxItems: 17
|
||||
|
||||
renesas,mode:
|
||||
description: Board-specific settings of the MD_CK* bits on R-Mobile A1
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@ properties:
|
|||
- renesas,r8a7745-cpg-mssr # RZ/G1E
|
||||
- renesas,r8a77470-cpg-mssr # RZ/G1C
|
||||
- renesas,r8a774a1-cpg-mssr # RZ/G2M
|
||||
- renesas,r8a774a3-cpg-mssr # RZ/G2M v3.0
|
||||
- renesas,r8a774b1-cpg-mssr # RZ/G2N
|
||||
- renesas,r8a774c0-cpg-mssr # RZ/G2E
|
||||
- renesas,r8a774e1-cpg-mssr # RZ/G2H
|
||||
|
|
|
|||
80
dts/upstream/Bindings/clock/renesas,rzv2h-cpg.yaml
Normal file
80
dts/upstream/Bindings/clock/renesas,rzv2h-cpg.yaml
Normal file
|
|
@ -0,0 +1,80 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
|
||||
|
||||
maintainers:
|
||||
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
|
||||
|
||||
description:
|
||||
On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
|
||||
and control of clock signals for the IP modules, generation and control of resets,
|
||||
and control over booting, low power consumption and power supply domains.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: renesas,r9a09g057-cpg
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: AUDIO_EXTAL clock input
|
||||
- description: RTXIN clock input
|
||||
- description: QEXTAL clock input
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: audio_extal
|
||||
- const: rtxin
|
||||
- const: qextal
|
||||
|
||||
'#clock-cells':
|
||||
description: |
|
||||
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
|
||||
and a core clock reference, as defined in
|
||||
<dt-bindings/clock/renesas,r9a09g057-cpg.h>,
|
||||
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
|
||||
a module number. The module number is calculated as the CLKON register
|
||||
offset index multiplied by 16, plus the actual bit in the register
|
||||
used to turn the CLK ON. For example, for CGC_GIC_0_GICCLK, the
|
||||
calculation is (1 * 16 + 3) = 0x13.
|
||||
const: 2
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 0
|
||||
|
||||
'#reset-cells':
|
||||
description:
|
||||
The single reset specifier cell must be the reset number. The reset number
|
||||
is calculated as the reset register offset index multiplied by 16, plus the
|
||||
actual bit in the register used to reset the specific IP block. For example,
|
||||
for SYS_0_PRESETN, the calculation is (3 * 16 + 0) = 0x30.
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#power-domain-cells'
|
||||
- '#reset-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@10420000 {
|
||||
compatible = "renesas,r9a09g057-cpg";
|
||||
reg = <0x10420000 0x10000>;
|
||||
clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
|
||||
clock-names = "audio_extal", "rtxin", "qextal";
|
||||
#clock-cells = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
56
dts/upstream/Bindings/clock/rockchip,rk3576-cru.yaml
Normal file
56
dts/upstream/Bindings/clock/rockchip,rk3576-cru.yaml
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3576-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip rk3576 Family Clock and Reset Control Module
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
- Detlev Casanova <detlev.casanova@collabora.com>
|
||||
|
||||
description:
|
||||
The RK3576 clock controller generates the clock and also implements a reset
|
||||
controller for SoC peripherals. For example it provides SCLK_UART2 and
|
||||
PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART
|
||||
module.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: rockchip,rk3576-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xin24m
|
||||
- const: xin32k
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@27200000 {
|
||||
compatible = "rockchip,rk3576-cru";
|
||||
reg = <0xfd7c0000 0x5c000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
|
@ -42,10 +42,6 @@ properties:
|
|||
- const: xin24m
|
||||
- const: xin32k
|
||||
|
||||
assigned-clocks: true
|
||||
|
||||
assigned-clock-rates: true
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: >
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@ properties:
|
|||
- samsung,exynosautov9-cmu-top
|
||||
- samsung,exynosautov9-cmu-busmc
|
||||
- samsung,exynosautov9-cmu-core
|
||||
- samsung,exynosautov9-cmu-dpum
|
||||
- samsung,exynosautov9-cmu-fsys0
|
||||
- samsung,exynosautov9-cmu-fsys1
|
||||
- samsung,exynosautov9-cmu-fsys2
|
||||
|
|
@ -109,6 +110,24 @@ allOf:
|
|||
- const: oscclk
|
||||
- const: dout_clkcmu_core_bus
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov9-cmu-dpum
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: DPU Main bus clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
162
dts/upstream/Bindings/clock/samsung,exynosautov920-clock.yaml
Normal file
162
dts/upstream/Bindings/clock/samsung,exynosautov920-clock.yaml
Normal file
|
|
@ -0,0 +1,162 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/samsung,exynosautov920-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung ExynosAuto v920 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Sunyeal Hong <sunyeal.hong@samsung.com>
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
|
||||
description: |
|
||||
ExynosAuto v920 clock controller is comprised of several CMU units, generating
|
||||
clocks for different domains. Those CMU units are modeled as separate device
|
||||
tree nodes, and might depend on each other. Root clocks in that clock tree are
|
||||
two external clocks:: OSCCLK/XTCXO (38.4 MHz) and RTCCLK/XrtcXTI (32768 Hz).
|
||||
The external OSCCLK must be defined as fixed-rate clock in dts.
|
||||
|
||||
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
|
||||
dividers; all other clocks of function blocks (other CMUs) are usually
|
||||
derived from CMU_TOP.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All clocks available for usage
|
||||
in clock consumer nodes are defined as preprocessor macros in
|
||||
'include/dt-bindings/clock/samsung,exynosautov920.h' header.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynosautov920-cmu-top
|
||||
- samsung,exynosautov920-cmu-peric0
|
||||
- samsung,exynosautov920-cmu-peric1
|
||||
- samsung,exynosautov920-cmu-misc
|
||||
- samsung,exynosautov920-cmu-hsi0
|
||||
- samsung,exynosautov920-cmu-hsi1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov920-cmu-top
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (38.4 MHz)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- samsung,exynosautov920-cmu-peric0
|
||||
- samsung,exynosautov920-cmu-peric1
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (38.4 MHz)
|
||||
- description: CMU_PERICn NOC clock (from CMU_TOP)
|
||||
- description: CMU_PERICn IP clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: noc
|
||||
- const: ip
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynosautov920-cmu-misc
|
||||
- samsung,exynosautov920-cmu-hsi0
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (38.4 MHz)
|
||||
- description: CMU_MISC/CMU_HSI0 NOC clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: noc
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov920-cmu-hsi1
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (38.4 MHz)
|
||||
- description: CMU_HSI1 NOC clock (from CMU_TOP)
|
||||
- description: CMU_HSI1 USBDRD clock (from CMU_TOP)
|
||||
- description: CMU_HSI1 MMC_CARD clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: noc
|
||||
- const: usbdrd
|
||||
- const: mmc_card
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Clock controller node for CMU_PERIC0
|
||||
- |
|
||||
#include <dt-bindings/clock/samsung,exynosautov920.h>
|
||||
|
||||
cmu_peric0: clock-controller@10800000 {
|
||||
compatible = "samsung,exynosautov920-cmu-peric0";
|
||||
reg = <0x10800000 0x8000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&xtcxo>,
|
||||
<&cmu_top DOUT_CLKCMU_PERIC0_NOC>,
|
||||
<&cmu_top DOUT_CLKCMU_PERIC0_IP>;
|
||||
clock-names = "oscclk",
|
||||
"noc",
|
||||
"ip";
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -60,8 +60,14 @@ properties:
|
|||
- st,stm32mp1-rcc
|
||||
- st,stm32mp13-rcc
|
||||
- const: syscon
|
||||
clocks: true
|
||||
clock-names: true
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -385,7 +385,7 @@ patternProperties:
|
|||
|
||||
This property is required in idle state nodes of device tree meant
|
||||
for RISC-V systems. For more details on the suspend_type parameter
|
||||
refer the SBI specifiation v0.3 (or higher) [7].
|
||||
refer the SBI specification v0.3 (or higher) [7].
|
||||
|
||||
local-timer-stop:
|
||||
description:
|
||||
|
|
|
|||
|
|
@ -1,37 +0,0 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/cpu/nvidia,tegra186-ccplex-cluster.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra186 CCPLEX Cluster
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: nvidia,tegra186-ccplex-cluster
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
nvidia,bpmp:
|
||||
description: phandle to the BPMP used to query CPU frequency tables
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- nvidia,bpmp
|
||||
|
||||
examples:
|
||||
- |
|
||||
ccplex@e000000 {
|
||||
compatible = "nvidia,tegra186-ccplex-cluster";
|
||||
reg = <0x0e000000 0x400000>;
|
||||
nvidia,bpmp = <&bpmp>;
|
||||
};
|
||||
|
|
@ -137,7 +137,10 @@ patternProperties:
|
|||
- const: fsl,sec-v4.0-rtic
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
items:
|
||||
- description: RTIC control and status register space.
|
||||
- description: RTIC recoverable error indication register space.
|
||||
minItems: 1
|
||||
|
||||
ranges:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@ properties:
|
|||
- qcom,prng-ee # 8996 and later using EE
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sa8255p-trng
|
||||
- qcom,sa8775p-trng
|
||||
- qcom,sc7280-trng
|
||||
- qcom,sm8450-trng
|
||||
|
|
|
|||
|
|
@ -92,12 +92,31 @@ properties:
|
|||
reference to a valid DPI output or input endpoint node.
|
||||
|
||||
port@2:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description: |
|
||||
eDP/DP output port. The remote endpoint phandle should be a
|
||||
reference to a valid eDP panel input endpoint node. This port is
|
||||
optional, treated as DP panel if not defined
|
||||
|
||||
properties:
|
||||
endpoint:
|
||||
$ref: /schemas/media/video-interfaces.yaml#
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
toshiba,pre-emphasis:
|
||||
description:
|
||||
Display port output Pre-Emphasis settings for both DP lanes.
|
||||
$ref: /schemas/types.yaml#/definitions/uint8-array
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
items:
|
||||
enum:
|
||||
- 0 # No pre-emphasis
|
||||
- 1 # 3.5dB pre-emphasis
|
||||
- 2 # 6dB pre-emphasis
|
||||
|
||||
oneOf:
|
||||
- required:
|
||||
- port@0
|
||||
|
|
|
|||
54
dts/upstream/Bindings/display/elgin,jg10309-01.yaml
Normal file
54
dts/upstream/Bindings/display/elgin,jg10309-01.yaml
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/elgin,jg10309-01.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Elgin JG10309-01 SPI-controlled display
|
||||
|
||||
maintainers:
|
||||
- Fabio Estevam <festevam@gmail.com>
|
||||
|
||||
description: |
|
||||
The Elgin JG10309-01 SPI-controlled display is used on the RV1108-Elgin-r1
|
||||
board and is a custom display.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/spi/spi-peripheral-props.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: elgin,jg10309-01
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
spi-max-frequency:
|
||||
maximum: 24000000
|
||||
|
||||
spi-cpha: true
|
||||
|
||||
spi-cpol: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- spi-cpha
|
||||
- spi-cpol
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
display@0 {
|
||||
compatible = "elgin,jg10309-01";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <24000000>;
|
||||
spi-cpha;
|
||||
spi-cpol;
|
||||
};
|
||||
};
|
||||
|
|
@ -50,6 +50,14 @@ properties:
|
|||
- const: disp_axi
|
||||
minItems: 1
|
||||
|
||||
dmas:
|
||||
items:
|
||||
- description: DMA specifier for the RX DMA channel.
|
||||
|
||||
dma-names:
|
||||
items:
|
||||
- const: rx
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: LCDIF DMA interrupt
|
||||
|
|
@ -156,6 +164,18 @@ allOf:
|
|||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- fsl,imx28-lcdif
|
||||
then:
|
||||
properties:
|
||||
dmas: false
|
||||
dma-names: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/imx6sx-clock.h>
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@ maintainers:
|
|||
description:
|
||||
This binding extends the data mapping defined in lvds-data-mapping.yaml.
|
||||
It supports reversing the bit order on the formats defined there in order
|
||||
to accomodate for even more specialized data formats, since a variety of
|
||||
to accommodate for even more specialized data formats, since a variety of
|
||||
data formats and layouts is used to drive LVDS displays.
|
||||
|
||||
properties:
|
||||
|
|
|
|||
|
|
@ -62,6 +62,19 @@ properties:
|
|||
- const: default
|
||||
- const: sleep
|
||||
|
||||
power-domains:
|
||||
description: |
|
||||
The MediaTek DPI module is typically associated with one of the
|
||||
following multimedia power domains:
|
||||
POWER_DOMAIN_DISPLAY
|
||||
POWER_DOMAIN_VDOSYS
|
||||
POWER_DOMAIN_MM
|
||||
The specific power domain used varies depending on the SoC design.
|
||||
|
||||
It is recommended to explicitly add the appropriate power domain
|
||||
property to the DPI node in the device tree.
|
||||
maxItems: 1
|
||||
|
||||
port:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@ properties:
|
|||
description: A phandle and PM domain specifier as defined by bindings of
|
||||
the power controller specified by phandle. See
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml for details.
|
||||
maxItems: 1
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description:
|
||||
|
|
@ -57,6 +58,9 @@ properties:
|
|||
clocks:
|
||||
items:
|
||||
- description: SPLIT Clock
|
||||
- description: Used for interfacing with the HDMI RX signal source.
|
||||
- description: Paired with receiving HDMI RX metadata.
|
||||
minItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
|
@ -72,9 +76,24 @@ allOf:
|
|||
const: mediatek,mt8195-mdp3-split
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 3
|
||||
|
||||
required:
|
||||
- mediatek,gce-client-reg
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: mediatek,mt8173-disp-split
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
|
|
|||
|
|
@ -19,14 +19,15 @@ properties:
|
|||
- qcom,hdmi-tx-8974
|
||||
- qcom,hdmi-tx-8994
|
||||
- qcom,hdmi-tx-8996
|
||||
- qcom,hdmi-tx-8998
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
maxItems: 8
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
maxItems: 8
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
|
|
@ -142,6 +143,7 @@ allOf:
|
|||
properties:
|
||||
clocks:
|
||||
minItems: 5
|
||||
maxItems: 5
|
||||
clock-names:
|
||||
items:
|
||||
- const: mdp_core
|
||||
|
|
@ -151,6 +153,28 @@ allOf:
|
|||
- const: extp
|
||||
hdmi-mux-supplies: false
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,hdmi-tx-8998
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
clock-names:
|
||||
items:
|
||||
- const: mdp_core
|
||||
- const: iface
|
||||
- const: core
|
||||
- const: alt_iface
|
||||
- const: extp
|
||||
- const: bus
|
||||
- const: mnoc
|
||||
- const: iface_mmss
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
|
|
|||
|
|
@ -9,20 +9,20 @@ title: BOE TH101MB31IG002-28A WXGA DSI Display Panel
|
|||
maintainers:
|
||||
- Manuel Traut <manut@mecka.net>
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
# BOE TH101MB31IG002-28A 10.1" WXGA TFT LCD panel
|
||||
- boe,th101mb31ig002-28a
|
||||
# The Starry-er88577 is a 10.1" WXGA TFT-LCD panel
|
||||
- starry,er88577
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
backlight: true
|
||||
enable-gpios: true
|
||||
reset-gpios: true
|
||||
power-supply: true
|
||||
port: true
|
||||
rotation: true
|
||||
|
|
@ -33,6 +33,20 @@ required:
|
|||
- enable-gpios
|
||||
- power-supply
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
# The Starry-er88577 is a 10.1" WXGA TFT-LCD panel
|
||||
const: starry,er88577
|
||||
then:
|
||||
properties:
|
||||
reset-gpios: false
|
||||
else:
|
||||
required:
|
||||
- reset-gpios
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
|
@ -47,6 +61,7 @@ examples:
|
|||
reg = <0>;
|
||||
backlight = <&backlight_lcd0>;
|
||||
enable-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>;
|
||||
reset-gpios = <&gpio 55 GPIO_ACTIVE_LOW>;
|
||||
rotation = <90>;
|
||||
power-supply = <&vcc_3v3>;
|
||||
port {
|
||||
|
|
|
|||
63
dts/upstream/Bindings/display/panel/boe,tv101wum-ll2.yaml
Normal file
63
dts/upstream/Bindings/display/panel/boe,tv101wum-ll2.yaml
Normal file
|
|
@ -0,0 +1,63 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/panel/boe,tv101wum-ll2.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: BOE TV101WUM-LL2 DSI Display Panel
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: boe,tv101wum-ll2
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: DSI virtual channel
|
||||
|
||||
backlight: true
|
||||
reset-gpios: true
|
||||
vsp-supply: true
|
||||
vsn-supply: true
|
||||
port: true
|
||||
rotation: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reset-gpios
|
||||
- vsp-supply
|
||||
- vsn-supply
|
||||
- port
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
dsi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
panel@0 {
|
||||
compatible = "boe,tv101wum-ll2";
|
||||
reg = <0>;
|
||||
|
||||
vsn-supply = <&vsn_lcd>;
|
||||
vsp-supply = <&vsp_lcd>;
|
||||
|
||||
reset-gpios = <&pio 45 GPIO_ACTIVE_LOW>;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&dsi_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -15,14 +15,12 @@ description:
|
|||
such as the HannStar HSD060BHW4 720x1440 TFT LCD panel connected with
|
||||
a MIPI-DSI video interface.
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- hannstar,hsd060bhw4
|
||||
- microchip,ac40t08a-mipi-panel
|
||||
- powkiddy,x55-panel
|
||||
- const: himax,hx8394
|
||||
|
||||
|
|
@ -46,7 +44,6 @@ properties:
|
|||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reset-gpios
|
||||
- backlight
|
||||
- port
|
||||
- vcc-supply
|
||||
|
|
@ -54,6 +51,18 @@ required:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- microchip,ac40t08a-mipi-panel
|
||||
then:
|
||||
required:
|
||||
- reset-gpios
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@ properties:
|
|||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- densitron,dmt028vghmcmi-1d
|
||||
- ortustech,com35h3p70ulc
|
||||
- const: ilitek,ili9806e
|
||||
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@ properties:
|
|||
- enum:
|
||||
- chongzhou,cz101b4001
|
||||
- kingdisplay,kd101ne3-40ti
|
||||
- melfas,lmfbx101117480
|
||||
- radxa,display-10hd-ad001
|
||||
- radxa,display-8hd-ad002
|
||||
- const: jadard,jd9365da-h3
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Add table
Reference in a new issue