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imx: imx8mm/n/p-venice: enable pinctrl_wdog in SPL

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Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,

The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan 2022-06-11 20:21:05 +08:00 • committed by Stefano Babic
parent 333a6fa12f
commit 6692cd967d
4 changed files with 12 additions and 29 deletions
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4
arch/arm/dts/imx8mm-venice-u-boot.dtsi
View file

@ -72,3 +72,7 @@
&wdog1 { &wdog1 {
u-boot,dm-spl; u-boot,dm-spl;
}; };
&pinctrl_wdog {
u-boot,dm-spl;
};

4
arch/arm/dts/imx8mn-venice-u-boot.dtsi
View file

@ -110,6 +110,10 @@
u-boot,dm-spl; u-boot,dm-spl;
}; };
&pinctrl_wdog {
u-boot,dm-spl;
};
&binman { &binman {
u-boot-spl-ddr { u-boot-spl-ddr {
align = <4>; align = <4>;

4
arch/arm/dts/imx8mp-venice-u-boot.dtsi
View file

@ -72,3 +72,7 @@
&wdog1 { &wdog1 {
u-boot,dm-spl; u-boot,dm-spl;
}; };
&pinctrl_wdog {
u-boot,dm-spl;
};

29
board/gateworks/venice/spl.c
View file

@ -87,33 +87,6 @@ static void spl_dram_init(int size)
ddr_init(dram_timing); ddr_init(dram_timing);
} }
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#ifdef CONFIG_IMX8MM
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
#elif CONFIG_IMX8MN
static const iomux_v3_cfg_t wdog_pads[] = {
IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
#elif CONFIG_IMX8MP
static const iomux_v3_cfg_t wdog_pads[] = {
MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
#endif
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
return 0;
}
/* /*
* Model specific PMIC adjustments necessary prior to DRAM init * Model specific PMIC adjustments necessary prior to DRAM init
* *
@ -253,8 +226,6 @@ void board_init_f(ulong dummy)
init_uart_clk(1); init_uart_clk(1);
board_early_init_f();
timer_init(); timer_init();
/* Clear the BSS. */ /* Clear the BSS. */