net: phy: Replace PHY_ANEG_TIMEOUT with Kconfig symbol

Switch PHY_ANEG_TIMEOUT to CONFIG_PHY_ANEG_TIMEOUT Kconfig symbol.
This removes one more configuration headers option finalizes its
Kconfig symbol conversion. No functional change expected.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut 2024-05-31 18:47:17 +02:00 committed by Tom Rini
parent 4031a4299c
commit 6610375959
116 changed files with 75 additions and 89 deletions

View file

@ -74,6 +74,7 @@ CONFIG_SYS_NAND_OOBSIZE=0xe0
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y

View file

@ -50,6 +50,7 @@ CONFIG_DFU_SF=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_POWER_TPS65218=y

View file

@ -64,6 +64,7 @@ CONFIG_SYS_NAND_OOBSIZE=0xe0
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y

View file

@ -77,6 +77,7 @@ CONFIG_SYS_NAND_OOBSIZE=0xe0
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y

View file

@ -70,6 +70,7 @@ CONFIG_SYS_NAND_OOBSIZE=0xe0
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y

View file

@ -51,6 +51,7 @@ CONFIG_DFU_SF=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_POWER_TPS65218=y

View file

@ -94,6 +94,7 @@ CONFIG_HSMMC2_8BIT=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_MII=y

View file

@ -90,6 +90,7 @@ CONFIG_HSMMC2_8BIT=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_MII=y

View file

@ -88,6 +88,7 @@ CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_MII=y

View file

@ -99,6 +99,7 @@ CONFIG_SYS_MXC_I2C3_SPEED=400000
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ANEG_TIMEOUT=15000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_FEC_MXC=y

View file

@ -64,6 +64,7 @@ CONFIG_MMC_SDHCI_MV=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y

View file

@ -65,6 +65,7 @@ CONFIG_MMC_SDHCI_MV=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y

View file

@ -65,6 +65,7 @@ CONFIG_MMC_SDHCI_MV=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y

View file

@ -85,6 +85,7 @@ CONFIG_SF_DEFAULT_BUS=1
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y

View file

@ -64,6 +64,7 @@ CONFIG_MISC=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVPP2=y

View file

@ -71,6 +71,7 @@ CONFIG_SF_DEFAULT_BUS=1
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y

View file

@ -75,6 +75,7 @@ CONFIG_SF_DEFAULT_BUS=1
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y

View file

@ -68,6 +68,7 @@ CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y

View file

@ -70,6 +70,7 @@ CONFIG_NAND_PXA3XX=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y

View file

@ -71,6 +71,7 @@ CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y

View file

@ -68,6 +68,7 @@ CONFIG_SYS_I2C_MVTWSI=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_ANEG_TIMEOUT=16000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y

View file

@ -64,6 +64,7 @@ CONFIG_MMC_SDHCI_MV=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y

View file

@ -68,6 +68,7 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_RENESAS_RAVB=y
CONFIG_DM_REGULATOR=y

View file

@ -61,6 +61,8 @@ CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MSM=y
CONFIG_PHYLIB=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y

View file

@ -124,6 +124,7 @@ CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_PHY_FIXED=y

View file

@ -193,6 +193,7 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_DM_MDIO=y

View file

@ -87,6 +87,7 @@ CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DWC_ETH_QOS=y

View file

@ -113,6 +113,7 @@ CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y

View file

@ -206,6 +206,7 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT=y
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_MICREL=y

View file

@ -76,6 +76,7 @@ CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y

View file

@ -201,6 +201,7 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT=y
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_PHY_SMSC=y

View file

@ -208,6 +208,7 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT=y
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_PHY_SMSC=y

View file

@ -93,6 +93,7 @@ CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y

View file

@ -126,6 +126,7 @@ CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y

View file

@ -127,6 +127,7 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y

View file

@ -74,6 +74,7 @@ CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PHYLIB=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_FEC_MXC=y

View file

@ -98,6 +98,7 @@ CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y

View file

@ -95,6 +95,7 @@ CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y

View file

@ -112,6 +112,7 @@ CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_ADIN=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_REALTEK=y

View file

@ -81,6 +81,7 @@ CONFIG_SF_DEFAULT_BUS=1
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_ANEG_TIMEOUT=10000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y

View file

@ -57,6 +57,7 @@ CONFIG_SF_DEFAULT_BUS=1
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_ANEG_TIMEOUT=10000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y

View file

@ -83,6 +83,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_TI=y
CONFIG_PHY_GIGE=y
CONFIG_FEC_MXC=y

View file

@ -77,6 +77,7 @@ CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MSCC=y
CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y

View file

@ -53,6 +53,7 @@ CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y

View file

@ -85,6 +85,7 @@ CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_TI=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y

View file

@ -75,6 +75,7 @@ CONFIG_NAND_PXA3XX=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y

View file

@ -63,6 +63,7 @@ CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_DM_MDIO=y
CONFIG_DM_ETH_PHY=y

View file

@ -67,6 +67,7 @@ CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y

View file

@ -72,6 +72,7 @@ CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y

View file

@ -75,6 +75,7 @@ CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y

View file

@ -68,6 +68,7 @@ CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y

View file

@ -89,6 +89,7 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y

View file

@ -86,6 +86,7 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y

View file

@ -61,6 +61,7 @@ CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y

View file

@ -64,6 +64,7 @@ CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHYLIB_10G=y
CONFIG_PHY_MARVELL_10G=y
CONFIG_DM_ETH_PHY=y

View file

@ -60,6 +60,7 @@ CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y

View file

@ -60,6 +60,7 @@ CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y

View file

@ -92,6 +92,7 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y

View file

@ -90,6 +90,7 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH_PHY=y

View file

@ -66,6 +66,7 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y

View file

@ -68,6 +68,7 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_RENESAS_RAVB=y
CONFIG_DM_REGULATOR=y

View file

@ -67,6 +67,7 @@ CONFIG_MMC_DW=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y

View file

@ -133,6 +133,7 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_DWC_ETH_QOS=y
CONFIG_KS8851_MLL=y
CONFIG_PHY=y

View file

@ -131,6 +131,7 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DWC_ETH_QOS=y

View file

@ -78,6 +78,7 @@ CONFIG_SYS_I2C_MVTWSI=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y

View file

@ -96,6 +96,7 @@ CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_FIXED=y
CONFIG_DM_DSA=y

View file

@ -101,6 +101,7 @@ CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y

View file

@ -102,6 +102,7 @@ CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_ADIN=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y

View file

@ -158,6 +158,7 @@ CONFIG_DM_MTD=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_ADIN=y
CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_XILINX_GMII2RGMII=y

View file

@ -169,6 +169,7 @@ CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_ADIN=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_MICREL=y

View file

@ -566,9 +566,9 @@ int aquantia_startup(struct phy_device *phydev)
if ((i++ % 500) == 0)
printf(".");
} while (!aquantia_link_is_up(phydev) &&
i < (4 * PHY_ANEG_TIMEOUT));
i < (4 * CONFIG_PHY_ANEG_TIMEOUT));
if (i > PHY_ANEG_TIMEOUT)
if (i > CONFIG_PHY_ANEG_TIMEOUT)
printf(" TIMEOUT !\n");
}

View file

@ -250,7 +250,7 @@ int genphy_update_link(struct phy_device *phydev)
/*
* Timeout reached ?
*/
if (i > (PHY_ANEG_TIMEOUT / 50)) {
if (i > (CONFIG_PHY_ANEG_TIMEOUT / 50)) {
printf(" TIMEOUT !\n");
phydev->link = 0;
return -ETIMEDOUT;

View file

@ -361,7 +361,7 @@ static int pcs_pma_startup(struct axidma_priv *priv)
* and the external PHY is not obtained.
*/
debug("axiemac: waiting for link status of the PCS/PMA PHY");
while (retry_cnt * 10 < PHY_ANEG_TIMEOUT) {
while (retry_cnt * 10 < CONFIG_PHY_ANEG_TIMEOUT) {
rc = phyread(priv, priv->pcsaddr, MII_BMSR, &mii_reg);
if ((mii_reg & BMSR_LSTATUS) && mii_reg != 0xffff && !rc) {
debug(".Done\n");

View file

@ -102,8 +102,6 @@
#endif
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
/* NAND support */
#ifdef CONFIG_MTD_RAW_NAND
/* NAND: device related configs */

View file

@ -36,7 +36,6 @@
#include <configs/ti_omap5_common.h>
/* CPSW Ethernet */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
/*
* Default to using SPI for environment, etc.

View file

@ -22,7 +22,6 @@
#define CFG_SYS_FSL_USDHC_NUM 3
/* Network */
#define PHY_ANEG_TIMEOUT 15000 /* PHY needs longer aneg time */
/* USB Configs */
/* Host */

View file

@ -26,8 +26,6 @@
* image and environment
*/
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define RELOCATION_LIMITS_ENV_SETTINGS \
"fdt_high=0x10000000\0" \

View file

@ -15,8 +15,6 @@
/* Environment in SPI NOR flash */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
/*
* Environment Configuration
*/

View file

@ -23,8 +23,6 @@
/* Environment in SPI NOR flash */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros

View file

@ -12,8 +12,6 @@
/* Environment in SPI NOR flash */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
/* NAND */
/* Keep device tree and initrd in lower memory so the kernel can access them */

View file

@ -15,8 +15,6 @@
/* Environment in SPI NOR flash */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define CFG_EXTRA_ENV_SETTINGS \
"fdt_high=0x10000000\0" \

View file

@ -19,8 +19,6 @@
/* Environment in SPI NOR flash */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
/* NAND */
/*

View file

@ -7,8 +7,6 @@
#ifndef _CONFIG_DS116_H
#define _CONFIG_DS116_H
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define RELOCATION_LIMITS_ENV_SETTINGS \
"fdt_high=0x10000000\0" \

View file

@ -55,6 +55,5 @@
/* increase autoneg timeout, my NIC sucks */
#define PHY_ANEG_TIMEOUT 16000
#endif /* _CONFIG_SYNOLOGY_DS414_H */

View file

@ -26,8 +26,6 @@
* image and environment
*/
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define RELOCATION_LIMITS_ENV_SETTINGS \
"fdt_high=0x10000000\0" \

View file

@ -9,7 +9,6 @@
#define __CONFIGS_HMIBSC_H
/* PHY needs a longer aneg time */
#define PHY_ANEG_TIMEOUT 8000
#define CFG_ENV_FLAGS_LIST_STATIC "BOOT_A_LEFT:dw,BOOT_B_LEFT:dw,BOOT_ORDER:sw"

View file

@ -9,7 +9,6 @@
#include <configs/verdin-imx8mm.h>
/* PHY needs a longer autoneg timeout */
#define PHY_ANEG_TIMEOUT 20000
/* Custom initial environment variables */
#undef CFG_EXTRA_ENV_SETTINGS

View file

@ -28,7 +28,6 @@
#define CFG_MXC_UART_BASE UART3_BASE_ADDR
/* PHY needs a longer autonegotiation timeout after reset */
#define PHY_ANEG_TIMEOUT 20000
/* USDHC */
#define CFG_SYS_FSL_USDHC_NUM 2

View file

@ -10,10 +10,6 @@
#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#if defined(CONFIG_CMD_NET)
#define PHY_ANEG_TIMEOUT 20000
#endif
/* Link Definitions */
#define CFG_SYS_INIT_RAM_ADDR 0x40000000

View file

@ -21,7 +21,6 @@
#define CFG_MXC_UART_BASE UART3_BASE_ADDR
/* PHY needs a longer autonegotiation timeout after reset */
#define PHY_ANEG_TIMEOUT 20000
#define FEC_QUIRK_ENET_MAC
#define CFG_EXTRA_ENV_SETTINGS \

View file

@ -16,8 +16,6 @@
#if defined(CONFIG_CMD_NET)
#define CFG_FEC_MXC_PHYADDR 1
#define PHY_ANEG_TIMEOUT 20000
#endif
#define BOOT_TARGET_DEVICES(func) \

View file

@ -21,7 +21,6 @@
#define CFG_MXC_UART_BASE UART1_BASE_ADDR
/* PHY needs a longer autonegotiation timeout after reset */
#define PHY_ANEG_TIMEOUT 20000
#define FEC_QUIRK_ENET_MAC
/* USDHC */

View file

@ -15,8 +15,6 @@
#if defined(CONFIG_CMD_NET)
#define CFG_FEC_MXC_PHYADDR 1
#define PHY_ANEG_TIMEOUT 20000
#endif
#define BOOT_TARGET_DEVICES(func) \

View file

@ -18,8 +18,6 @@
#define DWC_NET_PHYADDR 1
#define PHY_ANEG_TIMEOUT 20000
#endif
#define BOOT_TARGET_DEVICES(func) \

View file

@ -35,8 +35,6 @@
#if defined(CONFIG_CMD_NET)
#define CFG_FEC_MXC_PHYADDR 4
#define PHY_ANEG_TIMEOUT 20000
#endif
#if IS_ENABLED(CONFIG_CMD_MMC)

View file

@ -19,8 +19,6 @@
/* ENET Config */
#if defined(CONFIG_FEC_MXC)
#define PHY_ANEG_TIMEOUT 20000
#define CFG_FEC_MXC_PHYADDR 1
#endif

View file

@ -134,8 +134,4 @@
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG3_BASE_ADDR
#if defined(CONFIG_CMD_NET)
#define PHY_ANEG_TIMEOUT 20000
#endif
#endif

View file

@ -41,8 +41,4 @@
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG3_BASE_ADDR
#if defined(CONFIG_CMD_NET)
#define PHY_ANEG_TIMEOUT 20000
#endif
#endif

View file

@ -11,7 +11,6 @@
/* Network */
#define CFG_KSNET_CPSW_NUM_PORTS 2
#define PHY_ANEG_TIMEOUT 10000 /* PHY needs longer aneg time */
#include <configs/ti_armv7_keystone2.h>

View file

@ -26,8 +26,6 @@
#if defined(CONFIG_CMD_NET)
#define CFG_FEC_MXC_PHYADDR 0
#define PHY_ANEG_TIMEOUT 20000
#endif
#define ENV_MEM_LAYOUT_SETTINGS \

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