From 3a9f642ca946d6a5cda0ecc3f6805976d9d8e660 Mon Sep 17 00:00:00 2001 From: Jim Liu Date: Mon, 29 Apr 2024 14:38:03 +0800 Subject: [PATCH 001/383] crypto: nuvoton: npcm_sha: Support SHA 384/512 1. Use vendor naming rule to rename each function 2. add SHA 384/512 support Signed-off-by: Jim Liu --- drivers/crypto/nuvoton/npcm_sha.c | 1108 ++++++++--------------------- 1 file changed, 294 insertions(+), 814 deletions(-) diff --git a/drivers/crypto/nuvoton/npcm_sha.c b/drivers/crypto/nuvoton/npcm_sha.c index f06be86ca59..6da162069aa 100644 --- a/drivers/crypto/nuvoton/npcm_sha.c +++ b/drivers/crypto/nuvoton/npcm_sha.c @@ -1,867 +1,344 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (c) 2022 Nuvoton Technology Corp. + * Copyright (c) 2024 Nuvoton Technology Corp. */ #include #include #include -#include #include +#include -#define HASH_DIG_H_NUM 8 +#define SHA512_BLOCK_LENGTH (1024 / 8) +/* Register fields */ #define HASH_CTR_STS_SHA_EN BIT(0) #define HASH_CTR_STS_SHA_BUSY BIT(1) #define HASH_CTR_STS_SHA_RST BIT(2) #define HASH_CFG_SHA1_SHA2 BIT(0) +#define SHA512_CMD_SHA_512 BIT(3) +#define SHA512_CMD_INTERNAL_ROUND BIT(2) +#define SHA512_CMD_WRITE BIT(1) +#define SHA512_CMD_READ BIT(0) -/* SHA type */ -enum npcm_sha_type { - npcm_sha_type_sha2 = 0, - npcm_sha_type_sha1, - npcm_sha_type_num +enum { + type_sha1 = 0, + type_sha256, + type_sha384, + type_sha512, }; struct npcm_sha_regs { - unsigned int hash_data_in; - unsigned char hash_ctr_sts; - unsigned char reserved_0[0x03]; - unsigned char hash_cfg; - unsigned char reserved_1[0x03]; - unsigned char hash_ver; - unsigned char reserved_2[0x13]; - unsigned int hash_dig[HASH_DIG_H_NUM]; + u8 data_in; + u8 data_out; + u8 ctr_sts; + u8 hash_cfg; + u8 sha512_cmd; +}; + +struct hash_info { + u32 block_sz; + u32 digest_len; + u8 length_bytes; + u8 type; +}; + +struct message_block { + u64 length[2]; + u64 nonhash_sz; + u8 buffer[SHA512_BLOCK_LENGTH * 2]; }; struct npcm_sha_priv { + void *base; struct npcm_sha_regs *regs; + struct hash_info *hash; + struct message_block block; + bool internal_round; + bool support_sha512; +}; + +static struct npcm_sha_regs npcm_sha_reg_tbl[] = { + { .data_in = 0x0, .data_out = 0x20, .ctr_sts = 0x4, .hash_cfg = 0x8 }, + { .data_in = 0x10, .data_out = 0x1c, .ctr_sts = 0x14, .sha512_cmd = 0x18 }, +}; + +static struct hash_info npcm_hash_tbl[] = { + { .type = type_sha1, .block_sz = 64, .digest_len = 160, .length_bytes = 8 }, + { .type = type_sha256, .block_sz = 64, .digest_len = 256, .length_bytes = 8 }, + { .type = type_sha384, .block_sz = 128, .digest_len = 384, .length_bytes = 16 }, + { .type = type_sha512, .block_sz = 128, .digest_len = 512, .length_bytes = 16 }, }; static struct npcm_sha_priv *sha_priv; -#ifdef SHA_DEBUG_MODULE -#define sha_print(fmt, args...) printf(fmt, ##args) -#else -#define sha_print(fmt, args...) (void)0 -#endif - -#define SHA_BLOCK_LENGTH (512 / 8) -#define SHA_2_HASH_LENGTH (256 / 8) -#define SHA_1_HASH_LENGTH (160 / 8) -#define SHA_HASH_LENGTH(type) ((type == npcm_sha_type_sha2) ? \ - (SHA_2_HASH_LENGTH) : (SHA_1_HASH_LENGTH)) - -#define SHA_SECRUN_BUFF_SIZE 64 -#define SHA_TIMEOUT 100 -#define SHA_DATA_LAST_BYTE 0x80 - -#define SHA2_NUM_OF_SELF_TESTS 3 -#define SHA1_NUM_OF_SELF_TESTS 4 - -#define NUVOTON_ALIGNMENT 4 - -/*-----------------------------------------------------------------------------*/ -/* SHA instance struct handler */ -/*-----------------------------------------------------------------------------*/ -struct SHA_HANDLE_T { - u32 hv[SHA_2_HASH_LENGTH / sizeof(u32)]; - u32 length0; - u32 length1; - u32 block[SHA_BLOCK_LENGTH / sizeof(u32)]; - u8 type; - bool active; -}; - -// The # of bytes currently in the sha block buffer -#define SHA_BUFF_POS(length) ((length) & (SHA_BLOCK_LENGTH - 1)) - -// The # of free bytes in the sha block buffer -#define SHA_BUFF_FREE(length) (SHA_BLOCK_LENGTH - SHA_BUFF_POS(length)) - -static void SHA_FlushLocalBuffer_l(const u32 *buff); -static int SHA_BusyWait_l(void); -static void SHA_GetShaDigest_l(u8 *hashdigest, u8 type); -static void SHA_SetShaDigest_l(const u32 *hashdigest, u8 type); -static void SHA_SetBlock_l(const u8 *data, u32 len, u16 position, u32 *block); -static void SHA_ClearBlock_l(u16 len, u16 position, u32 *block); -static void SHA_SetLength32_l(struct SHA_HANDLE_T *handleptr, u32 *block); - -static int SHA_Init(struct SHA_HANDLE_T *handleptr); -static int SHA_Start(struct SHA_HANDLE_T *handleptr, u8 type); -static int SHA_Update(struct SHA_HANDLE_T *handleptr, const u8 *buffer, u32 len); -static int SHA_Finish(struct SHA_HANDLE_T *handleptr, u8 *hashdigest); -static int SHA_Reset(void); -static int SHA_Power(bool on); -#ifdef SHA_PRINT -static void SHA_PrintRegs(void); -static void SHA_PrintVersion(void); -#endif - -static struct SHA_HANDLE_T sha_handle; - -/*----------------------------------------------------------------------------*/ -/* Checks if give function returns int error, and returns the error */ -/* immediately after SHA disabling */ -/*----------------------------------------------------------------------------*/ -int npcm_sha_check(int status) +static int npcm_sha_init(u8 type) { - if (status != 0) { - SHA_Power(false); - return status; + struct message_block *block = &sha_priv->block; + + if (type > type_sha512 || + (!sha_priv->support_sha512 && + (type == type_sha384 || type == type_sha512))) + return -ENOTSUPP; + + sha_priv->regs = &npcm_sha_reg_tbl[type / 2]; + sha_priv->hash = &npcm_hash_tbl[type]; + block->length[0] = 0; + block->length[1] = 0; + block->nonhash_sz = 0; + sha_priv->internal_round = false; + + return 0; +} + +static void npcm_sha_reset(void) +{ + struct npcm_sha_regs *regs = sha_priv->regs; + struct hash_info *hash = sha_priv->hash; + u8 val; + + if (hash->type == type_sha1) + writeb(HASH_CFG_SHA1_SHA2, sha_priv->base + regs->hash_cfg); + else if (hash->type == type_sha256) + writeb(0, sha_priv->base + regs->hash_cfg); + else if (hash->type == type_sha384) + writeb(0, sha_priv->base + regs->sha512_cmd); + else if (hash->type == type_sha512) + writeb(SHA512_CMD_SHA_512, sha_priv->base + regs->sha512_cmd); + + val = readb(sha_priv->base + regs->ctr_sts) & ~HASH_CTR_STS_SHA_EN; + writeb(val | HASH_CTR_STS_SHA_RST, sha_priv->base + regs->ctr_sts); +} + +static void npcm_sha_enable(bool on) +{ + struct npcm_sha_regs *regs = sha_priv->regs; + u8 val; + + val = readb(sha_priv->base + regs->ctr_sts) & ~HASH_CTR_STS_SHA_EN; + val |= on; + writeb(val | on, sha_priv->base + regs->ctr_sts); +} + +static int npcm_sha_flush_block(u8 *block) +{ + struct npcm_sha_regs *regs = sha_priv->regs; + struct hash_info *hash = sha_priv->hash; + u32 *blk_dw = (u32 *)block; + u8 val; + int i; + + if (readb_poll_timeout(sha_priv->base + regs->ctr_sts, val, + !(val & HASH_CTR_STS_SHA_BUSY), 100)) + return -ETIMEDOUT; + + if (hash->type == type_sha384 || hash->type == type_sha512) { + val = SHA512_CMD_WRITE; + if (hash->type == type_sha512) + val |= SHA512_CMD_SHA_512; + if (sha_priv->internal_round) + val |= SHA512_CMD_INTERNAL_ROUND; + writeb(val, sha_priv->base + regs->sha512_cmd); } - return 0; -} + for (i = 0; i < (hash->block_sz / sizeof(u32)); i++) + writel(blk_dw[i], sha_priv->base + regs->data_in); -/*----------------------------------------------------------------------------*/ -/* Function: npcm_sha_calc */ -/* */ -/* Parameters: type - SHA module type */ -/* inBuff - Pointer to a buffer containing the data to */ -/* be hashed */ -/* len - Length of the data to hash */ -/* hashDigest - Pointer to a buffer where the reseulting */ -/* digest will be copied to */ -/* */ -/* Returns: 0 on success or other int error code on error */ -/* Side effects: */ -/* Description: */ -/* This routine performs complete SHA calculation in one */ -/* step */ -/*----------------------------------------------------------------------------*/ -int npcm_sha_calc(u8 type, const u8 *inbuff, u32 len, u8 *hashdigest) -{ - int status; - struct SHA_HANDLE_T handle; - - SHA_Init(&handle); - SHA_Power(true); - SHA_Reset(); - SHA_Start(&handle, type); - status = SHA_Update(&handle, inbuff, len); - npcm_sha_check(status); - status = SHA_Finish(&handle, hashdigest); - npcm_sha_check(status); - SHA_Power(false); + sha_priv->internal_round = true; return 0; } -/* - * Computes hash value of input pbuf using h/w acceleration - * - * @param in_addr A pointer to the input buffer - * @param bufleni Byte length of input buffer - * @param out_addr A pointer to the output buffer. When complete - * 32 bytes are copied to pout[0]...pout[31]. Thus, a user - * should allocate at least 32 bytes at pOut in advance. - * @param chunk_size chunk size for sha256 - */ -void hw_sha256(const uchar *in_addr, uint buflen, uchar *out_addr, uint chunk_size) +static int npcm_sha_update_block(const u8 *in, u32 len) { - puts("\nhw_sha256 using BMC HW accelerator\t"); - npcm_sha_calc(npcm_sha_type_sha2, (u8 *)in_addr, buflen, (u8 *)out_addr); + struct message_block *block = &sha_priv->block; + struct hash_info *hash = sha_priv->hash; + u8 *buffer = &block->buffer[0]; + u32 block_sz = hash->block_sz; + u32 hash_sz; + + hash_sz = (block->nonhash_sz + len) > block_sz ? + (block_sz - block->nonhash_sz) : len; + memcpy(buffer + block->nonhash_sz, in, hash_sz); + block->nonhash_sz += hash_sz; + block->length[0] += hash_sz; + if (block->length[0] < hash_sz) + block->length[1]++; + + if (block->nonhash_sz == block_sz) { + block->nonhash_sz = 0; + if (npcm_sha_flush_block(buffer)) + return -EBUSY; + } + + return hash_sz; } -/* - * Computes hash value of input pbuf using h/w acceleration - * - * @param in_addr A pointer to the input buffer - * @param bufleni Byte length of input buffer - * @param out_addr A pointer to the output buffer. When complete - * 32 bytes are copied to pout[0]...pout[31]. Thus, a user - * should allocate at least 32 bytes at pOut in advance. - * @param chunk_size chunk_size for sha1 - */ -void hw_sha1(const uchar *in_addr, uint buflen, uchar *out_addr, uint chunk_size) +static int npcm_sha_update(const u8 *input, u32 len) { - puts("\nhw_sha1 using BMC HW accelerator\t"); - npcm_sha_calc(npcm_sha_type_sha1, (u8 *)in_addr, buflen, (u8 *)out_addr); + int hash_sz; + + while (len) { + hash_sz = npcm_sha_update_block(input, len); + if (hash_sz < 0) { + printf("SHA512 module busy\n"); + return -EBUSY; + } + len -= hash_sz; + input += hash_sz; + } + + return 0; +} + +static int npcm_sha_finish(u8 *out) +{ + struct npcm_sha_regs *regs = sha_priv->regs; + struct message_block *block = &sha_priv->block; + struct hash_info *hash = sha_priv->hash; + u8 *buffer = &block->buffer[0]; + u32 block_sz = hash->block_sz; + u32 *out32 = (u32 *)out; + u32 zero_len, val; + u64 *length; + u8 reg_data_out; + int i; + + /* Padding, minimal padding size is last_byte+length_bytes */ + if ((block_sz - block->nonhash_sz) >= (hash->length_bytes + 1)) + zero_len = block_sz - block->nonhash_sz - (hash->length_bytes + 1); + else + zero_len = block_sz * 2 - block->nonhash_sz - (hash->length_bytes + 1); + /* Last byte */ + buffer[block->nonhash_sz++] = 0x80; + /* Zero bits padding */ + memset(&buffer[block->nonhash_sz], 0, zero_len); + block->nonhash_sz += zero_len; + /* Message length */ + length = (u64 *)&buffer[block->nonhash_sz]; + if (hash->length_bytes == 16) { + *length++ = cpu_to_be64(block->length[1] << 3 | block->length[0] >> 61); + block->nonhash_sz += 8; + } + *length = cpu_to_be64(block->length[0] << 3); + block->nonhash_sz += 8; + if (npcm_sha_flush_block(&block->buffer[0])) + return -ETIMEDOUT; + + /* After padding, the last message may produce 2 blocks */ + if (block->nonhash_sz > block_sz) { + if (npcm_sha_flush_block(&block->buffer[block_sz])) + return -ETIMEDOUT; + } + /* Read digest */ + if (readb_poll_timeout(sha_priv->base + regs->ctr_sts, val, + !(val & HASH_CTR_STS_SHA_BUSY), 100)) + return -ETIMEDOUT; + if (hash->type == type_sha384) + writeb(SHA512_CMD_READ, sha_priv->base + regs->sha512_cmd); + else if (hash->type == type_sha512) + writeb(SHA512_CMD_SHA_512 | SHA512_CMD_READ, + sha_priv->base + regs->sha512_cmd); + + reg_data_out = regs->data_out; + for (i = 0; i < (hash->digest_len / 32); i++) { + *out32 = readl(sha_priv->base + reg_data_out); + out32++; + if (hash->type == type_sha1 || hash->type == type_sha256) + reg_data_out += 4; + } + + return 0; +} + +int npcm_sha_calc(const u8 *input, u32 len, u8 *output, u8 type) +{ + if (npcm_sha_init(type)) + return -ENOTSUPP; + npcm_sha_reset(); + npcm_sha_enable(true); + npcm_sha_update(input, len); + npcm_sha_finish(output); + npcm_sha_enable(false); + + return 0; +} + +void hw_sha512(const unsigned char *input, unsigned int len, + unsigned char *output, unsigned int chunk_sz) +{ + if (!sha_priv->support_sha512) { + puts(" HW accelerator not support\n"); + return; + } + puts(" using BMC HW accelerator\n"); + npcm_sha_calc(input, len, output, type_sha512); +} + +void hw_sha384(const unsigned char *input, unsigned int len, + unsigned char *output, unsigned int chunk_sz) +{ + if (!sha_priv->support_sha512) { + puts(" HW accelerator not support\n"); + return; + } + puts(" using BMC HW accelerator\n"); + npcm_sha_calc(input, len, output, type_sha384); +} + +void hw_sha256(const unsigned char *input, unsigned int len, + unsigned char *output, unsigned int chunk_sz) +{ + puts(" using BMC HW accelerator\n"); + npcm_sha_calc(input, len, output, type_sha256); +} + +void hw_sha1(const unsigned char *input, unsigned int len, + unsigned char *output, unsigned int chunk_sz) +{ + puts(" using BMC HW accelerator\n"); + npcm_sha_calc(input, len, output, type_sha1); } -/* - * Create the context for sha progressive hashing using h/w acceleration - * - * @algo: Pointer to the hash_algo struct - * @ctxp: Pointer to the pointer of the context for hashing - * @return 0 if ok, -ve on error - */ int hw_sha_init(struct hash_algo *algo, void **ctxp) { - const char *algo_name1 = "sha1"; - const char *algo_name2 = "sha256"; + if (!strcmp("sha1", algo->name)) { + npcm_sha_init(type_sha1); + } else if (!strcmp("sha256", algo->name)) { + npcm_sha_init(type_sha256); + } else if (!strcmp("sha384", algo->name)) { + if (!sha_priv->support_sha512) + return -ENOTSUPP; + npcm_sha_init(type_sha384); + } else if (!strcmp("sha512", algo->name)) { + if (!sha_priv->support_sha512) + return -ENOTSUPP; + npcm_sha_init(type_sha512); + } else { + return -ENOTSUPP; + } - SHA_Init(&sha_handle); - SHA_Power(true); - SHA_Reset(); - if (!strcmp(algo_name1, algo->name)) - return SHA_Start(&sha_handle, npcm_sha_type_sha1); - else if (!strcmp(algo_name2, algo->name)) - return SHA_Start(&sha_handle, npcm_sha_type_sha2); - else - return -EPROTO; + printf("Using npcm SHA engine\n"); + npcm_sha_reset(); + npcm_sha_enable(true); + + return 0; } -/* - * Update buffer for sha progressive hashing using h/w acceleration - * - * The context is freed by this function if an error occurs. - * - * @algo: Pointer to the hash_algo struct - * @ctx: Pointer to the context for hashing - * @buf: Pointer to the buffer being hashed - * @size: Size of the buffer being hashed - * @is_last: 1 if this is the last update; 0 otherwise - * @return 0 if ok, -ve on error - */ int hw_sha_update(struct hash_algo *algo, void *ctx, const void *buf, unsigned int size, int is_last) { - return SHA_Update(&sha_handle, buf, size); + return npcm_sha_update(buf, size); } -/* - * Copy sha hash result at destination location - * - * The context is freed after completion of hash operation or after an error. - * - * @algo: Pointer to the hash_algo struct - * @ctx: Pointer to the context for hashing - * @dest_buf: Pointer to the destination buffer where hash is to be copied - * @size: Size of the buffer being hashed - * @return 0 if ok, -ve on error - */ -int hw_sha_finish(struct hash_algo *algo, void *ctx, void *dest_buf, int size) +int hw_sha_finish(struct hash_algo *algo, void *ctx, void *dest_buf, + int size) { - int status; + int ret; - status = SHA_Finish(&sha_handle, dest_buf); - npcm_sha_check(status); - return SHA_Power(false); -} + ret = npcm_sha_finish(dest_buf); + npcm_sha_enable(false); -/*----------------------------------------------------------------------------*/ -/* Function: SHA_Init */ -/* */ -/* Parameters: handlePtr - SHA processing handle pointer */ -/* Returns: 0 on success or other int error code on error. */ -/* Side effects: */ -/* Description: */ -/* This routine initialize the SHA module */ -/*----------------------------------------------------------------------------*/ -static int SHA_Init(struct SHA_HANDLE_T *handleptr) -{ - handleptr->active = false; - - return 0; -} - -/*----------------------------------------------------------------------------*/ -/* Function: SHA_Start */ -/* */ -/* Parameters: handlePtr - SHA processing handle pointer */ -/* type - SHA module type */ -/* */ -/* Returns: 0 on success or other int error code on error. */ -/* Side effects: */ -/* Description: */ -/* This routine start a single SHA process */ -/*----------------------------------------------------------------------------*/ -static int SHA_Start(struct SHA_HANDLE_T *handleptr, u8 type) -{ - struct npcm_sha_regs *regs = sha_priv->regs; - - // Initialize handle - handleptr->length0 = 0; - handleptr->length1 = 0; - handleptr->type = type; - handleptr->active = true; - - // Set SHA type - writeb(handleptr->type & HASH_CFG_SHA1_SHA2, ®s->hash_cfg); - - // Reset SHA hardware - SHA_Reset(); - - /* The handlePtr->hv is initialized with the correct IV as the SHA engine - * automatically fill the HASH_DIG_Hn registers according to SHA spec - * (following SHA_RST assertion) - */ - SHA_GetShaDigest_l((u8 *)handleptr->hv, type); - - // Init block with zeros - memset(handleptr->block, 0, sizeof(handleptr->block)); - - return 0; -} - -/*----------------------------------------------------------------------------*/ -/* Function: SHA_Update */ -/* */ -/* Parameters: handlePtr - SHA processing handle pointer */ -/* buffer - Pointer to the data that will be added to */ -/* the hash calculation */ -/* len - Length of data to add to SHA calculation */ -/* */ -/* */ -/* Returns: 0 on success or other int error code on error */ -/* Side effects: */ -/* Description: */ -/* This routine adds data to previously started SHA */ -/* calculation */ -/*----------------------------------------------------------------------------*/ -static int SHA_Update(struct SHA_HANDLE_T *handleptr, const u8 *buffer, u32 len) -{ - struct npcm_sha_regs *regs = sha_priv->regs; - u32 localbuffer[SHA_SECRUN_BUFF_SIZE / sizeof(u32)]; - u32 bufferlen = len; - u16 pos = 0; - u8 *blockptr; - int status; - - // Error check - if (!handleptr->active) - return -EPROTO; - - // Wait till SHA is not busy - status = SHA_BusyWait_l(); - npcm_sha_check(status); - - // Set SHA type - writeb(handleptr->type & HASH_CFG_SHA1_SHA2, ®s->hash_cfg); - - // Write SHA latest digest into SHA module - SHA_SetShaDigest_l(handleptr->hv, handleptr->type); - - // Set number of unhashed bytes which remained from last update - pos = SHA_BUFF_POS(handleptr->length0); - - // Copy unhashed bytes which remained from last update to secrun buffer - SHA_SetBlock_l((u8 *)handleptr->block, pos, 0, localbuffer); - - while (len) { - // Wait for the hardware to be available (in case we are hashing) - status = SHA_BusyWait_l(); - npcm_sha_check(status); - - // Move as much bytes as we can into the secrun buffer - bufferlen = min(len, SHA_BUFF_FREE(handleptr->length0)); - - // Copy current given buffer to the secrun buffer - SHA_SetBlock_l((u8 *)buffer, bufferlen, pos, localbuffer); - - // Update size of hashed bytes - handleptr->length0 += bufferlen; - - if (handleptr->length0 < bufferlen) - handleptr->length1++; - - // Update length of data left to digest - len -= bufferlen; - - // Update given buffer pointer - buffer += bufferlen; - - // If secrun buffer is full - if (SHA_BUFF_POS(handleptr->length0) == 0) { - /* We just filled up the buffer perfectly, so let it hash (we'll - * unload the hash only when we are done with all hashing) - */ - SHA_FlushLocalBuffer_l(localbuffer); - - pos = 0; - bufferlen = 0; - } - } - - // Wait till SHA is not busy - status = SHA_BusyWait_l(); - npcm_sha_check(status); - - /* Copy unhashed bytes from given buffer to handle block for next update/finish */ - blockptr = (u8 *)handleptr->block; - while (bufferlen) - blockptr[--bufferlen + pos] = *(--buffer); - - // Save SHA current digest - SHA_GetShaDigest_l((u8 *)handleptr->hv, handleptr->type); - - return 0; -} - -/*----------------------------------------------------------------------------*/ -/* Function: SHA_Finish */ -/* */ -/* Parameters: handlePtr - SHA processing handle pointer */ -/* hashDigest - Pointer to a buffer where the final digest */ -/* will be copied to */ -/* */ -/* Returns: 0 on success or other int error code on error */ -/* Side effects: */ -/* Description: */ -/* This routine finish SHA calculation and get */ -/* the resulting SHA digest */ -/*----------------------------------------------------------------------------*/ -static int SHA_Finish(struct SHA_HANDLE_T *handleptr, u8 *hashdigest) -{ - struct npcm_sha_regs *regs = sha_priv->regs; - u32 localbuffer[SHA_SECRUN_BUFF_SIZE / sizeof(u32)]; - const u8 lastbyte = SHA_DATA_LAST_BYTE; - u16 pos; - int status; - - // Error check - if (!handleptr->active) - return -EPROTO; - - // Set SHA type - writeb(handleptr->type & HASH_CFG_SHA1_SHA2, ®s->hash_cfg); - - // Wait till SHA is not busy - status = SHA_BusyWait_l(); - npcm_sha_check(status); - - // Finish off the current buffer with the SHA spec'ed padding - pos = SHA_BUFF_POS(handleptr->length0); - - // Init SHA digest - SHA_SetShaDigest_l(handleptr->hv, handleptr->type); - - // Load data into secrun buffer - SHA_SetBlock_l((u8 *)handleptr->block, pos, 0, localbuffer); - - // Set data last byte as in SHA algorithm spec - SHA_SetBlock_l(&lastbyte, 1, pos++, localbuffer); - - // If the remainder of data is longer then one block - if (pos > (SHA_BLOCK_LENGTH - 8)) { - /* The length will be in the next block Pad the rest of the last block with 0's */ - SHA_ClearBlock_l((SHA_BLOCK_LENGTH - pos), pos, localbuffer); - - // Hash the current block - SHA_FlushLocalBuffer_l(localbuffer); - - pos = 0; - - // Wait till SHA is not busy - status = SHA_BusyWait_l(); - npcm_sha_check(status); - } - - // Pad the rest of the last block with 0's except for the last 8-3 bytes - SHA_ClearBlock_l((SHA_BLOCK_LENGTH - (8 - 3)) - pos, pos, localbuffer); - - /* The last 8-3 bytes are set to the bit-length of the message in big-endian form */ - SHA_SetLength32_l(handleptr, localbuffer); - - // Hash all that, and save the hash for the caller - SHA_FlushLocalBuffer_l(localbuffer); - - // Wait till SHA is not busy - status = SHA_BusyWait_l(); - npcm_sha_check(status); - - // Save SHA final digest into given buffer - SHA_GetShaDigest_l(hashdigest, handleptr->type); - - // Free handle - handleptr->active = false; - - return 0; -} - -/*----------------------------------------------------------------------------*/ -/* Function: SHA_Reset */ -/* */ -/* Parameters: none */ -/* Returns: none */ -/* Side effects: */ -/* Description: */ -/* This routine reset SHA module */ -/*----------------------------------------------------------------------------*/ -static int SHA_Reset(void) -{ - struct npcm_sha_regs *regs = sha_priv->regs; - - writel(readl(®s->hash_ctr_sts) | HASH_CTR_STS_SHA_RST, ®s->hash_ctr_sts); - - return 0; -} - -/*----------------------------------------------------------------------------*/ -/* Function: SHA_Power */ -/* */ -/* Parameters: on - true enable the module, false disable the module */ -/* Returns: none */ -/* Side effects: */ -/* Description: */ -/* This routine set SHA module power on/off */ -/*----------------------------------------------------------------------------*/ -static int SHA_Power(bool on) -{ - struct npcm_sha_regs *regs = sha_priv->regs; - u8 hash_sts; - - hash_sts = readb(®s->hash_ctr_sts) & ~HASH_CTR_STS_SHA_EN; - writeb(hash_sts | (on & HASH_CTR_STS_SHA_EN), ®s->hash_ctr_sts); - - return 0; -} - -#ifdef SHA_PRINT -/*----------------------------------------------------------------------------*/ -/* Function: SHA_PrintRegs */ -/* */ -/* Parameters: none */ -/* Returns: none */ -/* Side effects: */ -/* Description: */ -/* This routine prints the module registers */ -/*----------------------------------------------------------------------------*/ -static void SHA_PrintRegs(void) -{ -#ifdef SHA_DEBUG_MODULE - struct npcm_sha_regs *regs = sha_priv->regs; -#endif - unsigned int i; - - sha_print("/*--------------*/\n"); - sha_print("/* SHA */\n"); - sha_print("/*--------------*/\n\n"); - - sha_print("HASH_CTR_STS = 0x%02X\n", readb(®s->hash_ctr_sts)); - sha_print("HASH_CFG = 0x%02X\n", readb(®s->hash_cfg)); - - for (i = 0; i < HASH_DIG_H_NUM; i++) - sha_print("HASH_DIG_H%d = 0x%08X\n", i, readl(®s->hash_dig[i])); - - sha_print("HASH_VER = 0x%08X\n", readb(®s->hash_ver)); - - sha_print("\n"); -} - -/*----------------------------------------------------------------------------*/ -/* Function: SHA_PrintVersion */ -/* */ -/* Parameters: none */ -/* Returns: none */ -/* Side effects: */ -/* Description: */ -/* This routine prints the module version */ -/*----------------------------------------------------------------------------*/ -static void SHA_PrintVersion(void) -{ - struct npcm_sha_regs *regs = sha_priv->regs; - - printf("SHA MODULE VER = %d\n", readb(®s->hash_ver)); -} -#endif - -/*----------------------------------------------------------------------------*/ -/* Function: npcm_sha_selftest */ -/* */ -/* Parameters: type - SHA module type */ -/* Returns: 0 on success or other int error code on error */ -/* Side effects: */ -/* Description: */ -/* This routine performs various tests on the SHA HW and SW */ -/*----------------------------------------------------------------------------*/ -int npcm_sha_selftest(u8 type) -{ - int status; - struct SHA_HANDLE_T handle; - u8 hashdigest[max(SHA_1_HASH_LENGTH, SHA_2_HASH_LENGTH)]; - u16 i, j; - - /*------------------------------------------------------------------------*/ - /* SHA1 tests info */ - /*------------------------------------------------------------------------*/ - - static const u8 sha1selftestbuff[SHA1_NUM_OF_SELF_TESTS][94] = { - {"abc"}, - {"abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"}, - {"0123456789012345678901234567890123456789012345678901234567890123"}, - {0x30, 0x5c, 0x30, 0x2c, 0x02, 0x01, 0x00, 0x30, 0x09, 0x06, 0x05, 0x2b, - 0x0e, 0x03, 0x02, 0x1a, 0x05, 0x00, 0x30, 0x06, 0x06, 0x04, 0x67, 0x2a, - 0x01, 0x0c, 0x04, 0x14, 0xe1, 0xb6, 0x93, 0xfe, 0x33, 0x43, 0xc1, 0x20, - 0x5d, 0x4b, 0xaa, 0xb8, 0x63, 0xfb, 0xcf, 0x6c, 0x46, 0x1e, 0x88, 0x04, - 0x30, 0x2c, 0x02, 0x01, 0x00, 0x30, 0x09, 0x06, 0x05, 0x2b, 0x0e, 0x03, - 0x02, 0x1a, 0x05, 0x00, 0x30, 0x06, 0x06, 0x04, 0x67, 0x2a, 0x01, 0x0c, - 0x04, 0x14, 0x13, 0xc1, 0x0c, 0xfc, 0xc8, 0x92, 0xd7, 0xde, 0x07, 0x1c, - 0x40, 0xde, 0x4f, 0xcd, 0x07, 0x5b, 0x68, 0x20, 0x5a, 0x6c} - }; - - static const u8 sha1selftestbufflen[SHA1_NUM_OF_SELF_TESTS] = { - 3, 56, 64, 94 - }; - - static const u8 sha1selftestexpres[SHA1_NUM_OF_SELF_TESTS][SHA_1_HASH_LENGTH] = { - {0xA9, 0x99, 0x3E, 0x36, - 0x47, 0x06, 0x81, 0x6A, - 0xBA, 0x3E, 0x25, 0x71, - 0x78, 0x50, 0xC2, 0x6C, - 0x9C, 0xD0, 0xD8, 0x9D}, - {0x84, 0x98, 0x3E, 0x44, - 0x1C, 0x3B, 0xD2, 0x6E, - 0xBA, 0xAE, 0x4A, 0xA1, - 0xF9, 0x51, 0x29, 0xE5, - 0xE5, 0x46, 0x70, 0xF1}, - {0xCF, 0x08, 0x00, 0xF7, - 0x64, 0x4A, 0xCE, 0x3C, - 0xB4, 0xC3, 0xFA, 0x33, - 0x38, 0x8D, 0x3B, 0xA0, - 0xEA, 0x3C, 0x8B, 0x6E}, - {0xc9, 0x84, 0x45, 0xc8, - 0x64, 0x04, 0xb1, 0xe3, - 0x3c, 0x6b, 0x0a, 0x8c, - 0x8b, 0x80, 0x94, 0xfc, - 0xf3, 0xc9, 0x98, 0xab} - }; - - /*------------------------------------------------------------------------*/ - /* SHA2 tests info */ - /*------------------------------------------------------------------------*/ - - static const u8 sha2selftestbuff[SHA2_NUM_OF_SELF_TESTS][100] = { - { "abc" }, - { "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq" }, - {'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', - 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', - 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', - 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', - 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', - 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', - 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', - 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', - 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', - 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a'} - }; - - static const u8 sha2selftestbufflen[SHA2_NUM_OF_SELF_TESTS] = { - 3, 56, 100 - }; - - static const u8 sha2selftestexpres[SHA2_NUM_OF_SELF_TESTS][SHA_2_HASH_LENGTH] = { - /* - * SHA-256 test vectors - */ - { 0xBA, 0x78, 0x16, 0xBF, 0x8F, 0x01, 0xCF, 0xEA, - 0x41, 0x41, 0x40, 0xDE, 0x5D, 0xAE, 0x22, 0x23, - 0xB0, 0x03, 0x61, 0xA3, 0x96, 0x17, 0x7A, 0x9C, - 0xB4, 0x10, 0xFF, 0x61, 0xF2, 0x00, 0x15, 0xAD }, - { 0x24, 0x8D, 0x6A, 0x61, 0xD2, 0x06, 0x38, 0xB8, - 0xE5, 0xC0, 0x26, 0x93, 0x0C, 0x3E, 0x60, 0x39, - 0xA3, 0x3C, 0xE4, 0x59, 0x64, 0xFF, 0x21, 0x67, - 0xF6, 0xEC, 0xED, 0xD4, 0x19, 0xDB, 0x06, 0xC1 }, - { 0xCD, 0xC7, 0x6E, 0x5C, 0x99, 0x14, 0xFB, 0x92, - 0x81, 0xA1, 0xC7, 0xE2, 0x84, 0xD7, 0x3E, 0x67, - 0xF1, 0x80, 0x9A, 0x48, 0xA4, 0x97, 0x20, 0x0E, - 0x04, 0x6D, 0x39, 0xCC, 0xC7, 0x11, 0x2C, 0xD0 }, - }; - - if (type == npcm_sha_type_sha1) { - /*--------------------------------------------------------------------*/ - /* SHA 1 TESTS */ - /*--------------------------------------------------------------------*/ - for (i = 0; i < SHA1_NUM_OF_SELF_TESTS; i++) { - if (i != 3) { - status = npcm_sha_calc(npcm_sha_type_sha1, sha1selftestbuff[i], sha1selftestbufflen[i], hashdigest); - npcm_sha_check(status); - } else { - SHA_Power(true); - SHA_Reset(); - status = SHA_Start(&handle, npcm_sha_type_sha1); - npcm_sha_check(status); - status = SHA_Update(&handle, sha1selftestbuff[i], 73); - npcm_sha_check(status); - status = SHA_Update(&handle, &sha1selftestbuff[i][73], sha1selftestbufflen[i] - 73); - npcm_sha_check(status); - status = SHA_Finish(&handle, hashdigest); - npcm_sha_check(status); - SHA_Power(false); - } - - if (memcmp(hashdigest, sha1selftestexpres[i], SHA_1_HASH_LENGTH)) - return -1; - } - - } else { - /*--------------------------------------------------------------------*/ - /* SHA 2 TESTS */ - /*--------------------------------------------------------------------*/ - for (i = 0; i < SHA2_NUM_OF_SELF_TESTS; i++) { - SHA_Power(true); - SHA_Reset(); - status = SHA_Start(&handle, npcm_sha_type_sha2); - npcm_sha_check(status); - if (i == 2) { - for (j = 0; j < 10000; j++) { //not working - status = SHA_Update(&handle, sha2selftestbuff[i], sha2selftestbufflen[i]); - npcm_sha_check(status); - } - } else { - status = SHA_Update(&handle, sha2selftestbuff[i], sha2selftestbufflen[i]); - npcm_sha_check(status); - } - - status = SHA_Finish(&handle, hashdigest); - npcm_sha_check(status); - SHA_Power(false); - if (memcmp(hashdigest, sha2selftestexpres[i], SHA_2_HASH_LENGTH)) - return -1; - - npcm_sha_calc(npcm_sha_type_sha2, sha2selftestbuff[i], sha2selftestbufflen[i], hashdigest); - if (memcmp(hashdigest, sha2selftestexpres[i], SHA_2_HASH_LENGTH)) - return -1; - } - } - - return 0; -} - -/*----------------------------------------------------------------------------*/ -/* Function: SHA_FlushLocalBuffer_l */ -/* */ -/* Parameters: */ -/* Returns: none */ -/* Side effects: */ -/* Description: This routine flush secrun buffer to SHA module */ -/*----------------------------------------------------------------------------*/ -static void SHA_FlushLocalBuffer_l(const u32 *buff) -{ - struct npcm_sha_regs *regs = sha_priv->regs; - u32 i; - - for (i = 0; i < (SHA_BLOCK_LENGTH / sizeof(u32)); i++) - writel(buff[i], ®s->hash_data_in); -} - -/*----------------------------------------------------------------------------*/ -/* Function: SHA_BusyWait_l */ -/* */ -/* Parameters: */ -/* Returns: 0 if no error was found or DEFS_STATUS_ERROR otherwise */ -/* Side effects: */ -/* Description: This routine wait for SHA unit to no longer be busy */ -/*----------------------------------------------------------------------------*/ -static int SHA_BusyWait_l(void) -{ - struct npcm_sha_regs *regs = sha_priv->regs; - u32 timeout = SHA_TIMEOUT; - - do { - if (timeout-- == 0) - return -ETIMEDOUT; - } while ((readb(®s->hash_ctr_sts) & HASH_CTR_STS_SHA_BUSY) - == HASH_CTR_STS_SHA_BUSY); - - return 0; -} - -/*----------------------------------------------------------------------------*/ -/* Function: SHA_GetShaDigest_l */ -/* */ -/* Parameters: hashDigest - buffer for the hash output. */ -/* type - SHA module type */ -/* Returns: none */ -/* Side effects: */ -/* Description: This routine copy the hash digest from the hardware */ -/* and into given buffer (in ram) */ -/*----------------------------------------------------------------------------*/ -static void SHA_GetShaDigest_l(u8 *hashdigest, u8 type) -{ - struct npcm_sha_regs *regs = sha_priv->regs; - u16 j; - u8 len = SHA_HASH_LENGTH(type) / sizeof(u32); - - // Copy Bytes from SHA module to given buffer - for (j = 0; j < len; j++) - ((u32 *)hashdigest)[j] = readl(®s->hash_dig[j]); -} - -/*----------------------------------------------------------------------------*/ -/* Function: SHA_SetShaDigest_l */ -/* */ -/* Parameters: hashDigest - input buffer to set as hash digest */ -/* type - SHA module type */ -/* Returns: none */ -/* Side effects: */ -/* Description: This routine set the hash digest in the hardware from */ -/* a given buffer (in ram) */ -/*----------------------------------------------------------------------------*/ -static void SHA_SetShaDigest_l(const u32 *hashdigest, u8 type) -{ - struct npcm_sha_regs *regs = sha_priv->regs; - u16 j; - u8 len = SHA_HASH_LENGTH(type) / sizeof(u32); - - // Copy Bytes from given buffer to SHA module - for (j = 0; j < len; j++) - writel(hashdigest[j], ®s->hash_dig[j]); -} - -/*----------------------------------------------------------------------------*/ -/* Function: SHA_SetBlock_l */ -/* */ -/* Parameters: data - data to copy */ -/* len - size of data */ -/* position - byte offset into the block at which data */ -/* should be placed */ -/* block - block buffer */ -/* Returns: none */ -/* Side effects: */ -/* Description: This routine load bytes into block buffer */ -/*----------------------------------------------------------------------------*/ -static void SHA_SetBlock_l(const u8 *data, u32 len, u16 position, u32 *block) -{ - u8 *dest = (u8 *)block; - - memcpy(dest + position, data, len); -} - -/*----------------------------------------------------------------------------*/ -/* Function: SHA_SetBlock_l */ -/* */ -/* Parameters: */ -/* len - size of data */ -/* position - byte offset into the block at which data */ -/* should be placed */ -/* block - block buffer */ -/* Returns: none */ -/* Side effects: */ -/* Description: This routine load zero's into the block buffer */ -/*----------------------------------------------------------------------------*/ -static void SHA_ClearBlock_l(u16 len, u16 position, u32 *block) -{ - u8 *dest = (u8 *)block; - - memset(dest + position, 0, len); -} - -/*----------------------------------------------------------------------------*/ -/* Function: SHA_SetLength32_l */ -/* */ -/* Parameters: */ -/* handlePtr - SHA processing handle pointer */ -/* block - block buffer */ -/* Returns: none */ -/* Side effects: */ -/* Description: This routine set the length of the hash's data */ -/* len is the 32-bit byte length of the message */ -/*lint -efunc(734,SHA_SetLength32_l) Supperess loss of percision lint warning */ -/*----------------------------------------------------------------------------*/ -static void SHA_SetLength32_l(struct SHA_HANDLE_T *handleptr, u32 *block) -{ - u16 *secrunbufferswappedptr = (u16 *)(void *)(block); - - secrunbufferswappedptr[(SHA_BLOCK_LENGTH / sizeof(u16)) - 1] = (u16) - ((handleptr->length0 << 3) << 8) | ((u16)(handleptr->length0 << 3) >> 8); - secrunbufferswappedptr[(SHA_BLOCK_LENGTH / sizeof(u16)) - 2] = (u16) - ((handleptr->length0 >> (16 - 3)) >> 8) | ((u16)(handleptr->length0 >> (16 - 3)) << 8); - secrunbufferswappedptr[(SHA_BLOCK_LENGTH / sizeof(u16)) - 3] = (u16) - ((handleptr->length1 << 3) << 8) | ((u16)(handleptr->length1 << 3) >> 8); - secrunbufferswappedptr[(SHA_BLOCK_LENGTH / sizeof(u16)) - 4] = (u16) - ((handleptr->length1 >> (16 - 3)) >> 8) | ((u16)(handleptr->length1 >> (16 - 3)) << 8); + return ret; } static int npcm_sha_bind(struct udevice *dev) @@ -870,12 +347,15 @@ static int npcm_sha_bind(struct udevice *dev) if (!sha_priv) return -ENOMEM; - sha_priv->regs = dev_remap_addr_index(dev, 0); - if (!sha_priv->regs) { + sha_priv->base = dev_read_addr_ptr(dev); + if (!sha_priv->base) { printf("Cannot find sha reg address, binding failed\n"); return -EINVAL; } + if (IS_ENABLED(CONFIG_ARCH_NPCM8XX)) + sha_priv->support_sha512 = true; + printf("SHA: NPCM SHA module bind OK\n"); return 0; From cd85e0d443a40fe5e0814023e1c976127b761351 Mon Sep 17 00:00:00 2001 From: WHR Date: Wed, 1 May 2024 00:28:32 +0800 Subject: [PATCH 002/383] zfs: recognize zpools formatted with features support Currently no features are implemented, only the zpool version 5000 that indicating the features support, is recognized. Since it is possible for OpenZFS to create a pool with features support enabled, but without enabling any actual feature, this change enables U-Boot to read such pools. Signed-off-by: WHR --- fs/zfs/zfs.c | 18 +++++++++++------- include/zfs/zfs.h | 1 + 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/fs/zfs/zfs.c b/fs/zfs/zfs.c index c44e7ece5df..06221e68b35 100644 --- a/fs/zfs/zfs.c +++ b/fs/zfs/zfs.c @@ -333,6 +333,12 @@ vdev_uberblock_compare(uberblock_t *ub1, uberblock_t *ub2) return 0; } +static inline int +is_supported_spa_version(uint64_t version) { + return version == FEATURES_SUPPORTED_SPA_VERSION || + (version > 0 && version <= SPA_VERSION); +} + /* * Three pieces of information are needed to verify an uberblock: the magic * number, the version number, and the checksum. @@ -354,14 +360,12 @@ uberblock_verify(uberblock_t *uber, int offset, struct zfs_data *data) return ZFS_ERR_BAD_FS; } - if (zfs_to_cpu64(uber->ub_magic, LITTLE_ENDIAN) == UBERBLOCK_MAGIC - && zfs_to_cpu64(uber->ub_version, LITTLE_ENDIAN) > 0 - && zfs_to_cpu64(uber->ub_version, LITTLE_ENDIAN) <= SPA_VERSION) + if (zfs_to_cpu64(uber->ub_magic, LITTLE_ENDIAN) == UBERBLOCK_MAGIC && + is_supported_spa_version(zfs_to_cpu64(uber->ub_version, LITTLE_ENDIAN))) endian = LITTLE_ENDIAN; - if (zfs_to_cpu64(uber->ub_magic, BIG_ENDIAN) == UBERBLOCK_MAGIC - && zfs_to_cpu64(uber->ub_version, BIG_ENDIAN) > 0 - && zfs_to_cpu64(uber->ub_version, BIG_ENDIAN) <= SPA_VERSION) + if (zfs_to_cpu64(uber->ub_magic, BIG_ENDIAN) == UBERBLOCK_MAGIC && + is_supported_spa_version(zfs_to_cpu64(uber->ub_version, BIG_ENDIAN))) endian = BIG_ENDIAN; if (endian == UNKNOWN_ENDIAN) { @@ -1787,7 +1791,7 @@ check_pool_label(struct zfs_data *data) return ZFS_ERR_BAD_FS; } - if (version > SPA_VERSION) { + if (!is_supported_spa_version(version)) { free(nvlist); printf("SPA version too new %llu > %llu\n", (unsigned long long) version, diff --git a/include/zfs/zfs.h b/include/zfs/zfs.h index 17b93c10c81..72d87452ddf 100644 --- a/include/zfs/zfs.h +++ b/include/zfs/zfs.h @@ -15,6 +15,7 @@ * On-disk version number. */ #define SPA_VERSION 28ULL +#define FEATURES_SUPPORTED_SPA_VERSION 5000ULL /* * The following are configuration names used in the nvlist describing a pool's From 1466e065a94b3cd242f945f16c916a7f7da02985 Mon Sep 17 00:00:00 2001 From: WHR Date: Wed, 1 May 2024 00:40:38 +0800 Subject: [PATCH 003/383] zfs: fix function 'zlib_decompress' pointlessly calling itself In order to prevent crashing due to infinite recursion and actually decompress the requested data, call the zlib function 'uncompress' instead. Signed-off-by: WHR --- fs/zfs/zfs.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/fs/zfs/zfs.c b/fs/zfs/zfs.c index 06221e68b35..9906d553fa6 100644 --- a/fs/zfs/zfs.c +++ b/fs/zfs/zfs.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "zfs_common.h" #include "div64.h" @@ -182,7 +183,8 @@ static int zlib_decompress(void *s, void *d, uint32_t slen, uint32_t dlen) { - if (zlib_decompress(s, d, slen, dlen) < 0) + uLongf z_dest_len = dlen; + if (uncompress(d, &z_dest_len, s, slen) != Z_OK) return ZFS_ERR_BAD_FS; return ZFS_ERR_NONE; } From e0112bc508b142786b919eb48c2dc8eca9f0361b Mon Sep 17 00:00:00 2001 From: WHR Date: Wed, 1 May 2024 00:55:10 +0800 Subject: [PATCH 004/383] sandbox: make function 'do_undefined' properly compiles for PowerPC The 2 bytes 0xffff is too short for being a PowerPC instruction, resulting in an error similar to: /tmp/ccW8yjie.s: Assembler messages: /tmp/ccW8yjie.s: Error: unaligned opcodes detected in executable segment /tmp/ccW8yjie.s:223: Error: instruction address is not a multiple of 4 make[2]: *** [/tmp/ccyF4HIC.mk:17: /tmp/ccCKUFuF.ltrans5.ltrans.o] Error 1 Signed-off-by: WHR --- cmd/sandbox/exception.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/cmd/sandbox/exception.c b/cmd/sandbox/exception.c index cfa153da260..f9c847d8ff2 100644 --- a/cmd/sandbox/exception.c +++ b/cmd/sandbox/exception.c @@ -19,7 +19,11 @@ static int do_sigsegv(struct cmd_tbl *cmdtp, int flag, int argc, static int do_undefined(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { +#ifdef __powerpc__ + asm volatile (".long 0xffffffff\n"); +#else asm volatile (".word 0xffff\n"); +#endif return CMD_RET_FAILURE; } From b18a3c183d20812933d192d4b0d622b11ef2bf29 Mon Sep 17 00:00:00 2001 From: Peter Hoyes Date: Wed, 1 May 2024 09:16:32 +0100 Subject: [PATCH 005/383] arm: Move sev() and wfe() definitions to common Arm header file The sev() and wfe() asm macros are currently defined only for mach-exynos. As these are common Arm instructions, move them to the common asm/system.h header file, for both Armv7 and Armv8, so they can be used by other machines. wfe may theoretically trigger a context switch if an interrupt occurs so add a memory barrier to this call. Signed-off-by: Peter Hoyes Reviewed-by: Andre Przywara --- arch/arm/include/asm/system.h | 9 +++++++++ arch/arm/mach-exynos/include/mach/system.h | 19 ------------------- 2 files changed, 9 insertions(+), 19 deletions(-) diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 43f7503571d..51123c29684 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -154,6 +154,13 @@ enum dcache_option { "wfi" : : : "memory"); \ }) +#define wfe() \ + ({asm volatile( \ + "wfe" : : : "memory"); \ + }) + +#define sev() asm volatile("sev") + static inline unsigned int current_el(void) { unsigned long el; @@ -369,6 +376,8 @@ void switch_to_hypervisor_ret(void); #ifdef __ARM_ARCH_7A__ #define wfi() __asm__ __volatile__ ("wfi" : : : "memory") +#define wfe() __asm__ __volatile__ ("wfe" : : : "memory") +#define sev() __asm__ __volatile__ ("sev") #else #define wfi() #endif diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h index 5d0bebac573..0aed4c3e2bf 100644 --- a/arch/arm/mach-exynos/include/mach/system.h +++ b/arch/arm/mach-exynos/include/mach/system.h @@ -36,25 +36,6 @@ struct exynos5_sysreg { #define USB20_PHY_CFG_HOST_LINK_EN (1 << 0) -/* - * This instruction causes an event to be signaled to all cores - * within a multiprocessor system. If SEV is implemented, - * WFE must also be implemented. - */ -#define sev() __asm__ __volatile__ ("sev\n\t" : : ); -/* - * If the Event Register is not set, WFE suspends execution until - * one of the following events occurs: - * - an IRQ interrupt, unless masked by the CPSR I-bit - * - an FIQ interrupt, unless masked by the CPSR F-bit - * - an Imprecise Data abort, unless masked by the CPSR A-bit - * - a Debug Entry request, if Debug is enabled - * - an Event signaled by another processor using the SEV instruction. - * If the Event Register is set, WFE clears it and returns immediately. - * If WFE is implemented, SEV must also be implemented. - */ -#define wfe() __asm__ __volatile__ ("wfe\n\t" : : ); - /* Move 0xd3 value to CPSR register to enable SVC mode */ #define svc32_mode_en() __asm__ __volatile__ \ ("@ I&F disable, Mode: 0x13 - SVC\n\t" \ From ebc84d7b60c1ed3398e9f600fe3dc8406500bd35 Mon Sep 17 00:00:00 2001 From: Peter Hoyes Date: Wed, 1 May 2024 09:16:33 +0100 Subject: [PATCH 006/383] armv8: generic_timer: Use event stream for udelay Polling cntpct_el0 in a tight loop for delays is inefficient. This is particularly apparent on Arm FVPs, which do not simulate real time, meaning that a 1s sleep can take a couple of orders of magnitude longer to execute in wall time. If running at EL2 or above (where CNTHCTL_EL2 is available), enable the cntpct_el0 event stream temporarily and use wfe to implement the delay more efficiently. The event period is chosen as a trade-off between efficiency and the fact that Arm FVPs do not typically simulate real time. This is only implemented for Armv8 boards, where an architectural timer exists, and only enabled by default for the ARCH_VEXPRESS64 board family. Signed-off-by: Peter Hoyes Reviewed-by: Andre Przywara --- arch/arm/cpu/armv8/Kconfig | 8 ++++++++ arch/arm/cpu/armv8/generic_timer.c | 27 +++++++++++++++++++++++++++ arch/arm/include/asm/system.h | 6 ++++-- 3 files changed, 39 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 9f0fb369f77..199335cd604 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -191,6 +191,14 @@ config ARMV8_EA_EL3_FIRST Exception handling at all exception levels for External Abort and SError interrupt exception are taken in EL3. +config ARMV8_UDELAY_EVENT_STREAM + bool "Use the event stream for udelay" + default y if ARCH_VEXPRESS64 + help + Use the event stream provided by the AArch64 architectural timer for + delays. This is more efficient than the default polling + implementation. + menuconfig ARMV8_CRYPTO bool "ARM64 Accelerated Cryptographic Algorithms" diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c index e4aa5a47455..1de7ec596fc 100644 --- a/arch/arm/cpu/armv8/generic_timer.c +++ b/arch/arm/cpu/armv8/generic_timer.c @@ -114,3 +114,30 @@ ulong timer_get_boot_us(void) return val / get_tbclk(); } + +#if CONFIG_IS_ENABLED(ARMV8_UDELAY_EVENT_STREAM) +void __udelay(unsigned long usec) +{ + u64 target = get_ticks() + usec_to_tick(usec); + + /* At EL2 or above, use the event stream to avoid polling CNTPCT_EL0 so often */ + if (current_el() >= 2) { + u32 cnthctl_val; + const u8 event_period = 0x7; + + asm volatile("mrs %0, cnthctl_el2" : "=r" (cnthctl_val)); + asm volatile("msr cnthctl_el2, %0" : : "r" + (cnthctl_val | CNTHCTL_EL2_EVNT_EN | CNTHCTL_EL2_EVNT_I(event_period))); + + while (get_ticks() + (1ULL << event_period) <= target) + wfe(); + + /* Reset the event stream */ + asm volatile("msr cnthctl_el2, %0" : : "r" (cnthctl_val)); + } + + /* Fall back to polling CNTPCT_EL0 */ + while (get_ticks() <= target) + ; +} +#endif diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 51123c29684..7e30cac32a0 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -69,8 +69,10 @@ /* * CNTHCTL_EL2 bits definitions */ -#define CNTHCTL_EL2_EL1PCEN_EN (1 << 1) /* Physical timer regs accessible */ -#define CNTHCTL_EL2_EL1PCTEN_EN (1 << 0) /* Physical counter accessible */ +#define CNTHCTL_EL2_EVNT_EN BIT(2) /* Enable the event stream */ +#define CNTHCTL_EL2_EVNT_I(val) ((val) << 4) /* Event stream trigger bits */ +#define CNTHCTL_EL2_EL1PCEN_EN (1 << 1) /* Physical timer regs accessible */ +#define CNTHCTL_EL2_EL1PCTEN_EN (1 << 0) /* Physical counter accessible */ /* * HCR_EL2 bits definitions From 4f652182a0777085eb9022648c33c5fd8356a0de Mon Sep 17 00:00:00 2001 From: Fiona Klute Date: Wed, 1 May 2024 10:54:09 +0200 Subject: [PATCH 007/383] Init virtio before loading ENV from EXT4 or FAT Specifying a file in an EXT4 or FAT partition on a virtio device as environment location failed because virtio hadn't been initialized by the time the environment was loaded. This patch mirrors commit 54ee5ae84191 ("Add SCSI scan for ENV in EXT4 or FAT") in issue and fix, just for a different kind of block device. The additional include in include/virtio.h is needed so all functions called there are defined, the alternative would have been to include dm/device.h separately in the env/ sources. Checkpatch suggests using "if (IS_ENABLED(CONFIG...))" instead of "#if defined(CONFIG_...)", I'm sticking to the style of the existing code here. Signed-off-by: Fiona Klute CC: Joe Hershberger CC: Bin Meng CC: Rogier Stam --- env/ext4.c | 5 +++++ env/fat.c | 5 +++++ include/virtio.h | 1 + 3 files changed, 11 insertions(+) diff --git a/env/ext4.c b/env/ext4.c index eb16568bd46..d92c844ea6c 100644 --- a/env/ext4.c +++ b/env/ext4.c @@ -31,6 +31,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -150,6 +151,10 @@ static int env_ext4_load(void) if (!strcmp(ifname, "scsi")) scsi_scan(true); #endif +#if defined(CONFIG_VIRTIO) + if (!strcmp(ifname, "virtio")) + virtio_init(); +#endif part = blk_get_device_part_str(ifname, dev_and_part, &dev_desc, &info, 1); diff --git a/env/fat.c b/env/fat.c index 2a40f123936..f3f8b7301ee 100644 --- a/env/fat.c +++ b/env/fat.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -133,6 +134,10 @@ static int env_fat_load(void) if (!strcmp(CONFIG_ENV_FAT_INTERFACE, "scsi")) scsi_scan(true); #endif +#if defined(CONFIG_VIRTIO) + if (!strcmp(ifname, "virtio")) + virtio_init(); +#endif #endif part = blk_get_device_part_str(ifname, dev_and_part, &dev_desc, &info, 1); diff --git a/include/virtio.h b/include/virtio.h index 1ab0ec5f39f..17f894a79e3 100644 --- a/include/virtio.h +++ b/include/virtio.h @@ -21,6 +21,7 @@ #define __VIRTIO_H__ #include +#include #include #include #include From 830d83ec385ddf9eeb541027ef09453657deed56 Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Fri, 3 May 2024 17:18:36 +0200 Subject: [PATCH 008/383] scripts: gen_compile_commands: fix invalid escape sequence warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since Python 3.12 unrecognised escape sequences trigger a SyntaxWarning. Convert the '\#' string to a raw string so the backslash is correctly used as a literal. Ported from Linux commit dae4a0171e25 ("gen_compile_commands: fix invalid escape sequence warning"). This updates the script to be in-line with Linux 6.9-rc6. Signed-off-by: Caleb Connolly Reviewed-by: João Marcos Costa --- scripts/gen_compile_commands.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/gen_compile_commands.py b/scripts/gen_compile_commands.py index fec513e5547..e746adddd92 100755 --- a/scripts/gen_compile_commands.py +++ b/scripts/gen_compile_commands.py @@ -172,7 +172,7 @@ def process_line(root_directory, command_prefix, file_path): # escape the pound sign '#', either as '\#' or '$(pound)' (depending on the # kernel version). The compile_commands.json file is not interepreted # by Make, so this code replaces the escaped version with '#'. - prefix = command_prefix.replace('\#', '#').replace('$(pound)', '#') + prefix = command_prefix.replace(r'\#', '#').replace('$(pound)', '#') # Return the canonical path, eliminating any symbolic links encountered in the path. abs_path = os.path.realpath(os.path.join(root_directory, file_path)) From 42826664e4452304bdadc909d7c5f791d4abc552 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Fri, 10 May 2024 15:21:24 -0500 Subject: [PATCH 009/383] arm: mach-k3: Move code specific to a SoC into that SoC's directory Each SoC now has a directory in mach-k3, let's move the SoC specific files into their respective directories. Signed-off-by: Andrew Davis --- arch/arm/mach-k3/Makefile | 24 ++++++--------------- arch/arm/mach-k3/am62ax/Makefile | 7 ++++++ arch/arm/mach-k3/{ => am62ax}/am62a7_fdt.c | 3 ++- arch/arm/mach-k3/{ => am62ax}/am62a7_init.c | 5 +++-- arch/arm/mach-k3/am62px/Makefile | 6 ++++++ arch/arm/mach-k3/{ => am62px}/am62p5_init.c | 5 +++-- arch/arm/mach-k3/am62x/Makefile | 3 +++ arch/arm/mach-k3/{ => am62x}/am625_fdt.c | 3 ++- arch/arm/mach-k3/{ => am62x}/am625_init.c | 5 +++-- arch/arm/mach-k3/am64x/Makefile | 2 ++ arch/arm/mach-k3/{ => am64x}/am642_init.c | 5 +++-- arch/arm/mach-k3/am65x/Makefile | 7 ++++++ arch/arm/mach-k3/{ => am65x}/am654_fdt.c | 3 ++- arch/arm/mach-k3/{ => am65x}/am654_init.c | 5 +++-- arch/arm/mach-k3/j721e/Makefile | 7 ++++++ arch/arm/mach-k3/{ => j721e}/j721e_fdt.c | 3 ++- arch/arm/mach-k3/{ => j721e}/j721e_init.c | 5 +++-- arch/arm/mach-k3/j721s2/Makefile | 7 ++++++ arch/arm/mach-k3/{ => j721s2}/j721s2_fdt.c | 3 ++- arch/arm/mach-k3/{ => j721s2}/j721s2_init.c | 5 +++-- arch/arm/mach-k3/j784s4/Makefile | 7 ++++++ arch/arm/mach-k3/{ => j784s4}/j784s4_fdt.c | 3 ++- arch/arm/mach-k3/{ => j784s4}/j784s4_init.c | 5 +++-- 23 files changed, 88 insertions(+), 40 deletions(-) create mode 100644 arch/arm/mach-k3/am62ax/Makefile rename arch/arm/mach-k3/{ => am62ax}/am62a7_fdt.c (93%) rename arch/arm/mach-k3/{ => am62ax}/am62a7_init.c (99%) create mode 100644 arch/arm/mach-k3/am62px/Makefile rename arch/arm/mach-k3/{ => am62px}/am62p5_init.c (99%) rename arch/arm/mach-k3/{ => am62x}/am625_fdt.c (98%) rename arch/arm/mach-k3/{ => am62x}/am625_init.c (99%) rename arch/arm/mach-k3/{ => am64x}/am642_init.c (99%) create mode 100644 arch/arm/mach-k3/am65x/Makefile rename arch/arm/mach-k3/{ => am65x}/am654_fdt.c (88%) rename arch/arm/mach-k3/{ => am65x}/am654_init.c (99%) create mode 100644 arch/arm/mach-k3/j721e/Makefile rename arch/arm/mach-k3/{ => j721e}/j721e_fdt.c (88%) rename arch/arm/mach-k3/{ => j721e}/j721e_init.c (99%) create mode 100644 arch/arm/mach-k3/j721s2/Makefile rename arch/arm/mach-k3/{ => j721s2}/j721s2_fdt.c (88%) rename arch/arm/mach-k3/{ => j721s2}/j721s2_init.c (99%) create mode 100644 arch/arm/mach-k3/j784s4/Makefile rename arch/arm/mach-k3/{ => j784s4}/j784s4_fdt.c (92%) rename arch/arm/mach-k3/{ => j784s4}/j784s4_init.c (99%) diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile index 3101f57d324..2b3ebd5c535 100644 --- a/arch/arm/mach-k3/Makefile +++ b/arch/arm/mach-k3/Makefile @@ -6,24 +6,12 @@ obj-$(CONFIG_ARM64) += arm64/ obj-$(CONFIG_CPU_V7R) += r5/ obj-$(CONFIG_OF_LIBFDT) += common_fdt.o -ifeq ($(CONFIG_OF_LIBFDT)$(CONFIG_OF_SYSTEM_SETUP),yy) -obj-$(CONFIG_SOC_K3_AM654) += am654_fdt.o -obj-$(CONFIG_SOC_K3_J721E) += j721e_fdt.o -obj-$(CONFIG_SOC_K3_J721S2) += j721s2_fdt.o -obj-$(CONFIG_SOC_K3_AM625) += am625_fdt.o -obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_fdt.o -obj-$(CONFIG_SOC_K3_J784S4) += j784s4_fdt.o -endif -ifeq ($(CONFIG_SPL_BUILD),y) -obj-$(CONFIG_SOC_K3_AM654) += am654_init.o -obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o -obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o -obj-$(CONFIG_SOC_K3_AM642) += am642_init.o -obj-$(CONFIG_SOC_K3_AM625) += am625_init.o -obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_init.o -obj-$(CONFIG_SOC_K3_J784S4) += j784s4_init.o -obj-$(CONFIG_SOC_K3_AM62P5) += am62p5_init.o -endif obj-y += common.o security.o +obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/ +obj-$(CONFIG_SOC_K3_AM62P5) += am62px/ obj-$(CONFIG_SOC_K3_AM625) += am62x/ obj-$(CONFIG_SOC_K3_AM642) += am64x/ +obj-$(CONFIG_SOC_K3_AM654) += am65x/ +obj-$(CONFIG_SOC_K3_J721E) += j721e/ +obj-$(CONFIG_SOC_K3_J721S2) += j721s2/ +obj-$(CONFIG_SOC_K3_J784S4) += j784s4/ diff --git a/arch/arm/mach-k3/am62ax/Makefile b/arch/arm/mach-k3/am62ax/Makefile new file mode 100644 index 00000000000..1717ca343d6 --- /dev/null +++ b/arch/arm/mach-k3/am62ax/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis + +obj-$(CONFIG_OF_SYSTEM_SETUP) += am62a7_fdt.o +obj-$(CONFIG_SPL_BUILD) += am62a7_init.o diff --git a/arch/arm/mach-k3/am62a7_fdt.c b/arch/arm/mach-k3/am62ax/am62a7_fdt.c similarity index 93% rename from arch/arm/mach-k3/am62a7_fdt.c rename to arch/arm/mach-k3/am62ax/am62a7_fdt.c index d67f012a5dc..7f764ab36b5 100644 --- a/arch/arm/mach-k3/am62a7_fdt.c +++ b/arch/arm/mach-k3/am62ax/am62a7_fdt.c @@ -4,9 +4,10 @@ */ #include -#include "common_fdt.h" #include +#include "../common_fdt.h" + int ft_system_setup(void *blob, struct bd_info *bd) { fdt_fixup_reserved(blob, "tfa", CONFIG_K3_ATF_LOAD_ADDR, 0x80000); diff --git a/arch/arm/mach-k3/am62a7_init.c b/arch/arm/mach-k3/am62ax/am62a7_init.c similarity index 99% rename from arch/arm/mach-k3/am62a7_init.c rename to arch/arm/mach-k3/am62ax/am62a7_init.c index 658828cf75f..0f62f39075b 100644 --- a/arch/arm/mach-k3/am62a7_init.c +++ b/arch/arm/mach-k3/am62ax/am62a7_init.c @@ -8,12 +8,13 @@ #include #include #include -#include "sysfw-loader.h" -#include "common.h" #include #include #include +#include "../sysfw-loader.h" +#include "../common.h" + struct fwl_data cbass_main_fwls[] = { { "FSS_DAT_REG3", 7, 8 }, }; diff --git a/arch/arm/mach-k3/am62px/Makefile b/arch/arm/mach-k3/am62px/Makefile new file mode 100644 index 00000000000..5902862b29c --- /dev/null +++ b/arch/arm/mach-k3/am62px/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis + +obj-$(CONFIG_SPL_BUILD) += am62p5_init.o diff --git a/arch/arm/mach-k3/am62p5_init.c b/arch/arm/mach-k3/am62px/am62p5_init.c similarity index 99% rename from arch/arm/mach-k3/am62p5_init.c rename to arch/arm/mach-k3/am62px/am62p5_init.c index aab99aa0c95..34ed01cd78c 100644 --- a/arch/arm/mach-k3/am62p5_init.c +++ b/arch/arm/mach-k3/am62px/am62p5_init.c @@ -8,12 +8,13 @@ #include #include #include -#include "sysfw-loader.h" -#include "common.h" #include #include #include +#include "../sysfw-loader.h" +#include "../common.h" + struct fwl_data cbass_main_fwls[] = { { "FSS_DAT_REG3", 7, 8 }, }; diff --git a/arch/arm/mach-k3/am62x/Makefile b/arch/arm/mach-k3/am62x/Makefile index acf09c3426c..8494cdda482 100644 --- a/arch/arm/mach-k3/am62x/Makefile +++ b/arch/arm/mach-k3/am62x/Makefile @@ -1,2 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ + +obj-$(CONFIG_OF_SYSTEM_SETUP) += am625_fdt.o +obj-$(CONFIG_SPL_BUILD) += am625_init.o obj-y += boot.o diff --git a/arch/arm/mach-k3/am625_fdt.c b/arch/arm/mach-k3/am62x/am625_fdt.c similarity index 98% rename from arch/arm/mach-k3/am625_fdt.c rename to arch/arm/mach-k3/am62x/am625_fdt.c index c56adef13bd..8fe200a4231 100644 --- a/arch/arm/mach-k3/am625_fdt.c +++ b/arch/arm/mach-k3/am62x/am625_fdt.c @@ -4,9 +4,10 @@ */ #include -#include "common_fdt.h" #include +#include "../common_fdt.h" + static void fdt_fixup_cores_nodes_am625(void *blob, int core_nr) { char node_path[32]; diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am62x/am625_init.c similarity index 99% rename from arch/arm/mach-k3/am625_init.c rename to arch/arm/mach-k3/am62x/am625_init.c index 668f9a51ef4..ed8d24e0433 100644 --- a/arch/arm/mach-k3/am625_init.c +++ b/arch/arm/mach-k3/am62x/am625_init.c @@ -9,13 +9,14 @@ #include #include #include -#include "sysfw-loader.h" -#include "common.h" #include #include #include #include +#include "../sysfw-loader.h" +#include "../common.h" + #define RTC_BASE_ADDRESS 0x2b1f0000 #define REG_K3RTC_S_CNT_LSW (RTC_BASE_ADDRESS + 0x18) #define REG_K3RTC_KICK0 (RTC_BASE_ADDRESS + 0x70) diff --git a/arch/arm/mach-k3/am64x/Makefile b/arch/arm/mach-k3/am64x/Makefile index acf09c3426c..d0b286276c8 100644 --- a/arch/arm/mach-k3/am64x/Makefile +++ b/arch/arm/mach-k3/am64x/Makefile @@ -1,2 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ + +obj-$(CONFIG_SPL_BUILD) += am642_init.o obj-y += boot.o diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am64x/am642_init.c similarity index 99% rename from arch/arm/mach-k3/am642_init.c rename to arch/arm/mach-k3/am64x/am642_init.c index f341b4f367c..41812b7dbf7 100644 --- a/arch/arm/mach-k3/am642_init.c +++ b/arch/arm/mach-k3/am64x/am642_init.c @@ -11,8 +11,6 @@ #include #include #include -#include "sysfw-loader.h" -#include "common.h" #include #include #include @@ -21,6 +19,9 @@ #include #include +#include "../sysfw-loader.h" +#include "../common.h" + #define CTRLMMR_MCU_RST_CTRL 0x04518170 #define CTRLMMR_MCU_RST_SRC (MCU_CTRL_MMR0_BASE + 0x18178) diff --git a/arch/arm/mach-k3/am65x/Makefile b/arch/arm/mach-k3/am65x/Makefile new file mode 100644 index 00000000000..20d5f1d3bf1 --- /dev/null +++ b/arch/arm/mach-k3/am65x/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis + +obj-$(CONFIG_OF_SYSTEM_SETUP) += am654_fdt.o +obj-$(CONFIG_SPL_BUILD) += am654_init.o diff --git a/arch/arm/mach-k3/am654_fdt.c b/arch/arm/mach-k3/am65x/am654_fdt.c similarity index 88% rename from arch/arm/mach-k3/am654_fdt.c rename to arch/arm/mach-k3/am65x/am654_fdt.c index 652fe8d32bb..bcb15208be9 100644 --- a/arch/arm/mach-k3/am654_fdt.c +++ b/arch/arm/mach-k3/am65x/am654_fdt.c @@ -3,9 +3,10 @@ * Copyright 2023 Toradex - https://www.toradex.com/ */ -#include "common_fdt.h" #include +#include "../common_fdt.h" + int ft_system_setup(void *blob, struct bd_info *bd) { return fdt_fixup_msmc_ram_k3(blob); diff --git a/arch/arm/mach-k3/am654_init.c b/arch/arm/mach-k3/am65x/am654_init.c similarity index 99% rename from arch/arm/mach-k3/am654_init.c rename to arch/arm/mach-k3/am65x/am654_init.c index 7c2a143ed1b..a4f038029d7 100644 --- a/arch/arm/mach-k3/am654_init.c +++ b/arch/arm/mach-k3/am65x/am654_init.c @@ -12,8 +12,6 @@ #include #include #include -#include "sysfw-loader.h" -#include "common.h" #include #include #include @@ -22,6 +20,9 @@ #include #include +#include "../sysfw-loader.h" +#include "../common.h" + DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_K3_LOAD_SYSFW diff --git a/arch/arm/mach-k3/j721e/Makefile b/arch/arm/mach-k3/j721e/Makefile new file mode 100644 index 00000000000..982b88db57d --- /dev/null +++ b/arch/arm/mach-k3/j721e/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis + +obj-$(CONFIG_OF_SYSTEM_SETUP) += j721e_fdt.o +obj-$(CONFIG_SPL_BUILD) += j721e_init.o diff --git a/arch/arm/mach-k3/j721e_fdt.c b/arch/arm/mach-k3/j721e/j721e_fdt.c similarity index 88% rename from arch/arm/mach-k3/j721e_fdt.c rename to arch/arm/mach-k3/j721e/j721e_fdt.c index 652fe8d32bb..bcb15208be9 100644 --- a/arch/arm/mach-k3/j721e_fdt.c +++ b/arch/arm/mach-k3/j721e/j721e_fdt.c @@ -3,9 +3,10 @@ * Copyright 2023 Toradex - https://www.toradex.com/ */ -#include "common_fdt.h" #include +#include "../common_fdt.h" + int ft_system_setup(void *blob, struct bd_info *bd) { return fdt_fixup_msmc_ram_k3(blob); diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e/j721e_init.c similarity index 99% rename from arch/arm/mach-k3/j721e_init.c rename to arch/arm/mach-k3/j721e/j721e_init.c index 7ee9b75de4d..c2024f2500d 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e/j721e_init.c @@ -11,8 +11,6 @@ #include #include #include -#include "sysfw-loader.h" -#include "common.h" #include #include #include @@ -22,6 +20,9 @@ #include #include +#include "../sysfw-loader.h" +#include "../common.h" + #ifdef CONFIG_K3_LOAD_SYSFW struct fwl_data cbass_hc_cfg0_fwls[] = { #if defined(CONFIG_TARGET_J721E_R5_EVM) diff --git a/arch/arm/mach-k3/j721s2/Makefile b/arch/arm/mach-k3/j721s2/Makefile new file mode 100644 index 00000000000..ceef68297c9 --- /dev/null +++ b/arch/arm/mach-k3/j721s2/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis + +obj-$(CONFIG_OF_SYSTEM_SETUP) += j721s2_fdt.o +obj-$(CONFIG_SPL_BUILD) += j721s2_init.o diff --git a/arch/arm/mach-k3/j721s2_fdt.c b/arch/arm/mach-k3/j721s2/j721s2_fdt.c similarity index 88% rename from arch/arm/mach-k3/j721s2_fdt.c rename to arch/arm/mach-k3/j721s2/j721s2_fdt.c index 652fe8d32bb..bcb15208be9 100644 --- a/arch/arm/mach-k3/j721s2_fdt.c +++ b/arch/arm/mach-k3/j721s2/j721s2_fdt.c @@ -3,9 +3,10 @@ * Copyright 2023 Toradex - https://www.toradex.com/ */ -#include "common_fdt.h" #include +#include "../common_fdt.h" + int ft_system_setup(void *blob, struct bd_info *bd) { return fdt_fixup_msmc_ram_k3(blob); diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2/j721s2_init.c similarity index 99% rename from arch/arm/mach-k3/j721s2_init.c rename to arch/arm/mach-k3/j721s2/j721s2_init.c index 3374889558a..fe9766e9b4b 100644 --- a/arch/arm/mach-k3/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2/j721s2_init.c @@ -11,8 +11,6 @@ #include #include #include -#include "sysfw-loader.h" -#include "common.h" #include #include #include @@ -21,6 +19,9 @@ #include #include +#include "../sysfw-loader.h" +#include "../common.h" + struct fwl_data cbass_hc_cfg0_fwls[] = { { "PCIE0_CFG", 2577, 7 }, { "EMMC8SS0_CFG", 2579, 4 }, diff --git a/arch/arm/mach-k3/j784s4/Makefile b/arch/arm/mach-k3/j784s4/Makefile new file mode 100644 index 00000000000..6d1841e3f9e --- /dev/null +++ b/arch/arm/mach-k3/j784s4/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis + +obj-$(CONFIG_OF_SYSTEM_SETUP) += j784s4_fdt.o +obj-$(CONFIG_SPL_BUILD) += j784s4_init.o diff --git a/arch/arm/mach-k3/j784s4_fdt.c b/arch/arm/mach-k3/j784s4/j784s4_fdt.c similarity index 92% rename from arch/arm/mach-k3/j784s4_fdt.c rename to arch/arm/mach-k3/j784s4/j784s4_fdt.c index d05ed8b9911..e1275097051 100644 --- a/arch/arm/mach-k3/j784s4_fdt.c +++ b/arch/arm/mach-k3/j784s4/j784s4_fdt.c @@ -6,9 +6,10 @@ * Apurva Nandan */ -#include "common_fdt.h" #include +#include "../common_fdt.h" + int ft_system_setup(void *blob, struct bd_info *bd) { return fdt_fixup_msmc_ram_k3(blob); diff --git a/arch/arm/mach-k3/j784s4_init.c b/arch/arm/mach-k3/j784s4/j784s4_init.c similarity index 99% rename from arch/arm/mach-k3/j784s4_init.c rename to arch/arm/mach-k3/j784s4/j784s4_init.c index ae4420362d0..1ce13e0f494 100644 --- a/arch/arm/mach-k3/j784s4_init.c +++ b/arch/arm/mach-k3/j784s4/j784s4_init.c @@ -11,8 +11,6 @@ #include #include #include -#include "sysfw-loader.h" -#include "common.h" #include #include #include @@ -20,6 +18,9 @@ #include #include +#include "../sysfw-loader.h" +#include "../common.h" + #define J784S4_MAX_DDR_CONTROLLERS 4 struct fwl_data infra_cbass0_fwls[] = { From 92114d7c0a19a9719cfd821cf9e44a7fc090b2c1 Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Mon, 6 May 2024 15:38:41 +0100 Subject: [PATCH 010/383] usb: dwc3: Add dwc3 glue driver for am62 Add glue code for TI AM62 to the dwc3 driver; Most code adopted from TI vendor u-boot code. Signed-off-by: Sjoerd Simons Tested-by: Alexander Sverdlin Reviewed-by: Mattijs Korpershoek Tested-by: Mattijs Korpershoek # on beagle play --- drivers/usb/dwc3/Kconfig | 14 ++++ drivers/usb/dwc3/Makefile | 1 + drivers/usb/dwc3/dwc3-am62.c | 125 +++++++++++++++++++++++++++++++++++ 3 files changed, 140 insertions(+) create mode 100644 drivers/usb/dwc3/dwc3-am62.c diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index c0c8c16fd9c..0100723a68b 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -37,6 +37,20 @@ config SPL_USB_DWC3_GENERIC Select this for Xilinx ZynqMP and similar Platforms. This wrapper supports Host and Peripheral operation modes. +config SPL_USB_DWC3_AM62 + bool "TI AM62 USB wrapper" + depends on SPL_DM_USB && SPL_USB_DWC3_GENERIC && SPL_SYSCON + help + Select this for TI AM62 Platforms. + This wrapper supports Host and Peripheral operation modes. + +config USB_DWC3_AM62 + bool "TI AM62 USB wrapper" + depends on DM_USB && USB_DWC3_GENERIC && SYSCON + help + Select this for TI AM62 Platforms. + This wrapper supports Host and Peripheral operation modes. + config USB_DWC3_MESON_G12A bool "Amlogic Meson G12A USB wrapper" depends on DM_USB && USB_DWC3 && ARCH_MESON diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index 97b4f7191ca..a46b6824ab7 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -6,6 +6,7 @@ dwc3-y := core.o obj-$(CONFIG_USB_DWC3_GADGET) += gadget.o ep0.o +obj-$(CONFIG_$(SPL_)USB_DWC3_AM62) += dwc3-am62.o obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o obj-$(CONFIG_USB_DWC3_MESON_G12A) += dwc3-meson-g12a.o obj-$(CONFIG_USB_DWC3_MESON_GXL) += dwc3-meson-gxl.o diff --git a/drivers/usb/dwc3/dwc3-am62.c b/drivers/usb/dwc3/dwc3-am62.c new file mode 100644 index 00000000000..99519602eb2 --- /dev/null +++ b/drivers/usb/dwc3/dwc3-am62.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * TI AM62 specific glue layer for DWC3 + */ + +#include +#include +#include +#include +#include + +#include "dwc3-generic.h" + +#define USBSS_MODE_CONTROL 0x1c +#define USBSS_PHY_CONFIG 0x8 +#define USBSS_PHY_VBUS_SEL_MASK GENMASK(2, 1) +#define USBSS_PHY_VBUS_SEL_SHIFT 1 +#define USBSS_MODE_VALID BIT(0) +#define PHY_PLL_REFCLK_MASK GENMASK(3, 0) +static const int dwc3_ti_am62_rate_table[] = { /* in KHZ */ + 9600, + 10000, + 12000, + 19200, + 20000, + 24000, + 25000, + 26000, + 38400, + 40000, + 58000, + 50000, + 52000, +}; + +static void dwc3_ti_am62_glue_configure(struct udevice *dev, int index, + enum usb_dr_mode mode) +{ + struct clk usb2_refclk; + int rate_code, i, ret; + unsigned long rate; + u32 reg; + void *usbss; + bool vbus_divider; + struct regmap *syscon; + struct ofnode_phandle_args args; + + usbss = dev_remap_addr_index(dev, 0); + if (IS_ERR(usbss)) { + dev_err(dev, "can't map IOMEM resource\n"); + return; + } + + ret = clk_get_by_name(dev, "ref", &usb2_refclk); + if (ret) { + dev_err(dev, "can't get usb2_refclk\n"); + return; + } + + /* Calculate the rate code */ + rate = clk_get_rate(&usb2_refclk); + rate /= 1000; /* To KHz */ + for (i = 0; i < ARRAY_SIZE(dwc3_ti_am62_rate_table); i++) { + if (dwc3_ti_am62_rate_table[i] == rate) + break; + } + + if (i == ARRAY_SIZE(dwc3_ti_am62_rate_table)) { + dev_err(dev, "unsupported usb2_refclk rate: %lu KHz\n", rate); + return; + } + + rate_code = i; + + /* Read the syscon property */ + syscon = syscon_regmap_lookup_by_phandle(dev, "ti,syscon-phy-pll-refclk"); + if (IS_ERR(syscon)) { + dev_err(dev, "unable to get ti,syscon-phy-pll-refclk regmap\n"); + return; + } + + ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "ti,syscon-phy-pll-refclk", NULL, 1, + 0, &args); + if (ret) + return; + + /* Program PHY PLL refclk by reading syscon property */ + ret = regmap_update_bits(syscon, args.args[0], PHY_PLL_REFCLK_MASK, rate_code); + if (ret) { + dev_err(dev, "failed to set phy pll reference clock rate\n"); + return; + } + + /* VBUS divider select */ + reg = readl(usbss + USBSS_PHY_CONFIG); + vbus_divider = dev_read_bool(dev, "ti,vbus-divider"); + if (vbus_divider) + reg |= 1 << USBSS_PHY_VBUS_SEL_SHIFT; + + writel(reg, usbss + USBSS_PHY_CONFIG); + + /* Set mode valid */ + reg = readl(usbss + USBSS_MODE_CONTROL); + reg |= USBSS_MODE_VALID; + writel(reg, usbss + USBSS_MODE_CONTROL); +} + +struct dwc3_glue_ops ti_am62_ops = { + .glue_configure = dwc3_ti_am62_glue_configure, +}; + +static const struct udevice_id dwc3_am62_match[] = { + { .compatible = "ti,am62-usb", .data = (ulong)&ti_am62_ops }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(dwc3_am62_wrapper) = { + .name = "dwc3-am62", + .id = UCLASS_SIMPLE_BUS, + .of_match = dwc3_am62_match, + .bind = dwc3_glue_bind, + .probe = dwc3_glue_probe, + .remove = dwc3_glue_remove, + .plat_auto = sizeof(struct dwc3_glue_data), +}; From 6c33a83e80e443a615eebb1bd9d49781fdcd23e6 Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Mon, 6 May 2024 15:38:42 +0100 Subject: [PATCH 011/383] board: ti: am62x: am62x: include env for DFU Include standard TI K3 dfu environment Signed-off-by: Sjoerd Simons Reviewed-by: Alexander Sverdlin Reviewed-by: Mattijs Korpershoek Tested-by: Mattijs Korpershoek # on beagle play --- board/ti/am62x/am62x.env | 1 + 1 file changed, 1 insertion(+) diff --git a/board/ti/am62x/am62x.env b/board/ti/am62x/am62x.env index 9cb186c2a03..09b9b16a3e5 100644 --- a/board/ti/am62x/am62x.env +++ b/board/ti/am62x/am62x.env @@ -1,5 +1,6 @@ #include #include +#include name_kern=Image console=ttyS2,115200n8 From 6165b923e89ce50b1f3566057d98bc556f39c807 Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Mon, 6 May 2024 15:38:43 +0100 Subject: [PATCH 012/383] arm: dts: k3-am625-sk: Enable usb port in u-boot Enable usb0 in all boot phases for use with DFU Signed-off-by: Sjoerd Simons Reviewed-by: Alexander Sverdlin Signed-off-by: Martyn Welch Reviewed-by: Mattijs Korpershoek --- arch/arm/dts/k3-am625-sk-u-boot.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/dts/k3-am625-sk-u-boot.dtsi b/arch/arm/dts/k3-am625-sk-u-boot.dtsi index fa778b0ff4c..1fc0d407cbf 100644 --- a/arch/arm/dts/k3-am625-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-sk-u-boot.dtsi @@ -46,3 +46,12 @@ &cpsw_port2 { status = "disabled"; }; + +&usbss0 { + bootph-all; +}; + +&usb0 { + dr_mode = "peripheral"; + bootph-all; +}; From dfc2dff5a8442aea4923f757bfc118da5dbd9fbe Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Mon, 6 May 2024 15:38:44 +0100 Subject: [PATCH 013/383] configs: am62x_evm_*: Enable USB and DFU support Provide config fragments to enable USB host as well as USB gadget and DFU support for a53 and r5. This relevant fragment is included into the am62x EVM a53 defconfig. For the r5, due to the smaller available size, the config fragment also disables support for persistent storage to free up space for USB support. This fragment needs to be included is DFU booting is desired. The CONFIG_DFU_SF option is placed in the defconfig rather than the fragment as this is known not to be supported on all boards that can support DFU. Signed-off-by: Sjoerd Simons Signed-off-by: Martyn Welch Reviewed-by: Mattijs Korpershoek --- configs/am62x_a53_usbdfu.config | 29 +++++++++++++++++++++++++++++ configs/am62x_evm_a53_defconfig | 3 +++ configs/am62x_r5_usbdfu.config | 28 ++++++++++++++++++++++++++++ 3 files changed, 60 insertions(+) create mode 100644 configs/am62x_a53_usbdfu.config create mode 100644 configs/am62x_r5_usbdfu.config diff --git a/configs/am62x_a53_usbdfu.config b/configs/am62x_a53_usbdfu.config new file mode 100644 index 00000000000..3a19cf23287 --- /dev/null +++ b/configs/am62x_a53_usbdfu.config @@ -0,0 +1,29 @@ +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_DFU=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_AM62=y +CONFIG_USB_DWC3_AM62=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 +CONFIG_USB_GADGET_DOWNLOAD=y diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig index 6c708dcb052..16294a6a794 100644 --- a/configs/am62x_evm_a53_defconfig +++ b/configs/am62x_evm_a53_defconfig @@ -68,6 +68,7 @@ CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_TI_SCI=y +CONFIG_DFU_SF=y CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y @@ -111,3 +112,5 @@ CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 CONFIG_EFI_SET_TIME=y + +#include diff --git a/configs/am62x_r5_usbdfu.config b/configs/am62x_r5_usbdfu.config new file mode 100644 index 00000000000..772bb2ab935 --- /dev/null +++ b/configs/am62x_r5_usbdfu.config @@ -0,0 +1,28 @@ +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000 +CONFIG_MISC=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_AM62=y +CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_DFU=y +# CONFIG_SPL_MMC is not set +# CONFIG_SPL_FS_FAT is not set +# CONFIG_SPL_LIBDISK_SUPPORT is not set +# CONFIG_SPL_SPI is not set +# CONFIG_SPL_SYS_MALLOC is not set +# CONFIG_CMD_GPT is not set +# CONFIG_CMD_MMC is not set +# CONFIG_CMD_FAT is not set +# CONFIG_MMC_SDHCI is not set From b00c2fe70ae50c275c9166fe5b1fee5597e557bb Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Mon, 6 May 2024 15:38:45 +0100 Subject: [PATCH 014/383] beagleplay: Add DFU support DFU mode on a beagleplay can be used via the Type-C connector by holding the USR switch while powering on. Configuration is already provided as fragments for both the A53 and R5 u-boot parts. Include the am62x_a53_usbdfu.config config. The am62x_r5_usbdfu.config fragment needs to be added should DFU boot be required as this will disable booting from persistent storage due to binary size constraints. Signed-off-by: Sjoerd Simons Signed-off-by: Martyn Welch Reviewed-by: Mattijs Korpershoek Tested-by: Mattijs Korpershoek --- arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi | 9 +++++++++ board/beagle/beagleplay/beagleplay.env | 1 + configs/am62x_beagleplay_a53_defconfig | 2 ++ 3 files changed, 12 insertions(+) diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi index fb2032068d1..967a2bdcd1c 100644 --- a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi @@ -54,6 +54,15 @@ >; }; +&usbss0 { + bootph-all; +}; + +&usb0 { + dr_mode = "peripheral"; + bootph-all; +}; + #ifdef CONFIG_TARGET_AM625_A53_BEAGLEPLAY #define SPL_NODTB "spl/u-boot-spl-nodtb.bin" diff --git a/board/beagle/beagleplay/beagleplay.env b/board/beagle/beagleplay/beagleplay.env index bbf6b925d02..8dbfc2f7d24 100644 --- a/board/beagle/beagleplay/beagleplay.env +++ b/board/beagle/beagleplay/beagleplay.env @@ -1,5 +1,6 @@ #include #include +#include name_kern=Image console=ttyS2,115200n8 diff --git a/configs/am62x_beagleplay_a53_defconfig b/configs/am62x_beagleplay_a53_defconfig index 4f1be1df593..ec62670d55d 100644 --- a/configs/am62x_beagleplay_a53_defconfig +++ b/configs/am62x_beagleplay_a53_defconfig @@ -121,3 +121,5 @@ CONFIG_EXT4_WRITE=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 CONFIG_LZO=y CONFIG_EFI_SET_TIME=y + +#include From def64b49374889fc3e22072af7794f4d3c446cf6 Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Mon, 6 May 2024 15:38:46 +0100 Subject: [PATCH 015/383] doc: board: Add document for DFU boot on am62x SoCs Both AM62 SK and beagleplay support DFU boot in a similar way now; Document how to actually run DFU boot for both boards Signed-off-by: Sjoerd Simons Reviewed-by: Mattijs Korpershoek Tested-by: Mattijs Korpershoek # on beagle play Signed-off-by: Martyn Welch --- doc/board/beagle/am62x_beagleplay.rst | 14 +++++++++- doc/board/ti/am62x_sk.rst | 37 +++++++++++++++++++++++++++ 2 files changed, 50 insertions(+), 1 deletion(-) diff --git a/doc/board/beagle/am62x_beagleplay.rst b/doc/board/beagle/am62x_beagleplay.rst index 7784e62b0b7..cdc610264e1 100644 --- a/doc/board/beagle/am62x_beagleplay.rst +++ b/doc/board/beagle/am62x_beagleplay.rst @@ -268,7 +268,19 @@ for details. - USB Device Firmware Upgrade (DFU) mode To switch to SD card boot mode, hold the USR button while powering on -with Type-C power supply, then release when power LED lights up. +with a USB type C power supply, then release when power LED lights up. + +DFU based boot +-------------- + +To boot the board over DFU, ensure there is no SD card inserted with a +bootloader. Hold the USR switch while plugging into the type C to boot into DFU +mode. After power-on the build artifacts needs to be uploaded one by one with a +tool like dfu-util. + +.. include:: ../ti/am62x_sk.rst + :start-after: .. am62x_evm_rst_include_start_dfu_boot + :end-before: .. am62x_evm_rst_include_end_dfu_boot Debugging U-Boot ---------------- diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst index b12dc85f06b..d5f7fe3b036 100644 --- a/doc/board/ti/am62x_sk.rst +++ b/doc/board/ti/am62x_sk.rst @@ -105,6 +105,20 @@ Set the variables corresponding to this platform: * 3.1 R5: +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_build_steps_spl_r5 + :end-before: .. k3_rst_include_end_build_steps_spl_r5 + +* 3.1.1 Alternative build of R5 for DFU boot: + +As the SPL size can get too big when building with support for booting both +from local storage *and* DFU an extra config fragment should be used to enable +DFU support (and disable storage support) + +.. prompt:: bash $ + + export UBOOT_CFG_CORTEXR="${UBOOT_CFG_CORTEXR} am62x_r5_usbdfu.config" + .. include:: ../ti/k3.rst :start-after: .. k3_rst_include_start_build_steps_spl_r5 :end-before: .. k3_rst_include_end_build_steps_spl_r5 @@ -251,6 +265,29 @@ https://www.ti.com/lit/pdf/spruiv7 under the `Boot Mode Pins` section. For SW2 and SW1, the switch state in the "ON" position = 1. +DFU based boot +-------------- + +To boot the board over DFU, set the switches to DFU mode and connect to the +USB type C DRD port on the board. After power-on the build artifacts needs to be +uploaded one by one with a tool like dfu-util. + +.. am62x_evm_rst_include_start_dfu_boot + +The initial ROM will have a DFU alt named `bootloader` for the initial R5 spl +upload. The next stages as exposed by U-Boot have target alts matching the name +of the artifacts, for these a USB reset has to be done after each upload. + +When using dfu-util the following commands can be used to boot to a U-Boot shell: + +.. prompt:: bash $ + + dfu-util -a bootloader -D tiboot3.bin + dfu-util -R -a tispl -D tispl.bin + dfu-util -R -a u-boot.img -D u-boot.img + +.. am62x_evm_rst_include_end_dfu_boot + Debugging U-Boot ---------------- From a5366098b650e5152ba83961faa719e523b09e42 Mon Sep 17 00:00:00 2001 From: Hari Nagalla Date: Thu, 9 May 2024 09:20:34 -0500 Subject: [PATCH 016/383] remoteproc: k3-dsp: Enable C71x support for AM62A AM62A SoC has a single C71x DSP subsystem with analytics engine in main voltage domain. Extend support to AM62A with compatible strings. Signed-off-by: Hari Nagalla Reviewed-by: Devarsh Thakkar --- drivers/remoteproc/ti_k3_dsp_rproc.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/remoteproc/ti_k3_dsp_rproc.c b/drivers/remoteproc/ti_k3_dsp_rproc.c index e790406324a..ed13729c33a 100644 --- a/drivers/remoteproc/ti_k3_dsp_rproc.c +++ b/drivers/remoteproc/ti_k3_dsp_rproc.c @@ -339,7 +339,8 @@ static int k3_dsp_of_get_memories(struct udevice *dev) for (i = 0; i < dsp->num_mems; i++) { /* C71 cores only have a L1P Cache, there are no L1P SRAMs */ if (((device_is_compatible(dev, "ti,j721e-c71-dsp")) || - (device_is_compatible(dev, "ti,j721s2-c71-dsp"))) && + (device_is_compatible(dev, "ti,j721s2-c71-dsp")) || + (device_is_compatible(dev, "ti,am62a-c7xv-dsp"))) && !strcmp(mem_names[i], "l1pram")) { dsp->mem[i].bus_addr = FDT_ADDR_T_NONE; dsp->mem[i].dev_addr = FDT_ADDR_T_NONE; @@ -347,7 +348,14 @@ static int k3_dsp_of_get_memories(struct udevice *dev) dsp->mem[i].size = 0; continue; } - + if (device_is_compatible(dev, "ti,am62a-c7xv-dsp") && + !strcmp(mem_names[i], "l1dram")) { + dsp->mem[i].bus_addr = FDT_ADDR_T_NONE; + dsp->mem[i].dev_addr = FDT_ADDR_T_NONE; + dsp->mem[i].cpu_addr = NULL; + dsp->mem[i].size = 0; + continue; + } dsp->mem[i].bus_addr = dev_read_addr_size_name(dev, mem_names[i], (fdt_addr_t *)&dsp->mem[i].size); if (dsp->mem[i].bus_addr == FDT_ADDR_T_NONE) { @@ -459,6 +467,7 @@ static const struct udevice_id k3_dsp_ids[] = { { .compatible = "ti,j721e-c66-dsp", .data = (ulong)&c66_data, }, { .compatible = "ti,j721e-c71-dsp", .data = (ulong)&c71_data, }, { .compatible = "ti,j721s2-c71-dsp", .data = (ulong)&c71_data, }, + { .compatible = "ti,am62a-c7xv-dsp", .data = (ulong)&c71_data, }, {} }; From 8d5e97181ebedb2a5d00552c65631a2f59081e36 Mon Sep 17 00:00:00 2001 From: Hari Nagalla Date: Thu, 9 May 2024 09:20:35 -0500 Subject: [PATCH 017/383] remoteproc: k3-r5: Add support for R5F core on AM62A SoCs AM62A has a R5F core in MCU voltage domain. Extend support for R5F remote proc driver on AM62A with compatible strings. Signed-off-by: Hari Nagalla Reviewed-by: Devarsh Thakkar --- drivers/remoteproc/ti_k3_r5f_rproc.c | 29 ++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c index 631e548dcce..35835b2d61c 100644 --- a/drivers/remoteproc/ti_k3_r5f_rproc.c +++ b/drivers/remoteproc/ti_k3_r5f_rproc.c @@ -40,6 +40,8 @@ #define PROC_BOOT_CFG_FLAG_GEN_IGN_BOOTVECTOR 0x10000000 /* Available from J7200 SoCs onwards */ #define PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS 0x00004000 +#define PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE 0x00008000 + /* R5 TI-SCI Processor Control Flags */ #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001 @@ -55,6 +57,8 @@ enum cluster_mode { CLUSTER_MODE_SPLIT = 0, CLUSTER_MODE_LOCKSTEP, + CLUSTER_MODE_SINGLECPU, + CLUSTER_MODE_SINGLECORE, }; /** @@ -65,6 +69,7 @@ enum cluster_mode { struct k3_r5f_ip_data { bool tcm_is_double; bool tcm_ecc_autoinit; + bool is_single_core; }; /** @@ -599,8 +604,10 @@ static int k3_r5f_rproc_configure(struct k3_r5f_core *core) /* Sanity check for Lockstep mode */ lockstep_permitted = !!(sts & PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED); - if (cluster->mode && is_primary_core(core) && !lockstep_permitted) { - dev_err(core->dev, "LockStep mode not permitted on this device\n"); + if (cluster->mode == CLUSTER_MODE_LOCKSTEP && is_primary_core(core) && + !lockstep_permitted) { + dev_err(core->dev, "LockStep mode not permitted on this \ + device\n"); ret = -EINVAL; goto out; } @@ -615,6 +622,9 @@ static int k3_r5f_rproc_configure(struct k3_r5f_core *core) clr_cfg |= PROC_BOOT_CFG_FLAG_R5_LOCKSTEP; } + if (core->ipdata->is_single_core) + set_cfg = PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE; + if (core->atcm_enable) set_cfg |= PROC_BOOT_CFG_FLAG_R5_ATCM_EN; else @@ -853,11 +863,19 @@ static int k3_r5f_remove(struct udevice *dev) static const struct k3_r5f_ip_data k3_data = { .tcm_is_double = false, .tcm_ecc_autoinit = false, + .is_single_core = false, }; static const struct k3_r5f_ip_data j7200_j721s2_data = { .tcm_is_double = true, .tcm_ecc_autoinit = true, + .is_single_core = false, +}; + +static const struct k3_r5f_ip_data am62_data = { + .tcm_is_double = false, + .tcm_ecc_autoinit = false, + .is_single_core = true, }; static const struct udevice_id k3_r5f_rproc_ids[] = { @@ -865,6 +883,7 @@ static const struct udevice_id k3_r5f_rproc_ids[] = { { .compatible = "ti,j721e-r5f", .data = (ulong)&k3_data, }, { .compatible = "ti,j7200-r5f", .data = (ulong)&j7200_j721s2_data, }, { .compatible = "ti,j721s2-r5f", .data = (ulong)&j7200_j721s2_data, }, + { .compatible = "ti,am62-r5f", .data = (ulong)&am62_data, }, {} }; @@ -887,6 +906,11 @@ static int k3_r5f_cluster_probe(struct udevice *dev) cluster->mode = dev_read_u32_default(dev, "ti,cluster-mode", CLUSTER_MODE_LOCKSTEP); + if (device_is_compatible(dev, "ti,am62-r5fss")) { + cluster->mode = CLUSTER_MODE_SINGLECORE; + return 0; + } + if (device_get_child_count(dev) != 2) { dev_err(dev, "Invalid number of R5 cores"); return -EINVAL; @@ -903,6 +927,7 @@ static const struct udevice_id k3_r5fss_ids[] = { { .compatible = "ti,j721e-r5fss"}, { .compatible = "ti,j7200-r5fss"}, { .compatible = "ti,j721s2-r5fss"}, + { .compatible = "ti,am62-r5fss"}, {} }; From 1ba3ad235de5352cfd3426bb030a559415f50cc2 Mon Sep 17 00:00:00 2001 From: Hari Nagalla Date: Thu, 9 May 2024 09:20:36 -0500 Subject: [PATCH 018/383] configs: am62ax: enable remote proc drivers Enable K3-DSP and K3-R5FSS remote proc drivers for am62ax. Signed-off-by: Hari Nagalla Reviewed-by: Devarsh Thakkar --- configs/am62ax_evm_a53_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig index c4556f5dd2e..6b29a4b9cff 100644 --- a/configs/am62ax_evm_a53_defconfig +++ b/configs/am62ax_evm_a53_defconfig @@ -72,6 +72,8 @@ CONFIG_POWER_DOMAIN=y CONFIG_TI_SCI_POWER_DOMAIN=y CONFIG_K3_SYSTEM_CONTROLLER=y CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_REMOTEPROC_TI_K3_R5F=y +CONFIG_REMOTEPROC_TI_K3_DSP=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y CONFIG_SOC_DEVICE=y @@ -81,3 +83,4 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_CMD_REMOTEPROC=y From bf37851dc639273feefea8115fa3d43898d58e8d Mon Sep 17 00:00:00 2001 From: Hari Nagalla Date: Thu, 9 May 2024 09:20:37 -0500 Subject: [PATCH 019/383] board: ti: am62ax: Add support for remote proc load Add AM62a remote proc firmware names to environment variables for loading of C7x DSP and R5F processors. Signed-off-by: Hari Nagalla Reviewed-by: Devarsh Thakkar --- board/ti/am62ax/am62ax.env | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/ti/am62ax/am62ax.env b/board/ti/am62ax/am62ax.env index 334374abb73..97122fb57ba 100644 --- a/board/ti/am62ax/am62ax.env +++ b/board/ti/am62ax/am62ax.env @@ -1,5 +1,8 @@ #include #include +#if CONFIG_CMD_REMOTEPROC +#include +#endif name_kern=Image console=ttyS2,115200n8 @@ -27,3 +30,4 @@ get_kern_mmc=load mmc ${bootpart} ${loadaddr} get_fit_mmc=load mmc ${bootpart} ${addr_fit} ${bootdir}/${name_fit} partitions=name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs} +rproc_fw_binaries= 0 /lib/firmware/am62a-mcu-r5f0_0-fw 1 /lib/firmware/am62a-c71_0-fw From ef9d4da6c92b07f0668f059d0cdc51eb34ed947e Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 26 Apr 2024 10:02:24 +0200 Subject: [PATCH 020/383] net: eth-uclass: guard against reentrant eth_init()/eth_halt() calls With netconsole, any log message can result in an eth_init(), possibly causing an reentrant call into eth_init() if a driver's ops print anything: eth_init() -> driver.start() -> printf() -> netconsole -> eth_init() eth_halt() -> driver.stop() -> printf() -> netconsole -> eth_init() Rather than expecting every single Ethernet driver to handle this case, prevent the reentrant calls in eth_init() and eth_halt(). The issue was noticed on an AM62x board, where a bootm after simultaneous netconsole and TFTP would result in a crash. Signed-off-by: Matthias Schiffer Link: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1350550/sk-am62a-lp-am65_cpsw_nuss_port-error-in-u-boot-while-using-netconsole-functionality/ --- net/eth-uclass.c | 40 ++++++++++++++++++++++++++++++++-------- 1 file changed, 32 insertions(+), 8 deletions(-) diff --git a/net/eth-uclass.c b/net/eth-uclass.c index 4e3933fd05f..e34d7af0229 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -47,6 +47,8 @@ struct eth_uclass_priv { /* eth_errno - This stores the most recent failure code from DM functions */ static int eth_errno; +/* Are we currently in eth_init() or eth_halt()? */ +static bool in_init_halt; /* board-specific Ethernet Interface initializations. */ __weak int board_interface_eth_init(struct udevice *dev, @@ -284,11 +286,19 @@ U_BOOT_ENV_CALLBACK(ethaddr, on_ethaddr); int eth_init(void) { - char *ethact = env_get("ethact"); - char *ethrotate = env_get("ethrotate"); struct udevice *current = NULL; struct udevice *old_current; int ret = -ENODEV; + char *ethrotate; + char *ethact; + + if (in_init_halt) + return -EBUSY; + + in_init_halt = true; + + ethact = env_get("ethact"); + ethrotate = env_get("ethrotate"); /* * When 'ethrotate' variable is set to 'no' and 'ethact' variable @@ -297,8 +307,10 @@ int eth_init(void) if ((ethrotate != NULL) && (strcmp(ethrotate, "no") == 0)) { if (ethact) { current = eth_get_dev_by_name(ethact); - if (!current) - return -EINVAL; + if (!current) { + ret = -EINVAL; + goto end; + } } } @@ -306,7 +318,8 @@ int eth_init(void) current = eth_get_dev(); if (!current) { log_err("No ethernet found.\n"); - return -ENODEV; + ret = -ENODEV; + goto end; } } @@ -323,7 +336,8 @@ int eth_init(void) priv->state = ETH_STATE_ACTIVE; priv->running = true; - return 0; + ret = 0; + goto end; } } else { ret = eth_errno; @@ -343,6 +357,8 @@ int eth_init(void) current = eth_get_dev(); } while (old_current != current); +end: + in_init_halt = false; return ret; } @@ -351,17 +367,25 @@ void eth_halt(void) struct udevice *current; struct eth_device_priv *priv; + if (in_init_halt) + return; + + in_init_halt = true; + current = eth_get_dev(); if (!current) - return; + goto end; priv = dev_get_uclass_priv(current); if (!priv || !priv->running) - return; + goto end; eth_get_ops(current)->stop(current); priv->state = ETH_STATE_PASSIVE; priv->running = false; + +end: + in_init_halt = false; } int eth_is_active(struct udevice *dev) From 0898f44b23effb5a0efbbb9783f8669d02d67dca Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 26 Apr 2024 10:02:25 +0200 Subject: [PATCH 021/383] net: ti: am65-cpsw-nuss: avoid errors due to imbalanced start()/stop() The eth-uclass state machine doesn't prevent imbalanced start()/stop() calls - to the contrary, it even provides eth_init_state_only() and eth_halt_state_only() functions that change the state without any calls into the driver. This means that the driver must be robust against duplicate start() and stop() calls as well as send/recv calls while the interface is down. We decide not to print error messages but just to return an error in the latter case, as trying to send packets on a disabled interface commonly happens when the netconsole is still active after the Ethernet has been halted during bootm. Signed-off-by: Matthias Schiffer --- drivers/net/ti/am65-cpsw-nuss.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index 335c8bee3fe..e0968f6e6fc 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -327,6 +327,9 @@ static int am65_cpsw_start(struct udevice *dev) struct ti_udma_drv_chan_cfg_data *dma_rx_cfg_data; int ret, i; + if (common->started) + return 0; + ret = power_domain_on(&common->pwrdmn); if (ret) { dev_err(dev, "power_domain_on() failed %d\n", ret); @@ -487,6 +490,9 @@ static int am65_cpsw_send(struct udevice *dev, void *packet, int length) struct ti_udma_drv_packet_data packet_data; int ret; + if (!common->started) + return -ENETDOWN; + packet_data.pkt_type = AM65_CPSW_CPPI_PKT_TYPE; packet_data.dest_tag = priv->port_id; ret = dma_send(&common->dma_tx, packet, length, &packet_data); @@ -503,6 +509,9 @@ static int am65_cpsw_recv(struct udevice *dev, int flags, uchar **packetp) struct am65_cpsw_priv *priv = dev_get_priv(dev); struct am65_cpsw_common *common = priv->cpsw_common; + if (!common->started) + return -ENETDOWN; + /* try to receive a new packet */ return dma_receive(&common->dma_rx, (void **)packetp, NULL); } From b079bd9e294b64c86dd2b4520de027bc9042a8dc Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 26 Apr 2024 10:02:26 +0200 Subject: [PATCH 022/383] net: ti: am65-cpsw-nuss: fix error handling for "RX dma add buf failed" The RX DMA channel has been requested at this point already, so it must be freed. Signed-off-by: Matthias Schiffer --- drivers/net/ti/am65-cpsw-nuss.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index e0968f6e6fc..c70b42f6bcc 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -361,7 +361,7 @@ static int am65_cpsw_start(struct udevice *dev) UDMA_RX_BUF_SIZE); if (ret) { dev_err(dev, "RX dma add buf failed %d\n", ret); - goto err_free_tx; + goto err_free_rx; } } From e563593d6e3759519cb1b1493e67e032109c8cae Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 26 Apr 2024 10:02:27 +0200 Subject: [PATCH 023/383] dma: ti: k3-udma: add missing include net.h is needed for PKTBUFSRX. Without this definition, the driver will always use 4 RX buffers, causing am65-cpsw-nuss initialization to fail when a higher number of buffers is requested. Signed-off-by: Matthias Schiffer --- drivers/dma/ti/k3-udma.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 8e11d817a5b..e92ede570cf 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include From 1db973b65f9c1efbfa5370a95d6330f29557b3ab Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 26 Apr 2024 10:02:28 +0200 Subject: [PATCH 024/383] dma: ti: k3-udma: invalidate prepared buffers before pushing to recv ring Buffers must not have an unclean cache before being used for DMA - a pending write-back may corrupt the next dev-to-mem transfer otherwise. This was consistently noticeable during long TFTP transfers, when an ARP request is answered by U-Boot in the middle of the transfer: As U-Boot's arp_receive() reuses the receive buffer to prepare its reply packet, the beginning of one of the next incoming TFTP packets is overwritten by the ARP reply. The corrupted packet is ignored, but the TFTP transfer stalls for a few seconds until a timeout is detected and a retransmit is triggered. Signed-off-by: Matthias Schiffer Tested-by: Alexander Sverdlin --- drivers/dma/ti/k3-udma.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index e92ede570cf..da341a24778 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -2677,6 +2677,9 @@ int udma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size) cppi5_hdesc_set_pktlen(desc_rx, size); cppi5_hdesc_attach_buf(desc_rx, dma_dst, size, dma_dst, size); + invalidate_dcache_range((unsigned long)dma_dst, + (unsigned long)(dma_dst + size)); + flush_dcache_range((unsigned long)desc_rx, ALIGN((unsigned long)desc_rx + uc->config.hdesc_size, ARCH_DMA_MINALIGN)); From a70bb482ef314ccd9b5c3319995c2dd4eae460f9 Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Fri, 10 May 2024 10:20:20 +0530 Subject: [PATCH 025/383] board: ti: j721s2: j721s2.env: Add explicit boot_targets Add explicit boot_targets to indicate the specific boot sequence to follow. Signed-off-by: Neha Malcom Francis Signed-off-by: Manorit Chawdhry --- board/ti/j721s2/j721s2.env | 1 + 1 file changed, 1 insertion(+) diff --git a/board/ti/j721s2/j721s2.env b/board/ti/j721s2/j721s2.env index 9a03b9f30ae..a6b22550809 100644 --- a/board/ti/j721s2/j721s2.env +++ b/board/ti/j721s2/j721s2.env @@ -13,6 +13,7 @@ args_all=setenv optargs earlycon=ns16550a,mmio32,0x02880000 ${mtdparts} run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr} +boot_targets=mmc1 mmc0 usb pxe dhcp boot=mmc mmcdev=1 bootpart=1:2 From 237d60459e86ebe82b3714cded3a58eb71ddecd0 Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Fri, 10 May 2024 10:20:21 +0530 Subject: [PATCH 026/383] configs: j721s2_evm_a72_defconfig: Switch to bootstd Switch to using bootstd. Note that with this change, we will stop using distro_bootcmd and instead depend entirely on bootflow method of starting the system up. Also config_distro_bootcmd.h header file that is no longer needed in j721s2_evm.h. Signed-off-by: Neha Malcom Francis Signed-off-by: Manorit Chawdhry --- configs/j721s2_evm_a72_defconfig | 5 +++-- include/configs/j721s2_evm.h | 1 - 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig index 19cd44b068c..8b02d07a9f0 100644 --- a/configs/j721s2_evm_a72_defconfig +++ b/configs/j721s2_evm_a72_defconfig @@ -33,9 +33,10 @@ CONFIG_SPL_SPI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 -CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_SYSTEM_SETUP=y -CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;" +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTSTD_DEFAULTS=y +CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" CONFIG_LOGLEVEL=7 CONFIG_SPL_MAX_SIZE=0xc0000 CONFIG_SPL_BOARD_INIT=y diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h index 846cfa7531c..6186ec32b1d 100644 --- a/include/configs/j721s2_evm.h +++ b/include/configs/j721s2_evm.h @@ -10,7 +10,6 @@ #define __CONFIG_J721S2_EVM_H #include -#include /* SPL Loader Configuration */ #if defined(CONFIG_TARGET_J721S2_A72_EVM) From 30fee2a917a41a7f087c0ede530c8627b08d77f4 Mon Sep 17 00:00:00 2001 From: Manorit Chawdhry Date: Fri, 10 May 2024 10:20:22 +0530 Subject: [PATCH 027/383] arch: arm: dts: k3-am68-sk-r5: Sync with J721s2 R5 file Currently AM68 SK boots with J721s2 R5 DTS and then later changes to AM68 SK DT during runtime. To split the support of J721s2 and AM68, sync AM68 R5 DT with J721s2 R5 DT as that contains some essential node changes for booting up AM68 using AM68 R5 DT. secure_proxy_sa3 and secure_proxy_mcu node changes are required for establishing contact with ROM and TIFS running on SMS M4 core, respectively, and the addition of new power domain helps in holding A72 cluster in reset for configuration of firewalls. Reviewed-by: Neha Malcom Francis Signed-off-by: Manorit Chawdhry --- arch/arm/dts/k3-am68-sk-r5-base-board.dts | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/k3-am68-sk-r5-base-board.dts b/arch/arm/dts/k3-am68-sk-r5-base-board.dts index 695aadc287b..038b08dc3e0 100644 --- a/arch/arm/dts/k3-am68-sk-r5-base-board.dts +++ b/arch/arm/dts/k3-am68-sk-r5-base-board.dts @@ -24,7 +24,8 @@ compatible = "ti,am654-rproc"; reg = <0x0 0x00a90000 0x0 0x10>; power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>; + <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 202 0>; clocks = <&k3_clks 61 1>; assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>; @@ -54,10 +55,12 @@ &secure_proxy_mcu { bootph-pre-ram; + status = "okay"; }; &secure_proxy_sa3 { bootph-pre-ram; + status = "okay"; }; &cbass_mcu_wakeup { From e84b004abc056233d5ac75d852f1361eeac7e27e Mon Sep 17 00:00:00 2001 From: Manorit Chawdhry Date: Fri, 10 May 2024 10:20:23 +0530 Subject: [PATCH 028/383] arch: arm: dts: k3-j721s2-r5: Introduce k3-j721s2-r5.dtsi Create an SoC R5 dtsi file that could be used at board level R5 files. This would help in keeping the SoC level changes in sync across board files. Reviewed-by: Neha Malcom Francis Signed-off-by: Manorit Chawdhry --- arch/arm/dts/k3-am68-sk-r5-base-board.dts | 78 +----------------- .../dts/k3-j721s2-r5-common-proc-board.dts | 78 +----------------- arch/arm/dts/k3-j721s2-r5.dtsi | 81 +++++++++++++++++++ board/ti/j721s2/MAINTAINERS | 1 + 4 files changed, 84 insertions(+), 154 deletions(-) create mode 100644 arch/arm/dts/k3-j721s2-r5.dtsi diff --git a/arch/arm/dts/k3-am68-sk-r5-base-board.dts b/arch/arm/dts/k3-am68-sk-r5-base-board.dts index 038b08dc3e0..3b2d7af2e52 100644 --- a/arch/arm/dts/k3-am68-sk-r5-base-board.dts +++ b/arch/arm/dts/k3-am68-sk-r5-base-board.dts @@ -9,80 +9,4 @@ #include "k3-j721s2-ddr-evm-lp4-4266.dtsi" #include "k3-j721s2-ddr.dtsi" #include "k3-am68-sk-base-board-u-boot.dtsi" - -/ { - chosen { - tick-timer = &mcu_timer0; - }; - - aliases { - remoteproc0 = &sysctrler; - remoteproc1 = &a72_0; - }; - - a72_0: a72@0 { - compatible = "ti,am654-rproc"; - reg = <0x0 0x00a90000 0x0 0x10>; - power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; - resets = <&k3_reset 202 0>; - clocks = <&k3_clks 61 1>; - assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>; - assigned-clock-parents = <&k3_clks 61 2>; - assigned-clock-rates = <200000000>, <2000000000>; - ti,sci = <&sms>; - ti,sci-proc-id = <32>; - ti,sci-host-id = <10>; - bootph-pre-ram; - }; - - dm_tifs: dm-tifs { - compatible = "ti,j721e-dm-sci"; - ti,host-id = <3>; - ti,secure-host; - mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_mcu 21>, - <&secure_proxy_mcu 23>; - bootph-pre-ram; - }; -}; - -&mcu_timer0 { - clock-frequency = <250000000>; - bootph-pre-ram; -}; - -&secure_proxy_mcu { - bootph-pre-ram; - status = "okay"; -}; - -&secure_proxy_sa3 { - bootph-pre-ram; - status = "okay"; -}; - -&cbass_mcu_wakeup { - sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; - mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>, <&secure_proxy_sa3 5>; - mbox-names = "tx", "rx", "boot_notify"; - bootph-pre-ram; - }; -}; - -&sms { - mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>; - mbox-names = "tx", "rx", "notify"; - ti,host-id = <4>; - ti,secure-host; -}; - -&mcu_ringacc { - ti,sci = <&dm_tifs>; -}; - -&mcu_udmap { - ti,sci = <&dm_tifs>; -}; +#include "k3-j721s2-r5.dtsi" diff --git a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts index 03bd680f442..e92b1917df4 100644 --- a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts @@ -9,80 +9,4 @@ #include "k3-j721s2-ddr-evm-lp4-4266.dtsi" #include "k3-j721s2-ddr.dtsi" #include "k3-j721s2-common-proc-board-u-boot.dtsi" - -/ { - chosen { - tick-timer = &mcu_timer0; - }; - - aliases { - remoteproc0 = &sysctrler; - remoteproc1 = &a72_0; - }; - - a72_0: a72@0 { - compatible = "ti,am654-rproc"; - reg = <0x0 0x00a90000 0x0 0x10>; - power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; - resets = <&k3_reset 202 0>; - clocks = <&k3_clks 61 1>; - assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>; - assigned-clock-parents = <&k3_clks 61 2>; - assigned-clock-rates = <200000000>, <2000000000>; - ti,sci = <&sms>; - ti,sci-proc-id = <32>; - ti,sci-host-id = <10>; - bootph-pre-ram; - }; - - dm_tifs: dm-tifs { - compatible = "ti,j721e-dm-sci"; - ti,host-id = <3>; - ti,secure-host; - mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_mcu 21>, - <&secure_proxy_mcu 23>; - bootph-pre-ram; - }; -}; - -&mcu_timer0 { - clock-frequency = <250000000>; - bootph-pre-ram; -}; - -&secure_proxy_sa3 { - bootph-pre-ram; - status = "okay"; -}; - -&secure_proxy_mcu { - bootph-pre-ram; - status = "okay"; -}; - -&cbass_mcu_wakeup { - sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; - mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>, <&secure_proxy_sa3 5>; - mbox-names = "tx", "rx", "boot_notify"; - bootph-pre-ram; - }; -}; - -&sms { - mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>; - mbox-names = "tx", "rx", "notify"; - ti,host-id = <4>; - ti,secure-host; -}; - -&mcu_ringacc { - ti,sci = <&dm_tifs>; -}; - -&mcu_udmap { - ti,sci = <&dm_tifs>; -}; +#include "k3-j721s2-r5.dtsi" diff --git a/arch/arm/dts/k3-j721s2-r5.dtsi b/arch/arm/dts/k3-j721s2-r5.dtsi new file mode 100644 index 00000000000..eb0df42583a --- /dev/null +++ b/arch/arm/dts/k3-j721s2-r5.dtsi @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/ { + chosen { + tick-timer = &mcu_timer0; + }; + + aliases { + remoteproc0 = &sysctrler; + remoteproc1 = &a72_0; + }; + + a72_0: a72@0 { + compatible = "ti,am654-rproc"; + reg = <0x0 0x00a90000 0x0 0x10>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 202 0>; + clocks = <&k3_clks 61 1>; + assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>; + assigned-clock-parents = <&k3_clks 61 2>; + assigned-clock-rates = <200000000>, <2000000000>; + ti,sci = <&sms>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + bootph-pre-ram; + }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <3>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_mcu 21>, + <&secure_proxy_mcu 23>; + bootph-pre-ram; + }; +}; + +&mcu_timer0 { + clock-frequency = <250000000>; + bootph-pre-ram; +}; + +&secure_proxy_sa3 { + bootph-pre-ram; + status = "okay"; +}; + +&secure_proxy_mcu { + bootph-pre-ram; + status = "okay"; +}; + +&cbass_mcu_wakeup { + sysctrler: sysctrler { + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>, <&secure_proxy_sa3 5>; + mbox-names = "tx", "rx", "boot_notify"; + bootph-pre-ram; + }; +}; + +&sms { + mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>; + mbox-names = "tx", "rx", "notify"; + ti,host-id = <4>; + ti,secure-host; +}; + +&mcu_ringacc { + ti,sci = <&dm_tifs>; +}; + +&mcu_udmap { + ti,sci = <&dm_tifs>; +}; diff --git a/board/ti/j721s2/MAINTAINERS b/board/ti/j721s2/MAINTAINERS index 08c8d110ac0..561c3dfff9b 100644 --- a/board/ti/j721s2/MAINTAINERS +++ b/board/ti/j721s2/MAINTAINERS @@ -14,6 +14,7 @@ F: arch/arm/dts/k3-j721s2-thermal.dtsi F: arch/arm/dts/k3-j721s2-som-p0.dtsi F: arch/arm/dts/k3-j721s2-common-proc-board.dts F: arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi +F: arch/arm/dts/k3-j721s2-r5.dtsi F: arch/arm/dts/k3-j721s2-r5-common-proc-board.dts F: arch/arm/dts/k3-j721s2-ddr.dtsi F: arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi From a96be9b8c05ea835d27f7c9bae03279b8bd5dcf2 Mon Sep 17 00:00:00 2001 From: Manorit Chawdhry Date: Fri, 10 May 2024 10:20:24 +0530 Subject: [PATCH 029/383] configs: am68_sk: Move to separate defconfig for AM68 SK board Add defconfig for AM68 SK R5 and A72 configuration. This includes and modifies the AM68 EVM defconfigs: j721s2_evm_r5_defconfig -> am68_sk_r5_defconfig j721s2_evm_a72_defconfig -> am68_sk_a72_defconfig Reviewed-by: Neha Malcom Francis Signed-off-by: Manorit Chawdhry --- .../arm/dts/k3-am68-sk-base-board-u-boot.dtsi | 23 +++++ arch/arm/dts/k3-j721s2-binman.dtsi | 89 +------------------ board/ti/j721s2/MAINTAINERS | 2 + configs/am68_sk_a72_defconfig | 10 +++ configs/am68_sk_r5_defconfig | 10 +++ configs/j721s2_evm_a72_defconfig | 2 +- configs/j721s2_evm_r5_defconfig | 2 +- 7 files changed, 49 insertions(+), 89 deletions(-) create mode 100644 configs/am68_sk_a72_defconfig create mode 100644 configs/am68_sk_r5_defconfig diff --git a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi index b8fc62f0dd1..dca588485d4 100644 --- a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi @@ -129,3 +129,26 @@ dr_mode = "peripheral"; bootph-all; }; + +#ifdef CONFIG_TARGET_J721S2_A72_EVM + +#define SPL_AM68_SK_DTB "spl/dts/k3-am68-sk-base-board.dtb" +#define AM68_SK_DTB "u-boot.dtb" + +&spl_j721s2_evm_dtb { + filename = SPL_AM68_SK_DTB; +}; + +&j721s2_evm_dtb { + filename = AM68_SK_DTB; +}; + +&spl_j721s2_evm_dtb_unsigned { + filename = SPL_AM68_SK_DTB; +}; + +&j721s2_evm_dtb_unsigned { + filename = AM68_SK_DTB; +}; + +#endif diff --git a/arch/arm/dts/k3-j721s2-binman.dtsi b/arch/arm/dts/k3-j721s2-binman.dtsi index 7efb135bdff..c46fda66b0b 100644 --- a/arch/arm/dts/k3-j721s2-binman.dtsi +++ b/arch/arm/dts/k3-j721s2-binman.dtsi @@ -142,10 +142,7 @@ #ifdef CONFIG_TARGET_J721S2_A72_EVM #define SPL_J721S2_EVM_DTB "spl/dts/k3-j721s2-common-proc-board.dtb" -#define SPL_AM68_SK_DTB "spl/dts/k3-am68-sk-base-board.dtb" - #define J721S2_EVM_DTB "u-boot.dtb" -#define AM68_SK_DTB "arch/arm/dts/k3-am68-sk-base-board.dtb" &binman { ti-dm { @@ -306,20 +303,6 @@ }; }; - - fdt-1 { - description = "k3-am68-sk-base-board"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - ti-secure { - content = <&spl_am68_sk_dtb>; - keyfile = "custMpk.pem"; - }; - spl_am68_sk_dtb: blob-ext { - filename = SPL_AM68_SK_DTB; - }; - }; }; configurations { @@ -331,13 +314,6 @@ loadables = "tee", "dm", "spl"; fdt = "fdt-0"; }; - - conf-1 { - description = "k3-am68-sk-base-board"; - firmware = "atf"; - loadables = "tee", "dm", "spl"; - fdt = "fdt-1"; - }; }; }; }; @@ -370,25 +346,6 @@ algo = "crc32"; }; }; - - fdt-1 { - description = "k3-am68-sk-base-board"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - ti-secure { - content = <&am68_sk_dtb>; - keyfile = "custMpk.pem"; - }; - am68_sk_dtb: blob-ext { - filename = AM68_SK_DTB; - }; - - hash { - algo = "crc32"; - }; - }; - }; configurations { @@ -400,13 +357,6 @@ loadables = "uboot"; fdt = "fdt-0"; }; - conf-1 { - description = "k3-am68-sk-base-board"; - firmware = "uboot"; - loadables = "uboot"; - fdt = "fdt-1"; - }; - }; }; }; @@ -429,20 +379,10 @@ type = "flat_dt"; arch = "arm"; compression = "none"; - blob { + spl_j721s2_evm_dtb_unsigned: blob { filename = SPL_J721S2_EVM_DTB; }; }; - fdt-1 { - description = "k3-am68-sk-base-board"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - blob { - filename = SPL_AM68_SK_DTB; - }; - }; - }; configurations { @@ -454,12 +394,6 @@ loadables = "tee", "dm", "spl"; fdt = "fdt-0"; }; - conf-1 { - description = "k3-am68-sk-base-board"; - firmware = "atf"; - loadables = "tee", "dm", "spl"; - fdt = "fdt-1"; - }; }; }; }; @@ -480,26 +414,13 @@ type = "flat_dt"; arch = "arm"; compression = "none"; - blob { + j721s2_evm_dtb_unsigned: blob { filename = J721S2_EVM_DTB; }; hash { algo = "crc32"; }; }; - fdt-1 { - description = "k3-am68-sk-base-board"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - blob { - filename = AM68_SK_DTB; - }; - hash { - algo = "crc32"; - }; - }; - }; configurations { @@ -511,12 +432,6 @@ loadables = "uboot"; fdt = "fdt-0"; }; - conf-1 { - description = "k3-am68-sk-base-board"; - firmware = "uboot"; - loadables = "uboot"; - fdt = "fdt-1"; - }; }; }; }; diff --git a/board/ti/j721s2/MAINTAINERS b/board/ti/j721s2/MAINTAINERS index 561c3dfff9b..6cf90014a09 100644 --- a/board/ti/j721s2/MAINTAINERS +++ b/board/ti/j721s2/MAINTAINERS @@ -7,6 +7,8 @@ F: doc/board/ti/j721s2_evm.rst F: include/configs/j721s2_evm.h F: configs/j721s2_evm_r5_defconfig F: configs/j721s2_evm_a72_defconfig +F: configs/am68_sk_r5_defconfig +F: configs/am68_sk_a72_defconfig F: arch/arm/dts/k3-j721s2.dtsi F: arch/arm/dts/k3-j721s2-main.dtsi F: arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi diff --git a/configs/am68_sk_a72_defconfig b/configs/am68_sk_a72_defconfig new file mode 100644 index 00000000000..d477f9e4e98 --- /dev/null +++ b/configs/am68_sk_a72_defconfig @@ -0,0 +1,10 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_J721S2=y +CONFIG_TARGET_J721S2_A72_EVM=y + +CONFIG_DEFAULT_DEVICE_TREE="k3-am68-sk-base-board" +CONFIG_SPL_OF_LIST="k3-am68-sk-base-board" +CONFIG_OF_LIST="k3-am68-sk-base-board" diff --git a/configs/am68_sk_r5_defconfig b/configs/am68_sk_r5_defconfig new file mode 100644 index 00000000000..e9b6882c1f6 --- /dev/null +++ b/configs/am68_sk_r5_defconfig @@ -0,0 +1,10 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_J721S2=y +CONFIG_TARGET_J721S2_R5_EVM=y + +CONFIG_DEFAULT_DEVICE_TREE="k3-am68-sk-r5-base-board" +CONFIG_SPL_OF_LIST="k3-am68-sk-r5-base-board" +CONFIG_OF_LIST="k3-am68-sk-r5-base-board" diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig index 8b02d07a9f0..dd86b5c0509 100644 --- a/configs/j721s2_evm_a72_defconfig +++ b/configs/j721s2_evm_a72_defconfig @@ -84,7 +84,7 @@ CONFIG_CMD_UBI=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="k3-j721s2-common-proc-board k3-am68-sk-base-board" +CONFIG_OF_LIST="k3-j721s2-common-proc-board" CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index 5ef5247a3e0..3c958cafbe8 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -82,7 +82,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_MULTI_DTB_FIT=y -CONFIG_SPL_OF_LIST="k3-j721s2-r5-common-proc-board k3-am68-sk-r5-base-board" +CONFIG_SPL_OF_LIST="k3-j721s2-r5-common-proc-board" CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y From 90e5a61976f5f6b37c357d4204369f1fdfa72f6f Mon Sep 17 00:00:00 2001 From: Manorit Chawdhry Date: Fri, 10 May 2024 10:20:25 +0530 Subject: [PATCH 030/383] arm: dts: k3-j721s2|am68: Migrate to OF_UPSTREAM Use OF_UPSTREAM to pull Linux DT from dts/ tree Signed-off-by: Manorit Chawdhry --- arch/arm/dts/Makefile | 4 +- .../arm/dts/k3-am68-sk-base-board-u-boot.dtsi | 20 +- arch/arm/dts/k3-am68-sk-base-board.dts | 611 ------ arch/arm/dts/k3-am68-sk-som.dtsi | 259 --- arch/arm/dts/k3-j721s2-binman.dtsi | 2 +- .../k3-j721s2-common-proc-board-u-boot.dtsi | 18 +- arch/arm/dts/k3-j721s2-common-proc-board.dts | 504 ----- arch/arm/dts/k3-j721s2-main.dtsi | 1928 ----------------- arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi | 738 ------- arch/arm/dts/k3-j721s2-som-p0.dtsi | 361 --- arch/arm/dts/k3-j721s2-thermal.dtsi | 101 - arch/arm/dts/k3-j721s2.dtsi | 175 -- board/ti/j721s2/MAINTAINERS | 8 - configs/am68_sk_a72_defconfig | 6 +- configs/j721s2_evm_a72_defconfig | 5 +- 15 files changed, 23 insertions(+), 4717 deletions(-) delete mode 100644 arch/arm/dts/k3-am68-sk-base-board.dts delete mode 100644 arch/arm/dts/k3-am68-sk-som.dtsi delete mode 100644 arch/arm/dts/k3-j721s2-common-proc-board.dts delete mode 100644 arch/arm/dts/k3-j721s2-main.dtsi delete mode 100644 arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi delete mode 100644 arch/arm/dts/k3-j721s2-som-p0.dtsi delete mode 100644 arch/arm/dts/k3-j721s2-thermal.dtsi delete mode 100644 arch/arm/dts/k3-j721s2.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c9f1b25ad64..60660f24d94 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1331,9 +1331,7 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ k3-j721e-beagleboneai64.dtb \ k3-j721e-r5-beagleboneai64.dtb -dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-base-board.dtb\ - k3-am68-sk-r5-base-board.dtb\ - k3-j721s2-common-proc-board.dtb\ +dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-r5-base-board.dtb\ k3-j721s2-r5-common-proc-board.dtb dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-r5-sk.dtb \ diff --git a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi index dca588485d4..4b8d73a92d6 100644 --- a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi @@ -19,10 +19,14 @@ &cbass_mcu_wakeup { bootph-all; +}; - chipid@43000014 { - bootph-all; - }; +&wkup_conf { + bootph-all; +}; + +&chipid { + bootph-all; }; &mcu_navss { @@ -34,14 +38,6 @@ }; &mcu_udmap { - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x284c0000 0x0 0x4000>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x284a0000 0x0 0x4000>, - <0x0 0x2aa00000 0x0 0x40000>, - <0x0 0x28400000 0x0 0x2000>; - reg-names = "gcfg", "rchan", "rchanrt", "tchan", - "tchanrt", "rflow"; bootph-all; }; @@ -132,7 +128,7 @@ #ifdef CONFIG_TARGET_J721S2_A72_EVM -#define SPL_AM68_SK_DTB "spl/dts/k3-am68-sk-base-board.dtb" +#define SPL_AM68_SK_DTB "spl/dts/ti/k3-am68-sk-base-board.dtb" #define AM68_SK_DTB "u-boot.dtb" &spl_j721s2_evm_dtb { diff --git a/arch/arm/dts/k3-am68-sk-base-board.dts b/arch/arm/dts/k3-am68-sk-base-board.dts deleted file mode 100644 index 1e1a82f9d2b..00000000000 --- a/arch/arm/dts/k3-am68-sk-base-board.dts +++ /dev/null @@ -1,611 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ - * - * Base Board: https://www.ti.com/lit/zip/SPRR463 - */ - -/dts-v1/; - -#include "k3-am68-sk-som.dtsi" -#include -#include -#include - -#include "k3-serdes.h" - -/ { - compatible = "ti,am68-sk", "ti,j721s2"; - model = "Texas Instruments AM68 SK"; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart8; - mmc1 = &main_sdhci1; - can0 = &mcu_mcan0; - can1 = &mcu_mcan1; - can2 = &main_mcan6; - can3 = &main_mcan7; - }; - - vusb_main: regulator-vusb-main5v0 { - /* USB MAIN INPUT 5V DC */ - compatible = "regulator-fixed"; - regulator-name = "vusb-main5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_3v3: regulator-vsys3v3 { - /* Output of LM5141 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vusb_main>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_mmc1: regulator-sd { - /* Output of TPS22918 */ - compatible = "regulator-fixed"; - regulator-name = "vdd_mmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - vin-supply = <&vsys_3v3>; - gpio = <&exp1 8 GPIO_ACTIVE_HIGH>; - }; - - vdd_sd_dv: regulator-tlv71033 { - /* Output of TLV71033 */ - compatible = "regulator-gpio"; - regulator-name = "tlv71033"; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_sd_dv_pins_default>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - vin-supply = <&vsys_3v3>; - gpios = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0>, - <3300000 0x1>; - }; - - vsys_io_1v8: regulator-vsys-io-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vsys_io_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_io_1v2: regulator-vsys-io-1v2 { - compatible = "regulator-fixed"; - regulator-name = "vsys_io_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - transceiver1: can-phy0 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - }; - - transceiver2: can-phy1 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - }; - - transceiver3: can-phy2 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - }; - - transceiver4: can-phy3 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - }; - - connector-hdmi { - compatible = "hdmi-connector"; - label = "hdmi"; - type = "a"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_pins_default>; - ddc-i2c-bus = <&mcu_i2c1>; - /* HDMI_HPD */ - hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - bridge-dvi { - compatible = "ti,tfp410"; - /* HDMI_PDn */ - powerdown-gpios = <&exp2 0 GPIO_ACTIVE_LOW>; - ti,deskew = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi_out0>; - pclk-sample = <1>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; -}; - -&main_pmx0 { - main_uart8_pins_default: main-uart8-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ - J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ - >; - }; - - main_i2c0_pins_default: main-i2c0-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x0e0, PIN_INPUT, 0) /* (AH25) I2C0_SCL */ - J721S2_IOPAD(0x0e4, PIN_INPUT, 0) /* (AE24) I2C0_SDA */ - >; - }; - - main_mmc1_pins_default: main-mmc1-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ - J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ - J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */ - J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ - J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ - J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ - J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ - >; - }; - - vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x0c4, PIN_INPUT, 7) /* (AB26) ECAP0_IN_APWM_OUT.GPIO0_49 */ - >; - }; - - main_usbss0_pins_default: main-usbss0-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ - >; - }; - - main_mcan6_pins_default: main-mcan6-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x098, PIN_INPUT, 0) /* (V25) MCASP0_AXR10.MCAN6_RX */ - J721S2_IOPAD(0x094, PIN_INPUT, 0) /* (AA25) MCASP0_AXR9.MCAN6_TX */ - >; - }; - - main_mcan7_pins_default: main-mcan7-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x0a0, PIN_INPUT, 0) /* (AB25) MCASP0_AXR12.MCAN7_RX */ - J721S2_IOPAD(0x09c, PIN_INPUT, 0) /* (T24) MCASP0_AXR11.MCAN7_TX */ - >; - }; - - main_i2c4_pins_default: main-i2c4-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) MCAN13_RX.I2C4_SDA */ - J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) MCAN14_TX.I2C4_SCL */ - >; - }; - - rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x0a8, PIN_INPUT, 7) /* (U24) MCASP0_AXR14.GPIO0_42 */ - J721S2_IOPAD(0x090, PIN_INPUT, 7) /* (W24) MCASP0_AXR8.GPIO0_36 */ - J721S2_IOPAD(0x0bc, PIN_INPUT, 7) /* (V28) MCASP1_AFSX.GPIO0_47 */ - J721S2_IOPAD(0x06c, PIN_INPUT, 7) /* (V26) MCAN1_TX.GPIO0_27 */ - J721S2_IOPAD(0x004, PIN_INPUT, 7) /* (W25) MCAN12_TX.GPIO0_1 */ - J721S2_IOPAD(0x008, PIN_INPUT, 7) /* (AC24) MCAN12_RX.GPIO0_2 */ - J721S2_IOPAD(0x0b8, PIN_INPUT, 7) /* (AA24) MCASP1_ACLKX.GPIO0_46 */ - J721S2_IOPAD(0x00c, PIN_INPUT, 7) /* (AE28) MCAN13_TX.GPIO0_3 */ - J721S2_IOPAD(0x034, PIN_INPUT, 7) /* (AD24) PMIC_WAKE0.GPIO0_13 */ - J721S2_IOPAD(0x0a4, PIN_INPUT, 7) /* (T23) MCASP0_AXR13.GPIO0_41 */ - J721S2_IOPAD(0x0c0, PIN_INPUT, 7) /* (T28) MCASP1_AXR0.GPIO0_48 */ - J721S2_IOPAD(0x0b4, PIN_INPUT, 7) /* (U25) MCASP1_AXR4.GPIO0_45 */ - J721S2_IOPAD(0x0cc, PIN_INPUT, 7) /* (AE27) SPI0_CS0.GPIO0_51 */ - J721S2_IOPAD(0x08c, PIN_INPUT, 7) /* (T25) MCASP0_AXR7.GPIO0_35 */ - >; - }; - - dss_vout0_pins_default: dss-vout0-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x074, PIN_OUTPUT, 2) /* (R28) MCAN2_TX.VOUT0_DATA0 */ - J721S2_IOPAD(0x070, PIN_OUTPUT, 2) /* (R27) MCAN1_RX.VOUT0_DATA1 */ - J721S2_IOPAD(0x04c, PIN_OUTPUT, 2) /* (V27) MCASP1_AXR1.VOUT0_DATA10 */ - J721S2_IOPAD(0x048, PIN_OUTPUT, 2) /* (AB27) MCASP0_AXR2.VOUT0_DATA11 */ - J721S2_IOPAD(0x044, PIN_OUTPUT, 2) /* (Y26) MCASP0_AXR1.VOUT0_DATA12 */ - J721S2_IOPAD(0x040, PIN_OUTPUT, 2) /* (AC28) MCASP0_AXR0.VOUT0_DATA13 */ - J721S2_IOPAD(0x03c, PIN_OUTPUT, 2) /* (U27) MCASP0_AFSX.VOUT0_DATA14 */ - J721S2_IOPAD(0x038, PIN_OUTPUT, 2) /* (AB28) MCASP0_ACLKX.VOUT0_DATA15 */ - J721S2_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AD28) EXT_REFCLK1.VOUT0_DATA16 */ - J721S2_IOPAD(0x030, PIN_OUTPUT, 2) /* (T26) GPIO0_12.VOUT0_DATA17 */ - J721S2_IOPAD(0x02c, PIN_OUTPUT, 2) /* (V23) GPIO0_11.VOUT0_DATA18 */ - J721S2_IOPAD(0x028, PIN_OUTPUT, 2) /* (AB24) MCAN16_RX.VOUT0_DATA19 */ - J721S2_IOPAD(0x07c, PIN_OUTPUT, 2) /* (T27) MCASP0_AXR3.VOUT0_DATA2 */ - J721S2_IOPAD(0x024, PIN_OUTPUT, 2) /* (Y28) MCAN16_TX.VOUT0_DATA20 */ - J721S2_IOPAD(0x020, PIN_OUTPUT, 2) /* (AA23) MCAN15_RX.VOUT0_DATA21 */ - J721S2_IOPAD(0x01c, PIN_OUTPUT, 2) /* (Y24) MCAN15_TX.VOUT0_DATA22 */ - J721S2_IOPAD(0x018, PIN_OUTPUT, 2) /* (W23) MCAN14_RX.VOUT0_DATA23 */ - J721S2_IOPAD(0x068, PIN_OUTPUT, 2) /* (U28) MCAN0_RX.VOUT0_DATA3 */ - J721S2_IOPAD(0x064, PIN_OUTPUT, 2) /* (W28) MCAN0_TX.VOUT0_DATA4 */ - J721S2_IOPAD(0x060, PIN_OUTPUT, 2) /* (AC27) MCASP2_AXR1.VOUT0_DATA5 */ - J721S2_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AA26) MCASP2_AXR0.VOUT0_DATA6 */ - J721S2_IOPAD(0x058, PIN_OUTPUT, 2) /* (AA27) MCASP2_AFSX.VOUT0_DATA7 */ - J721S2_IOPAD(0x054, PIN_OUTPUT, 2) /* (Y27) MCASP2_ACLKX.VOUT0_DATA8 */ - J721S2_IOPAD(0x050, PIN_OUTPUT, 2) /* (W27) MCASP1_AXR2.VOUT0_DATA9 */ - J721S2_IOPAD(0x084, PIN_OUTPUT, 2) /* (AA28) MCASP0_AXR5.VOUT0_DE */ - J721S2_IOPAD(0x080, PIN_OUTPUT, 2) /* (U26) MCASP0_AXR4.VOUT0_HSYNC */ - J721S2_IOPAD(0x078, PIN_OUTPUT, 2) /* (Y25) MCAN2_RX.VOUT0_PCLK */ - J721S2_IOPAD(0x088, PIN_OUTPUT, 2) /* (AD27) MCASP0_AXR6.VOUT0_VP0_VSYNC */ - >; - }; - - hdmi_hpd_pins_default: hdmi-hpd-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x000, PIN_INPUT, 7) /* (AG24) EXTINTN.GPIO0_0 */ - >; - }; -}; - -&wkup_pmx2 { - wkup_uart0_pins_default: wkup-uart0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */ - J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */ - J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ - J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ - >; - }; - - mcu_cpsw_pins_default: mcu-cpsw-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x02C, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ - J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ - J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ - J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ - J721S2_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ - J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ - J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ - J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ - J721S2_WKUP_IOPAD(0x00C, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ - J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ - J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ - J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ - >; - }; - - mcu_mdio_pins_default: mcu-mdio-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ - J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ - >; - }; - - mcu_mcan0_pins_default: mcu-mcan0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ - J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ - >; - }; - - mcu_mcan1_pins_default: mcu-mcan1-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x06C, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ - J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/ - >; - }; - - mcu_i2c0_pins_default: mcu-i2c0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0a0, PIN_INPUT, 0) /* (G24) MCU_I2C0_SCL */ - J721S2_WKUP_IOPAD(0x0a4, PIN_INPUT, 0) /* (J25) MCU_I2C0_SDA */ - >; - }; - - mcu_i2c1_pins_default: mcu-i2c1-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x078, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */ - J721S2_WKUP_IOPAD(0x07c, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */ - >; - }; - - mcu_uart0_pins_default: mcu-uart0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ - J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ - >; - }; - - mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-default-pins-0 { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */ - J721S2_WKUP_IOPAD(0x05C, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */ - J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) MCU_SPI1_D1.WKUP_GPIO0_2 */ - J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) MCU_SPI1_CLK.WKUP_GPIO0_0 */ - J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (D25) MCU_SPI1_CS2.WKUP_GPIO0_15*/ - J721S2_WKUP_IOPAD(0x0B8, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */ - J721S2_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (J26) WKUP_GPIO0_57 */ - J721S2_WKUP_IOPAD(0x11C, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */ - J721S2_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (C27) MCU_SPI1_CS0.WKUP_GPIO0_3 */ - >; - }; -}; - -&wkup_pmx3 { - mcu_rpi_header_gpio0_pins1_default: mcu-rpi-header-gpio0-default-pins-1 { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (K26) WKUP_GPIO0_49 */ - >; - }; -}; - -&main_gpio0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&rpi_header_gpio0_pins_default>; -}; - -&wkup_gpio0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_rpi_header_gpio0_pins0_default>, <&mcu_rpi_header_gpio0_pins1_default>; -}; - -&wkup_uart0 { - status = "reserved"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_uart0_pins_default>; -}; - -&mcu_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_uart0_pins_default>; -}; - -&main_uart8 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart8_pins_default>; - /* Shared with TFA on this platform */ - power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>; -}; - -&main_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - exp1: gpio@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = " ", " ", " ", " ", " ", - "BOARDID_EEPROM_WP", "CAN_STB", " ", - "GPIO_uSD_PWR_EN", " ", "IO_EXP_PCIe1_M.2_RTSz", - "IO_EXP_MCU_RGMII_RST#", " ", " ", " ", " "; - }; -}; - -&main_i2c4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c4_pins_default>; - clock-frequency = <400000>; -}; - -&mcu_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_i2c0_pins_default>; - clock-frequency = <400000>; -}; - -&mcu_i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_i2c1_pins_default>; - /* i2c1 is used for DVI DDC, so we need to use 100kHz */ - clock-frequency = <100000>; - - exp2: gpio@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "HDMI_PDn","HDMI_LS_OE", - "DP0_3V3_EN","eDP_ENABLE"; - }; -}; - -&main_sdhci1 { - /* SD card */ - status = "okay"; - pinctrl-0 = <&main_mmc1_pins_default>; - pinctrl-names = "default"; - disable-wp; - vmmc-supply = <&vdd_mmc1>; - vqmmc-supply = <&vdd_sd_dv>; -}; - -&mcu_cpsw { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; -}; - -&davinci_mdio { - phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = ; - ti,fifo-depth = ; - ti,min-output-impedance; - }; -}; - -&cpsw_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&phy0>; -}; - -&mcu_mcan0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan0_pins_default>; - phys = <&transceiver1>; -}; - -&mcu_mcan1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan1_pins_default>; - phys = <&transceiver2>; -}; - -&main_mcan6 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mcan6_pins_default>; - phys = <&transceiver3>; -}; - -&main_mcan7 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mcan7_pins_default>; - phys = <&transceiver4>; -}; - -&dss { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dss_vout0_pins_default>; - /* - * These clock assignments are chosen to enable the following outputs: - * - * VP0 - DisplayPort SST - * VP1 - DPI0 - * VP2 - DSI - * VP3 - DPI1 - */ - assigned-clocks = <&k3_clks 158 2>, - <&k3_clks 158 5>, - <&k3_clks 158 14>, - <&k3_clks 158 18>; - assigned-clock-parents = <&k3_clks 158 3>, - <&k3_clks 158 7>, - <&k3_clks 158 16>, - <&k3_clks 158 22>; -}; - -&dss_ports { - #address-cells = <1>; - #size-cells = <0>; - - /* HDMI */ - port@1 { - reg = <1>; - - dpi_out0: endpoint { - remote-endpoint = <&tfp410_in>; - }; - }; -}; - -&serdes_ln_ctrl { - idle-states = , , - , ; -}; - -&serdes_refclk { - clock-frequency = <100000000>; -}; - -&serdes0 { - status = "okay"; - - serdes0_pcie_link: phy@0 { - reg = <0>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = ; - resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; - }; - - serdes0_usb_link: phy@2 { - status = "okay"; - reg = <2>; - cdns,num-lanes = <1>; - #phy-cells = <0>; - cdns,phy-type = ; - resets = <&serdes_wiz0 3>; - }; -}; - -&pcie1_rc { - status = "okay"; - reset-gpios = <&exp1 10 GPIO_ACTIVE_HIGH>; - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; -}; - -&usb_serdes_mux { - idle-states = <0>; /* USB0 to SERDES lane 2 */ -}; - -&usbss0 { - status = "okay"; - pinctrl-0 = <&main_usbss0_pins_default>; - pinctrl-names = "default"; - ti,vbus-divider; -}; - -&usb0 { - dr_mode = "host"; - maximum-speed = "super-speed"; - phys = <&serdes0_usb_link>; - phy-names = "cdns3,usb3-phy"; -}; diff --git a/arch/arm/dts/k3-am68-sk-som.dtsi b/arch/arm/dts/k3-am68-sk-som.dtsi deleted file mode 100644 index 20861a0a46b..00000000000 --- a/arch/arm/dts/k3-am68-sk-som.dtsi +++ /dev/null @@ -1,259 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; - -#include "k3-j721s2.dtsi" -#include - -/ { - memory@80000000 { - device_type = "memory"; - /* 16 GB RAM */ - reg = <0x00 0x80000000 0x00 0x80000000>, - <0x08 0x80000000 0x03 0x80000000>; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0100000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c71_1_dma_memory_region: c71-dma-memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c71_1_memory_region: c71-memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a8000000 { - reg = <0x00 0xa8000000 0x00 0x01c00000>; - alignment = <0x1000>; - no-map; - }; - }; -}; - -&wkup_pmx2 { - wkup_i2c0_pins_default: wkup-i2c0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ - J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ - >; - }; -}; - -&wkup_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <400000>; - - eeprom@51 { - /* AT24C512C-MAHM-T */ - compatible = "atmel,24c512"; - reg = <0x51>; - }; -}; - -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c71_1: mbox-c71-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; - -&c71_1 { - status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>; - memory-region = <&c71_1_dma_memory_region>, - <&c71_1_memory_region>; -}; diff --git a/arch/arm/dts/k3-j721s2-binman.dtsi b/arch/arm/dts/k3-j721s2-binman.dtsi index c46fda66b0b..46297ebef9e 100644 --- a/arch/arm/dts/k3-j721s2-binman.dtsi +++ b/arch/arm/dts/k3-j721s2-binman.dtsi @@ -141,7 +141,7 @@ #ifdef CONFIG_TARGET_J721S2_A72_EVM -#define SPL_J721S2_EVM_DTB "spl/dts/k3-j721s2-common-proc-board.dtb" +#define SPL_J721S2_EVM_DTB "spl/dts/ti/k3-j721s2-common-proc-board.dtb" #define J721S2_EVM_DTB "u-boot.dtb" &binman { diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi index 19b2d48c7f8..91a82b3b7ca 100644 --- a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi @@ -19,10 +19,14 @@ &cbass_mcu_wakeup { bootph-all; +}; - chipid@43000014 { - bootph-all; - }; +&wkup_conf { + bootph-all; +}; + +&chipid { + bootph-all; }; &mcu_navss { @@ -34,14 +38,6 @@ }; &mcu_udmap { - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x284c0000 0x0 0x4000>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x284a0000 0x0 0x4000>, - <0x0 0x2aa00000 0x0 0x40000>, - <0x0 0x28400000 0x0 0x2000>; - reg-names = "gcfg", "rchan", "rchanrt", "tchan", - "tchanrt", "rflow"; bootph-all; }; diff --git a/arch/arm/dts/k3-j721s2-common-proc-board.dts b/arch/arm/dts/k3-j721s2-common-proc-board.dts deleted file mode 100644 index c6b85bbf9a1..00000000000 --- a/arch/arm/dts/k3-j721s2-common-proc-board.dts +++ /dev/null @@ -1,504 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ - * - * Common Processor Board: https://www.ti.com/tool/J721EXCPXEVM - */ - -/dts-v1/; - -#include "k3-j721s2-som-p0.dtsi" -#include -#include -#include - -#include "k3-serdes.h" - -/ { - compatible = "ti,j721s2-evm", "ti,j721s2"; - model = "Texas Instruments J721S2 EVM"; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - aliases { - serial1 = &mcu_uart0; - serial2 = &main_uart8; - mmc0 = &main_sdhci0; - mmc1 = &main_sdhci1; - can0 = &main_mcan16; - can1 = &mcu_mcan0; - can2 = &mcu_mcan1; - can3 = &main_mcan3; - can4 = &main_mcan5; - }; - - evm_12v0: fixedregulator-evm12v0 { - /* main supply */ - compatible = "regulator-fixed"; - regulator-name = "evm_12v0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_3v3: fixedregulator-vsys3v3 { - /* Output of LM5140 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_5v0: fixedregulator-vsys5v0 { - /* Output of LM5140 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_mmc1: fixedregulator-sd { - /* Output of TPS22918 */ - compatible = "regulator-fixed"; - regulator-name = "vdd_mmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - vin-supply = <&vsys_3v3>; - gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; - }; - - vdd_sd_dv: gpio-regulator-TLV71033 { - /* Output of TLV71033 */ - compatible = "regulator-gpio"; - regulator-name = "tlv71033"; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_sd_dv_pins_default>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - vin-supply = <&vsys_5v0>; - gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0>, - <3300000 0x1>; - }; - - transceiver1: can-phy1 { - compatible = "ti,tcan1043"; - #phy-cells = <0>; - max-bitrate = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; - standby-gpios = <&wkup_gpio0 69 GPIO_ACTIVE_LOW>; - enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>; - }; - - transceiver2: can-phy2 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; - standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; - }; - - transceiver3: can-phy3 { - compatible = "ti,tcan1043"; - #phy-cells = <0>; - max-bitrate = <5000000>; - standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>; - enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; - mux-states = <&mux0 1>; - }; - - transceiver4: can-phy4 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - standby-gpios = <&exp_som 7 GPIO_ACTIVE_HIGH>; - mux-states = <&mux1 1>; - }; -}; - -&main_pmx0 { - main_uart8_pins_default: main-uart8-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */ - J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */ - J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ - J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ - >; - }; - - main_i2c3_pins_default: main-i2c3-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x064, PIN_INPUT_PULLUP, 13) /* (W28) MCAN0_TX.I2C3_SCL */ - J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MCASP2_AXR1.I2C3_SDA */ - >; - }; - - main_mmc1_pins_default: main-mmc1-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ - J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ - J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */ - J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */ - J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ - J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ - J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ - J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ - >; - }; - - vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */ - >; - }; - - main_usbss0_pins_default: main-usbss0-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ - >; - }; - - main_mcan3_pins_default: main-mcan3-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x080, PIN_INPUT, 0) /* (U26) MCASP0_AXR4.MCAN3_RX */ - J721S2_IOPAD(0x07c, PIN_OUTPUT, 0) /* (T27) MCASP0_AXR3.MCAN3_TX */ - >; - }; - - main_mcan5_pins_default: main-mcan5-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x03c, PIN_INPUT, 0) /* (U27) MCASP0_AFSX.MCAN5_RX */ - J721S2_IOPAD(0x038, PIN_OUTPUT, 0) /* (AB28) MCASP0_ACLKX.MCAN5_TX */ - >; - }; -}; - -&wkup_pmx2 { - wkup_uart0_pins_default: wkup-uart0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */ - J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */ - J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ - J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ - >; - }; - - mcu_uart0_pins_default: mcu-uart0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */ - J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */ - J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ - J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ - >; - }; - - mcu_cpsw_pins_default: mcu-cpsw-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ - J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ - J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ - J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ - J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ - J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ - J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ - J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ - J721S2_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ - J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ - J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ - J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ - >; - }; - - mcu_mdio_pins_default: mcu-mdio-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ - J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ - >; - }; - - mcu_mcan0_pins_default: mcu-mcan0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ - J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ - >; - }; - - mcu_mcan1_pins_default: mcu-mcan1-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ - J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /*(C23) WKUP_GPIO0_4.MCU_MCAN1_TX */ - >; - }; - - mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */ - J721S2_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */ - >; - }; - - mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ - >; - }; - - mcu_adc0_pins_default: mcu-adc0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (L25) MCU_ADC0_AIN0 */ - J721S2_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN1 */ - J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (M24) MCU_ADC0_AIN2 */ - J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (L24) MCU_ADC0_AIN3 */ - J721S2_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (L27) MCU_ADC0_AIN4 */ - J721S2_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN5 */ - J721S2_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (M27) MCU_ADC0_AIN6 */ - J721S2_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (M26) MCU_ADC0_AIN7 */ - >; - }; - - mcu_adc1_pins_default: mcu-adc1-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (P25) MCU_ADC1_AIN0 */ - J721S2_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (R25) MCU_ADC1_AIN1 */ - J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (P28) MCU_ADC1_AIN2 */ - J721S2_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (P27) MCU_ADC1_AIN3 */ - J721S2_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (N25) MCU_ADC1_AIN4 */ - J721S2_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (P26) MCU_ADC1_AIN5 */ - J721S2_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (N26) MCU_ADC1_AIN6 */ - J721S2_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */ - >; - }; -}; - -&wkup_pmx1 { - mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ - J721S2_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ - J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ - J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ - J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ - J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ - J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ - J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ - >; - }; -}; - -&main_gpio0 { - status = "okay"; -}; - -&wkup_gpio0 { - status = "okay"; -}; - -&wkup_uart0 { - status = "reserved"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_uart0_pins_default>; -}; - -&mcu_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_uart0_pins_default>; -}; - -&main_uart8 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart8_pins_default>; - /* Shared with TFA on this platform */ - power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>; -}; - -&main_i2c0 { - clock-frequency = <400000>; - - exp1: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "PCIE_2L_MODE_SEL", "PCIE_2L_PERSTZ", "PCIE_2L_RC_RSTZ", - "PCIE_2L_EP_RST_EN", "PCIE_1L_MODE_SEL", "PCIE_1L_PERSTZ", - "PCIE_1L_RC_RSTZ", "PCIE_1L_EP_RST_EN", "PCIE_2L_PRSNT#", - "PCIE_1L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", "EXP_MUX1", - "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTz"; - }; - - exp2: gpio@22 { - compatible = "ti,tca6424"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "APPLE_AUTH_RSTZ", "MLB_RSTZ", "GPIO_USD_PWR_EN", "USBC_PWR_EN", - "USBC_MODE_SEL1", "USBC_MODE_SEL0", "MCAN0_EN", "MCAN0_STB#", - "MUX_SPAREMUX_SPARE", "MCASP/TRACE_MUX_S0", "MCASP/TRACE_MUX_S1", - "MLB_MUX_SEL", "MCAN_MUX_SEL", "MCASP2/SPI3_MUX_SEL", "PCIe_CLKREQn_MUX_SEL", - "CDCI2_RSTZ", "ENET_EXP_PWRDN", "ENET_EXP_RESETZ", "ENET_I2CMUX_SEL", - "ENET_EXP_SPARE2", "M2PCIE_RTSZ", "USER_INPUT1", "USER_LED1", "USER_LED2"; - }; -}; - -&main_sdhci0 { - /* eMMC */ - status = "okay"; - non-removable; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&main_sdhci1 { - /* SD card */ - status = "okay"; - pinctrl-0 = <&main_mmc1_pins_default>; - pinctrl-names = "default"; - disable-wp; - vmmc-supply = <&vdd_mmc1>; - vqmmc-supply = <&vdd_sd_dv>; -}; - -&mcu_cpsw { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; -}; - -&davinci_mdio { - phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = ; - ti,fifo-depth = ; - ti,min-output-impedance; - }; -}; - -&cpsw_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&phy0>; -}; - -&serdes_ln_ctrl { - idle-states = , , - , ; -}; - -&serdes_refclk { - clock-frequency = <100000000>; -}; - -&serdes0 { - status = "okay"; - serdes0_pcie_link: phy@0 { - reg = <0>; - cdns,num-lanes = <1>; - #phy-cells = <0>; - cdns,phy-type = ; - resets = <&serdes_wiz0 1>; - }; -}; - -&usb_serdes_mux { - idle-states = <1>; /* USB0 to SERDES lane 1 */ -}; - -&usbss0 { - status = "okay"; - pinctrl-0 = <&main_usbss0_pins_default>; - pinctrl-names = "default"; - ti,vbus-divider; - ti,usb2-only; -}; - -&usb0 { - dr_mode = "otg"; - maximum-speed = "high-speed"; -}; - -&ospi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - spi-max-frequency = <40000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <2>; - }; -}; - -&pcie1_rc { - status = "okay"; - reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <1>; -}; - -&mcu_mcan0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan0_pins_default>; - phys = <&transceiver1>; -}; - -&mcu_mcan1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan1_pins_default>; - phys = <&transceiver2>; -}; - -&tscadc0 { - pinctrl-0 = <&mcu_adc0_pins_default>; - pinctrl-names = "default"; - status = "okay"; - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&tscadc1 { - pinctrl-0 = <&mcu_adc1_pins_default>; - pinctrl-names = "default"; - status = "okay"; - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&main_mcan3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mcan3_pins_default>; - phys = <&transceiver3>; -}; - -&main_mcan5 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mcan5_pins_default>; - phys = <&transceiver4>; -}; diff --git a/arch/arm/dts/k3-j721s2-main.dtsi b/arch/arm/dts/k3-j721s2-main.dtsi deleted file mode 100644 index b03731b53a2..00000000000 --- a/arch/arm/dts/k3-j721s2-main.dtsi +++ /dev/null @@ -1,1928 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J721S2 SoC Family Main Domain peripherals - * - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include -#include - -/ { - serdes_refclk: clock-cmnrefclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; -}; - -&cbass_main { - msmc_ram: sram@70000000 { - compatible = "mmio-sram"; - reg = <0x0 0x70000000 0x0 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x70000000 0x400000>; - - atf-sram@0 { - reg = <0x0 0x20000>; - }; - - tifs-sram@1f0000 { - reg = <0x1f0000 0x10000>; - }; - - l3cache-sram@200000 { - reg = <0x200000 0x200000>; - }; - }; - - scm_conf: syscon@104000 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00 0x00104000 0x00 0x18000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00 0x00 0x00104000 0x18000>; - - usb_serdes_mux: mux-controller@0 { - compatible = "mmio-mux"; - reg = <0x0 0x4>; - #mux-control-cells = <1>; - mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ - }; - - phy_gmii_sel_cpsw: phy@34 { - compatible = "ti,am654-phy-gmii-sel"; - reg = <0x34 0x4>; - #phy-cells = <1>; - }; - - serdes_ln_ctrl: mux-controller@80 { - compatible = "mmio-mux"; - reg = <0x80 0x10>; - #mux-control-cells = <1>; - mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */ - <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */ - }; - - ehrpwm_tbclk: clock-controller@140 { - compatible = "ti,am654-ehrpwm-tbclk"; - reg = <0x140 0x18>; - #clock-cells = <1>; - }; - }; - - main_ehrpwm0: pwm@3000000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3000000 0x00 0x100>; - power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 0>, <&k3_clks 160 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm1: pwm@3010000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3010000 0x00 0x100>; - power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 1>, <&k3_clks 161 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm2: pwm@3020000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3020000 0x00 0x100>; - power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 2>, <&k3_clks 162 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm3: pwm@3030000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3030000 0x00 0x100>; - power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 3>, <&k3_clks 163 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm4: pwm@3040000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3040000 0x00 0x100>; - power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 4>, <&k3_clks 164 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm5: pwm@3050000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3050000 0x00 0x100>; - power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 5>, <&k3_clks 165 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - gic500: interrupt-controller@1800000 { - compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */ - <0x00 0x01900000 0x00 0x100000>, /* GICR */ - <0x00 0x6f000000 0x00 0x2000>, /* GICC */ - <0x00 0x6f010000 0x00 0x1000>, /* GICH */ - <0x00 0x6f020000 0x00 0x2000>; /* GICV */ - - /* vcpumntirq: virtual CPU interface maintenance interrupt */ - interrupts = ; - - gic_its: msi-controller@1820000 { - compatible = "arm,gic-v3-its"; - reg = <0x00 0x01820000 0x00 0x10000>; - socionext,synquacer-pre-its = <0x1000000 0x400000>; - msi-controller; - #msi-cells = <1>; - }; - }; - - main_gpio_intr: interrupt-controller@a00000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x00a00000 0x00 0x800>; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&sms>; - ti,sci-dev-id = <148>; - ti,interrupt-ranges = <8 392 56>; - }; - - main_pmx0: pinctrl@11c000 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x0 0x11c000 0x0 0x120>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ - main_timerio_input: pinctrl@104200 { - compatible = "pinctrl-single"; - reg = <0x00 0x104200 0x00 0x50>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x00000007>; - }; - - /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ - main_timerio_output: pinctrl@104280 { - compatible = "pinctrl-single"; - reg = <0x00 0x104280 0x00 0x20>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000001f>; - }; - - main_crypto: crypto@4e00000 { - compatible = "ti,j721e-sa2ul"; - reg = <0x00 0x04e00000 0x00 0x1200>; - power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; - - dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, - <&main_udmap 0x4a41>; - dma-names = "tx", "rx1", "rx2"; - - rng: rng@4e10000 { - compatible = "inside-secure,safexcel-eip76"; - reg = <0x00 0x04e10000 0x00 0x7d>; - interrupts = ; - }; - }; - - main_timer0: timer@2400000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2400000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 63 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 63 1>; - assigned-clock-parents = <&k3_clks 63 2>; - power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer1: timer@2410000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2410000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 64 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 64 1>; - assigned-clock-parents = <&k3_clks 64 2>; - power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer2: timer@2420000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2420000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 65 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 65 1>; - assigned-clock-parents = <&k3_clks 65 2>; - power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer3: timer@2430000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2430000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 66 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 66 1>; - assigned-clock-parents = <&k3_clks 66 2>; - power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer4: timer@2440000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2440000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 67 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 67 1>; - assigned-clock-parents = <&k3_clks 67 2>; - power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer5: timer@2450000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2450000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 68 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 68 1>; - assigned-clock-parents = <&k3_clks 68 2>; - power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer6: timer@2460000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2460000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 69 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 69 1>; - assigned-clock-parents = <&k3_clks 69 2>; - power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer7: timer@2470000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2470000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 70 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 70 1>; - assigned-clock-parents = <&k3_clks 70 2>; - power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer8: timer@2480000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2480000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 71 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 71 1>; - assigned-clock-parents = <&k3_clks 71 2>; - power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer9: timer@2490000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2490000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 72 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 72 1>; - assigned-clock-parents = <&k3_clks 72 2>; - power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer10: timer@24a0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24a0000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 73 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 73 1>; - assigned-clock-parents = <&k3_clks 73 2>; - power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer11: timer@24b0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24b0000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 74 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 74 1>; - assigned-clock-parents = <&k3_clks 74 2>; - power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer12: timer@24c0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24c0000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 75 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 75 1>; - assigned-clock-parents = <&k3_clks 75 2>; - power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer13: timer@24d0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24d0000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 76 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 76 1>; - assigned-clock-parents = <&k3_clks 76 2>; - power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer14: timer@24e0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24e0000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 77 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 77 1>; - assigned-clock-parents = <&k3_clks 77 2>; - power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer15: timer@24f0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24f0000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 78 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 78 1>; - assigned-clock-parents = <&k3_clks 78 2>; - power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer16: timer@2500000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2500000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 79 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 79 1>; - assigned-clock-parents = <&k3_clks 79 2>; - power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer17: timer@2510000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2510000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 80 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 80 1>; - assigned-clock-parents = <&k3_clks 80 2>; - power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer18: timer@2520000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2520000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 81 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 81 1>; - assigned-clock-parents = <&k3_clks 81 2>; - power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer19: timer@2530000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2530000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 82 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 82 1>; - assigned-clock-parents = <&k3_clks 82 2>; - power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_uart0: serial@2800000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02800000 0x00 0x200>; - interrupts = ; - current-speed = <115200>; - clocks = <&k3_clks 146 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_uart1: serial@2810000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02810000 0x00 0x200>; - interrupts = ; - current-speed = <115200>; - clocks = <&k3_clks 350 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_uart2: serial@2820000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02820000 0x00 0x200>; - interrupts = ; - current-speed = <115200>; - clocks = <&k3_clks 351 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_uart3: serial@2830000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02830000 0x00 0x200>; - interrupts = ; - current-speed = <115200>; - clocks = <&k3_clks 352 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_uart4: serial@2840000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02840000 0x00 0x200>; - interrupts = ; - current-speed = <115200>; - clocks = <&k3_clks 353 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_uart5: serial@2850000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02850000 0x00 0x200>; - interrupts = ; - current-speed = <115200>; - clocks = <&k3_clks 354 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_uart6: serial@2860000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02860000 0x00 0x200>; - interrupts = ; - current-speed = <115200>; - clocks = <&k3_clks 355 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_uart7: serial@2870000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02870000 0x00 0x200>; - interrupts = ; - current-speed = <115200>; - clocks = <&k3_clks 356 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_uart8: serial@2880000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02880000 0x00 0x200>; - interrupts = ; - current-speed = <115200>; - clocks = <&k3_clks 357 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_uart9: serial@2890000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02890000 0x00 0x200>; - interrupts = ; - current-speed = <115200>; - clocks = <&k3_clks 358 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_gpio0: gpio@600000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00600000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <145>, <146>, <147>, <148>, <149>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <66>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 111 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio2: gpio@610000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00610000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <154>, <155>, <156>, <157>, <158>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <66>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 112 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio4: gpio@620000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00620000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <163>, <164>, <165>, <166>, <167>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <66>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 113 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio6: gpio@630000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00630000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <172>, <173>, <174>, <175>, <176>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <66>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 114 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_i2c0: i2c@2000000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x02000000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 214 1>; - clock-names = "fck"; - power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; - }; - - main_i2c1: i2c@2010000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x02010000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 215 1>; - clock-names = "fck"; - power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c2: i2c@2020000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x02020000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 216 1>; - clock-names = "fck"; - power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c3: i2c@2030000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x02030000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 217 1>; - clock-names = "fck"; - power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c4: i2c@2040000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x02040000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 218 1>; - clock-names = "fck"; - power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c5: i2c@2050000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x02050000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 219 1>; - clock-names = "fck"; - power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c6: i2c@2060000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x02060000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 220 1>; - clock-names = "fck"; - power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_sdhci0: mmc@4f80000 { - compatible = "ti,j721e-sdhci-8bit"; - reg = <0x00 0x04f80000 0x00 0x1000>, - <0x00 0x04f88000 0x00 0x400>; - interrupts = ; - power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 98 7>, <&k3_clks 98 1>; - clock-names = "clk_ahb", "clk_xin"; - assigned-clocks = <&k3_clks 98 1>; - assigned-clock-parents = <&k3_clks 98 2>; - bus-width = <8>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-mmc-hs = <0x0>; - ti,otap-del-sel-ddr52 = <0x6>; - ti,otap-del-sel-hs200 = <0x8>; - ti,otap-del-sel-hs400 = <0x5>; - ti,itap-del-sel-legacy = <0x10>; - ti,itap-del-sel-mmc-hs = <0xa>; - ti,strobe-sel = <0x77>; - ti,clkbuf-sel = <0x7>; - ti,trm-icp = <0x8>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - dma-coherent; - status = "disabled"; - }; - - main_sdhci1: mmc@4fb0000 { - compatible = "ti,j721e-sdhci-4bit"; - reg = <0x00 0x04fb0000 0x00 0x1000>, - <0x00 0x04fb8000 0x00 0x400>; - interrupts = ; - power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 99 8>, <&k3_clks 99 1>; - clock-names = "clk_ahb", "clk_xin"; - assigned-clocks = <&k3_clks 99 1>; - assigned-clock-parents = <&k3_clks 99 2>; - bus-width = <4>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0xf>; - ti,otap-del-sel-sdr25 = <0xf>; - ti,otap-del-sel-sdr50 = <0xc>; - ti,otap-del-sel-sdr104 = <0x5>; - ti,otap-del-sel-ddr50 = <0xc>; - ti,itap-del-sel-legacy = <0x0>; - ti,itap-del-sel-sd-hs = <0x0>; - ti,itap-del-sel-sdr12 = <0x0>; - ti,itap-del-sel-sdr25 = <0x0>; - ti,clkbuf-sel = <0x7>; - ti,trm-icp = <0x8>; - dma-coherent; - /* Masking support for SDR104 capability */ - sdhci-caps-mask = <0x00000003 0x00000000>; - status = "disabled"; - }; - - main_navss: bus@30000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; - ti,sci-dev-id = <224>; - dma-coherent; - dma-ranges; - - main_navss_intr: interrupt-controller@310e0000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x310e0000 0x00 0x4000>; - ti,intr-trigger-type = <4>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&sms>; - ti,sci-dev-id = <227>; - ti,interrupt-ranges = <0 64 64>, - <64 448 64>, - <128 672 64>; - }; - - main_udmass_inta: msi-controller@33d00000 { - compatible = "ti,sci-inta"; - reg = <0x00 0x33d00000 0x00 0x100000>; - interrupt-controller; - #interrupt-cells = <0>; - interrupt-parent = <&main_navss_intr>; - msi-controller; - ti,sci = <&sms>; - ti,sci-dev-id = <265>; - ti,interrupt-ranges = <0 0 256>; - ti,unmapped-event-sources = <&main_bcdma_csi>; - }; - - secure_proxy_main: mailbox@32c00000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x00 0x32c00000 0x00 0x100000>, - <0x00 0x32400000 0x00 0x100000>, - <0x00 0x32800000 0x00 0x100000>; - interrupt-names = "rx_011"; - interrupts = ; - }; - - hwspinlock: spinlock@30e00000 { - compatible = "ti,am654-hwspinlock"; - reg = <0x00 0x30e00000 0x00 0x1000>; - #hwlock-cells = <1>; - }; - - mailbox0_cluster0: mailbox@31f80000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f80000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster1: mailbox@31f81000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f81000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster2: mailbox@31f82000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f82000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster3: mailbox@31f83000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f83000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster4: mailbox@31f84000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f84000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster5: mailbox@31f85000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f85000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster6: mailbox@31f86000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f86000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster7: mailbox@31f87000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f87000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster8: mailbox@31f88000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f88000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster9: mailbox@31f89000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f89000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster10: mailbox@31f8a000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f8a000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster11: mailbox@31f8b000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f8b000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster0: mailbox@31f90000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f90000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster1: mailbox@31f91000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f91000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster2: mailbox@31f92000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f92000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster3: mailbox@31f93000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f93000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster4: mailbox@31f94000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f94000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster5: mailbox@31f95000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f95000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster6: mailbox@31f96000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f96000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster7: mailbox@31f97000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f97000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster8: mailbox@31f98000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f98000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster9: mailbox@31f99000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f99000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster10: mailbox@31f9a000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f9a000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster11: mailbox@31f9b000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f9b000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - main_ringacc: ringacc@3c000000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x3c000000 0x0 0x400000>, - <0x0 0x38000000 0x0 0x400000>, - <0x0 0x31120000 0x0 0x100>, - <0x0 0x33000000 0x0 0x40000>, - <0x0 0x31080000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; - ti,num-rings = <1024>; - ti,sci-rm-range-gp-rings = <0x1>; - ti,sci = <&sms>; - ti,sci-dev-id = <259>; - msi-parent = <&main_udmass_inta>; - }; - - main_udmap: dma-controller@31150000 { - compatible = "ti,j721e-navss-main-udmap"; - reg = <0x0 0x31150000 0x0 0x100>, - <0x0 0x34000000 0x0 0x80000>, - <0x0 0x35000000 0x0 0x200000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&main_udmass_inta>; - #dma-cells = <1>; - - ti,sci = <&sms>; - ti,sci-dev-id = <263>; - ti,ringacc = <&main_ringacc>; - - ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ - <0x0f>, /* TX_HCHAN */ - <0x10>; /* TX_UHCHAN */ - ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ - <0x0b>, /* RX_HCHAN */ - <0x0c>; /* RX_UHCHAN */ - ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ - }; - - main_bcdma_csi: dma-controller@311a0000 { - compatible = "ti,j721s2-dmss-bcdma-csi"; - reg = <0x00 0x311a0000 0x00 0x100>, - <0x00 0x35d00000 0x00 0x20000>, - <0x00 0x35c00000 0x00 0x10000>, - <0x00 0x35e00000 0x00 0x80000>; - reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; - msi-parent = <&main_udmass_inta>; - #dma-cells = <3>; - ti,sci = <&sms>; - ti,sci-dev-id = <225>; - ti,sci-rm-range-rchan = <0x21>; - ti,sci-rm-range-tchan = <0x22>; - status = "disabled"; - }; - - cpts@310d0000 { - compatible = "ti,j721e-cpts"; - reg = <0x0 0x310d0000 0x0 0x400>; - reg-names = "cpts"; - clocks = <&k3_clks 226 5>; - clock-names = "cpts"; - assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */ - assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */ - interrupts-extended = <&main_navss_intr 391>; - interrupt-names = "cpts"; - ti,cpts-periodic-outputs = <6>; - ti,cpts-ext-ts-inputs = <8>; - }; - }; - - main_cpsw: ethernet@c200000 { - compatible = "ti,j721e-cpsw-nuss"; - reg = <0x00 0xc200000 0x00 0x200000>; - reg-names = "cpsw_nuss"; - ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>; - #address-cells = <2>; - #size-cells = <2>; - dma-coherent; - clocks = <&k3_clks 28 28>; - clock-names = "fck"; - power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>; - - dmas = <&main_udmap 0xc640>, - <&main_udmap 0xc641>, - <&main_udmap 0xc642>, - <&main_udmap 0xc643>, - <&main_udmap 0xc644>, - <&main_udmap 0xc645>, - <&main_udmap 0xc646>, - <&main_udmap 0xc647>, - <&main_udmap 0x4640>; - dma-names = "tx0", "tx1", "tx2", "tx3", - "tx4", "tx5", "tx6", "tx7", - "rx"; - - status = "disabled"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - main_cpsw_port1: port@1 { - reg = <1>; - ti,mac-only; - label = "port1"; - phys = <&phy_gmii_sel_cpsw 1>; - status = "disabled"; - }; - }; - - main_cpsw_mdio: mdio@f00 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x00 0xf00 0x00 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 28 28>; - clock-names = "fck"; - bus_freq = <1000000>; - status = "disabled"; - }; - - cpts@3d000 { - compatible = "ti,am65-cpts"; - reg = <0x00 0x3d000 0x00 0x400>; - clocks = <&k3_clks 28 3>; - clock-names = "cpts"; - interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cpts"; - ti,cpts-ext-ts-inputs = <4>; - ti,cpts-periodic-outputs = <2>; - }; - }; - - usbss0: cdns-usb@4104000 { - compatible = "ti,j721e-usb"; - reg = <0x00 0x04104000 0x00 0x100>; - clocks = <&k3_clks 360 16>, <&k3_clks 360 15>; - clock-names = "ref", "lpm"; - assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */ - assigned-clock-parents = <&k3_clks 360 17>; - power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-coherent; - - status = "disabled"; /* Needs pinmux */ - - usb0: usb@6000000 { - compatible = "cdns,usb3"; - reg = <0x00 0x06000000 0x00 0x10000>, - <0x00 0x06010000 0x00 0x10000>, - <0x00 0x06020000 0x00 0x10000>; - reg-names = "otg", "xhci", "dev"; - interrupts = , - , - ; - interrupt-names = "host", "peripheral", "otg"; - maximum-speed = "super-speed"; - dr_mode = "otg"; - }; - }; - - serdes_wiz0: wiz@5060000 { - compatible = "ti,j721s2-wiz-10g"; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>; - clock-names = "fck", "core_ref_clk", "ext_ref_clk"; - num-lanes = <4>; - #reset-cells = <1>; - #clock-cells = <1>; - ranges = <0x5060000 0x0 0x5060000 0x10000>; - - assigned-clocks = <&k3_clks 365 3>; - assigned-clock-parents = <&k3_clks 365 7>; - - serdes0: serdes@5060000 { - compatible = "ti,j721e-serdes-10g"; - reg = <0x05060000 0x00010000>; - reg-names = "torrent_phy"; - resets = <&serdes_wiz0 0>; - reset-names = "torrent_reset"; - clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, - <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; - clock-names = "refclk", "phy_en_refclk"; - assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, - <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, - <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; - assigned-clock-parents = <&k3_clks 365 3>, - <&k3_clks 365 3>, - <&k3_clks 365 3>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - - status = "disabled"; /* Needs lane config */ - }; - }; - - pcie1_rc: pcie@2910000 { - compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; - reg = <0x00 0x02910000 0x00 0x1000>, - <0x00 0x02917000 0x00 0x400>, - <0x00 0x0d800000 0x00 0x800000>, - <0x00 0x18000000 0x00 0x1000>; - reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - interrupt-names = "link_state"; - interrupts = ; - device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x074>; - max-link-speed = <3>; - num-lanes = <4>; - power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 276 41>; - clock-names = "fck"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - vendor-id = <0x104c>; - device-id = <0xb013>; - msi-map = <0x0 &gic_its 0x0 0x10000>; - dma-coherent; - ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, - <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; - dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */ - <0 0 0 2 &pcie1_intc 0>, /* INT B */ - <0 0 0 3 &pcie1_intc 0>, /* INT C */ - <0 0 0 4 &pcie1_intc 0>; /* INT D */ - - status = "disabled"; /* Needs gpio and serdes info */ - - pcie1_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic500>; - interrupts = ; - }; - }; - - main_mcan0: can@2701000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02701000 0x00 0x200>, - <0x00 0x02708000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 182 0>, <&k3_clks 182 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan1: can@2711000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02711000 0x00 0x200>, - <0x00 0x02718000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 183 0>, <&k3_clks 183 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan2: can@2721000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02721000 0x00 0x200>, - <0x00 0x02728000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 184 0>, <&k3_clks 184 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan3: can@2731000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02731000 0x00 0x200>, - <0x00 0x02738000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 185 0>, <&k3_clks 185 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan4: can@2741000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02741000 0x00 0x200>, - <0x00 0x02748000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 186 0>, <&k3_clks 186 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan5: can@2751000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02751000 0x00 0x200>, - <0x00 0x02758000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 187 0>, <&k3_clks 187 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan6: can@2761000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02761000 0x00 0x200>, - <0x00 0x02768000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 188 0>, <&k3_clks 188 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan7: can@2771000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02771000 0x00 0x200>, - <0x00 0x02778000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 189 0>, <&k3_clks 189 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan8: can@2781000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02781000 0x00 0x200>, - <0x00 0x02788000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 190 0>, <&k3_clks 190 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan9: can@2791000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02791000 0x00 0x200>, - <0x00 0x02798000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 191 0>, <&k3_clks 191 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan10: can@27a1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x027a1000 0x00 0x200>, - <0x00 0x027a8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 192 0>, <&k3_clks 192 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan11: can@27b1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x027b1000 0x00 0x200>, - <0x00 0x027b8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 193 0>, <&k3_clks 193 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan12: can@27c1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x027c1000 0x00 0x200>, - <0x00 0x027c8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 194 0>, <&k3_clks 194 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan13: can@27d1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x027d1000 0x00 0x200>, - <0x00 0x027d8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 195 0>, <&k3_clks 195 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan14: can@2681000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02681000 0x00 0x200>, - <0x00 0x02688000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 197 0>, <&k3_clks 197 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan15: can@2691000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02691000 0x00 0x200>, - <0x00 0x02698000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 199 0>, <&k3_clks 199 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan16: can@26a1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x026a1000 0x00 0x200>, - <0x00 0x026a8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 201 0>, <&k3_clks 201 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan17: can@26b1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x026b1000 0x00 0x200>, - <0x00 0x026b8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 206 0>, <&k3_clks 206 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_spi0: spi@2100000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02100000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 339 1>; - status = "disabled"; - }; - - main_spi1: spi@2110000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02110000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 340 1>; - status = "disabled"; - }; - - main_spi2: spi@2120000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02120000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 341 1>; - status = "disabled"; - }; - - main_spi3: spi@2130000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02130000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 342 1>; - status = "disabled"; - }; - - main_spi4: spi@2140000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02140000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 343 1>; - status = "disabled"; - }; - - main_spi5: spi@2150000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02150000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 344 1>; - status = "disabled"; - }; - - main_spi6: spi@2160000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02160000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 345 1>; - status = "disabled"; - }; - - main_spi7: spi@2170000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02170000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 346 1>; - status = "disabled"; - }; - - dss: dss@4a00000 { - compatible = "ti,j721e-dss"; - reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ - <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ - <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ - <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ - <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ - <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ - <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ - <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ - <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ - <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ - <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ - <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ - <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ - <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ - <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ - <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ - <0x00 0x04af0000 0x00 0x10000>; /* wb */ - reg-names = "common_m", "common_s0", - "common_s1", "common_s2", - "vidl1", "vidl2","vid1","vid2", - "ovr1", "ovr2", "ovr3", "ovr4", - "vp1", "vp2", "vp3", "vp4", - "wb"; - clocks = <&k3_clks 158 0>, - <&k3_clks 158 2>, - <&k3_clks 158 5>, - <&k3_clks 158 14>, - <&k3_clks 158 18>; - clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; - power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; - interrupts = , - , - , - ; - interrupt-names = "common_m", - "common_s0", - "common_s1", - "common_s2"; - status = "disabled"; - - dss_ports: ports { - }; - }; - - main_r5fss0: r5fss@5c00000 { - compatible = "ti,j721s2-r5fss"; - ti,cluster-mode = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5c00000 0x00 0x5c00000 0x20000>, - <0x5d00000 0x00 0x5d00000 0x20000>; - power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; - - main_r5fss0_core0: r5f@5c00000 { - compatible = "ti,j721s2-r5f"; - reg = <0x5c00000 0x00010000>, - <0x5c10000 0x00010000>; - reg-names = "atcm", "btcm"; - ti,sci = <&sms>; - ti,sci-dev-id = <279>; - ti,sci-proc-ids = <0x06 0xff>; - resets = <&k3_reset 279 1>; - firmware-name = "j721s2-main-r5f0_0-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - - main_r5fss0_core1: r5f@5d00000 { - compatible = "ti,j721s2-r5f"; - reg = <0x5d00000 0x00010000>, - <0x5d10000 0x00010000>; - reg-names = "atcm", "btcm"; - ti,sci = <&sms>; - ti,sci-dev-id = <280>; - ti,sci-proc-ids = <0x07 0xff>; - resets = <&k3_reset 280 1>; - firmware-name = "j721s2-main-r5f0_1-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - }; - - main_r5fss1: r5fss@5e00000 { - compatible = "ti,j721s2-r5fss"; - ti,cluster-mode = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5e00000 0x00 0x5e00000 0x20000>, - <0x5f00000 0x00 0x5f00000 0x20000>; - power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; - - main_r5fss1_core0: r5f@5e00000 { - compatible = "ti,j721s2-r5f"; - reg = <0x5e00000 0x00010000>, - <0x5e10000 0x00010000>; - reg-names = "atcm", "btcm"; - ti,sci = <&sms>; - ti,sci-dev-id = <281>; - ti,sci-proc-ids = <0x08 0xff>; - resets = <&k3_reset 281 1>; - firmware-name = "j721s2-main-r5f1_0-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - - main_r5fss1_core1: r5f@5f00000 { - compatible = "ti,j721s2-r5f"; - reg = <0x5f00000 0x00010000>, - <0x5f10000 0x00010000>; - reg-names = "atcm", "btcm"; - ti,sci = <&sms>; - ti,sci-dev-id = <282>; - ti,sci-proc-ids = <0x09 0xff>; - resets = <&k3_reset 282 1>; - firmware-name = "j721s2-main-r5f1_1-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - }; - - c71_0: dsp@64800000 { - compatible = "ti,j721s2-c71-dsp"; - reg = <0x00 0x64800000 0x00 0x00080000>, - <0x00 0x64e00000 0x00 0x0000c000>; - reg-names = "l2sram", "l1dram"; - ti,sci = <&sms>; - ti,sci-dev-id = <8>; - ti,sci-proc-ids = <0x30 0xff>; - resets = <&k3_reset 8 1>; - firmware-name = "j721s2-c71_0-fw"; - status = "disabled"; - }; - - c71_1: dsp@65800000 { - compatible = "ti,j721s2-c71-dsp"; - reg = <0x00 0x65800000 0x00 0x00080000>, - <0x00 0x65e00000 0x00 0x0000c000>; - reg-names = "l2sram", "l1dram"; - ti,sci = <&sms>; - ti,sci-dev-id = <11>; - ti,sci-proc-ids = <0x31 0xff>; - resets = <&k3_reset 11 1>; - firmware-name = "j721s2-c71_1-fw"; - status = "disabled"; - }; - - main_esm: esm@700000 { - compatible = "ti,j721e-esm"; - reg = <0x00 0x700000 0x00 0x1000>; - ti,esm-pins = <688>, <689>; - bootph-pre-ram; - }; - - watchdog0: watchdog@2200000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x2200000 0x00 0x100>; - clocks = <&k3_clks 286 1>; - power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 286 1>; - assigned-clock-parents = <&k3_clks 286 5>; - }; - - watchdog1: watchdog@2210000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x2210000 0x00 0x100>; - clocks = <&k3_clks 287 1>; - power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 287 1>; - assigned-clock-parents = <&k3_clks 287 5>; - }; - - /* - * The following RTI instances are coupled with MCU R5Fs, c7x and - * GPU so keeping them reserved as these will be used by their - * respective firmware - */ - watchdog2: watchdog@22f0000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x22f0000 0x00 0x100>; - clocks = <&k3_clks 290 1>; - power-domains = <&k3_pds 290 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 290 1>; - assigned-clock-parents = <&k3_clks 290 5>; - /* reserved for GPU */ - status = "reserved"; - }; - - watchdog3: watchdog@2300000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x2300000 0x00 0x100>; - clocks = <&k3_clks 288 1>; - power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 288 1>; - assigned-clock-parents = <&k3_clks 288 5>; - /* reserved for C7X_0 */ - status = "reserved"; - }; - - watchdog4: watchdog@2310000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x2310000 0x00 0x100>; - clocks = <&k3_clks 289 1>; - power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 289 1>; - assigned-clock-parents = <&k3_clks 289 5>; - /* reserved for C7X_1 */ - status = "reserved"; - }; - - watchdog5: watchdog@23c0000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x23c0000 0x00 0x100>; - clocks = <&k3_clks 291 1>; - power-domains = <&k3_pds 291 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 291 1>; - assigned-clock-parents = <&k3_clks 291 5>; - /* reserved for MAIN_R5F0_0 */ - status = "reserved"; - }; - - watchdog6: watchdog@23d0000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x23d0000 0x00 0x100>; - clocks = <&k3_clks 292 1>; - power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 292 1>; - assigned-clock-parents = <&k3_clks 292 5>; - /* reserved for MAIN_R5F0_1 */ - status = "reserved"; - }; - - watchdog7: watchdog@23e0000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x23e0000 0x00 0x100>; - clocks = <&k3_clks 293 1>; - power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 293 1>; - assigned-clock-parents = <&k3_clks 293 5>; - /* reserved for MAIN_R5F1_0 */ - status = "reserved"; - }; - - watchdog8: watchdog@23f0000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x23f0000 0x00 0x100>; - clocks = <&k3_clks 294 1>; - power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 294 1>; - assigned-clock-parents = <&k3_clks 294 5>; - /* reserved for MAIN_R5F1_1 */ - status = "reserved"; - }; -}; diff --git a/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi deleted file mode 100644 index 7254f3bd363..00000000000 --- a/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi +++ /dev/null @@ -1,738 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals - * - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&cbass_mcu_wakeup { - sms: system-controller@44083000 { - compatible = "ti,k2g-sci"; - ti,host-id = <12>; - - mbox-names = "rx", "tx"; - - mboxes = <&secure_proxy_main 11>, - <&secure_proxy_main 13>; - - reg-names = "debug_messages"; - reg = <0x00 0x44083000 0x00 0x1000>; - - k3_pds: power-controller { - compatible = "ti,sci-pm-domain"; - #power-domain-cells = <2>; - }; - - k3_clks: clock-controller { - compatible = "ti,k2g-sci-clk"; - #clock-cells = <2>; - }; - - k3_reset: reset-controller { - compatible = "ti,sci-reset"; - #reset-cells = <2>; - }; - }; - - chipid@43000014 { - compatible = "ti,am654-chipid"; - reg = <0x00 0x43000014 0x00 0x4>; - }; - - secure_proxy_sa3: mailbox@43600000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x00 0x43600000 0x00 0x10000>, - <0x00 0x44880000 0x00 0x20000>, - <0x00 0x44860000 0x00 0x20000>; - /* - * Marked Disabled: - * Node is incomplete as it is meant for bootloaders and - * firmware on non-MPU processors - */ - status = "disabled"; - }; - - mcu_ram: sram@41c00000 { - compatible = "mmio-sram"; - reg = <0x00 0x41c00000 0x00 0x100000>; - ranges = <0x00 0x00 0x41c00000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - wkup_pmx0: pinctrl@4301c000 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c000 0x00 0x034>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - wkup_pmx1: pinctrl@4301c038 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c038 0x00 0x02C>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - wkup_pmx2: pinctrl@4301c068 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c068 0x00 0x120>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - wkup_pmx3: pinctrl@4301c190 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c190 0x00 0x004>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ - mcu_timerio_input: pinctrl@40f04200 { - compatible = "pinctrl-single"; - reg = <0x00 0x40f04200 0x00 0x28>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000f>; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ - mcu_timerio_output: pinctrl@40f04280 { - compatible = "pinctrl-single"; - reg = <0x00 0x40f04280 0x00 0x28>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000f>; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - wkup_gpio_intr: interrupt-controller@42200000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x42200000 0x00 0x400>; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&sms>; - ti,sci-dev-id = <125>; - ti,interrupt-ranges = <16 960 16>; - }; - - mcu_conf: syscon@40f00000 { - compatible = "syscon", "simple-mfd"; - reg = <0x0 0x40f00000 0x0 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x40f00000 0x20000>; - - phy_gmii_sel: phy@4040 { - compatible = "ti,am654-phy-gmii-sel"; - reg = <0x4040 0x4>; - #phy-cells = <1>; - }; - - }; - - mcu_timer0: timer@40400000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40400000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 35 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 35 1>; - assigned-clock-parents = <&k3_clks 35 2>; - power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer1: timer@40410000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40410000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 83 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 83 1>; - assigned-clock-parents = <&k3_clks 83 2>; - power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer2: timer@40420000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40420000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 84 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 84 1>; - assigned-clock-parents = <&k3_clks 84 2>; - power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer3: timer@40430000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40430000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 85 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 85 1>; - assigned-clock-parents = <&k3_clks 85 2>; - power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer4: timer@40440000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40440000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 86 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 86 1>; - assigned-clock-parents = <&k3_clks 86 2>; - power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer5: timer@40450000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40450000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 87 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 87 1>; - assigned-clock-parents = <&k3_clks 87 2>; - power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer6: timer@40460000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40460000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 88 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 88 1>; - assigned-clock-parents = <&k3_clks 88 2>; - power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer7: timer@40470000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40470000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 89 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 89 1>; - assigned-clock-parents = <&k3_clks 89 2>; - power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer8: timer@40480000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40480000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 90 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 90 1>; - assigned-clock-parents = <&k3_clks 90 2>; - power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer9: timer@40490000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40490000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 91 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 91 1>; - assigned-clock-parents = <&k3_clks 91 2>; - power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - wkup_uart0: serial@42300000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x42300000 0x00 0x200>; - interrupts = ; - current-speed = <115200>; - clocks = <&k3_clks 359 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcu_uart0: serial@40a00000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x40a00000 0x00 0x200>; - interrupts = ; - current-speed = <115200>; - clocks = <&k3_clks 149 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - wkup_gpio0: gpio@42110000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x42110000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&wkup_gpio_intr>; - interrupts = <103>, <104>, <105>, <106>, <107>, <108>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <89>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 115 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - wkup_gpio1: gpio@42100000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x42100000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&wkup_gpio_intr>; - interrupts = <112>, <113>, <114>, <115>, <116>, <117>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <89>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 116 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - wkup_i2c0: i2c@42120000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x42120000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 223 1>; - clock-names = "fck"; - power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcu_i2c0: i2c@40b00000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x40b00000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 221 1>; - clock-names = "fck"; - power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcu_i2c1: i2c@40b10000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x40b10000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 222 1>; - clock-names = "fck"; - power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcu_mcan0: can@40528000 { - compatible = "bosch,m_can"; - reg = <0x00 0x40528000 0x00 0x200>, - <0x00 0x40500000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 207 0>, <&k3_clks 207 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - mcu_mcan1: can@40568000 { - compatible = "bosch,m_can"; - reg = <0x00 0x40568000 0x00 0x200>, - <0x00 0x40540000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 208 0>, <&k3_clks 208 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - mcu_spi0: spi@40300000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x040300000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 347 0>; - status = "disabled"; - }; - - mcu_spi1: spi@40310000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x040310000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 348 0>; - status = "disabled"; - }; - - mcu_spi2: spi@40320000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x040320000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 349 0>; - status = "disabled"; - }; - - mcu_navss: bus@28380000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; - dma-coherent; - dma-ranges; - - ti,sci-dev-id = <267>; - - mcu_ringacc: ringacc@2b800000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x2b800000 0x0 0x400000>, - <0x0 0x2b000000 0x0 0x400000>, - <0x0 0x28590000 0x0 0x100>, - <0x0 0x2a500000 0x0 0x40000>, - <0x0 0x28440000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; - ti,num-rings = <286>; - ti,sci-rm-range-gp-rings = <0x1>; - ti,sci = <&sms>; - ti,sci-dev-id = <272>; - msi-parent = <&main_udmass_inta>; - }; - - mcu_udmap: dma-controller@285c0000 { - compatible = "ti,j721e-navss-mcu-udmap"; - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x2aa00000 0x0 0x40000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&main_udmass_inta>; - #dma-cells = <1>; - - ti,sci = <&sms>; - ti,sci-dev-id = <273>; - ti,ringacc = <&mcu_ringacc>; - ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ - <0x0f>; /* TX_HCHAN */ - ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ - <0x0b>; /* RX_HCHAN */ - ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ - }; - }; - - secure_proxy_mcu: mailbox@2a480000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x00 0x2a480000 0x00 0x80000>, - <0x00 0x2a380000 0x00 0x80000>, - <0x00 0x2a400000 0x00 0x80000>; - /* - * Marked Disabled: - * Node is incomplete as it is meant for bootloaders and - * firmware on non-MPU processors - */ - status = "disabled"; - }; - - mcu_cpsw: ethernet@46000000 { - compatible = "ti,j721e-cpsw-nuss"; - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x46000000 0x0 0x200000>; - reg-names = "cpsw_nuss"; - ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; - dma-coherent; - clocks = <&k3_clks 29 28>; - clock-names = "fck"; - power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>; - - dmas = <&mcu_udmap 0xf000>, - <&mcu_udmap 0xf001>, - <&mcu_udmap 0xf002>, - <&mcu_udmap 0xf003>, - <&mcu_udmap 0xf004>, - <&mcu_udmap 0xf005>, - <&mcu_udmap 0xf006>, - <&mcu_udmap 0xf007>, - <&mcu_udmap 0x7000>; - dma-names = "tx0", "tx1", "tx2", "tx3", - "tx4", "tx5", "tx6", "tx7", - "rx"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - cpsw_port1: port@1 { - reg = <1>; - ti,mac-only; - label = "port1"; - ti,syscon-efuse = <&mcu_conf 0x200>; - phys = <&phy_gmii_sel 1>; - }; - }; - - davinci_mdio: mdio@f00 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x0 0xf00 0x0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 29 28>; - clock-names = "fck"; - bus_freq = <1000000>; - }; - - cpts@3d000 { - compatible = "ti,am65-cpts"; - reg = <0x0 0x3d000 0x0 0x400>; - clocks = <&k3_clks 29 3>; - clock-names = "cpts"; - assigned-clocks = <&k3_clks 29 3>; /* CPTS_RFT_CLK */ - assigned-clock-parents = <&k3_clks 29 5>; /* MAIN_0_HSDIVOUT6_CLK */ - interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cpts"; - ti,cpts-ext-ts-inputs = <4>; - ti,cpts-periodic-outputs = <2>; - }; - }; - - tscadc0: tscadc@40200000 { - compatible = "ti,am3359-tscadc"; - reg = <0x00 0x40200000 0x00 0x1000>; - interrupts = ; - power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 0 0>; - assigned-clocks = <&k3_clks 0 2>; - assigned-clock-rates = <60000000>; - clock-names = "fck"; - dmas = <&main_udmap 0x7400>, - <&main_udmap 0x7401>; - dma-names = "fifo0", "fifo1"; - status = "disabled"; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am3359-adc"; - }; - }; - - tscadc1: tscadc@40210000 { - compatible = "ti,am3359-tscadc"; - reg = <0x00 0x40210000 0x00 0x1000>; - interrupts = ; - power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 1 0>; - assigned-clocks = <&k3_clks 1 2>; - assigned-clock-rates = <60000000>; - clock-names = "fck"; - dmas = <&main_udmap 0x7402>, - <&main_udmap 0x7403>; - dma-names = "fifo0", "fifo1"; - status = "disabled"; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am3359-adc"; - }; - }; - - fss: bus@47000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; - - ospi0: spi@47040000 { - compatible = "ti,am654-ospi", "cdns,qspi-nor"; - reg = <0x00 0x47040000 0x00 0x100>, - <0x05 0x00000000 0x01 0x00000000>; - interrupts = ; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x0>; - clocks = <&k3_clks 109 5>; - assigned-clocks = <&k3_clks 109 5>; - assigned-clock-parents = <&k3_clks 109 7>; - assigned-clock-rates = <166666666>; - power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; /* Needs pinmux */ - }; - - ospi1: spi@47050000 { - compatible = "ti,am654-ospi", "cdns,qspi-nor"; - reg = <0x00 0x47050000 0x00 0x100>, - <0x07 0x00000000 0x01 0x00000000>; - interrupts = ; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x0>; - clocks = <&k3_clks 110 5>; - power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; /* Needs pinmux */ - }; - }; - - wkup_vtm0: temperature-sensor@42040000 { - compatible = "ti,j7200-vtm"; - reg = <0x00 0x42040000 0x0 0x350>, - <0x00 0x42050000 0x0 0x350>; - power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>; - #thermal-sensor-cells = <1>; - }; - - mcu_r5fss0: r5fss@41000000 { - compatible = "ti,j721s2-r5fss"; - ti,cluster-mode = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x41000000 0x00 0x41000000 0x20000>, - <0x41400000 0x00 0x41400000 0x20000>; - power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; - - mcu_r5fss0_core0: r5f@41000000 { - compatible = "ti,j721s2-r5f"; - reg = <0x41000000 0x00010000>, - <0x41010000 0x00010000>; - reg-names = "atcm", "btcm"; - ti,sci = <&sms>; - ti,sci-dev-id = <284>; - ti,sci-proc-ids = <0x01 0xff>; - resets = <&k3_reset 284 1>; - firmware-name = "j721s2-mcu-r5f0_0-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - - mcu_r5fss0_core1: r5f@41400000 { - compatible = "ti,j721s2-r5f"; - reg = <0x41400000 0x00010000>, - <0x41410000 0x00010000>; - reg-names = "atcm", "btcm"; - ti,sci = <&sms>; - ti,sci-dev-id = <285>; - ti,sci-proc-ids = <0x02 0xff>; - resets = <&k3_reset 285 1>; - firmware-name = "j721s2-mcu-r5f0_1-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - }; - - mcu_esm: esm@40800000 { - compatible = "ti,j721e-esm"; - reg = <0x00 0x40800000 0x00 0x1000>; - ti,esm-pins = <95>; - bootph-pre-ram; - }; - - wkup_esm: esm@42080000 { - compatible = "ti,j721e-esm"; - reg = <0x00 0x42080000 0x00 0x1000>; - ti,esm-pins = <63>; - bootph-pre-ram; - }; - - /* - * The 2 RTI instances are couple with MCU R5Fs so keeping them - * reserved as these will be used by their respective firmware - */ - mcu_watchdog0: watchdog@40600000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x40600000 0x00 0x100>; - clocks = <&k3_clks 295 1>; - power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 295 1>; - assigned-clock-parents = <&k3_clks 295 5>; - /* reserved for MCU_R5F0_0 */ - status = "reserved"; - }; - - mcu_watchdog1: watchdog@40610000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x40610000 0x00 0x100>; - clocks = <&k3_clks 296 1>; - power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 296 1>; - assigned-clock-parents = <&k3_clks 296 5>; - /* reserved for MCU_R5F0_1 */ - status = "reserved"; - }; -}; diff --git a/arch/arm/dts/k3-j721s2-som-p0.dtsi b/arch/arm/dts/k3-j721s2-som-p0.dtsi deleted file mode 100644 index dcad372620b..00000000000 --- a/arch/arm/dts/k3-j721s2-som-p0.dtsi +++ /dev/null @@ -1,361 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * SoM: https://www.ti.com/lit/zip/sprr439 - * - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; - -#include "k3-j721s2.dtsi" -#include - -/ { - memory@80000000 { - device_type = "memory"; - /* 16 GB RAM */ - reg = <0x00 0x80000000 0x00 0x80000000>, - <0x08 0x80000000 0x03 0x80000000>; - }; - - /* Reserving memory regions still pending */ - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; - alignment = <0x1000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0100000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c71_1_dma_memory_region: c71-dma-memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c71_1_memory_region: c71-memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a8000000 { - reg = <0x00 0xa8000000 0x00 0x01c00000>; - alignment = <0x1000>; - no-map; - }; - }; - - mux0: mux-controller { - compatible = "gpio-mux"; - #mux-state-cells = <1>; - mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>; - }; - - mux1: mux-controller { - compatible = "gpio-mux"; - #mux-state-cells = <1>; - mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>; - }; - - transceiver0: can-phy0 { - /* standby pin has been grounded by default */ - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - }; -}; - -&wkup_pmx0 { - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ - J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ - J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ - J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ - J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ - J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ - J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ - J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ - J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ - J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ - J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ - J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ - >; - }; -}; - -&wkup_pmx2 { - wkup_i2c0_pins_default: wkup-i2c0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ - J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ - >; - }; -}; - -&main_pmx0 { - main_i2c0_pins_default: main-i2c0-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */ - J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */ - >; - }; - - main_mcan16_pins_default: main-mcan16-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */ - J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */ - >; - }; -}; - -&wkup_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <400000>; - - eeprom@50 { - /* CAV24C256WE-GT3 */ - compatible = "atmel,24c256"; - reg = <0x50>; - }; -}; - -&main_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - exp_som: gpio@21 { - compatible = "ti,tca6408"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0", - "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1", - "GPIO_RGMII1_RST", "GPIO_eDP_ENABLE", - "GPIO_LIN_EN", "CAN_STB"; - }; -}; - -&main_mcan16 { - status = "okay"; - pinctrl-0 = <&main_mcan16_pins_default>; - pinctrl-names = "default"; - phys = <&transceiver0>; -}; - -&ospi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <8>; - spi-rx-bus-width = <8>; - spi-max-frequency = <25000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <4>; - }; -}; - -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c71_1: mbox-c71-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; - -&c71_1 { - status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>; - memory-region = <&c71_1_dma_memory_region>, - <&c71_1_memory_region>; -}; diff --git a/arch/arm/dts/k3-j721s2-thermal.dtsi b/arch/arm/dts/k3-j721s2-thermal.dtsi deleted file mode 100644 index f7b1a15b8fa..00000000000 --- a/arch/arm/dts/k3-j721s2-thermal.dtsi +++ /dev/null @@ -1,101 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include - -wkup0_thermal: wkup0-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 0>; - - trips { - wkup0_crit: wkup0-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; - -wkup1_thermal: wkup1-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 1>; - - trips { - wkup1_crit: wkup1-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; - -main0_thermal: main0-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 2>; - - trips { - main0_crit: main0-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; - -main1_thermal: main1-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 3>; - - trips { - main1_crit: main1-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; - -main2_thermal: main2-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 4>; - - trips { - main2_crit: main2-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; - -main3_thermal: main3-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 5>; - - trips { - main3_crit: main3-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; - -main4_thermal: main4-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 6>; - - trips { - main4_crit: main4-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; diff --git a/arch/arm/dts/k3-j721s2.dtsi b/arch/arm/dts/k3-j721s2.dtsi deleted file mode 100644 index 1f636acd4ee..00000000000 --- a/arch/arm/dts/k3-j721s2.dtsi +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J721S2 SoC Family - * - * TRM (SPRUJ28 NOVEMBER 2021): https://www.ti.com/lit/pdf/spruj28 - * - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ - * - */ - -#include -#include -#include - -#include "k3-pinctrl.h" - -/ { - - model = "Texas Instruments K3 J721S2 SoC"; - compatible = "ti,j721s2"; - interrupt-parent = <&gic500>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu-map { - cluster0: cluster0 { - core0 { - cpu = <&cpu0>; - }; - - core1 { - cpu = <&cpu1>; - }; - }; - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a72"; - reg = <0x000>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a72"; - reg = <0x001>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_0>; - }; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - next-level-cache = <&msmc_l3>; - }; - - msmc_l3: l3-cache0 { - compatible = "cache"; - cache-level = <3>; - cache-unified; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - - psci: psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - }; - - a72_timer0: timer-cl0-cpu0 { - compatible = "arm,armv8-timer"; - interrupts = , /* cntpsirq */ - , /* cntpnsirq */ - , /* cntvirq */ - ; /* cnthpirq */ - - }; - - pmu: pmu { - compatible = "arm,cortex-a72-pmu"; - /* Recommendation from GIC500 TRM Table A.3 */ - interrupts = ; - }; - - cbass_main: bus@100000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ - <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ - <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ - <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe Core*/ - <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ - <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */ - <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */ - <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ - <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */ - <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ - <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ - <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ - - /* MCUSS_WKUP Range */ - <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, - <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; - - cbass_mcu_wakeup: bus@28380000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ - <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ - - }; - - }; - - thermal_zones: thermal-zones { - #include "k3-j721s2-thermal.dtsi" - }; -}; - -/* Now include peripherals from each bus segment */ -#include "k3-j721s2-main.dtsi" -#include "k3-j721s2-mcu-wakeup.dtsi" diff --git a/board/ti/j721s2/MAINTAINERS b/board/ti/j721s2/MAINTAINERS index 6cf90014a09..e31f2acea7b 100644 --- a/board/ti/j721s2/MAINTAINERS +++ b/board/ti/j721s2/MAINTAINERS @@ -9,18 +9,10 @@ F: configs/j721s2_evm_r5_defconfig F: configs/j721s2_evm_a72_defconfig F: configs/am68_sk_r5_defconfig F: configs/am68_sk_a72_defconfig -F: arch/arm/dts/k3-j721s2.dtsi -F: arch/arm/dts/k3-j721s2-main.dtsi -F: arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi -F: arch/arm/dts/k3-j721s2-thermal.dtsi -F: arch/arm/dts/k3-j721s2-som-p0.dtsi -F: arch/arm/dts/k3-j721s2-common-proc-board.dts F: arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi F: arch/arm/dts/k3-j721s2-r5.dtsi F: arch/arm/dts/k3-j721s2-r5-common-proc-board.dts F: arch/arm/dts/k3-j721s2-ddr.dtsi F: arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi -F: arch/arm/dts/k3-am68-sk-som.dtsi -F: arch/arm/dts/k3-am68-sk-base-board.dts F: arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi F: arch/arm/dts/k3-am68-sk-r5-base-board.dts diff --git a/configs/am68_sk_a72_defconfig b/configs/am68_sk_a72_defconfig index d477f9e4e98..e750614ba30 100644 --- a/configs/am68_sk_a72_defconfig +++ b/configs/am68_sk_a72_defconfig @@ -5,6 +5,6 @@ CONFIG_ARCH_K3=y CONFIG_SOC_K3_J721S2=y CONFIG_TARGET_J721S2_A72_EVM=y -CONFIG_DEFAULT_DEVICE_TREE="k3-am68-sk-base-board" -CONFIG_SPL_OF_LIST="k3-am68-sk-base-board" -CONFIG_OF_LIST="k3-am68-sk-base-board" +CONFIG_SPL_OF_LIST="ti/k3-am68-sk-base-board" +CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am68-sk-base-board" +CONFIG_OF_LIST="ti/k3-am68-sk-base-board" diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig index dd86b5c0509..5ed8d00662e 100644 --- a/configs/j721s2_evm_a72_defconfig +++ b/configs/j721s2_evm_a72_defconfig @@ -13,7 +13,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 CONFIG_ENV_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="k3-j721s2-common-proc-board" +CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j721s2-common-proc-board" CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y @@ -84,8 +84,9 @@ CONFIG_CMD_UBI=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="k3-j721s2-common-proc-board" +CONFIG_OF_LIST="ti/k3-j721s2-common-proc-board" CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_OF_UPSTREAM=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y From 31cf22099bc3243ba2779d55fba0282bbcf29ddf Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 10 May 2024 19:35:51 +0000 Subject: [PATCH 031/383] pinctrl: Fix pinctrl_gpio_get_pinctrl_and_offset() Linux kernel Documentation/devicetree/bindings/gpio/gpio.txt define the format of the gpio-ranges prop as: The format is: <[pin controller phandle], [GPIO controller offset], [pin controller offset], [number of pins]>; Example: gpio-ranges = <&foo 0 20 10>, <&bar 10 50 20>; This means: - pins 20..29 on pin controller "foo" is mapped to GPIO line 0..9 and - pins 50..69 on pin controller "bar" is mapped to GPIO line 10..29 For this example, a call to pinctrl_gpio_get_pinctrl_and_offset() using offset 10 incorrectly return pin controller "foo" instead of "bar". Fix this by using an exclusive range check. Fixes: d0bb00adccb8 ("pinctrl: fix pinctrl_gpio_get_pinctrl_and_offset for gpio-ranges array") Signed-off-by: Jonas Karlman Reviewed-by: Quanyang Wang --- drivers/pinctrl/pinctrl-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c index d9bda7494e2..d9c76898a96 100644 --- a/drivers/pinctrl/pinctrl-uclass.c +++ b/drivers/pinctrl/pinctrl-uclass.c @@ -209,7 +209,7 @@ pinctrl_gpio_get_pinctrl_and_offset(struct udevice *dev, unsigned offset, pfc_base = args.args[1]; pfc_pins = args.args[2]; - if (offset >= gpio_offset && offset <= gpio_offset + pfc_pins) + if (offset >= gpio_offset && offset < gpio_offset + pfc_pins) break; } From a4247055d1926e2f3ee56f6ed3e55ebb9c0cf426 Mon Sep 17 00:00:00 2001 From: Jim Liu Date: Mon, 13 May 2024 15:25:32 +0800 Subject: [PATCH 032/383] phy: Use dt-bindig definations for npcm usb phy Use dt-binding definations for the phy switch connection. It declares the target usb controller it is connected to. Signed-off-by: Jim Liu --- drivers/phy/phy-npcm-usb.c | 27 ++++++++++----------------- 1 file changed, 10 insertions(+), 17 deletions(-) diff --git a/drivers/phy/phy-npcm-usb.c b/drivers/phy/phy-npcm-usb.c index 028fedf92dc..2cca0f4a054 100644 --- a/drivers/phy/phy-npcm-usb.c +++ b/drivers/phy/phy-npcm-usb.c @@ -11,6 +11,7 @@ #include #include #include +#include /* GCR Register Offsets */ #define GCR_INTCR3 0x9C @@ -31,14 +32,6 @@ #define USBPHY3SW_HOST2 FIELD_PREP(USBPHY3SW, 1) #define USBPHY3SW_DEV8_PHY3 FIELD_PREP(USBPHY3SW, 3) -enum controller_id { - UDC0_7, - UDC8, - UDC9, - USBH1, - USBH2, -}; - enum phy_id { PHY1 = 1, PHY2, @@ -46,13 +39,13 @@ enum phy_id { }; /* Phy Switch Settings */ -#define USBDPHY1 ((PHY1 << 8) | UDC0_7) /* Connect UDC0~7 to PHY1 */ -#define USBD8PHY1 ((PHY1 << 8) | UDC8) /* Connect UDC8 to PHY1 */ -#define USBD9PHY1 ((PHY1 << 8) | UDC9) /* Connect UDC9 to PHY1 */ -#define USBD9PHY2 ((PHY2 << 8) | UDC9) /* Connect UDC9 to PHY2 */ -#define USBH1PHY2 ((PHY2 << 8) | USBH1) /* Connect USBH1 to PHY2 */ -#define USBD8PHY3 ((PHY3 << 8) | UDC8) /* Connect UDC8 to PHY3 */ -#define USBH2PHY3 ((PHY3 << 8) | USBH2) /* Connect USBH2 to PHY3 */ +#define USBDPHY1 ((PHY1 << 8) | NPCM_UDC0_7) /* Connect UDC0~7 to PHY1 */ +#define USBD8PHY1 ((PHY1 << 8) | NPCM_UDC8) /* Connect UDC8 to PHY1 */ +#define USBD9PHY1 ((PHY1 << 8) | NPCM_UDC9) /* Connect UDC9 to PHY1 */ +#define USBD9PHY2 ((PHY2 << 8) | NPCM_UDC9) /* Connect UDC9 to PHY2 */ +#define USBH1PHY2 ((PHY2 << 8) | NPCM_USBH1) /* Connect USBH1 to PHY2 */ +#define USBD8PHY3 ((PHY3 << 8) | NPCM_UDC8) /* Connect UDC8 to PHY3 */ +#define USBH2PHY3 ((PHY3 << 8) | NPCM_USBH2) /* Connect USBH2 to PHY3 */ struct npcm_usbphy { struct regmap *syscon; @@ -152,12 +145,12 @@ static int npcm_usb_phy_exit(struct phy *phy) return 0; } -static int npcm_usb_phy_xlate(struct phy *phy, struct ofnode_phandle_args *args) +static int npcm_usb_phy_xlate(struct phy *phy, struct ofnode_phandle_args *args) { struct npcm_usbphy *priv = dev_get_priv(phy->dev); u16 phy_switch; - if (args->args_count < 1 || args->args[0] > USBH2) + if (args->args_count < 1 || args->args[0] > NPCM_MAX_USB_CTRL_ID) return -EINVAL; phy_switch = (priv->id << 8) | args->args[0]; From 00761e6acd347f98bc10148ad0215c0e9f6684a9 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Mon, 13 May 2024 15:13:54 +0300 Subject: [PATCH 033/383] arm: dts: k3-am62*: sync with Linux v6.9 Update k3-am62 DT files from Linux v6.9 Signed-off-by: Roger Quadros --- arch/arm/dts/k3-am62-main.dtsi | 126 ++++++++++++++--- arch/arm/dts/k3-am62-mcu.dtsi | 4 +- arch/arm/dts/k3-am62-thermal.dtsi | 5 +- arch/arm/dts/k3-am62-wakeup.dtsi | 38 +++-- arch/arm/dts/k3-am62.dtsi | 4 +- arch/arm/dts/k3-am625-beagleplay.dts | 58 +++----- arch/arm/dts/k3-am625-sk.dts | 4 +- arch/arm/dts/k3-am625.dtsi | 4 +- arch/arm/dts/k3-am62a-main.dtsi | 201 +++++++++++++++++++++++++-- arch/arm/dts/k3-am62a-mcu.dtsi | 4 +- arch/arm/dts/k3-am62a-thermal.dtsi | 5 +- arch/arm/dts/k3-am62a-wakeup.dtsi | 4 +- arch/arm/dts/k3-am62a.dtsi | 4 +- arch/arm/dts/k3-am62a7-sk.dts | 162 ++++++++++++++++++++- arch/arm/dts/k3-am62a7.dtsi | 4 +- arch/arm/dts/k3-am62x-sk-common.dtsi | 24 +++- 16 files changed, 552 insertions(+), 99 deletions(-) diff --git a/arch/arm/dts/k3-am62-main.dtsi b/arch/arm/dts/k3-am62-main.dtsi index e5c64c86d1d..e9cffca073e 100644 --- a/arch/arm/dts/k3-am62-main.dtsi +++ b/arch/arm/dts/k3-am62-main.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM625 SoC Family Main Domain peripherals * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_main { @@ -42,9 +42,8 @@ }; }; - main_conf: syscon@100000 { - compatible = "syscon", "simple-mfd"; - reg = <0x00 0x00100000 0x00 0x20000>; + main_conf: bus@100000 { + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x00 0x00100000 0x20000>; @@ -121,8 +120,13 @@ <0x00 0x4c000000 0x00 0x20000>, <0x00 0x4a820000 0x00 0x20000>, <0x00 0x4aa40000 0x00 0x20000>, - <0x00 0x4bc00000 0x00 0x100000>; - reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; + <0x00 0x4bc00000 0x00 0x100000>, + <0x00 0x48600000 0x00 0x8000>, + <0x00 0x484a4000 0x00 0x2000>, + <0x00 0x484c2000 0x00 0x2000>, + <0x00 0x48420000 0x00 0x2000>; + reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", + "ring", "tchan", "rchan", "bchan"; msi-parent = <&inta_main_dmss>; #dma-cells = <3>; @@ -138,8 +142,13 @@ reg = <0x00 0x485c0000 0x00 0x100>, <0x00 0x4a800000 0x00 0x20000>, <0x00 0x4aa00000 0x00 0x40000>, - <0x00 0x4b800000 0x00 0x400000>; - reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; + <0x00 0x4b800000 0x00 0x400000>, + <0x00 0x485e0000 0x00 0x10000>, + <0x00 0x484a0000 0x00 0x2000>, + <0x00 0x484c0000 0x00 0x2000>, + <0x00 0x48430000 0x00 0x1000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", + "ring", "tchan", "rchan", "rflow"; msi-parent = <&inta_main_dmss>; #dma-cells = <2>; @@ -502,6 +511,9 @@ main_gpio0: gpio@600000 { compatible = "ti,am64-gpio", "ti,keystone-gpio"; reg = <0x0 0x00600000 0x0 0x100>; + gpio-ranges = <&main_pmx0 0 0 32>, + <&main_pmx0 32 33 38>, + <&main_pmx0 70 72 22>; gpio-controller; #gpio-cells = <2>; interrupt-parent = <&main_gpio_intr>; @@ -520,6 +532,10 @@ compatible = "ti,am64-gpio", "ti,keystone-gpio"; reg = <0x0 0x00601000 0x0 0x100>; gpio-controller; + gpio-ranges = <&main_pmx0 0 94 41>, + <&main_pmx0 41 136 6>, + <&main_pmx0 47 143 3>, + <&main_pmx0 50 149 2>; #gpio-cells = <2>; interrupt-parent = <&main_gpio_intr>; interrupts = <180>, <181>, <182>, @@ -542,10 +558,9 @@ clock-names = "clk_ahb", "clk_xin"; assigned-clocks = <&k3_clks 57 6>; assigned-clock-parents = <&k3_clks 57 8>; + bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; - ti,trm-icp = <0x2>; - bus-width = <8>; ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; @@ -563,7 +578,8 @@ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x8>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0x0>; @@ -575,8 +591,6 @@ ti,itap-del-sel-sd-hs = <0x1>; ti,itap-del-sel-sdr12 = <0xa>; ti,itap-del-sel-sdr25 = <0x1>; - ti,clkbuf-sel = <0x7>; - bus-width = <4>; status = "disabled"; }; @@ -587,7 +601,8 @@ power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x8>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0x0>; @@ -599,7 +614,6 @@ ti,itap-del-sel-sd-hs = <0xa>; ti,itap-del-sel-sdr12 = <0xa>; ti,itap-del-sel-sdr25 = <0x1>; - ti,clkbuf-sel = <0x7>; status = "disabled"; }; @@ -623,6 +637,8 @@ interrupt-names = "host", "peripheral"; maximum-speed = "high-speed"; dr_mode = "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; }; }; @@ -646,6 +662,8 @@ interrupt-names = "host", "peripheral"; maximum-speed = "high-speed"; dr_mode = "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; }; }; @@ -675,6 +693,15 @@ }; }; + gpu: gpu@fd00000 { + compatible = "ti,am62-gpu", "img,img-axe"; + reg = <0x00 0x0fd00000 0x00 0x20000>; + clocks = <&k3_clks 187 0>; + clock-names = "core"; + interrupts = ; + power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; + }; + cpsw3g: ethernet@8000000 { compatible = "ti,am642-cpsw-nuss"; #address-cells = <2>; @@ -753,9 +780,10 @@ <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ - <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */ + <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ + <0x00 0x30201000 0x00 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 186 6>, <&dss_vp1_clk>, @@ -965,4 +993,66 @@ power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; + + ti_csi2rx0: ticsi2rx@30102000 { + compatible = "ti,j721e-csi2rx-shim"; + dmas = <&main_bcdma 0 0x4700 0>; + dma-names = "rx0"; + reg = <0x00 0x30102000 0x00 0x1000>; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@30101000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x30101000 0x00 0x1000>; + clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, + <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@30110000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x30110000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + }; diff --git a/arch/arm/dts/k3-am62-mcu.dtsi b/arch/arm/dts/k3-am62-mcu.dtsi index 0e0b234581c..e66d486ef1f 100644 --- a/arch/arm/dts/k3-am62-mcu.dtsi +++ b/arch/arm/dts/k3-am62-mcu.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM625 SoC Family MCU Domain peripherals * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu { diff --git a/arch/arm/dts/k3-am62-thermal.dtsi b/arch/arm/dts/k3-am62-thermal.dtsi index a358757e26f..12ba833002a 100644 --- a/arch/arm/dts/k3-am62-thermal.dtsi +++ b/arch/arm/dts/k3-am62-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include diff --git a/arch/arm/dts/k3-am62-wakeup.dtsi b/arch/arm/dts/k3-am62-wakeup.dtsi index fef76f52a52..23ce1bfda8d 100644 --- a/arch/arm/dts/k3-am62-wakeup.dtsi +++ b/arch/arm/dts/k3-am62-wakeup.dtsi @@ -1,10 +1,12 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM625 SoC Family Wakeup Domain peripherals * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ +#include + &cbass_wakeup { wkup_conf: syscon@43000000 { bootph-all; @@ -21,14 +23,34 @@ }; }; - wkup_uart0: serial@2b300000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x2b300000 0x00 0x100>; - interrupts = ; + target-module@2b300050 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x00 0x2b300050 0x00 0x4>, + <0x00 0x2b300054 0x00 0x4>, + <0x00 0x2b300058 0x00 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + ti,no-reset-on-init; power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 114 0>; - clock-names = "fclk"; - status = "disabled"; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x2b300000 0x100000>; + + wkup_uart0: serial@0 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x0 0x100>; + interrupts = ; + status = "disabled"; + }; }; wkup_i2c0: i2c@2b200000 { diff --git a/arch/arm/dts/k3-am62.dtsi b/arch/arm/dts/k3-am62.dtsi index f1e15206e1c..f0781f2bea2 100644 --- a/arch/arm/dts/k3-am62.dtsi +++ b/arch/arm/dts/k3-am62.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM62 SoC Family * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include diff --git a/arch/arm/dts/k3-am625-beagleplay.dts b/arch/arm/dts/k3-am625-beagleplay.dts index 9a6bd0a3c94..a34e0df2ab8 100644 --- a/arch/arm/dts/k3-am625-beagleplay.dts +++ b/arch/arm/dts/k3-am625-beagleplay.dts @@ -1,9 +1,9 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * https://beagleplay.org/ * - * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ - * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Robert Nelson, BeagleBoard.org Foundation */ /dts-v1/; @@ -29,7 +29,6 @@ i2c3 = &main_i2c3; i2c4 = &wkup_i2c0; i2c5 = &mcu_i2c0; - mdio-gpio0 = &mdio0; mmc0 = &sdhci0; mmc1 = &sdhci1; mmc2 = &sdhci2; @@ -231,27 +230,6 @@ }; }; - /* Workaround for errata i2329 - just use mdio bitbang */ - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&mdio0_pins_default>; - gpios = <&main_gpio0 86 GPIO_ACTIVE_HIGH>, /* MDC */ - <&main_gpio0 85 GPIO_ACTIVE_HIGH>; /* MDIO */ - #address-cells = <1>; - #size-cells = <0>; - - cpsw3g_phy0: ethernet-phy@0 { - reg = <0>; - }; - - cpsw3g_phy1: ethernet-phy@1 { - reg = <1>; - reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>; - reset-assert-us = <25>; - reset-deassert-us = <60000>; /* T2 */ - }; - }; }; &main_pmx0 { @@ -312,8 +290,8 @@ mdio0_pins_default: mdio0-default-pins { pinctrl-single,pins = < - AM62X_IOPAD(0x0160, PIN_OUTPUT, 7) /* (AD24) MDIO0_MDC.GPIO0_86 */ - AM62X_IOPAD(0x015c, PIN_INPUT, 7) /* (AB22) MDIO0_MDIO.GPIO0_85 */ + AM62X_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ + AM62X_IOPAD(0x015c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ >; }; @@ -443,7 +421,7 @@ >; }; - console_pins_default: console-default-pins { + main_uart0_pins_default: main-uart0-default-pins { bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x01c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ @@ -573,11 +551,13 @@ }; &usbss0 { + bootph-all; ti,vbus-divider; status = "okay"; }; &usb0 { + bootph-all; dr_mode = "peripheral"; }; @@ -611,8 +591,20 @@ }; &cpsw3g_mdio { - /* Workaround for errata i2329 - Use mdio bitbang */ - status = "disabled"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_pins_default>; + + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + }; + + cpsw3g_phy1: ethernet-phy@1 { + reg = <1>; + reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <25>; + reset-deassert-us = <60000>; /* T2 */ + }; }; &main_gpio0 { @@ -827,7 +819,6 @@ bootph-all; pinctrl-names = "default"; pinctrl-0 = <&emmc_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; status = "okay"; }; @@ -840,7 +831,6 @@ vmmc-supply = <&vdd_3v3_sd>; vqmmc-supply = <&vdd_sd_dv>; - ti,driver-strength-ohm = <50>; disable-wp; cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>; cd-debounce-delay-ms = <100>; @@ -852,12 +842,10 @@ vmmc-supply = <&wlan_en>; pinctrl-names = "default"; pinctrl-0 = <&wifi_pins_default>, <&wifi_32k_clk>; - bus-width = <4>; non-removable; ti,fails-without-test-cd; cap-power-off-card; keep-power-in-suspend; - ti,driver-strength-ohm = <50>; assigned-clocks = <&k3_clks 157 158>; assigned-clock-parents = <&k3_clks 157 160>; #address-cells = <1>; @@ -877,7 +865,7 @@ &main_uart0 { bootph-all; pinctrl-names = "default"; - pinctrl-0 = <&console_pins_default>; + pinctrl-0 = <&main_uart0_pins_default>; status = "okay"; }; diff --git a/arch/arm/dts/k3-am625-sk.dts b/arch/arm/dts/k3-am625-sk.dts index b18092497c9..ae81ebb39d0 100644 --- a/arch/arm/dts/k3-am625-sk.dts +++ b/arch/arm/dts/k3-am625-sk.dts @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * AM625 SK: https://www.ti.com/lit/zip/sprr448 * - * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/dts/k3-am625.dtsi b/arch/arm/dts/k3-am625.dtsi index 4193c2b3eed..4014add6320 100644 --- a/arch/arm/dts/k3-am625.dtsi +++ b/arch/arm/dts/k3-am625.dtsi @@ -1,10 +1,10 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM625 SoC family in Quad core configuration * * TRM: https://www.ti.com/lit/pdf/spruiv7 * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/dts/k3-am62a-main.dtsi b/arch/arm/dts/k3-am62a-main.dtsi index 4ae7fdc5221..aa1e057082f 100644 --- a/arch/arm/dts/k3-am62a-main.dtsi +++ b/arch/arm/dts/k3-am62a-main.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM62A SoC Family Main Domain peripherals * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_main { @@ -42,9 +42,8 @@ }; }; - main_conf: syscon@100000 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00 0x00100000 0x00 0x20000>; + main_conf: bus@100000 { + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00 0x00 0x00100000 0x20000>; @@ -101,8 +100,13 @@ <0x00 0x4c000000 0x00 0x20000>, <0x00 0x4a820000 0x00 0x20000>, <0x00 0x4aa40000 0x00 0x20000>, - <0x00 0x4bc00000 0x00 0x100000>; - reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; + <0x00 0x4bc00000 0x00 0x100000>, + <0x00 0x48600000 0x00 0x8000>, + <0x00 0x484a4000 0x00 0x2000>, + <0x00 0x484c2000 0x00 0x2000>, + <0x00 0x48420000 0x00 0x2000>; + reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", + "ring", "tchan", "rchan", "bchan"; msi-parent = <&inta_main_dmss>; #dma-cells = <3>; ti,sci = <&dmsc>; @@ -117,8 +121,13 @@ reg = <0x00 0x485c0000 0x00 0x100>, <0x00 0x4a800000 0x00 0x20000>, <0x00 0x4aa00000 0x00 0x40000>, - <0x00 0x4b800000 0x00 0x400000>; - reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; + <0x00 0x4b800000 0x00 0x400000>, + <0x00 0x485e0000 0x00 0x10000>, + <0x00 0x484a0000 0x00 0x2000>, + <0x00 0x484c0000 0x00 0x2000>, + <0x00 0x48430000 0x00 0x1000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", + "ring", "tchan", "rchan", "rflow"; msi-parent = <&inta_main_dmss>; #dma-cells = <2>; ti,sci = <&dmsc>; @@ -144,6 +153,44 @@ }; }; + dmss_csi: bus@4e000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges; + ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x300000>; + + ti,sci-dev-id = <198>; + + inta_main_dmss_csi: interrupt-controller@4e0a0000 { + compatible = "ti,sci-inta"; + reg = <0x00 0x4e0a0000 0x00 0x8000>; + #interrupt-cells = <0>; + interrupt-controller; + interrupt-parent = <&gic500>; + msi-controller; + ti,sci = <&dmsc>; + ti,sci-dev-id = <200>; + ti,interrupt-ranges = <0 237 8>; + ti,unmapped-event-sources = <&main_bcdma_csi>; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + }; + + main_bcdma_csi: dma-controller@4e230000 { + compatible = "ti,am62a-dmss-bcdma-csirx"; + reg = <0x00 0x4e230000 0x00 0x100>, + <0x00 0x4e180000 0x00 0x8000>, + <0x00 0x4e100000 0x00 0x10000>; + reg-names = "gcfg", "rchanrt", "ringrt"; + msi-parent = <&inta_main_dmss_csi>; + #dma-cells = <3>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <199>; + ti,sci-rm-range-rchan = <0x21>; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + }; + }; + dmsc: system-controller@44043000 { compatible = "ti,k2g-sci"; reg = <0x00 0x44043000 0x00 0xfe0>; @@ -462,7 +509,7 @@ <193>, <194>, <195>; interrupt-controller; #interrupt-cells = <2>; - ti,ngpio = <87>; + ti,ngpio = <92>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 77 0>; @@ -480,7 +527,7 @@ <183>, <184>, <185>; interrupt-controller; #interrupt-cells = <2>; - ti,ngpio = <88>; + ti,ngpio = <52>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 78 0>; @@ -488,6 +535,24 @@ status = "disabled"; }; + sdhci0: mmc@fa10000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; + interrupts = ; + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; + clock-names = "clk_ahb", "clk_xin"; + assigned-clocks = <&k3_clks 57 6>; + assigned-clock-parents = <&k3_clks 57 8>; + bus-width = <8>; + mmc-hs200-1_8v; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; + ti,otap-del-sel-hs200 = <0x6>; + status = "disabled"; + }; + sdhci1: mmc@fa00000 { compatible = "ti,am62-sdhci"; reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; @@ -495,7 +560,8 @@ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; @@ -507,8 +573,30 @@ ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; - ti,clkbuf-sel = <0x7>; + no-1-8-v; + status = "disabled"; + }; + + sdhci2: mmc@fa20000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0xfa20000 0x00 0x260>, <0x00 0xfa28000 0x00 0x134>; + interrupts = ; + power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; + clock-names = "clk_ahb", "clk_xin"; bus-width = <4>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; no-1-8-v; status = "disabled"; }; @@ -876,4 +964,91 @@ power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; + + ti_csi2rx0: ticsi2rx@30102000 { + compatible = "ti,j721e-csi2rx-shim"; + dmas = <&main_bcdma_csi 0 0x5000 0>; + dma-names = "rx0"; + reg = <0x00 0x30102000 0x00 0x1000>; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@30101000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x30101000 0x00 0x1000>; + clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, + <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@30110000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x30110000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dss: dss@30200000 { + compatible = "ti,am62a7-dss"; + reg = <0x00 0x30200000 0x00 0x1000>, /* common */ + <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ + <0x00 0x30206000 0x00 0x1000>, /* vid */ + <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ + <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ + <0x00 0x3020a000 0x00 0x1000>, /* vp1: Tied OFF in the SoC */ + <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ + <0x00 0x30201000 0x00 0x1000>; /* common1 */ + reg-names = "common", "vidl1", "vid", + "ovr1", "ovr2", "vp1", "vp2", "common1"; + power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 186 6>, + <&k3_clks 186 0>, + <&k3_clks 186 2>; + clock-names = "fck", "vp1", "vp2"; + interrupts = ; + status = "disabled"; + + dss_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; diff --git a/arch/arm/dts/k3-am62a-mcu.dtsi b/arch/arm/dts/k3-am62a-mcu.dtsi index a6d16a94088..8c36e56f413 100644 --- a/arch/arm/dts/k3-am62a-mcu.dtsi +++ b/arch/arm/dts/k3-am62a-mcu.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM625 SoC Family MCU Domain peripherals * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu { diff --git a/arch/arm/dts/k3-am62a-thermal.dtsi b/arch/arm/dts/k3-am62a-thermal.dtsi index 85ce545633e..c7486fb2a5b 100644 --- a/arch/arm/dts/k3-am62a-thermal.dtsi +++ b/arch/arm/dts/k3-am62a-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include diff --git a/arch/arm/dts/k3-am62a-wakeup.dtsi b/arch/arm/dts/k3-am62a-wakeup.dtsi index 4e8279fa01e..f7bec484705 100644 --- a/arch/arm/dts/k3-am62a-wakeup.dtsi +++ b/arch/arm/dts/k3-am62a-wakeup.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM62A SoC Family Wakeup Domain peripherals * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_wakeup { diff --git a/arch/arm/dts/k3-am62a.dtsi b/arch/arm/dts/k3-am62a.dtsi index 61a210ecd5f..b1b88460029 100644 --- a/arch/arm/dts/k3-am62a.dtsi +++ b/arch/arm/dts/k3-am62a.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM62A SoC Family * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include diff --git a/arch/arm/dts/k3-am62a7-sk.dts b/arch/arm/dts/k3-am62a7-sk.dts index 8f64ac2c756..f241637a564 100644 --- a/arch/arm/dts/k3-am62a7-sk.dts +++ b/arch/arm/dts/k3-am62a7-sk.dts @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * AM62A SK: https://www.ti.com/lit/zip/sprr459 * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -20,6 +20,7 @@ serial0 = &wkup_uart0; serial2 = &main_uart0; serial3 = &main_uart1; + mmc0 = &sdhci0; mmc1 = &sdhci1; }; @@ -132,6 +133,18 @@ clock-frequency = <12288000>; }; + hdmi0: connector-hdmi { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&sii9022_out>; + }; + }; + }; + codec_audio: sound { compatible = "simple-audio-card"; simple-audio-card,name = "AM62Ax-SKEVM"; @@ -181,6 +194,39 @@ }; &main_pmx0 { + main_dss0_pins_default: main-dss0-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x100, PIN_OUTPUT, 0) /* (V17) VOUT0_VSYNC */ + AM62AX_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (T18) VOUT0_HSYNC */ + AM62AX_IOPAD(0x104, PIN_OUTPUT, 0) /* (AA22) VOUT0_PCLK */ + AM62AX_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (U17) VOUT0_DE */ + AM62AX_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */ + AM62AX_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (U21) VOUT0_DATA1 */ + AM62AX_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (U20) VOUT0_DATA2 */ + AM62AX_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (U19) VOUT0_DATA3 */ + AM62AX_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (T19) VOUT0_DATA4 */ + AM62AX_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (U18) VOUT0_DATA5 */ + AM62AX_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (V22) VOUT0_DATA6 */ + AM62AX_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA7 */ + AM62AX_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V19) VOUT0_DATA8 */ + AM62AX_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (V18) VOUT0_DATA9 */ + AM62AX_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (W22) VOUT0_DATA10 */ + AM62AX_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA11 */ + AM62AX_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (W20) VOUT0_DATA12 */ + AM62AX_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (W19) VOUT0_DATA13 */ + AM62AX_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y21) VOUT0_DATA14 */ + AM62AX_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA15 */ + AM62AX_IOPAD(0x05c, PIN_OUTPUT, 1) /* (P22) GPMC0_AD8.VOUT0_DATA16 */ + AM62AX_IOPAD(0x060, PIN_OUTPUT, 1) /* (R19) GPMC0_AD9.VOUT0_DATA17 */ + AM62AX_IOPAD(0x064, PIN_OUTPUT, 1) /* (R20) GPMC0_AD10.VOUT0_DATA18 */ + AM62AX_IOPAD(0x068, PIN_OUTPUT, 1) /* (R22) GPMC0_AD11.VOUT0_DATA19 */ + AM62AX_IOPAD(0x06c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */ + AM62AX_IOPAD(0x070, PIN_OUTPUT, 1) /* (R21) GPMC0_AD13.VOUT0_DATA21 */ + AM62AX_IOPAD(0x074, PIN_OUTPUT, 1) /* (T20) GPMC0_AD14.VOUT0_DATA22 */ + AM62AX_IOPAD(0x078, PIN_OUTPUT, 1) /* (T21) GPMC0_AD15.VOUT0_DATA23 */ + >; + }; + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */ @@ -218,6 +264,22 @@ >; }; + main_mmc0_pins_default: main-mmc0-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ + AM62AX_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLKLB */ + AM62AX_IOPAD(0x21c, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ + AM62AX_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ + AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */ + AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */ + AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */ + AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */ + AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */ + AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ + AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ @@ -274,6 +336,12 @@ AM62AX_IOPAD(0x084, PIN_INPUT, 2) /* (L18) GPMC0_ADVn_ALE.MCASP1_AXR2 */ >; }; + + main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x01d4, PIN_INPUT, 7) /* (C15) UART0_RTSn.GPIO1_23 */ + >; + }; }; &mcu_pmx0 { @@ -407,6 +475,12 @@ reg = <0x22>; gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&main_gpio1>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>; gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", "BT_EN_SOC", "MMC1_SD_EN", @@ -434,6 +508,72 @@ DRVDD-supply = <&vcc_3v3_sys>; DVDD-supply = <&buck5>; }; + + exp2: gpio@23 { + compatible = "ti,tca6424"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = "", "", + "", "", + "", "", + "", "", + "WL_LT_EN", "CSI_RSTz", + "", "", + "", "", + "", "", + "SPI0_FET_SEL", "SPI0_FET_OE", + "RGMII2_BRD_CONN_DET", "CSI_SEL2", + "CSI_EN", "AUTO_100M_1000M_CONFIG", + "CSI_VLDO_SEL", "SoC_WLAN_SDIO_RST"; + }; + + sii9022: bridge-hdmi@3b { + compatible = "sil,sii9022"; + reg = <0x3b>; + interrupt-parent = <&exp1>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + #sound-dai-cells = <0>; + sil,i2s-data-lanes = < 0 >; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in: endpoint { + remote-endpoint = <&dpi1_out>; + }; + }; + + port@1 { + reg = <1>; + + sii9022_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&main_i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c2_pins_default>; + clock-frequency = <400000>; +}; + +&sdhci0 { + /* eMMC */ + status = "okay"; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + disable-wp; }; &sdhci1 { @@ -442,7 +582,6 @@ vmmc-supply = <&vdd_mmc1>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; @@ -544,3 +683,20 @@ tx-num-evt = <32>; rx-num-evt = <32>; }; + +&dss { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_dss0_pins_default>; +}; + +&dss_ports { + /* VP2: DPI Output */ + port@1 { + reg = <1>; + + dpi1_out: endpoint { + remote-endpoint = <&sii9022_in>; + }; + }; +}; diff --git a/arch/arm/dts/k3-am62a7.dtsi b/arch/arm/dts/k3-am62a7.dtsi index 58f1c43edcf..f86a23404e6 100644 --- a/arch/arm/dts/k3-am62a7.dtsi +++ b/arch/arm/dts/k3-am62a7.dtsi @@ -1,10 +1,10 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM62A7 SoC family in Quad core configuration * * TRM: https://www.ti.com/lit/zip/spruj16 * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/dts/k3-am62x-sk-common.dtsi b/arch/arm/dts/k3-am62x-sk-common.dtsi index 19f57ead4eb..3c45782ab2b 100644 --- a/arch/arm/dts/k3-am62x-sk-common.dtsi +++ b/arch/arm/dts/k3-am62x-sk-common.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Common dtsi for AM62x SK and derivatives * - * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include @@ -399,12 +399,18 @@ }; }; +&main_i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c2_pins_default>; + clock-frequency = <400000>; +}; + &sdhci0 { bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mmc0_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; @@ -414,7 +420,6 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; @@ -453,6 +458,7 @@ }; &usbss0 { + bootph-all; status = "okay"; ti,vbus-divider; }; @@ -463,6 +469,7 @@ }; &usb0 { + bootph-all; #address-cells = <1>; #size-cells = <0>; usb-role-switch; @@ -517,3 +524,12 @@ }; }; }; + +/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */ +&mcu_gpio0 { + status = "reserved"; +}; + +&mcu_gpio_intr { + status = "reserved"; +}; From 7517eea09f6f8e76b20edff73d242e6a7e854b13 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Mon, 13 May 2024 15:13:55 +0300 Subject: [PATCH 034/383] arm: dts: k3-am625-beagleplay: get CPSW Ethernet to work Add missing bits in -u-boot.dtsi to get CPSW Ethernet working. Signed-off-by: Roger Quadros --- arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi | 63 ++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi index fb2032068d1..54a7702037d 100644 --- a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi @@ -206,3 +206,66 @@ }; }; #endif + +&main_bcdma { + reg = <0x00 0x485c0100 0x00 0x100>, + <0x00 0x4c000000 0x00 0x20000>, + <0x00 0x4a820000 0x00 0x20000>, + <0x00 0x4aa40000 0x00 0x20000>, + <0x00 0x4bc00000 0x00 0x100000>, + <0x00 0x48600000 0x00 0x8000>, + <0x00 0x484a4000 0x00 0x2000>, + <0x00 0x484c2000 0x00 0x2000>; + reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", + "cfg", "tchan", "rchan"; +}; + +&main_pktdma { + reg = <0x00 0x485c0000 0x00 0x100>, + <0x00 0x4a800000 0x00 0x20000>, + <0x00 0x4aa00000 0x00 0x40000>, + <0x00 0x4b800000 0x00 0x400000>, + <0x00 0x485e0000 0x00 0x20000>, + <0x00 0x484a0000 0x00 0x4000>, + <0x00 0x484c0000 0x00 0x2000>, + <0x00 0x48430000 0x00 0x4000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", "cfg", + "tchan", "rchan", "rflow"; + bootph-all; +}; + +&mdio0_pins_default { + bootph-all; +}; + +&cpsw3g_mdio { + bootph-all; +}; + +&cpsw3g_phy0 { + bootph-all; +}; + +&rgmii1_pins_default { + bootph-all; +}; + +&cpsw3g { + bootph-all; + + ethernet-ports { + bootph-all; + }; +}; + +&phy_gmii_sel { + bootph-all; +}; + +&cpsw_port1 { + bootph-all; +}; + +&cpsw_port2 { + status = "disabled"; +}; From 3bfef5fe9006d1995b68dd0eb716d2b6f252f45e Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Mon, 13 May 2024 15:13:56 +0300 Subject: [PATCH 035/383] arm: dts: k3-am625-beagleplay: Fix Ethernet PHY reset GPIO Move GPIO pinmux to MDIO node. Add GB Ethernet reset GPIO. Add PIN_INPUT to Fix SPE ethernet reset gpio so that reading the GPIO can give correct status. Signed-off-by: Roger Quadros --- arch/arm/dts/k3-am625-beagleplay.dts | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/k3-am625-beagleplay.dts b/arch/arm/dts/k3-am625-beagleplay.dts index a34e0df2ab8..8ab838f1697 100644 --- a/arch/arm/dts/k3-am625-beagleplay.dts +++ b/arch/arm/dts/k3-am625-beagleplay.dts @@ -292,6 +292,8 @@ pinctrl-single,pins = < AM62X_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ AM62X_IOPAD(0x015c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ + AM62X_IOPAD(0x003c, PIN_INPUT, 7) /* (M25) GPMC0_AD0.GPIO0_15 */ + AM62X_IOPAD(0x018c, PIN_INPUT, 7) /* (AC21) RGMII2_RD2.GPIO1_5 */ >; }; @@ -383,7 +385,6 @@ AM62X_IOPAD(0x016c, PIN_INPUT, 1) /* (Y18) RGMII2_TD0.RMII2_TXD0 */ AM62X_IOPAD(0x0170, PIN_INPUT, 1) /* (AA18) RGMII2_TD1.RMII2_TXD1 */ AM62X_IOPAD(0x0164, PIN_INPUT, 1) /* (AA19) RGMII2_TX_CTL.RMII2_TX_EN */ - AM62X_IOPAD(0x018c, PIN_OUTPUT, 7) /* (AC21) RGMII2_RD2.GPIO1_5 */ AM62X_IOPAD(0x0190, PIN_INPUT, 7) /* (AE22) RGMII2_RD3.GPIO1_6 */ AM62X_IOPAD(0x01f0, PIN_OUTPUT, 5) /* (A18) EXT_REFCLK1.CLKOUT0 */ >; @@ -597,6 +598,9 @@ cpsw3g_phy0: ethernet-phy@0 { reg = <0>; + reset-gpios = <&main_gpio0 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <50000>; }; cpsw3g_phy1: ethernet-phy@1 { @@ -615,7 +619,7 @@ "USR0", "USR1", "USR2", "USR3", "", "", "USR4", /* 3-9 */ "EEPROM_WP", /* 10 */ "CSI2_CAMERA_GPIO1", "CSI2_CAMERA_GPIO2", /* 11-12 */ - "CC1352P7_BOOT", "CC1352P7_RSTN", "", "", "", /* 13-17 */ + "CC1352P7_BOOT", "CC1352P7_RSTN", "GBE_RSTN", "", "", /* 13-17 */ "USR_BUTTON", "", "", "", "", "", "", "", "", /* 18-26 */ "", "", "", "", "", "", "", "", "", "HDMI_INT", /* 27-36 */ "", "VDD_WLAN_EN", "", "", "WL_IRQ", "GBE_INTN",/* 37-42 */ From 6bb92fcf7d2fea2314d616e5e2391a8bf2b0fdfa Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 20 May 2024 09:54:58 -0600 Subject: [PATCH 036/383] Squashed 'dts/upstream/' changes from b35b9bd1d4ee..7e08733c96c8 7e08733c96c8 Merge tag 'v6.9-dts-raw' ccdce3340fc5 Merge tag 'net-6.9-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net cb4ccb79bf49 dt-bindings: net: mediatek: remove wrongly added clocks and SerDes 6bd14595bb37 Merge tag 'soc-fixes-6.9-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc a6d12fb4ba6f Merge tag 'qcom-arm64-fixes-for-6.9-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes 71c2fe626e53 Merge tag 'v6.9-rc7-dts-raw' 62d74bd1c58f Merge tag 'char-misc-6.9-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc bdc631c5b7eb arm64: dts: mediatek: mt8183-pico6: Fix bluetooth node 9818a367c6b8 Merge tag 'sound-6.9-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound c861ae2b0770 Merge tag 'pinctrl-v6.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl c9551dbd4ea4 Merge tag 'v6.9-rc6-dts-raw' 17c632b49122 Merge tag 'i2c-for-6.9-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux a1bf8545a7b4 Merge tag 'soc-fixes-6.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc d13e05c0fe9b Merge tag 'arc-6.9-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc 83b7bf1bdd47 Merge tag 'imx-fixes-6.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into for-next 3a940d011934 Merge tag 'mtk-dts64-fixes-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into for-next 6eeb1be299fc Merge tag 'at91-fixes-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into for-next 733db5273cb7 Merge tag 'qcom-arm64-fixes-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into for-next 76a235f6ef02 Merge branch 'v6.9-armsoc/dtsfixes' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into for-next a4916498fb4a Merge tag 'at24-fixes-for-v6.9-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into i2c/for-current 6ee8c2d34ea8 ARM: dts: imx6ull-tarragon: fix USB over-current polarity c3ee365cb940 Merge tag 'iio-fixes-for-6.9a' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-linus bb3b0f6bb688 Merge tag 'v6.9-rc5-dts-raw' ca2b45c908c0 arm64: dts: imx8mp: Fix assigned-clocks for second CSI2 b91b30ccdb82 Merge tag 'tty-6.9-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty 9e347843c73f ARM: dts: microchip: at91-sama7g54_curiosity: Replace regulator-suspend-voltage with the valid property a6e3d2cb9d6d ARM: dts: microchip: at91-sama7g5ek: Replace regulator-suspend-voltage with the valid property 01c2febb3cdb arm64: dts: qcom: sa8155p-adp: fix SDHC2 CD pin configuration 460856d18366 arm64: dts: rockchip: Fix USB interface compatible string on kobol-helios64 e91f447c8573 Merge tag 'pwm/for-6.9-rc5-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux b362458a0941 dt-bindings: eeprom: at24: Fix ST M24C64-D compatible schema 4c77f098d193 ARC: [plat-hsdk]: Remove misplaced interrupt-cells property bc5665bd550f dt-bindings: pwm: mediatek,pwm-disp: Document power-domains property bdb049c4d14f Merge tag 'v6.9-rc4-dts-raw' ea20dda12f5b Merge tag 'soc-fixes-6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc c43f5bbe57fe arm64: dts: qcom: sc8180x: Fix ss_phy_irq for secondary USB controller 09bbdcd84ac2 arm64: dts: qcom: sm8650: Fix the msi-map entries 864783541376 arm64: dts: qcom: sm8550: Fix the msi-map entries ddedda592d70 arm64: dts: qcom: sm8450: Fix the msi-map entries 960336e0e880 arm64: dts: qcom: sc8280xp: add missing PCIe minimum OPP eb57b8e07fd7 arm64: dts: qcom: x1e80100: Fix the compatible for cluster idle states 64b22344a08d arm64: dts: qcom: Fix type of "wdog" IRQs for remoteprocs 3d4da9353d8a Merge tag 'drm-fixes-2024-04-12' of https://gitlab.freedesktop.org/drm/kernel 94d5ae8ffd5b Merge tag 'drm-msm-next-2024-04-11' of https://gitlab.freedesktop.org/drm/msm into drm-fixes 45ab49b70c99 LoongArch: Update dts for Loongson-2K2000 to support GMAC/GNET e5f2765cdef5 LoongArch: Update dts for Loongson-2K2000 to support PCI-MSI 65d54f215c81 LoongArch: Update dts for Loongson-2K2000 to support ISA/LPC 05bddcf85f2c LoongArch: Update dts for Loongson-2K1000 to support ISA/LPC e32b794a9062 arm64: dts: rockchip: regulator for sd needs to be always on for BPI-R2Pro cf90790de0b2 dt-bindings: rockchip: grf: Add missing type to 'pcie-phy' node ad6402eb7acc arm64: dts: rockchip: drop redundant disable-gpios in Lubancat 2 ace753017ab4 arm64: dts: rockchip: drop redundant disable-gpios in Lubancat 1 24eae3d76a2b arm64: dts: rockchip: drop redundant pcie-reset-suspend in Scarlet Dumo 6ddbc8e4f612 arm64: dts: rockchip: mark system power controller and fix typo on orangepi-5-plus 7d1e92c191e5 arm64: dts: rockchip: Designate the system power controller on QuartzPro64 b2f8ee07aa8e ASoC: dt-bindings: rt5645: add cbj sleeve gpio property 39841e784daa MAINTAINERS: mailmap: update Richard Genoud's email address 10c6631c86d1 Merge tag 'v6.9-rc3-dts-raw' 4ea847a91dd6 Merge tag 'devicetree-fixes-for-6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 446b3564a952 arm64: dts: mediatek: mt2712: fix validation errors 65d0eb62f0f1 arm64: dts: mediatek: mt7986: prefix BPI-R3 cooling maps with "map-" a2ac24e9a4dc arm64: dts: mediatek: mt7986: drop invalid thermal block clock 7d65b24f6c7b arm64: dts: mediatek: mt7986: drop "#reset-cells" from Ethernet controller 6674a5ba09ef arm64: dts: mediatek: mt7986: drop invalid properties from ethsys fb0a8e849646 dt-bindings: timer: narrow regex for unit address to hex numbers cb1b6952348f dt-bindings: soc: fsl: narrow regex for unit address to hex numbers 27c8017d28c8 dt-bindings: remoteproc: ti,davinci: remove unstable remark 9095a10d281f dt-bindings: clock: ti: remove unstable remark 3f61301c1488 dt-bindings: clock: keystone: remove unstable remark 31b1ce263042 arm64: dts: imx8qm-ss-dma: fix can lpcg indices 743b20b5d4db arm64: dts: imx8-ss-dma: fix can lpcg indices d8f0818c58bc arm64: dts: imx8-ss-dma: fix adc lpcg indices 2349133feee2 arm64: dts: imx8-ss-dma: fix pwm lpcg indices a18420af419e arm64: dts: imx8-ss-dma: fix spi lpcg indices d6d2add292ae arm64: dts: imx8-ss-conn: fix usb lpcg indices fc19a9596662 arm64: dts: imx8-ss-lsio: fix pwm lpcg indices 64a1c4a72a08 arm64: dts: mediatek: mt7622: drop "reset-names" from thermal block f91467bb0e7c arm64: dts: mediatek: mt7622: fix ethernet controller "compatible" 8e632e3e98df arm64: dts: mediatek: mt7622: fix IR nodename 1472eb8a5653 arm64: dts: mediatek: mt7622: fix clock controllers 5802f95e74db arm64: dts: mediatek: mt8186-corsola: Update min voltage constraint for Vgpu 6cb73d686d58 arm64: dts: mediatek: mt8183-kukui: Use default min voltage for MT6358 cd3a14e0479e arm64: dts: mediatek: mt8195-cherry: Update min voltage constraint for MT6315 2814659a8a80 arm64: dts: mediatek: mt8192-asurada: Update min voltage constraint for MT6315 3ea180fa00c5 arm64: dts: mediatek: cherry: Describe CPU supplies c452106eb835 arm64: dts: mediatek: mt8195: Add missing gce-client-reg to mutex1 5893bd804364 arm64: dts: mediatek: mt8195: Add missing gce-client-reg to mutex ad1660ce46c3 arm64: dts: mediatek: mt8195: Add missing gce-client-reg to vpp/vdosys 744724419d4c arm64: dts: mediatek: mt8192: Add missing gce-client-reg to mutex 902cad91425f arm64: dts: mediatek: mt8183: Add power-domains properity to mfgcfg 7b49bc388147 ARM: dts: imx7s-warp: Pass OV2680 link-frequencies bd5623d08b6c ARM: dts: imx7-mba7: Use 'no-mmc' property 51b8028c7925 arm64: dts: imx8-ss-conn: fix usdhc wrong lpcg clock order 6beeed742637 dt-bindings: display/msm: sm8150-mdss: add DP node 954f369b81da ARC: Fix typos 3d2c4d764916 arm64: dts: rockchip: drop panel port unit address in GRU Scarlet fa6ab1a0c8a1 arm64: dts: rockchip: Remove unsupported node from the Pinebook Pro dts 7f80622495d4 arm64: dts: qcom: sc7180-trogdor: mark bluetooth address as broken 92953647265f dt-bindings: bluetooth: add 'qcom,local-bd-address-broken' 6421f94d75f4 arm64: dts: freescale: imx8mp-venice-gw73xx-2x: fix USB vbus regulator 4bb321df9164 arm64: dts: freescale: imx8mp-venice-gw72xx-2x: fix USB vbus regulator f37161a9cf0c dt-bindings: ufs: qcom: document SM6125 UFS b2a26b71ae7d dt-bindings: ufs: qcom: document SC7180 UFS 1cb1e2605d33 dt-bindings: ufs: qcom: document SC8180X UFS 6bd77a407d2e dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow 'input' and 'output-enable' properties 2639a0e2fdbd Merge tag 'v6.9-rc1-dts-raw' 15eca7b21493 docs: dt-bindings: add missing address/size-cells to example 9ace491cae40 arm64: dts: rockchip: Fix the i2c address of es8316 on Cool Pi CM5 d8bdab44b3fe arm64: dts: rockchip: add regulators for PCIe on RK3399 Puma Haikou 1331876fe9c8 arm64: dts: rockchip: enable internal pull-up on PCIE_WAKE# for RK3399 Puma 57878497676a arm64: dts: rockchip: enable internal pull-up on Q7_USB_ID for RK3399 Puma a9686a9d2878 arm64: dts: rockchip: fix alphabetical ordering RK3399 puma 6125abd98f94 arm64: dts: rockchip: enable internal pull-up for Q7_THRM# on RK3399 Puma e51b8871e6a8 arm64: dts: rockchip: set PHY address of MT7531 switch to 0x1f 8c7a1135d13d dt-bindings: iio: health: maxim,max30102: fix compatible check 7eea89692b5a Merge tag 'timers-core-2024-03-23' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 665795c05a77 Merge tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux 9497bb8a116e Merge tag 'spi-fix-v6.9-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi 6aef9b1ef737 Merge tag 'sound-fix2-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound 17cde028ffcc Merge tag 'i2c-for-6.9-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux 7bbd20ac15d0 Merge tag 'rtc-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux b2bb86451efb Merge tag 'ubifs-for-linus-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs 203aa834e5f2 Merge tag 'char-misc-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc 9125147fa946 Merge tag 'tty-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty e5738ce51174 Merge tag 'usb-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb d4a1391985cc Merge tag 'rproc-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux b3632b121e0d Merge tag 'asoc-fix-v6.9-merge-window' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus 4a7dcd8c3a18 dt-bindings: i2c: qcom,i2c-cci: Fix OV7251 'data-lanes' entries f76fa412f9a8 Merge tag 'i2c-host-6.9-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-mergewindow 8cd35b85c4b0 Merge tag 'soc-late-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc f6c32d4a4ede Merge tag 'thermal-6.9-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm 6630f47c5f9a spi: Merge up v6.8 release ec2e44a038f5 Merge tag 'timers-v6.9-rc1' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core ef0c6b10c2da Merge tag 'i3c/for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux 6defc064e93e Merge tag 'linux-watchdog-6.9-rc1' of git://www.linux-watchdog.org/linux-watchdog 72fe2cde7b8a Merge tag 'input-for-v6.9-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input a546e7273d2d Merge tag 'phy-for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy 3972e256bfa2 Merge tag 'v6.9-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6 a355cc2d4dcb Merge tag 'mips_6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux aefedca6e1b1 Merge tag 'devicetree-for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 8eb838e35ade Merge tag 'mtd/for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux 7497080a0eda Merge tag 'dmaengine-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine 571f27ef129d Merge tag 'i2c-for-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux fb60e6d58b2d dt-bindings: input: samsung,s3c6410-keypad: convert to DT Schema 34598dab4724 Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 9d67b3ce96cb Merge tag 'media/v6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media 3fe3426bca72 dt-bindings: soc: imx: fsl,imx-anatop: add imx6q regulators 7311bc58c158 Merge tag 'nand/for-6.9' into mtd/next 146d9a6f3ded dt-bindings: atmel-nand: add microchip,sam9x7-pmecc e2a5c7c3959b arm64: dts: broadcom: bcmbca: Update router boards 1bd13f3b7695 arm64: dts: broadcom: bcmbca: Add NAND controller node cc519333e3cf ARM: dts: broadcom: bcmbca: Add NAND controller node c1e4264b6d55 Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 6371c24fe180 Merge tag 'sound-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound 98c06b3a9483 Merge tag 'pci-v6.9-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci 7fa73443a89b Merge tag 'platform-drivers-x86-v6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86 e76bc30ffbd6 Merge tag 'leds-next-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/leds 19186d59b259 Merge tag 'backlight-next-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/backlight 75c5518e62b1 Merge tag 'mfd-next-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd 099699809967 Merge tag 'pinctrl-v6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 8e49bd3cbb58 Merge tag 'auxdisplay-v6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-auxdisplay a775511def90 Merge tag 'drm-next-2024-03-13' of https://gitlab.freedesktop.org/drm/kernel 4d3acb15ed8a Merge tag 'spi-nor/for-6.9' into mtd/next 51591c70d1ca Merge branches 'clk-samsung', 'clk-imx', 'clk-rockchip', 'clk-clkdev' and 'clk-rate-exclusive' into clk-next 0c05d2bca0f7 Merge tag 'thermal-v6.9-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/thermal/linux a55648d846e7 Merge branches 'clk-remove', 'clk-amlogic', 'clk-qcom', 'clk-parent' and 'clk-microchip' into clk-next 749f625e4547 Merge branches 'clk-aspeed', 'clk-keystone', 'clk-mobileye' and 'clk-allwinner' into clk-next 82d0f90167fc Merge branches 'clk-renesas', 'clk-cleanup', 'clk-hisilicon', 'clk-mediatek' and 'clk-bulk' into clk-next 6526c4a4b4e5 Merge tag 'tpmdd-v6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/jarkko/linux-tpmdd 1da1a2503cbc Merge tag 'mailbox-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox cecb3b4fdac3 Merge tag 'pm-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm 49c8db52641c Merge tag 'pmdomain-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm b15efb2ec6a3 Merge tag 'hwmon-for-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging 51da5c0be9f6 ASoC: Merge up release 82088fb378a1 Merge tag 'gpio-updates-for-v6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux 08aa0ae1911b Merge tag 'spi-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi 4a3bf9f36d1e Merge tag 'regulator-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator c77ca2066932 Merge tag 'mmc-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc c5d224537c1b Merge tag 'pwm/for-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux 4915b8cd98b1 Merge tag 'ata-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/libata/linux 087aaa6a3b72 Merge tag 'iommu-updates-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu 8a195fe51ba1 Merge tag 'net-next-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next 80731b204b02 Merge tag 'soc-drivers-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc ba13a7bc46d2 Merge tag 'soc-dt-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 8bdef0681554 Merge branch 'pci/controller/qcom' 5ad36cd7e767 riscv: dts: renesas: Add Andes PMU extension for r9a07g043f 8ecbb51f81c3 dt-bindings: riscv: Add Andes PMU extension description 9b464e19669d riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC 7d51e7e2e08f dt-bindings: riscv: Add Andes interrupt controller compatible string 9ff0305a8ca8 ASoC: dt-bindings: cirrus,cs42l43: Fix 'gpio-ranges' schema 9527f40e46b6 Input: allocate keycode for Display refresh rate toggle 62e63d55bebc Merge tag 'i2c-host-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-mergewindow 9570e92757ae dt-bindings: tpm: Add compatible string atmel,attpm20p 7cfac8b79d64 Merge tag 'irq-core-2024-03-10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 432d7edb5952 dt-bindings: thermal: rcar-gen3-thermal: Add r8a779h0 support 338820b14493 dt-bindings: thermal-zones: Don't require polling-delay(-passive) 586ddb37a9a4 dt-bindings: thermal: sun8i: Add H616 THS controller 167b4b5a2247 dt-bindings: thermal: qoriq-thermal: Adjust fsl,tmu-range min/maxItems 97f8ab2a1af7 Merge tag 'opp-updates-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm into pm 6478cc89c8f9 Merge tag 'asoc-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus ac6125bb95c2 mips: dts: ralink: mt7621: add cell count properties to usb c5bb691ccc3e mips: dts: ralink: mt7621: add serial1 and serial2 nodes 7b09814959b2 mips: dts: ralink: mt7621: reorder serial0 properties ec836787ded4 mips: dts: ralink: mt7621: associate uart1_pins with serial0 7d9359e47208 Merge tag 'riscv-dt-fixes-for-v6.8-final' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt 078fe0b4bda8 Merge tag 'arm-soc/for-6.9/drivers' of https://github.com/Broadcom/stblinux into soc/late a851536f7d1f Merge tag 'arm-soc/for-6.9/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/late 63fbbfa8e739 dt-bindings: opp: drop maxItems from inner items 54c13b3c325d dt-bindings: mailbox: fsl,mu: add i.MX95 Generic/ELE/V2X MU compatible 4950062963d6 dt-bindings: input: imagis: Document touch keys cfb6e7e4aab8 dt-bindings: PCI: qcom: Document the X1E80100 PCIe Controller c779c938fb22 dt-bindings: pinctrl: qcom: update compatible name for match with driver 98b8ca8bcb74 dt-bindings: input: atmel,captouch: convert bindings to YAML f4627ef4c35c dt-bindings: i2c: nomadik: add mobileye,eyeq5-i2c bindings and example e6a7453cf514 Merge tag 'wireless-next-2024-03-08' of git://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next 826587e76776 dt-bindings: PCI: qcom: Do not require 'msi-map-mask' e776ecb01509 dt-bindings: PCI: qcom: Allow 'required-opps' 41c94df7b508 dt-bindings: auxdisplay: Add bindings for generic 7-segment LED 51ec88485bd0 dt-bindings: rtc: zynqmp: Add support for Versal/Versal NET SoCs 4a0688c342c5 dt-bindings: rtc: abx80x: Improve checks on trickle charger constraints 09ed5b86a7c0 Merge branches 'arm/mediatek', 'arm/renesas', 'arm/smmu', 'x86/vt-d', 'x86/amd' and 'core' into next 1ca49df08091 dt-bindings: net: dp83822: change ti,rmii-mode description 9e691f2ca146 Merge tag 'drm-msm-next-2024-03-07' of https://gitlab.freedesktop.org/drm/msm into drm-next cfe04ff5f8c9 dt-bindings: serial: stm32: add power-domains property b072a75f7faf dt-bindings: nvmem: add common definition of nvmem-cell-cells be64edb74cf7 dt-bindings: nvmem: Convert xlnx,zynqmp-nvmem.txt to yaml baca151add1c nvmem: fixed-cell: Simplify nested if/then schema 1c0b231f57e0 dt-bindings: hwmon: Support Aspeed g6 PWM TACH Control a0c034ed370f dt-bindings: hwmon: fan: Add fan binding to schema 5f3df8a26d1e dt-bindings: hwmon: tda38640: Add interrupt & regulator properties ea5fd00e7566 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net 1cd0ddec1f0e dt-bindings: timer: mediatek: Convert to json-schema 4a513c9ee434 ASoC: codecs: ES8326: change support for ES8326 9428855666bf dt-bindings: backlight: qcom-wled: Fix bouncing email addresses ded680d1011e dt-bindings: leds: Add NCP5623 multi-LED Controller 36c053ec1940 dt-bindings: leds: qcom-lpg: Narrow nvmem for other variants 86d79b6e9034 dt-bindings: leds: qcom-lpg: Drop redundant qcom,pm8550-pwm in if:then: 0d9351b5397b dt-bindings: leds: Add LED_FUNCTION_WAN_ONLINE for Internet access 00b899276322 dt-bindings: leds: Add FUNCTION defines for per-band WLANs 0d85184c07f6 dt-bindings: leds: leds-qcom-lpg: Add support for LPG PPG b4ab63101636 Merge branches 'ib-qcom-leds-6.9' and 'ib-leds-backlight-6.9' into ibs-for-leds-merged 3555e8d0b9fc dt-bindings: backlight: Add Kinetic KTD2801 binding a8c949969077 Merge branch 'ib-nomadik-gpio' into devel 62c3262f7fe3 dt-bindings: net: renesas,etheravb: Add support for R-Car V4M 918ae23afab4 dt-bindings: interrupt-controller: fsl,intmux: Include power-domains support e53ec66488c1 Merge tag 'icc-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next 1f0e4fc46ee7 Merge tag 'qcom-arm64-for-6.9-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt ea75705aeacc Merge tag 'riscv-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/late 584c83fce20d dt-bindings: remoteproc: qcom,sm8550-pas: document the X1E80100 aDSP & cDSP c04e94fc3b79 dt-bindings: remoteproc: do not override firmware-name $ref 4b39a7e1c39f dt-bindings: remoteproc: qcom,glink-rpm-edge: drop redundant type from label e6ec88170ffc dt-bindings: pinctrl: Add bindings for Awinic AW9523/AW9523B fc76e2ec0af9 spi: dt-bindings: introduce FIFO depth properties 649423f8a081 ASoC: dt-bindings: rt1015: Convert to dtschema 7a4e8175bafb riscv: dts: starfive: jh7100: fix root clock names eed1e7dce0c5 Merge tag 'ath-next-20240305' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath b77c6d6ecd26 Merge tag 'v6.8-rc7' into gpio/for-next b6f4257e837d dt-bindings: input: allwinner,sun4i-a10-lrad: drop redundant type from label ab13fd756619 dt-bindings: fsl-imx-sdma: fix HDMI audio index 8183e8af3de8 dt-bindings: soc: imx: fsl,imx-iomuxc-gpr: add imx6 364eb93f21bc dt-bindings: soc: imx: fsl,imx-anatop: add binding 0d6b9633b62c dt-bindings: input: touchscreen: fsl,imx6ul-tsc convert to YAML e24d180df3e3 dt-bindings: pinctrl: fsl,imx6ul-pinctrl: convert to YAML c6cb9528755c Merge tag 'v6.9-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt 1541b5f7169a dt-bindings: usb: typec-tcpci: add tcpci fallback binding 30cfb408e45f dt-bindings: usb: Add downstream facing ports to realtek binding ba19f225f401 dt-bindings: usb: Add binding for TI USB8020B hub controller c3251302f8d3 dt-bindings: usb: analogix,anx7411: drop redundant connector properties c6425032f69e dt-bindings: usb: add hisilicon,hi3798mv200-dwc3 a1bd84637b96 dt-bindings: mmc: hisilicon,hi3798cv200-dw-mshc: add Hi3798MV200 binding 7fc53b04c1ea dt-bindings: mmc: dw-mshc-hi3798cv200: convert to YAML f1338ec7ac44 dt-bindings: i2c: mpc: use proper binding for transfer timeouts 78ad26b5f48f dt-bindings: interrupt-controller: Convert Atmel AIC to json-schema 99d17f43c09c Merge tag 'reset-for-v6.9' of git://git.pengutronix.de/pza/linux into soc/late 14c572ddf1f9 Merge tag 'omap-for-v6.9/dt-warnings-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into soc/late 04cdefa63030 Merge tag 'vexpress-update-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/dt 8100aecad25e ARM: dts: samsung: exynos4412: decrease memory to account for unusable region 44ffff36c17a Merge tag 'ti-keystone-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt 38d2af77456f Merge tag 'memory-controller-drv-6.9-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers 4b3d3727fe21 Merge tag 'qcom-drivers-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers 1390bca92db4 spi: dt-bindings: samsung: make dma properties not required f3f062800bf5 dt-bindings: perf: starfive: Add JH8100 StarLink PMU 8ade2ed03067 dt-bindings: usb: qcom,pmic-typec: add support for the PM4125 block ffd54b03300e dt-bindings: leds: pwm-multicolour: re-allow active-low 2bd3e3e38b19 dt-bindings: imx6q-pcie: Add iMX95 pcie endpoint compatible string a1a33ad5df89 dt-bindings: imx6q-pcie: Add imx95 pcie compatible string d5b3866ee39c dt-bindings: imx6q-pcie: Restruct reg and reg-name 17964120885e dt-bindings: imx6q-pcie: Clean up duplicate clocks check b2e87666166c Merge tag 'qcom-arm32-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt d6f0d6fbd771 Merge tag 'v6.9-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt 9beae6e4f5b2 Merge tag 'v6.9-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt bfa16e672f23 Merge tag 'riscv-sophgo-dt-for-v6.9' of https://github.com/sophgo/linux into soc/dt b9a523277cff Merge tag 'mvebu-dt64-6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt 472acadc4b85 Merge tag 'mvebu-dt-6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt a1c9c09fe4c6 Merge tag 'renesas-dt-bindings-for-v6.9-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt ed9768f823d1 Merge tag 'stm32-dt-for-v6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt a93afb6c68a1 arm64: dts: qcom: sm8250-xiaomi-elish: set rotation c1d25c9b315c arm64: dts: qcom: sm8650: Fix SPMI channels size f203c283f5bb arm64: dts: qcom: sm8550: Fix SPMI channels size 6b3cdc5e247c Merge tag 'drm-misc-next-2024-02-29' into msm-next 0ccaa0050371 dt-bindings: input/touchscreen: imagis: add compatible for IST3032C f4cd9022dce6 dt-bindings: input/touchscreen: Add compatible for IST3038B 147eff3c7cff dt-bindings: watchdog: sama5d4-wdt: add compatible for sam9x7-wdt 3a9200687cf7 dt-bindings: watchdog: sprd,sp9860-wdt: convert to YAML cbe08f41aa59 dt-bindings: watchdog: starfive,jh7100-wdt: Add compatible for JH8100 be02d67086d9 dt-bindings: watchdog: arm,sp805: document the reset signal 201c69876dc6 dt-bindings: watchdog: renesas-wdt: Add support for R-Car V4M 653594df87d5 dt-bindings: serial: convert st,asc to DT schema 1a0b7e8acef8 powerpc: dts: akebono: Harmonize EHCI/OHCI DT nodes name 8d179c0b54fb dt-bindings: usb: qcom,dwc3: fix a typo in interrupts' description c630e9b5a72f arm64: dts: qcom: pm6150: define USB-C related blocks da1d13674619 dt-bindings: usb: qcom,pmic-typec: Add support for the PM6150 PMIC d3864961a639 Merge tag 'w1-drv-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-w1 into tty-next 8f130bd54c7b Merge tag 'iio-for-6.9b' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next 20d54e06e2a3 Merge tag 'coresight-next-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux into char-misc-next c326cc675c68 arm64: dts: rockchip: Fix name for UART pin header on qnap-ts433 3965a283125e dt-bindings: pwm: amlogic: Add a new binding for meson8 pwm types d397107f4e3a dt-bindings: pwm: amlogic: fix s4 bindings 6d25cc8fd5da dt-bindings: i2c: Remove obsolete i2c.txt 59488a1b3652 dt-bindings: arm: syna: remove unstable remark 1d325ff1ed92 dt-bindings: net: bluetooth: qualcomm: Fix bouncing @codeaurora 9f1d679268ba dt-bindings: watchdog: drop obsolete brcm,bcm2835-pm-wdt bindings 090fc268fac4 dt-bindings: watchdog: qcom-wdt: Update maintainer to Rajendra Nayak 0451b0796a61 dt-bindings: hwmon: lm75: use common hwmon schema 371142306400 Merge tag 'amlogic-arm64-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt 0e7fe10bc9e6 Merge tag 'amlogic-arm-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt d0cb807cfef4 Merge tag 'omap-for-v6.9/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into soc/dt 3578f1b6dbed Merge tag 'ti-k3-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt d68c28418b67 riscv: dts: starfive: jh7110: Add camera subsystem nodes aa86c303373a arm: dts: marvell: clearfog-gtr-l8: align port numbers with enclosure ae315320f5d1 arm: dts: marvell: clearfog-gtr-l8: add support for second sfp connector 6330d58dd4fe dt-bindings: soc: renesas: renesas-soc: Add pattern for gray-hawk 1a4325f9d215 Merge tag 'arm-smmu-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into arm/smmu 6d23cfa8897b Merge tag 'at91-dt-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt 7632a364f33e Merge tag 'zynqmp-dt-for-6.9' of https://github.com/Xilinx/linux-xlnx into soc/dt 02eba1b4512a Merge tag 'sgx-for-v6.9-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into soc/dt c0d63be31667 Merge tag 'imx-dt64-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt 0d1bd814646e Merge tag 'imx-dt-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt fcd3ba0ec7e6 Merge tag 'imx-bindings-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt 911a0e5da311 Merge tag 'socfpga_dts_updates_for_v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt fec957a967a1 dt-bindings: rng: atmel,at91-trng: add sam9x7 TRNG f25a9445fef8 dt-bindings: crypto: add sam9x7 in Atmel TDES 8790f16edade dt-bindings: crypto: add sam9x7 in Atmel SHA 44266f1d25b2 dt-bindings: crypto: add sam9x7 in Atmel AES 2b1ebc6d769d Merge tag 'qcom-arm64-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt 43a56bf3bdaf Merge tag 'sunxi-dt-for-6.9-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt e19434848bd8 Merge tag 'drm-msm-next-2024-02-29' of https://gitlab.freedesktop.org/drm/msm into drm-next 01321d44f1ec dt-bindings: net: brcm,asp-v2.0: Add asp-v2.2 d5a543a359ce dt-bindings: net: brcm,unimac-mdio: Add asp-v2.2 089e8a0b0394 dt-bindings: gpio: aspeed,ast2400-gpio: Convert to DT schema 925e183d1d3e Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net c44ea78dc972 dt-bindings: rtc: abx80x: convert to yaml 3a25f24b71ce dt-bindings: at91rm9260-rtt: add sam9x7 compatible 6ae5f27fcef7 dt-bindings: rtc: convert MT7622 RTC to the json-schema 8e6eb376128e dt-bindings: rtc: convert MT2717 RTC to the json-schema dffd03e7b3c3 Merge branch 'icc-sm7150' into icc-next f8afb1ebc676 dt-bindings: interconnect: Add Qualcomm SM7150 DT bindings 253a470f5420 dt-bindings: mfd: syscon: Add ti,am62-usb-phy-ctrl compatible f689de1b40f9 dt-bindings: mfd: dlg,da9063: Make #interrupt-cells required a029ec8c35c4 Merge tag 'tegra-for-6.9-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt cbda1f9ca478 Merge tag 'tegra-for-6.9-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt 061a7ef8ce88 Merge tag 'tegra-for-6.9-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt 2788cdbbf836 Merge tag 'renesas-dts-for-v6.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt af467f28aa2e Merge tag 'renesas-dt-bindings-for-v6.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt e422e34ebe7a Merge tag 'v6.9-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt 15643f4b8b71 Merge tag 'v6.9-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt 3b71bcf355d9 Merge tag 'versatile-dts-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into soc/dt d73cece0601b Merge tag 'gemini-dts-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into soc/dt d5e822510e6a Merge tag 'mtk-dts64-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt 88c6586d8ddc Merge tag 'dt-cleanup-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt 485c27391cf2 Merge tag 'samsung-dt-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt 9a55de21e5e8 Merge tag 'samsung-dt64-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt 7fe0c3cf50e7 Merge tag 'renesas-dts-for-v6.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt a28ccc2c8a1e Merge tag 'renesas-dt-bindings-for-v6.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt 3a1d10b8a7ea dt-bindings: pinctrl: at91: add sam9x7 25fa45a7091a arm64: dts: st: add video encoder support to stm32mp255 374df3f7a69d arm64: dts: st: add video decoder support to stm32mp255 f1523e3d07c3 dt-bindings: gpio: nomadik: add optional reset property 7c456af0e520 dt-bindings: gpio: nomadik: add mobileye,eyeq5-gpio compatible 6412671654fb dt-bindings: gpio: nomadik: add optional ngpios property 33796ff4220d dt-bindings: gpio: nomadik: convert into yaml format e5443d45c0ec ARM: dts: stm32: enable crypto accelerator on stm32mp135f-dk fdf13e6831f2 ARM: dts: stm32: enable CRC on stm32mp135f-dk b5c98471fd1a ARM: dts: stm32: add CRC on stm32mp131 f454b7a85920 dt-bindings: pinctrl: mobileye,eyeq5-pinctrl: add bindings e03c12f18d62 ARM: dts: add stm32f769-disco-mb1166-reva09 690f4c3b681a ARM: dts: stm32: add display support on stm32f769-disco 4cb81b91ac87 ARM: dts: stm32: rename mmc_vcard to vcc-3v3 on stm32f769-disco 82d1ed24df95 ARM: dts: stm32: add DSI support on stm32f769 c8114c09da2c dt-bindings: mfd: stm32f7: Add binding definition for DSI 363d4a9715e5 dt-bindings: nt35510: document 'port' property 9059c18b6d10 dt-bindings: iio: gyroscope: bosch,bmg160: add spi-max-frequency ebcb39d7a66e dt-bindings: iio: adc: imx93: drop the 4th interrupt 2f1ec66e6c94 dt-bindings: iio: adc: drop redundant type from label d24619ffe43c dt-bindings: iio: ti,tmp117: add optional label property 633fffb7c377 dt-bindings: iio: magnetometer: Add Voltafield AF8133J a36a9e62abdf dt-bindings: vendor-prefix: Add prefix for Voltafield 2ef6443e1743 dt-bindings: iio: light: vishay,veml6075: make vdd-supply required c9c055c5470f dt-bindings: iio: adc: adding support for PAC193X a288cab1e5a6 dt-bindings: iio: hmc425a: add entry for LTC6373 43172d694644 dt-bindings: iio: hmc425a: add conditional GPIO array size constraints 42707bcbabe0 dt-bindings: iio: humidity: hdc20x0: add optional interrupts property 49676274cbd7 dt-bindings: iio: ti,tmp117: add vcc supply binding 6dafe28e7298 dt-bindings: mmc: fsl-imx-mmc: Document the required clocks 620fcff9d53c spi: dt-bindings: atmel,at91rm9200-spi: remove 9x60 compatible from list 22502bd8725d dt-bindings: mmc: fsl-imx-esdhc: add default and 100mhz state a3da0bec1dd6 arm64: dts: rockchip: Add basic support for QNAP TS-433 e5d58e2bc9d5 dt-bindings: arm: rockchip: Add QNAP TS-433 78b9bf1a6128 arm64: dts: rockchip: add Haikou baseboard with RK3588-Q7 SoM 2ffa10c5e5ad arm64: dts: rockchip: add RK3588-Q7 (Tiger) SoM 7009dfbb88d7 dt-bindings: arm: rockchip: Add Theobroma-Systems RK3588 Q7 with baseboard 2516daa7bde5 arm64: dts: rockchip: drop rockchip,trcm-sync-tx-only from rk3588 i2s fc876128d301 dt-bindings: net: ethernet-controller: drop redundant type from label 13ab34ef0793 arm64: dts: rockchip: fix reset-names for rk356x i2s2 controller 883bb3a0ffc9 arm64: dts: rockchip: add missing interrupt-names for rk356x vdpu eec8be52f681 arm64: dts: rockchip: add clock to vo1-grf syscon on rk3588 103ec967103c dt-bindings: net: dsa: realtek: add reset controller 3018a826c97d dt-bindings: net: dsa: realtek: reset-gpios is not required 6dc9f167486c dt-bindings: arm: rockchip: Add Toybrick TB-RK3588X a181bc600877 arm64: dts: rockchip: Add devicetree support for TB-RK3588X board cc35d14ce704 ARM: dts: rockchip: Wifi improvements for Sonoff iHost d3e564c6f34a ARM: dts: rockchip: mmc aliases for Sonoff iHost ca5df862ea65 arm64: dts: rockchip: adjust vendor on orangepi rk3399 board ed51c83e418c arm64: dts: rockchip: adjust vendor on Banana Pi R2 Pro board cff456e5f266 dt-bindings: arm: rockchip: Correct vendor for Banana Pi R2 Pro 3522950a8c39 dt-bindings: arm: rockchip: Correct vendor for Orange Pi RK3399 board 82a17c8827d1 arm64: dts: rockchip: Add HDMI0 PHY to rk3588 e66d1e81aed1 arm64: dts: armada-ap807: update thermal compatible 1d32f2a19cc3 arm64: dts: marvell: reorder crypto interrupts on Armada SoCs 35290ca22165 arm64: dts: ac5: add mmc node and clock f5ba7df64a26 arm: dts: marvell: clearfog-gtr: add missing pinctrl for all used gpios a64c072c8b1d arm: dts: marvell: clearfog-gtr: sort pinctrl nodes alphabetically 57a80269cb6c arm: dts: marvell: clearfog-gtr: add board-specific compatible strings 9f7d319ef30b arm: dts: marvell: clearfog: add pro variant compatible in legacy dts ee29a2404550 dt-bindings: marvell: a38x: add solidrun armada 385 clearfog gtr boards a94644e247d1 dt-bindings: marvell: a38x: add kobol helios-4 board 977f211a8ee3 dt-bindings: marvell: a38x: add solidrun armada 388 clearfog boards 6fe97bf74341 dt-bindings: marvell: a38x: convert soc compatibles to yaml 313957b8c112 Merge branch 'v6.9-shared/clkids' into v6.9-armsoc/dts64 e0f54133c394 dt-bindings: clock: rk3588: add missing PCLK_VO1GRF e32d677022ca dt-bindings: clock: rk3588: drop CLK_NR_CLKS 4b58a7ccfd97 Merge tag 'mt76-for-kvalo-2024-02-22' of https://github.com/nbd168/wireless 479c5ca5c8ae dt-bindings: arm: amlogic: add Neil, Martin and Jerome as maintainers 39d812837cdd dt-bindings: arm: amlogic: remove unstable remark 54469d99a2af dt-bindings: mmc: sdhci-of-dwcmhsc: Add Sophgo CV1800B and SG2002 support f4bffe85d2e7 dt-bindings: arm: qcom,coresight-tpdm: Rename qcom,dsb-element-size 7c2c6922effb dt-bindings: memory-controller: st,stm32: add MP25 support b3f6be88f1f5 Merge 6.8-rc6 into tty-next f4288db518a8 dt-bindings: net: cdns,macb: add sam9x7 ethernet interface 5315d5ea1db7 dt-bindings: i2c: at91: Add sam9x7 compatible string b99dd7ccd5b8 dt-bindings: i2c: imx-lpi2c: add i.MX95 LPI2C d377e1b8336c Convert some regulator drivers to GPIO descriptors d5220c4662fe dt-bindings: auxdisplay: Add Maxim MAX6958/6959 2f25ffe9d998 dt-bindings: arm-smmu: Document SM8650 GPU SMMU b4c3aaf580d9 dt-bindings: arm-smmu: fix SM8[45]50 GPU SMMU if condition 0abc1ff2be4e dt-bindings: display/msm/gmu: Document Adreno 750 GMU ec4f0c02c1ec dt-bindings: display/msm: gpu: Allow multiple digits for patchid 49915776f063 dt-bindings: lcdif: Do not require power-domains for i.MX6ULL a2a81ebc850d dt-bindings: timer: Add support for cadence TTC PWM 0a54c5eb5a02 Merge tag 'renesas-pinctrl-for-v6.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel f12177200edc dt-bindings: interrupt-controller: Add starfive,jh8100-intc 99b3211ce73c regulator: dt-bindings: gpio-regulator: Fix "gpios-states" and "states" array bounds ca5cca640867 ARM: dts: omap4-panda-common: Enable powering off the device 6b4a8eca637d ARM: dts: omap-embt2ws: system-power-controller for bt200 87c4cebd8708 ARM: dts: omap: Switch over to https:// url 80adf5afe7f6 ARM: dts: ti: omap: add missing abb_{mpu,ivahd,dspeve,gpu} unit addresses for dra7 SoC a446d52725b5 ARM: dts: ti: omap: add missing sys_32k_ck unit address for dra7 SoC 4d96b742cb3e ARM: dts: ti: omap: add missing phy_gmii_sel unit address for dra7 SoC 7f22c5d06f8d dt-bindings: net: dp83822: support configuring RMII master/slave mode 5a411c0575cc ARM: dts: omap3: Update clksel clocks to use reg instead of ti,bit-shift 43768eba3fa4 ARM: dts: am3: Update clksel clocks to use reg instead of ti,bit-shift 0f8d14846135 Merge v6.8-rc6 into drm-next 5ac99b57e27a dt-bindings: mtd: brcmnand: Add ecc strap property d973f6e60329 dt-bindings: mtd: brcmnand: Add WP pin connection property e8cf96a62e99 dt-bindings: mtd: brcmnand: Updates for bcmbca SoCs 4284b95c3a7d dt-bindings: mtd: st,stm32: add MP25 support 5ffc0c6588e1 dt-bindings: mtd: update references from partition.txt to mtd.yaml 079feabfa500 arm64: dts: ti: hummingboard-t: add overlays for m.2 pci-e and usb-3 77aac4df148c arm64: dts: add description for solidrun am642 som and evaluation board bab419b95c2c dt-bindings: arm: ti: Add bindings for SolidRun AM642 HummingBoard-T bc85817742eb dt-bindings: mtd: spi-nor: add optional interrupts property 201ac0128678 dt-bindings: pwm: opencores: Add compatible for StarFive JH8100 c0aae9685a91 dt-bindings: riscv: cpus: reg matches hart ID 8e0b9c610742 dt-bindings: bus: imx-weim: convert to YAML c622150ed65c Merge v6.8-rc6 into usb-next 09994ac519e2 arm64: dts: imx8mm-kontron-bl-osm-s: Fix Ethernet PHY compatible c8b82b8dd480 arm64: dts: imx8-apalis-v1.1: Remove reset-names from ethernet-phy 20cdb2916423 ARM: dts: nxp: imx: fix weim node name 064185347fff ARM: dts: nxp: imx6ul: fix touchscreen node name 42a236fd930d ARM: dts: nxp: imx6ul: xnur-gpio -> xnur-gpios d9725dc952ee ARM: dts: imx6ul: Remove fsl,anatop from usbotg1 6cc27853e1c4 ARM: dts: imx6ull: fix pinctrl node name c23b15b18c81 ARM: dts: imx1-apf9328: Fix Ethernet node name 7c8b8cf4dd15 ARM: dts: imx28-evk: Use 'eeprom' as the node name 102744f8003d ARM: dts: ls1021a: Enable usb3-lpm-capable for usb3 node 4822eab2af53 Merge branch 'icc-cleanup' into icc-next 0b20018b1dbc dt-bindings: mtd: ubi-volume: allow UBI volumes to provide NVMEM 5d1f49b1b6b0 dt-bindings: mtd: add basic bindings for UBI 9a35e12f4b1a dt-bindings: hwmon: reference common hwmon schema 3d36f23ac624 dt-bindings: hwmon: lltc,ltc4286: use common hwmon schema 798f72d666b8 dt-bindings: hwmon: adi,adm1275: use common hwmon schema 809baabdec34 dt-bindings: hwmon: ti,ina2xx: use common hwmon schema 42d06958b709 dt-bindings: hwmon: add common properties f567e7a0ce93 regulator: dt-bindings: promote infineon buck converters to their own binding b1715c2bbc33 dt-bindings: hwmon/pmbus: ti,lm25066: document regulators 0c5601d53cce dt-bindings: hwmon: nuvoton,nct6775: Add compatible value for NCT6799 fb5eada36609 dt-bindings: trivial-devices: add Astera Labs PT5161L 7d3134823476 dt-bindings: vendor-prefixes: add asteralabs c75f1a591ccd dt-bindings: hwmon: Add Amphenol ChipCap 2 737f7b7c7c23 dt-bindings: vendor-prefixes: add Amphenol 380e45011084 dt-bindings: Add MPQ8785 voltage regulator device adb144c788f3 dt-bindings: clock: exynos850: Add CMU_CPUCLK0 and CMU_CPUCL1 77ced3f45487 dt-bindings: arm: add UNI-T UTi260B 521023b8972b dt-bindings: vendor-prefixes: add UNI-T 10a08d63eb50 arm64: dts: imx8mp-evk: Fix hdmi@3d node 96099eef1a2c arm64: dts: imx93-var-som: Remove phy-supply from eqos 0ee187cdb35f Merge tag 'iio-for-6.9a' of http://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next 9aa0ba8c3e6a arm64: dts: imx8mp-phyboard-pollux: Disable pull-up for CD GPIO 195bcec93c44 arm64: dts: imx8mp-phyboard-pollux: Reduce drive strength for eqos tx lines adb0eb622cec arm64: dts: imx8mp-phyboard-pollux: Set debug uart muxing to 0x140 8032acfdf1a8 arm64: dts: imx8mp-phyboard-pollux: Add and update rtc devicetree node 9ffab265f1ac arm64: dts: imx8mm-evk: Add spdif sound card support 3f1b2e8d9e29 arm64: dts: mba8xx: Add missing #interrupt-cells dd5af1f60a28 arm64: dts: imx8mp: Set SPI NOR to max 40 MHz on Data Modul i.MX8M Plus eDM SBC f461418b3107 ARM: dts: imx6dl-yapp4: Move the internal switch PHYs under the switch node dbaddd2cc383 ARM: dts: imx6dl-yapp4: Fix typo in the QCA switch register address 6a28d56cd75a arm64: dts: imx8mn: tqma8mqnl-mba8mx: Add USB DR overlay 68f02dd7e55f arm64: dts: imx8mq: tqma8mq-mba8mx: Add missing USB vbus supply 06e63f07db24 arm64: dts: freescale: imx8mm/imx8mq: mba8mx: Use PCIe clock generator 65f27cc9ca1b arm64: dts: imx8mn-beacon: Remove unnecessary clock configuration ec091103f662 arm64: dts: imx8mn: Slow default video_pll clock rate f3ed68d12445 arm64: dts: imx8mp-beacon: Configure multiple queues on eqos 825a35212289 arm64: dts: imx8mp-beacon: Enable Bluetooth e32a570a61aa ARM: dts: imx6ul: Set macaddress location in ocotp 48b05a3282bd arm64: dts: freescale: minor whitespace cleanup 4b0cf920e774 arm64: dts: allwinner: h616: Add thermal sensor and zones d0665f60cec0 ARM: dts: sun8i: Open FETA40i-C regulator aldo1 f0c099b60ae3 arm64: dts: allwinner: h616: Add Sipeed Longan SoM 3H and Pi 3H board support 01ae6c03a880 dt-bindings: arm: sunxi: Add Sipeed Longan Module 3H and Longan Pi 3H c763b1cf0ca7 arm64: dts: allwinner: h616: minor whitespace cleanup fba9e58bbd03 arm64: dts: allwinner: use capital "OR" for multiple licenses in SPDX c6b7cf5d4b69 arm64: dts: allwinner: Transpeed 8K618-T: add WiFi nodes 13d73fcac8c9 arm64: dts: allwinner: h616: Add 32K fanout pin 05bdbb1eb3fd arm64: dts: allwinner: Add Jide Remix Mini PC support 0df51b232403 dt-bindings: arm: sunxi: document Remix Mini PC name 898b36322bb2 dt-bindings: vendor-prefixes: add Jide 70e735bb236e arm64: dts: allwinner: h616: Add SPDIF device node 10969c04cb6e arm64: dts: allwinner: h616: Add DMA controller and DMA channels c5182cdc0aa8 arm64: dts: allwinner: h6: Add RX DMA channel for SPDIF e31d5ca612d6 dt-bindings: sram: narrow regex for unit address to hex numbers 013b1096017d ARM: dts: microchip: sama7g5: add sama7g5 compatible 782f527e1b30 ARM: dts: microchip: sam9x60: align dmas to the opening '<' d08950521775 ARM: dts: microchip: sama7g5: align dmas to the opening '<' c9cdb533541e ARM: dts: microchip: sama7g54_curiosity: Add initial device tree of the board 28a13f689e75 ARM: dts: microchip: sama7g5: Add flexcom 10 node 57fb3296fc2d ASoC: dt-bindings: microchip: add sam9x7 81a8f19d991d ASoC: dt-bindings: atmel-classd: add sam9x7 compatible c1e8427eb3df dt-bindings: ARM: at91: Document Microchip SAMA7G54 Curiosity 708077cf30a4 arm64: tegra: Remove Jetson Orin NX and Jetson Orin Nano DTSI 14b1c490371e arm64: tegra: Add audio support for Jetson Orin NX and Jetson Orin Nano 5bdc0a8fed68 arm64: tegra: Define missing IO ports 8ff1bf770a0c arm64: tegra: Move AHUB ports to SoC DTSI 9fd53de0ed30 arm64: tegra: Add USB Type-C controller for Jetson AGX Xavier 6c9a92242095 arm64: tegra: Add USB device support for Jetson AGX Xavier 495a87da7a47 arm64: tegra: Add current monitors for Jetson Xavier 426c1ddbd76b arm64: tegra: Add AXI configuration for Tegra234 MGBE 134b7a20eea2 dt-bindings: mfd: Convert atmel-flexcom to json-schema 7268c6969288 dt-bindings: mfd: cros-ec: Add properties for GPIO controller a5c0c33c25f1 dt-bindings: mfd: ti,twl: Document system-power-controller 507cf9210c91 dt-bindings: net: wireless: qcom: Update maintainers a9219f105d93 dt-bindings: mfd: syscon: Add ti,am654-serdes-ctrl compatible 37c3dbbbca5d dt-bindings: mfd: syscon: Add ti,j784s4-pcie-ctrl compatible ef9712ce90c9 dt-bindings: mfd: atmel,hlcdc: Convert to DT schema format fc3911fb624f dt-bindings: mfd: qcom,tcsr: Add compatibles for QCM2290 and SM6115 bcc7a549de96 dt-bindings: mfd: iqs62x: Do not override firmware-name $ref e3889bfdf9d5 dt-bindings: media: rkisp1: Add i.MX8MP ISP to compatible e7d16b884c9d dt-bindings: timer: add Ralink SoCs system tick counter f4535baea464 dt-bindings: PCI: qcom,pcie-sa8775p: Move SA8775p to dedicated schema 169fa31aecaa dt-bindings: PCI: qcom,pcie-sc7280: Move SC7280 to dedicated schema 9a6e22b46113 dt-bindings: PCI: qcom,pcie-sc8180x: Move SC8180X to dedicated schema e114fb24a186 dt-bindings: PCI: qcom,pcie-sc8280xp: Move SC8280XP to dedicated schema 88e9e05efe99 dt-bindings: PCI: qcom,pcie-sm8350: Move SM8350 to dedicated schema 977832dca6ab dt-bindings: PCI: qcom,pcie-sm8150: Move SM8150 to dedicated schema 53908f6ff54c dt-bindings: PCI: qcom,pcie-sm8250: Move SM8250 to dedicated schema 96931e6b08ab dt-bindings: PCI: qcom,pcie-sm8450: Move SM8450 to dedicated schema 3c9f28bcffc2 dt-bindings: PCI: qcom,pcie-sm8550: Move SM8550 to dedicated schema c2f1d4a9447a arm64: dts: renesas: rzg2l-smarc: Enable DU and link with DSI b39f9a0e920d arm64: dts: renesas: r9a07g054: Add DU node 3ecd2f1980c9 arm64: dts: renesas: r9a07g044: Add DU node 93d319ea783c arm64: dts: lx2160a: Fix DTS for full PL011 UART 8365edf2f65e arm64: dts: ls1088a: Add the PME interrupt for PCIe EP node 084a47a95058 arm64: dts: imx8qm: add i2c1 for imx8qm-mek board d84b45a3c712 arm64: dts: imx8qm: add i2c4 and i2c4_lpcg node 9d3bb1c53622 ASoC: Revert "ASoC: dt-bindings: Update example for enabling USB offload on SM8250" 7ada2cb724f2 riscv: dts: add resets property for uart node a034d20d33af riscv: dts: add reset generator for Sophgo SG2042 SoC b312f7c28451 ARM: dts: imx53-qsb: add support for the HDMI expander 65d763356aad arm64: dts: imx8mp: Enable SAI audio on Data Modul i.MX8M Plus eDM SBC c3b757a52529 arm64: dts: imx8: Fix lpuart DMA channel order a9c570888e1c arm64: dts: freescale: imx8-ss-dma: Fix edma3's location 1880684dfc18 arm64: dts: imx8dxl update edma0 information 95a51114540e arm64: dts: imx8dxl: add fsl-dma.h dt-binding header file 87cc839ce871 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net 595539769055 dt-bindings: vendor-prefixes: Add missing prefixes used in compatibles 2b8f61f2af78 dt-bindings: display: convert Atmel's HLCDC to DT schema d4e9fb508b98 dt-bindings: display/msm: Document MDSS on X1E80100 26ae54a934e7 dt-bindings: display/msm: Document the DPU for X1E80100 eec4611e4fa5 dt-bindings: arm-smmu: Document SM8650 GPU SMMU 011fc2593f52 dt-bindings: arm-smmu: Fix SM8[45]50 GPU SMMU 'if' condition f45f80911a1e ARM: tegra: Add device-tree for LG Optimus 4X HD (P880) c99ab6147bdd ARM: tegra: Add device-tree for LG Optimus Vu (P895) 9668ead0c4a9 ARM: tegra: nexus7: Add missing clock binding into sound node 1a7c7ca1209d dt-bindings: arm: tegra: Add LG Optimus Vu P895 and Optimus 4X P880 55fa85648879 arm64: dts: Add gpio_intc node for Amlogic-T7 SoCs 3040579f9058 dt-bindings: interrupt-controller: Add support for Amlogic-T7 SoCs ac30a4ade02e dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update interrupts cf713971ea71 dt-bindings: arm-smmu: Add QCM2290 GPU SMMU cfbcf932a683 arm64: dts: renesas: gray-hawk-single: Add QSPI FLASH support 7b0d1d64e101 arm64: dts: renesas: r8a779h0: Add RPC node cf8ea631a9d7 arm64: dts: renesas: r8a779h0: Add DMA support 44de0122e321 arm64: dts: renesas: gray-hawk-single: Add eMMC support 697c226a4355 arm64: dts: renesas: r8a779h0: Add SD/MMC node bc3ce3810946 ARM: dts: renesas: r8a7778: Add missing reg-names to sound node 59d2898af1c8 arm64: dts: renesas: rzg2ul-smarc: Enable CRU, CSI support e4684cc943fe arm64: dts: renesas: gray-hawk-single: Add Ethernet support 08896ba8e650 arm64: dts: renesas: r8a779h0: Add Ethernet-AVB support fe2d22e4ae91 arm64: dts: renesas: r8a779g0: Correct avb[01] reg sizes 4c2e92819772 arm64: dts: renesas: r8a779a0: Correct avb[01] reg sizes d857aea85b27 arm64: dts: renesas: r9a08g045: Add PSCI support ac45f97b1f9c arm64: dts: renesas: rzg3s-smarc-som: Guard Ethernet IRQ GPIO hogs aef97a58051b arm64: dts: renesas: r9a08g045: Add missing interrupts to IRQC node 68b5a3b20687 arm64: dts: renesas: rzg2l: Add missing interrupts to IRQC nodes 5a4108c215f6 arm64: dts: renesas: r8a779h0: Add CA76 operating points bd25260cfef9 arm64: dts: renesas: r8a779h0: Add CPU core clocks 291552f30777 arm64: dts: renesas: r8a779h0: Add CPUIdle support 20170eff3c40 arm64: dts: renesas: r8a779h0: Add secondary CA76 CPU cores 4c3851d7302a arm64: dts: renesas: r8a779h0: Add L3 cache controller 149125c48481 arm64: dts: renesas: r8a779h0: Add GPIO nodes e6842397bea1 arm64: dts: renesas: gray-hawk-single: Add I2C0 and EEPROMs 4ab7a0fae505 arm64: dts: renesas: r8a779h0: Add I2C nodes 4f678406736f arm64: dts: renesas: ulcb-kf: Adapt sound 5v regulator to schematics ab5123a5fcbb arm64: dts: renesas: ulcb-kf: Adapt 1.8V HDMI regulator to schematics 36bd3f79100c arm64: dts: renesas: ulcb-kf: Add regulators for PCIe ch1 d79c233e5296 arm64: dts: renesas: gray-hawk-single: Add serial console pin control adb055f45503 arm64: dts: renesas: r8a779h0: Add pinctrl device node 393149daa9ec dt-bindings: net: wireless: mt76: allow all 4 interrupts for MT7981 abc93201d108 dt-bindings: net: wireless: mt76: add interrupts description for MT7986 6ff46183ee46 dt-bindings: memory: renesas,rpc-if: Document R-Car V4M support caaf33bab010 dt-bindings: reset: mobileye,eyeq5-reset: add bindings d627a28b5d6f dt-bindings: clock: mobileye,eyeq5-clk: add bindings ebd3bcd073ce dt-bindings: clock: ast2600: Add FSI clock d19d06cdbb21 dt-bindings: reset: mediatek: add MT7988 infracfg reset IDs f907dd749888 dt-bindings: clock: mediatek: convert SSUSBSYS to the json-schema clock 77f559281267 dt-bindings: clock: mediatek: convert PCIESYS to the json-schema clock 5776acd8f40b dt-bindings: clock: mediatek: convert hifsys to the json-schema clock 2b71a4051c65 dt-bindings: arm: realview: Spelling s/ARM 11/Arm11/, s/Cortex A-/Cortex-A/ d5d9be3159cd ARM: dts: integrator: Fix up VGA connector e7ff0fa9dc10 ARM: dts: versatile: Fix up VGA connector 5cc0ca358e86 ARM: dts: arm: realview: Fix development chip ROM compatible value 17690d898c6b arm64: dts: ti: k3-am62p: Add Wave5 Video Encoder/Decoder Node 1a04d9e2ea04 arm64: dts: ti: k3-j721s2-main: Add Wave5 Video Encoder/Decoder Node 037f82133c88 arm64: dts: ti: k3-j784s4: Add Wave5 Video Encoder/Decoder Node b9b4934fd72d arm64: dts: ti: k3-am69-sk: Add support for OSPI flash 54bdd26cd110 arm64: dts: ti: k3-am69-sk: Enable CAN interfaces for AM69 SK board 5ddb529be866 arm64: dts: ti: k3-am62p: Add nodes for CSI-RX 2bc64591456d arm64: dts: ti: k3-am62p: Add DMASS1 for CSI fb6e8cb37b07 arm64: dts: ti: k3-am62p: Fix memory ranges for DMSS 4a664d32a079 arm64: dts: ti: k3-j722s-evm: Enable OSPI NOR support 0a3c08b6205b arm64: dts: ti: k3-j722s-evm: Enable CPSW3G RGMII1 6d9068d2f3e7 arm64: dts: ti: k3-j784s4-main: Fix mux-reg-masks in serdes_ln_ctrl 8f04b7849578 arm64: dts: ti: k3-j721e: Fix mux-reg-masks in hbmc_mux c3982938ea86 dt-bindings: display: renesas,rzg2l-du: Document RZ/V2L DU bindings 62d59754ec63 dt-bindings: display: Document Renesas RZ/G2L DU bindings b9138e8af159 arm64: tegra: Use consistent SD/MMC aliases on Tegra234 dcff839661ba arm64: dts: amlogic: add fbx8am DT overlays 0d16b6bd5803 ARM: dts: gemini: Fix switch node names on Vitesse switches 81e1d1cfd2f9 ARM: dts: gemini: Map reset keys to KEY_RESTART 915ebb1bf1e0 ARM: dts: gemini: Fix wiligear compatible strings d8869f38c863 ARM: dts: gemini: Fix switch node names in the DIR-685 4466332a360b ASoC: dt-bindings: qcom,wsa8840: Add reset-gpios for shared line 8d8332ce62c5 dt-bindings: reset: sophgo: support SG2042 357d5bbac5af ASoC: Intel: avs: Fixes and new platforms support ed4851e1d924 regulator: dt-bindings: qcom,usb-vbus-regulator: add support for PM4125 bcf5ae8600f6 regulator: dt-bindings: qcom,usb-vbus-regulator: add support for PM4125 90ad8fbfa7f9 Merge tag 'memory-controller-drv-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers 6a8fb7b89e73 arm64: dts: qcom: sm6115: fix USB PHY configuration 0dc3ecab7183 Merge tag 'linux-can-next-for-6.9-20240220' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next f923d17647b5 MIPS: mobileye: Add EPM5 device tree 885d1e731299 MIPS: mobileye: Add EyeQ5 dtsi 7fb9ce7c1dde dt-bindings: mips: Add bindings for Mobileye SoCs e3797e6a3708 dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core 9a705909b63d dt-bindings: mips: cpus: Sort the entries e0340332869b dt-bindings: Add vendor prefix for Mobileye Vision Technologies Ltd. 011bf078c7bc dt-bindings: pinctrl: renesas,pfc: Document R-Car V4M support 49888873d596 dt-bindings: net: fec: add iommus property 80733980e6ba dt-bindings: iio: adc: ti-ads1298: Add bindings 26a3005ca5c0 dt-bindings: iio: pressure: honeywell,hsc030pa.yaml add spi props d64846638639 dt-bindings: adc: axi-adc: update bindings for backend framework a3fc6ec1428b dt-bindings: adc: ad9467: add new io-backend property c0d436471a5f regulator: Merge up v6.8-rc5 52dcafce5828 dt-bindings: regulator: qcom,usb-vbus-regulator: Add PM6150 compatible 66f7b7966dfc arm64: dts: ti: Add common1 register space for AM62A SoC 6b911cea73bb arm64: dts: ti: Add common1 register space for AM62x SoC bb6e999b30ab arm64: dts: ti: Add common1 register space for AM65x SoC 2a98a4ff884d arm64: dts: mt8195-cherry-tomato: change watchdog reset boot flow b5c66885729f dt-bindings: display: simple: Add boe,bp082wx1-100 8.2" panel 0b9a359a81b7 dt-bindings: display: ti,am65x-dss: Add support for common1 region 0033e16adcd4 dt-bindings: renesas: Document preferred compatible naming 1771fa16d31e dt-bindings: ata: convert MediaTek controller to the json-schema 127ae13f4e5e arm64: dts: mt7986: add port@5 as CPU port 57f255ff84ed arm64: dts: mt7622: add port@5 as CPU port 1e471beb8eea ARM: dts: meson8b: fix &hwrng node compatible string 320da6153b8a ARM: dts: meson8: fix &hwrng node compatible string 9625cfa0c727 ARM: dts: meson: fix bus node names f496b04c1652 arm64: dts: amlogic: add fbx8am board 686e2be425fd dt-bindings: arm: amlogic: add fbx8am binding 48371b0670ac dt-bindings: vendor-prefixes: add freebox 471f9b9dd5e2 arm64: dts: amlogic: replace underscores in node names 6e0fb3cc9b68 arm64: dts: ti: k3-am642-evm: add overlay for ICSSG1 2nd port 7526121625ee dt-bindings: interconnect: qcom,rpmh: Fix bouncing @codeaurora address fcda7c3e7ef7 Merge 6.8-rc5 into usb-next 670cbcdfbb09 arm64: dts: ti: k3-am642-evm: add ICSSG1 Ethernet support cea3277e3b5e arm64: dts: ti: k3-am64-main: Add ICSSG IEP nodes eb0aea3a7c5a Merge 6.8-rc5 into tty-next c07c11c8be59 arm64: dts: ti: k3-am6*: Add bootph-all property in MMC node 59d465b82cb4 arm64: dts: ti: k3-am6*: Fix bus-width property in MMC nodes 16af8c673aff arm64: dts: ti: k3-am6*: Fix ti,clkbuf-sel property in MMC nodes 87f154491e63 arm64: dts: ti: k3-am6*: Remove DLL properties for soft PHYs 722bd88c8fab arm64: dts: ti: k3-am62p: Add ITAP/OTAP values for MMC 18c8263c1ec1 arm64: dts: ti: k3-am64-main: Fix ITAP/OTAP values for MMC 73f1cbbcb198 arm64: dts: ti: k3-am62a7-sk: Enable eMMC support 973681d9002a arm64: dts: ti: k3-am62a-main: Add sdhci2 instance 4430a5c5a0ec arm64: dts: ti: k3-am62a-main: Add sdhci0 instance be340f86aaf1 arm64: dts: sm8650: Add msi-map-mask for PCIe nodes 49cf8bb8b63f arm64: dts: qcom: replace underscores in node names 8f9d0aa368d0 ARM: dts: qcom: samsung-matisse-common: Add UART ce30f2d31d9c ARM: dts: qcom: Add support for Samsung Galaxy Tab 4 10.1 LTE (SM-T535) afbdd6233c4a ARM: dts: qcom: samsung-matisse-common: Add initial common device tree 6a80ca4b242a dt-bindings: arm: qcom: Add Samsung Galaxy Tab 4 10.1 LTE 3cef33d6916c dt-bindings: soc: qcom: qcom,saw2: add msm8226 l2 compatible e4d2d663cf96 arm64: dts: ti: k3-j784s4-evm: Remove Pinmux for CTS and RTS in wkup_uart0 d43ac341179d arm64: dts: ti: k3-j721s2-common-proc-board: Remove Pinmux for CTS and RTS in wkup_uart0 80e20b3b69c9 arm64: dts: ti: k3-j7200-common-proc-board: Remove clock-frequency from mcu_uart0 35877fcaea3a arm64: dts: ti: k3-j7200-common-proc-board: Modify Pinmux for wkup_uart0 and mcu_uart0 cac67785c0a6 arm64: dts: ti: k3-j721e-sk: Add overlay for IMX219 b1d7814ca372 arm64: dts: ti: k3-j784s4-main: Add CSI2RX capture nodes b6b2d86e2411 arm64: dts: ti: k3-j721s2-main: Add CSI2RX capture nodes 58403c60add6 arm64: dts: ti: k3-j721e-main: Add CSI2RX capture nodes 4796014c5f92 arm64: dts: ti: k3-j721e-sk: Model CSI2RX connector mux b599ef1ba8ff arm64: dts: ti: k3-am69-sk: Enable camera peripherals 248c870c7bd6 arm64: dts: ti: k3-am68-sk-base-board: Enable camera peripherals a5f6b550f77b arm64: dts: ti: k3-j784s4-evm: Enable camera peripherals f70c4ae50ecf arm64: dts: ti: k3-j721s2-common-proc-board: Enable camera peripherals 4141c6b09a96 dt-bindings: i3c: drop "master" node name suffix f3ca3a16bd19 dt-bindings: timer: nxp,sysctr-timer: support i.MX95 19b1a141c8dd dt-bindings: usb: qcom,pmic-typec: add support for the PMI632 block 15c348192cc2 dt-bindings: regulator: qcom,usb-vbus-regulator: add support for PMI632 3c201cdbc89a dt-bindings: iio: humidity: hdc3020: add interrupt bindings in example 0fc77339f456 dt-bindings: iio: afe: voltage-divider: Add io-channel-cells 7adf6f669393 dt-bindings: iio: imu: st_lsm6dsx: add asm330lhhxg1 bd37e5428ced dt-bindings: iio: frequency: add admfm2000 f6c7124a3d91 dt-bindings: usb/ti,am62-usb.yaml: Add PHY2 register space 3102faf7d698 dt-bindings: usb: microchip,usb5744: Remove peer-hub as requirement d403cb0d5128 arm64: dts: qcom: qcm6490-fairphone-fp5: Add PMIC GLINK 7ab947b60396 dt-bindings: usb: dwc3: drop 'snps,host-vbus-glitches-quirk' e007ca0c7920 ASoC: dt-bindings: Update example for enabling USB offload on SM8250 14bd5c629408 ASoC: dt-bindings: Add Q6USB backend 86b2f37571d9 arm64: dts: ti: Add reserved memory for watchdog 0ffb30594139 arm64: dts: qcom: pm4125: define USB-C related blocks 437f7c2c748a arm64: dts: qcom: sa8540p-ride: disable pcie2a node ddc97b021a4f arm64: dts: qcom: sc7280: add slimbus DT node 174b19d0a453 dt-bindings: display: ltk500hd1829: add variant compatible for ltk101b4029w 9990fd362767 dt-bindings: display: panel-lvds: Add compatible for admatec 9904370 panel 3a9936a295c2 dt-bindings: vendor-prefixes: add prefix for admatec GmbH 11b2a690403f arm64: dts: qcom: sc7280: Add capacity and DPC properties 23437543023d ARM: dts: qcom: ipq8064: drop 'regulator' property from SAW2 devices cabc075cf325 ARM: dts: qcom: ipq4019: drop 'regulator' property from SAW2 devices 484c003d94ab ARM: dts: qcom: msm8974: drop 'regulator' property from SAW2 device 6445cb8886be ARM: dts: qcom: apq8084: drop 'regulator' property from SAW2 device 98ba5545146c ARM: dts: qcom: msm8960: declare SAW2 regulators b54dea12770f ARM: dts: qcom: apq8064: declare SAW2 regulators 4dce2cf9f83d ARM: dts: qcom: ipq8064: rename SAW nodes to power-manager 5b13a9611268 ARM: dts: qcom: ipq4019: rename SAW nodes to power-manager 0ec0f547bc86 ARM: dts: qcom: msm8974: rename SAW nodes to power-manager 9c6828f9c895 ARM: dts: qcom: msm8960: rename SAW nodes to power-manager d5acf25ed148 ARM: dts: qcom: apq8084: rename SAW nodes to power-manager 643db1cecca9 ARM: dts: qcom: apq8064: rename SAW nodes to power-manager 4de620145e88 ARM: dts: qcom: ipq8064: use SoC-specific compatibles for SAW2 devices c44fb47e47a5 ARM: dts: qcom: ipq4019: use SoC-specific compatibles for SAW2 devices 5e99522aa387 ARM: dts: qcom: msm8960: use SoC-specific compatibles for SAW2 devices 75a6d010f715 ARM: dts: qcom: msm8974: use new compat string for L2 SAW2 unit 9eb4395e3cbc ARM: dts: qcom: apq8084: use new compat string for L2 SAW2 unit 0cc21b045573 arm64: dts: qcom: pmi632: Add PBS client and use in LPG node adaff156bd89 arm64: dts: qcom: sm8550: Use GIC-ITS for PCIe0 and PCIe1 567a4e2c1bfd arm64: dts: qcom: sm8150: correct PCIe wake-gpios aff4851c71af arm64: dts: qcom: sdm845-db845c: correct PCIe wake-gpios d12e2e81b378 dt-bindings: soc: qcom: qcom,saw2: define optional regulator node 87cb0efb080c dt-bindings: soc: qcom: qcom,saw2: add missing compatible strings 78779d5162e9 dt-bindings: soc: qcom: merge qcom,saw2.txt into qcom,spm.yaml 90689200835c arm64: dts: qcom: sm7225-fairphone-fp4: Enable display and GPU 49fc8baa3dd8 arm64: dts: qcom: sm6350: Remove "disabled" state of GMU 3bb88ee4bafc dt-bindings: clk: qcom: drop the SC7180 Modem subsystem clock controller 08488eb0c95c arm64: dts: qcom: msm8916-samsung-fortuna/rossa: Add fuel gauge 9230383364ef arm64: dts: qcom: sm6350: Add interconnect for MDSS 93d1070a237b dt-bindings: can: xilinx_can: Add 'xlnx,has-ecc' optional property 09c2905a6449 dt-bindings: renesas,rcar-dmac: Add r8a779h0 support 8500691f667d dt-bindings: dma: convert MediaTek High-Speed controller to the json-schema 7b382eea018b arm64: tegra: Enable cros-ec-spi as wake source 73f09474de21 ARM: tegra: Enable cros-ec-spi as wake source 9c3c23577ad9 dt-bindings: tegra: pmc: Update scratch as an optional aperture 296aea7e0f2a dt-bindings: display: panel: Add Himax HX83112A 5b0ce634f06d dt-bindings: phy: Add Rockchip HDMI/eDP Combo PHY schema 01f41446bb7f Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net 87dd58b7c6ca dt-bindings: mmc: renesas,sdhi: Document R-Car V4M support ec136bb18fcc arm64: dts: ti: Add support for TI J722S Evaluation Module 4dd9e11aa40f arm64: dts: ti: Introduce J722S family of SoCs 1339c374a4c1 dt-bindings: arm: ti: Add bindings for J722S SoCs 723c10f0bd63 arm64: dts: ti: iot2050: Support IOT2050-SM variant 4a95da5a5df9 arm64: dts: ti: iot2050: Annotate LED nodes a2119b7f92bd arm64: dts: ti: iot2050: Factor out DP related bits a3f672abd86f arm64: dts: ti: iot2050: Factor out enabling of USB3 support 0f7fd425cef9 arm64: dts: ti: iot2050: Factor out arduino connector bits 326a69a3e459 arm64: dts: ti: iot2050: Disable R5 lockstep for all PG2 boards 9f6227cced13 dt-bindings: arm: ti: Add binding for Siemens IOT2050 SM variant 4c8ad6e37e97 arm64: dts: ti: k3-am62-main: disable usb lpm 58003d5a29e5 arm64: dts: ti: verdin-am62: Set VDD CORE minimum voltage to 0.75V 09148e5825bc arm64: dts: ti: k3-am62-wakeup: Configure ti-sysc for wkup_uart0 8d7152a47403 arm64: dts: ti: am62-phyboard-lyra: Add overlay to enable a GPIO fan 16c636f5b152 arm64: dts: ti: k3-j721e-sk: fix PMIC interrupt number 2932b4306805 arm64: dts: ti: k3-am69-sk: fix PMIC interrupt number f6c375e9f85d arm64: dts: ti: verdin-am62: add support for Verdin USB1 interface 309045be68da arm64: dts: ti: Add DT overlay for PCIe + USB3.0 SERDES personality card 2979217a850f arm64: dts: ti: Add DT overlay for PCIe + USB2.0 SERDES personality card b70ff6a5d411 dt-bindings: w1: UART 1-Wire bus 21e00d907bfb dt-bindings: serial: allow onewire as child node 1f162c88f711 dt-bindings: pwm: mediatek,mt2712: add compatible for MT7988 b69225cd6653 dt-bindings: atmel,hlcdc: convert pwm bindings to json-schema 4fc4f31db241 dt-bindings: pxa-pwm: Convert to YAML 61f4ac7c5c90 ARM: dts: vexpress: Set stdout-path to serial0 in the chosen node 199bf4b635e6 arm64: dts: mediatek: Replace deprecated extcon-usb-gpio id-gpio/vbus-gpio properties 73d46717fb3d ARM: dts: qcom: msm8226: Add watchdog node 01815a93d9ab dt-bindings: auxdisplay: hit,hd44780: use defines for GPIO flags 41e657a00f9c dt-bindings: auxdisplay: adjust example indentation and use generic node names 81b0dd090434 arm64: dts: qcom: msm8916-samsung-fortuna/rossa: Add initial device trees 3fa556edfd69 arm64: dts: qcom: sm8550: Switch UFS from opp-table-hz to opp-v2 8761bb9477f3 arm64: dts: qcom: sc8180x: describe all PCI MSI interrupts 3419b50ca541 arm64: dts: qcom: minor whitespace cleanup 1a30651d27f6 arm64: dts: qcom: ssm7125-xiaomi: drop incorrect UFS phy max current 8f644a3c370b arm64: dts: qcom: x1e80100-crd: add sound card 22e29ff5c4c3 arm64: dts: x1e80100: correct DMIC2 and DMIC3 pin config node names b32ccff427b3 arm64: dts: sm8650: correct DMIC2 and DMIC3 pin config node names 8b41c24a5900 arm64: dts: sm8550: correct DMIC2 and DMIC3 pin config node names d0bad83ec278 arm64: dts: sm8450: correct DMIC2 and DMIC3 pin config node names 736ebb0686f6 arm64: dts: sc8280xp: correct DMIC2 and DMIC3 pin config node names 33ef3b7fb778 dt-bindings: can: tcan4x5x: Document the wakeup-source flag 11322433ed0f dt-bindings: net: dp83826: support TX data voltage tuning a745442704dd ARM: dts: stm32: lxa-tac: reduce RGMII interface drive strength bdbd2fbe2a1f arm64: dts: mediatek: replace underscores in node names bb7b4de1613f pmdomain: Merge branch dt into next 20b8bae8b8eb arm64: dts: ti: k3-am62a: Make the main_conf node a simple-bus e42f80bc5bcf arm64: dts: ti: k3-am62: Make the main_conf node a simple-bus 8ba7dd15abdd arm64: dts: ti: k3-j7200: Make the FSS node a simple-bus 42ed47d60a80 arm64: dts: ti: k3-j721s2: Convert serdes_ln_ctrl node into reg-mux bf6f8e6f98e5 arm64: dts: ti: k3-j721s2: Convert usb_serdes_mux node into reg-mux 0167a788d9c5 arm64: dts: ti: k3-j721e: Convert usb_serdes_mux node into reg-mux 124c59a52517 arm64: dts: ti: k3-j721e: Convert serdes_ln_ctrl node into reg-mux ebb5990bd126 arm64: dts: ti: k3-j7200: Convert usb_serdes_mux node into reg-mux c0c92c3b24bd arm64: dts: ti: k3-j7200: Convert serdes_ln_ctrl node into reg-mux 8c7e27a256ed arm64: dts: ti: k3-am64: Convert serdes_ln_ctrl node into reg-mux ecaaf99dee6f arm64: dts: mediatek: mt8186: Add missing xhci clock to usb controllers 546dd2b71775 arm64: dts: mediatek: mt8186: Add missing clocks to ssusb power domains 845392fb2a8c ARM: dts: qcom: msm8960: expressatt: Add mXT224S touchscreen a5fc0fcda8d3 ARM: dts: qcom: msm8960: Add gsbi3 node e5357a45e304 ARM: dts: qcom: msm8226: Add CPU and SAW/ACC nodes df98c13b52f1 ARM: dts: qcom: msm8226: Sort and clean up nodes 4250f1c8ff79 ARM: dts: qcom: msm8974: correct qfprom node size 7d8cff577be7 dt-bindings: arm: qcom,ids: Add IDs for SM8475 family ee8caed03c87 arm64: dts: qcom: sdm845: Enable cros-ec-spi as wake source 6eef1cbc79c9 arm64: dts: qcom: sc7280: Enable cros-ec-spi as wake source 097f3128d091 arm64: dts: qcom: sc7180: Enable cros-ec-spi as wake source 1a1c9101358c arm64: dts: qcom: sdm845: Use the Low Power Island CX/MX for SLPI 292108e317ec arm64: dts: qcom: msm8996: Define UFS UniPro clock limits 71aab956985a arm64: dts: qcom: qcs6490-rb3gen2: Declare GCC clocks protected 5a7b32324b50 arm64: dts: qcom: sc8280xp-pmics: Define adc for temp-alarms c7cdefde3890 arm64: dts: qcom: sc8280xp-crd: Add PMIC die-temp vadc channels fc4657cf641c dt-bindings: net: qca,ar9331: convert to DT schema f8930a53d1df arm64: dts: rockchip: Add USB3.0 to Indiedroid Nova 5e1a3b5538e5 arm64: dts: rockchip: adjust phy-handle name on rock-pi-e 67a655c02d0c arm64: dts: rockchip: fix rk3399 hdmi ports node 1ce4f570403a arm64: dts: rockchip: fix rk3328 hdmi ports node fe75fb3e4156 ARM: dts: rockchip: fix rk322x hdmi ports node d8715fea4366 ARM: dts: rockchip: fix rk3288 hdmi ports node 3693fdfce256 dt-bindings: display: rockchip,dw-hdmi: add power-domains property a3f511793cc1 dt-bindings: display: rockchip: rockchip,dw-hdmi: remove port property fdad3ea0d962 arm64: dts: rockchip: remove redundant cd-gpios from rk3588 sdmmc nodes 1619cbd3e975 arm64: dts: rockchip: add rs485 support on uart5 of px30-ringneck-haikou 2134fa3eaa7f arm64: dts: rockchip: add rs485 support on uart2 of rk3399-puma-haikou 7a4285c5d69e arm64: dts: rockchip: Add Powkiddy RGB10MAX3 b9b257004011 dt-bindings: arm: rockchip: Add Powkiddy RGB10MAX3 a3adfa889806 arm64: dts: rockchip: Update powkiddy rk2023 dtsi for RGB10MAX3 8c24e7309a68 dt-bindings: display: rocktech,jh057n00900: Document panel rotation 46ed672258f7 dt-bindings: display: Add Powkiddy RGB10MAX3 panel 01125f93dff3 dt-bindings: soc: rockchip: add rk3588 USB3 syscon f12733bf8794 dt-bindings: soc: rockchip: add clock to RK3588 VO grf 94e3c5a3f928 docs: dt: writing-schema: document expectations on example DTS fe91d6f4b5e3 docs: dt: writing-schema: explain additional/unevaluatedProperties 4a3d3359c02d docs: dt: writing-schema: clarify that schema should describe hardware d91bf686801b dt-bindings: use capital "OR" for multiple licenses in SPDX 496c29b2e9a6 dt-bindings: vendor-prefixes: add smartrg 24ffa3c14c93 dt-bindings: misc: qcom,fastrpc: Compute callbacks can be DMA coherent 0723544f32df dt-bindings: soc: renesas: Preserve the order of SoCs based on their part numbers a6d969083d23 clk: renesas: r8a779g0: Correct PFC/GPIO parent clocks 1c22386104aa ASoC: dt-bindings: fsl,imx-asrc: convert to YAML 0a4520722599 dt-bindings: timer: renesas: ostm: Document RZ/Five SoC 82515ffc20b0 dt-bindings: mmc: fsl-imx-esdhc: add iommus property 54b4d099b066 dt-bindings: mmc: fsl-imx-esdhc: add i.MX95 compatible string 878060d5ab93 dt-bindings: power: rpmpd: Add MSM8974 power domains ba7f2dd56d71 arm64: dts: amlogic: t7: minor whitespace cleanup 0e3777330164 Merge tag 'renesas-pinctrl-for-v6.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel 2b637c08d90d arm64: dts: amlogic: axg: initialize default SoC capacitance 56b8815ee298 arm64: dts: amlogic: axg: move cpu cooling-cells to common dtsi 38e9d49495a7 arch: arm64: dts: meson: a1: add assigned-clocks for usb node 04303030d8a7 arm64: dts: amlogic: meson-g12-common: Set the rates of the clocks for the NPU 96f1514933cd arm64: dts: amlogic: add reset controller for Amlogic C3 SoC b6cee0d8e50c dt-bindings: i2c: mux: i2c-demux-pinctrl: Define "i2c-parent" constraints cbcbd116c3bb dt-bindings: i2c: mux: i2c-demux-pinctrl: Drop i2c-mux.yaml reference d21de1b0f205 dt-bindings: can: fsl,flexcan: add i.MX95 compatible string 18dd617a729c ASoC: dt-bindings: cs35l45: Add interrupts d649337cab0d ASoC: dt-bindings: qcom,sm8250: Allow up to 8 codec DAIs 168cf4050131 arm64: dts: fsd: Add fifosize for UART in Device Tree c49f54ab8258 arm64: dts: exynos: gs101: minor whitespace cleanup 761c7555e3a6 arm64: dts: mediatek: mt7622: add missing "device_type" to memory nodes feb82cd75ca1 arm64: dts: mediatek: mt7986: reorder nodes afeb2b683c6a arm64: dts: mediatek: mt7986: reorder properties 1f41c46b7784 arm64: dts: mediatek: Add Acelink EW-7886CAX a9e4cb01cbbd dt-bindings: arm64: dts: mediatek: Add Acelink EW-7886CAX access point a0d0e301bacb dt-bindings: vendor-prefixes: add acelink 6355f4d21fe2 arm64: dts: mediatek: Introduce the MT8395 Radxa NIO 12L board ad8297de07f0 dt-bindings: arm64: mediatek: Add MT8395 Radxa NIO 12L board compatible c878dc2878b8 arm64: dts: mediatek: mt8186: Add video decoder device nodes 86ae11dcbfb0 arm64: dts: mediatek: mt8195: Add MTU3 nodes and correctly describe USB a1bccd014f43 arm64: dts: mediatek: Add MT8186 Magneton Chromebooks f06a044c7c87 arm64: dts: mediatek: Add MT8186 Steelix platform based Rusty 3d00e9da10ee arm64: dts: mediatek: Introduce MT8186 Steelix 2047c128ed63 arm64: dts: mediatek: Add MT8186 Krabby platform based Tentacruel / Tentacool 0526f7bc6fb8 dt-bindings: arm: mediatek: Add MT8186 Magneton Chromebooks 089e49677706 dt-bindings: arm: mediatek: Add MT8186 Rusty Chromebook f9d037124e77 dt-bindings: arm: mediatek: Add MT8186 Steelix Chromebook f5956f4a6314 dt-bindings: arm: mediatek: Add MT8186 Tentacruel / Tentacool Chromebooks 38bba08bb5f5 dt-bindings: arm: mediatek: Sort entries by SoC then board compatibles ae447c85bffd arm64: dts: mediatek: mt8186: Add jpgenc node 2ee45888f0f1 dt-bindings: media: mediatek-jpeg-encoder: change max iommus count 9dd1d78b9108 arm64: dts: mediatek: mt8186: Add venc node 928e533f64ce arm64: dts: mediatek: mt8186: fix VENC power domain clocks 10ccafc6dfc8 dt-bindings: media: mtk-vcodec-encoder: add compatible for mt8186 a26c81acaef4 arm64: dts: mediatek: mt8192: fix vencoder clock name 6d5ecd0c0bf1 dt-bindings: media: mtk-vcodec-encoder: fix non-vp8 clock name 44858bf6309d arm64: dts: mediatek: Add socinfo efuses to MT8173/83/96/92/95 SoCs 87674b38b34a arm64: dts: mediatek: mt8195: Enable cros-ec-spi as wake source a5e0493deb44 arm64: dts: mediatek: mt8192: Enable cros-ec-spi as wake source d8de0db07270 arm64: dts: mediatek: mt8183: Enable cros-ec-spi as wake source e62bf57bf4ce arm64: dts: mediatek: mt8173: Enable cros-ec-spi as wake source 80f419da8e71 arm64: dts: mediatek: mt7988: add clock controllers 0da54052e647 arm64: dts: mediatek: Add initial MT7988A and BPI-R4 17df9b07965f dt-bindings: arm64: mediatek: Add MT7988A and BPI-R4 58b0724c52ef arm64: dts: mediatek: Add initial MT7981B and Xiaomi AX3000T f2654823e7da dt-bindings: arm64: mediatek: Add MT7981B and Xiaomi AX3000T ec60c59a2f5a arm64: dts: mediatek: mt8192-asurada: Remove CrosEC base detection node 4cc812e03139 arm64: dts: mediatek: mt7986: add "#reset-cells" to infracfg a70fe7a32743 arm64: dts: mediatek: mt7986: drop "#clock-cells" from PWM 08e6a51e82bf arm64: dts: mediatek: mt7986: fix SPI nodename 0ce82b652753 arm64: dts: mediatek: mt7986: fix SPI bus width properties 1654679b7b86 arm64: dts: mediatek: mt7986: drop crypto's unneeded/invalid clock name 0db4b3814808 arm64: dts: mediatek: mt7986: fix reference to PWM in fan node e14ff64a492a arm64: dts: mt8183: Move CrosEC base detection node to kukui-based DTs 5af22a48d387 dt-bindings: net: qcom,ethqos: add binding doc for safety IRQ for sa8775p f0efaf410576 dt-bindings: arm: qcom,coresight-tpdm: Add support for TPDM CMB MSR register a31e6ce97f3b dt-bindings: arm: qcom,coresight-tpdm: Add support for CMB element size 42aa700e6b6a Merge tag 'v6.8-rc4' into gpio/for-next 28ff43a9c5cf dt-bindings: hwmon: Add LTC4282 bindings 946976867e95 dt-bindings: hwmon: ina2xx: Describe ina260 chip 60a5255306fa dt-bindings: hwmon: ina2xx: Describe #io-channel-cells property ccda6b1eb4cb dt-bindings: hwmon: ina2xx: Add label property 29abc2d8cf78 dt-bindings: display: msm: sm8650-mdss: Add missing explicit "additionalProperties" ca193aa48798 dt-bindings: msm: qcom, mdss: Include ommited fam-b compatible fb87bba01a93 dt-bindings: dsi-controller-main: Document missing msm8976 compatible 6e32138572e8 dt-bindings: net: Document Qcom QCA807x PHY package d65891d631e7 dt-bindings: net: document ethernet PHY package nodes 05327165c680 arm64: dts: qcom: qrb4210-rb2: enable USB-C port handling c48cf2ca774b arm64: dts: qcom: sm6115: drop pipe clock selection 0529c70be68e arm64: dts: qcom: pmi632: define USB-C related blocks 8f3c2d458408 arm64: dts: qcom: qcs6490-rb3gen2: Correct the voltage setting for vph_pwr f077c9e8cdcc arm64: dts: qcom: qcm6490-idp: Correct the voltage setting for vph_pwr ed36b9e79976 dt-bindings/perf: Add Arm CoreSight PMU 6bea5f945518 dt-bindings: pinctrl: cy8c95x0: Update gpio-reserved-ranges ff6ea0429974 dt-bindings: pinctrl: nvidia,tegra234-pinmux: Restructure common schema f8a5525e9f69 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net b64c0f80d53a spi: get rid of some legacy macros adfae82db04a spi: dt-bindings: samsung: add google,gs101-spi compatible 7d4159bca342 dt-bindings: mfd: dlg,da9063: Convert da9062 to json-schema 84465d53e06e dt-bindings: mfd: dlg,da9063: Sort child devices a5d5c9ca95f6 dt-bindings: thermal: Convert da906{1,2} thermal to json-schema 9491d890e23c dt-bindings: input: Convert da906{1,2,3} onkey to json-schema bf94a53ad831 dt-bindings: mfd: dlg,da9063: Update watchdog child node 5d2f1ff23c1f dt-bindings: mfd: da9062: Update watchdog description 6d63119dedee dt-bindings: soc: qcom: qcom,pmic-glink: document QCM6490 compatible eadfdbf7cfd7 dt-bindings: i2c: renesas,rcar-i2c: Add r8a779h0 support 506140c4b36b dt-bindings: i2c: pca954x: Add custom properties for MAX7357 a3cf64f59235 arm64: dts: exynos: gs101: enable i2c bus 12 on gs101-oriole 66fd6a721305 arm64: dts: exynos: gs101: define USI12 with I2C configuration bc3a8ffe73f6 arm64: dts: exynos: gs101: enable cmu-peric1 clock controller 85f5d68af4a0 Merge tag 'samsung-dt-bindings-clk-6.9-3' into next/dt64 eff597e8d6d7 Merge branch '20240131-ufs-phy-clock-v3-3-58a49d2f4605@linaro.org' into clk-for-6.9 9d58463252f8 Merge branch '20240125-msm8953-mdss-reset-v2-1-fd7824559426@z3ntu.xyz' into clk-for-6.9 53156f9a9b8b dt-bindings: samsung: exynos-sysreg: gs101-peric0/1 require a clock f0fc02f810bc Merge tag 'samsung-dt-bindings-clk-6.9-3' into next/clk 3a17e325742d dt-bindings: clock: google,gs101-clock: add PERIC1 clock management unit f8f976624cd6 ASoC: dt-bindings: atmel,asoc-wm8904: Convert to json-schema e07e6605bd92 ARM: dts: samsung: exynos5420-galaxy-tab-common: add wifi node 833d20d41eff dt-bindings: phy: add mediatek MIPI CD-PHY module v0.5 0aff1be67191 dt-bindings: phy: cadence-torrent: Add a separate compatible for TI J7200 61354e32b738 dt-bindings: phy: cadence-torrent: Add optional input reference clock for PLL1 0ed441cb60fc Merge drm/drm-next into drm-misc-next fa4e28b76a28 dt-bindings: phy: qmp-ufs: Fix PHY clocks edf14e92f825 dt-bindings: fsl-dma: fsl-edma: add fsl,imx95-edma5 compatible string db56af9d1adc dt-bindings: mmp-dma: convert to YAML 69f5e9afcf9a arm64: dts: qcom: sc8280xp: Introduce additional tsens instances d34aa18b328e arm64: dts: qcom: sm8550-hdk: correct WCD9385 route and port mapping c5ac3bf2b9e9 arm64: dts: qcom: sm8650: Fix UFS PHY clocks 960dc14fb417 arm64: dts: qcom: sm8550: Fix UFS PHY clocks 5b487a71e59a arm64: dts: qcom: sm8350: Fix UFS PHY clocks 1019d3b3dd76 arm64: dts: qcom: sc8280xp: Fix UFS PHY clocks d909cc2c57f0 arm64: dts: qcom: sc8180x: Fix UFS PHY clocks 32798a824479 Merge branch '20240131-ufs-phy-clock-v3-3-58a49d2f4605@linaro.org' into HEAD 647fc2ed0999 dt-bindings: trivial-devices: sort entries alphanumerically d87ada5ab8a5 arm64: dts: qcom: sm8250: Fix UFS PHY clocks 71ea2327fa6f arm64: dts: qcom: sm8150: Fix UFS PHY clocks 64da7648e2cd arm64: dts: qcom: sm6350: Fix UFS PHY clocks fd0f61fefaf5 arm64: dts: qcom: sm6125: Fix UFS PHY clocks 4d7ec8559332 arm64: dts: qcom: sm6115: Fix UFS PHY clocks 1b77533e4915 arm64: dts: qcom: sdm845: Fix UFS PHY clocks 18872b4ddd5f arm64: dts: qcom: msm8998: Fix UFS PHY clocks 9a197a6489bc arm64: dts: qcom: msm8996: Fix UFS PHY clocks 1c92660aee2a dt-bindings: clock: qcom: Add missing UFS QREF clocks a20d2718cc23 arm64: dts: qcom: ipq8074: add clock-frequency to MDIO node 6ed4e54f3d0a arm64: dts: qcom: qrb2210-rb1: disable cluster power domains 1816222d14d0 arm64: dts: qcom: msm8953: Add GPU 289d949a2fa0 arm64: dts: qcom: msm8953: Add GPU IOMMU d8789c7d4887 arm64: dts: qcom: msm8953: add reset for display subsystem e3e73e0578cb Merge branch '20240125-msm8953-mdss-reset-v2-1-fd7824559426@z3ntu.xyz' into arm64-for-6.9 6beb0be6d4fc dt-bindings: clock: gcc-msm8953: add more resets f84a5b88e932 arm64: dts: qcom: sm8650-mtp: add Audio sound card node 92c1bbcc400a arm64: dts: qcom: sm8650-qrd: add Audio nodes b0e0830701c8 arm64: dts: qcom: sm8650: Add dma-coherent property d16840039a98 arm64: dts: qcom: sm8550: Add dma-coherent property f515a57656b3 arm64: dts: qcom: sm8650-qrd: add PM8010 regulators 03371084ea86 arm64: dts: qcom: sm8650-mtp: add PM8010 regulators a5d205597cdb arm64: dts: qcom: ipq6018: add thermal zones a536a392c199 arm64: dts: qcom: ipq6018: add tsens node 93475982136a arm64: dts: qcom: sm8550-mtp: add correct analogue microphones 94d226438171 arm64: dts: qcom: sm8550-qrd: add correct analogue microphones da9e6dd17060 arm64: dts: qcom: sm8550-mtp: correct WCD9385 TX port mapping 19f3548ab2ee arm64: dts: qcom: sm8550-qrd: correct WCD9385 TX port mapping 70387c1a6e20 arm64: dts: qcom: sm6350: Add tsens thermal zones 14a45c7e6691 arm64: dts: qcom: sm6115: declare VLS CLAMP register for USB3 PHY 62ceca9a978f arm64: dts: qcom: qcm2290: declare VLS CLAMP register for USB3 PHY 1243c8cd7c3d arm64: dts: qcom: msm8998: declare VLS CLAMP register for USB3 PHY 41b532e3d8fb arm64: dts: qcom: sc7280: Update domain-idle-states for cluster sleep 9067770d28da arm64: dts: qcom: sdm630-nile: Enable and configure PM660L WLED 59950318f199 dt-bindings: arm: qcom: drop the superfluous device compatibility schema 5906b6dbb4b8 arm64: dts: qcom: sm8650: add missing qlink_logging reserved memory for mpss 1a5594201259 arm64: dts: qcom: ipq9574: Enable Inline Crypto Engine for MMC 6c5dcfe50eeb arm64: dts: qcom: x1e80100-crd: add WSA8845 speakers 641aa52f01a1 arm64: dts: qcom: x1e80100-crd: add WCD9385 Audio Codec adad71a77e32 arm64: dts: qcom: x1e80100: add Soundwire controllers fcb540f3e31d arm64: dts: qcom: x1e80100: add ADSP audio codec macros fe7149ac0fe1 arm64: dts: qcom: x1e80100: add LPASS LPI pin controller 89656eaec676 arm64: dts: qcom: x1e80100: add ADSP GPR a24c8ba00dac dt-bindings: remoteproc: qcom,sm8550-pas: document the SM8650 PAS 552c8b9c51bd riscv: dts: microchip: add specific compatible for mpfs pdma 0359a2873d27 arm64: dts: qcom: ipq6018: add QUP5 I2C node 2109082a047e arm64: dts: qcom: x1e80100-qcp: Fix supplies for LDOs 3E and 2J ad5e70a893a6 arm64: dts: qcom: x1e80100-qcp: Enable more support 70e1e5caf55a arm64: dts: qcom: x1e80100-crd: Enable more support e7f823deb502 arm64: dts: qcom: x1e80100: Add display nodes 09888df4cabf arm64: dts: qcom: x1e80100: Add PCIe nodes 113e1447c4b7 arm64: dts: qcom: x1e80100: Add USB nodes d042016c875e arm64: dts: qcom: x1e80100: Add TCSR node 1e12a915f76a arm64: dts: qcom: x1e80100: Add ADSP/CDSP remoteproc nodes 21784a99d799 arm64: dts: qcom: x1e80100: Add QMP AOSS node adac34e54b92 arm64: dts: qcom: x1e80100: Add SMP2P nodes f6ae972c7d7a arm64: dts: qcom: x1e80100: Add IPCC node f858f5571e59 Merge branch '20240202-x1e80100-clock-controllers-v4-5-7fb08c861c7c@linaro.org' into arm64-for-6.9 16f9c84b0c9a Merge branch '20240202-x1e80100-clock-controllers-v4-5-7fb08c861c7c@linaro.org' into clk-for-6.9 77ff05b89311 dt-bindings: clock: qcom: Document the X1E80100 Camera Clock Controller 9b09558a4d02 dt-bindings: clock: qcom: Document the X1E80100 TCSR Clock Controller 009188ad89c1 dt-bindings: clock: qcom: Document the X1E80100 GPU Clock Controller 619f14d3ee00 dt-bindings: clock: qcom: Document the X1E80100 Display Clock Controller 5c691ea9dfde dt-bindings: clock: Drop the SM8650 DISPCC dedicated schema fd99a9349fc8 dt-bindings: soc: qcom: qcom,pmic-glink: document X1E80100 compatible 3de725e88fb0 arm64: dts: qcom: sa8775p: Add new memory map updates to SA8775P 62872aebbbd8 dt-bindings: soc: imx: add missing clock and power-domains to imx8mp-hdmi-blk-ctrl 4ff28e3e2d94 ASoC: dt-bindings: atmel,sam9x5-wm8731: Convert to json-schema 906cab843596 riscv: dts: microchip: add missing CAN bus clocks 70bee5f22413 dt-bindings: can: mpfs: add missing required clock 91d53111ca13 dt-bindings: clock: mpfs: add more MSSPLL output definitions 7564dfecdf9e Revert "media: ov08x40: Reduce start streaming time" 230eabe62cac arm64: dts: ti: iot2050*: Clarify GPL-2.0 as GPL-2.0-only 81c25598663e arm64: dts: ti: phycore*: Add MIT license along with GPL-2.0 49ad241d7ba0 arm64: dts: ti: beagle*: Add MIT license along with GPL-2.0 af13011bc32a arm64: dts: ti: k3-serdes: Add MIT license along with GPL-2.0 97f615d94c52 arm64: dts: ti: k3-pinctrl: Add MIT license along with GPL-2.0 fb7c92cfa0d7 arm64: dts: ti: k3-j784s4: Add MIT license along with GPL-2.0 ef720a09d820 arm64: dts: ti: k3-j721s2: Add MIT license along with GPL-2.0 b5d3132ac896 arm64: dts: ti: k3-j721e: Add MIT license along with GPL-2.0 a08b6e3c500d arm64: dts: ti: k3-j7200: Add MIT license along with GPL-2.0 67b92cb4a9b8 arm64: dts: ti: k3-am65: Add MIT license along with GPL-2.0 4270ef124316 arm64: dts: ti: k3-am64: Add MIT license along with GPL-2.0 6bbb88ff7998 arm64: dts: ti: k3-am62p: Add MIT license along with GPL-2.0 0ffeaa9662f1 arm64: dts: ti: k3-am625: Add MIT license along with GPL-2.0 5db4fd731c54 arm64: dts: ti: k3-am62a7: Add MIT license along with GPL-2.0 99e9047746eb arm64: dts: ti: Use https for urls 3fa55a728a3d arm64: dts: imx8mn-evk: Add PDM micphone sound card support 8d8a62fd968d arm64: dts: imx8mm-evk: Add PDM micphone sound card support 151935e24c16 arm64: dts: imx8qm: add smmu stream id information 7ca27214673d arm64: dts: imx8qm: add smmu node b9f9b709c278 arm64: dts: imx8dxl-evk: add flexcan2 and flecan3 f42aa20f9119 arm64: dts: imx8dxl-evk: add i2c3 and its children nodes 93d6366b8356 arm64: dts: imx8dxl: update flexcan[1-3] interrupt number c5d90c61def2 arm64: dts: imx8mp-phyboard-pollux-rdk: add etml panel support 16c8d47dc262 arm64: dts: imx8mn-rve-gateway: remove redundant company name b08765c243bb dt-bindings: arm: fsl: remove redundant company name 65cffffa0551 ARM: dts: samsung: exynos5420-galaxy-tab: decrease available memory d01b22a61768 dt-bindings: ata: atmel: remove at91 compact flash documentation d242043d9d60 arm64: dts: renesas: gray-hawk-single: Enable watchdog timer 2e8d8e405f93 arm64: dts: renesas: r8a779h0: Add RWDT node 35665cd38eb8 arm64: dts: renesas: Improve TMU interrupt descriptions 6c5ee3279bcd ARM: dts: renesas: Improve TMU interrupt descriptions 78e358d25cba ARM: dts: imx6ull-dhcom: Remove /omit-if-no-ref/ from node usdhc1-pwrseq f53c235dce4f arm64: dts: freescale: imx8qm: add apalis eval v1.2 carrier board c6a20bf4953d dt-bindings: arm: fsl: add imx8qm apalis eval v1.2 carrier board 4a2797e6299b dt-bindings: display: imx: add binding for i.MX8MP HDMI TX 46daefc82714 arm64: dts: exynos: Add SPI nodes for Exynos850 864d0966e626 ARM: dts: imx: Add support for Apalis Evaluation Board v1.2 ab38fa94e38c dt-bindings: arm: fsl: Add toradex,apalis_imx6q-eval-v1.2 board 79c6446e27a7 ARM: dts: imx6: skov: add aliases for all ethernet nodes 00cba1b18156 arm64: dts: imx93: Add phyBOARD-Segin-i.MX93 support ee42eae10f7a dt-bindings: arm: fsl: Add phyBOARD-Segin-i.MX93 1dcb02c43ac3 arm64: dts: imx8mp: Enable PCIe to Data Modul i.MX8M Plus eDM SBC c35148dd66cc dt-bindings: firmware: xilinx: Describe soc-nvmem subnode e4d158a009f2 arm64: dts: ls1012a: fix DWC3 USB VBUS glitch issue 2cc69dbdcc3b arm64: dts: ls1012a: add gpio for i2c bus recovery 86f029cb9916 arm64: dts: ls1012a: add big-endian property for PCIe nodes 1344dd97c94d arm64: dts: ls1012a: correct the size of dcfg block eebf4e8a4de5 arm64: dts: ti: k3-j7200: use ti,j7200-padconf compatible b2c927e92eb5 arm64: dts: ti: k3-am62p-mcu/wakeup: Disable MCU and wakeup R5FSS nodes 1ed877819eca arm64: dts: ti: k3-am69-sk: remove assigned-clock-parents for unused VP b2e13a92bcd3 dt-bindings: drm/bridge: ti-sn65dsi86: Fix bouncing @codeaurora address 5aafe0eb29a5 dt-bindings: mux: restrict node name suffixes 959645b1cb6f ARM: dts: keystone: Replace http urls with https 9c307f485cc5 arm64: dts: ti: k3-am62a7-sk: Add HDMI support 33aa21cb5f84 arm64: dts: ti: k3-am62a-main: Add node for Display SubSystem (DSS) e197413922a3 arm64: dts: ti: phycore-am64: Add ADC cbb614f03fe0 arm64: dts: ti: k3-j784s4: Fix power domain for VTM node 4979495296af arm64: dts: ti: k3-j721s2: Fix power domain for VTM node 66f98925474a arm64: dts: ti: k3-am62p5-sk: Enable CPSW MDIO node 8af95677c0a4 arm64: dts: ti: k3-j7200: Add support for multiple CAN instances 3416ecb8c84b arm64: dts: ti: k3-j7200-som-p0: Add support for CAN instance 0 in main domain b190cdb39a78 arm64: dts: ti: k3-j7200: Add support for CAN nodes 049925dbe4ef arm64: dts: ti: verdin-am62: mallow: add TPM device d18d4a279eac arm64: dts: ti: k3-am64: Remove PCIe endpoint node 45e8e613d391 arm64: dts: ti: k3-am65: Remove PCIe endpoint nodes 9482566d8484 arm64: dts: ti: k3-j7200: Remove PCIe endpoint node f2db5b44a21b arm64: dts: ti: k3-j7200: Enable PCIe nodes at the board level 1b1b2953ae47 arm64: dts: ti: k3-j721s2-som-p0: Do not split single items 1ab381b19847 arm64: dts: ti: k3-j721e-som-p0: Do not split single items 3bbf314c8e51 arm64: dts: ti: k3-j721e-sk: Do not split single items 9982ca1fa62d arm64: dts: ti: k3-j721e-beagleboneai64: Do not split single items 685e4624960e arm64: dts: ti: k3-j7200-som-p0: Do not split single items bb743de0d3fe arm64: dts: ti: k3-am69-sk: Do not split single items 6081c21a3e9b arm64: dts: ti: k3-am68-sk-som: Do not split single items 7aebe586ccdc arm64: dts: ti: k3-am654-base-board: Do not split single items 756750059f96 arm64: dts: ti: iot2050: Do not split single items 83cac2593e26 arm64: dts: ti: k3-am642-sk: Do not split single items c266381d0608 arm64: dts: ti: k3-am642-evm: Do not split single items ff6e034104fc arm64: dts: ti: k3-am642-phyboard-electra: Add TPM support 986edbf094b5 arm64: dts: ti: Disable clock output of the ethernet PHY 140c5468b668 arm64: dts: ti: Add phase tags for memory node on J784S4 EVM and AM69 SK fb6ffd10b764 arm64: dts: ti: k3-am625-beagleplay: Use the builtin mdio bus abed090f1e99 arm64: dts: ti: k3-am625-beagleplay: Add boot phase tags for USB0 0424a17ecb7a arm64: dts: ti: k3-am625-sk: Add boot phase tags for USB0 ac8143f3b013 dt-bindings: mtd: avoid automatically select from mtd.yaml 828b9467f60f media: dt-bindings: techwell,tw9900: Fix port schema ref 2b2619e4c6c5 dt-bindings: display: imx: add binding for i.MX8MP HDMI PVI 141f2102cc12 ARM: dts: imx6qdl-hummingboard: Add rtc0 and rtc1 aliases to fix hctosys ffe7dc298435 arm64: dts: imx93: drop "master" I3C node name suffix 99af7a0dae65 ARM: dts: imx6dl: Add support for Sielaff i.MX6 Solo board ff6929d462c4 dt-bindings: arm: fsl: Add Sielaff i.MX6 Solo board d3413ad34a12 arm64: dts: freescale: tqma9352: Update I2C eeprom compatible ad2d1ba26a13 arm64: dts: imx8mp: reparent MEDIA_MIPI_PHY1_REF to CLK_24M 3b589ade448f dt-bindings: gpio: pca9570: Add label property 11eb3d98d38b dt-bindings: gpio: mvebu: Fix "unevaluatedProperties" to be false 9c0a4b40a3ac ARM: dts: imx6ul: Add missing #thermal-sensor-cells to tempmon fee43501308a arm64: dts: imx8mp-verdin: Label ldo5 and link to usdhc2 b8d7d5f3690b arm64: dts: imx93-var-som: Add Variscite VAR-SOM-MX93 188a8bb94d35 dt-bindings: arm: fsl: Add VAR-SOM-MX93 with Symphony fecb422bac6a arm64: dts: ls1046a: Remove big-endian from thermal 78343d7acd50 ARM: dts: imx6sl-tolino-shine2hd: fix touchscreen rotation e57037e98946 ARM: dts: imx6ull-dhcor: Remove 900MHz operating point 31d9e29f0d8e Merge tag 'drm-misc-next-2024-01-11' of git://anongit.freedesktop.org/drm/drm-misc into drm-next e6d71526460e dt-bindings: misc: xlnx,sd-fec: convert bindings to yaml 01b5de94aa82 Merge 6.8-rc3 into tty-next 7030aa5067b6 Merge 6.8-rc3 into usb-next 5f856030cc8b arm64: dts: rockchip: Add devicetree for Pine64 PineTab2 c87344c32c61 dt-bindings: arm64: rockchip: Add Pine64 PineTab2 6944e5df2f35 arm64: dts: rockchip: Add Touch to Anbernic RG-ARC D 9a90efccd7ee ARM: dts: microchip: gardena-smart-gateway: Use DMA for USART3 9a2b5d99e0ff ARM: dts: microchip: at91sam9x5ek: Use DMA for DBGU serial port 7051d52cf5b9 arm64: dts: imx8mp-venice-gw71xx: add TPM device 4ecbc5946cc5 arm64: dts: imx8mm-venice-gw71xx: add TPM device 3c805459dfd7 arm64: dts: imx8mm-venice-gw71xx: fix USB OTG VBUS af9118771e3c arm64: dts: imx8mm-venice-gw7901: add TPM device bcc4aff9ee00 arm64: dts: imx8mm-venice-gw7901: add digital I/O direction control GPIO's 6ea0c6a49b64 ARM: dts: imx7-tqma7: Fix PMIC v33 rail voltage range 2482c75bff8e ARM: dts: imx7-mba7: Add missing vcc supply to i2c devices 4d19ec066c6b ARM: dts: imx7-tqma7: Add missing vcc supply to i2c eeproms fda2672c8e68 ARM: dts: imx7d-mba7: Remove USB OTG related properties on USB node f71b70123d20 ARM: dts: imx7-tqma7: rename node for SE97BTP 56382af8168e ARM: dts: imx7-tqma7: mark system data eeprom as read-only 59c9c040a0db ARM: dts: imx7-tqma7: remove superfluous status property ac9f05a3b8ee ARM: dts: imx7-tqma7: restrict usdhc interface modes 54b93adb1393 ARM: dts: imx7-mba7: restrict usdhc interface modes 6980af2d9f17 ARM: dts: imx7-tqma7: Fix iomuxc node names efad19cdde77 ARM: dts: imx7-mba7: Fix iomuxc node names fe330835b74e ARM: dts: imx7-tqma7: fix EEPROM compatible for SE97BTP 77f6e05fdfa1 ARM: dts: imx7-mba7: Add i2c bus recovery 8f9993282d52 ARM: dts: imx7-tqma7: Add i2c bus recovery 4065cdaa82bd ARM: dts: imx7-mba7: Add SPI1_SS0 as chip select 3 10cde7452d93 ARM: dts: imx7-mba7: Add RTC aliases 67c6d0e81520 ARM: dts: imx7-mba7: Enable SNVS power key 2ccae767cb74 ARM: dts: imx7-mba7: Mark gpio-buttons as wakeup-source 235e861d016e ARM: dts: imx7[d]-mba7: hog Mini PCIe signals cd553893ac90 ARM: dts: imx7[d]-mba7: disable PCIe interface 2faa76d25aef ARM: dts: imx7[d]-mba7: disable USB OC on USB host and USB OTG2 f9152233518d ARM: dts: imx7[d]-mba7: Move ethernet PHY reset into PHY node 0d8f0cba144c ARM: dts: imx7-tqma7/mba7: convert fsl,pins to uint32-matrix c09e630c5912 arm64: dts: qcom: qcm6490-idp: Include PM7250B edd0bc8b8d0b arm64: dts: qcom: sm8650: Use GIC-ITS for PCIe0 and PCIe1 4fe52e68f13c arm64: dts: qcom: qcm6490-idp: Add definition for three LEDs cc592e051541 arm64: dts: qcom: sm8650-qrd: add USB-C Altmode Support b789944a89fc arm64: dts: qcom: sm8550-qrd: enable Touchscreen 200b0b3875ef dt-bindings: clock: qcom: Fix @codeaurora email in Q6SSTOP 5eaa8712fb96 dt-bindings: visionox-rm69299: Update maintainers ae0b823f0536 dt-bindings: gpio: renesas,rcar-gpio: Add r8a779h0 support d4458c6492e6 dt-bindings: net: ti: Update maintainers list a3fa7f3f82f7 dt-bindings: net: ipq4019-mdio: document now supported clock-frequency 9c3280cd3020 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net 19adc3b90590 Merge branch '20240201204421.16992-2-quic_amelende@quicinc.com' into drivers-for-6.9 b5c560279d08 dt-bindings: soc: qcom: Add qcom,pbs bindings 08d014730db7 regulator: dt-bindings: microchip,mcp16502: convert to YAML bdef327947f5 arm64: dts: intel: agilex5: drop "master" I3C node name suffix 1c0d4ea255ee media: ov08x40: Reduce start streaming time 7d92af412d2e arm64: dts: exynos: Add PDMA node for Exynos850 1868ee800d4c arm64: dts: exynos: gs101: use correct clocks for usi_uart 5d5769f28954 arm64: dts: exynos: gs101: use correct clocks for usi8 dc00c7274ea6 dt-bindings: net: dsa: Add KSZ8567 switch support 58475bd50ec5 media: arm64: dts: st: add video encoder support to stm32mp255 380408454fb2 media: arm64: dts: st: add video decoder support to stm32mp255 4eea1b53e82e media: dt-bindings: media: Document STM32MP25 VDEC & VENC video codecs 39ecce7ee54a arm64: dts: imx8qxp: add GPU nodes b206b48e8a91 arm64: dts: imx8qm: Correct edma3 power-domains and interrupt numbers 7a74326b4893 arm64: dts: imx8qm: Align edma3 power-domains resources indentation 0be926d25dbc arm64: dts: imx8qxp: mba8xx: Add analog audio output on MBa8Xx 43aab34e5e0c arm64: dts: imx8qxp: Add mclkout clock gates 8c7666d283be arm64: dts: imx8qxp: Add audio SAI nodes a12fa3d0c150 arm64: dts: imx8qxp: Add audio clock mux node 6c44f7583fd5 arm64: dts: imx8qxp: Add ACM input clock gates cf7ea553fe5a arm64: dts: freescale: add initial device tree for TQMa8Xx 98de130e34e4 dt-bindings: arm: add TQMa8Xx boards dc089f5f4bb0 arm64: dts: imx: add imx8dxp support a5a40554f207 dt-bindings: net: qcom,ipa: do not override firmware-name $ref 927f00767ef5 arm64: dts: imx8mm-kontron: Refactor devicetree for OSM-S module and board dc0c1bca1831 arm64: dts: imx8mm-kontron: Add I2C EEPROM on OSM-S Kontron i.MX8MM 071edd561a01 arm64: dts: imx8mm-kontron: Remove useless trickle-diode-disable from RTC node bc9a25d78a35 arm64: dts: imx8mm-kontron: Disable uneffective PUE bit in SDIO IOMUX 48e6dc42724c arm64: dts: imx8mm-kontron: Fix OSM-S devicetrees to match latest hardware 1749a50ca797 arm64: dts: imx8mm-kontron: Fix interrupt for RTC on OSM-S i.MX8MM module 6985d8cd5c40 arm64: dts: imx8mm-kontron: Disable pull resistors for SD card signals on BL board 688fff06ac4e arm64: dts: imx8mm-kontron: Disable pull resistors for SD card signals on BL OSM-S board 4b8efdb73a46 arm64: dts: imx8mm-kontron: Disable pullups for onboard UART signals on BL board 123efe05e212 arm64: dts: imx8mm-kontron: Disable pullups for onboard UART signals on BL OSM-S board 9f02292756b9 arm64: dts: imx8mm-kontron: Disable pullups for I2C signals on SL/BL i.MX8MM 928dc77f0003 arm64: dts: imx8mm-kontron: Disable pullups for I2C signals on OSM-S i.MX8MM c2b4ecb58452 dt-bindings: fpga: Convert fpga-region binding to yaml 85d6c583d5f5 MAINTAINERS: Drop my "+dt" sub-address 0f6ed4032e99 dt-bindings: timer: renesas,tmu: Document input capture interrupt 05c9f46083ba arm64: dts: renesas: r9a07g043u: Add CSI and CRU nodes aa403cfc2a6c arm64: dts: renesas: Add Gray Hawk Single board support 82a8a0a3e608 arm64: dts: renesas: Add Renesas R8A779H0 SoC support 356004f72bd0 Merge tag 'renesas-r8a779h0-dt-binding-defs-tag' into renesas-dts-for-v6.9 1200029387ce arm64: dts: renesas: rzg3s-smarc-som: Enable the watchdog interface d58eb8846937 arm64: dts: renesas: r9a08g045: Add watchdog node b1de14ce277c arm64: dts: renesas: r8a779g0: Add missing SCIF_CLK2 fe98cda6e099 dt-bindings: soc: renesas: Document R-Car V4M Gray Hawk Single bcdc951ea508 dt-bindings: reset: renesas,rst: Document R-Car V4M support 55647b66aba2 pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28 fc9d9f1cfef8 dt-bindings: interconnect: Remove bogus interconnect nodes 47509af4504a soundwire/SOF: add SoundWire Interface support for f521b204bcd2 dt-bindings: interconnect: Add Qualcomm MSM8909 DT bindings 72ececa06e31 riscv: dts: starfive: beaglev-starlight: Setup phy reset gpio 0279da4a6715 riscv: dts: starfive: visionfive-v1: Setup ethernet phy 19f7725fe372 riscv: dts: starfive: jh7100-common: Setup pinmux and enable gmac d05053a8b239 riscv: dts: starfive: jh7100: Add sysmain and gmac DT nodes 921e5e1327ef dt-bindings: net: starfive,jh7110-dwmac: Add JH7100 SoC compatible 7020ebc26757 dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions 35d633af4efc dt-bindings: clock: renesas,cpg-mssr: Document R-Car V4M support 1de76ced2497 dt-bindings: soc: xilinx: Add support for KV260 CC c9aeb5c33863 dt-bindings: soc: xilinx: Add support for K26 rev2 SOMs e36f379d8c82 dt-bindings: pinctr: pinctrl-zynq: Fix compatible string c7a574ba2a6c dt-bindings: pinctrl: nuvoton,npcm845: Drop redundant type for "slew-rate" da1b37add707 dt-bindings: pinctrl: Unify "input-debounce" schema 234d836b6a1a dt-bindings: input: document Goodix Berlin Touchscreen IC 8df2aa5a1297 arm64: dts: qcom: Add support for Xiaomi Redmi Note 9S 5c09bd2b6ce1 arm64: dts: qcom: sm7125-xiaomi-common: Add UFS nodes 5c38e796a3a1 arm64: dts: qcom: sc7180: Add UFS nodes 307cdcc3f9c2 dt-bindings: arm: qcom: Add Xiaomi Redmi Note 9S d9eda103eb64 ARM: dts: qcom: apq8026-lg-lenok: Add vibrator support 2590e420cf2c ARM: dts: qcom: msm8960: expressatt: Add gpio-keys 9d906fe262e0 arm64: dts: qcom: sda660-ifc6560: enable USB 3.0 PHY 6b10b59bd1db arm64: dts: qcom: sdm630: add USB QMP PHY support 329fb714e840 arm64: dts: qcom: sc8280xp: camss: Add CAMSS block definition ca14c11bb9a4 arm64: dts: qcom: sc8280xp: camss: Add CCI definitions 5ce7895c7b2b dt-bindings: clock: qcom: Allow VDD_GFX supply to GX 3a9a9247f661 arm64: dts: qcom: sa8295p-adp: Enable GPU 08f93d65d530 arm64: dts: qcom: sa8295p-adp: add max20411 1129eea99cc1 arm64: dts: qcom: sa8540p: Drop gfx.lvl as power-domain for gpucc 14bc12ecdfe3 dt-bindings: interrupt-controller: convert MediaTek sysirq to the json-schema 77a4323bd64f dt-bindings: dma: allwinner,sun50i-a64-dma: Add compatible for H616 82bf0037e8d8 dt-bindings: power: Add r8a779h0 SYSC power domain definitions d98d5e6ce56e dt-bindings: power: renesas,rcar-sysc: Document R-Car V4M support 5ee26dab625b dt-bindings: bus: Document Broadcom GISB arbiter 74165 compatible c6234d82a072 arm64: dts: broadcom: bcmbca: bcm4908: drop invalid switch cells bc4ef25abdc1 arm64: dts: broadcom: bcmbca: bcm4908: use NVMEM layout for Asus GT-AC5300 b6e08822ed8c arm64: dts: renesas: r8a779g2: Add White Hawk Single support 7e3862db4c62 arm64: dts: renesas: Add Renesas R8A779G2 SoC support 51fc2376ba1d arm64: dts: renesas: white-hawk: Factor out common parts a248c1746935 arm64: dts: renesas: white-hawk-cpu: Factor out common parts fdea5d785497 arm64: dts: renesas: white-hawk: Add SoC name to top-level comment a77e323e0dc2 arm64: dts: renesas: white-hawk: Drop SoC parts from sub boards 3e8f05b2b81d arm64: dts: renesas: white-hawk-cpu: Restore sort order e90ffb9d53b7 arm64: dts: renesas: r8a779g0: Add standalone White Hawk CPU support eccddc31dfa9 arm64: dts: renesas: ulcb-kf: Add node for GNSS 3d3e628e12d6 arm64: dts: renesas: ulcb-kf: Drop duplicate 3.3v regulators bf721e67a7fb Merge drm/drm-next into drm-misc-next 351548ba8841 dt-bindings: soc: renesas: Document R-Car V4H White Hawk Single ad352af0d46f dt-bindings: nfc: ti,trf7970a: fix usage example d4d212c5cf34 dt-bindings: display: panel-simple: add ETML1010G3DRA 6aee668021fc arm64: dts: qcom: sm7225-fairphone-fp4: Switch firmware ext to .mbn aa54779772ae arm64: dts: qcom: rename PM2250 to PM4125 dbcb19ed3275 arm64: dts: qcom: qcm6490-fairphone-fp5: Add PMIC GLINK dc376fa4a27c arm64: dts: qcom: sdm845-oneplus-common: improve DAI node naming 048423deb9a5 arm64: dts: qcom: qcm6490-fairphone-fp5: Add missing reserved-memory b4d0c1c61afa arm64: dts: qcom: sc7280: Add static properties to cryptobam f3f780c01899 arm64: dts: qcom: sa8775p: enable safety IRQ fd61cbbd53a9 dt-bindings: clock: qcom,gcc-sm8150: Add gcc video resets for sm8150 30e2fa95b585 dt-bindings: arm: qcom,ids: add SoC ID for QCM8550 and QCS8550 27f4e6aa609c dt-bindings: Add reference to rs485.yaml 5e11848e4c98 dt-bindings: serial: renesas,hscif: Document r8a779h0 bindings c7aaa6160c61 dt-bindings: serial: fsl-lpuart: support i.MX95 3ee8c19304d9 dt-bindings: serial: samsung: do not allow reg-io-width for gs101 d70fdb79f945 arm64: dts: qcom: apq8016-sbc-d3-camera: Use more generic node names 95830229bcb5 ARM: dts: qcom: msm8960: drop 2nd clock frequency from timer 4f433e3e9a04 ARM: dts: qcom: ipq4019-ap.dk01.1: align flash node with bindings 39065990752b ARM: dts: qcom: ipq4019-ap.dk01.1: use existing labels for nodes a6106c8748a7 arm64: dts: qcom: split PCIe interrupt-names entries per lines f1ac2340280d arm64: dts: qcom: sm8650: describe all PCI MSI interrupts 653638c9dceb arm64: dts: qcom: sm8550: describe all PCI MSI interrupts 90840a974369 arm64: dts: qcom: sm8450: describe all PCI MSI interrupts c681c8ad796c arm64: dts: qcom: sm8350: describe all PCI MSI interrupts 9186fa649278 arm64: dts: qcom: sm8250: describe all PCI MSI interrupts a2e5b5e27b91 arm64: dts: qcom: sm8150: describe all PCI MSI interrupts ed0b4f3e69ba ARM: dts: qcom: msm8926-htc-memul: Add rmtfs memory node 3556e0895e7a dt-bindings: usb: dwc3: Add snps,host-vbus-glitches-quirk avoid vbus glitch 75bae0c78ef3 dt-bindings: usb: usb-nop-xceiv: Repurpose vbus-regulator 20e5fb946959 dt-bindings: usb: mtu3: Add MT8195 MTU3 ip-sleep support 0145e6824861 dt-bindings: usb: Clean-up "usb-phy" constraints eb9bdcaff280 dt-bindings: usb: add common Type-C USB Switch schema a67690a90fb9 dt-bindings: usb: Add Marvell ac5 59434babb8e4 arm64: dts: qcom: sm8450: Add missing interconnects to serial 6b60607aa5cc dt-bindings: usb: Introduce ITE IT5205 Alt. Mode Passive MUX fe0ce9c54778 dt-bindings: pinctrl: amlogic: narrow regex for unit address to hex numbers 8c58779baca1 dt-bindings: qcom: Document new msm8916-samsung devices 1438aadecf94 arm64: dts: qcom: sm8450-hdk: correct AMIC4 and AMIC5 microphones b4d502118ad4 arm64: dts: qcom: sm8150: add necessary ref clock to PCIe 018a13d36a57 arm64: dts: qcom: sdm630: Hook up GPU cooling device 2b51fa0934c8 arm64: dts: qcom: sm8550: Hook up GPU cooling device 15018cdc0470 arm64: dts: qcom: sm8450: Hook up GPU cooling device f5906fc26422 arm64: dts: qcom: sm8350: Hook up GPU cooling device 9df3c73a8511 arm64: dts: qcom: sm8250: Hook up GPU cooling device 257e0300ca3a arm64: dts: qcom: sm8150: Hook up GPU cooling device b16301e27866 arm64: dts: qcom: sm6115: Mark GPU @ 125C critical ccc769ffd9fa arm64: dts: qcom: sm6115: Hook up GPU cooling device cf4e80b514f2 arm64: dts: qcom: sdm845: Hook up GPU cooling device 6ddaa894ac00 arm64: dts: qcom: sc8180x: Hook up GPU cooling device 1a13cc6e08c9 arm64: dts: qcom: msm8939: Hook up GPU cooling device 04962e8ee80d arm64: dts: qcom: msm8916: Hook up GPU cooling device de58665d5a86 arm64: dts: qcom: x1e80100: Flush RSC sleep & wake votes 5792135ff692 arm64: dts: qcom: x1e80100: Add missing system-wide PSCI power domain 7dddf3cf2c2d dt-bindings: soc/qcom: Add size constraints on "qcom,rpm-msg-ram" f3e26b603762 arm64: dts: qcom: Add missing interrupts for qcs404/ipq5332 d2eb087d6a3f arm64: dts: qcom: Fix hs_phy_irq for SDM670/SDM845/SM6350 e912f5a885bc arm64: dts: qcom: Fix hs_phy_irq for non-QUSB2 targets cc58f6b02229 arm64: dts: qcom: Fix hs_phy_irq for QUSB2 targets ed2747597b2e arm64: dts: qcom: sm8550: add support for the SM8550-HDK board 0beb12a79761 dt-bindings: arm: qcom: Document the HDK8550 board 1182dc50de01 dt-bindings: net: Document QCA808x PHYs 8869fe2b8c59 dt-bindings: net: phy: Document LED inactive high impedance mode 8a5d470f446f dt-bindings: net: phy: Make LED active-low property common ee170c770dce ASoC: dt-bindings: audio-graph-port: Drop type from "clocks" 52dc7498eed1 ASoC: dt-bindings: samsung,tm2: Correct "audio-codec" constraints 2294f77ec0a5 ARM: dts: sti: minor whitespace cleanup around '=' e8f034522bd8 arm64: dts: exynos: gs101: sysreg_peric0 needs a clock d7849025c947 ARM: dts: da850: add MMD SDIO interrupts f831c925b07a ARM: dts: marvell: dove-cubox: fix si5351 node names 70e16db126d5 arm: dts: marvell: Fix maxium->maxim typo in brownstone dts 29fba2976ec3 dt-bindings: crypto: ice: Document SC7180 inline crypto engine 3d331a17e8c9 dt-bindings: qcom-qce: Add compatible for SM6350 4fd1499f0d02 arm64: dts: ti: k3-am654-main: Add device tree entry for SGX GPU 459e64009a83 ARM: dts: DRA7xx: Add device tree entry for SGX GPU 33828a263695 ARM: dts: AM437x: Add device tree entry for SGX GPU b812a94b3a14 ARM: dts: AM33xx: Add device tree entry for SGX GPU a43b7f4412c3 ARM: dts: omap5: Add device tree entry for SGX GPU 26a571cb3312 ARM: dts: omap4: Add device tree entry for SGX GPU 0590991057c3 ARM: dts: omap3: Add device tree entry for SGX GPU 6cfc912186fd dt-bindings: gpu: Add PowerVR Series5 SGX GPUs ecd5e84cb911 dt-bindings: gpu: Rename img,powervr to img,powervr-rogue 674fba836cdb arm64: dts: rockchip: fix nanopc-t6 sdmmc regulator 33b030710624 arm64: dts: rockchip: remove duplicate SPI aliases for helios64 7c0fd87b35a8 arm64: dts: rockchip: add spi controller aliases on rk3399 774db835de8a arm64: dts: rockchip: Add support for NanoPi R6C 245ed9f66edb arm64: dts: rockchip: Add support for NanoPi R6S 7ed25d8d0d24 dt-bindings: arm: rockchip: Add NanoPi R6 series boards 4fc6e0686faf arm64: dts: rockchip: Increase maximum frequency of SPI flash for ROCK Pi 4A/B/C 47aafd8512e1 arm64: dts: rockchip: add sdmmc card detect to the nanopc-t6 5bdf0ecf003d arm64: dts: rockchip: Add cache information to the SoC dtsi for RK3399 3d67b6c2a2af ARM: dts: rockchip: Enable HDMI output for XPI-3128 8ac6f9cf696a ARM: dts: rockchip: Add HDMI node for RK3128 06cbcacf56ad ARM: dts: rockchip: Add display subsystem for RK3128 9a9dc5b9e06a arm64: dts: rockchip: add rfkill node for M.2 Key E WiFi on rock-5b c7f1c6bb420a arm64: dts: rockchip: enable NanoPC-T6 MiniPCIe power 9604142e6a0d arm64: dts: rockchip: Add LED_GREEN for edgeble-neu6a cbd461ded362 arm64: dts: rockchip: Add Edgeble NCM6A-IO USB2 051aa218e679 arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 B-Key, E-Key e24b6c90f78b arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 M-Key c04566174738 arm64: dts: rockchip: Add Edgeble NCM6A-IO 2.5G ETH 1696541973b9 arm64: dts: rockchip: Add vdd_cpu_big reg to rk3588-edgeble-ncm6 fed4b47f48ac arm64: dts: rockchip: Add Edgeble NCM6A WiFi6 Overlay 648060033a16 arm64: dts: rockchip: Add common DT for edgeble-neu6b-io 14b26b2835cb arm64: dts: rockchip: Add edgeble-neu6a-common DT 8360c7a53f95 arm64: dts: rockchip: Drop edgeble-neu6b dcdc-reg4 regulator-init-microvolt e497dc0158dd arm64: dts: rockchip: add missing definition of pmu io domains 1 and 2 on ringneck f1cb710d9302 arm64: dts: rockchip: add Anbernic RG-ARC S and RG-ARC D 351c26e7934f dt-bindings: arm: rockchip: Add Anbernic RG-Arc 294dd835c5d0 arm64: dts: rockchip: Move device specific properties e8f6b6072ce6 dt-bindings: soc: rockchip: Add rk3588 hdptxphy syscon 663d347eb7a7 ARM: dts: stm32: fix DSI peripheral clock on stm32mp15 boards 6e307e6bd72d dt-bindings: memory-controllers: narrow regex for unit address to hex numbers ef93727c9def spi: dt-bindings: samsung: Add Exynos850 SPI c714a4c1273b ARM: dts: qcom: use defines for interrupts 7f37d45ff70d ARM: dts: qcom: apq8026-samsung-matissewifi: Configure touch keys cf76727f86a3 ARM: dts: stm32: lxa-tac: drive powerboard lines as open-drain 19fee3189355 dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHYs 899bb26cef2c dt-bindings: iio: adc: rtq6056: add support for the whole RTQ6056 family 09065a127e3c dt-bindings: input: melfas,mms114: add MMS252 compatible ef76ae751c3c dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: support SDM660 97fd9e67ede2 dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: add TCSR registers 25bfbe442a13 dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: support USB-C data 6ec985dff442 dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: split from sc8280xp PHY schema 8b41b5f06d8a arm64: dts: exynos: gs101: enable eeprom on gs101-oriole eb43c96a2716 arm64: dts: exynos: gs101: define USI8 with I2C configuration 688d19a4c1d5 arm64: dts: exynos: gs101: update USI UART to use peric0 clocks c8631c01c9d5 arm64: dts: exynos: gs101: enable cmu-peric0 clock controller 7f078f4efe48 arm64: dts: exynos: gs101: remove reg-io-width from serial dfa299ac5670 arm64: dts: exynos: gs101: define Multi Core Timer (MCT) node dd8d6cdb498f dt-bindings: clock: tesla,fsd: Fix spelling mistake 2a50cd8b4cad Merge tag 'samsung-dt-bindings-clk-6.9-2' into next/clk 1308a1709db2 dt-bindings: clock: exynos850: Add PDMA clocks 5f252cf1954d dt-bindings: clock: google,gs101-clock: add PERIC0 clock management unit b7045107b13d dt-bindings: phy: Add QMP UFS PHY compatible for SC7180 806828c18886 arm64: dts: qcom: sc8180x: Add RPMh sleep stats 8bfa57f18d67 arm64: dts: qcom: sc8180x: Shrink aoss_qmp register space size 39124f597a6a arm64: dts: qcom: sc8180x: Add missing CPU<->MDP_CFG path 076044c5542f arm64: dts: qcom: sc8180x: Require LOW_SVS vote for MMCX if DISPCC is on 76f855a9dca6 arm64: dts: qcom: sc8180x: Don't hold MDP core clock at FMAX 37f3285d146b arm64: dts: qcom: sc8180x: Fix eDP PHY power-domains 5e5b25b16167 arm64: dts: qcom: sc8180x: Add missing CPU off state a971a001fe6a arm64: dts: qcom: sc8180x: Fix up big CPU idle state entry latency d43c023044f1 arm64: dts: qcom: sc8180x: Hook up VDD_CX as GCC parent domain 0a90e0fc5c4b dt-bindings: clock: gcc-sc8180x: Add the missing CX power domain 7d930fbfa6d1 riscv: dts: starfive: jh7110: Add PWM node and pins configuration 98729d5d619d riscv: dts: starfive: jh7100: Add PWM node and pins configuration 2613a64bdc5e dt-bindings: spi: nxp-fspi: support i.MX93 and i.MX95 36d4b81404af dt-bindings: spi: fsl-lpspi: support i.MX95 LPSPI 3ff4d525b9f7 ASoC: dt-bindings: fsl-sai: Support Rx-only SAI fc98068e41fe ASoC: dt-bindings: fsl-sai: Add power-domains 7e4487f7e723 ASoC: Support SAI and MICFIL on i.MX95 platform 170639843215 dt-bindings: iio: pressure: honeywell,mprls0025pa.yaml add spi bus e06b0404e4ef dt-bindings: iio: pressure: honeywell,mprls0025pa.yaml add pressure-triplet cb500c9133ee dt-bindings: iio: pressure: honeywell,mprls0025pa.yaml improvements 0c9fbdab661d dt-bindings: iio: light: as73211: add support for as7331 668faa4c00b6 ARM: dts: qcom: ipq4019: correct clock order in DWC3 node 01f571222843 ARM: dts: qcom: sdx65: correct clock order in DWC3 node f0606dbf1b06 ARM: dts: qcom: ipq8064: drop unused reset-names from DWC3 node 638f430aa2c5 arm64: dts: qcom: qcm6490-fairphone-fp5: Enable venus node 2bf14ff2de89 arm64: dts: qcom: sc7280: Move video-firmware to chrome-common e694053a2504 arm64: dts: qcom: x1e80100: drop qcom,drv-count ae0bc4781d25 arm64: dts: qcom: sc7280: Add additional MSI interrupts fbc40e8570be dt-bindings: pwm: Add bindings for OpenCores PWM Controller f86a5abc5095 ASoC: codecs: add support for WCD939x Codec 0023860e3cd8 dt-bindings: Add DPS310 as trivial device 4d5cba356b2e docs: dt: submitting-patches: add commit subject prefix in reversed format 86c6d04414f3 docs: dt: submitting-patches: drop outdated points to TXT format 20fea215870b dt-bindings: Turn on undocumented compatible checks c15bd0d0ea0d arm64: zynqmp: Align usb clock nodes with binding 506404184883 arm64: zynqmp: Comment all smmu entries 702fb0df1a8d arm64: zynqmp: Rename i2c?-gpio to i2c?-gpio-grp 8dae08d3ef0c arm64: zynqmp: Disable Tri-state for MIO38 Pin 08cee7c9acca arm64: zynqmp: Remove incorrect comment from kv260s c28bc39bcbe4 arm64: zynqmp: Introduce u-boot options node with bootscr-address 346b5266ae26 arm64: zynqmp: Fix comment to be aligned with board name. 69a088e616d5 arm64: zynqmp: Update ECAM size to discover up to 256 buses c78a834d7d85 arm64: zynqmp: Describe assigned-clocks for uarts aab3209386cd arm64: zynqmp: Setup default si570 frequency to 156.25MHz 70d8c607c90e arm64: zynqmp: Add resets property for CAN nodes 1e662bbad32e arm64: zynqmp: Add an OP-TEE node to the device tree b97de3d1f0f1 arm64: zynqmp: Add output-enable pins to SOMs 5149181eb2a0 arm64: zynqmp: Rename zynqmp-power node to power-management 4bbdddd5f137 dt-bindings: firmware: xilinx: Sort node names (clock-controller) bbe26a5d3a74 dt-bindings: firmware: xilinx: Describe missing child nodes 3bb58ba1f178 dt-bindings: firmware: xilinx: Fix versal-fpga node name 552578beff16 dt-bindings: firmware: versal: add versal-net compatible string a1e42c2d1feb dt-bindings: timer: exynos4210-mct: Add google,gs101-mct compatible 793923947260 dt-bindings: i2c: exynos5: add google,gs101-hsi2c compatible e40d0f28e904 ARM: dts: samsung: exynos4412-p4note: add accelerometer and gyro to p4note b0f7ebf9ebb5 ARM: dts: samsung: exynos5800-peach: Enable cros-ec-spi as wake source 7fb70f62fdc1 ARM: dts: samsung: exynos5420-peach: Enable cros-ec-spi as wake source 69ffe89c1f09 ARM: dts: samsung: exynos5422-odroidxu3: disable thermal polling efc6740c2555 arm64: dts: renesas: r8a779g0: Restore sort order 4d29837048f1 ARM: dts: renesas: r8a73a4: Fix thermal parent clock b3b5e2c31a6a ARM: dts: renesas: r8a73a4: Add cp clock 0355cc519d58 ARM: dts: renesas: r8a73a4: Fix external clocks and clock rate c7faddebe0f9 arm64: dts: renesas: rzg3s-smarc: Add gpio keys cf58f575cc98 dt-bindings: regulator: Convert ti,tps65132 to YAML fc588d5d53ae ASoC: dt-bindings: Do not override firmware-name $ref 81002cf24ea5 ASoC: dt-bindings: document WCD939x Audio Codec f47aa77e7a94 ASoC: dt-bindings: qcom,wcd938x: move out common properties d7f07526a034 ASoC: dt-bindings: fsl,micfil: Add compatible string for i.MX95 platform e4fa9d184d78 ASoC: dt-bindings: fsl,sai: Add compatible string for i.MX95 platform 6d65dad20b03 dt-bindings: input: touchscreen: goodix: clarify irq-gpios misleading text 1f08757666ca dt-bindings: input: silead,gsl1680: do not override firmware-name $ref ffc68c88254b dt-bindings: display: panel: Add Novatek NT36672E LCD DSI 22dafcaa7945 dt-bindings: display: panel: Add BOE TH101MB31IG002-28A panel 29e394c3abcd dt-bindings: nt35510: add compatible for FRIDA FRD400B25025-A-CTK c378224488e5 dt-bindings: display: Add SSD133x OLED controllers d4d009fba537 dt-bindings: display: ssd132x: Add vendor prefix to width and height b74c86bcffbc dt-bindings: display: ssd1307fb: Add vendor prefix to width and height 140b66753a95 dt-bindings: panel: lvds: Append edt,etml0700z9ndha in panel-lvds git-subtree-dir: dts/upstream git-subtree-split: 7e08733c96c84eb323f47e9b248c924e2ac6272a --- Bindings/Makefile | 3 - Bindings/arm/amlogic.yaml | 15 +- Bindings/arm/arm,realview.yaml | 6 +- Bindings/arm/atmel-at91.yaml | 6 + Bindings/arm/fsl.yaml | 41 +- Bindings/arm/marvell/armada-38x.txt | 27 - Bindings/arm/marvell/armada-38x.yaml | 70 + Bindings/arm/mediatek.yaml | 198 +- Bindings/arm/mediatek/mediatek,hifsys.txt | 26 - Bindings/arm/mediatek/mediatek,pciesys.txt | 25 - Bindings/arm/mediatek/mediatek,ssusbsys.txt | 25 - Bindings/arm/msm/qcom,saw2.txt | 58 - Bindings/arm/qcom,coresight-tpdm.yaml | 40 +- Bindings/arm/qcom.yaml | 58 +- Bindings/arm/rockchip.yaml | 71 +- Bindings/arm/sunxi.yaml | 12 + Bindings/arm/syna.txt | 12 - Bindings/arm/tegra.yaml | 8 + Bindings/arm/tegra/nvidia,tegra186-pmc.yaml | 54 +- Bindings/arm/ti/k3.yaml | 14 + Bindings/ata/ahci-mtk.txt | 51 - Bindings/ata/atmel-at91_cf.txt | 19 - Bindings/ata/mediatek,mtk-ahci.yaml | 98 + Bindings/auxdisplay/arm,versatile-lcd.yaml | 4 +- Bindings/auxdisplay/gpio-7-segment.yaml | 55 + Bindings/auxdisplay/hit,hd44780.yaml | 62 +- Bindings/auxdisplay/holtek,ht16k33.yaml | 50 +- Bindings/auxdisplay/img,ascii-lcd.yaml | 4 +- Bindings/auxdisplay/maxim,max6959.yaml | 44 + Bindings/bus/brcm,gisb-arb.yaml | 1 + Bindings/bus/imx-weim.txt | 117 - Bindings/clock/google,gs101-clock.yaml | 28 +- Bindings/clock/keystone-gate.txt | 2 - Bindings/clock/keystone-pll.txt | 2 - Bindings/clock/mediatek,mt2701-hifsys.yaml | 50 + Bindings/clock/mediatek,mt7622-pciesys.yaml | 45 + Bindings/clock/mediatek,mt7622-ssusbsys.yaml | 45 + Bindings/clock/mobileye,eyeq5-clk.yaml | 51 + Bindings/clock/qcom,gcc-sc8180x.yaml | 7 + Bindings/clock/qcom,gpucc.yaml | 9 + Bindings/clock/qcom,q6sstopcc.yaml | 2 +- Bindings/clock/qcom,sc7180-mss.yaml | 61 - Bindings/clock/qcom,sm8450-camcc.yaml | 2 + Bindings/clock/qcom,sm8450-gpucc.yaml | 2 + Bindings/clock/qcom,sm8550-dispcc.yaml | 7 +- Bindings/clock/qcom,sm8550-tcsr.yaml | 1 + Bindings/clock/qcom,sm8650-dispcc.yaml | 106 - Bindings/clock/renesas,cpg-mssr.yaml | 1 + Bindings/clock/samsung,exynos850-clock.yaml | 42 + Bindings/clock/tesla,fsd-clock.yaml | 2 +- Bindings/clock/ti/adpll.txt | 2 - Bindings/clock/ti/apll.txt | 2 - Bindings/clock/ti/autoidle.txt | 2 - Bindings/clock/ti/clockdomain.txt | 2 - Bindings/clock/ti/composite.txt | 2 - Bindings/clock/ti/divider.txt | 2 - Bindings/clock/ti/dpll.txt | 2 - Bindings/clock/ti/fapll.txt | 2 - Bindings/clock/ti/fixed-factor-clock.txt | 2 - Bindings/clock/ti/gate.txt | 2 - Bindings/clock/ti/interface.txt | 2 - Bindings/clock/ti/mux.txt | 2 - Bindings/crypto/atmel,at91sam9g46-aes.yaml | 6 +- Bindings/crypto/atmel,at91sam9g46-sha.yaml | 6 +- Bindings/crypto/atmel,at91sam9g46-tdes.yaml | 6 +- .../crypto/qcom,inline-crypto-engine.yaml | 1 + Bindings/crypto/qcom-qce.yaml | 1 + .../atmel/atmel,hlcdc-display-controller.yaml | 63 + Bindings/display/atmel/hlcdc-dc.txt | 75 - .../display/bridge/fsl,imx8mp-hdmi-tx.yaml | 102 + Bindings/display/bridge/ti,sn65dsi86.yaml | 2 +- Bindings/display/fsl,lcdif.yaml | 8 +- Bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml | 84 + Bindings/display/msm/dsi-controller-main.yaml | 2 + Bindings/display/msm/gmu.yaml | 1 + Bindings/display/msm/gpu.yaml | 6 +- Bindings/display/msm/qcom,mdss.yaml | 1 + Bindings/display/msm/qcom,sm8150-mdss.yaml | 9 + Bindings/display/msm/qcom,sm8650-dpu.yaml | 4 +- Bindings/display/msm/qcom,sm8650-mdss.yaml | 4 + Bindings/display/msm/qcom,x1e80100-mdss.yaml | 251 ++ .../display/panel/boe,th101mb31ig002-28a.yaml | 58 + Bindings/display/panel/himax,hx83112a.yaml | 74 + .../display/panel/leadtek,ltk500hd1829.yaml | 4 +- Bindings/display/panel/novatek,nt35510.yaml | 5 +- Bindings/display/panel/novatek,nt36672e.yaml | 66 + Bindings/display/panel/panel-lvds.yaml | 4 + Bindings/display/panel/panel-simple.yaml | 4 + .../display/panel/rocktech,jh057n00900.yaml | 3 + Bindings/display/panel/visionox,r66451.yaml | 2 +- Bindings/display/panel/visionox,rm69299.yaml | 3 +- Bindings/display/renesas,rzg2l-du.yaml | 126 + .../display/rockchip/rockchip,dw-hdmi.yaml | 33 +- Bindings/display/solomon,ssd1307fb.yaml | 20 +- Bindings/display/solomon,ssd132x.yaml | 12 +- Bindings/display/solomon,ssd133x.yaml | 45 + Bindings/display/ti/ti,am65x-dss.yaml | 7 +- Bindings/dma/allwinner,sun50i-a64-dma.yaml | 12 +- Bindings/dma/fsl,edma.yaml | 2 + Bindings/dma/fsl,imx-sdma.yaml | 3 +- Bindings/dma/marvell,mmp-dma.yaml | 72 + Bindings/dma/mediatek,mt7622-hsdma.yaml | 63 + Bindings/dma/mmp-dma.txt | 81 - Bindings/dma/mtk-hsdma.txt | 33 - Bindings/dma/renesas,rcar-dmac.yaml | 1 + Bindings/dts-coding-style.rst | 2 + Bindings/eeprom/at24.yaml | 5 +- .../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 96 +- Bindings/fpga/fpga-region.txt | 479 ---- Bindings/fpga/fpga-region.yaml | 358 +++ Bindings/fpga/xlnx,versal-fpga.yaml | 2 +- Bindings/gpio/aspeed,ast2400-gpio.yaml | 148 ++ Bindings/gpio/gateworks,pld-gpio.txt | 3 +- Bindings/gpio/gpio-aspeed.txt | 39 - Bindings/gpio/gpio-mvebu.yaml | 2 +- Bindings/gpio/gpio-nmk.txt | 31 - Bindings/gpio/gpio-pca9570.yaml | 3 + Bindings/gpio/mrvl-gpio.yaml | 2 +- Bindings/gpio/renesas,rcar-gpio.yaml | 1 + Bindings/gpio/st,nomadik-gpio.yaml | 95 + ...mg,powervr.yaml => img,powervr-rogue.yaml} | 4 +- Bindings/gpu/img,powervr-sgx.yaml | 138 ++ Bindings/hwmon/adi,adm1177.yaml | 5 +- Bindings/hwmon/adi,adm1275.yaml | 7 +- Bindings/hwmon/adi,ltc2945.yaml | 5 +- Bindings/hwmon/adi,ltc4282.yaml | 159 ++ Bindings/hwmon/amphenol,chipcap2.yaml | 77 + Bindings/hwmon/aspeed,g6-pwm-tach.yaml | 71 + Bindings/hwmon/fan-common.yaml | 79 + Bindings/hwmon/hwmon-common.yaml | 19 + Bindings/hwmon/lltc,ltc4151.yaml | 5 +- Bindings/hwmon/lltc,ltc4286.yaml | 9 +- Bindings/hwmon/lm75.yaml | 3 +- Bindings/hwmon/nuvoton,nct6775.yaml | 1 + Bindings/hwmon/pmbus/infineon,tda38640.yaml | 28 + Bindings/hwmon/pmbus/ti,lm25066.yaml | 17 +- Bindings/hwmon/ti,ina2xx.yaml | 11 +- Bindings/hwmon/ti,tmp513.yaml | 5 +- Bindings/hwmon/ti,tps23861.yaml | 5 +- Bindings/i2c/atmel,at91sam-i2c.yaml | 4 +- Bindings/i2c/i2c-demux-pinctrl.yaml | 3 +- Bindings/i2c/i2c-exynos5.yaml | 1 + Bindings/i2c/i2c-imx-lpi2c.yaml | 1 + Bindings/i2c/i2c-mpc.yaml | 2 +- Bindings/i2c/i2c-mux-pca954x.yaml | 30 + Bindings/i2c/i2c-pxa.yaml | 2 +- Bindings/i2c/i2c.txt | 151 -- Bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml | 3 +- Bindings/i2c/qcom,i2c-cci.yaml | 2 +- Bindings/i2c/renesas,rcar-i2c.yaml | 1 + Bindings/i2c/st,nomadik-i2c.yaml | 49 +- Bindings/i3c/aspeed,ast2600-i3c.yaml | 2 +- Bindings/i3c/cdns,i3c-master.yaml | 2 +- Bindings/i3c/i3c.yaml | 6 +- Bindings/i3c/mipi-i3c-hci.yaml | 2 +- Bindings/i3c/silvaco,i3c-master.yaml | 2 +- Bindings/i3c/snps,dw-i3c-master.yaml | 2 +- Bindings/iio/adc/adc.yaml | 1 - Bindings/iio/adc/adi,ad9467.yaml | 4 + Bindings/iio/adc/adi,axi-adc.yaml | 8 +- Bindings/iio/adc/microchip,pac1934.yaml | 120 + Bindings/iio/adc/nxp,imx93-adc.yaml | 4 +- Bindings/iio/adc/qcom,spmi-vadc.yaml | 1 - Bindings/iio/adc/richtek,rtq6056.yaml | 9 +- Bindings/iio/adc/ti,ads1298.yaml | 80 + Bindings/iio/afe/voltage-divider.yaml | 11 + Bindings/iio/amplifiers/adi,hmc425a.yaml | 47 +- Bindings/iio/frequency/adi,admfm2000.yaml | 127 + Bindings/iio/gyroscope/bosch,bmg160.yaml | 8 +- Bindings/iio/health/maxim,max30102.yaml | 2 +- Bindings/iio/humidity/ti,hdc2010.yaml | 3 + Bindings/iio/humidity/ti,hdc3020.yaml | 3 + Bindings/iio/imu/st,lsm6dsx.yaml | 4 +- Bindings/iio/light/ams,as73211.yaml | 7 +- Bindings/iio/light/vishay,veml6075.yaml | 1 + .../iio/magnetometer/voltafield,af8133j.yaml | 60 + Bindings/iio/pressure/honeywell,hsc030pa.yaml | 3 + .../iio/pressure/honeywell,mprls0025pa.yaml | 98 +- Bindings/iio/temperature/ti,tmp117.yaml | 8 + .../input/allwinner,sun4i-a10-lradc-keys.yaml | 1 - Bindings/input/atmel,captouch.txt | 36 - Bindings/input/atmel,captouch.yaml | 59 + Bindings/input/da9062-onkey.txt | 47 - Bindings/input/dlg,da9062-onkey.yaml | 38 + Bindings/input/samsung,s3c6410-keypad.yaml | 121 + Bindings/input/samsung-keypad.txt | 77 - .../input/touchscreen/fsl,imx6ul-tsc.yaml | 97 + Bindings/input/touchscreen/goodix,gt9916.yaml | 95 + Bindings/input/touchscreen/goodix.yaml | 5 +- .../input/touchscreen/imagis,ist3038c.yaml | 21 +- Bindings/input/touchscreen/imx6ul_tsc.txt | 38 - Bindings/input/touchscreen/melfas,mms114.yaml | 6 +- .../input/touchscreen/silead,gsl1680.yaml | 2 +- Bindings/interconnect/qcom,rpm.yaml | 3 + Bindings/interconnect/qcom,rpmh.yaml | 2 +- Bindings/interconnect/qcom,sm7150-rpmh.yaml | 84 + .../amlogic,meson-gpio-intc.yaml | 1 + Bindings/interrupt-controller/atmel,aic.txt | 43 - Bindings/interrupt-controller/atmel,aic.yaml | 89 + Bindings/interrupt-controller/fsl,intmux.yaml | 3 + .../mediatek,mt6577-sysirq.yaml | 85 + .../interrupt-controller/mediatek,sysirq.txt | 44 - .../renesas,rzg2l-irqc.yaml | 44 +- .../starfive,jh8100-intc.yaml | 61 + Bindings/iommu/arm,smmu.yaml | 20 +- Bindings/leds/backlight/kinetic,ktd2801.yaml | 46 + Bindings/leds/backlight/qcom-wled.yaml | 4 +- Bindings/leds/common.yaml | 12 + Bindings/leds/leds-bcm63138.yaml | 4 - Bindings/leds/leds-bcm6328.yaml | 4 - Bindings/leds/leds-bcm6358.txt | 2 - Bindings/leds/leds-pwm-multicolor.yaml | 4 +- Bindings/leds/leds-pwm.yaml | 5 - Bindings/leds/leds-qcom-lpg.yaml | 102 +- Bindings/leds/onnn,ncp5623.yaml | 96 + Bindings/mailbox/fsl,mu.yaml | 58 +- Bindings/media/i2c/techwell,tw9900.yaml | 2 +- Bindings/media/mediatek,vcodec-encoder.yaml | 31 +- Bindings/media/mediatek-jpeg-encoder.yaml | 3 +- Bindings/media/rockchip-isp1.yaml | 37 +- Bindings/media/st,stm32mp25-video-codec.yaml | 49 + .../fsl/fsl,imx-weim-peripherals.yaml | 31 + .../memory-controllers/fsl/fsl,imx-weim.yaml | 204 ++ .../mc-peripheral-props.yaml | 1 + .../nvidia,tegra20-emc.yaml | 2 +- .../memory-controllers/renesas,rpc-if.yaml | 1 + .../memory-controllers/st,stm32-fmc2-ebi.yaml | 7 +- Bindings/mfd/atmel,hlcdc.yaml | 99 + Bindings/mfd/atmel,sama5d2-flexcom.yaml | 99 + Bindings/mfd/atmel-flexcom.txt | 64 - Bindings/mfd/atmel-hlcdc.txt | 56 - Bindings/mfd/da9062.txt | 124 - Bindings/mfd/dlg,da9063.yaml | 253 +- Bindings/mfd/google,cros-ec.yaml | 7 + Bindings/mfd/iqs62x.yaml | 2 +- Bindings/mfd/qcom,tcsr.yaml | 2 + Bindings/mfd/syscon.yaml | 3 + Bindings/mfd/ti,twl.yaml | 2 + Bindings/mips/cpus.yaml | 15 +- Bindings/mips/mobileye.yaml | 32 + Bindings/misc/qcom,fastrpc.yaml | 2 + Bindings/misc/xlnx,sd-fec.txt | 58 - Bindings/misc/xlnx,sd-fec.yaml | 140 ++ Bindings/mmc/fsl-imx-esdhc.yaml | 11 +- Bindings/mmc/fsl-imx-mmc.yaml | 12 + Bindings/mmc/hi3798cv200-dw-mshc.txt | 40 - .../mmc/hisilicon,hi3798cv200-dw-mshc.yaml | 97 + Bindings/mmc/renesas,sdhi.yaml | 1 + Bindings/mmc/snps,dwcmshc-sdhci.yaml | 2 + Bindings/mtd/atmel-nand.txt | 1 + Bindings/mtd/brcm,brcmnand.yaml | 44 +- Bindings/mtd/davinci-nand.txt | 2 +- Bindings/mtd/flctl-nand.txt | 2 +- Bindings/mtd/fsl-upm-nand.txt | 2 +- Bindings/mtd/gpio-control-nand.txt | 2 +- Bindings/mtd/gpmi-nand.yaml | 2 +- Bindings/mtd/hisi504-nand.txt | 2 +- Bindings/mtd/jedec,spi-nor.yaml | 3 + Bindings/mtd/mtd.yaml | 2 + Bindings/mtd/nvidia-tegra20-nand.txt | 2 +- Bindings/mtd/orion-nand.txt | 2 +- Bindings/mtd/partitions/linux,ubi.yaml | 75 + Bindings/mtd/partitions/ubi-volume.yaml | 40 + Bindings/mtd/samsung-s3c2410.txt | 2 +- Bindings/mtd/st,stm32-fmc2-nand.yaml | 25 +- Bindings/mux/mux-controller.yaml | 2 +- .../net/bluetooth/qualcomm-bluetooth.yaml | 8 +- Bindings/net/brcm,asp-v2.0.yaml | 4 + Bindings/net/brcm,unimac-mdio.yaml | 1 + Bindings/net/can/fsl,flexcan.yaml | 3 + Bindings/net/can/microchip,mpfs-can.yaml | 6 +- Bindings/net/can/tcan4x5x.txt | 3 + Bindings/net/can/xilinx,can.yaml | 5 + Bindings/net/cdns,macb.yaml | 5 + Bindings/net/dsa/ar9331.txt | 147 -- Bindings/net/dsa/microchip,ksz.yaml | 1 + Bindings/net/dsa/qca,ar9331.yaml | 161 ++ Bindings/net/dsa/realtek.yaml | 4 +- Bindings/net/ethernet-controller.yaml | 1 - Bindings/net/ethernet-phy-package.yaml | 52 + Bindings/net/fsl,fec.yaml | 3 + Bindings/net/mediatek,net.yaml | 22 +- Bindings/net/nfc/ti,trf7970a.yaml | 2 +- Bindings/net/qca,qca808x.yaml | 54 + Bindings/net/qcom,ethqos.yaml | 9 +- Bindings/net/qcom,ipa.yaml | 2 +- Bindings/net/qcom,ipq4019-mdio.yaml | 15 + Bindings/net/qcom,qca807x.yaml | 184 ++ Bindings/net/renesas,etheravb.yaml | 1 + Bindings/net/snps,dwmac.yaml | 17 +- Bindings/net/starfive,jh7110-dwmac.yaml | 72 +- Bindings/net/ti,cpsw-switch.yaml | 5 +- Bindings/net/ti,dp83822.yaml | 34 + Bindings/net/ti,k3-am654-cpsw-nuss.yaml | 5 +- Bindings/net/ti,k3-am654-cpts.yaml | 5 +- Bindings/net/wireless/mediatek,mt76.yaml | 33 +- Bindings/net/wireless/qcom,ath10k.yaml | 1 + Bindings/net/wireless/qcom,ath11k-pci.yaml | 1 + Bindings/net/wireless/qcom,ath11k.yaml | 1 + Bindings/nvmem/layouts/fixed-cell.yaml | 22 +- Bindings/nvmem/nvmem-provider.yaml | 18 + Bindings/nvmem/xlnx,zynqmp-nvmem.txt | 46 - Bindings/nvmem/xlnx,zynqmp-nvmem.yaml | 42 + Bindings/opp/opp-v2-base.yaml | 2 - Bindings/pci/fsl,imx6q-pcie-common.yaml | 17 +- Bindings/pci/fsl,imx6q-pcie-ep.yaml | 46 +- Bindings/pci/fsl,imx6q-pcie.yaml | 49 +- Bindings/pci/qcom,pcie-common.yaml | 100 + Bindings/pci/qcom,pcie-sa8775p.yaml | 166 ++ Bindings/pci/qcom,pcie-sc7280.yaml | 166 ++ Bindings/pci/qcom,pcie-sc8180x.yaml | 170 ++ Bindings/pci/qcom,pcie-sc8280xp.yaml | 180 ++ Bindings/pci/qcom,pcie-sm8150.yaml | 158 ++ Bindings/pci/qcom,pcie-sm8250.yaml | 173 ++ Bindings/pci/qcom,pcie-sm8350.yaml | 184 ++ Bindings/pci/qcom,pcie-sm8450.yaml | 178 ++ Bindings/pci/qcom,pcie-sm8550.yaml | 171 ++ Bindings/pci/qcom,pcie-x1e80100.yaml | 165 ++ Bindings/pci/qcom,pcie.yaml | 378 +-- Bindings/perf/arm,coresight-pmu.yaml | 39 + .../perf/starfive,jh8100-starlink-pmu.yaml | 46 + Bindings/phy/mediatek,mt8365-csi-rx.yaml | 79 + Bindings/phy/phy-cadence-torrent.yaml | 11 +- Bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml | 184 ++ Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 6 + Bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 48 +- .../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 22 - Bindings/phy/rockchip,rk3588-hdptx-phy.yaml | 91 + .../pinctrl/amlogic,meson-pinctrl-a1.yaml | 2 +- .../amlogic,meson-pinctrl-g12a-aobus.yaml | 2 +- .../amlogic,meson-pinctrl-g12a-periphs.yaml | 2 +- .../pinctrl/amlogic,meson8-pinctrl-aobus.yaml | 2 +- .../pinctrl/amlogic,meson8-pinctrl-cbus.yaml | 2 +- Bindings/pinctrl/atmel,at91-pinctrl.txt | 2 + Bindings/pinctrl/awinic,aw9523-pinctrl.yaml | 139 ++ Bindings/pinctrl/cirrus,madera.yaml | 3 +- Bindings/pinctrl/cypress,cy8c95x0.yaml | 24 +- Bindings/pinctrl/fsl,imx6ul-pinctrl.txt | 37 - Bindings/pinctrl/fsl,imx6ul-pinctrl.yaml | 116 + Bindings/pinctrl/mobileye,eyeq5-pinctrl.yaml | 242 ++ Bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml | 2 - Bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml | 3 +- .../pinctrl/nvidia,tegra234-pinmux-aon.yaml | 7 +- .../nvidia,tegra234-pinmux-common.yaml | 82 +- Bindings/pinctrl/nvidia,tegra234-pinmux.yaml | 7 +- Bindings/pinctrl/pincfg-node.yaml | 2 +- Bindings/pinctrl/qcom,sm4450-tlmm.yaml | 2 +- Bindings/pinctrl/renesas,pfc.yaml | 1 + Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 2 + ...nq-pinctrl.yaml => xlnx,pinctrl-zynq.yaml} | 6 +- Bindings/power/qcom,rpmpd.yaml | 2 + Bindings/power/renesas,rcar-sysc.yaml | 1 + Bindings/power/wakeup-source.txt | 2 +- Bindings/pwm/atmel,hlcdc-pwm.yaml | 35 + Bindings/pwm/atmel-hlcdc-pwm.txt | 29 - Bindings/pwm/marvell,pxa-pwm.yaml | 51 + Bindings/pwm/mediatek,mt2712-pwm.yaml | 1 + Bindings/pwm/mediatek,pwm-disp.yaml | 3 + Bindings/pwm/opencores,pwm.yaml | 56 + Bindings/pwm/pwm-amlogic.yaml | 115 +- Bindings/pwm/pxa-pwm.txt | 30 - Bindings/regulator/gpio-regulator.yaml | 4 +- Bindings/regulator/infineon,ir38060.yaml | 45 + Bindings/regulator/mcp16502-regulator.txt | 144 -- Bindings/regulator/microchip,mcp16502.yaml | 180 ++ .../regulator/qcom,usb-vbus-regulator.yaml | 11 +- Bindings/regulator/ti,tps65132.yaml | 84 + Bindings/regulator/tps65132-regulator.txt | 46 - Bindings/remoteproc/mtk,scp.yaml | 4 +- Bindings/remoteproc/qcom,glink-rpm-edge.yaml | 1 - Bindings/remoteproc/qcom,qcs404-pas.yaml | 2 +- Bindings/remoteproc/qcom,sc7180-pas.yaml | 2 +- Bindings/remoteproc/qcom,sc7280-wpss-pil.yaml | 2 +- Bindings/remoteproc/qcom,sc8180x-pas.yaml | 2 +- Bindings/remoteproc/qcom,sm6115-pas.yaml | 2 +- Bindings/remoteproc/qcom,sm6350-pas.yaml | 2 +- Bindings/remoteproc/qcom,sm6375-pas.yaml | 2 +- Bindings/remoteproc/qcom,sm8150-pas.yaml | 2 +- Bindings/remoteproc/qcom,sm8350-pas.yaml | 2 +- Bindings/remoteproc/qcom,sm8550-pas.yaml | 51 +- Bindings/remoteproc/qcom,wcnss-pil.yaml | 2 +- Bindings/remoteproc/ti,davinci-rproc.txt | 3 - Bindings/reset/mobileye,eyeq5-reset.yaml | 43 + Bindings/reset/renesas,rst.yaml | 1 + Bindings/reset/sophgo,sg2042-reset.yaml | 35 + Bindings/riscv/cpus.yaml | 10 +- Bindings/riscv/extensions.yaml | 7 + Bindings/rng/atmel,at91-trng.yaml | 4 + Bindings/rtc/abracon,abx80x.txt | 31 - Bindings/rtc/abracon,abx80x.yaml | 98 + Bindings/rtc/atmel,at91sam9260-rtt.yaml | 4 +- Bindings/rtc/mediatek,mt2712-rtc.yaml | 39 + Bindings/rtc/mediatek,mt7622-rtc.yaml | 52 + Bindings/rtc/rtc-mt2712.txt | 14 - Bindings/rtc/rtc-mt7622.txt | 21 - Bindings/rtc/sa1100-rtc.yaml | 2 +- Bindings/rtc/xlnx,zynqmp-rtc.yaml | 11 +- Bindings/serial/atmel,at91-usart.yaml | 2 +- Bindings/serial/cdns,uart.yaml | 1 + Bindings/serial/fsl-lpuart.yaml | 1 + Bindings/serial/renesas,hscif.yaml | 1 + Bindings/serial/samsung_uart.yaml | 2 + Bindings/serial/serial.yaml | 2 +- Bindings/serial/st,asc.yaml | 55 + Bindings/serial/st,stm32-uart.yaml | 3 + Bindings/serial/st-asc.txt | 18 - Bindings/soc/fsl/fsl,layerscape-dcfg.yaml | 2 +- Bindings/soc/fsl/fsl,layerscape-scfg.yaml | 2 +- Bindings/soc/imx/fsl,imx-anatop.yaml | 128 + Bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml | 18 +- .../soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml | 22 +- Bindings/soc/qcom/qcom,pbs.yaml | 46 + Bindings/soc/qcom/qcom,pmic-glink.yaml | 3 + Bindings/soc/qcom/qcom,rpm-master-stats.yaml | 2 + .../qcom/{qcom,spm.yaml => qcom,saw2.yaml} | 46 +- Bindings/soc/renesas/renesas-soc.yaml | 73 + Bindings/soc/renesas/renesas.yaml | 25 +- Bindings/soc/rockchip/grf.yaml | 23 + .../soc/samsung/samsung,exynos-sysreg.yaml | 2 + Bindings/soc/xilinx/xilinx.yaml | 70 +- Bindings/sound/atmel,asoc-wm8904.yaml | 84 + Bindings/sound/atmel,sam9x5-wm8731-audio.yaml | 76 + Bindings/sound/atmel,sama5d2-classd.yaml | 7 +- Bindings/sound/atmel-sam9x5-wm8731-audio.txt | 35 - Bindings/sound/atmel-wm8904.txt | 55 - Bindings/sound/audio-graph-port.yaml | 2 +- Bindings/sound/cirrus,cs35l45.yaml | 3 + Bindings/sound/cirrus,cs42l43.yaml | 11 +- Bindings/sound/cs4341.txt | 2 +- Bindings/sound/everest,es8326.yaml | 8 +- Bindings/sound/fsl,asrc.txt | 80 - Bindings/sound/fsl,easrc.yaml | 4 +- Bindings/sound/fsl,imx-asrc.yaml | 162 ++ Bindings/sound/fsl,micfil.yaml | 14 +- Bindings/sound/fsl,sai.yaml | 6 + Bindings/sound/infineon,peb2466.yaml | 2 +- Bindings/sound/microchip,sama7g5-i2smcc.yaml | 11 +- Bindings/sound/qcom,q6usb.yaml | 55 + Bindings/sound/qcom,sm8250.yaml | 2 +- Bindings/sound/qcom,wcd938x.yaml | 81 +- Bindings/sound/qcom,wcd939x-sdw.yaml | 69 + Bindings/sound/qcom,wcd939x.yaml | 96 + Bindings/sound/qcom,wcd93xx-common.yaml | 95 + Bindings/sound/qcom,wsa8840.yaml | 11 +- Bindings/sound/realtek,rt1015.yaml | 41 + Bindings/sound/rt1015.txt | 23 - Bindings/sound/rt5645.txt | 6 + Bindings/sound/samsung,tm2.yaml | 7 +- Bindings/spi/atmel,at91rm9200-spi.yaml | 1 - Bindings/spi/samsung,spi.yaml | 4 +- Bindings/spi/spi-controller.yaml | 27 + Bindings/spi/spi-fsl-lpspi.yaml | 1 + Bindings/spi/spi-nxp-fspi.yaml | 18 +- .../allwinner,sun4i-a10-system-control.yaml | 2 +- Bindings/submitting-patches.rst | 23 +- .../thermal/allwinner,sun8i-a83t-ths.yaml | 34 +- Bindings/thermal/da9062-thermal.txt | 36 - Bindings/thermal/dlg,da9062-thermal.yaml | 35 + Bindings/thermal/qoriq-thermal.yaml | 3 +- Bindings/thermal/rcar-gen3-thermal.yaml | 2 + Bindings/thermal/thermal-zones.yaml | 2 - Bindings/timer/arm,arch_timer_mmio.yaml | 2 +- Bindings/timer/cdns,ttc.yaml | 22 +- Bindings/timer/mediatek,mtk-timer.txt | 48 - Bindings/timer/mediatek,timer.yaml | 84 + Bindings/timer/mrvl,mmp-timer.yaml | 2 +- Bindings/timer/nxp,sysctr-timer.yaml | 4 +- Bindings/timer/ralink,cevt-systick.yaml | 38 + Bindings/timer/renesas,ostm.yaml | 2 +- Bindings/timer/renesas,tmu.yaml | 18 +- Bindings/timer/samsung,exynos4210-mct.yaml | 2 + Bindings/tpm/tcg,tpm_tis-spi.yaml | 1 + Bindings/trivial-devices.yaml | 87 +- Bindings/ufs/qcom,ufs.yaml | 38 +- Bindings/usb/analogix,anx7411.yaml | 13 - Bindings/usb/ci-hdrc-usb2.yaml | 2 +- Bindings/usb/cypress,hx3.yaml | 2 +- Bindings/usb/fcs,fsa4480.yaml | 12 +- Bindings/usb/generic-ehci.yaml | 1 + Bindings/usb/gpio-sbu-mux.yaml | 12 +- Bindings/usb/hisilicon,hi3798mv200-dwc3.yaml | 99 + Bindings/usb/ite,it5205.yaml | 72 + Bindings/usb/mediatek,mtu3.yaml | 5 +- Bindings/usb/microchip,usb5744.yaml | 2 - Bindings/usb/nxp,ptn36502.yaml | 12 +- Bindings/usb/nxp,ptn5110.yaml | 6 +- Bindings/usb/onnn,nb7vpq904m.yaml | 13 +- Bindings/usb/qcom,dwc3.yaml | 2 +- Bindings/usb/qcom,pmic-typec.yaml | 46 +- Bindings/usb/qcom,wcd939x-usbss.yaml | 12 +- Bindings/usb/realtek,rts5411.yaml | 55 + Bindings/usb/ti,am62-usb.yaml | 8 +- Bindings/usb/ti,usb8020b.yaml | 69 + Bindings/usb/usb-nop-xceiv.yaml | 11 +- Bindings/usb/usb-switch.yaml | 67 + Bindings/usb/usb.yaml | 2 + Bindings/vendor-prefixes.yaml | 45 + Bindings/w1/w1-uart.yaml | 59 + Bindings/watchdog/arm,sp805.yaml | 5 + Bindings/watchdog/atmel,sama5d4-wdt.yaml | 12 +- Bindings/watchdog/brcm,bcm2835-pm-wdog.txt | 18 - Bindings/watchdog/qcom-wdt.yaml | 2 +- Bindings/watchdog/renesas,wdt.yaml | 1 + Bindings/watchdog/sprd,sp9860-wdt.yaml | 64 + Bindings/watchdog/sprd-wdt.txt | 19 - Bindings/watchdog/starfive,jh7100-wdt.yaml | 40 +- Bindings/writing-schema.rst | 30 +- include/dt-bindings/arm/qcom,ids.h | 5 + include/dt-bindings/clock/ast2600-clock.h | 1 + include/dt-bindings/clock/exynos850.h | 56 + include/dt-bindings/clock/google,gs101.h | 129 + .../dt-bindings/clock/microchip,mpfs-clock.h | 5 + .../dt-bindings/clock/mobileye,eyeq5-clk.h | 22 + include/dt-bindings/clock/qcom,gcc-msm8953.h | 4 + include/dt-bindings/clock/qcom,gcc-sc8180x.h | 2 + include/dt-bindings/clock/qcom,gcc-sm8150.h | 3 + .../dt-bindings/clock/qcom,x1e80100-camcc.h | 135 ++ .../dt-bindings/clock/qcom,x1e80100-dispcc.h | 98 + .../dt-bindings/clock/qcom,x1e80100-gpucc.h | 41 + .../dt-bindings/clock/qcom,x1e80100-tcsr.h | 23 + include/dt-bindings/clock/r8a779g0-cpg-mssr.h | 1 + .../clock/renesas,r8a779h0-cpg-mssr.h | 96 + .../dt-bindings/clock/rockchip,rk3588-cru.h | 3 +- include/dt-bindings/input/linux-event-codes.h | 1 + .../dt-bindings/interconnect/qcom,msm8909.h | 93 + .../interconnect/qcom,sm7150-rpmh.h | 150 ++ .../interconnect/qcom,x1e80100-rpmh.h | 24 - include/dt-bindings/leds/common.h | 4 + include/dt-bindings/mfd/stm32f7-rcc.h | 1 + include/dt-bindings/power/amlogic,c3-pwrc.h | 2 +- include/dt-bindings/power/qcom-rpmpd.h | 7 + .../dt-bindings/power/renesas,r8a779h0-sysc.h | 49 + .../reset/mediatek,mt7988-resets.h | 6 + .../dt-bindings/reset/qcom,x1e80100-gpucc.h | 19 + .../dt-bindings/reset/sophgo,sg2042-reset.h | 87 + src/arc/axc003.dtsi | 4 +- src/arc/hsdk.dts | 1 - src/arc/vdk_axs10x_mb.dtsi | 2 +- src/arm/allwinner/sun8i-r40-feta40i.dtsi | 7 + src/arm/amlogic/meson.dtsi | 6 +- src/arm/amlogic/meson8.dtsi | 1 - src/arm/amlogic/meson8b.dtsi | 1 - src/arm/arm/arm-realview-pb1176.dts | 2 +- src/arm/arm/integratorap-im-pd1.dts | 3 +- src/arm/arm/versatile-ab.dts | 3 +- src/arm/arm/vexpress-v2p-ca9.dts | 4 +- src/arm/broadcom/bcm47622.dtsi | 14 + src/arm/broadcom/bcm63138.dtsi | 7 +- src/arm/broadcom/bcm63148.dtsi | 14 + src/arm/broadcom/bcm63178.dtsi | 14 + src/arm/broadcom/bcm6756.dtsi | 14 + src/arm/broadcom/bcm6846.dtsi | 14 + src/arm/broadcom/bcm6855.dtsi | 14 + src/arm/broadcom/bcm6878.dtsi | 14 + src/arm/broadcom/bcm947622.dts | 10 + src/arm/broadcom/bcm963138.dts | 10 + src/arm/broadcom/bcm963138dvt.dts | 14 +- src/arm/broadcom/bcm963148.dts | 10 + src/arm/broadcom/bcm963178.dts | 10 + src/arm/broadcom/bcm96756.dts | 10 + src/arm/broadcom/bcm96846.dts | 10 + src/arm/broadcom/bcm96855.dts | 10 + src/arm/broadcom/bcm96878.dts | 10 + src/arm/gemini/gemini-dlink-dir-685.dts | 30 +- src/arm/gemini/gemini-dlink-dns-313.dts | 4 +- src/arm/gemini/gemini-sl93512r.dts | 16 +- src/arm/gemini/gemini-sq201.dts | 16 +- src/arm/gemini/gemini-wbd111.dts | 6 +- src/arm/gemini/gemini-wbd222.dts | 6 +- .../marvell/armada-385-clearfog-gtr-l8.dts | 38 +- .../marvell/armada-385-clearfog-gtr-s4.dts | 2 + src/arm/marvell/armada-385-clearfog-gtr.dtsi | 130 +- src/arm/marvell/armada-388-clearfog.dts | 5 +- src/arm/marvell/dove-cubox.dts | 4 +- src/arm/marvell/mmp2-brownstone.dts | 2 +- src/arm/microchip/at91-sama7g54_curiosity.dts | 482 ++++ src/arm/microchip/at91-sama7g5ek.dts | 8 +- .../at91sam9g25-gardena-smart-gateway.dts | 2 + src/arm/microchip/at91sam9x5ek.dtsi | 2 + src/arm/microchip/sam9x60.dtsi | 64 +- src/arm/microchip/sama7g5.dtsi | 56 +- src/arm/nvidia/tegra124-nyan.dtsi | 1 + src/arm/nvidia/tegra124-venice2.dts | 1 + .../tegra30-asus-nexus7-grouper-common.dtsi | 3 + src/arm/nvidia/tegra30-lg-p880.dts | 489 ++++ src/arm/nvidia/tegra30-lg-p895.dts | 496 ++++ src/arm/nvidia/tegra30-lg-x3.dtsi | 1812 ++++++++++++++ src/arm/nxp/imx/imx1-apf9328.dts | 2 +- src/arm/nxp/imx/imx1.dtsi | 2 +- src/arm/nxp/imx/imx27.dtsi | 2 +- src/arm/nxp/imx/imx31.dtsi | 2 +- src/arm/nxp/imx/imx35.dtsi | 2 +- src/arm/nxp/imx/imx51.dtsi | 2 +- src/arm/nxp/imx/imx53-qsb-hdmi.dtso | 87 + src/arm/nxp/imx/imx6dl-sielaff.dts | 533 ++++ src/arm/nxp/imx/imx6dl-yapp4-common.dtsi | 25 +- src/arm/nxp/imx/imx6q-apalis-eval-v1.2.dts | 200 ++ src/arm/nxp/imx/imx6q-apalis-eval.dts | 108 +- src/arm/nxp/imx/imx6q-apalis-eval.dtsi | 120 + src/arm/nxp/imx/imx6qdl-hummingboard.dtsi | 7 +- src/arm/nxp/imx/imx6qdl-hummingboard2.dtsi | 5 + src/arm/nxp/imx/imx6qdl-skov-cpu.dtsi | 10 +- src/arm/nxp/imx/imx6qdl.dtsi | 2 +- src/arm/nxp/imx/imx6sl-tolino-shine2hd.dts | 6 +- src/arm/nxp/imx/imx6sl.dtsi | 2 +- src/arm/nxp/imx/imx6sx.dtsi | 2 +- src/arm/nxp/imx/imx6ul-14x14-evk.dtsi | 2 +- src/arm/nxp/imx/imx6ul-geam.dts | 2 +- .../nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi | 2 +- src/arm/nxp/imx/imx6ul.dtsi | 18 +- .../nxp/imx/imx6ull-dhcom-som-cfg-sdcard.dtsi | 4 +- src/arm/nxp/imx/imx6ull-dhcom-som.dtsi | 4 +- src/arm/nxp/imx/imx6ull-dhcor-som.dtsi | 7 +- src/arm/nxp/imx/imx6ull-tarragon-common.dtsi | 1 + src/arm/nxp/imx/imx6ull.dtsi | 2 +- src/arm/nxp/imx/imx7-mba7.dtsi | 315 +-- src/arm/nxp/imx/imx7-tqma7.dtsi | 144 +- src/arm/nxp/imx/imx7d-mba7.dts | 94 +- src/arm/nxp/imx/imx7s-warp.dts | 1 + src/arm/nxp/ls/ls1021a.dtsi | 2 + src/arm/nxp/mxs/imx28-evk.dts | 2 +- src/arm/qcom/qcom-apq8026-lg-lenok.dts | 38 + .../qcom-apq8026-samsung-matisse-wifi.dts | 452 +--- src/arm/qcom/qcom-apq8064.dtsi | 70 +- src/arm/qcom/qcom-apq8084.dtsi | 13 +- src/arm/qcom/qcom-ipq4019-ap.dk01.1.dtsi | 146 +- src/arm/qcom/qcom-ipq4019.dtsi | 35 +- src/arm/qcom/qcom-ipq8064.dtsi | 12 +- .../qcom-msm8226-samsung-matisse-common.dtsi | 457 ++++ src/arm/qcom/qcom-msm8226.dtsi | 764 +++--- src/arm/qcom/qcom-msm8660.dtsi | 17 +- src/arm/qcom/qcom-msm8926-htc-memul.dts | 15 +- .../qcom/qcom-msm8926-samsung-matisselte.dts | 37 + src/arm/qcom/qcom-msm8960-pins.dtsi | 21 + .../qcom/qcom-msm8960-samsung-expressatt.dts | 71 +- src/arm/qcom/qcom-msm8960.dtsi | 48 +- src/arm/qcom/qcom-msm8974.dtsi | 33 +- src/arm/qcom/qcom-sdx55.dtsi | 32 +- src/arm/qcom/qcom-sdx65.dtsi | 48 +- src/arm/renesas/r8a73a4-ape6evm.dts | 12 + src/arm/renesas/r8a73a4.dtsi | 23 +- src/arm/renesas/r8a7740.dtsi | 2 + src/arm/renesas/r8a7778.dtsi | 11 +- src/arm/renesas/r8a7779.dtsi | 9 +- src/arm/rockchip/rk3128-xpi-3128.dts | 29 + src/arm/rockchip/rk3128.dtsi | 60 + src/arm/rockchip/rk322x.dtsi | 16 +- src/arm/rockchip/rk3288.dtsi | 16 +- src/arm/rockchip/rv1126-sonoff-ihost.dtsi | 10 +- src/arm/samsung/exynos4412-i9300.dts | 2 +- src/arm/samsung/exynos4412-i9305.dts | 2 +- src/arm/samsung/exynos4412-n710x.dts | 2 +- src/arm/samsung/exynos4412-p4note.dtsi | 53 +- .../samsung/exynos5420-galaxy-tab-common.dtsi | 34 +- src/arm/samsung/exynos5420-peach-pit.dts | 1 + .../samsung/exynos5422-odroidxu3-common.dtsi | 16 +- src/arm/samsung/exynos5800-peach-pi.dts | 1 + src/arm/st/stih407-pinctrl.dtsi | 8 +- src/arm/st/stm32f769-disco-mb1166-reva09.dts | 13 + src/arm/st/stm32f769-disco.dts | 70 +- src/arm/st/stm32f769.dtsi | 20 + src/arm/st/stm32mp131.dtsi | 7 + src/arm/st/stm32mp135f-dk.dts | 8 + src/arm/st/stm32mp157.dtsi | 2 +- src/arm/st/stm32mp157a-dk1-scmi.dts | 2 +- src/arm/st/stm32mp157c-dk2-scmi.dts | 2 +- src/arm/st/stm32mp157c-ed1-scmi.dts | 2 +- src/arm/st/stm32mp157c-ev1-scmi.dts | 2 +- src/arm/st/stm32mp157c-lxa-tac-gen2.dts | 2 +- src/arm/st/stm32mp15xc-lxa-tac.dtsi | 6 +- src/arm/ti/davinci/da850.dtsi | 4 +- src/arm/ti/keystone/keystone-clocks.dtsi | 2 +- src/arm/ti/keystone/keystone-k2e-clocks.dtsi | 2 +- src/arm/ti/keystone/keystone-k2e-evm.dts | 2 +- src/arm/ti/keystone/keystone-k2e-netcp.dtsi | 2 +- src/arm/ti/keystone/keystone-k2e.dtsi | 2 +- src/arm/ti/keystone/keystone-k2g-evm.dts | 2 +- src/arm/ti/keystone/keystone-k2g-ice.dts | 2 +- src/arm/ti/keystone/keystone-k2g-netcp.dtsi | 2 +- src/arm/ti/keystone/keystone-k2g.dtsi | 2 +- src/arm/ti/keystone/keystone-k2hk-clocks.dtsi | 2 +- src/arm/ti/keystone/keystone-k2hk-evm.dts | 2 +- src/arm/ti/keystone/keystone-k2hk-netcp.dtsi | 2 +- src/arm/ti/keystone/keystone-k2hk.dtsi | 2 +- src/arm/ti/keystone/keystone-k2l-clocks.dtsi | 2 +- src/arm/ti/keystone/keystone-k2l-evm.dts | 2 +- src/arm/ti/keystone/keystone-k2l-netcp.dtsi | 2 +- src/arm/ti/keystone/keystone-k2l.dtsi | 2 +- src/arm/ti/keystone/keystone.dtsi | 2 +- src/arm/ti/omap/am335x-baltos-ir2110.dts | 2 +- src/arm/ti/omap/am335x-baltos-ir3220.dts | 2 +- src/arm/ti/omap/am335x-baltos-ir5221.dts | 2 +- src/arm/ti/omap/am335x-baltos-leds.dtsi | 2 +- src/arm/ti/omap/am335x-baltos.dtsi | 2 +- src/arm/ti/omap/am335x-base0033.dts | 2 +- src/arm/ti/omap/am335x-bone-common.dtsi | 4 +- src/arm/ti/omap/am335x-cm-t335.dts | 2 +- src/arm/ti/omap/am335x-evmsk.dts | 2 +- src/arm/ti/omap/am335x-guardian.dts | 4 +- src/arm/ti/omap/am335x-icev2.dts | 2 +- src/arm/ti/omap/am335x-igep0033.dtsi | 2 +- src/arm/ti/omap/am335x-myirtech-myc.dtsi | 2 +- src/arm/ti/omap/am335x-myirtech-myd.dts | 2 +- src/arm/ti/omap/am335x-nano.dts | 2 +- src/arm/ti/omap/am335x-netcan-plus-1xx.dts | 2 +- src/arm/ti/omap/am335x-netcom-plus-2xx.dts | 2 +- src/arm/ti/omap/am335x-netcom-plus-8xx.dts | 2 +- src/arm/ti/omap/am335x-pdu001.dts | 2 +- .../am335x-sancloud-bbe-extended-wifi.dts | 2 +- src/arm/ti/omap/am335x-sancloud-bbe-lite.dts | 2 +- src/arm/ti/omap/am335x-sbc-t335.dts | 2 +- src/arm/ti/omap/am335x-sl50.dts | 3 +- src/arm/ti/omap/am33xx-clocks.dtsi | 39 +- src/arm/ti/omap/am33xx.dtsi | 9 +- src/arm/ti/omap/am3517.dtsi | 11 +- src/arm/ti/omap/am35xx-clocks.dtsi | 18 +- src/arm/ti/omap/am4372.dtsi | 6 + src/arm/ti/omap/am437x-cm-t43.dts | 2 +- src/arm/ti/omap/am437x-sbc-t43.dts | 2 +- src/arm/ti/omap/am5729-beagleboneai.dts | 2 +- src/arm/ti/omap/am57xx-cl-som-am57x.dts | 2 +- src/arm/ti/omap/am57xx-sbc-am57x.dts | 2 +- src/arm/ti/omap/compulab-sb-som.dtsi | 2 +- src/arm/ti/omap/dra7-l4.dtsi | 2 +- src/arm/ti/omap/dra7.dtsi | 17 +- src/arm/ti/omap/dra74x-p.dtsi | 2 +- src/arm/ti/omap/dra7xx-clocks.dtsi | 2 +- src/arm/ti/omap/omap3430es1-clocks.dtsi | 52 +- src/arm/ti/omap/omap34xx-omap36xx-clocks.dtsi | 86 +- src/arm/ti/omap/omap34xx.dtsi | 11 +- ...map36xx-am35xx-omap3430es2plus-clocks.dtsi | 28 +- src/arm/ti/omap/omap36xx-clocks.dtsi | 7 +- .../omap/omap36xx-omap3430es2plus-clocks.dtsi | 46 +- src/arm/ti/omap/omap36xx.dtsi | 9 +- src/arm/ti/omap/omap3xxx-clocks.dtsi | 510 ++-- src/arm/ti/omap/omap4-epson-embt2ws.dts | 1 + src/arm/ti/omap/omap4-panda-common.dtsi | 1 + src/arm/ti/omap/omap4-sdp.dts | 2 +- src/arm/ti/omap/omap4.dtsi | 9 +- src/arm/ti/omap/omap5-igep0050.dts | 2 +- src/arm/ti/omap/omap5.dtsi | 9 +- src/arm/ti/omap/twl4030.dtsi | 2 +- src/arm/ti/omap/twl6030.dtsi | 4 +- src/arm64/allwinner/sun50i-h6-beelink-gs1.dts | 2 + src/arm64/allwinner/sun50i-h6-tanix.dtsi | 2 + src/arm64/allwinner/sun50i-h6.dtsi | 7 +- .../sun50i-h616-bigtreetech-cb1-manta.dts | 2 +- .../sun50i-h616-bigtreetech-cb1.dtsi | 4 +- .../allwinner/sun50i-h616-bigtreetech-pi.dts | 2 +- src/arm64/allwinner/sun50i-h616.dtsi | 155 ++ .../sun50i-h618-longan-module-3h.dtsi | 75 + .../allwinner/sun50i-h618-longanpi-3h.dts | 144 ++ .../sun50i-h618-transpeed-8k618-t.dts | 23 + .../allwinner/sun50i-h64-remix-mini-pc.dts | 356 +++ src/arm64/amlogic/amlogic-c3.dtsi | 7 + src/arm64/amlogic/amlogic-t7.dtsi | 12 +- src/arm64/amlogic/meson-a1-ad402.dts | 2 +- src/arm64/amlogic/meson-a1.dtsi | 2 + .../meson-axg-jethome-jethub-j1xx.dtsi | 30 +- src/arm64/amlogic/meson-axg-s400.dts | 16 +- src/arm64/amlogic/meson-axg.dtsi | 8 + src/arm64/amlogic/meson-g12-common.dtsi | 3 + src/arm64/amlogic/meson-g12a-fbx8am-brcm.dtso | 31 + .../amlogic/meson-g12a-fbx8am-realtek.dtso | 21 + src/arm64/amlogic/meson-g12a-fbx8am.dts | 462 ++++ src/arm64/amlogic/meson-g12a-radxa-zero.dts | 12 +- src/arm64/amlogic/meson-g12a-sei510.dts | 14 +- src/arm64/amlogic/meson-g12a-u200.dts | 16 +- src/arm64/amlogic/meson-g12a-x96-max.dts | 14 +- src/arm64/amlogic/meson-g12b-odroid-n2.dtsi | 2 +- src/arm64/amlogic/meson-g12b-odroid.dtsi | 20 +- src/arm64/amlogic/meson-g12b-w400.dtsi | 10 +- src/arm64/amlogic/meson-gx-libretech-pc.dtsi | 12 +- src/arm64/amlogic/meson-gx-p23x-q20x.dtsi | 8 +- src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts | 6 +- src/arm64/amlogic/meson-gxbb-odroidc2.dts | 8 +- src/arm64/amlogic/meson-gxbb-p200.dts | 4 +- src/arm64/amlogic/meson-gxbb-p20x.dtsi | 6 +- src/arm64/amlogic/meson-gxbb-vega-s95.dtsi | 8 +- src/arm64/amlogic/meson-gxbb-wetek.dtsi | 8 +- .../amlogic/meson-gxl-s805x-libretech-ac.dts | 8 +- src/arm64/amlogic/meson-gxl-s805x-p241.dts | 8 +- .../meson-gxl-s905w-jethome-jethub-j80.dts | 8 +- .../meson-gxl-s905x-hwacom-amazetv.dts | 6 +- .../meson-gxl-s905x-libretech-cc-v2.dts | 12 +- .../amlogic/meson-gxl-s905x-libretech-cc.dts | 6 +- .../amlogic/meson-gxl-s905x-nexbox-a95x.dts | 6 +- src/arm64/amlogic/meson-gxl-s905x-p212.dtsi | 8 +- src/arm64/amlogic/meson-gxm-khadas-vim2.dts | 8 +- .../amlogic/meson-gxm-s912-libretech-pc.dts | 2 +- src/arm64/amlogic/meson-khadas-vim3.dtsi | 16 +- .../amlogic/meson-libretech-cottonwood.dtsi | 6 +- src/arm64/amlogic/meson-sm1-ac2xx.dtsi | 10 +- src/arm64/amlogic/meson-sm1-bananapi.dtsi | 14 +- src/arm64/amlogic/meson-sm1-odroid-hc4.dts | 4 +- src/arm64/amlogic/meson-sm1-odroid.dtsi | 20 +- src/arm64/amlogic/meson-sm1-sei610.dts | 12 +- .../bcmbca/bcm4906-netgear-r8000p.dts | 5 + .../bcmbca/bcm4906-tplink-archer-c2300-v1.dts | 5 + .../bcmbca/bcm4908-asus-gt-ac5300.dts | 19 +- src/arm64/broadcom/bcmbca/bcm4908.dtsi | 7 +- src/arm64/broadcom/bcmbca/bcm4912.dtsi | 14 + src/arm64/broadcom/bcmbca/bcm63146.dtsi | 14 + src/arm64/broadcom/bcmbca/bcm63158.dtsi | 14 + src/arm64/broadcom/bcmbca/bcm6813.dtsi | 14 + src/arm64/broadcom/bcmbca/bcm6856.dtsi | 14 + src/arm64/broadcom/bcmbca/bcm6858.dtsi | 14 + src/arm64/broadcom/bcmbca/bcm94908.dts | 10 + src/arm64/broadcom/bcmbca/bcm94912.dts | 10 + src/arm64/broadcom/bcmbca/bcm963146.dts | 10 + src/arm64/broadcom/bcmbca/bcm963158.dts | 10 + src/arm64/broadcom/bcmbca/bcm96813.dts | 10 + src/arm64/broadcom/bcmbca/bcm96856.dts | 10 + src/arm64/broadcom/bcmbca/bcm96858.dts | 10 + src/arm64/exynos/exynos850.dtsi | 64 + src/arm64/exynos/google/gs101-oriole.dts | 24 + src/arm64/exynos/google/gs101-pinctrl.dtsi | 2 +- src/arm64/exynos/google/gs101.dtsi | 131 +- src/arm64/freescale/fsl-ls1012a.dtsi | 10 +- src/arm64/freescale/fsl-ls1046a.dtsi | 1 - src/arm64/freescale/fsl-ls1088a.dtsi | 6 + src/arm64/freescale/fsl-lx2160a.dtsi | 32 +- .../freescale/imx8-apalis-eval-v1.1.dtsi | 26 + .../freescale/imx8-apalis-eval-v1.2.dtsi | 124 + src/arm64/freescale/imx8-apalis-eval.dtsi | 22 - src/arm64/freescale/imx8-apalis-v1.1.dtsi | 1 - src/arm64/freescale/imx8-ss-audio.dtsi | 330 +++ src/arm64/freescale/imx8-ss-conn.dtsi | 16 +- src/arm64/freescale/imx8-ss-dma.dtsi | 103 +- src/arm64/freescale/imx8-ss-gpu0.dtsi | 27 + src/arm64/freescale/imx8-ss-lsio.dtsi | 16 +- src/arm64/freescale/imx8dxl-evk.dts | 101 + src/arm64/freescale/imx8dxl-ss-adma.dtsi | 77 + src/arm64/freescale/imx8dxl.dtsi | 1 + .../freescale/imx8dxp-tqma8xdp-mba8xx.dts | 16 + src/arm64/freescale/imx8dxp-tqma8xdp.dtsi | 24 + src/arm64/freescale/imx8dxp.dtsi | 24 + src/arm64/freescale/imx8mm-evk.dtsi | 69 + .../freescale/imx8mm-kontron-bl-osm-s.dts | 294 +-- src/arm64/freescale/imx8mm-kontron-bl.dts | 38 +- src/arm64/freescale/imx8mm-kontron-osm-s.dtsi | 567 ++++- src/arm64/freescale/imx8mm-kontron-sl.dtsi | 4 +- .../freescale/imx8mm-tqma8mqml-mba8mx.dts | 14 +- src/arm64/freescale/imx8mm-venice-gw71xx.dtsi | 40 +- src/arm64/freescale/imx8mm-venice-gw7901.dts | 14 +- src/arm64/freescale/imx8mn-beacon-kit.dts | 2 - src/arm64/freescale/imx8mn-evk.dtsi | 36 + src/arm64/freescale/imx8mn-rve-gateway.dts | 2 +- .../imx8mn-tqma8mqnl-mba8mx-usbotg.dtso | 64 + .../freescale/imx8mn-tqma8mqnl-mba8mx.dts | 5 +- src/arm64/freescale/imx8mn.dtsi | 2 +- src/arm64/freescale/imx8mp-beacon-som.dtsi | 71 + .../freescale/imx8mp-data-modul-edm-sbc.dts | 82 +- src/arm64/freescale/imx8mp-evk.dts | 33 +- .../freescale/imx8mp-phyboard-pollux-rdk.dts | 107 +- src/arm64/freescale/imx8mp-phycore-som.dtsi | 1 - src/arm64/freescale/imx8mp-venice-gw71xx.dtsi | 10 +- src/arm64/freescale/imx8mp-venice-gw72xx.dtsi | 2 +- src/arm64/freescale/imx8mp-venice-gw73xx.dtsi | 2 +- src/arm64/freescale/imx8mp-verdin.dtsi | 3 +- src/arm64/freescale/imx8mp.dtsi | 12 +- src/arm64/freescale/imx8mq-tqma8mq-mba8mx.dts | 24 +- .../freescale/imx8qm-apalis-eval-v1.2.dts | 16 + src/arm64/freescale/imx8qm-apalis-eval.dts | 2 +- .../imx8qm-apalis-v1.1-eval-v1.2.dts | 26 + .../freescale/imx8qm-apalis-v1.1-eval.dts | 2 +- src/arm64/freescale/imx8qm-mek.dts | 26 + src/arm64/freescale/imx8qm-ss-conn.dtsi | 5 + src/arm64/freescale/imx8qm-ss-dma.dtsi | 63 +- src/arm64/freescale/imx8qm.dtsi | 41 + .../freescale/imx8qxp-tqma8xqp-mba8xx.dts | 16 + src/arm64/freescale/imx8qxp-tqma8xqp.dtsi | 14 + src/arm64/freescale/imx8qxp.dtsi | 8 + src/arm64/freescale/imx8ulp-evk.dts | 2 +- src/arm64/freescale/imx93-phyboard-segin.dts | 117 + src/arm64/freescale/imx93-phycore-som.dtsi | 126 + src/arm64/freescale/imx93-tqma9352.dtsi | 4 +- .../freescale/imx93-var-som-symphony.dts | 351 +++ src/arm64/freescale/imx93-var-som.dtsi | 110 + src/arm64/freescale/imx93.dtsi | 4 +- src/arm64/freescale/mba8mx.dtsi | 21 +- src/arm64/freescale/mba8xx.dtsi | 554 +++++ src/arm64/freescale/tqma8xx.dtsi | 265 ++ src/arm64/intel/socfpga_agilex5.dtsi | 4 +- src/arm64/marvell/ac5-98dx25xx.dtsi | 31 +- src/arm64/marvell/ac5-98dx35xx-rd.dts | 4 + src/arm64/marvell/armada-37xx.dtsi | 10 +- src/arm64/marvell/armada-ap807.dtsi | 3 + src/arm64/marvell/armada-cp11x.dtsi | 10 +- src/arm64/mediatek/mt2712-evb.dts | 12 +- src/arm64/mediatek/mt2712e.dtsi | 5 +- src/arm64/mediatek/mt6797.dtsi | 8 +- .../mediatek/mt7622-bananapi-bpi-r64.dts | 13 + src/arm64/mediatek/mt7622-rfb1.dts | 25 + src/arm64/mediatek/mt7622.dtsi | 34 +- src/arm64/mediatek/mt7981b-xiaomi-ax3000t.dts | 15 + src/arm64/mediatek/mt7981b.dtsi | 105 + .../mediatek/mt7986a-acelink-ew-7886cax.dts | 173 ++ .../mt7986a-bananapi-bpi-r3-nand.dtso | 2 +- .../mediatek/mt7986a-bananapi-bpi-r3.dts | 8 +- src/arm64/mediatek/mt7986a-rfb.dts | 31 +- src/arm64/mediatek/mt7986a.dtsi | 218 +- src/arm64/mediatek/mt7986b-rfb.dts | 31 +- .../mediatek/mt7988a-bananapi-bpi-r4.dts | 11 + src/arm64/mediatek/mt7988a.dtsi | 136 ++ src/arm64/mediatek/mt8173-elm-hana-rev7.dts | 2 +- src/arm64/mediatek/mt8173-elm.dtsi | 3 +- src/arm64/mediatek/mt8173-evb.dts | 2 +- src/arm64/mediatek/mt8173.dtsi | 19 +- .../mediatek/mt8183-kukui-jacuzzi-pico6.dts | 3 +- src/arm64/mediatek/mt8183-kukui-kakadu.dtsi | 4 + src/arm64/mediatek/mt8183-kukui-kodama.dtsi | 4 + src/arm64/mediatek/mt8183-kukui-krane.dtsi | 4 + src/arm64/mediatek/mt8183-kukui.dtsi | 6 +- src/arm64/mediatek/mt8183-pumpkin.dts | 2 +- src/arm64/mediatek/mt8183.dtsi | 12 +- src/arm64/mediatek/mt8186-corsola-krabby.dtsi | 129 + .../mt8186-corsola-magneton-sku393216.dts | 39 + .../mt8186-corsola-magneton-sku393217.dts | 39 + .../mt8186-corsola-magneton-sku393218.dts | 26 + .../mt8186-corsola-rusty-sku196608.dts | 26 + .../mt8186-corsola-steelix-sku131072.dts | 18 + .../mt8186-corsola-steelix-sku131073.dts | 18 + .../mediatek/mt8186-corsola-steelix.dtsi | 199 ++ .../mt8186-corsola-tentacool-sku327681.dts | 57 + .../mt8186-corsola-tentacool-sku327683.dts | 24 + .../mt8186-corsola-tentacruel-sku262144.dts | 44 + .../mt8186-corsola-tentacruel-sku262148.dts | 26 + src/arm64/mediatek/mt8186-corsola.dtsi | 1681 +++++++++++++ src/arm64/mediatek/mt8186.dtsi | 93 +- src/arm64/mediatek/mt8192-asurada.dtsi | 11 +- src/arm64/mediatek/mt8192.dtsi | 11 +- .../mediatek/mt8195-cherry-tomato-r1.dts | 4 + .../mediatek/mt8195-cherry-tomato-r2.dts | 4 + .../mediatek/mt8195-cherry-tomato-r3.dts | 4 + src/arm64/mediatek/mt8195-cherry.dtsi | 63 +- src/arm64/mediatek/mt8195-demo.dts | 18 +- src/arm64/mediatek/mt8195-evb.dts | 12 + src/arm64/mediatek/mt8195.dtsi | 133 +- src/arm64/mediatek/mt8395-genio-1200-evk.dts | 17 +- src/arm64/mediatek/mt8395-radxa-nio-12l.dts | 825 +++++++ src/arm64/nvidia/tegra132-norrin.dts | 1 + src/arm64/nvidia/tegra194-p2888.dtsi | 50 + src/arm64/nvidia/tegra194-p2972-0000.dts | 51 +- src/arm64/nvidia/tegra194-p3668.dtsi | 27 + src/arm64/nvidia/tegra234-p3701.dtsi | 1953 +-------------- .../nvidia/tegra234-p3737-0000+p3701-0000.dts | 1 - src/arm64/nvidia/tegra234-p3767-0000.dtsi | 14 - src/arm64/nvidia/tegra234-p3767-0005.dtsi | 14 - src/arm64/nvidia/tegra234-p3767.dtsi | 86 + .../nvidia/tegra234-p3768-0000+p3767-0000.dts | 7 +- .../nvidia/tegra234-p3768-0000+p3767-0005.dts | 12 +- src/arm64/nvidia/tegra234-sim-vdk.dts | 1 - src/arm64/nvidia/tegra234.dtsi | 2138 ++++++++++++++++- .../qcom/apq8016-sbc-d3-camera-mezzanine.dts | 8 +- src/arm64/qcom/ipq5332.dtsi | 8 +- src/arm64/qcom/ipq6018.dtsi | 159 ++ src/arm64/qcom/ipq8074.dtsi | 16 + src/arm64/qcom/ipq9574.dtsi | 12 +- src/arm64/qcom/msm8216-samsung-fortuna3g.dts | 11 + .../qcom/msm8916-samsung-fortuna-common.dtsi | 203 ++ .../qcom/msm8916-samsung-gprimeltecan.dts | 27 + .../qcom/msm8916-samsung-grandprimelte.dts | 16 + .../qcom/msm8916-samsung-rossa-common.dtsi | 16 + src/arm64/qcom/msm8916-samsung-rossa.dts | 16 + src/arm64/qcom/msm8916.dtsi | 9 + src/arm64/qcom/msm8939.dtsi | 11 +- src/arm64/qcom/msm8953.dtsi | 155 +- .../qcom/msm8994-msft-lumia-octagon.dtsi | 2 +- .../qcom/msm8994-sony-xperia-kitakami.dtsi | 2 +- src/arm64/qcom/msm8994.dtsi | 4 +- src/arm64/qcom/msm8996.dtsi | 18 +- src/arm64/qcom/msm8998.dtsi | 26 +- src/arm64/qcom/{pm2250.dtsi => pm4125.dtsi} | 38 +- src/arm64/qcom/pm6150.dtsi | 46 + src/arm64/qcom/pmi632.dtsi | 39 + src/arm64/qcom/qcm2290.dtsi | 7 + src/arm64/qcom/qcm6490-fairphone-fp5.dts | 56 +- src/arm64/qcom/qcm6490-idp.dts | 39 +- src/arm64/qcom/qcs404.dtsi | 16 + src/arm64/qcom/qcs6490-rb3gen2.dts | 23 +- src/arm64/qcom/qrb2210-rb1.dts | 96 +- src/arm64/qcom/qrb4210-rb2.dts | 50 +- src/arm64/qcom/sa8155p-adp.dts | 30 +- src/arm64/qcom/sa8295p-adp.dts | 68 + src/arm64/qcom/sa8540p-ride.dts | 4 +- src/arm64/qcom/sa8540p.dtsi | 3 + src/arm64/qcom/sa8775p.dtsi | 121 +- src/arm64/qcom/sc7180-trogdor.dtsi | 3 + src/arm64/qcom/sc7180.dtsi | 86 +- src/arm64/qcom/sc7280-chrome-common.dtsi | 28 + src/arm64/qcom/sc7280-herobrine.dtsi | 1 + src/arm64/qcom/sc7280-idp-ec-h1.dtsi | 1 + src/arm64/qcom/sc7280.dtsi | 129 +- src/arm64/qcom/sc8180x.dtsi | 143 +- .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 39 +- src/arm64/qcom/sc8280xp-pmics.dtsi | 39 +- src/arm64/qcom/sc8280xp.dtsi | 612 ++++- src/arm64/qcom/sda660-inforce-ifc6560.dts | 5 + src/arm64/qcom/sdm450-motorola-ali.dts | 2 +- src/arm64/qcom/sdm450.dtsi | 14 + src/arm64/qcom/sdm630-sony-xperia-nile.dtsi | 16 + src/arm64/qcom/sdm630.dtsi | 62 +- src/arm64/qcom/sdm632.dtsi | 8 + src/arm64/qcom/sdm660-xiaomi-lavender.dts | 6 + src/arm64/qcom/sdm670.dtsi | 14 +- src/arm64/qcom/sdm845-cheza.dtsi | 1 + src/arm64/qcom/sdm845-db845c.dts | 2 +- src/arm64/qcom/sdm845-oneplus-common.dtsi | 8 +- src/arm64/qcom/sdm845-shift-axolotl.dts | 2 +- src/arm64/qcom/sdm845.dtsi | 63 +- src/arm64/qcom/sm4450.dtsi | 2 +- src/arm64/qcom/sm6115.dtsi | 95 +- src/arm64/qcom/sm6125.dtsi | 17 +- src/arm64/qcom/sm6350.dtsi | 601 ++++- src/arm64/qcom/sm6375.dtsi | 14 +- src/arm64/qcom/sm7125-xiaomi-common.dtsi | 26 + src/arm64/qcom/sm7125-xiaomi-curtana.dts | 16 + src/arm64/qcom/sm7225-fairphone-fp4.dts | 61 +- src/arm64/qcom/sm8150.dtsi | 115 +- .../qcom/sm8250-xiaomi-elish-common.dtsi | 3 +- src/arm64/qcom/sm8250.dtsi | 113 +- src/arm64/qcom/sm8350.dtsi | 87 +- src/arm64/qcom/sm8450-hdk.dts | 6 +- src/arm64/qcom/sm8450.dtsi | 97 +- src/arm64/qcom/sm8550-hdk.dts | 1306 ++++++++++ src/arm64/qcom/sm8550-mtp.dts | 11 +- src/arm64/qcom/sm8550-qrd.dts | 53 +- src/arm64/qcom/sm8550.dtsi | 187 +- src/arm64/qcom/sm8650-mtp.dts | 155 ++ src/arm64/qcom/sm8650-qrd.dts | 439 +++- src/arm64/qcom/sm8650.dtsi | 81 +- src/arm64/qcom/x1e80100-crd.dts | 450 ++++ src/arm64/qcom/x1e80100-qcp.dts | 175 +- src/arm64/qcom/x1e80100.dtsi | 1781 +++++++++++++- src/arm64/renesas/r8a774a1.dtsi | 11 +- src/arm64/renesas/r8a774b1.dtsi | 11 +- src/arm64/renesas/r8a774c0.dtsi | 11 +- src/arm64/renesas/r8a774e1.dtsi | 11 +- src/arm64/renesas/r8a77951.dtsi | 11 +- src/arm64/renesas/r8a77960.dtsi | 11 +- src/arm64/renesas/r8a77961.dtsi | 11 +- src/arm64/renesas/r8a77965.dtsi | 11 +- src/arm64/renesas/r8a77970.dtsi | 11 +- src/arm64/renesas/r8a77980.dtsi | 17 +- src/arm64/renesas/r8a77990.dtsi | 11 +- src/arm64/renesas/r8a77995.dtsi | 11 +- src/arm64/renesas/r8a779a0.dtsi | 21 +- src/arm64/renesas/r8a779f0.dtsi | 17 +- src/arm64/renesas/r8a779g0-white-hawk-cpu.dts | 13 + .../renesas/r8a779g0-white-hawk-cpu.dtsi | 368 +-- src/arm64/renesas/r8a779g0-white-hawk.dts | 58 +- src/arm64/renesas/r8a779g0.dtsi | 105 +- .../renesas/r8a779g2-white-hawk-single.dts | 26 + src/arm64/renesas/r8a779g2.dtsi | 12 + .../renesas/r8a779h0-gray-hawk-single.dts | 230 ++ src/arm64/renesas/r8a779h0.dtsi | 664 +++++ src/arm64/renesas/r9a07g043u.dtsi | 81 +- .../r9a07g043u11-smarc-cru-csi-ov5645.dtso | 21 + src/arm64/renesas/r9a07g044.dtsi | 68 +- src/arm64/renesas/r9a07g054.dtsi | 69 +- src/arm64/renesas/r9a08g045.dtsi | 27 +- src/arm64/renesas/rzg2l-smarc.dtsi | 14 +- src/arm64/renesas/rzg2lc-smarc.dtsi | 14 +- src/arm64/renesas/rzg3s-smarc-som.dtsi | 9 + src/arm64/renesas/rzg3s-smarc.dtsi | 53 + src/arm64/renesas/ulcb-kf.dtsi | 81 +- src/arm64/renesas/white-hawk-common.dtsi | 65 + src/arm64/renesas/white-hawk-cpu-common.dtsi | 375 +++ ...k-csi-dsi.dtsi => white-hawk-csi-dsi.dtsi} | 2 +- ...ethernet.dtsi => white-hawk-ethernet.dtsi} | 2 +- src/arm64/rockchip/px30-ringneck-haikou.dts | 1 + src/arm64/rockchip/px30-ringneck.dtsi | 6 + src/arm64/rockchip/rk3328-rock-pi-e.dts | 4 +- src/arm64/rockchip/rk3328.dtsi | 11 +- src/arm64/rockchip/rk3399-gru-scarlet.dtsi | 3 +- src/arm64/rockchip/rk3399-kobol-helios64.dts | 5 +- src/arm64/rockchip/rk3399-orangepi.dts | 2 +- src/arm64/rockchip/rk3399-pinebook-pro.dts | 1 - src/arm64/rockchip/rk3399-puma-haikou.dts | 5 +- src/arm64/rockchip/rk3399-puma.dtsi | 53 +- src/arm64/rockchip/rk3399-rock-pi-4a.dts | 2 +- src/arm64/rockchip/rk3399-rock-pi-4b.dts | 2 +- src/arm64/rockchip/rk3399-rock-pi-4c.dts | 2 +- src/arm64/rockchip/rk3399.dtsi | 82 +- .../rockchip/rk3566-anbernic-rg-arc-d.dts | 60 + .../rockchip/rk3566-anbernic-rg-arc-s.dts | 19 + .../rockchip/rk3566-anbernic-rg-arc.dtsi | 237 ++ .../rockchip/rk3566-anbernic-rg353x.dtsi | 74 + src/arm64/rockchip/rk3566-anbernic-rg503.dts | 74 + src/arm64/rockchip/rk3566-anbernic-rgxx3.dtsi | 74 - src/arm64/rockchip/rk3566-lubancat-1.dts | 1 - src/arm64/rockchip/rk3566-pinetab2-v0.1.dts | 28 + src/arm64/rockchip/rk3566-pinetab2-v2.0.dts | 48 + src/arm64/rockchip/rk3566-pinetab2.dtsi | 943 ++++++++ .../rockchip/rk3566-powkiddy-rgb10max3.dts | 87 + src/arm64/rockchip/rk3566-powkiddy-rgb30.dts | 18 + src/arm64/rockchip/rk3566-powkiddy-rk2023.dts | 18 + .../rockchip/rk3566-powkiddy-rk2023.dtsi | 18 +- src/arm64/rockchip/rk3568-bpi-r2-pro.dts | 8 +- src/arm64/rockchip/rk3568-lubancat-2.dts | 1 - src/arm64/rockchip/rk3568-qnap-ts433.dts | 86 + src/arm64/rockchip/rk356x.dtsi | 3 +- src/arm64/rockchip/rk3588-coolpi-cm5.dtsi | 4 +- .../rockchip/rk3588-edgeble-neu6a-common.dtsi | 466 ++++ .../rockchip/rk3588-edgeble-neu6a-io.dts | 10 +- .../rockchip/rk3588-edgeble-neu6a-io.dtsi | 232 ++ .../rockchip/rk3588-edgeble-neu6a-wifi.dtso | 56 + src/arm64/rockchip/rk3588-edgeble-neu6a.dtsi | 25 +- .../rockchip/rk3588-edgeble-neu6b-io.dts | 76 +- src/arm64/rockchip/rk3588-edgeble-neu6b.dtsi | 383 +-- src/arm64/rockchip/rk3588-nanopc-t6.dts | 31 +- src/arm64/rockchip/rk3588-orangepi-5-plus.dts | 4 +- src/arm64/rockchip/rk3588-quartzpro64.dts | 2 +- src/arm64/rockchip/rk3588-rock-5b.dts | 8 +- src/arm64/rockchip/rk3588-tiger-haikou.dts | 266 ++ src/arm64/rockchip/rk3588-tiger.dtsi | 690 ++++++ src/arm64/rockchip/rk3588-toybrick-x0.dts | 688 ++++++ .../rockchip/rk3588s-indiedroid-nova.dts | 8 + src/arm64/rockchip/rk3588s-nanopi-r6c.dts | 14 + src/arm64/rockchip/rk3588s-nanopi-r6s.dts | 764 ++++++ src/arm64/rockchip/rk3588s-rock-5a.dts | 1 - src/arm64/rockchip/rk3588s.dtsi | 24 +- src/arm64/st/stm32mp251.dtsi | 12 + src/arm64/st/stm32mp255.dtsi | 17 + src/arm64/tesla/fsd.dtsi | 2 + src/arm64/ti/k3-am62-lp-sk.dts | 4 +- src/arm64/ti/k3-am62-main.dtsi | 30 +- src/arm64/ti/k3-am62-mcu.dtsi | 4 +- src/arm64/ti/k3-am62-phycore-som.dtsi | 5 +- src/arm64/ti/k3-am62-thermal.dtsi | 5 +- src/arm64/ti/k3-am62-verdin-dahlia.dtsi | 1 - src/arm64/ti/k3-am62-verdin-dev.dtsi | 1 - src/arm64/ti/k3-am62-verdin-mallow.dtsi | 10 + src/arm64/ti/k3-am62-verdin-wifi.dtsi | 1 - src/arm64/ti/k3-am62-verdin.dtsi | 59 +- src/arm64/ti/k3-am62-wakeup.dtsi | 38 +- src/arm64/ti/k3-am62.dtsi | 4 +- .../ti/k3-am625-beagleplay-csi2-ov5640.dtso | 4 +- .../k3-am625-beagleplay-csi2-tevi-ov5640.dtso | 4 +- src/arm64/ti/k3-am625-beagleplay.dts | 54 +- src/arm64/ti/k3-am625-phyboard-lyra-rdk.dts | 6 +- src/arm64/ti/k3-am625-sk.dts | 4 +- src/arm64/ti/k3-am625.dtsi | 4 +- src/arm64/ti/k3-am62a-main.dtsi | 80 +- src/arm64/ti/k3-am62a-mcu.dtsi | 4 +- src/arm64/ti/k3-am62a-thermal.dtsi | 5 +- src/arm64/ti/k3-am62a-wakeup.dtsi | 4 +- src/arm64/ti/k3-am62a.dtsi | 4 +- src/arm64/ti/k3-am62a7-sk.dts | 123 +- src/arm64/ti/k3-am62a7.dtsi | 4 +- src/arm64/ti/k3-am62p-main.dtsi | 154 +- src/arm64/ti/k3-am62p-mcu.dtsi | 6 +- src/arm64/ti/k3-am62p-thermal.dtsi | 5 +- src/arm64/ti/k3-am62p-wakeup.dtsi | 5 +- src/arm64/ti/k3-am62p.dtsi | 6 +- src/arm64/ti/k3-am62p5-sk.dts | 11 +- src/arm64/ti/k3-am62p5.dtsi | 4 +- .../ti/k3-am62x-phyboard-lyra-gpio-fan.dtso | 50 + src/arm64/ti/k3-am62x-sk-common.dtsi | 8 +- src/arm64/ti/k3-am62x-sk-csi2-imx219.dtso | 4 +- src/arm64/ti/k3-am62x-sk-csi2-ov5640.dtso | 4 +- .../ti/k3-am62x-sk-csi2-tevi-ov5640.dtso | 4 +- src/arm64/ti/k3-am62x-sk-hdmi-audio.dtso | 4 +- src/arm64/ti/k3-am64-main.dtsi | 69 +- src/arm64/ti/k3-am64-mcu.dtsi | 4 +- src/arm64/ti/k3-am64-phycore-som.dtsi | 13 +- src/arm64/ti/k3-am64-thermal.dtsi | 5 +- src/arm64/ti/k3-am64.dtsi | 4 +- .../ti/k3-am642-evm-icssg1-dualemac.dtso | 79 + src/arm64/ti/k3-am642-evm.dts | 119 +- .../ti/k3-am642-hummingboard-t-pcie.dtso | 45 + .../ti/k3-am642-hummingboard-t-usb3.dtso | 44 + src/arm64/ti/k3-am642-hummingboard-t.dts | 292 +++ .../ti/k3-am642-phyboard-electra-rdk.dts | 30 +- src/arm64/ti/k3-am642-sk.dts | 14 +- src/arm64/ti/k3-am642-sr-som.dtsi | 594 +++++ src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts | 1 - src/arm64/ti/k3-am642.dtsi | 4 +- .../ti/k3-am65-iot2050-arduino-connector.dtsi | 768 ++++++ src/arm64/ti/k3-am65-iot2050-common-pg1.dtsi | 7 +- src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi | 27 +- src/arm64/ti/k3-am65-iot2050-common.dtsi | 887 +------ src/arm64/ti/k3-am65-iot2050-dp.dtsi | 98 + src/arm64/ti/k3-am65-iot2050-usb3.dtsi | 27 + src/arm64/ti/k3-am65-main.dtsi | 44 +- src/arm64/ti/k3-am65-mcu.dtsi | 4 +- src/arm64/ti/k3-am65-wakeup.dtsi | 4 +- src/arm64/ti/k3-am65.dtsi | 4 +- src/arm64/ti/k3-am652.dtsi | 4 +- .../ti/k3-am6528-iot2050-basic-common.dtsi | 8 +- src/arm64/ti/k3-am6528-iot2050-basic-pg2.dts | 4 +- src/arm64/ti/k3-am6528-iot2050-basic.dts | 7 +- ...am654-base-board-rocktech-rk101-panel.dtso | 4 +- src/arm64/ti/k3-am654-base-board.dts | 8 +- src/arm64/ti/k3-am654-icssg2.dtso | 4 +- src/arm64/ti/k3-am654-idk.dtso | 4 +- src/arm64/ti/k3-am654-industrial-thermal.dtsi | 5 +- src/arm64/ti/k3-am654-pcie-usb2.dtso | 59 + src/arm64/ti/k3-am654-pcie-usb3.dtso | 61 + src/arm64/ti/k3-am654.dtsi | 4 +- .../ti/k3-am6548-iot2050-advanced-common.dtsi | 2 +- .../ti/k3-am6548-iot2050-advanced-m2.dts | 22 +- .../ti/k3-am6548-iot2050-advanced-pg2.dts | 12 +- .../ti/k3-am6548-iot2050-advanced-sm.dts | 189 ++ src/arm64/ti/k3-am6548-iot2050-advanced.dts | 3 +- src/arm64/ti/k3-am68-sk-base-board.dts | 54 +- src/arm64/ti/k3-am68-sk-som.dtsi | 20 +- src/arm64/ti/k3-am69-sk.dts | 253 +- src/arm64/ti/k3-j7200-common-proc-board.dts | 109 +- .../ti/k3-j7200-evm-quad-port-eth-exp.dtso | 4 +- src/arm64/ti/k3-j7200-main.dtsi | 315 ++- src/arm64/ti/k3-j7200-mcu-wakeup.dtsi | 57 +- src/arm64/ti/k3-j7200-som-p0.dtsi | 47 +- src/arm64/ti/k3-j7200-thermal.dtsi | 5 +- src/arm64/ti/k3-j7200.dtsi | 4 +- src/arm64/ti/k3-j721e-beagleboneai64.dts | 26 +- src/arm64/ti/k3-j721e-common-proc-board.dts | 4 +- src/arm64/ti/k3-j721e-evm-gesi-exp-board.dtso | 4 +- src/arm64/ti/k3-j721e-evm-pcie0-ep.dtso | 4 +- .../ti/k3-j721e-evm-quad-port-eth-exp.dtso | 4 +- src/arm64/ti/k3-j721e-main.dtsi | 149 +- src/arm64/ti/k3-j721e-mcu-wakeup.dtsi | 8 +- .../ti/k3-j721e-sk-csi2-dual-imx219.dtso | 165 ++ src/arm64/ti/k3-j721e-sk.dts | 45 +- src/arm64/ti/k3-j721e-som-p0.dtsi | 22 +- src/arm64/ti/k3-j721e-thermal.dtsi | 5 +- src/arm64/ti/k3-j721e.dtsi | 4 +- src/arm64/ti/k3-j721s2-common-proc-board.dts | 31 +- .../ti/k3-j721s2-evm-gesi-exp-board.dtso | 4 +- src/arm64/ti/k3-j721s2-evm-pcie1-ep.dtso | 4 +- src/arm64/ti/k3-j721s2-main.dtsi | 143 +- src/arm64/ti/k3-j721s2-mcu-wakeup.dtsi | 6 +- src/arm64/ti/k3-j721s2-som-p0.dtsi | 20 +- src/arm64/ti/k3-j721s2-thermal.dtsi | 5 +- src/arm64/ti/k3-j721s2.dtsi | 4 +- src/arm64/ti/k3-j722s-evm.dts | 383 +++ src/arm64/ti/k3-j722s.dtsi | 89 + src/arm64/ti/k3-j784s4-evm.dts | 32 +- src/arm64/ti/k3-j784s4-main.dtsi | 215 +- src/arm64/ti/k3-j784s4-mcu-wakeup.dtsi | 6 +- src/arm64/ti/k3-j784s4-thermal.dtsi | 5 +- src/arm64/ti/k3-j784s4.dtsi | 6 +- src/arm64/ti/k3-pinctrl.h | 7 +- src/arm64/ti/k3-serdes.h | 4 +- src/arm64/xilinx/zynqmp-clk-ccf.dtsi | 16 +- src/arm64/xilinx/zynqmp-sck-kv-g-revA.dtso | 36 +- src/arm64/xilinx/zynqmp-sck-kv-g-revB.dtso | 37 +- src/arm64/xilinx/zynqmp-zc1751-xm015-dc1.dts | 2 +- src/arm64/xilinx/zynqmp-zc1751-xm016-dc2.dts | 2 +- src/arm64/xilinx/zynqmp-zc1751-xm019-dc5.dts | 4 +- src/arm64/xilinx/zynqmp-zcu100-revC.dts | 2 +- src/arm64/xilinx/zynqmp-zcu102-revA.dts | 6 +- src/arm64/xilinx/zynqmp-zcu104-revA.dts | 2 +- src/arm64/xilinx/zynqmp-zcu104-revC.dts | 2 +- src/arm64/xilinx/zynqmp-zcu106-revA.dts | 6 +- src/arm64/xilinx/zynqmp-zcu111-revA.dts | 4 +- src/arm64/xilinx/zynqmp-zcu1275-revA.dts | 2 +- src/arm64/xilinx/zynqmp.dtsi | 85 +- src/loongarch/loongson-2k1000.dtsi | 7 + src/loongarch/loongson-2k2000-ref.dts | 33 + src/loongarch/loongson-2k2000.dtsi | 24 +- src/mips/mobileye/eyeq5-epm5.dts | 23 + src/mips/mobileye/eyeq5-fixed-clocks.dtsi | 292 +++ src/mips/mobileye/eyeq5.dtsi | 124 + src/mips/ralink/mt7621.dtsi | 51 +- src/powerpc/akebono.dts | 6 +- src/riscv/microchip/mpfs.dtsi | 6 +- src/riscv/renesas/r9a07g043f.dtsi | 8 +- src/riscv/sophgo/sg2042.dtsi | 9 + .../starfive/jh7100-beaglev-starlight.dts | 11 + src/riscv/starfive/jh7100-common.dtsi | 108 + .../jh7100-starfive-visionfive-v1.dts | 22 +- src/riscv/starfive/jh7100.dtsi | 49 + .../jh7110-starfive-visionfive-2.dtsi | 71 + src/riscv/starfive/jh7110.dtsi | 76 + 1276 files changed, 55369 insertions(+), 12556 deletions(-) delete mode 100644 Bindings/arm/marvell/armada-38x.txt create mode 100644 Bindings/arm/marvell/armada-38x.yaml delete mode 100644 Bindings/arm/mediatek/mediatek,hifsys.txt delete mode 100644 Bindings/arm/mediatek/mediatek,pciesys.txt delete mode 100644 Bindings/arm/mediatek/mediatek,ssusbsys.txt delete mode 100644 Bindings/arm/msm/qcom,saw2.txt delete mode 100644 Bindings/ata/ahci-mtk.txt delete mode 100644 Bindings/ata/atmel-at91_cf.txt create mode 100644 Bindings/ata/mediatek,mtk-ahci.yaml create mode 100644 Bindings/auxdisplay/gpio-7-segment.yaml create mode 100644 Bindings/auxdisplay/maxim,max6959.yaml delete mode 100644 Bindings/bus/imx-weim.txt create mode 100644 Bindings/clock/mediatek,mt2701-hifsys.yaml create mode 100644 Bindings/clock/mediatek,mt7622-pciesys.yaml create mode 100644 Bindings/clock/mediatek,mt7622-ssusbsys.yaml create mode 100644 Bindings/clock/mobileye,eyeq5-clk.yaml delete mode 100644 Bindings/clock/qcom,sc7180-mss.yaml delete mode 100644 Bindings/clock/qcom,sm8650-dispcc.yaml create mode 100644 Bindings/display/atmel/atmel,hlcdc-display-controller.yaml delete mode 100644 Bindings/display/atmel/hlcdc-dc.txt create mode 100644 Bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml create mode 100644 Bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml create mode 100644 Bindings/display/msm/qcom,x1e80100-mdss.yaml create mode 100644 Bindings/display/panel/boe,th101mb31ig002-28a.yaml create mode 100644 Bindings/display/panel/himax,hx83112a.yaml create mode 100644 Bindings/display/panel/novatek,nt36672e.yaml create mode 100644 Bindings/display/renesas,rzg2l-du.yaml create mode 100644 Bindings/display/solomon,ssd133x.yaml create mode 100644 Bindings/dma/marvell,mmp-dma.yaml create mode 100644 Bindings/dma/mediatek,mt7622-hsdma.yaml delete mode 100644 Bindings/dma/mmp-dma.txt delete mode 100644 Bindings/dma/mtk-hsdma.txt delete mode 100644 Bindings/fpga/fpga-region.txt create mode 100644 Bindings/fpga/fpga-region.yaml create mode 100644 Bindings/gpio/aspeed,ast2400-gpio.yaml delete mode 100644 Bindings/gpio/gpio-aspeed.txt delete mode 100644 Bindings/gpio/gpio-nmk.txt create mode 100644 Bindings/gpio/st,nomadik-gpio.yaml rename Bindings/gpu/{img,powervr.yaml => img,powervr-rogue.yaml} (91%) create mode 100644 Bindings/gpu/img,powervr-sgx.yaml create mode 100644 Bindings/hwmon/adi,ltc4282.yaml create mode 100644 Bindings/hwmon/amphenol,chipcap2.yaml create mode 100644 Bindings/hwmon/aspeed,g6-pwm-tach.yaml create mode 100644 Bindings/hwmon/fan-common.yaml create mode 100644 Bindings/hwmon/hwmon-common.yaml delete mode 100644 Bindings/i2c/i2c.txt create mode 100644 Bindings/iio/adc/microchip,pac1934.yaml create mode 100644 Bindings/iio/adc/ti,ads1298.yaml create mode 100644 Bindings/iio/frequency/adi,admfm2000.yaml create mode 100644 Bindings/iio/magnetometer/voltafield,af8133j.yaml delete mode 100644 Bindings/input/atmel,captouch.txt create mode 100644 Bindings/input/atmel,captouch.yaml delete mode 100644 Bindings/input/da9062-onkey.txt create mode 100644 Bindings/input/dlg,da9062-onkey.yaml create mode 100644 Bindings/input/samsung,s3c6410-keypad.yaml delete mode 100644 Bindings/input/samsung-keypad.txt create mode 100644 Bindings/input/touchscreen/fsl,imx6ul-tsc.yaml create mode 100644 Bindings/input/touchscreen/goodix,gt9916.yaml delete mode 100644 Bindings/input/touchscreen/imx6ul_tsc.txt create mode 100644 Bindings/interconnect/qcom,sm7150-rpmh.yaml delete mode 100644 Bindings/interrupt-controller/atmel,aic.txt create mode 100644 Bindings/interrupt-controller/atmel,aic.yaml create mode 100644 Bindings/interrupt-controller/mediatek,mt6577-sysirq.yaml delete mode 100644 Bindings/interrupt-controller/mediatek,sysirq.txt create mode 100644 Bindings/interrupt-controller/starfive,jh8100-intc.yaml create mode 100644 Bindings/leds/backlight/kinetic,ktd2801.yaml create mode 100644 Bindings/leds/onnn,ncp5623.yaml create mode 100644 Bindings/media/st,stm32mp25-video-codec.yaml create mode 100644 Bindings/memory-controllers/fsl/fsl,imx-weim-peripherals.yaml create mode 100644 Bindings/memory-controllers/fsl/fsl,imx-weim.yaml create mode 100644 Bindings/mfd/atmel,hlcdc.yaml create mode 100644 Bindings/mfd/atmel,sama5d2-flexcom.yaml delete mode 100644 Bindings/mfd/atmel-flexcom.txt delete mode 100644 Bindings/mfd/atmel-hlcdc.txt delete mode 100644 Bindings/mfd/da9062.txt create mode 100644 Bindings/mips/mobileye.yaml delete mode 100644 Bindings/misc/xlnx,sd-fec.txt create mode 100644 Bindings/misc/xlnx,sd-fec.yaml delete mode 100644 Bindings/mmc/hi3798cv200-dw-mshc.txt create mode 100644 Bindings/mmc/hisilicon,hi3798cv200-dw-mshc.yaml create mode 100644 Bindings/mtd/partitions/linux,ubi.yaml create mode 100644 Bindings/mtd/partitions/ubi-volume.yaml delete mode 100644 Bindings/net/dsa/ar9331.txt create mode 100644 Bindings/net/dsa/qca,ar9331.yaml create mode 100644 Bindings/net/ethernet-phy-package.yaml create mode 100644 Bindings/net/qca,qca808x.yaml create mode 100644 Bindings/net/qcom,qca807x.yaml create mode 100644 Bindings/nvmem/nvmem-provider.yaml delete mode 100644 Bindings/nvmem/xlnx,zynqmp-nvmem.txt create mode 100644 Bindings/nvmem/xlnx,zynqmp-nvmem.yaml create mode 100644 Bindings/pci/qcom,pcie-common.yaml create mode 100644 Bindings/pci/qcom,pcie-sa8775p.yaml create mode 100644 Bindings/pci/qcom,pcie-sc7280.yaml create mode 100644 Bindings/pci/qcom,pcie-sc8180x.yaml create mode 100644 Bindings/pci/qcom,pcie-sc8280xp.yaml create mode 100644 Bindings/pci/qcom,pcie-sm8150.yaml create mode 100644 Bindings/pci/qcom,pcie-sm8250.yaml create mode 100644 Bindings/pci/qcom,pcie-sm8350.yaml create mode 100644 Bindings/pci/qcom,pcie-sm8450.yaml create mode 100644 Bindings/pci/qcom,pcie-sm8550.yaml create mode 100644 Bindings/pci/qcom,pcie-x1e80100.yaml create mode 100644 Bindings/perf/arm,coresight-pmu.yaml create mode 100644 Bindings/perf/starfive,jh8100-starlink-pmu.yaml create mode 100644 Bindings/phy/mediatek,mt8365-csi-rx.yaml create mode 100644 Bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml create mode 100644 Bindings/phy/rockchip,rk3588-hdptx-phy.yaml create mode 100644 Bindings/pinctrl/awinic,aw9523-pinctrl.yaml delete mode 100644 Bindings/pinctrl/fsl,imx6ul-pinctrl.txt create mode 100644 Bindings/pinctrl/fsl,imx6ul-pinctrl.yaml create mode 100644 Bindings/pinctrl/mobileye,eyeq5-pinctrl.yaml rename Bindings/pinctrl/{xlnx,zynq-pinctrl.yaml => xlnx,pinctrl-zynq.yaml} (98%) create mode 100644 Bindings/pwm/atmel,hlcdc-pwm.yaml delete mode 100644 Bindings/pwm/atmel-hlcdc-pwm.txt create mode 100644 Bindings/pwm/marvell,pxa-pwm.yaml create mode 100644 Bindings/pwm/opencores,pwm.yaml delete mode 100644 Bindings/pwm/pxa-pwm.txt create mode 100644 Bindings/regulator/infineon,ir38060.yaml delete mode 100644 Bindings/regulator/mcp16502-regulator.txt create mode 100644 Bindings/regulator/microchip,mcp16502.yaml create mode 100644 Bindings/regulator/ti,tps65132.yaml delete mode 100644 Bindings/regulator/tps65132-regulator.txt create mode 100644 Bindings/reset/mobileye,eyeq5-reset.yaml create mode 100644 Bindings/reset/sophgo,sg2042-reset.yaml delete mode 100644 Bindings/rtc/abracon,abx80x.txt create mode 100644 Bindings/rtc/abracon,abx80x.yaml create mode 100644 Bindings/rtc/mediatek,mt2712-rtc.yaml create mode 100644 Bindings/rtc/mediatek,mt7622-rtc.yaml delete mode 100644 Bindings/rtc/rtc-mt2712.txt delete mode 100644 Bindings/rtc/rtc-mt7622.txt create mode 100644 Bindings/serial/st,asc.yaml delete mode 100644 Bindings/serial/st-asc.txt create mode 100644 Bindings/soc/imx/fsl,imx-anatop.yaml create mode 100644 Bindings/soc/qcom/qcom,pbs.yaml rename Bindings/soc/qcom/{qcom,spm.yaml => qcom,saw2.yaml} (53%) create mode 100644 Bindings/soc/renesas/renesas-soc.yaml create mode 100644 Bindings/sound/atmel,asoc-wm8904.yaml create mode 100644 Bindings/sound/atmel,sam9x5-wm8731-audio.yaml delete mode 100644 Bindings/sound/atmel-sam9x5-wm8731-audio.txt delete mode 100644 Bindings/sound/atmel-wm8904.txt delete mode 100644 Bindings/sound/fsl,asrc.txt create mode 100644 Bindings/sound/fsl,imx-asrc.yaml create mode 100644 Bindings/sound/qcom,q6usb.yaml create mode 100644 Bindings/sound/qcom,wcd939x-sdw.yaml create mode 100644 Bindings/sound/qcom,wcd939x.yaml create mode 100644 Bindings/sound/qcom,wcd93xx-common.yaml create mode 100644 Bindings/sound/realtek,rt1015.yaml delete mode 100644 Bindings/sound/rt1015.txt delete mode 100644 Bindings/thermal/da9062-thermal.txt create mode 100644 Bindings/thermal/dlg,da9062-thermal.yaml delete mode 100644 Bindings/timer/mediatek,mtk-timer.txt create mode 100644 Bindings/timer/mediatek,timer.yaml create mode 100644 Bindings/timer/ralink,cevt-systick.yaml create mode 100644 Bindings/usb/hisilicon,hi3798mv200-dwc3.yaml create mode 100644 Bindings/usb/ite,it5205.yaml create mode 100644 Bindings/usb/ti,usb8020b.yaml create mode 100644 Bindings/usb/usb-switch.yaml create mode 100644 Bindings/w1/w1-uart.yaml delete mode 100644 Bindings/watchdog/brcm,bcm2835-pm-wdog.txt create mode 100644 Bindings/watchdog/sprd,sp9860-wdt.yaml delete mode 100644 Bindings/watchdog/sprd-wdt.txt create mode 100644 include/dt-bindings/clock/mobileye,eyeq5-clk.h create mode 100644 include/dt-bindings/clock/qcom,x1e80100-camcc.h create mode 100644 include/dt-bindings/clock/qcom,x1e80100-dispcc.h create mode 100644 include/dt-bindings/clock/qcom,x1e80100-gpucc.h create mode 100644 include/dt-bindings/clock/qcom,x1e80100-tcsr.h create mode 100644 include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h create mode 100644 include/dt-bindings/interconnect/qcom,msm8909.h create mode 100644 include/dt-bindings/interconnect/qcom,sm7150-rpmh.h create mode 100644 include/dt-bindings/power/renesas,r8a779h0-sysc.h create mode 100644 include/dt-bindings/reset/qcom,x1e80100-gpucc.h create mode 100644 include/dt-bindings/reset/sophgo,sg2042-reset.h create mode 100644 src/arm/microchip/at91-sama7g54_curiosity.dts create mode 100644 src/arm/nvidia/tegra30-lg-p880.dts create mode 100644 src/arm/nvidia/tegra30-lg-p895.dts create mode 100644 src/arm/nvidia/tegra30-lg-x3.dtsi create mode 100644 src/arm/nxp/imx/imx53-qsb-hdmi.dtso create mode 100644 src/arm/nxp/imx/imx6dl-sielaff.dts create mode 100644 src/arm/nxp/imx/imx6q-apalis-eval-v1.2.dts create mode 100644 src/arm/nxp/imx/imx6q-apalis-eval.dtsi create mode 100644 src/arm/qcom/qcom-msm8226-samsung-matisse-common.dtsi create mode 100644 src/arm/qcom/qcom-msm8926-samsung-matisselte.dts create mode 100644 src/arm/qcom/qcom-msm8960-pins.dtsi create mode 100644 src/arm/st/stm32f769-disco-mb1166-reva09.dts create mode 100644 src/arm/st/stm32f769.dtsi create mode 100644 src/arm64/allwinner/sun50i-h618-longan-module-3h.dtsi create mode 100644 src/arm64/allwinner/sun50i-h618-longanpi-3h.dts create mode 100644 src/arm64/allwinner/sun50i-h64-remix-mini-pc.dts create mode 100644 src/arm64/amlogic/meson-g12a-fbx8am-brcm.dtso create mode 100644 src/arm64/amlogic/meson-g12a-fbx8am-realtek.dtso create mode 100644 src/arm64/amlogic/meson-g12a-fbx8am.dts create mode 100644 src/arm64/freescale/imx8-apalis-eval-v1.1.dtsi create mode 100644 src/arm64/freescale/imx8-apalis-eval-v1.2.dtsi create mode 100644 src/arm64/freescale/imx8-ss-gpu0.dtsi create mode 100644 src/arm64/freescale/imx8dxp-tqma8xdp-mba8xx.dts create mode 100644 src/arm64/freescale/imx8dxp-tqma8xdp.dtsi create mode 100644 src/arm64/freescale/imx8dxp.dtsi create mode 100644 src/arm64/freescale/imx8mn-tqma8mqnl-mba8mx-usbotg.dtso create mode 100644 src/arm64/freescale/imx8qm-apalis-eval-v1.2.dts create mode 100644 src/arm64/freescale/imx8qm-apalis-v1.1-eval-v1.2.dts create mode 100644 src/arm64/freescale/imx8qxp-tqma8xqp-mba8xx.dts create mode 100644 src/arm64/freescale/imx8qxp-tqma8xqp.dtsi create mode 100644 src/arm64/freescale/imx93-phyboard-segin.dts create mode 100644 src/arm64/freescale/imx93-phycore-som.dtsi create mode 100644 src/arm64/freescale/imx93-var-som-symphony.dts create mode 100644 src/arm64/freescale/imx93-var-som.dtsi create mode 100644 src/arm64/freescale/mba8xx.dtsi create mode 100644 src/arm64/freescale/tqma8xx.dtsi create mode 100644 src/arm64/mediatek/mt7981b-xiaomi-ax3000t.dts create mode 100644 src/arm64/mediatek/mt7981b.dtsi create mode 100644 src/arm64/mediatek/mt7986a-acelink-ew-7886cax.dts create mode 100644 src/arm64/mediatek/mt7988a-bananapi-bpi-r4.dts create mode 100644 src/arm64/mediatek/mt7988a.dtsi create mode 100644 src/arm64/mediatek/mt8186-corsola-krabby.dtsi create mode 100644 src/arm64/mediatek/mt8186-corsola-magneton-sku393216.dts create mode 100644 src/arm64/mediatek/mt8186-corsola-magneton-sku393217.dts create mode 100644 src/arm64/mediatek/mt8186-corsola-magneton-sku393218.dts create mode 100644 src/arm64/mediatek/mt8186-corsola-rusty-sku196608.dts create mode 100644 src/arm64/mediatek/mt8186-corsola-steelix-sku131072.dts create mode 100644 src/arm64/mediatek/mt8186-corsola-steelix-sku131073.dts create mode 100644 src/arm64/mediatek/mt8186-corsola-steelix.dtsi create mode 100644 src/arm64/mediatek/mt8186-corsola-tentacool-sku327681.dts create mode 100644 src/arm64/mediatek/mt8186-corsola-tentacool-sku327683.dts create mode 100644 src/arm64/mediatek/mt8186-corsola-tentacruel-sku262144.dts create mode 100644 src/arm64/mediatek/mt8186-corsola-tentacruel-sku262148.dts create mode 100644 src/arm64/mediatek/mt8186-corsola.dtsi create mode 100644 src/arm64/mediatek/mt8395-radxa-nio-12l.dts delete mode 100644 src/arm64/nvidia/tegra234-p3767-0000.dtsi delete mode 100644 src/arm64/nvidia/tegra234-p3767-0005.dtsi create mode 100644 src/arm64/qcom/msm8216-samsung-fortuna3g.dts create mode 100644 src/arm64/qcom/msm8916-samsung-fortuna-common.dtsi create mode 100644 src/arm64/qcom/msm8916-samsung-gprimeltecan.dts create mode 100644 src/arm64/qcom/msm8916-samsung-grandprimelte.dts create mode 100644 src/arm64/qcom/msm8916-samsung-rossa-common.dtsi create mode 100644 src/arm64/qcom/msm8916-samsung-rossa.dts rename src/arm64/qcom/{pm2250.dtsi => pm4125.dtsi} (56%) create mode 100644 src/arm64/qcom/sdm450.dtsi create mode 100644 src/arm64/qcom/sm7125-xiaomi-curtana.dts create mode 100644 src/arm64/qcom/sm8550-hdk.dts create mode 100644 src/arm64/renesas/r8a779g0-white-hawk-cpu.dts create mode 100644 src/arm64/renesas/r8a779g2-white-hawk-single.dts create mode 100644 src/arm64/renesas/r8a779g2.dtsi create mode 100644 src/arm64/renesas/r8a779h0-gray-hawk-single.dts create mode 100644 src/arm64/renesas/r8a779h0.dtsi create mode 100644 src/arm64/renesas/r9a07g043u11-smarc-cru-csi-ov5645.dtso create mode 100644 src/arm64/renesas/white-hawk-common.dtsi create mode 100644 src/arm64/renesas/white-hawk-cpu-common.dtsi rename src/arm64/renesas/{r8a779g0-white-hawk-csi-dsi.dtsi => white-hawk-csi-dsi.dtsi} (97%) rename src/arm64/renesas/{r8a779g0-white-hawk-ethernet.dtsi => white-hawk-ethernet.dtsi} (76%) create mode 100644 src/arm64/rockchip/rk3566-anbernic-rg-arc-d.dts create mode 100644 src/arm64/rockchip/rk3566-anbernic-rg-arc-s.dts create mode 100644 src/arm64/rockchip/rk3566-anbernic-rg-arc.dtsi create mode 100644 src/arm64/rockchip/rk3566-pinetab2-v0.1.dts create mode 100644 src/arm64/rockchip/rk3566-pinetab2-v2.0.dts create mode 100644 src/arm64/rockchip/rk3566-pinetab2.dtsi create mode 100644 src/arm64/rockchip/rk3566-powkiddy-rgb10max3.dts create mode 100644 src/arm64/rockchip/rk3568-qnap-ts433.dts create mode 100644 src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi create mode 100644 src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi create mode 100644 src/arm64/rockchip/rk3588-edgeble-neu6a-wifi.dtso create mode 100644 src/arm64/rockchip/rk3588-tiger-haikou.dts create mode 100644 src/arm64/rockchip/rk3588-tiger.dtsi create mode 100644 src/arm64/rockchip/rk3588-toybrick-x0.dts create mode 100644 src/arm64/rockchip/rk3588s-nanopi-r6c.dts create mode 100644 src/arm64/rockchip/rk3588s-nanopi-r6s.dts create mode 100644 src/arm64/ti/k3-am62x-phyboard-lyra-gpio-fan.dtso create mode 100644 src/arm64/ti/k3-am642-evm-icssg1-dualemac.dtso create mode 100644 src/arm64/ti/k3-am642-hummingboard-t-pcie.dtso create mode 100644 src/arm64/ti/k3-am642-hummingboard-t-usb3.dtso create mode 100644 src/arm64/ti/k3-am642-hummingboard-t.dts create mode 100644 src/arm64/ti/k3-am642-sr-som.dtsi create mode 100644 src/arm64/ti/k3-am65-iot2050-arduino-connector.dtsi create mode 100644 src/arm64/ti/k3-am65-iot2050-dp.dtsi create mode 100644 src/arm64/ti/k3-am65-iot2050-usb3.dtsi create mode 100644 src/arm64/ti/k3-am654-pcie-usb2.dtso create mode 100644 src/arm64/ti/k3-am654-pcie-usb3.dtso create mode 100644 src/arm64/ti/k3-am6548-iot2050-advanced-sm.dts create mode 100644 src/arm64/ti/k3-j721e-sk-csi2-dual-imx219.dtso create mode 100644 src/arm64/ti/k3-j722s-evm.dts create mode 100644 src/arm64/ti/k3-j722s.dtsi create mode 100644 src/mips/mobileye/eyeq5-epm5.dts create mode 100644 src/mips/mobileye/eyeq5-fixed-clocks.dtsi create mode 100644 src/mips/mobileye/eyeq5.dtsi diff --git a/Bindings/Makefile b/Bindings/Makefile index 129cf698fa8..5e08e3a6a97 100644 --- a/Bindings/Makefile +++ b/Bindings/Makefile @@ -64,9 +64,6 @@ override DTC_FLAGS := \ -Wno-unique_unit_address \ -Wunique_unit_address_if_enabled -# Disable undocumented compatible checks until warning free -override DT_CHECKER_FLAGS ?= - $(obj)/processed-schema.json: $(DT_DOCS) $(src)/.yamllint check_dtschema_version FORCE $(call if_changed_rule,chkdt) diff --git a/Bindings/arm/amlogic.yaml b/Bindings/arm/amlogic.yaml index caab7ceeda4..949537cea6b 100644 --- a/Bindings/arm/amlogic.yaml +++ b/Bindings/arm/amlogic.yaml @@ -7,19 +7,11 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Amlogic SoC based Platforms maintainers: + - Neil Armstrong + - Martin Blumenstingl + - Jerome Brunet - Kevin Hilman -description: |+ - Work in progress statement: - - Device tree files and bindings applying to Amlogic SoCs and boards are - considered "unstable". Any Amlogic device tree binding may change at - any time. Be sure to use a device tree binary and a kernel image - generated from the same source tree. - - Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a - stable binding/ABI. - properties: $nodename: const: '/' @@ -146,6 +138,7 @@ properties: - enum: - amediatech,x96-max - amlogic,u200 + - freebox,fbx8am - radxa,zero - seirobotics,sei510 - const: amlogic,g12a diff --git a/Bindings/arm/arm,realview.yaml b/Bindings/arm/arm,realview.yaml index d1bdee98f9a..3c5f1688dbd 100644 --- a/Bindings/arm/arm,realview.yaml +++ b/Bindings/arm/arm,realview.yaml @@ -10,9 +10,9 @@ maintainers: - Linus Walleij description: |+ - The ARM RealView series of reference designs were built to explore the ARM - 11, Cortex A-8 and Cortex A-9 CPUs. This included new features compared to - the earlier CPUs such as TrustZone and multicore (MPCore). + The ARM RealView series of reference designs were built to explore the Arm11, + Cortex-A8, and Cortex-A9 CPUs. This included new features compared to the + earlier CPUs such as TrustZone and multicore (MPCore). properties: $nodename: diff --git a/Bindings/arm/atmel-at91.yaml b/Bindings/arm/atmel-at91.yaml index 89d75fbb1de..82f37328cc6 100644 --- a/Bindings/arm/atmel-at91.yaml +++ b/Bindings/arm/atmel-at91.yaml @@ -179,6 +179,12 @@ properties: - const: microchip,sama7g5 - const: microchip,sama7 + - description: Microchip SAMA7G54 Curiosity Board + items: + - const: microchip,sama7g54-curiosity + - const: microchip,sama7g5 + - const: microchip,sama7 + - description: Microchip LAN9662 Evaluation Boards. items: - enum: diff --git a/Bindings/arm/fsl.yaml b/Bindings/arm/fsl.yaml index 228dcc5c7d6..0027201e19f 100644 --- a/Bindings/arm/fsl.yaml +++ b/Bindings/arm/fsl.yaml @@ -384,7 +384,8 @@ properties: - toradex,apalis_imx6q-ixora # Apalis iMX6Q/D Module on Ixora Carrier Board - toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6Q/D Module on Ixora V1.1 Carrier Board - toradex,apalis_imx6q-ixora-v1.2 # Apalis iMX6Q/D Module on Ixora V1.2 Carrier Board - - toradex,apalis_imx6q-eval # Apalis iMX6Q/D Module on Apalis Evaluation Board + - toradex,apalis_imx6q-eval # Apalis iMX6Q/D Module on Apalis Evaluation Board v1.0/v1.1 + - toradex,apalis_imx6q-eval-v1.2 # Apalis iMX6Q/D Module on Apalis Evaluation Board v1.2 - const: toradex,apalis_imx6q - const: fsl,imx6q @@ -469,6 +470,7 @@ properties: - prt,prtvt7 # Protonic VT7 board - rex,imx6dl-rex-basic # Rex Basic i.MX6 Dual Lite Board - riot,imx6s-riotboard # RIoTboard i.MX6S + - sielaff,imx6dl-board # Sielaff i.MX6 Solo Board - skov,imx6dl-skov-revc-lt2 # SKOV IMX6 CPU SoloCore lt2 - skov,imx6dl-skov-revc-lt6 # SKOV IMX6 CPU SoloCore lt6 - solidrun,cubox-i/dl # SolidRun Cubox-i Solo/DualLite @@ -708,6 +710,7 @@ properties: - toradex,colibri-imx6ull # Colibri iMX6ULL Modules - toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module - toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Modules + - uni-t,uti260b # UNI-T UTi260B Thermal Camera - const: fsl,imx6ull - description: i.MX6ULL Armadeus Systems OPOS6ULDev Board @@ -1026,7 +1029,7 @@ properties: items: - enum: - dimonoff,gateway-evk # i.MX8MN Dimonoff Gateway EVK Board - - rve,rve-gateway # i.MX8MN RVE Gateway Board + - rve,gateway # i.MX8MN RVE Gateway Board - variscite,var-som-mx8mn-symphony - const: variscite,var-som-mx8mn - const: fsl,imx8mn @@ -1194,7 +1197,8 @@ properties: - description: i.MX8QM Boards with Toradex Apalis iMX8 Modules items: - enum: - - toradex,apalis-imx8-eval # Apalis iMX8 Module on Apalis Evaluation Board + - toradex,apalis-imx8-eval # Apalis iMX8 Module on Apalis Evaluation V1.0/V1.1 Board + - toradex,apalis-imx8-eval-v1.2 # Apalis iMX8 Module on Apalis Evaluation V1.2 Board - toradex,apalis-imx8-ixora-v1.1 # Apalis iMX8 Module on Ixora V1.1 Carrier Board - const: toradex,apalis-imx8 - const: fsl,imx8qm @@ -1202,7 +1206,8 @@ properties: - description: i.MX8QM Boards with Toradex Apalis iMX8 V1.1 Modules items: - enum: - - toradex,apalis-imx8-v1.1-eval # Apalis iMX8 V1.1 Module on Apalis Eval. Board + - toradex,apalis-imx8-v1.1-eval # Apalis iMX8 V1.1 Module on Apalis Eval. V1.0/V1.1 Board + - toradex,apalis-imx8-v1.1-eval-v1.2 # Apalis iMX8 V1.1 Module on Apalis Eval. V1.2 Board - toradex,apalis-imx8-v1.1-ixora-v1.1 # Apalis iMX8 V1.1 Module on Ixora V1.1 C. Board - toradex,apalis-imx8-v1.1-ixora-v1.2 # Apalis iMX8 V1.1 Module on Ixora V1.2 C. Board - const: toradex,apalis-imx8-v1.1 @@ -1232,6 +1237,22 @@ properties: - const: toradex,colibri-imx8x - const: fsl,imx8qxp + - description: + TQMa8Xx is a series of SOM featuring NXP i.MX8X system-on-chip + variants. It is designed to be clicked on different carrier boards + MBa8Xx is the starterkit + oneOf: + - items: + - enum: + - tq,imx8dxp-tqma8xdp-mba8xx # TQ-Systems GmbH TQMa8XDP SOM on MBa8Xx + - const: tq,imx8dxp-tqma8xdp # TQ-Systems GmbH TQMa8XDP SOM (with i.MX8DXP) + - const: fsl,imx8dxp + - items: + - enum: + - tq,imx8qxp-tqma8xqp-mba8xx # TQ-Systems GmbH TQMa8XQP SOM on MBa8Xx + - const: tq,imx8qxp-tqma8xqp # TQ-Systems GmbH TQMa8XQP SOM (with i.MX8QXP) + - const: fsl,imx8qxp + - description: i.MX8ULP based Boards items: - enum: @@ -1275,6 +1296,18 @@ properties: - const: tq,imx93-tqma9352 # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM - const: fsl,imx93 + - description: PHYTEC phyCORE-i.MX93 SoM based boards + items: + - const: phytec,imx93-phyboard-segin # phyBOARD-Segin with i.MX93 + - const: phytec,imx93-phycore-som # phyCORE-i.MX93 SoM + - const: fsl,imx93 + + - description: Variscite VAR-SOM-MX93 based boards + items: + - const: variscite,var-som-mx93-symphony + - const: variscite,var-som-mx93 + - const: fsl,imx93 + - description: Freescale Vybrid Platform Device Tree Bindings diff --git a/Bindings/arm/marvell/armada-38x.txt b/Bindings/arm/marvell/armada-38x.txt deleted file mode 100644 index 202953f1887..00000000000 --- a/Bindings/arm/marvell/armada-38x.txt +++ /dev/null @@ -1,27 +0,0 @@ -Marvell Armada 38x Platforms Device Tree Bindings -------------------------------------------------- - -Boards with a SoC of the Marvell Armada 38x family shall have the -following property: - -Required root node property: - - - compatible: must contain "marvell,armada380" - -In addition, boards using the Marvell Armada 385 SoC shall have the -following property before the previous one: - -Required root node property: - -compatible: must contain "marvell,armada385" - -In addition, boards using the Marvell Armada 388 SoC shall have the -following property before the previous one: - -Required root node property: - -compatible: must contain "marvell,armada388" - -Example: - -compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada380"; diff --git a/Bindings/arm/marvell/armada-38x.yaml b/Bindings/arm/marvell/armada-38x.yaml new file mode 100644 index 00000000000..cdf805b5db9 --- /dev/null +++ b/Bindings/arm/marvell/armada-38x.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/marvell/armada-38x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 38x Platforms + +maintainers: + - Gregory CLEMENT + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: + Netgear Armada 380 GS110EM Managed Switch. + items: + - const: netgear,gs110emx + - const: marvell,armada380 + + - description: + Marvell Armada 385 Development Boards. + items: + - enum: + - marvell,a385-db-amc + - marvell,a385-db-ap + - const: marvell,armada385 + - const: marvell,armada380 + + - description: + SolidRun Armada 385 based single-board computers. + items: + - enum: + - solidrun,clearfog-gtr-l8 + - solidrun,clearfog-gtr-s4 + - const: marvell,armada385 + - const: marvell,armada380 + + - description: + Kobol Armada 388 based Helios-4 NAS. + items: + - const: kobol,helios4 + - const: marvell,armada388 + - const: marvell,armada385 + - const: marvell,armada380 + + - description: + Marvell Armada 388 Development Boards. + items: + - enum: + - marvell,a388-gp + - const: marvell,armada388 + - const: marvell,armada385 + - const: marvell,armada380 + + - description: + SolidRun Armada 388 clearfog family single-board computers. + items: + - enum: + - solidrun,clearfog-base-a1 + - solidrun,clearfog-pro-a1 + - const: solidrun,clearfog-a1 + - const: marvell,armada388 + - const: marvell,armada385 + - const: marvell,armada380 + +additionalProperties: true diff --git a/Bindings/arm/mediatek.yaml b/Bindings/arm/mediatek.yaml index 6f2f64ae76f..09f9ffd3ff7 100644 --- a/Bindings/arm/mediatek.yaml +++ b/Bindings/arm/mediatek.yaml @@ -17,6 +17,7 @@ properties: const: '/' compatible: oneOf: + # Sort by SoC (last) compatible, then board compatible - items: - enum: - mediatek,mt2701-evb @@ -84,6 +85,11 @@ properties: - const: mediatek,mt7629 - items: - enum: + - xiaomi,ax3000t + - const: mediatek,mt7981b + - items: + - enum: + - acelink,ew-7886cax - bananapi,bpi-r3 - mediatek,mt7986a-rfb - const: mediatek,mt7986a @@ -91,6 +97,10 @@ properties: - enum: - mediatek,mt7986b-rfb - const: mediatek,mt7986b + - items: + - enum: + - bananapi,bpi-r4 + - const: mediatek,mt7988a - items: - enum: - mediatek,mt8127-moose @@ -129,75 +139,10 @@ properties: - enum: - mediatek,mt8173-evb - const: mediatek,mt8173 - - items: - - enum: - - mediatek,mt8183-evb - - const: mediatek,mt8183 - - description: Google Hayato rev5 - items: - - const: google,hayato-rev5-sku2 - - const: google,hayato-sku2 - - const: google,hayato - - const: mediatek,mt8192 - - description: Google Hayato - items: - - const: google,hayato-rev1 - - const: google,hayato - - const: mediatek,mt8192 - - description: Google Spherion rev4 (Acer Chromebook 514) - items: - - const: google,spherion-rev4 - - const: google,spherion - - const: mediatek,mt8192 - - description: Google Spherion (Acer Chromebook 514) - items: - - const: google,spherion-rev3 - - const: google,spherion-rev2 - - const: google,spherion-rev1 - - const: google,spherion-rev0 - - const: google,spherion - - const: mediatek,mt8192 - - description: Acer Tomato (Acer Chromebook Spin 513 CP513-2H) - items: - - enum: - - google,tomato-rev2 - - google,tomato-rev1 - - const: google,tomato - - const: mediatek,mt8195 - - description: Acer Tomato rev3 - 4 (Acer Chromebook Spin 513 CP513-2H) - items: - - const: google,tomato-rev4 - - const: google,tomato-rev3 - - const: google,tomato - - const: mediatek,mt8195 - - items: - - enum: - - mediatek,mt8186-evb - - const: mediatek,mt8186 - - items: - - enum: - - mediatek,mt8188-evb - - const: mediatek,mt8188 - - items: - - enum: - - mediatek,mt8192-evb - - const: mediatek,mt8192 - - items: - - enum: - - mediatek,mt8195-demo - - mediatek,mt8195-evb - - const: mediatek,mt8195 - description: Google Burnet (HP Chromebook x360 11MK G3 EE) items: - const: google,burnet - const: mediatek,mt8183 - - description: Google Krane (Lenovo IdeaPad Duet, 10e,...) - items: - - enum: - - google,krane-sku0 - - google,krane-sku176 - - const: google,krane - - const: mediatek,mt8183 - description: Google Cozmo (Acer Chromebook 314) items: - const: google,cozmo @@ -255,6 +200,13 @@ properties: - google,kodama-sku32 - const: google,kodama - const: mediatek,mt8183 + - description: Google Krane (Lenovo IdeaPad Duet, 10e,...) + items: + - enum: + - google,krane-sku0 + - google,krane-sku176 + - const: google,krane + - const: mediatek,mt8183 - description: Google Makomo (Lenovo 100e Chromebook 2nd Gen MTK 2) items: - enum: @@ -276,10 +228,125 @@ properties: - google,willow-sku1 - const: google,willow - const: mediatek,mt8183 + - items: + - enum: + - mediatek,mt8183-evb + - const: mediatek,mt8183 - items: - enum: - mediatek,mt8183-pumpkin - const: mediatek,mt8183 + - description: Google Magneton (Lenovo IdeaPad Slim 3 Chromebook (14M868)) + items: + - const: google,steelix-sku393219 + - const: google,steelix-sku393216 + - const: google,steelix + - const: mediatek,mt8186 + - description: Google Magneton (Lenovo IdeaPad Slim 3 Chromebook (14M868)) + items: + - const: google,steelix-sku393220 + - const: google,steelix-sku393217 + - const: google,steelix + - const: mediatek,mt8186 + - description: Google Magneton (Lenovo IdeaPad Slim 3 Chromebook (14M868)) + items: + - const: google,steelix-sku393221 + - const: google,steelix-sku393218 + - const: google,steelix + - const: mediatek,mt8186 + - description: Google Rusty (Lenovo 100e Chromebook Gen 4) + items: + - const: google,steelix-sku196609 + - const: google,steelix-sku196608 + - const: google,steelix + - const: mediatek,mt8186 + - description: Google Steelix (Lenovo 300e Yoga Chromebook Gen 4) + items: + - enum: + - google,steelix-sku131072 + - google,steelix-sku131073 + - const: google,steelix + - const: mediatek,mt8186 + - description: Google Tentacruel (ASUS Chromebook CM14 Flip CM1402F) + items: + - const: google,tentacruel-sku262147 + - const: google,tentacruel-sku262146 + - const: google,tentacruel-sku262145 + - const: google,tentacruel-sku262144 + - const: google,tentacruel + - const: mediatek,mt8186 + - description: Google Tentacruel (ASUS Chromebook CM14 Flip CM1402F) + items: + - const: google,tentacruel-sku262151 + - const: google,tentacruel-sku262150 + - const: google,tentacruel-sku262149 + - const: google,tentacruel-sku262148 + - const: google,tentacruel + - const: mediatek,mt8186 + - description: Google Tentacool (ASUS Chromebook CM14 CM1402C) + items: + - const: google,tentacruel-sku327681 + - const: google,tentacruel + - const: mediatek,mt8186 + - description: Google Tentacool (ASUS Chromebook CM14 CM1402C) + items: + - const: google,tentacruel-sku327683 + - const: google,tentacruel + - const: mediatek,mt8186 + - items: + - enum: + - mediatek,mt8186-evb + - const: mediatek,mt8186 + - items: + - enum: + - mediatek,mt8188-evb + - const: mediatek,mt8188 + - description: Google Hayato + items: + - const: google,hayato-rev1 + - const: google,hayato + - const: mediatek,mt8192 + - description: Google Hayato rev5 + items: + - const: google,hayato-rev5-sku2 + - const: google,hayato-sku2 + - const: google,hayato + - const: mediatek,mt8192 + - description: Google Spherion (Acer Chromebook 514) + items: + - const: google,spherion-rev3 + - const: google,spherion-rev2 + - const: google,spherion-rev1 + - const: google,spherion-rev0 + - const: google,spherion + - const: mediatek,mt8192 + - description: Google Spherion rev4 (Acer Chromebook 514) + items: + - const: google,spherion-rev4 + - const: google,spherion + - const: mediatek,mt8192 + - items: + - enum: + - mediatek,mt8192-evb + - const: mediatek,mt8192 + - description: Acer Tomato (Acer Chromebook Spin 513 CP513-2H) + items: + - enum: + - google,tomato-rev2 + - google,tomato-rev1 + - const: google,tomato + - const: mediatek,mt8195 + - description: Acer Tomato rev3 - 4 (Acer Chromebook Spin 513 CP513-2H) + items: + - const: google,tomato-rev4 + - const: google,tomato-rev3 + - const: google,tomato + - const: mediatek,mt8195 + - items: + - enum: + - mediatek,mt8195-demo + - mediatek,mt8195-evb + - const: mediatek,mt8195 - items: - enum: - mediatek,mt8365-evk @@ -287,6 +354,7 @@ properties: - items: - enum: - mediatek,mt8395-evk + - radxa,nio-12l - const: mediatek,mt8395 - const: mediatek,mt8195 - items: diff --git a/Bindings/arm/mediatek/mediatek,hifsys.txt b/Bindings/arm/mediatek/mediatek,hifsys.txt deleted file mode 100644 index 323905af82c..00000000000 --- a/Bindings/arm/mediatek/mediatek,hifsys.txt +++ /dev/null @@ -1,26 +0,0 @@ -Mediatek hifsys controller -============================ - -The Mediatek hifsys controller provides various clocks and reset -outputs to the system. - -Required Properties: - -- compatible: Should be: - - "mediatek,mt2701-hifsys", "syscon" - - "mediatek,mt7622-hifsys", "syscon" - - "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", "syscon" -- #clock-cells: Must be 1 - -The hifsys controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -hifsys: clock-controller@1a000000 { - compatible = "mediatek,mt2701-hifsys", "syscon"; - reg = <0 0x1a000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/Bindings/arm/mediatek/mediatek,pciesys.txt b/Bindings/arm/mediatek/mediatek,pciesys.txt deleted file mode 100644 index d179a61536f..00000000000 --- a/Bindings/arm/mediatek/mediatek,pciesys.txt +++ /dev/null @@ -1,25 +0,0 @@ -MediaTek PCIESYS controller -============================ - -The MediaTek PCIESYS controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be: - - "mediatek,mt7622-pciesys", "syscon" - - "mediatek,mt7629-pciesys", "syscon" -- #clock-cells: Must be 1 -- #reset-cells: Must be 1 - -The PCIESYS controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -pciesys: pciesys@1a100800 { - compatible = "mediatek,mt7622-pciesys", "syscon"; - reg = <0 0x1a100800 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/Bindings/arm/mediatek/mediatek,ssusbsys.txt b/Bindings/arm/mediatek/mediatek,ssusbsys.txt deleted file mode 100644 index 7cb02c93061..00000000000 --- a/Bindings/arm/mediatek/mediatek,ssusbsys.txt +++ /dev/null @@ -1,25 +0,0 @@ -MediaTek SSUSBSYS controller -============================ - -The MediaTek SSUSBSYS controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be: - - "mediatek,mt7622-ssusbsys", "syscon" - - "mediatek,mt7629-ssusbsys", "syscon" -- #clock-cells: Must be 1 -- #reset-cells: Must be 1 - -The SSUSBSYS controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -ssusbsys: ssusbsys@1a000000 { - compatible = "mediatek,mt7622-ssusbsys", "syscon"; - reg = <0 0x1a000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/Bindings/arm/msm/qcom,saw2.txt b/Bindings/arm/msm/qcom,saw2.txt deleted file mode 100644 index c0e3c3a42be..00000000000 --- a/Bindings/arm/msm/qcom,saw2.txt +++ /dev/null @@ -1,58 +0,0 @@ -SPM AVS Wrapper 2 (SAW2) - -The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the -Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable -power-controller that transitions a piece of hardware (like a processor or -subsystem) into and out of low power modes via a direct connection to -the PMIC. It can also be wired up to interact with other processors in the -system, notifying them when a low power state is entered or exited. - -Multiple revisions of the SAW hardware are supported using these Device Nodes. -SAW2 revisions differ in the register offset and configuration data. Also, the -same revision of the SAW in different SoCs may have different configuration -data due the differences in hardware capabilities. Hence the SoC name, the -version of the SAW hardware in that SoC and the distinction between cpu (big -or Little) or cache, may be needed to uniquely identify the SAW register -configuration and initialization data. The compatible string is used to -indicate this parameter. - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: Must have - "qcom,saw2" - A more specific value could be one of: - "qcom,apq8064-saw2-v1.1-cpu" - "qcom,msm8226-saw2-v2.1-cpu" - "qcom,msm8974-saw2-v2.1-cpu" - "qcom,apq8084-saw2-v2.1-cpu" - -- reg: - Usage: required - Value type: - Definition: the first element specifies the base address and size of - the register region. An optional second element specifies - the base address and size of the alias register region. - -- regulator: - Usage: optional - Value type: boolean - Definition: Indicates that this SPM device acts as a regulator device - device for the core (CPU or Cache) the SPM is attached - to. - -Example 1: - - power-controller@2099000 { - compatible = "qcom,saw2"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - -Example 2: - saw0: power-controller@f9089000 { - compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; - }; diff --git a/Bindings/arm/qcom,coresight-tpdm.yaml b/Bindings/arm/qcom,coresight-tpdm.yaml index 61ddc3b5b24..8eec07d9d45 100644 --- a/Bindings/arm/qcom,coresight-tpdm.yaml +++ b/Bindings/arm/qcom,coresight-tpdm.yaml @@ -44,14 +44,21 @@ properties: minItems: 1 maxItems: 2 - qcom,dsb-element-size: + qcom,dsb-element-bits: description: Specifies the DSB(Discrete Single Bit) element size supported by the monitor. The associated aggregator will read this size before it is enabled. DSB element size currently only supports 32-bit and 64-bit. - $ref: /schemas/types.yaml#/definitions/uint8 enum: [32, 64] + qcom,cmb-element-bits: + description: + Specifies the CMB(Continuous Multi-Bit) element size supported by + the monitor. The associated aggregator will read this size before it + is enabled. CMB element size currently only supports 8-bit, 32-bit + and 64-bit. + enum: [8, 32, 64] + qcom,dsb-msrs-num: description: Specifies the number of DSB(Discrete Single Bit) MSR(mux select register) @@ -61,6 +68,15 @@ properties: minimum: 0 maximum: 32 + qcom,cmb-msrs-num: + description: + Specifies the number of CMB MSR(mux select register) registers supported + by the monitor. If this property is not configured or set to 0, it means + this TPDM doesn't support CMB MSR. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 32 + clocks: maxItems: 1 @@ -94,7 +110,7 @@ examples: compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0684c000 0x1000>; - qcom,dsb-element-size = /bits/ 8 <32>; + qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <16>; clocks = <&aoss_qmp>; @@ -110,4 +126,22 @@ examples: }; }; + tpdm@6c29000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x06c29000 0x1000>; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_out_funnel_center: endpoint { + remote-endpoint = <&funnel_center_in_tpdm_ipcc>; + }; + }; + }; + }; ... diff --git a/Bindings/arm/qcom.yaml b/Bindings/arm/qcom.yaml index 1a5fb889a44..66beaac60e1 100644 --- a/Bindings/arm/qcom.yaml +++ b/Bindings/arm/qcom.yaml @@ -10,17 +10,10 @@ maintainers: - Bjorn Andersson description: | - Some qcom based bootloaders identify the dtb blob based on a set of - device properties like SoC and platform and revisions of those components. - To support this scheme, we encode this information into the board compatible - string. - - Each board must specify a top-level board compatible string with the following - format: - - compatible = "qcom,[-][-]-[/][-]" - - The 'SoC' and 'board' elements are required. All other elements are optional. + For devices using the Qualcomm SoC the "compatible" properties consists of + one or several "manufacturer,model" strings, describing the device itself, + followed by one or several "qcom," strings, describing the SoC used in + the device. The 'SoC' element must be one of the following strings: @@ -90,43 +83,9 @@ description: | sm8650 x1e80100 - The 'board' element must be one of the following strings: - - adp - cdp - dragonboard - idp - liquid - mtp - qcp - qrd - rb2 - ride - sbc - x100 - - The 'soc_version' and 'board_version' elements take the form of v. - where the minor number may be omitted when it's zero, i.e. v1.0 is the same - as v1. If all versions of the 'board_version' elements match, then a - wildcard '*' should be used, e.g. 'v*'. - - The 'foundry_id' and 'subtype' elements are one or more digits from 0 to 9. - - Examples: - - "qcom,msm8916-v1-cdp-pm8916-v2.1" - - A CDP board with an msm8916 SoC, version 1 paired with a pm8916 PMIC of version - 2.1. - - "qcom,apq8074-v2.0-2-dragonboard/1-v0.1" - - A dragonboard board v0.1 of subtype 1 with an apq8074 SoC version 2, made in - foundry 2. - There are many devices in the list below that run the standard ChromeOS bootloader setup and use the open source depthcharge bootloader to boot the - OS. These devices do not use the scheme described above. For details, see: + OS. These devices use the bootflow explained at https://docs.kernel.org/arch/arm/google/chromebook-boot-flow.html properties: @@ -187,6 +146,7 @@ properties: - microsoft,superman-lte - microsoft,tesla - motorola,peregrine + - samsung,matisselte - const: qcom,msm8926 - const: qcom,msm8226 @@ -244,11 +204,15 @@ properties: - samsung,a5u-eur - samsung,e5 - samsung,e7 + - samsung,fortuna3g + - samsung,gprimeltecan - samsung,grandmax + - samsung,grandprimelte - samsung,gt510 - samsung,gt58 - samsung,j5 - samsung,j5x + - samsung,rossa - samsung,serranove - thwc,uf896 - thwc,ufi001c @@ -988,6 +952,7 @@ properties: - items: - enum: + - xiaomi,curtana - xiaomi,joyeuse - const: qcom,sm7125 @@ -1035,6 +1000,7 @@ properties: - items: - enum: + - qcom,sm8550-hdk - qcom,sm8550-mtp - qcom,sm8550-qrd - const: qcom,sm8550 diff --git a/Bindings/arm/rockchip.yaml b/Bindings/arm/rockchip.yaml index 5cf5cbef2cf..fcf7316ecd7 100644 --- a/Bindings/arm/rockchip.yaml +++ b/Bindings/arm/rockchip.yaml @@ -37,29 +37,16 @@ properties: - anbernic,rg351v - const: rockchip,rk3326 - - description: Anbernic RG353P + - description: Anbernic RK3566 Handheld Gaming Console items: - - const: anbernic,rg353p - - const: rockchip,rk3566 - - - description: Anbernic RG353PS - items: - - const: anbernic,rg353ps - - const: rockchip,rk3566 - - - description: Anbernic RG353V - items: - - const: anbernic,rg353v - - const: rockchip,rk3566 - - - description: Anbernic RG353VS - items: - - const: anbernic,rg353vs - - const: rockchip,rk3566 - - - description: Anbernic RG503 - items: - - const: anbernic,rg503 + - enum: + - anbernic,rg353p + - anbernic,rg353ps + - anbernic,rg353v + - anbernic,rg353vs + - anbernic,rg503 + - anbernic,rg-arc-d + - anbernic,rg-arc-s - const: rockchip,rk3566 - description: Asus Tinker board @@ -237,6 +224,13 @@ properties: - friendlyarm,nanopi-r5s - const: rockchip,rk3568 + - description: FriendlyElec NanoPi R6 series boards + items: + - enum: + - friendlyarm,nanopi-r6c + - friendlyarm,nanopi-r6s + - const: rockchip,rk3588s + - description: FriendlyElec NanoPC T6 items: - const: friendlyarm,nanopc-t6 @@ -626,9 +620,9 @@ properties: - const: openailab,eaidk-610 - const: rockchip,rk3399 - - description: Orange Pi RK3399 board + - description: Xunlong Orange Pi RK3399 board items: - - const: rockchip,rk3399-orangepi + - const: xunlong,rk3399-orangepi - const: rockchip,rk3399 - description: Phytec phyCORE-RK3288 Rapid Development Kit @@ -655,6 +649,14 @@ properties: - const: pine64,pinephone-pro - const: rockchip,rk3399 + - description: Pine64 PineTab2 + items: + - enum: + - pine64,pinetab2-v0.1 + - pine64,pinetab2-v2.0 + - const: pine64,pinetab2 + - const: rockchip,rk3566 + - description: Pine64 Rock64 items: - const: pine64,rock64 @@ -692,11 +694,17 @@ properties: - description: Powkiddy RK3566 Handheld Gaming Console items: - enum: + - powkiddy,rgb10max3 - powkiddy,rgb30 - powkiddy,rk2023 - powkiddy,x55 - const: rockchip,rk3566 + - description: QNAP TS-433-4G 4-Bay NAS + items: + - const: qnap,ts433 + - const: rockchip,rk3568 + - description: Radxa Compute Module 3(CM3) items: - enum: @@ -878,6 +886,11 @@ properties: - const: rockchip,rv1108-evb - const: rockchip,rv1108 + - description: Rockchip Toybrick TB-RK3588X board + items: + - const: rockchip,rk3588-toybrick-x0 + - const: rockchip,rk3588 + - description: Theobroma Systems PX30-uQ7 with Haikou baseboard items: - const: tsd,px30-ringneck-haikou @@ -898,6 +911,12 @@ properties: - const: tsd,rk3588-jaguar - const: rockchip,rk3588 + - description: Theobroma Systems RK3588-Q7 with Haikou baseboard + items: + - const: tsd,rk3588-tiger-haikou + - const: tsd,rk3588-tiger + - const: rockchip,rk3588 + - description: Tronsmart Orion R68 Meta items: - const: tronsmart,orion-r68-meta @@ -940,9 +959,9 @@ properties: - const: rockchip,rk3568-evb1-v10 - const: rockchip,rk3568 - - description: Rockchip RK3568 Banana Pi R2 Pro + - description: Sinovoip RK3568 Banana Pi R2 Pro items: - - const: rockchip,rk3568-bpi-r2pro + - const: sinovoip,rk3568-bpi-r2pro - const: rockchip,rk3568 - description: Sonoff iHost Smart Home Hub diff --git a/Bindings/arm/sunxi.yaml b/Bindings/arm/sunxi.yaml index a9d8e85565b..09d835db6db 100644 --- a/Bindings/arm/sunxi.yaml +++ b/Bindings/arm/sunxi.yaml @@ -815,6 +815,12 @@ properties: - const: allwinner,r7-tv-dongle - const: allwinner,sun5i-a10s + - description: Remix Mini PC + items: + - const: jide,remix-mini-pc + - const: allwinner,sun50i-h64 + - const: allwinner,sun50i-a64 + - description: RerVision H3-DVK items: - const: rervision,h3-dvk @@ -835,6 +841,12 @@ properties: - const: sinlinx,sina33 - const: allwinner,sun8i-a33 + - description: Sipeed Longan Pi 3H board for the Sipeed Longan Module 3H + items: + - const: sipeed,longan-pi-3h + - const: sipeed,longan-module-3h + - const: allwinner,sun50i-h618 + - description: SourceParts PopStick v1.1 items: - const: sourceparts,popstick-v1.1 diff --git a/Bindings/arm/syna.txt b/Bindings/arm/syna.txt index 851f48ead92..f53c430f648 100644 --- a/Bindings/arm/syna.txt +++ b/Bindings/arm/syna.txt @@ -6,18 +6,6 @@ berlin SoCs are now Synaptics' SoCs now. --------------------------------------------------------------- -Work in progress statement: - -Device tree files and bindings applying to Marvell Berlin SoCs and boards are -considered "unstable". Any Marvell Berlin device tree binding may change at any -time. Be sure to use a device tree binary and a kernel image generated from the -same source tree. - -Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a -stable binding/ABI. - ---------------------------------------------------------------- - Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500 shall have the following properties: diff --git a/Bindings/arm/tegra.yaml b/Bindings/arm/tegra.yaml index fcf95640616..8fb4923517d 100644 --- a/Bindings/arm/tegra.yaml +++ b/Bindings/arm/tegra.yaml @@ -64,6 +64,14 @@ properties: - items: - const: asus,tf700t - const: nvidia,tegra30 + - description: LG Optimus 4X P880 + items: + - const: lg,p880 + - const: nvidia,tegra30 + - description: LG Optimus Vu P895 + items: + - const: lg,p895 + - const: nvidia,tegra30 - items: - const: toradex,apalis_t30-eval - const: toradex,apalis_t30 diff --git a/Bindings/arm/tegra/nvidia,tegra186-pmc.yaml b/Bindings/arm/tegra/nvidia,tegra186-pmc.yaml index 0faa403f68c..ea4fbf65522 100644 --- a/Bindings/arm/tegra/nvidia,tegra186-pmc.yaml +++ b/Bindings/arm/tegra/nvidia,tegra186-pmc.yaml @@ -27,7 +27,7 @@ properties: - const: pmc - const: wake - const: aotag - - const: scratch + - enum: [ scratch, misc ] - const: misc interrupt-controller: true @@ -41,25 +41,43 @@ properties: description: If present, inverts the PMU interrupt signal. $ref: /schemas/types.yaml#/definitions/flag -if: - properties: - compatible: - contains: - const: nvidia,tegra186-pmc -then: - properties: - reg: - maxItems: 4 +allOf: + - if: + properties: + compatible: + contains: + const: nvidia,tegra186-pmc + then: + properties: + reg: + maxItems: 4 + reg-names: + maxItems: 4 + contains: + const: scratch - reg-names: - maxItems: 4 -else: - properties: - reg: - minItems: 5 + - if: + properties: + compatible: + contains: + const: nvidia,tegra194-pmc + then: + properties: + reg: + minItems: 5 + reg-names: + minItems: 5 - reg-names: - minItems: 5 + - if: + properties: + compatible: + contains: + const: nvidia,tegra234-pmc + then: + properties: + reg-names: + contains: + const: misc patternProperties: "^[a-z0-9]+-[a-z0-9]+$": diff --git a/Bindings/arm/ti/k3.yaml b/Bindings/arm/ti/k3.yaml index c6506bccfe8..52b51fd7044 100644 --- a/Bindings/arm/ti/k3.yaml +++ b/Bindings/arm/ti/k3.yaml @@ -87,12 +87,20 @@ properties: - const: tq,am642-tqma6442l - const: ti,am642 + - description: K3 AM642 SoC SolidRun SoM based boards + items: + - enum: + - solidrun,am642-hummingboard-t + - const: solidrun,am642-sr-som + - const: ti,am642 + - description: K3 AM654 SoC items: - enum: - siemens,iot2050-advanced - siemens,iot2050-advanced-m2 - siemens,iot2050-advanced-pg2 + - siemens,iot2050-advanced-sm - siemens,iot2050-basic - siemens,iot2050-basic-pg2 - ti,am654-evm @@ -123,6 +131,12 @@ properties: - ti,j721s2-evm - const: ti,j721s2 + - description: K3 J722S SoC and Boards + items: + - enum: + - ti,j722s-evm + - const: ti,j722s + - description: K3 J784s4 SoC items: - enum: diff --git a/Bindings/ata/ahci-mtk.txt b/Bindings/ata/ahci-mtk.txt deleted file mode 100644 index d2aa696b161..00000000000 --- a/Bindings/ata/ahci-mtk.txt +++ /dev/null @@ -1,51 +0,0 @@ -MediaTek Serial ATA controller - -Required properties: - - compatible : Must be "mediatek,-ahci", "mediatek,mtk-ahci". - When using "mediatek,mtk-ahci" compatible strings, you - need SoC specific ones in addition, one of: - - "mediatek,mt7622-ahci" - - reg : Physical base addresses and length of register sets. - - interrupts : Interrupt associated with the SATA device. - - interrupt-names : Associated name must be: "hostc". - - clocks : A list of phandle and clock specifier pairs, one for each - entry in clock-names. - - clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm". - - phys : A phandle and PHY specifier pair for the PHY port. - - phy-names : Associated name must be: "sata-phy". - - ports-implemented : See ./ahci-platform.txt for details. - -Optional properties: - - power-domains : A phandle and power domain specifier pair to the power - domain which is responsible for collapsing and restoring - power to the peripheral. - - resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names : Associated names must be: "axi", "sw", "reg". - - mediatek,phy-mode : A phandle to the system controller, used to enable - SATA function. - -Example: - - sata: sata@1a200000 { - compatible = "mediatek,mt7622-ahci", - "mediatek,mtk-ahci"; - reg = <0 0x1a200000 0 0x1100>; - interrupts = ; - interrupt-names = "hostc"; - clocks = <&pciesys CLK_SATA_AHB_EN>, - <&pciesys CLK_SATA_AXI_EN>, - <&pciesys CLK_SATA_ASIC_EN>, - <&pciesys CLK_SATA_RBC_EN>, - <&pciesys CLK_SATA_PM_EN>; - clock-names = "ahb", "axi", "asic", "rbc", "pm"; - phys = <&u3port1 PHY_TYPE_SATA>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; - resets = <&pciesys MT7622_SATA_AXI_BUS_RST>, - <&pciesys MT7622_SATA_PHY_SW_RST>, - <&pciesys MT7622_SATA_PHY_REG_RST>; - reset-names = "axi", "sw", "reg"; - mediatek,phy-mode = <&pciesys>; - }; diff --git a/Bindings/ata/atmel-at91_cf.txt b/Bindings/ata/atmel-at91_cf.txt deleted file mode 100644 index c1d22b3ae13..00000000000 --- a/Bindings/ata/atmel-at91_cf.txt +++ /dev/null @@ -1,19 +0,0 @@ -Atmel AT91RM9200 CompactFlash - -Required properties: -- compatible : "atmel,at91rm9200-cf". -- reg : should specify localbus address and size used. -- gpios : specifies the gpio pins to control the CF device. Detect - and reset gpio's are mandatory while irq and vcc gpio's are - optional and may be set to 0 if not present. - -Example: -compact-flash@50000000 { - compatible = "atmel,at91rm9200-cf"; - reg = <0x50000000 0x30000000>; - gpios = <&pioC 13 0 /* irq */ - &pioC 15 0 /* detect */ - 0 /* vcc */ - &pioC 5 0 /* reset */ - >; -}; diff --git a/Bindings/ata/mediatek,mtk-ahci.yaml b/Bindings/ata/mediatek,mtk-ahci.yaml new file mode 100644 index 00000000000..a34bd2e9c35 --- /dev/null +++ b/Bindings/ata/mediatek,mtk-ahci.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/mediatek,mtk-ahci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Serial ATA controller + +maintainers: + - Ryder Lee + +allOf: + - $ref: ahci-common.yaml# + +properties: + compatible: + items: + - enum: + - mediatek,mt7622-ahci + - const: mediatek,mtk-ahci + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-names: + const: hostc + + clocks: + maxItems: 5 + + clock-names: + items: + - const: ahb + - const: axi + - const: asic + - const: rbc + - const: pm + + power-domains: + maxItems: 1 + + resets: + maxItems: 3 + + reset-names: + items: + - const: axi + - const: sw + - const: reg + + mediatek,phy-mode: + description: System controller phandle, used to enable SATA function + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - phys + - phy-names + - ports-implemented + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + sata@1a200000 { + compatible = "mediatek,mt7622-ahci", "mediatek,mtk-ahci"; + reg = <0x1a200000 0x1100>; + interrupts = ; + interrupt-names = "hostc"; + clocks = <&pciesys CLK_SATA_AHB_EN>, + <&pciesys CLK_SATA_AXI_EN>, + <&pciesys CLK_SATA_ASIC_EN>, + <&pciesys CLK_SATA_RBC_EN>, + <&pciesys CLK_SATA_PM_EN>; + clock-names = "ahb", "axi", "asic", "rbc", "pm"; + phys = <&u3port1 PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; + resets = <&pciesys MT7622_SATA_AXI_BUS_RST>, + <&pciesys MT7622_SATA_PHY_SW_RST>, + <&pciesys MT7622_SATA_PHY_REG_RST>; + reset-names = "axi", "sw", "reg"; + mediatek,phy-mode = <&pciesys>; + }; diff --git a/Bindings/auxdisplay/arm,versatile-lcd.yaml b/Bindings/auxdisplay/arm,versatile-lcd.yaml index 5d02bd032a8..439f7b811a9 100644 --- a/Bindings/auxdisplay/arm,versatile-lcd.yaml +++ b/Bindings/auxdisplay/arm,versatile-lcd.yaml @@ -39,6 +39,6 @@ additionalProperties: false examples: - | lcd@10008000 { - compatible = "arm,versatile-lcd"; - reg = <0x10008000 0x1000>; + compatible = "arm,versatile-lcd"; + reg = <0x10008000 0x1000>; }; diff --git a/Bindings/auxdisplay/gpio-7-segment.yaml b/Bindings/auxdisplay/gpio-7-segment.yaml new file mode 100644 index 00000000000..328954893c6 --- /dev/null +++ b/Bindings/auxdisplay/gpio-7-segment.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/auxdisplay/gpio-7-segment.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GPIO based LED segment display + +maintainers: + - Chris Packham + +properties: + compatible: + const: gpio-7-segment + + segment-gpios: + description: | + An array of GPIOs one per segment. The first GPIO corresponds to the A + segment, the seventh GPIO corresponds to the G segment. Some LED blocks + also have a decimal point which can be specified as an optional eighth + segment. + + -a- + | | + f b + | | + -g- + | | + e c + | | + -d- dp + + minItems: 7 + maxItems: 8 + +required: + - segment-gpios + +additionalProperties: false + +examples: + - | + + #include + + led-7seg { + compatible = "gpio-7-segment"; + segment-gpios = <&gpio 0 GPIO_ACTIVE_LOW>, + <&gpio 1 GPIO_ACTIVE_LOW>, + <&gpio 2 GPIO_ACTIVE_LOW>, + <&gpio 3 GPIO_ACTIVE_LOW>, + <&gpio 4 GPIO_ACTIVE_LOW>, + <&gpio 5 GPIO_ACTIVE_LOW>, + <&gpio 6 GPIO_ACTIVE_LOW>; + }; diff --git a/Bindings/auxdisplay/hit,hd44780.yaml b/Bindings/auxdisplay/hit,hd44780.yaml index 406a922a714..3ca0e9863d8 100644 --- a/Bindings/auxdisplay/hit,hd44780.yaml +++ b/Bindings/auxdisplay/hit,hd44780.yaml @@ -84,42 +84,44 @@ additionalProperties: false examples: - | #include - auxdisplay { - compatible = "hit,hd44780"; + display-controller { + compatible = "hit,hd44780"; - data-gpios = <&hc595 0 GPIO_ACTIVE_HIGH>, - <&hc595 1 GPIO_ACTIVE_HIGH>, - <&hc595 2 GPIO_ACTIVE_HIGH>, - <&hc595 3 GPIO_ACTIVE_HIGH>; - enable-gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; - rs-gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; + data-gpios = <&hc595 0 GPIO_ACTIVE_HIGH>, + <&hc595 1 GPIO_ACTIVE_HIGH>, + <&hc595 2 GPIO_ACTIVE_HIGH>, + <&hc595 3 GPIO_ACTIVE_HIGH>; + enable-gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; + rs-gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; - display-height-chars = <2>; - display-width-chars = <16>; + display-height-chars = <2>; + display-width-chars = <16>; }; + - | #include i2c { - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - pcf8574: pcf8574@27 { - compatible = "nxp,pcf8574"; - reg = <0x27>; - gpio-controller; - #gpio-cells = <2>; - }; + pcf8574: gpio-expander@27 { + compatible = "nxp,pcf8574"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + }; }; - hd44780 { - compatible = "hit,hd44780"; - display-height-chars = <2>; - display-width-chars = <16>; - data-gpios = <&pcf8574 4 0>, - <&pcf8574 5 0>, - <&pcf8574 6 0>, - <&pcf8574 7 0>; - enable-gpios = <&pcf8574 2 0>; - rs-gpios = <&pcf8574 0 0>; - rw-gpios = <&pcf8574 1 0>; - backlight-gpios = <&pcf8574 3 0>; + + display-controller { + compatible = "hit,hd44780"; + display-height-chars = <2>; + display-width-chars = <16>; + data-gpios = <&pcf8574 4 GPIO_ACTIVE_HIGH>, + <&pcf8574 5 GPIO_ACTIVE_HIGH>, + <&pcf8574 6 GPIO_ACTIVE_HIGH>, + <&pcf8574 7 GPIO_ACTIVE_HIGH>; + enable-gpios = <&pcf8574 2 GPIO_ACTIVE_HIGH>; + rs-gpios = <&pcf8574 0 GPIO_ACTIVE_HIGH>; + rw-gpios = <&pcf8574 1 GPIO_ACTIVE_HIGH>; + backlight-gpios = <&pcf8574 3 GPIO_ACTIVE_HIGH>; }; diff --git a/Bindings/auxdisplay/holtek,ht16k33.yaml b/Bindings/auxdisplay/holtek,ht16k33.yaml index be95f6b97b4..b90eec2077b 100644 --- a/Bindings/auxdisplay/holtek,ht16k33.yaml +++ b/Bindings/auxdisplay/holtek,ht16k33.yaml @@ -74,31 +74,31 @@ examples: #include #include i2c { - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - ht16k33: ht16k33@70 { - compatible = "holtek,ht16k33"; - reg = <0x70>; - refresh-rate-hz = <20>; - interrupt-parent = <&gpio4>; - interrupts = <5 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>; - debounce-delay-ms = <50>; - linux,keymap = , - , - , - , - , - , - , - , - , - ; + display-controller@70 { + compatible = "holtek,ht16k33"; + reg = <0x70>; + refresh-rate-hz = <20>; + interrupt-parent = <&gpio4>; + interrupts = <5 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>; + debounce-delay-ms = <50>; + linux,keymap = , + , + , + , + , + , + , + , + , + ; - led { - color = ; - function = LED_FUNCTION_BACKLIGHT; - linux,default-trigger = "backlight"; - }; + led { + color = ; + function = LED_FUNCTION_BACKLIGHT; + linux,default-trigger = "backlight"; }; - }; + }; + }; diff --git a/Bindings/auxdisplay/img,ascii-lcd.yaml b/Bindings/auxdisplay/img,ascii-lcd.yaml index 1899b23de7d..55e9831b3f6 100644 --- a/Bindings/auxdisplay/img,ascii-lcd.yaml +++ b/Bindings/auxdisplay/img,ascii-lcd.yaml @@ -50,6 +50,6 @@ additionalProperties: false examples: - | lcd: lcd@17fff000 { - compatible = "img,boston-lcd"; - reg = <0x17fff000 0x8>; + compatible = "img,boston-lcd"; + reg = <0x17fff000 0x8>; }; diff --git a/Bindings/auxdisplay/maxim,max6959.yaml b/Bindings/auxdisplay/maxim,max6959.yaml new file mode 100644 index 00000000000..20dd9e8c819 --- /dev/null +++ b/Bindings/auxdisplay/maxim,max6959.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/auxdisplay/maxim,max6959.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MAX6958/6959 7-segment LED display controller + +maintainers: + - Andy Shevchenko + +description: + The Maxim MAX6958/6959 7-segment LED display controller provides + an I2C interface to up to four 7-segment LED digits. The MAX6959, + in comparison to MAX6958, adds input support. Type of the chip can + be autodetected via specific register read, and hence the features + may be enabled in the driver at run-time, in case they are requested + via Device Tree. A given hardware is simple and does not provide + any additional pins, such as reset or power enable. + +properties: + compatible: + const: maxim,max6959 + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + display-controller@38 { + compatible = "maxim,max6959"; + reg = <0x38>; + }; + }; diff --git a/Bindings/bus/brcm,gisb-arb.yaml b/Bindings/bus/brcm,gisb-arb.yaml index 3aaefdbe361..9017c5a3f3d 100644 --- a/Bindings/bus/brcm,gisb-arb.yaml +++ b/Bindings/bus/brcm,gisb-arb.yaml @@ -18,6 +18,7 @@ properties: - const: brcm,gisb-arb - items: - enum: + - brcm,bcm74165-gisb-arb # for V7 new style 16nm chips - brcm,bcm7278-gisb-arb # for V7 28nm chips - brcm,bcm7435-gisb-arb # for newer 40nm chips - brcm,bcm7400-gisb-arb # for older 40nm chips and all 65nm chips diff --git a/Bindings/bus/imx-weim.txt b/Bindings/bus/imx-weim.txt deleted file mode 100644 index e7f502070d7..00000000000 --- a/Bindings/bus/imx-weim.txt +++ /dev/null @@ -1,117 +0,0 @@ -Device tree bindings for i.MX Wireless External Interface Module (WEIM) - -The term "wireless" does not imply that the WEIM is literally an interface -without wires. It simply means that this module was originally designed for -wireless and mobile applications that use low-power technology. - -The actual devices are instantiated from the child nodes of a WEIM node. - -Required properties: - - - compatible: Should contain one of the following: - "fsl,imx1-weim" - "fsl,imx27-weim" - "fsl,imx51-weim" - "fsl,imx50-weim" - "fsl,imx6q-weim" - - reg: A resource specifier for the register space - (see the example below) - - clocks: the clock, see the example below. - - #address-cells: Must be set to 2 to allow memory address translation - - #size-cells: Must be set to 1 to allow CS address passing - - ranges: Must be set up to reflect the memory layout with four - integer values for each chip-select line in use: - - 0 - -Optional properties: - - - fsl,weim-cs-gpr: For "fsl,imx50-weim" and "fsl,imx6q-weim" type of - devices, it should be the phandle to the system General - Purpose Register controller that contains WEIM CS GPR - register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0] - should be set up as one of the following 4 possible - values depending on the CS space configuration. - - IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3 - --------------------------------------------- - 05 128M 0M 0M 0M - 033 64M 64M 0M 0M - 0113 64M 32M 32M 0M - 01111 32M 32M 32M 32M - - In case that the property is absent, the reset value or - what bootloader sets up in IOMUXC_GPR1[11:0] will be - used. - - - fsl,burst-clk-enable For "fsl,imx50-weim" and "fsl,imx6q-weim" type of - devices, the presence of this property indicates that - the weim bus should operate in Burst Clock Mode. - - - fsl,continuous-burst-clk Make Burst Clock to output continuous clock. - Without this option Burst Clock will output clock - only when necessary. This takes effect only if - "fsl,burst-clk-enable" is set. - -Timing property for child nodes. It is mandatory, not optional. - - - fsl,weim-cs-timing: The timing array, contains timing values for the - child node. We get the CS indexes from the address - ranges in the child node's "reg" property. - The number of registers depends on the selected chip: - For i.MX1, i.MX21 ("fsl,imx1-weim") there are two - registers: CSxU, CSxL. - For i.MX25, i.MX27, i.MX31 and i.MX35 ("fsl,imx27-weim") - there are three registers: CSCRxU, CSCRxL, CSCRxA. - For i.MX50, i.MX53 ("fsl,imx50-weim"), - i.MX51 ("fsl,imx51-weim") and i.MX6Q ("fsl,imx6q-weim") - there are six registers: CSxGCR1, CSxGCR2, CSxRCR1, - CSxRCR2, CSxWCR1, CSxWCR2. - -Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM: - - weim: weim@21b8000 { - compatible = "fsl,imx6q-weim"; - reg = <0x021b8000 0x4000>; - clocks = <&clks 196>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x08000000 0x08000000>; - fsl,weim-cs-gpr = <&gpr>; - - nor@0,0 { - compatible = "cfi-flash"; - reg = <0 0 0x02000000>; - #address-cells = <1>; - #size-cells = <1>; - bank-width = <2>; - fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 - 0x0000c000 0x1404a38e 0x00000000>; - }; - }; - -Example for an imx6q-based board, a multi-chipselect device connected to WEIM: - -In this case, both chip select 0 and 1 will be configured with the same timing -array values. - - weim: weim@21b8000 { - compatible = "fsl,imx6q-weim"; - reg = <0x021b8000 0x4000>; - clocks = <&clks 196>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x08000000 0x02000000 - 1 0 0x0a000000 0x02000000 - 2 0 0x0c000000 0x02000000 - 3 0 0x0e000000 0x02000000>; - fsl,weim-cs-gpr = <&gpr>; - - acme@0 { - compatible = "acme,whatever"; - reg = <0 0 0x100>, <0 0x400000 0x800>, - <1 0x400000 0x800>; - fsl,weim-cs-timing = <0x024400b1 0x00001010 0x20081100 - 0x00000000 0xa0000240 0x00000000>; - }; - }; diff --git a/Bindings/clock/google,gs101-clock.yaml b/Bindings/clock/google,gs101-clock.yaml index ca7fdada3ff..1d2bcea41c8 100644 --- a/Bindings/clock/google,gs101-clock.yaml +++ b/Bindings/clock/google,gs101-clock.yaml @@ -30,14 +30,16 @@ properties: - google,gs101-cmu-top - google,gs101-cmu-apm - google,gs101-cmu-misc + - google,gs101-cmu-peric0 + - google,gs101-cmu-peric1 clocks: minItems: 1 - maxItems: 2 + maxItems: 3 clock-names: minItems: 1 - maxItems: 2 + maxItems: 3 "#clock-cells": const: 1 @@ -88,6 +90,28 @@ allOf: - const: bus - const: sss + - if: + properties: + compatible: + contains: + enum: + - google,gs101-cmu-peric0 + - google,gs101-cmu-peric1 + + then: + properties: + clocks: + items: + - description: External reference clock (24.576 MHz) + - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP) + - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - const: ip + additionalProperties: false examples: diff --git a/Bindings/clock/keystone-gate.txt b/Bindings/clock/keystone-gate.txt index c5aa187026e..43f6fb6c939 100644 --- a/Bindings/clock/keystone-gate.txt +++ b/Bindings/clock/keystone-gate.txt @@ -1,5 +1,3 @@ -Status: Unstable - ABI compatibility may be broken in the future - Binding for Keystone gate control driver which uses PSC controller IP. This binding uses the common clock binding[1]. diff --git a/Bindings/clock/keystone-pll.txt b/Bindings/clock/keystone-pll.txt index 9a3fbc66560..69b0eb7c03c 100644 --- a/Bindings/clock/keystone-pll.txt +++ b/Bindings/clock/keystone-pll.txt @@ -1,5 +1,3 @@ -Status: Unstable - ABI compatibility may be broken in the future - Binding for keystone PLLs. The main PLL IP typically has a multiplier, a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL and PAPLL are controlled by the memory mapped register where as the Main diff --git a/Bindings/clock/mediatek,mt2701-hifsys.yaml b/Bindings/clock/mediatek,mt2701-hifsys.yaml new file mode 100644 index 00000000000..9e7c725093a --- /dev/null +++ b/Bindings/clock/mediatek,mt2701-hifsys.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt2701-hifsys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek HIFSYS clock and reset controller + +description: + The MediaTek HIFSYS controller provides various clocks and reset outputs to + the system. + +maintainers: + - Matthias Brugger + +properties: + compatible: + oneOf: + - enum: + - mediatek,mt2701-hifsys + - mediatek,mt7622-hifsys + - items: + - enum: + - mediatek,mt7623-hifsys + - const: mediatek,mt2701-hifsys + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + description: The available clocks are defined in dt-bindings/clock/mt*-clk.h + + "#reset-cells": + const: 1 + +required: + - reg + - "#clock-cells" + +additionalProperties: false + +examples: + - | + clock-controller@1a000000 { + compatible = "mediatek,mt2701-hifsys"; + reg = <0x1a000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Bindings/clock/mediatek,mt7622-pciesys.yaml b/Bindings/clock/mediatek,mt7622-pciesys.yaml new file mode 100644 index 00000000000..c77111d10f9 --- /dev/null +++ b/Bindings/clock/mediatek,mt7622-pciesys.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt7622-pciesys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek PCIESYS clock and reset controller + +description: + The MediaTek PCIESYS controller provides various clocks to the system. + +maintainers: + - Matthias Brugger + +properties: + compatible: + enum: + - mediatek,mt7622-pciesys + - mediatek,mt7629-pciesys + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + description: The available clocks are defined in dt-bindings/clock/mt*-clk.h + + "#reset-cells": + const: 1 + +required: + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@1a100800 { + compatible = "mediatek,mt7622-pciesys"; + reg = <0x1a100800 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Bindings/clock/mediatek,mt7622-ssusbsys.yaml b/Bindings/clock/mediatek,mt7622-ssusbsys.yaml new file mode 100644 index 00000000000..da93eccdcfc --- /dev/null +++ b/Bindings/clock/mediatek,mt7622-ssusbsys.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt7622-ssusbsys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek SSUSBSYS clock and reset controller + +description: + The MediaTek SSUSBSYS controller provides various clocks to the system. + +maintainers: + - Matthias Brugger + +properties: + compatible: + enum: + - mediatek,mt7622-ssusbsys + - mediatek,mt7629-ssusbsys + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + description: The available clocks are defined in dt-bindings/clock/mt*-clk.h + + "#reset-cells": + const: 1 + +required: + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@1a000000 { + compatible = "mediatek,mt7622-ssusbsys"; + reg = <0x1a000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Bindings/clock/mobileye,eyeq5-clk.yaml b/Bindings/clock/mobileye,eyeq5-clk.yaml new file mode 100644 index 00000000000..2d4f2cde1e5 --- /dev/null +++ b/Bindings/clock/mobileye,eyeq5-clk.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mobileye,eyeq5-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye EyeQ5 clock controller + +description: + The EyeQ5 clock controller handles 10 read-only PLLs derived from the main + crystal clock. It also exposes one divider clock, a child of one of the PLLs. + Its registers live in a shared region called OLB. + +maintainers: + - Grégory Clement + - Théo Lebrun + - Vladimir Kondratiev + +properties: + compatible: + const: mobileye,eyeq5-clk + + reg: + maxItems: 2 + + reg-names: + items: + - const: plls + - const: ospi + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + description: + Input parent clock to all PLLs. Expected to be the main crystal. + + clock-names: + items: + - const: ref + +required: + - compatible + - reg + - reg-names + - "#clock-cells" + - clocks + - clock-names + +additionalProperties: false diff --git a/Bindings/clock/qcom,gcc-sc8180x.yaml b/Bindings/clock/qcom,gcc-sc8180x.yaml index 6c4846b34e4..a1085ef4fd0 100644 --- a/Bindings/clock/qcom,gcc-sc8180x.yaml +++ b/Bindings/clock/qcom,gcc-sc8180x.yaml @@ -31,10 +31,15 @@ properties: - const: bi_tcxo_ao - const: sleep_clk + power-domains: + items: + - description: CX domain + required: - compatible - clocks - clock-names + - power-domains allOf: - $ref: qcom,gcc.yaml# @@ -44,6 +49,7 @@ unevaluatedProperties: false examples: - | #include + #include clock-controller@100000 { compatible = "qcom,gcc-sc8180x"; reg = <0x00100000 0x1f0000>; @@ -51,6 +57,7 @@ examples: <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + power-domains = <&rpmhpd SC8180X_CX>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; diff --git a/Bindings/clock/qcom,gpucc.yaml b/Bindings/clock/qcom,gpucc.yaml index f369fa34e00..f57aceddac6 100644 --- a/Bindings/clock/qcom,gpucc.yaml +++ b/Bindings/clock/qcom,gpucc.yaml @@ -53,6 +53,9 @@ properties: power-domains: maxItems: 1 + vdd-gfx-supply: + description: Regulator supply for the VDD_GFX pads + '#clock-cells': const: 1 @@ -74,6 +77,12 @@ required: - '#reset-cells' - '#power-domain-cells' +# Require that power-domains and vdd-gfx-supply are not both present +not: + required: + - power-domains + - vdd-gfx-supply + additionalProperties: false examples: diff --git a/Bindings/clock/qcom,q6sstopcc.yaml b/Bindings/clock/qcom,q6sstopcc.yaml index 03fa30fe925..e0f4d692728 100644 --- a/Bindings/clock/qcom,q6sstopcc.yaml +++ b/Bindings/clock/qcom,q6sstopcc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Q6SSTOP clock Controller maintainers: - - Govind Singh + - Bjorn Andersson properties: compatible: diff --git a/Bindings/clock/qcom,sc7180-mss.yaml b/Bindings/clock/qcom,sc7180-mss.yaml deleted file mode 100644 index 873a2f918ba..00000000000 --- a/Bindings/clock/qcom,sc7180-mss.yaml +++ /dev/null @@ -1,61 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/clock/qcom,sc7180-mss.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm Modem Clock Controller on SC7180 - -maintainers: - - Taniya Das - -description: | - Qualcomm modem clock control module provides the clocks on SC7180. - - See also:: include/dt-bindings/clock/qcom,mss-sc7180.h - -properties: - compatible: - const: qcom,sc7180-mss - - clocks: - items: - - description: gcc_mss_mfab_axi clock from GCC - - description: gcc_mss_nav_axi clock from GCC - - description: gcc_mss_cfg_ahb clock from GCC - - clock-names: - items: - - const: gcc_mss_mfab_axis - - const: gcc_mss_nav_axi - - const: cfg_ahb - - '#clock-cells': - const: 1 - - reg: - maxItems: 1 - -required: - - compatible - - reg - - clocks - - '#clock-cells' - -additionalProperties: false - -examples: - - | - #include - clock-controller@41a8000 { - compatible = "qcom,sc7180-mss"; - reg = <0x041a8000 0x8000>; - clocks = <&gcc GCC_MSS_MFAB_AXIS_CLK>, - <&gcc GCC_MSS_NAV_AXI_CLK>, - <&gcc GCC_MSS_CFG_AHB_CLK>; - clock-names = "gcc_mss_mfab_axis", - "gcc_mss_nav_axi", - "cfg_ahb"; - #clock-cells = <1>; - }; -... diff --git a/Bindings/clock/qcom,sm8450-camcc.yaml b/Bindings/clock/qcom,sm8450-camcc.yaml index 48986460f99..fa0e5b6b02b 100644 --- a/Bindings/clock/qcom,sm8450-camcc.yaml +++ b/Bindings/clock/qcom,sm8450-camcc.yaml @@ -17,6 +17,7 @@ description: | include/dt-bindings/clock/qcom,sm8450-camcc.h include/dt-bindings/clock/qcom,sm8550-camcc.h include/dt-bindings/clock/qcom,sc8280xp-camcc.h + include/dt-bindings/clock/qcom,x1e80100-camcc.h allOf: - $ref: qcom,gcc.yaml# @@ -27,6 +28,7 @@ properties: - qcom,sc8280xp-camcc - qcom,sm8450-camcc - qcom,sm8550-camcc + - qcom,x1e80100-camcc clocks: items: diff --git a/Bindings/clock/qcom,sm8450-gpucc.yaml b/Bindings/clock/qcom,sm8450-gpucc.yaml index 1a384e8532a..36974309cf6 100644 --- a/Bindings/clock/qcom,sm8450-gpucc.yaml +++ b/Bindings/clock/qcom,sm8450-gpucc.yaml @@ -18,6 +18,7 @@ description: | include/dt-bindings/clock/qcom,sm8550-gpucc.h include/dt-bindings/reset/qcom,sm8450-gpucc.h include/dt-bindings/reset/qcom,sm8650-gpucc.h + include/dt-bindings/reset/qcom,x1e80100-gpucc.h properties: compatible: @@ -25,6 +26,7 @@ properties: - qcom,sm8450-gpucc - qcom,sm8550-gpucc - qcom,sm8650-gpucc + - qcom,x1e80100-gpucc clocks: items: diff --git a/Bindings/clock/qcom,sm8550-dispcc.yaml b/Bindings/clock/qcom,sm8550-dispcc.yaml index c129f8c16b5..bad0260764d 100644 --- a/Bindings/clock/qcom,sm8550-dispcc.yaml +++ b/Bindings/clock/qcom,sm8550-dispcc.yaml @@ -14,12 +14,17 @@ description: | Qualcomm display clock control module provides the clocks, resets and power domains on SM8550. - See also:: include/dt-bindings/clock/qcom,sm8550-dispcc.h + See also: + - include/dt-bindings/clock/qcom,sm8550-dispcc.h + - include/dt-bindings/clock/qcom,sm8650-dispcc.h + - include/dt-bindings/clock/qcom,x1e80100-dispcc.h properties: compatible: enum: - qcom,sm8550-dispcc + - qcom,sm8650-dispcc + - qcom,x1e80100-dispcc clocks: items: diff --git a/Bindings/clock/qcom,sm8550-tcsr.yaml b/Bindings/clock/qcom,sm8550-tcsr.yaml index af16b05eac9..48fdd562d74 100644 --- a/Bindings/clock/qcom,sm8550-tcsr.yaml +++ b/Bindings/clock/qcom,sm8550-tcsr.yaml @@ -23,6 +23,7 @@ properties: - enum: - qcom,sm8550-tcsr - qcom,sm8650-tcsr + - qcom,x1e80100-tcsr - const: syscon clocks: diff --git a/Bindings/clock/qcom,sm8650-dispcc.yaml b/Bindings/clock/qcom,sm8650-dispcc.yaml deleted file mode 100644 index 5e0c45c380f..00000000000 --- a/Bindings/clock/qcom,sm8650-dispcc.yaml +++ /dev/null @@ -1,106 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/clock/qcom,sm8650-dispcc.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm Display Clock & Reset Controller for SM8650 - -maintainers: - - Bjorn Andersson - - Neil Armstrong - -description: | - Qualcomm display clock control module provides the clocks, resets and power - domains on SM8650. - - See also:: include/dt-bindings/clock/qcom,sm8650-dispcc.h - -properties: - compatible: - enum: - - qcom,sm8650-dispcc - - clocks: - items: - - description: Board XO source - - description: Board Always On XO source - - description: Display's AHB clock - - description: sleep clock - - description: Byte clock from DSI PHY0 - - description: Pixel clock from DSI PHY0 - - description: Byte clock from DSI PHY1 - - description: Pixel clock from DSI PHY1 - - description: Link clock from DP PHY0 - - description: VCO DIV clock from DP PHY0 - - description: Link clock from DP PHY1 - - description: VCO DIV clock from DP PHY1 - - description: Link clock from DP PHY2 - - description: VCO DIV clock from DP PHY2 - - description: Link clock from DP PHY3 - - description: VCO DIV clock from DP PHY3 - - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - - power-domains: - description: - A phandle and PM domain specifier for the MMCX power domain. - maxItems: 1 - - required-opps: - description: - A phandle to an OPP node describing required MMCX performance point. - maxItems: 1 - -required: - - compatible - - reg - - clocks - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' - -additionalProperties: false - -examples: - - | - #include - #include - #include - #include - clock-controller@af00000 { - compatible = "qcom,sm8650-dispcc"; - reg = <0x0af00000 0x10000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&rpmhcc RPMH_CXO_CLK_A>, - <&gcc GCC_DISP_AHB_CLK>, - <&sleep_clk>, - <&dsi0_phy 0>, - <&dsi0_phy 1>, - <&dsi1_phy 0>, - <&dsi1_phy 1>, - <&dp0_phy 0>, - <&dp0_phy 1>, - <&dp1_phy 0>, - <&dp1_phy 1>, - <&dp2_phy 0>, - <&dp2_phy 1>, - <&dp3_phy 0>, - <&dp3_phy 1>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; - }; -... diff --git a/Bindings/clock/renesas,cpg-mssr.yaml b/Bindings/clock/renesas,cpg-mssr.yaml index 9c3dc6c4fa9..084259d3023 100644 --- a/Bindings/clock/renesas,cpg-mssr.yaml +++ b/Bindings/clock/renesas,cpg-mssr.yaml @@ -50,6 +50,7 @@ properties: - renesas,r8a779a0-cpg-mssr # R-Car V3U - renesas,r8a779f0-cpg-mssr # R-Car S4-8 - renesas,r8a779g0-cpg-mssr # R-Car V4H + - renesas,r8a779h0-cpg-mssr # R-Car V4M reg: maxItems: 1 diff --git a/Bindings/clock/samsung,exynos850-clock.yaml b/Bindings/clock/samsung,exynos850-clock.yaml index c752c8985a5..cdc5ded59fe 100644 --- a/Bindings/clock/samsung,exynos850-clock.yaml +++ b/Bindings/clock/samsung,exynos850-clock.yaml @@ -36,6 +36,8 @@ properties: - samsung,exynos850-cmu-aud - samsung,exynos850-cmu-cmgp - samsung,exynos850-cmu-core + - samsung,exynos850-cmu-cpucl0 + - samsung,exynos850-cmu-cpucl1 - samsung,exynos850-cmu-dpu - samsung,exynos850-cmu-g3d - samsung,exynos850-cmu-hsi @@ -152,6 +154,46 @@ allOf: - const: dout_core_mmc_embd - const: dout_core_sss + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-cpucl0 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CPUCL0 switch clock (from CMU_TOP) + - description: CPUCL0 debug clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_cpucl0_switch + - const: dout_cpucl0_dbg + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-cpucl1 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CPUCL1 switch clock (from CMU_TOP) + - description: CPUCL1 debug clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_cpucl1_switch + - const: dout_cpucl1_dbg + - if: properties: compatible: diff --git a/Bindings/clock/tesla,fsd-clock.yaml b/Bindings/clock/tesla,fsd-clock.yaml index dc808e2f832..b370a10a23a 100644 --- a/Bindings/clock/tesla,fsd-clock.yaml +++ b/Bindings/clock/tesla,fsd-clock.yaml @@ -12,7 +12,7 @@ maintainers: description: | FSD clock controller consist of several clock management unit - (CMU), which generates clocks for various inteernal SoC blocks. + (CMU), which generates clocks for various internal SoC blocks. The root clock comes from external OSC clock (24 MHz). All available clocks are defined as preprocessor macros in diff --git a/Bindings/clock/ti/adpll.txt b/Bindings/clock/ti/adpll.txt index 4c8a2ce2cd7..3122360adcf 100644 --- a/Bindings/clock/ti/adpll.txt +++ b/Bindings/clock/ti/adpll.txt @@ -1,7 +1,5 @@ Binding for Texas Instruments ADPLL clock. -Binding status: Unstable - ABI compatibility may be broken in the future - This binding uses the common clock binding[1]. It assumes a register-mapped ADPLL with two to three selectable input clocks and three to four children. diff --git a/Bindings/clock/ti/apll.txt b/Bindings/clock/ti/apll.txt index ade4dd4c30f..bbd505c1199 100644 --- a/Bindings/clock/ti/apll.txt +++ b/Bindings/clock/ti/apll.txt @@ -1,7 +1,5 @@ Binding for Texas Instruments APLL clock. -Binding status: Unstable - ABI compatibility may be broken in the future - This binding uses the common clock binding[1]. It assumes a register-mapped APLL with usually two selectable input clocks (reference clock and bypass clock), with analog phase locked diff --git a/Bindings/clock/ti/autoidle.txt b/Bindings/clock/ti/autoidle.txt index 7c735dde9fe..05645a10a9e 100644 --- a/Bindings/clock/ti/autoidle.txt +++ b/Bindings/clock/ti/autoidle.txt @@ -1,7 +1,5 @@ Binding for Texas Instruments autoidle clock. -Binding status: Unstable - ABI compatibility may be broken in the future - This binding uses the common clock binding[1]. It assumes a register mapped clock which can be put to idle automatically by hardware based on the usage and a configuration bit setting. Autoidle clock is never an individual diff --git a/Bindings/clock/ti/clockdomain.txt b/Bindings/clock/ti/clockdomain.txt index 9c6199249ce..edf0b5d4276 100644 --- a/Bindings/clock/ti/clockdomain.txt +++ b/Bindings/clock/ti/clockdomain.txt @@ -1,7 +1,5 @@ Binding for Texas Instruments clockdomain. -Binding status: Unstable - ABI compatibility may be broken in the future - This binding uses the common clock binding[1] in consumer role. Every clock on TI SoC belongs to one clockdomain, but software only needs this information for specific clocks which require diff --git a/Bindings/clock/ti/composite.txt b/Bindings/clock/ti/composite.txt index 33ac7c9ad05..6f7e1331b54 100644 --- a/Bindings/clock/ti/composite.txt +++ b/Bindings/clock/ti/composite.txt @@ -1,7 +1,5 @@ Binding for TI composite clock. -Binding status: Unstable - ABI compatibility may be broken in the future - This binding uses the common clock binding[1]. It assumes a register-mapped composite clock with multiple different sub-types; diff --git a/Bindings/clock/ti/divider.txt b/Bindings/clock/ti/divider.txt index 9b13b32974f..4d7c76f0b35 100644 --- a/Bindings/clock/ti/divider.txt +++ b/Bindings/clock/ti/divider.txt @@ -1,7 +1,5 @@ Binding for TI divider clock -Binding status: Unstable - ABI compatibility may be broken in the future - This binding uses the common clock binding[1]. It assumes a register-mapped adjustable clock rate divider that does not gate and has only one input clock or parent. By default the value programmed into diff --git a/Bindings/clock/ti/dpll.txt b/Bindings/clock/ti/dpll.txt index 37a7cb6ad07..14a1b72c2e7 100644 --- a/Bindings/clock/ti/dpll.txt +++ b/Bindings/clock/ti/dpll.txt @@ -1,7 +1,5 @@ Binding for Texas Instruments DPLL clock. -Binding status: Unstable - ABI compatibility may be broken in the future - This binding uses the common clock binding[1]. It assumes a register-mapped DPLL with usually two selectable input clocks (reference clock and bypass clock), with digital phase locked diff --git a/Bindings/clock/ti/fapll.txt b/Bindings/clock/ti/fapll.txt index c19b3f253b8..88986ef39dd 100644 --- a/Bindings/clock/ti/fapll.txt +++ b/Bindings/clock/ti/fapll.txt @@ -1,7 +1,5 @@ Binding for Texas Instruments FAPLL clock. -Binding status: Unstable - ABI compatibility may be broken in the future - This binding uses the common clock binding[1]. It assumes a register-mapped FAPLL with usually two selectable input clocks (reference clock and bypass clock), and one or more child diff --git a/Bindings/clock/ti/fixed-factor-clock.txt b/Bindings/clock/ti/fixed-factor-clock.txt index 518e3c14227..dc69477b6e9 100644 --- a/Bindings/clock/ti/fixed-factor-clock.txt +++ b/Bindings/clock/ti/fixed-factor-clock.txt @@ -1,7 +1,5 @@ Binding for TI fixed factor rate clock sources. -Binding status: Unstable - ABI compatibility may be broken in the future - This binding uses the common clock binding[1], and also uses the autoidle support from TI autoidle clock [2]. diff --git a/Bindings/clock/ti/gate.txt b/Bindings/clock/ti/gate.txt index 4982615c01b..a8e0335b006 100644 --- a/Bindings/clock/ti/gate.txt +++ b/Bindings/clock/ti/gate.txt @@ -1,7 +1,5 @@ Binding for Texas Instruments gate clock. -Binding status: Unstable - ABI compatibility may be broken in the future - This binding uses the common clock binding[1]. This clock is quite much similar to the basic gate-clock [2], however, it supports a number of additional features. If no register diff --git a/Bindings/clock/ti/interface.txt b/Bindings/clock/ti/interface.txt index d3eb5ca92a7..85fb1f2d2d2 100644 --- a/Bindings/clock/ti/interface.txt +++ b/Bindings/clock/ti/interface.txt @@ -1,7 +1,5 @@ Binding for Texas Instruments interface clock. -Binding status: Unstable - ABI compatibility may be broken in the future - This binding uses the common clock binding[1]. This clock is quite much similar to the basic gate-clock [2], however, it supports a number of additional features, including diff --git a/Bindings/clock/ti/mux.txt b/Bindings/clock/ti/mux.txt index b33f641f104..cd56d3c1c09 100644 --- a/Bindings/clock/ti/mux.txt +++ b/Bindings/clock/ti/mux.txt @@ -1,7 +1,5 @@ Binding for TI mux clock. -Binding status: Unstable - ABI compatibility may be broken in the future - This binding uses the common clock binding[1]. It assumes a register-mapped multiplexer with multiple input clock signals or parents, one of which can be selected as output. This clock does not diff --git a/Bindings/crypto/atmel,at91sam9g46-aes.yaml b/Bindings/crypto/atmel,at91sam9g46-aes.yaml index 0b7383b3106..7dc0748444f 100644 --- a/Bindings/crypto/atmel,at91sam9g46-aes.yaml +++ b/Bindings/crypto/atmel,at91sam9g46-aes.yaml @@ -12,7 +12,11 @@ maintainers: properties: compatible: - const: atmel,at91sam9g46-aes + oneOf: + - const: atmel,at91sam9g46-aes + - items: + - const: microchip,sam9x7-aes + - const: atmel,at91sam9g46-aes reg: maxItems: 1 diff --git a/Bindings/crypto/atmel,at91sam9g46-sha.yaml b/Bindings/crypto/atmel,at91sam9g46-sha.yaml index ee2ffb03432..d378c53314d 100644 --- a/Bindings/crypto/atmel,at91sam9g46-sha.yaml +++ b/Bindings/crypto/atmel,at91sam9g46-sha.yaml @@ -12,7 +12,11 @@ maintainers: properties: compatible: - const: atmel,at91sam9g46-sha + oneOf: + - const: atmel,at91sam9g46-sha + - items: + - const: microchip,sam9x7-sha + - const: atmel,at91sam9g46-sha reg: maxItems: 1 diff --git a/Bindings/crypto/atmel,at91sam9g46-tdes.yaml b/Bindings/crypto/atmel,at91sam9g46-tdes.yaml index 3d6ed24b1b0..6a441f79efe 100644 --- a/Bindings/crypto/atmel,at91sam9g46-tdes.yaml +++ b/Bindings/crypto/atmel,at91sam9g46-tdes.yaml @@ -12,7 +12,11 @@ maintainers: properties: compatible: - const: atmel,at91sam9g46-tdes + oneOf: + - const: atmel,at91sam9g46-tdes + - items: + - const: microchip,sam9x7-tdes + - const: atmel,at91sam9g46-tdes reg: maxItems: 1 diff --git a/Bindings/crypto/qcom,inline-crypto-engine.yaml b/Bindings/crypto/qcom,inline-crypto-engine.yaml index 09e43157cc7..e91bc7dc6ad 100644 --- a/Bindings/crypto/qcom,inline-crypto-engine.yaml +++ b/Bindings/crypto/qcom,inline-crypto-engine.yaml @@ -14,6 +14,7 @@ properties: items: - enum: - qcom,sa8775p-inline-crypto-engine + - qcom,sc7180-inline-crypto-engine - qcom,sm8450-inline-crypto-engine - qcom,sm8550-inline-crypto-engine - qcom,sm8650-inline-crypto-engine diff --git a/Bindings/crypto/qcom-qce.yaml b/Bindings/crypto/qcom-qce.yaml index a48bd381063..e285e382d4e 100644 --- a/Bindings/crypto/qcom-qce.yaml +++ b/Bindings/crypto/qcom-qce.yaml @@ -45,6 +45,7 @@ properties: - items: - enum: - qcom,sc7280-qce + - qcom,sm6350-qce - qcom,sm8250-qce - qcom,sm8350-qce - qcom,sm8450-qce diff --git a/Bindings/display/atmel/atmel,hlcdc-display-controller.yaml b/Bindings/display/atmel/atmel,hlcdc-display-controller.yaml new file mode 100644 index 00000000000..29ed42485de --- /dev/null +++ b/Bindings/display/atmel/atmel,hlcdc-display-controller.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/atmel/atmel,hlcdc-display-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel's High LCD Controller (HLCDC) + +maintainers: + - Nicolas Ferre + - Alexandre Belloni + - Claudiu Beznea + +description: + The LCD Controller (LCDC) consists of logic for transferring LCD image + data from an external display buffer to a TFT LCD panel. The LCDC has one + display input buffer per layer that fetches pixels through the single bus + host interface and a look-up table to allow palletized display + configurations. + +properties: + compatible: + const: atmel,hlcdc-display-controller + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Output endpoint of the controller, connecting the LCD panel signals. + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + reg: + maxItems: 1 + + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + description: + Endpoint connecting the LCD panel signals. + + properties: + bus-width: + enum: [ 12, 16, 18, 24 ] + +required: + - '#address-cells' + - '#size-cells' + - compatible + - port@0 + +additionalProperties: false diff --git a/Bindings/display/atmel/hlcdc-dc.txt b/Bindings/display/atmel/hlcdc-dc.txt deleted file mode 100644 index 923aea25344..00000000000 --- a/Bindings/display/atmel/hlcdc-dc.txt +++ /dev/null @@ -1,75 +0,0 @@ -Device-Tree bindings for Atmel's HLCDC (High LCD Controller) DRM driver - -The Atmel HLCDC Display Controller is subdevice of the HLCDC MFD device. -See ../../mfd/atmel-hlcdc.txt for more details. - -Required properties: - - compatible: value should be "atmel,hlcdc-display-controller" - - pinctrl-names: the pin control state names. Should contain "default". - - pinctrl-0: should contain the default pinctrl states. - - #address-cells: should be set to 1. - - #size-cells: should be set to 0. - -Required children nodes: - Children nodes are encoding available output ports and their connections - to external devices using the OF graph representation (see ../graph.txt). - At least one port node is required. - -Optional properties in grandchild nodes: - Any endpoint grandchild node may specify a desired video interface - according to ../../media/video-interfaces.txt, specifically - - bus-width: recognized values are <12>, <16>, <18> and <24>, and - override any output mode selection heuristic, forcing "rgb444", - "rgb565", "rgb666" and "rgb888" respectively. - -Example: - - hlcdc: hlcdc@f0030000 { - compatible = "atmel,sama5d3-hlcdc"; - reg = <0xf0030000 0x2000>; - interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; - clock-names = "periph_clk","sys_clk", "slow_clk"; - - hlcdc-display-controller { - compatible = "atmel,hlcdc-display-controller"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - hlcdc_panel_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwm>; - #pwm-cells = <3>; - }; - }; - -Example 2: With a video interface override to force rgb565; as above -but with these changes/additions: - - &hlcdc { - hlcdc-display-controller { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb565>; - - port@0 { - hlcdc_panel_output: endpoint@0 { - bus-width = <16>; - }; - }; - }; - }; diff --git a/Bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml b/Bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml new file mode 100644 index 00000000000..3791c9f4eba --- /dev/null +++ b/Bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8mp-hdmi-tx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8MP DWC HDMI TX Encoder + +maintainers: + - Lucas Stach + +description: + The i.MX8MP HDMI transmitter is a Synopsys DesignWare + HDMI 2.0a TX controller IP. + +allOf: + - $ref: /schemas/display/bridge/synopsys,dw-hdmi.yaml# + +properties: + compatible: + enum: + - fsl,imx8mp-hdmi-tx + + reg-io-width: + const: 1 + + clocks: + maxItems: 4 + + clock-names: + items: + - const: iahb + - const: isfr + - const: cec + - const: pix + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Parallel RGB input port + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: HDMI output port + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - power-domains + - ports + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + hdmi@32fd8000 { + compatible = "fsl,imx8mp-hdmi-tx"; + reg = <0x32fd8000 0x7eff>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_REF_266M>, + <&clk IMX8MP_CLK_32K>, + <&hdmi_tx_phy>; + clock-names = "iahb", "isfr", "cec", "pix"; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>; + reg-io-width = <1>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + + hdmi_tx_from_pvi: endpoint { + remote-endpoint = <&pvi_to_hdmi_tx>; + }; + }; + + port@1 { + reg = <1>; + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi0_con>; + }; + }; + }; + }; diff --git a/Bindings/display/bridge/ti,sn65dsi86.yaml b/Bindings/display/bridge/ti,sn65dsi86.yaml index 6ec6d287bff..c93878b6d71 100644 --- a/Bindings/display/bridge/ti,sn65dsi86.yaml +++ b/Bindings/display/bridge/ti,sn65dsi86.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: SN65DSI86 DSI to eDP bridge chip maintainers: - - Sandeep Panda + - Douglas Anderson description: | The Texas Instruments SN65DSI86 bridge takes MIPI DSI in and outputs eDP. diff --git a/Bindings/display/fsl,lcdif.yaml b/Bindings/display/fsl,lcdif.yaml index 1c2be8d6f63..0681fc49aa1 100644 --- a/Bindings/display/fsl,lcdif.yaml +++ b/Bindings/display/fsl,lcdif.yaml @@ -120,13 +120,19 @@ allOf: maxItems: 1 clock-names: maxItems: 1 + - if: + properties: + compatible: + const: fsl,imx6sx-lcdif + then: + required: + - power-domains - if: properties: compatible: contains: enum: - fsl,imx6sl-lcdif - - fsl,imx6sx-lcdif - fsl,imx8mm-lcdif - fsl,imx8mn-lcdif - fsl,imx8mp-lcdif diff --git a/Bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml b/Bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml new file mode 100644 index 00000000000..56da1636014 --- /dev/null +++ b/Bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx8mp-hdmi-pvi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8MP HDMI Parallel Video Interface + +maintainers: + - Lucas Stach + +description: + The HDMI parallel video interface is a timing and sync generator block in the + i.MX8MP SoC, that sits between the video source and the HDMI TX controller. + +properties: + compatible: + const: fsl,imx8mp-hdmi-pvi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input from the LCDIF controller. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Output to the HDMI TX controller. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - interrupts + - power-domains + - ports + +additionalProperties: false + +examples: + - | + #include + #include + + display-bridge@32fc4000 { + compatible = "fsl,imx8mp-hdmi-pvi"; + reg = <0x32fc4000 0x44>; + interrupt-parent = <&irqsteer_hdmi>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + pvi_from_lcdif3: endpoint { + remote-endpoint = <&lcdif3_to_pvi>; + }; + }; + + port@1 { + reg = <1>; + pvi_to_hdmi_tx: endpoint { + remote-endpoint = <&hdmi_tx_from_pvi>; + }; + }; + }; + }; diff --git a/Bindings/display/msm/dsi-controller-main.yaml b/Bindings/display/msm/dsi-controller-main.yaml index 4219936eda5..1fa28e97655 100644 --- a/Bindings/display/msm/dsi-controller-main.yaml +++ b/Bindings/display/msm/dsi-controller-main.yaml @@ -19,6 +19,7 @@ properties: - qcom,msm8916-dsi-ctrl - qcom,msm8953-dsi-ctrl - qcom,msm8974-dsi-ctrl + - qcom,msm8976-dsi-ctrl - qcom,msm8996-dsi-ctrl - qcom,msm8998-dsi-ctrl - qcom,qcm2290-dsi-ctrl @@ -248,6 +249,7 @@ allOf: contains: enum: - qcom,msm8953-dsi-ctrl + - qcom,msm8976-dsi-ctrl then: properties: clocks: diff --git a/Bindings/display/msm/gmu.yaml b/Bindings/display/msm/gmu.yaml index 4e1c25b4290..b3837368a26 100644 --- a/Bindings/display/msm/gmu.yaml +++ b/Bindings/display/msm/gmu.yaml @@ -224,6 +224,7 @@ allOf: enum: - qcom,adreno-gmu-730.1 - qcom,adreno-gmu-740.1 + - qcom,adreno-gmu-750.1 then: properties: reg: diff --git a/Bindings/display/msm/gpu.yaml b/Bindings/display/msm/gpu.yaml index b019db95479..40b5c6bd11f 100644 --- a/Bindings/display/msm/gpu.yaml +++ b/Bindings/display/msm/gpu.yaml @@ -23,7 +23,7 @@ properties: The driver is parsing the compat string for Adreno to figure out the gpu-id and patch level. items: - - pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]$' + - pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]+$' - const: qcom,adreno - description: | The driver is parsing the compat string for Imageon to @@ -127,7 +127,7 @@ allOf: properties: compatible: contains: - pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]$' + pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]+$' then: properties: @@ -203,7 +203,7 @@ allOf: properties: compatible: contains: - pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]$' + pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]+$' then: # Starting with A6xx, the clocks are usually defined in the GMU node properties: diff --git a/Bindings/display/msm/qcom,mdss.yaml b/Bindings/display/msm/qcom,mdss.yaml index 0999ea07f47..e4576546bf0 100644 --- a/Bindings/display/msm/qcom,mdss.yaml +++ b/Bindings/display/msm/qcom,mdss.yaml @@ -127,6 +127,7 @@ patternProperties: - qcom,dsi-phy-20nm - qcom,dsi-phy-28nm-8226 - qcom,dsi-phy-28nm-hpm + - qcom,dsi-phy-28nm-hpm-fam-b - qcom,dsi-phy-28nm-lp - qcom,hdmi-phy-8084 - qcom,hdmi-phy-8660 diff --git a/Bindings/display/msm/qcom,sm8150-mdss.yaml b/Bindings/display/msm/qcom,sm8150-mdss.yaml index c0d6a4fdff9..e6dc5494bae 100644 --- a/Bindings/display/msm/qcom,sm8150-mdss.yaml +++ b/Bindings/display/msm/qcom,sm8150-mdss.yaml @@ -53,6 +53,15 @@ patternProperties: compatible: const: qcom,sm8150-dpu + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + contains: + const: qcom,sm8150-dp + "^dsi@[0-9a-f]+$": type: object additionalProperties: true diff --git a/Bindings/display/msm/qcom,sm8650-dpu.yaml b/Bindings/display/msm/qcom,sm8650-dpu.yaml index a01d15a0331..c4087cc5abb 100644 --- a/Bindings/display/msm/qcom,sm8650-dpu.yaml +++ b/Bindings/display/msm/qcom,sm8650-dpu.yaml @@ -13,7 +13,9 @@ $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: - const: qcom,sm8650-dpu + enum: + - qcom,sm8650-dpu + - qcom,x1e80100-dpu reg: items: diff --git a/Bindings/display/msm/qcom,sm8650-mdss.yaml b/Bindings/display/msm/qcom,sm8650-mdss.yaml index bd11119dc93..24cece1e888 100644 --- a/Bindings/display/msm/qcom,sm8650-mdss.yaml +++ b/Bindings/display/msm/qcom,sm8650-mdss.yaml @@ -37,18 +37,21 @@ properties: patternProperties: "^display-controller@[0-9a-f]+$": type: object + additionalProperties: true properties: compatible: const: qcom,sm8650-dpu "^displayport-controller@[0-9a-f]+$": type: object + additionalProperties: true properties: compatible: const: qcom,sm8650-dp "^dsi@[0-9a-f]+$": type: object + additionalProperties: true properties: compatible: items: @@ -57,6 +60,7 @@ patternProperties: "^phy@[0-9a-f]+$": type: object + additionalProperties: true properties: compatible: const: qcom,sm8650-dsi-phy-4nm diff --git a/Bindings/display/msm/qcom,x1e80100-mdss.yaml b/Bindings/display/msm/qcom,x1e80100-mdss.yaml new file mode 100644 index 00000000000..3b01a0e4733 --- /dev/null +++ b/Bindings/display/msm/qcom,x1e80100-mdss.yaml @@ -0,0 +1,251 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,x1e80100-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm X1E80100 Display MDSS + +maintainers: + - Abel Vesa + +description: + X1E80100 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like + DPU display controller, DP interfaces, etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,x1e80100-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 3 + + interconnect-names: + maxItems: 3 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,x1e80100-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,x1e80100-dp + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,x1e80100-dp-phy + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + compatible = "qcom,x1e80100-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, + <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_DISPLAY_CFG 0>; + interconnect-names = "mdp0-mem", "mdp1-mem", "cpu-cfg"; + + resets = <&dispcc_core_bcr>; + + power-domains = <&dispcc_gdsc>; + + clocks = <&dispcc_ahb_clk>, + <&gcc_disp_hf_axi_clk>, + <&dispcc_mdp_clk>; + clock-names = "bus", "nrt_bus", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x1c00 0x2>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,x1e80100-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc_axi_clk>, + <&dispcc_ahb_clk>, + <&dispcc_mdp_lut_clk>, + <&dispcc_mdp_clk>, + <&dispcc_mdp_vsync_clk>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc_mdp_vsync_clk>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz = /bits/ 64 <514000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + displayport-controller@ae90000 { + compatible = "qcom,x1e80100-dp"; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0x600>, + <0 0xae91000 0 0x400>, + <0 0xae91400 0 0x400>; + + interrupt-parent = <&mdss>; + interrupts = <12>; + + clocks = <&dispcc_mdss_ahb_clk>, + <&dispcc_dptx0_aux_clk>, + <&dispcc_dptx0_link_clk>, + <&dispcc_dptx0_link_intf_clk>, + <&dispcc_dptx0_pixel0_clk>; + clock-names = "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>, + <&dispcc_mdss_dptx0_pixel0_clk_src>; + assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp0_in: endpoint { + remote-endpoint = <&mdss_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { + }; + }; + }; + + mdss_dp0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + }; +... diff --git a/Bindings/display/panel/boe,th101mb31ig002-28a.yaml b/Bindings/display/panel/boe,th101mb31ig002-28a.yaml new file mode 100644 index 00000000000..32df26cbfee --- /dev/null +++ b/Bindings/display/panel/boe,th101mb31ig002-28a.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/boe,th101mb31ig002-28a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: BOE TH101MB31IG002-28A WXGA DSI Display Panel + +maintainers: + - Manuel Traut + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + enum: + # BOE TH101MB31IG002-28A 10.1" WXGA TFT LCD panel + - boe,th101mb31ig002-28a + + reg: true + backlight: true + enable-gpios: true + power-supply: true + port: true + rotation: true + +required: + - compatible + - reg + - enable-gpios + - power-supply + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "boe,th101mb31ig002-28a"; + reg = <0>; + backlight = <&backlight_lcd0>; + enable-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>; + rotation = <90>; + power-supply = <&vcc_3v3>; + port { + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_con>; + }; + }; + }; + }; + +... diff --git a/Bindings/display/panel/himax,hx83112a.yaml b/Bindings/display/panel/himax,hx83112a.yaml new file mode 100644 index 00000000000..174661d1381 --- /dev/null +++ b/Bindings/display/panel/himax,hx83112a.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/himax,hx83112a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Himax HX83112A-based DSI display panels + +maintainers: + - Luca Weiss + +description: + The Himax HX83112A is a generic DSI Panel IC used to control + LCD panels. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + contains: + const: djn,9a-3r063-1102b + + vdd1-supply: + description: Digital voltage rail + + vsn-supply: + description: Positive source voltage rail + + vsp-supply: + description: Negative source voltage rail + + reg: true + port: true + +required: + - compatible + - reg + - reset-gpios + - vdd1-supply + - vsn-supply + - vsp-supply + - port + +unevaluatedProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "djn,9a-3r063-1102b"; + reg = <0>; + + backlight = <&pm6150l_wled>; + reset-gpios = <&pm6150l_gpios 9 GPIO_ACTIVE_LOW>; + + vdd1-supply = <&vreg_l1e>; + vsn-supply = <&pm6150l_lcdb_ncp>; + vsp-supply = <&pm6150l_lcdb_ldo>; + + port { + panel_in_0: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; + +... diff --git a/Bindings/display/panel/leadtek,ltk500hd1829.yaml b/Bindings/display/panel/leadtek,ltk500hd1829.yaml index c5944b4d636..d589f167721 100644 --- a/Bindings/display/panel/leadtek,ltk500hd1829.yaml +++ b/Bindings/display/panel/leadtek,ltk500hd1829.yaml @@ -14,7 +14,9 @@ allOf: properties: compatible: - const: leadtek,ltk500hd1829 + enum: + - leadtek,ltk101b4029w + - leadtek,ltk500hd1829 reg: true backlight: true reset-gpios: true diff --git a/Bindings/display/panel/novatek,nt35510.yaml b/Bindings/display/panel/novatek,nt35510.yaml index bc92928c805..91921f4b0e5 100644 --- a/Bindings/display/panel/novatek,nt35510.yaml +++ b/Bindings/display/panel/novatek,nt35510.yaml @@ -15,7 +15,9 @@ allOf: properties: compatible: items: - - const: hydis,hva40wv1 + - enum: + - frida,frd400b25025 + - hydis,hva40wv1 - const: novatek,nt35510 description: This indicates the panel manufacturer of the panel that is in turn using the NT35510 panel driver. The compatible @@ -29,6 +31,7 @@ properties: vddi-supply: description: regulator that supplies the vddi voltage backlight: true + port: true required: - compatible diff --git a/Bindings/display/panel/novatek,nt36672e.yaml b/Bindings/display/panel/novatek,nt36672e.yaml new file mode 100644 index 00000000000..dc4672f3d01 --- /dev/null +++ b/Bindings/display/panel/novatek,nt36672e.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/novatek,nt36672e.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Novatek NT36672E LCD DSI Panel + +maintainers: + - Ritesh Kumar + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: novatek,nt36672e + + reg: + maxItems: 1 + description: DSI virtual channel + + vddi-supply: true + avdd-supply: true + avee-supply: true + port: true + reset-gpios: true + backlight: true + +required: + - compatible + - reg + - vddi-supply + - avdd-supply + - avee-supply + - reset-gpios + - port + +additionalProperties: false + +examples: + - | + #include + dsi { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "novatek,nt36672e"; + reg = <0>; + + reset-gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>; + + vddi-supply = <&vreg_l8c_1p8>; + avdd-supply = <&disp_avdd>; + avee-supply = <&disp_avee>; + + backlight = <&pwm_backlight>; + + port { + panel0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; +... diff --git a/Bindings/display/panel/panel-lvds.yaml b/Bindings/display/panel/panel-lvds.yaml index 9f1016551e0..155d8ffa8f6 100644 --- a/Bindings/display/panel/panel-lvds.yaml +++ b/Bindings/display/panel/panel-lvds.yaml @@ -39,9 +39,13 @@ properties: compatible: items: - enum: + # Admatec 9904379 10.1" 1024x600 LVDS panel + - admatec,9904379 - auo,b101ew05 # Chunghwa Picture Tubes Ltd. 7" WXGA (800x1280) TFT LCD LVDS panel - chunghwa,claa070wp03xg + # EDT ETML0700Z9NDHA 7.0" WSVGA (1024x600) color TFT LCD LVDS panel + - edt,etml0700z9ndha # HannStar Display Corp. HSD101PWW2 10.1" WXGA (1280x800) LVDS panel - hannstar,hsd101pww2 # Hydis Technologies 7" WXGA (800x1280) TFT LCD LVDS panel diff --git a/Bindings/display/panel/panel-simple.yaml b/Bindings/display/panel/panel-simple.yaml index 634a10c6f2d..a95445f4087 100644 --- a/Bindings/display/panel/panel-simple.yaml +++ b/Bindings/display/panel/panel-simple.yaml @@ -73,6 +73,8 @@ properties: - auo,t215hvn01 # Shanghai AVIC Optoelectronics 7" 1024x600 color TFT-LCD panel - avic,tm070ddh03 + # BOE BP082WX1-100 8.2" WXGA (1280x800) LVDS panel + - boe,bp082wx1-100 # BOE BP101WX1-100 10.1" WXGA (1280x800) LVDS panel - boe,bp101wx1-100 # BOE EV121WXM-N10-1850 12.1" WXGA (1280x800) TFT LCD panel @@ -141,6 +143,8 @@ properties: - edt,etm0700g0edh6 # Emerging Display Technology Corp. LVDS WSVGA TFT Display with capacitive touch - edt,etml0700y5dha + # Emerging Display Technology Corp. 10.1" LVDS WXGA TFT Display with capacitive touch + - edt,etml1010g3dra # Emerging Display Technology Corp. 5.7" VGA TFT LCD panel with # capacitive touch - edt,etmv570g2dhu diff --git a/Bindings/display/panel/rocktech,jh057n00900.yaml b/Bindings/display/panel/rocktech,jh057n00900.yaml index 97cccd8a847..6ec471284f9 100644 --- a/Bindings/display/panel/rocktech,jh057n00900.yaml +++ b/Bindings/display/panel/rocktech,jh057n00900.yaml @@ -22,6 +22,8 @@ properties: enum: # Anberic RG353V-V2 5.0" 640x480 TFT LCD panel - anbernic,rg353v-panel-v2 + # Powkiddy RGB10MAX3 5.0" 720x1280 TFT LCD panel + - powkiddy,rgb10max3-panel # Powkiddy RGB30 3.0" 720x720 TFT LCD panel - powkiddy,rgb30-panel # Rocktech JH057N00900 5.5" 720x1440 TFT LCD panel @@ -43,6 +45,7 @@ properties: reset-gpios: true backlight: true + rotation: true required: - compatible diff --git a/Bindings/display/panel/visionox,r66451.yaml b/Bindings/display/panel/visionox,r66451.yaml index 6ba32368392..187840bb76c 100644 --- a/Bindings/display/panel/visionox,r66451.yaml +++ b/Bindings/display/panel/visionox,r66451.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/display/panel/visionox,r66451.yaml# diff --git a/Bindings/display/panel/visionox,rm69299.yaml b/Bindings/display/panel/visionox,rm69299.yaml index fa745a6f445..77239906751 100644 --- a/Bindings/display/panel/visionox,rm69299.yaml +++ b/Bindings/display/panel/visionox,rm69299.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Visionox model RM69299 Panels maintainers: - - Harigovindan P + - Abhinav Kumar + - Jessica Zhang description: | This binding is for display panels using a Visionox RM692999 panel. diff --git a/Bindings/display/renesas,rzg2l-du.yaml b/Bindings/display/renesas,rzg2l-du.yaml new file mode 100644 index 00000000000..08e5b947805 --- /dev/null +++ b/Bindings/display/renesas,rzg2l-du.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/renesas,rzg2l-du.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G2L Display Unit (DU) + +maintainers: + - Biju Das + - Laurent Pinchart + +description: | + These DT bindings describe the Display Unit embedded in the Renesas RZ/G2L + and RZ/V2L SoCs. + +properties: + compatible: + oneOf: + - enum: + - renesas,r9a07g044-du # RZ/G2{L,LC} + - items: + - enum: + - renesas,r9a07g054-du # RZ/V2L + - const: renesas,r9a07g044-du # RZ/G2L fallback + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Main clock + - description: Register access clock + - description: Video clock + + clock-names: + items: + - const: aclk + - const: pclk + - const: vclk + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + The connections to the DU output video ports are modeled using the OF + graph bindings. The number of ports and their assignment are + model-dependent. Each port shall have a single endpoint. + + patternProperties: + "^port@[0-1]$": + $ref: /schemas/graph.yaml#/properties/port + unevaluatedProperties: false + + required: + - port@0 + + unevaluatedProperties: false + + renesas,vsps: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle to VSP instance that serves the DU channel + - description: Channel index identifying the LIF instance in that VSP + description: + A list of phandle and channel index tuples to the VSPs that handle the + memory interfaces for the DU channels. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - power-domains + - ports + - renesas,vsps + +additionalProperties: false + +examples: + # RZ/G2L DU + - | + #include + #include + + display@10890000 { + compatible = "renesas,r9a07g044-du"; + reg = <0x10890000 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + resets = <&cpg R9A07G044_LCDC_RESET_N>; + power-domains = <&cpg>; + + renesas,vsps = <&vspd0 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + port@1 { + reg = <1>; + }; + }; + }; + +... diff --git a/Bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Bindings/display/rockchip/rockchip,dw-hdmi.yaml index 7e59dee15a5..af638b6c0d2 100644 --- a/Bindings/display/rockchip/rockchip,dw-hdmi.yaml +++ b/Bindings/display/rockchip/rockchip,dw-hdmi.yaml @@ -94,11 +94,14 @@ properties: - const: default - const: unwedge + power-domains: + maxItems: 1 + ports: $ref: /schemas/graph.yaml#/properties/ports - patternProperties: - "^port(@0)?$": + properties: + port@0: $ref: /schemas/graph.yaml#/properties/port description: Input of the DWC HDMI TX properties: @@ -108,11 +111,14 @@ properties: description: Connection to the VOPB endpoint@1: description: Connection to the VOPL - properties: port@1: $ref: /schemas/graph.yaml#/properties/port description: Output of the DWC HDMI TX + required: + - port@0 + - port@1 + rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -135,19 +141,25 @@ examples: #include #include #include + #include hdmi: hdmi@ff980000 { compatible = "rockchip,rk3288-dw-hdmi"; reg = <0xff980000 0x20000>; reg-io-width = <4>; - ddc-i2c-bus = <&i2c5>; - rockchip,grf = <&grf>; interrupts = ; clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; clock-names = "iahb", "isfr"; + ddc-i2c-bus = <&i2c5>; + power-domains = <&power RK3288_PD_VIO>; + rockchip,grf = <&grf>; ports { - port { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; #address-cells = <1>; #size-cells = <0>; @@ -155,11 +167,20 @@ examples: reg = <0>; remote-endpoint = <&vopb_out_hdmi>; }; + hdmi_in_vopl: endpoint@1 { reg = <1>; remote-endpoint = <&vopl_out_hdmi>; }; }; + + port@1 { + reg = <1>; + + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; }; }; diff --git a/Bindings/display/solomon,ssd1307fb.yaml b/Bindings/display/solomon,ssd1307fb.yaml index 3afbb52d1b7..153ff86fb40 100644 --- a/Bindings/display/solomon,ssd1307fb.yaml +++ b/Bindings/display/solomon,ssd1307fb.yaml @@ -131,9 +131,9 @@ allOf: const: sinowealth,sh1106 then: properties: - width: + solomon,width: default: 132 - height: + solomon,height: default: 64 solomon,dclk-div: default: 1 @@ -149,9 +149,9 @@ allOf: - solomon,ssd1305 then: properties: - width: + solomon,width: default: 132 - height: + solomon,height: default: 64 solomon,dclk-div: default: 1 @@ -167,9 +167,9 @@ allOf: - solomon,ssd1306 then: properties: - width: + solomon,width: default: 128 - height: + solomon,height: default: 64 solomon,dclk-div: default: 1 @@ -185,9 +185,9 @@ allOf: - solomon,ssd1307 then: properties: - width: + solomon,width: default: 128 - height: + solomon,height: default: 39 solomon,dclk-div: default: 2 @@ -205,9 +205,9 @@ allOf: - solomon,ssd1309 then: properties: - width: + solomon,width: default: 128 - height: + solomon,height: default: 64 solomon,dclk-div: default: 1 diff --git a/Bindings/display/solomon,ssd132x.yaml b/Bindings/display/solomon,ssd132x.yaml index 37975ee61c5..dd7939989cf 100644 --- a/Bindings/display/solomon,ssd132x.yaml +++ b/Bindings/display/solomon,ssd132x.yaml @@ -30,9 +30,9 @@ allOf: const: solomon,ssd1322 then: properties: - width: + solomon,width: default: 480 - height: + solomon,height: default: 128 - if: @@ -42,9 +42,9 @@ allOf: const: solomon,ssd1325 then: properties: - width: + solomon,width: default: 128 - height: + solomon,height: default: 80 - if: @@ -54,9 +54,9 @@ allOf: const: solomon,ssd1327 then: properties: - width: + solomon,width: default: 128 - height: + solomon,height: default: 128 unevaluatedProperties: false diff --git a/Bindings/display/solomon,ssd133x.yaml b/Bindings/display/solomon,ssd133x.yaml new file mode 100644 index 00000000000..b7780038a34 --- /dev/null +++ b/Bindings/display/solomon,ssd133x.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/solomon,ssd133x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Solomon SSD133x OLED Display Controllers + +maintainers: + - Javier Martinez Canillas + +allOf: + - $ref: solomon,ssd-common.yaml# + +properties: + compatible: + enum: + - solomon,ssd1331 + + solomon,width: + default: 96 + + solomon,height: + default: 64 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + oled@0 { + compatible = "solomon,ssd1331"; + reg = <0x0>; + reset-gpios = <&gpio2 7>; + dc-gpios = <&gpio2 8>; + spi-max-frequency = <10000000>; + }; + }; diff --git a/Bindings/display/ti/ti,am65x-dss.yaml b/Bindings/display/ti/ti,am65x-dss.yaml index b6767ef0d24..55e3e490d0e 100644 --- a/Bindings/display/ti/ti,am65x-dss.yaml +++ b/Bindings/display/ti/ti,am65x-dss.yaml @@ -37,6 +37,7 @@ properties: - description: OVR2 overlay manager for vp2 - description: VP1 video port 1 - description: VP2 video port 2 + - description: common1 DSS register area reg-names: items: @@ -47,6 +48,7 @@ properties: - const: ovr2 - const: vp1 - const: vp2 + - const: common1 clocks: items: @@ -147,9 +149,10 @@ examples: <0x04a07000 0x1000>, /* ovr1 */ <0x04a08000 0x1000>, /* ovr2 */ <0x04a0a000 0x1000>, /* vp1 */ - <0x04a0b000 0x1000>; /* vp2 */ + <0x04a0b000 0x1000>, /* vp2 */ + <0x04a01000 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 67 1>, diff --git a/Bindings/dma/allwinner,sun50i-a64-dma.yaml b/Bindings/dma/allwinner,sun50i-a64-dma.yaml index ec2d7a789ff..0f2501f72cc 100644 --- a/Bindings/dma/allwinner,sun50i-a64-dma.yaml +++ b/Bindings/dma/allwinner,sun50i-a64-dma.yaml @@ -28,6 +28,9 @@ properties: - items: - const: allwinner,sun8i-r40-dma - const: allwinner,sun50i-a64-dma + - items: + - const: allwinner,sun50i-h616-dma + - const: allwinner,sun50i-a100-dma reg: maxItems: 1 @@ -59,10 +62,11 @@ required: if: properties: compatible: - enum: - - allwinner,sun20i-d1-dma - - allwinner,sun50i-a100-dma - - allwinner,sun50i-h6-dma + contains: + enum: + - allwinner,sun20i-d1-dma + - allwinner,sun50i-a100-dma + - allwinner,sun50i-h6-dma then: properties: diff --git a/Bindings/dma/fsl,edma.yaml b/Bindings/dma/fsl,edma.yaml index 437db0c6233..aa51d278cb6 100644 --- a/Bindings/dma/fsl,edma.yaml +++ b/Bindings/dma/fsl,edma.yaml @@ -25,6 +25,7 @@ properties: - fsl,imx8qm-edma - fsl,imx93-edma3 - fsl,imx93-edma4 + - fsl,imx95-edma5 - items: - const: fsl,ls1028a-edma - const: fsl,vf610-edma @@ -83,6 +84,7 @@ allOf: - fsl,imx8qm-edma - fsl,imx93-edma3 - fsl,imx93-edma4 + - fsl,imx95-edma5 then: properties: "#dma-cells": diff --git a/Bindings/dma/fsl,imx-sdma.yaml b/Bindings/dma/fsl,imx-sdma.yaml index b95dd8db5a3..37135fa024f 100644 --- a/Bindings/dma/fsl,imx-sdma.yaml +++ b/Bindings/dma/fsl,imx-sdma.yaml @@ -92,7 +92,8 @@ properties: description: needs firmware more than ver 2 - Shared ASRC: 23 - SAI: 24 - - HDMI Audio: 25 + - Multi SAI: 25 + - HDMI Audio: 26 The third cell: transfer priority ID enum: diff --git a/Bindings/dma/marvell,mmp-dma.yaml b/Bindings/dma/marvell,mmp-dma.yaml new file mode 100644 index 00000000000..d447d5207be --- /dev/null +++ b/Bindings/dma/marvell,mmp-dma.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/marvell,mmp-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell MMP DMA controller + +maintainers: + - Duje Mihanović + +description: + Marvell MMP SoCs may have two types of DMA controllers, peripheral and audio. + +properties: + compatible: + enum: + - marvell,pdma-1.0 + - marvell,adma-1.0 + - marvell,pxa910-squ + + reg: + maxItems: 1 + + interrupts: + description: + Interrupt lines for the controller, may be shared or one per DMA channel + minItems: 1 + + asram: + description: + A phandle to the SRAM pool + $ref: /schemas/types.yaml#/definitions/phandle + + '#dma-channels': + deprecated: true + + '#dma-requests': + deprecated: true + +required: + - compatible + - reg + - interrupts + - '#dma-cells' + +allOf: + - $ref: dma-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - marvell,pdma-1.0 + then: + properties: + asram: false + else: + required: + - asram + +unevaluatedProperties: false + +examples: + - | + dma-controller@d4000000 { + compatible = "marvell,pdma-1.0"; + reg = <0xd4000000 0x10000>; + interrupts = <47>; + #dma-cells = <2>; + dma-channels = <16>; + }; diff --git a/Bindings/dma/mediatek,mt7622-hsdma.yaml b/Bindings/dma/mediatek,mt7622-hsdma.yaml new file mode 100644 index 00000000000..3f1e120e40a --- /dev/null +++ b/Bindings/dma/mediatek,mt7622-hsdma.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/mediatek,mt7622-hsdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek High-Speed DMA Controller + +maintainers: + - Sean Wang + +allOf: + - $ref: dma-controller.yaml# + +properties: + compatible: + enum: + - mediatek,mt7622-hsdma + - mediatek,mt7623-hsdma + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: hsdma + + power-domains: + maxItems: 1 + + "#dma-cells": + description: Channel number + const: 1 + +required: + - reg + - interrupts + - clocks + - clock-names + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + dma-controller@1b007000 { + compatible = "mediatek,mt7623-hsdma"; + reg = <0x1b007000 0x1000>; + interrupts = ; + clocks = <ðsys CLK_ETHSYS_HSDMA>; + clock-names = "hsdma"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; + #dma-cells = <1>; + }; diff --git a/Bindings/dma/mmp-dma.txt b/Bindings/dma/mmp-dma.txt deleted file mode 100644 index ec18bf0a802..00000000000 --- a/Bindings/dma/mmp-dma.txt +++ /dev/null @@ -1,81 +0,0 @@ -* MARVELL MMP DMA controller - -Marvell Peripheral DMA Controller -Used platforms: pxa688, pxa910, pxa3xx, etc - -Required properties: -- compatible: Should be "marvell,pdma-1.0" -- reg: Should contain DMA registers location and length. -- interrupts: Either contain all of the per-channel DMA interrupts - or one irq for pdma device - -Optional properties: -- dma-channels: Number of DMA channels supported by the controller (defaults - to 32 when not specified) -- #dma-channels: deprecated -- dma-requests: Number of DMA requestor lines supported by the controller - (defaults to 32 when not specified) -- #dma-requests: deprecated - -"marvell,pdma-1.0" -Used platforms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688. - -Examples: - -/* - * Each channel has specific irq - * ICU parse out irq channel from ICU register, - * while DMA controller may not able to distinguish the irq channel - * Using this method, interrupt-parent is required as demuxer - * For example, pxa688 icu register 0x128, bit 0~15 is PDMA channel irq, - * 18~21 is ADMA irq - */ -pdma: dma-controller@d4000000 { - compatible = "marvell,pdma-1.0"; - reg = <0xd4000000 0x10000>; - interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; - interrupt-parent = <&intcmux32>; - dma-channels = <16>; - }; - -/* - * One irq for all channels - * Dmaengine driver (DMA controller) distinguish irq channel via - * parsing internal register - */ -pdma: dma-controller@d4000000 { - compatible = "marvell,pdma-1.0"; - reg = <0xd4000000 0x10000>; - interrupts = <47>; - dma-channels = <16>; - }; - - -Marvell Two Channel DMA Controller used specifically for audio -Used platforms: pxa688, pxa910 - -Required properties: -- compatible: Should be "marvell,adma-1.0" or "marvell,pxa910-squ" -- reg: Should contain DMA registers location and length. -- interrupts: Either contain all of the per-channel DMA interrupts - or one irq for dma device - -"marvell,adma-1.0" used on pxa688 -"marvell,pxa910-squ" used on pxa910 - -Examples: - -/* each channel has specific irq */ -adma0: dma-controller@d42a0800 { - compatible = "marvell,adma-1.0"; - reg = <0xd42a0800 0x100>; - interrupts = <18 19>; - interrupt-parent = <&intcmux32>; - }; - -/* One irq for all channels */ -squ: dma-controller@d42a0800 { - compatible = "marvell,pxa910-squ"; - reg = <0xd42a0800 0x100>; - interrupts = <46>; - }; diff --git a/Bindings/dma/mtk-hsdma.txt b/Bindings/dma/mtk-hsdma.txt deleted file mode 100644 index 4bb317359dc..00000000000 --- a/Bindings/dma/mtk-hsdma.txt +++ /dev/null @@ -1,33 +0,0 @@ -MediaTek High-Speed DMA Controller -================================== - -This device follows the generic DMA bindings defined in dma/dma.txt. - -Required properties: - -- compatible: Must be one of - "mediatek,mt7622-hsdma": for MT7622 SoC - "mediatek,mt7623-hsdma": for MT7623 SoC -- reg: Should contain the register's base address and length. -- interrupts: Should contain a reference to the interrupt used by this - device. -- clocks: Should be the clock specifiers corresponding to the entry in - clock-names property. -- clock-names: Should contain "hsdma" entries. -- power-domains: Phandle to the power domain that the device is part of -- #dma-cells: The length of the DMA specifier, must be <1>. This one cell - in dmas property of a client device represents the channel - number. -Example: - - hsdma: dma-controller@1b007000 { - compatible = "mediatek,mt7623-hsdma"; - reg = <0 0x1b007000 0 0x1000>; - interrupts = ; - clocks = <ðsys CLK_ETHSYS_HSDMA>; - clock-names = "hsdma"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; - #dma-cells = <1>; - }; - -DMA clients must use the format described in dma/dma.txt file. diff --git a/Bindings/dma/renesas,rcar-dmac.yaml b/Bindings/dma/renesas,rcar-dmac.yaml index 03aa067b122..04fc4a99a7c 100644 --- a/Bindings/dma/renesas,rcar-dmac.yaml +++ b/Bindings/dma/renesas,rcar-dmac.yaml @@ -46,6 +46,7 @@ properties: - renesas,dmac-r8a779a0 # R-Car V3U - renesas,dmac-r8a779f0 # R-Car S4-8 - renesas,dmac-r8a779g0 # R-Car V4H + - renesas,dmac-r8a779h0 # R-Car V4M - const: renesas,rcar-gen4-dmac # R-Car Gen4 reg: true diff --git a/Bindings/dts-coding-style.rst b/Bindings/dts-coding-style.rst index a9bdd2b59dc..8a68331075a 100644 --- a/Bindings/dts-coding-style.rst +++ b/Bindings/dts-coding-style.rst @@ -144,6 +144,8 @@ Example:: #dma-cells = <1>; clocks = <&clock_controller 0>, <&clock_controller 1>; clock-names = "bus", "host"; + #address-cells = <1>; + #size-cells = <1>; vendor,custom-property = <2>; status = "disabled"; diff --git a/Bindings/eeprom/at24.yaml b/Bindings/eeprom/at24.yaml index 1812ef31d5f..3c36cd0510d 100644 --- a/Bindings/eeprom/at24.yaml +++ b/Bindings/eeprom/at24.yaml @@ -68,14 +68,10 @@ properties: pattern: cs16$ - items: pattern: c32$ - - items: - pattern: c32d-wl$ - items: pattern: cs32$ - items: pattern: c64$ - - items: - pattern: c64d-wl$ - items: pattern: cs64$ - items: @@ -136,6 +132,7 @@ properties: - renesas,r1ex24128 - samsung,s524ad0xd1 - const: atmel,24c128 + - pattern: '^atmel,24c(32|64)d-wl$' # Actual vendor is st label: description: Descriptive name of the EEPROM. diff --git a/Bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml index 8e584857ddd..ab8f32c440d 100644 --- a/Bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml +++ b/Bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml @@ -26,6 +26,12 @@ properties: - description: For implementations complying for Versal. const: xlnx,versal-firmware + - description: For implementations complying for Versal NET. + items: + - enum: + - xlnx,versal-net-firmware + - const: xlnx,versal-firmware + method: description: | The method of calling the PM-API firmware layer. @@ -41,7 +47,53 @@ properties: "#power-domain-cells": const: 1 - versal_fpga: + clock-controller: + $ref: /schemas/clock/xlnx,versal-clk.yaml# + description: The clock controller is a hardware block of Xilinx versal + clock tree. It reads required input clock frequencies from the devicetree + and acts as clock provider for all clock consumers of PS clocks.list of + clock specifiers which are external input clocks to the given clock + controller. + type: object + + gpio: + $ref: /schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml# + description: The gpio node describes connect to PS_MODE pins via firmware + interface. + type: object + + soc-nvmem: + $ref: /schemas/nvmem/xlnx,zynqmp-nvmem.yaml# + description: The ZynqMP MPSoC provides access to the hardware related data + like SOC revision, IDCODE and specific purpose efuses. + type: object + + pcap: + $ref: /schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml + description: The ZynqMP SoC uses the PCAP (Processor Configuration Port) to + configure the Programmable Logic (PL). The configuration uses the + firmware interface. + type: object + + pinctrl: + $ref: /schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml# + description: The pinctrl node provides access to pinconfig and pincontrol + functionality available in firmware. + type: object + + power-management: + $ref: /schemas/power/reset/xlnx,zynqmp-power.yaml# + description: The zynqmp-power node describes the power management + configurations. It will control remote suspend/shutdown interfaces. + type: object + + reset-controller: + $ref: /schemas/reset/xlnx,zynqmp-reset.yaml# + description: The reset-controller node describes connection to the reset + functionality via firmware interface. + type: object + + versal-fpga: $ref: /schemas/fpga/xlnx,versal-fpga.yaml# description: Compatible of the FPGA device. type: object @@ -53,15 +105,6 @@ properties: vector. type: object - clock-controller: - $ref: /schemas/clock/xlnx,versal-clk.yaml# - description: The clock controller is a hardware block of Xilinx versal - clock tree. It reads required input clock frequencies from the devicetree - and acts as clock provider for all clock consumers of PS clocks.list of - clock specifiers which are external input clocks to the given clock - controller. - type: object - required: - compatible @@ -73,7 +116,38 @@ examples: firmware { zynqmp_firmware: zynqmp-firmware { #power-domain-cells = <1>; + soc-nvmem { + compatible = "xlnx,zynqmp-nvmem-fw"; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + soc_revision: soc-revision@0 { + reg = <0x0 0x4>; + }; + }; }; + gpio { + compatible = "xlnx,zynqmp-gpio-modepin"; + gpio-controller; + #gpio-cells = <2>; + }; + pcap { + compatible = "xlnx,zynqmp-pcap-fpga"; + }; + pinctrl { + compatible = "xlnx,zynqmp-pinctrl"; + }; + power-management { + compatible = "xlnx,zynqmp-power"; + interrupts = <0 35 4>; + }; + reset-controller { + compatible = "xlnx,zynqmp-reset"; + #reset-cells = <1>; + }; + }; }; sata { @@ -84,7 +158,7 @@ examples: compatible = "xlnx,versal-firmware"; method = "smc"; - versal_fpga: versal_fpga { + versal_fpga: versal-fpga { compatible = "xlnx,versal-fpga"; }; diff --git a/Bindings/fpga/fpga-region.txt b/Bindings/fpga/fpga-region.txt deleted file mode 100644 index 528df8a0e6d..00000000000 --- a/Bindings/fpga/fpga-region.txt +++ /dev/null @@ -1,479 +0,0 @@ -FPGA Region Device Tree Binding - -Alan Tull 2016 - - CONTENTS - - Introduction - - Terminology - - Sequence - - FPGA Region - - Supported Use Models - - Device Tree Examples - - Constraints - - -Introduction -============ - -FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in -the Device Tree. FPGA Regions provide a way to program FPGAs under device tree -control. - -This device tree binding document hits some of the high points of FPGA usage and -attempts to include terminology used by both major FPGA manufacturers. This -document isn't a replacement for any manufacturers specifications for FPGA -usage. - - -Terminology -=========== - -Full Reconfiguration - * The entire FPGA is programmed. - -Partial Reconfiguration (PR) - * A section of an FPGA is reprogrammed while the rest of the FPGA is not - affected. - * Not all FPGA's support PR. - -Partial Reconfiguration Region (PRR) - * Also called a "reconfigurable partition" - * A PRR is a specific section of an FPGA reserved for reconfiguration. - * A base (or static) FPGA image may create a set of PRR's that later may - be independently reprogrammed many times. - * The size and specific location of each PRR is fixed. - * The connections at the edge of each PRR are fixed. The image that is loaded - into a PRR must fit and must use a subset of the region's connections. - * The busses within the FPGA are split such that each region gets its own - branch that may be gated independently. - -Persona - * Also called a "partial bit stream" - * An FPGA image that is designed to be loaded into a PRR. There may be - any number of personas designed to fit into a PRR, but only one at at time - may be loaded. - * A persona may create more regions. - -FPGA Bridge - * FPGA Bridges gate bus signals between a host and FPGA. - * FPGA Bridges should be disabled while the FPGA is being programmed to - prevent spurious signals on the cpu bus and to the soft logic. - * FPGA bridges may be actual hardware or soft logic on an FPGA. - * During Full Reconfiguration, hardware bridges between the host and FPGA - will be disabled. - * During Partial Reconfiguration of a specific region, that region's bridge - will be used to gate the busses. Traffic to other regions is not affected. - * In some implementations, the FPGA Manager transparently handles gating the - buses, eliminating the need to show the hardware FPGA bridges in the - device tree. - * An FPGA image may create a set of reprogrammable regions, each having its - own bridge and its own split of the busses in the FPGA. - -FPGA Manager - * An FPGA Manager is a hardware block that programs an FPGA under the control - of a host processor. - -Base Image - * Also called the "static image" - * An FPGA image that is designed to do full reconfiguration of the FPGA. - * A base image may set up a set of partial reconfiguration regions that may - later be reprogrammed. - - ---------------- ---------------------------------- - | Host CPU | | FPGA | - | | | | - | ----| | ----------- -------- | - | | H | | |==>| Bridge0 |<==>| PRR0 | | - | | W | | | ----------- -------- | - | | | | | | - | | B |<=====>|<==| ----------- -------- | - | | R | | |==>| Bridge1 |<==>| PRR1 | | - | | I | | | ----------- -------- | - | | D | | | | - | | G | | | ----------- -------- | - | | E | | |==>| Bridge2 |<==>| PRR2 | | - | ----| | ----------- -------- | - | | | | - ---------------- ---------------------------------- - -Figure 1: An FPGA set up with a base image that created three regions. Each -region (PRR0-2) gets its own split of the busses that is independently gated by -a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be -reprogrammed independently while the rest of the system continues to function. - - -Sequence -======== - -When a DT overlay that targets an FPGA Region is applied, the FPGA Region will -do the following: - - 1. Disable appropriate FPGA bridges. - 2. Program the FPGA using the FPGA manager. - 3. Enable the FPGA bridges. - 4. The Device Tree overlay is accepted into the live tree. - 5. Child devices are populated. - -When the overlay is removed, the child nodes will be removed and the FPGA Region -will disable the bridges. - - -FPGA Region -=========== - -FPGA Regions represent FPGA's and FPGA PR regions in the device tree. An FPGA -Region brings together the elements needed to program on a running system and -add the child devices: - - * FPGA Manager - * FPGA Bridges - * image-specific information needed to to the programming. - * child nodes - -The intended use is that a Device Tree overlay (DTO) can be used to reprogram an -FPGA while an operating system is running. - -An FPGA Region that exists in the live Device Tree reflects the current state. -If the live tree shows a "firmware-name" property or child nodes under an FPGA -Region, the FPGA already has been programmed. A DTO that targets an FPGA Region -and adds the "firmware-name" property is taken as a request to reprogram the -FPGA. After reprogramming is successful, the overlay is accepted into the live -tree. - -The base FPGA Region in the device tree represents the FPGA and supports full -reconfiguration. It must include a phandle to an FPGA Manager. The base -FPGA region will be the child of one of the hardware bridges (the bridge that -allows register access) between the cpu and the FPGA. If there are more than -one bridge to control during FPGA programming, the region will also contain a -list of phandles to the additional hardware FPGA Bridges. - -For partial reconfiguration (PR), each PR region will have an FPGA Region. -These FPGA regions are children of FPGA bridges which are then children of the -base FPGA region. The "Full Reconfiguration to add PRR's" example below shows -this. - -If an FPGA Region does not specify an FPGA Manager, it will inherit the FPGA -Manager specified by its ancestor FPGA Region. This supports both the case -where the same FPGA Manager is used for all of an FPGA as well the case where -a different FPGA Manager is used for each region. - -FPGA Regions do not inherit their ancestor FPGA regions' bridges. This prevents -shutting down bridges that are upstream from the other active regions while one -region is getting reconfigured (see Figure 1 above). During PR, the FPGA's -hardware bridges remain enabled. The PR regions' bridges will be FPGA bridges -within the static image of the FPGA. - -Required properties: -- compatible : should contain "fpga-region" -- fpga-mgr : should contain a phandle to an FPGA Manager. Child FPGA Regions - inherit this property from their ancestor regions. An fpga-mgr property - in a region will override any inherited FPGA manager. -- #address-cells, #size-cells, ranges : must be present to handle address space - mapping for child nodes. - -Optional properties: -- firmware-name : should contain the name of an FPGA image file located on the - firmware search path. If this property shows up in a live device tree - it indicates that the FPGA has already been programmed with this image. - If this property is in an overlay targeting an FPGA region, it is a - request to program the FPGA with that image. -- fpga-bridges : should contain a list of phandles to FPGA Bridges that must be - controlled during FPGA programming along with the parent FPGA bridge. - This property is optional if the FPGA Manager handles the bridges. - If the fpga-region is the child of an fpga-bridge, the list should not - contain the parent bridge. -- partial-fpga-config : boolean, set if partial reconfiguration is to be done, - otherwise full reconfiguration is done. -- external-fpga-config : boolean, set if the FPGA has already been configured - prior to OS boot up. -- encrypted-fpga-config : boolean, set if the bitstream is encrypted -- region-unfreeze-timeout-us : The maximum time in microseconds to wait for - bridges to successfully become enabled after the region has been - programmed. -- region-freeze-timeout-us : The maximum time in microseconds to wait for - bridges to successfully become disabled before the region has been - programmed. -- config-complete-timeout-us : The maximum time in microseconds time for the - FPGA to go to operating mode after the region has been programmed. -- child nodes : devices in the FPGA after programming. - -In the example below, when an overlay is applied targeting fpga-region0, -fpga_mgr is used to program the FPGA. Two bridges are controlled during -programming: the parent fpga_bridge0 and fpga_bridge1. Because the region is -the child of fpga_bridge0, only fpga_bridge1 needs to be specified in the -fpga-bridges property. During programming, these bridges are disabled, the -firmware specified in the overlay is loaded to the FPGA using the FPGA manager -specified in the region. If FPGA programming succeeds, the bridges are -reenabled and the overlay makes it into the live device tree. The child devices -are then populated. If FPGA programming fails, the bridges are left disabled -and the overlay is rejected. The overlay's ranges property maps the lwhps -bridge's region (0xff200000) and the hps bridge's region (0xc0000000) for use by -the two child devices. - -Example: -Base tree contains: - - fpga_mgr: fpga-mgr@ff706000 { - compatible = "altr,socfpga-fpga-mgr"; - reg = <0xff706000 0x1000 - 0xffb90000 0x20>; - interrupts = <0 175 4>; - }; - - fpga_bridge0: fpga-bridge@ff400000 { - compatible = "altr,socfpga-lwhps2fpga-bridge"; - reg = <0xff400000 0x100000>; - resets = <&rst LWHPS2FPGA_RESET>; - clocks = <&l4_main_clk>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - fpga_region0: fpga-region0 { - compatible = "fpga-region"; - fpga-mgr = <&fpga_mgr>; - }; - }; - - fpga_bridge1: fpga-bridge@ff500000 { - compatible = "altr,socfpga-hps2fpga-bridge"; - reg = <0xff500000 0x10000>; - resets = <&rst HPS2FPGA_RESET>; - clocks = <&l4_main_clk>; - }; - -Overlay contains: - -/dts-v1/; -/plugin/; - -&fpga_region0 { - #address-cells = <1>; - #size-cells = <1>; - - firmware-name = "soc_system.rbf"; - fpga-bridges = <&fpga_bridge1>; - ranges = <0x20000 0xff200000 0x100000>, - <0x0 0xc0000000 0x20000000>; - - gpio@10040 { - compatible = "altr,pio-1.0"; - reg = <0x10040 0x20>; - altr,ngpio = <4>; - #gpio-cells = <2>; - clocks = <2>; - gpio-controller; - }; - - onchip-memory { - device_type = "memory"; - compatible = "altr,onchipmem-15.1"; - reg = <0x0 0x10000>; - }; -}; - - -Supported Use Models -==================== - -In all cases the live DT must have the FPGA Manager, FPGA Bridges (if any), and -a FPGA Region. The target of the Device Tree Overlay is the FPGA Region. Some -uses are specific to an FPGA device. - - * No FPGA Bridges - In this case, the FPGA Manager which programs the FPGA also handles the - bridges behind the scenes. No FPGA Bridge devices are needed for full - reconfiguration. - - * Full reconfiguration with hardware bridges - In this case, there are hardware bridges between the processor and FPGA that - need to be controlled during full reconfiguration. Before the overlay is - applied, the live DT must include the FPGA Manager, FPGA Bridges, and a - FPGA Region. The FPGA Region is the child of the bridge that allows - register access to the FPGA. Additional bridges may be listed in a - fpga-bridges property in the FPGA region or in the device tree overlay. - - * Partial reconfiguration with bridges in the FPGA - In this case, the FPGA will have one or more PRR's that may be programmed - separately while the rest of the FPGA can remain active. To manage this, - bridges need to exist in the FPGA that can gate the buses going to each FPGA - region while the buses are enabled for other sections. Before any partial - reconfiguration can be done, a base FPGA image must be loaded which includes - PRR's with FPGA bridges. The device tree should have an FPGA region for each - PRR. - -Device Tree Examples -==================== - -The intention of this section is to give some simple examples, focusing on -the placement of the elements detailed above, especially: - * FPGA Manager - * FPGA Bridges - * FPGA Region - * ranges - * target-path or target - -For the purposes of this section, I'm dividing the Device Tree into two parts, -each with its own requirements. The two parts are: - * The live DT prior to the overlay being added - * The DT overlay - -The live Device Tree must contain an FPGA Region, an FPGA Manager, and any FPGA -Bridges. The FPGA Region's "fpga-mgr" property specifies the manager by phandle -to handle programming the FPGA. If the FPGA Region is the child of another FPGA -Region, the parent's FPGA Manager is used. If FPGA Bridges need to be involved, -they are specified in the FPGA Region by the "fpga-bridges" property. During -FPGA programming, the FPGA Region will disable the bridges that are in its -"fpga-bridges" list and will re-enable them after FPGA programming has -succeeded. - -The Device Tree Overlay will contain: - * "target-path" or "target" - The insertion point where the contents of the overlay will go into the - live tree. target-path is a full path, while target is a phandle. - * "ranges" - The address space mapping from processor to FPGA bus(ses). - * "firmware-name" - Specifies the name of the FPGA image file on the firmware search - path. The search path is described in the firmware class documentation. - * "partial-fpga-config" - This binding is a boolean and should be present if partial reconfiguration - is to be done. - * child nodes corresponding to hardware that will be loaded in this region of - the FPGA. - -Device Tree Example: Full Reconfiguration without Bridges -========================================================= - -Live Device Tree contains: - fpga_mgr0: fpga-mgr@f8007000 { - compatible = "xlnx,zynq-devcfg-1.0"; - reg = <0xf8007000 0x100>; - interrupt-parent = <&intc>; - interrupts = <0 8 4>; - clocks = <&clkc 12>; - clock-names = "ref_clk"; - syscon = <&slcr>; - }; - - fpga_region0: fpga-region0 { - compatible = "fpga-region"; - fpga-mgr = <&fpga_mgr0>; - #address-cells = <0x1>; - #size-cells = <0x1>; - ranges; - }; - -DT Overlay contains: - -/dts-v1/; -/plugin/; - -&fpga_region0 { - #address-cells = <1>; - #size-cells = <1>; - - firmware-name = "zynq-gpio.bin"; - - gpio1: gpio@40000000 { - compatible = "xlnx,xps-gpio-1.00.a"; - reg = <0x40000000 0x10000>; - gpio-controller; - #gpio-cells = <0x2>; - xlnx,gpio-width= <0x6>; - }; -}; - -Device Tree Example: Full Reconfiguration to add PRR's -====================================================== - -The base FPGA Region is specified similar to the first example above. - -This example programs the FPGA to have two regions that can later be partially -configured. Each region has its own bridge in the FPGA fabric. - -DT Overlay contains: - -/dts-v1/; -/plugin/; - -&fpga_region0 { - #address-cells = <1>; - #size-cells = <1>; - - firmware-name = "base.rbf"; - - fpga-bridge@4400 { - compatible = "altr,freeze-bridge-controller"; - reg = <0x4400 0x10>; - - fpga_region1: fpga-region1 { - compatible = "fpga-region"; - #address-cells = <0x1>; - #size-cells = <0x1>; - ranges; - }; - }; - - fpga-bridge@4420 { - compatible = "altr,freeze-bridge-controller"; - reg = <0x4420 0x10>; - - fpga_region2: fpga-region2 { - compatible = "fpga-region"; - #address-cells = <0x1>; - #size-cells = <0x1>; - ranges; - }; - }; -}; - -Device Tree Example: Partial Reconfiguration -============================================ - -This example reprograms one of the PRR's set up in the previous example. - -The sequence that occurs when this overlay is similar to the above, the only -differences are that the FPGA is partially reconfigured due to the -"partial-fpga-config" boolean and the only bridge that is controlled during -programming is the FPGA based bridge of fpga_region1. - -/dts-v1/; -/plugin/; - -&fpga_region1 { - #address-cells = <1>; - #size-cells = <1>; - - firmware-name = "soc_image2.rbf"; - partial-fpga-config; - - gpio@10040 { - compatible = "altr,pio-1.0"; - reg = <0x10040 0x20>; - clocks = <0x2>; - altr,ngpio = <0x4>; - #gpio-cells = <0x2>; - gpio-controller; - }; -}; - -Constraints -=========== - -It is beyond the scope of this document to fully describe all the FPGA design -constraints required to make partial reconfiguration work[1] [2] [3], but a few -deserve quick mention. - -A persona must have boundary connections that line up with those of the partition -or region it is designed to go into. - -During programming, transactions through those connections must be stopped and -the connections must be held at a fixed logic level. This can be achieved by -FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration. - --- -[1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf -[2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf -[3] https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf diff --git a/Bindings/fpga/fpga-region.yaml b/Bindings/fpga/fpga-region.yaml new file mode 100644 index 00000000000..77554885a6c --- /dev/null +++ b/Bindings/fpga/fpga-region.yaml @@ -0,0 +1,358 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/fpga-region.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FPGA Region + +maintainers: + - Michal Simek + +description: | + CONTENTS + - Introduction + - Terminology + - Sequence + - FPGA Region + - Supported Use Models + - Constraints + + + Introduction + ============ + + FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in + the Device Tree. FPGA Regions provide a way to program FPGAs under device tree + control. + + The documentation hits some of the high points of FPGA usage and + attempts to include terminology used by both major FPGA manufacturers. This + document isn't a replacement for any manufacturers specifications for FPGA + usage. + + + Terminology + =========== + + Full Reconfiguration + * The entire FPGA is programmed. + + Partial Reconfiguration (PR) + * A section of an FPGA is reprogrammed while the rest of the FPGA is not + affected. + * Not all FPGA's support PR. + + Partial Reconfiguration Region (PRR) + * Also called a "reconfigurable partition" + * A PRR is a specific section of an FPGA reserved for reconfiguration. + * A base (or static) FPGA image may create a set of PRR's that later may + be independently reprogrammed many times. + * The size and specific location of each PRR is fixed. + * The connections at the edge of each PRR are fixed. The image that is loaded + into a PRR must fit and must use a subset of the region's connections. + * The busses within the FPGA are split such that each region gets its own + branch that may be gated independently. + + Persona + * Also called a "partial bit stream" + * An FPGA image that is designed to be loaded into a PRR. There may be + any number of personas designed to fit into a PRR, but only one at a time + may be loaded. + * A persona may create more regions. + + FPGA Bridge + * FPGA Bridges gate bus signals between a host and FPGA. + * FPGA Bridges should be disabled while the FPGA is being programmed to + prevent spurious signals on the cpu bus and to the soft logic. + * FPGA bridges may be actual hardware or soft logic on an FPGA. + * During Full Reconfiguration, hardware bridges between the host and FPGA + will be disabled. + * During Partial Reconfiguration of a specific region, that region's bridge + will be used to gate the busses. Traffic to other regions is not affected. + * In some implementations, the FPGA Manager transparently handles gating the + buses, eliminating the need to show the hardware FPGA bridges in the + device tree. + * An FPGA image may create a set of reprogrammable regions, each having its + own bridge and its own split of the busses in the FPGA. + + FPGA Manager + * An FPGA Manager is a hardware block that programs an FPGA under the control + of a host processor. + + Base Image + * Also called the "static image" + * An FPGA image that is designed to do full reconfiguration of the FPGA. + * A base image may set up a set of partial reconfiguration regions that may + later be reprogrammed. + + ---------------- ---------------------------------- + | Host CPU | | FPGA | + | | | | + | ----| | ----------- -------- | + | | H | | |==>| Bridge0 |<==>| PRR0 | | + | | W | | | ----------- -------- | + | | | | | | + | | B |<=====>|<==| ----------- -------- | + | | R | | |==>| Bridge1 |<==>| PRR1 | | + | | I | | | ----------- -------- | + | | D | | | | + | | G | | | ----------- -------- | + | | E | | |==>| Bridge2 |<==>| PRR2 | | + | ----| | ----------- -------- | + | | | | + ---------------- ---------------------------------- + + Figure 1: An FPGA set up with a base image that created three regions. Each + region (PRR0-2) gets its own split of the busses that is independently gated by + a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be + reprogrammed independently while the rest of the system continues to function. + + + Sequence + ======== + + When a DT overlay that targets an FPGA Region is applied, the FPGA Region will + do the following: + + 1. Disable appropriate FPGA bridges. + 2. Program the FPGA using the FPGA manager. + 3. Enable the FPGA bridges. + 4. The Device Tree overlay is accepted into the live tree. + 5. Child devices are populated. + + When the overlay is removed, the child nodes will be removed and the FPGA Region + will disable the bridges. + + + FPGA Region + =========== + + FPGA Regions represent FPGA's and FPGA PR regions in the device tree. An FPGA + Region brings together the elements needed to program on a running system and + add the child devices: + + * FPGA Manager + * FPGA Bridges + * image-specific information needed to the programming. + * child nodes + + The intended use is that a Device Tree overlay (DTO) can be used to reprogram an + FPGA while an operating system is running. + + An FPGA Region that exists in the live Device Tree reflects the current state. + If the live tree shows a "firmware-name" property or child nodes under an FPGA + Region, the FPGA already has been programmed. A DTO that targets an FPGA Region + and adds the "firmware-name" property is taken as a request to reprogram the + FPGA. After reprogramming is successful, the overlay is accepted into the live + tree. + + The base FPGA Region in the device tree represents the FPGA and supports full + reconfiguration. It must include a phandle to an FPGA Manager. The base + FPGA region will be the child of one of the hardware bridges (the bridge that + allows register access) between the cpu and the FPGA. If there are more than + one bridge to control during FPGA programming, the region will also contain a + list of phandles to the additional hardware FPGA Bridges. + + For partial reconfiguration (PR), each PR region will have an FPGA Region. + These FPGA regions are children of FPGA bridges which are then children of the + base FPGA region. The "Full Reconfiguration to add PRR's" example below shows + this. + + If an FPGA Region does not specify an FPGA Manager, it will inherit the FPGA + Manager specified by its ancestor FPGA Region. This supports both the case + where the same FPGA Manager is used for all of an FPGA as well the case where + a different FPGA Manager is used for each region. + + FPGA Regions do not inherit their ancestor FPGA regions' bridges. This prevents + shutting down bridges that are upstream from the other active regions while one + region is getting reconfigured (see Figure 1 above). During PR, the FPGA's + hardware bridges remain enabled. The PR regions' bridges will be FPGA bridges + within the static image of the FPGA. + + + Supported Use Models + ==================== + + In all cases the live DT must have the FPGA Manager, FPGA Bridges (if any), and + a FPGA Region. The target of the Device Tree Overlay is the FPGA Region. Some + uses are specific to an FPGA device. + + * No FPGA Bridges + In this case, the FPGA Manager which programs the FPGA also handles the + bridges behind the scenes. No FPGA Bridge devices are needed for full + reconfiguration. + + * Full reconfiguration with hardware bridges + In this case, there are hardware bridges between the processor and FPGA that + need to be controlled during full reconfiguration. Before the overlay is + applied, the live DT must include the FPGA Manager, FPGA Bridges, and a + FPGA Region. The FPGA Region is the child of the bridge that allows + register access to the FPGA. Additional bridges may be listed in a + fpga-bridges property in the FPGA region or in the device tree overlay. + + * Partial reconfiguration with bridges in the FPGA + In this case, the FPGA will have one or more PRR's that may be programmed + separately while the rest of the FPGA can remain active. To manage this, + bridges need to exist in the FPGA that can gate the buses going to each FPGA + region while the buses are enabled for other sections. Before any partial + reconfiguration can be done, a base FPGA image must be loaded which includes + PRR's with FPGA bridges. The device tree should have an FPGA region for each + PRR. + + Constraints + =========== + + It is beyond the scope of this document to fully describe all the FPGA design + constraints required to make partial reconfiguration work[1] [2] [3], but a few + deserve quick mention. + + A persona must have boundary connections that line up with those of the partition + or region it is designed to go into. + + During programming, transactions through those connections must be stopped and + the connections must be held at a fixed logic level. This can be achieved by + FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration. + + -- + [1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf + [2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf + [3] https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf + +properties: + $nodename: + pattern: "^fpga-region(@.*|-([0-9]|[1-9][0-9]+))?$" + + compatible: + const: fpga-region + + reg: + maxItems: 1 + + ranges: true + "#address-cells": true + "#size-cells": true + + config-complete-timeout-us: + description: + The maximum time in microseconds time for the FPGA to go to operating + mode after the region has been programmed. + + encrypted-fpga-config: + type: boolean + description: + Set if the bitstream is encrypted. + + external-fpga-config: + type: boolean + description: + Set if the FPGA has already been configured prior to OS boot up. + + firmware-name: + maxItems: 1 + description: + Should contain the name of an FPGA image file located on the firmware + search path. If this property shows up in a live device tree it indicates + that the FPGA has already been programmed with this image. + If this property is in an overlay targeting an FPGA region, it is + a request to program the FPGA with that image. + + fpga-bridges: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Should contain a list of phandles to FPGA Bridges that must be + controlled during FPGA programming along with the parent FPGA bridge. + This property is optional if the FPGA Manager handles the bridges. + If the fpga-region is the child of an fpga-bridge, the list should not + contain the parent bridge. + + fpga-mgr: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Should contain a phandle to an FPGA Manager. Child FPGA Regions + inherit this property from their ancestor regions. An fpga-mgr property + in a region will override any inherited FPGA manager. + + partial-fpga-config: + type: boolean + description: + Set if partial reconfiguration is to be done, otherwise full + reconfiguration is done. + + region-freeze-timeout-us: + description: + The maximum time in microseconds to wait for bridges to successfully + become disabled before the region has been programmed. + + region-unfreeze-timeout-us: + description: + The maximum time in microseconds to wait for bridges to successfully + become enabled after the region has been programmed. + +required: + - compatible + - fpga-mgr + +additionalProperties: + type: object + +examples: + - | + /* + * Full Reconfiguration without Bridges with DT overlay + */ + fpga_region0: fpga-region@0 { + compatible = "fpga-region"; + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + fpga-mgr = <&fpga_mgr0>; + ranges = <0x10000000 0x20000000 0x10000000>; + + /* DT Overlay contains: &fpga_region0 */ + firmware-name = "zynq-gpio.bin"; + gpio@40000000 { + compatible = "xlnx,xps-gpio-1.00.a"; + reg = <0x40000000 0x10000>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + - | + /* + * Partial reconfiguration with bridge + */ + fpga_region1: fpga-region@0 { + compatible = "fpga-region"; + reg = <0 0>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + fpga-mgr = <&fpga_mgr1>; + fpga-bridges = <&fpga_bridge1>; + partial-fpga-config; + + /* DT Overlay contains: &fpga_region1 */ + firmware-name = "zynq-gpio-partial.bin"; + clk: clock { + compatible = "fixed-factor-clock"; + clocks = <&parentclk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + axi { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + gpio@40000000 { + compatible = "xlnx,xps-gpio-1.00.a"; + reg = <0x40000000 0x10000>; + #gpio-cells = <2>; + gpio-controller; + clocks = <&clk>; + }; + }; + }; diff --git a/Bindings/fpga/xlnx,versal-fpga.yaml b/Bindings/fpga/xlnx,versal-fpga.yaml index 26f18834caa..80833462f62 100644 --- a/Bindings/fpga/xlnx,versal-fpga.yaml +++ b/Bindings/fpga/xlnx,versal-fpga.yaml @@ -26,7 +26,7 @@ additionalProperties: false examples: - | - versal_fpga: versal_fpga { + versal_fpga: versal-fpga { compatible = "xlnx,versal-fpga"; }; diff --git a/Bindings/gpio/aspeed,ast2400-gpio.yaml b/Bindings/gpio/aspeed,ast2400-gpio.yaml new file mode 100644 index 00000000000..cf11aa7ec8c --- /dev/null +++ b/Bindings/gpio/aspeed,ast2400-gpio.yaml @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/aspeed,ast2400-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed GPIO controller + +maintainers: + - Andrew Jeffery + +properties: + compatible: + enum: + - aspeed,ast2400-gpio + - aspeed,ast2500-gpio + - aspeed,ast2600-gpio + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + description: The clock to use for debounce timings + + gpio-controller: true + gpio-line-names: + minItems: 36 + maxItems: 232 + + gpio-ranges: true + + "#gpio-cells": + const: 2 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + ngpios: + minimum: 36 + maximum: 232 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - "#interrupt-cells" + - gpio-controller + - "#gpio-cells" + +allOf: + - if: + properties: + compatible: + contains: + const: aspeed,ast2400-gpio + then: + properties: + gpio-line-names: + minItems: 220 + maxItems: 220 + ngpios: + const: 220 + - if: + properties: + compatible: + contains: + const: aspeed,ast2500-gpio + then: + properties: + gpio-line-names: + minItems: 232 + maxItems: 232 + ngpios: + const: 232 + - if: + properties: + compatible: + contains: + const: aspeed,ast2600-gpio + then: + properties: + gpio-line-names: + minItems: 36 + maxItems: 208 + ngpios: + enum: [ 36, 208 ] + required: + - ngpios + +additionalProperties: false + +examples: + - | + gpio@1e780000 { + compatible = "aspeed,ast2400-gpio"; + reg = <0x1e780000 0x1000>; + interrupts = <20>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + - | + gpio: gpio@1e780000 { + compatible = "aspeed,ast2500-gpio"; + reg = <0x1e780000 0x200>; + interrupts = <20>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 232>; + }; + - | + #include + #include + #include + gpio0: gpio@1e780000 { + compatible = "aspeed,ast2600-gpio"; + reg = <0x1e780000 0x400>; + clocks = <&syscon ASPEED_CLK_APB2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 208>; + ngpios = <208>; + }; + gpio1: gpio@1e780800 { + compatible = "aspeed,ast2600-gpio"; + reg = <0x1e780800 0x800>; + clocks = <&syscon ASPEED_CLK_APB1>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 208 36>; + ngpios = <36>; + }; diff --git a/Bindings/gpio/gateworks,pld-gpio.txt b/Bindings/gpio/gateworks,pld-gpio.txt index 6e81f8b755c..d543fd1b8b2 100644 --- a/Bindings/gpio/gateworks,pld-gpio.txt +++ b/Bindings/gpio/gateworks,pld-gpio.txt @@ -1,7 +1,6 @@ Gateworks PLD GPIO controller bindings -The GPIO controller should be a child node on an I2C bus, -see: i2c/i2c.txt for details. +The GPIO controller should be a child node on an I2C bus. Required properties: - compatible: Should be "gateworks,pld-gpio" diff --git a/Bindings/gpio/gpio-aspeed.txt b/Bindings/gpio/gpio-aspeed.txt deleted file mode 100644 index b2033fc3a71..00000000000 --- a/Bindings/gpio/gpio-aspeed.txt +++ /dev/null @@ -1,39 +0,0 @@ -Aspeed GPIO controller Device Tree Bindings -------------------------------------------- - -Required properties: -- compatible : Either "aspeed,ast2400-gpio", "aspeed,ast2500-gpio", - or "aspeed,ast2600-gpio". - -- #gpio-cells : Should be two - - First cell is the GPIO line number - - Second cell is used to specify optional - parameters (unused) - -- reg : Address and length of the register set for the device -- gpio-controller : Marks the device node as a GPIO controller. -- interrupts : Interrupt specifier (see interrupt bindings for - details) -- interrupt-controller : Mark the GPIO controller as an interrupt-controller - -Optional properties: - -- clocks : A phandle to the clock to use for debounce timings -- ngpios : Number of GPIOs controlled by this controller. Should be set - when there are multiple GPIO controllers on a SoC (ast2600). - -The gpio and interrupt properties are further described in their respective -bindings documentation: - -- Documentation/devicetree/bindings/gpio/gpio.txt -- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt - - Example: - gpio@1e780000 { - #gpio-cells = <2>; - compatible = "aspeed,ast2400-gpio"; - gpio-controller; - interrupts = <20>; - reg = <0x1e780000 0x1000>; - interrupt-controller; - }; diff --git a/Bindings/gpio/gpio-mvebu.yaml b/Bindings/gpio/gpio-mvebu.yaml index f1bd1e6b2e1..33d4e471651 100644 --- a/Bindings/gpio/gpio-mvebu.yaml +++ b/Bindings/gpio/gpio-mvebu.yaml @@ -115,7 +115,7 @@ allOf: required: - reg -unevaluatedProperties: true +unevaluatedProperties: false examples: - | diff --git a/Bindings/gpio/gpio-nmk.txt b/Bindings/gpio/gpio-nmk.txt deleted file mode 100644 index 8315ac7780e..00000000000 --- a/Bindings/gpio/gpio-nmk.txt +++ /dev/null @@ -1,31 +0,0 @@ -Nomadik GPIO controller - -Required properties: -- compatible : Should be "st,nomadik-gpio". -- reg : Physical base address and length of the controller's registers. -- interrupts : The interrupt outputs from the controller. -- #gpio-cells : Should be two: - The first cell is the pin number. - The second cell is used to specify optional parameters: - - bits[3:0] trigger type and level flags: - 1 = low-to-high edge triggered. - 2 = high-to-low edge triggered. - 4 = active high level-sensitive. - 8 = active low level-sensitive. -- gpio-controller : Marks the device node as a GPIO controller. -- interrupt-controller : Marks the device node as an interrupt controller. -- gpio-bank : Specifies which bank a controller owns. -- st,supports-sleepmode : Specifies whether controller can sleep or not - -Example: - - gpio1: gpio@8012e080 { - compatible = "st,nomadik-gpio"; - reg = <0x8012e080 0x80>; - interrupts = <0 120 0x4>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - st,supports-sleepmode; - gpio-bank = <1>; - }; diff --git a/Bindings/gpio/gpio-pca9570.yaml b/Bindings/gpio/gpio-pca9570.yaml index 452f8972a96..6f73961001b 100644 --- a/Bindings/gpio/gpio-pca9570.yaml +++ b/Bindings/gpio/gpio-pca9570.yaml @@ -28,6 +28,9 @@ properties: minItems: 4 maxItems: 8 + label: + description: A descriptive name for this device. + required: - compatible - reg diff --git a/Bindings/gpio/mrvl-gpio.yaml b/Bindings/gpio/mrvl-gpio.yaml index 9cf6137dd52..65155bb701a 100644 --- a/Bindings/gpio/mrvl-gpio.yaml +++ b/Bindings/gpio/mrvl-gpio.yaml @@ -9,7 +9,7 @@ title: Marvell PXA GPIO controller maintainers: - Linus Walleij - Bartosz Golaszewski - - Rob Herring + - Rob Herring allOf: - if: diff --git a/Bindings/gpio/renesas,rcar-gpio.yaml b/Bindings/gpio/renesas,rcar-gpio.yaml index aa424e2b95f..cc7a950a603 100644 --- a/Bindings/gpio/renesas,rcar-gpio.yaml +++ b/Bindings/gpio/renesas,rcar-gpio.yaml @@ -53,6 +53,7 @@ properties: - renesas,gpio-r8a779a0 # R-Car V3U - renesas,gpio-r8a779f0 # R-Car S4-8 - renesas,gpio-r8a779g0 # R-Car V4H + - renesas,gpio-r8a779h0 # R-Car V4M - const: renesas,rcar-gen4-gpio # R-Car Gen4 reg: diff --git a/Bindings/gpio/st,nomadik-gpio.yaml b/Bindings/gpio/st,nomadik-gpio.yaml new file mode 100644 index 00000000000..38d37d8f720 --- /dev/null +++ b/Bindings/gpio/st,nomadik-gpio.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/st,nomadik-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nomadik GPIO controller + +description: + The Nomadik GPIO driver handles Nomadik SoC GPIO blocks. This block has also + been called ST STA2X11. On the Nomadik platform, this driver is intertwined + with pinctrl-nomadik. + +maintainers: + - Linus Walleij + +properties: + $nodename: + pattern: "^gpio@[0-9a-f]+$" + + compatible: + enum: + - st,nomadik-gpio + - mobileye,eyeq5-gpio + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#gpio-cells": + const: 2 + + gpio-controller: true + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + gpio-bank: + description: System-wide GPIO bank index. + $ref: /schemas/types.yaml#/definitions/uint32 + + st,supports-sleepmode: + description: Whether the controller can sleep or not. + $ref: /schemas/types.yaml#/definitions/flag + + clocks: + maxItems: 1 + + gpio-ranges: + maxItems: 1 + + ngpios: + minimum: 0 + maximum: 32 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - "#gpio-cells" + - gpio-controller + - interrupt-controller + - gpio-bank + +unevaluatedProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: mobileye,eyeq5-gpio + then: + properties: + st,supports-sleepmode: false + +examples: + - | + gpio@8012e080 { + compatible = "st,nomadik-gpio"; + reg = <0x8012e080 0x80>; + interrupts = <0 120 0x4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + st,supports-sleepmode; + gpio-bank = <1>; + }; diff --git a/Bindings/gpu/img,powervr.yaml b/Bindings/gpu/img,powervr-rogue.yaml similarity index 91% rename from Bindings/gpu/img,powervr.yaml rename to Bindings/gpu/img,powervr-rogue.yaml index a13298f1a18..256e252f808 100644 --- a/Bindings/gpu/img,powervr.yaml +++ b/Bindings/gpu/img,powervr-rogue.yaml @@ -2,10 +2,10 @@ # Copyright (c) 2023 Imagination Technologies Ltd. %YAML 1.2 --- -$id: http://devicetree.org/schemas/gpu/img,powervr.yaml# +$id: http://devicetree.org/schemas/gpu/img,powervr-rogue.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Imagination Technologies PowerVR and IMG GPU +title: Imagination Technologies PowerVR and IMG Rogue GPUs maintainers: - Frank Binns diff --git a/Bindings/gpu/img,powervr-sgx.yaml b/Bindings/gpu/img,powervr-sgx.yaml new file mode 100644 index 00000000000..f5898b04381 --- /dev/null +++ b/Bindings/gpu/img,powervr-sgx.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2023 Imagination Technologies Ltd. +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/img,powervr-sgx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Imagination Technologies PowerVR SGX GPUs + +maintainers: + - Frank Binns + +properties: + compatible: + oneOf: + - items: + - enum: + - ti,omap3430-gpu # Rev 121 + - ti,omap3630-gpu # Rev 125 + - const: img,powervr-sgx530 + - items: + - enum: + - ingenic,jz4780-gpu # Rev 130 + - ti,omap4430-gpu # Rev 120 + - const: img,powervr-sgx540 + - items: + - enum: + - allwinner,sun6i-a31-gpu # MP2 Rev 115 + - ti,omap4470-gpu # MP1 Rev 112 + - ti,omap5432-gpu # MP2 Rev 105 + - ti,am5728-gpu # MP2 Rev 116 + - ti,am6548-gpu # MP1 Rev 117 + - const: img,powervr-sgx544 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 3 + + clock-names: + minItems: 1 + items: + - const: core + - const: mem + - const: sys + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +allOf: + - if: + properties: + compatible: + contains: + const: ti,am6548-gpu + then: + required: + - power-domains + else: + properties: + power-domains: false + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun6i-a31-gpu + - ingenic,jz4780-gpu + then: + required: + - clocks + - clock-names + else: + properties: + clocks: false + clock-names: false + - if: + properties: + compatible: + contains: + const: allwinner,sun6i-a31-gpu + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + minItems: 2 + maxItems: 2 + - if: + properties: + compatible: + contains: + const: ingenic,jz4780-gpu + then: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + +additionalProperties: false + +examples: + - | + #include + #include + #include + + gpu@7000000 { + compatible = "ti,am6548-gpu", "img,powervr-sgx544"; + reg = <0x7000000 0x10000>; + interrupts = ; + power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; + }; + + - | + #include + #include + + gpu: gpu@1c40000 { + compatible = "allwinner,sun6i-a31-gpu", "img,powervr-sgx544"; + reg = <0x01c40000 0x10000>; + interrupts = ; + clocks = <&ccu 1>, <&ccu 2>; + clock-names = "core", "mem"; + }; diff --git a/Bindings/hwmon/adi,adm1177.yaml b/Bindings/hwmon/adi,adm1177.yaml index 2e45364d054..be7e9e91a3a 100644 --- a/Bindings/hwmon/adi,adm1177.yaml +++ b/Bindings/hwmon/adi,adm1177.yaml @@ -46,7 +46,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: hwmon-common.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Bindings/hwmon/adi,adm1275.yaml b/Bindings/hwmon/adi,adm1275.yaml index ab87f51c5ae..b6806129496 100644 --- a/Bindings/hwmon/adi,adm1275.yaml +++ b/Bindings/hwmon/adi,adm1275.yaml @@ -33,10 +33,6 @@ properties: reg: maxItems: 1 - shunt-resistor-micro-ohms: - description: - Shunt resistor value in micro-Ohm. - adi,volt-curr-sample-average: description: | Number of samples to be used to report voltage and current values. @@ -50,6 +46,7 @@ properties: enum: [1, 2, 4, 8, 16, 32, 64, 128] allOf: + - $ref: hwmon-common.yaml# - if: properties: compatible: @@ -107,7 +104,7 @@ required: - compatible - reg -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Bindings/hwmon/adi,ltc2945.yaml b/Bindings/hwmon/adi,ltc2945.yaml index 5cb66e97e81..6401b0a9aff 100644 --- a/Bindings/hwmon/adi,ltc2945.yaml +++ b/Bindings/hwmon/adi,ltc2945.yaml @@ -31,7 +31,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: hwmon-common.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Bindings/hwmon/adi,ltc4282.yaml b/Bindings/hwmon/adi,ltc4282.yaml new file mode 100644 index 00000000000..4854b95a93e --- /dev/null +++ b/Bindings/hwmon/adi,ltc4282.yaml @@ -0,0 +1,159 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/adi,ltc4282.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices LTC4282 I2C High Current Hot Swap Controller over I2C + +maintainers: + - Nuno Sa + +description: | + Analog Devices LTC4282 I2C High Current Hot Swap Controller over I2C. + + https://www.analog.com/media/en/technical-documentation/data-sheets/ltc4282.pdf + +properties: + compatible: + enum: + - adi,ltc4282 + + reg: + maxItems: 1 + + vdd-supply: true + + clocks: + maxItems: 1 + + '#clock-cells': + const: 0 + + adi,rsense-nano-ohms: + description: Value of the sense resistor. + + adi,vin-mode-microvolt: + description: + Selects operating range for the Undervoltage, Overvoltage and Foldback + pins. Also for the ADC. Should be set to the nominal input voltage. + enum: [3300000, 5000000, 12000000, 24000000] + default: 12000000 + + adi,fet-bad-timeout-ms: + description: + From the moment a FET bad conditions is present, this property selects the + wait time/timeout for a FET-bad fault to be signaled. Setting this to 0, + disables FET bad faults to be reported. + default: 255 + maximum: 255 + + adi,overvoltage-dividers: + description: | + Select which dividers to use for VDD Overvoltage detection. Note that + when the internal dividers are used the threshold is referenced to VDD. + The percentages in the datasheet are misleading since the actual values + to look for are in the "Absolute Maximum Ratings" table in the + "Comparator Inputs" section. In there there's a line for each of the 5%, + 10% and 15% settings with the actual min, typical and max tolerances. + $ref: /schemas/types.yaml#/definitions/string + enum: [external, vdd_5_percent, vdd_10_percent, vdd_15_percent] + default: external + + adi,undervoltage-dividers: + description: | + Select which dividers to use for VDD Overvoltage detection. Note that + when the internal dividers are used the threshold is referenced to VDD. + The percentages in the datasheet are misleading since the actual values + to look for are in the "Absolute Maximum Ratings" table in the + "Comparator Inputs" section. In there there's a line for each of the 5%, + 10% and 15% settings with the actual min, typical and max tolerances. + $ref: /schemas/types.yaml#/definitions/string + enum: [external, vdd_5_percent, vdd_10_percent, vdd_15_percent] + default: external + + adi,current-limit-sense-microvolt: + description: + The current limit sense voltage of the chip is adjustable between + 12.5mV and 34.4mV in 3.1mV steps. This effectively limits the current + on the load. + enum: [12500, 15625, 18750, 21875, 25000, 28125, 31250, 34375] + default: 25000 + + adi,overcurrent-retry: + description: + If set, enables the chip to auto-retry 256 timer cycles after an + Overcurrent fault. + type: boolean + + adi,overvoltage-retry-disable: + description: + If set, disables the chip to auto-retry 50ms after an Overvoltage fault. + It's enabled by default. + type: boolean + + adi,undervoltage-retry-disable: + description: + If set, disables the chip to auto-retry 50ms after an Undervoltage fault. + It's enabled by default. + type: boolean + + adi,fault-log-enable: + description: + If set, enables the FAULT_LOG and ADC_ALERT_LOG registers to be written + to the EEPROM when a fault bit transitions high and hence, will be + available after a power cycle (the chip loads the contents of + the EE_FAULT_LOG register - the one in EEPROM - into FAULT_LOG at boot). + type: boolean + + adi,gpio1-mode: + description: Defines the function of the Pin. It can indicate that power is + good (PULL the pin low when power is not good) or that power is bad (Go + into high-z when power is not good). + $ref: /schemas/types.yaml#/definitions/string + enum: [power_bad, power_good] + default: power_good + + adi,gpio2-mode: + description: Defines the function of the Pin. It can be set as the input for + the ADC or indicating that the MOSFET is in stress (dissipating power). + $ref: /schemas/types.yaml#/definitions/string + enum: [adc_input, stress_fet] + default: adc_input + + adi,gpio3-monitor-enable: + description: If set, gpio3 is set as input for the ADC instead of gpio2. + type: boolean + +allOf: + - if: + required: + - adi,gpio3-monitor-enable + then: + properties: + adi,gpio2-mode: + const: stress_fet + +required: + - compatible + - reg + - adi,rsense-nano-ohms + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + hwmon@50 { + compatible = "adi,ltc4282"; + reg = <0x50>; + adi,rsense-nano-ohms = <500>; + + adi,gpio1-mode = "power_good"; + adi,gpio2-mode = "adc_input"; + }; + }; +... diff --git a/Bindings/hwmon/amphenol,chipcap2.yaml b/Bindings/hwmon/amphenol,chipcap2.yaml new file mode 100644 index 00000000000..17351fdbefc --- /dev/null +++ b/Bindings/hwmon/amphenol,chipcap2.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/amphenol,chipcap2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ChipCap 2 humidity and temperature iio sensor + +maintainers: + - Javier Carrasco + +description: | + Relative humidity and temperature sensor on I2C bus. + + Datasheets: + https://www.amphenol-sensors.com/en/telaire/humidity/527-humidity-sensors/3095-chipcap-2 + +properties: + compatible: + oneOf: + - const: amphenol,cc2d23 + - items: + - enum: + - amphenol,cc2d23s + - amphenol,cc2d25 + - amphenol,cc2d25s + - amphenol,cc2d33 + - amphenol,cc2d33s + - amphenol,cc2d35 + - amphenol,cc2d35s + - const: amphenol,cc2d23 + + reg: + maxItems: 1 + + interrupts: + items: + - description: measurement ready indicator + - description: low humidity alarm + - description: high humidity alarm + + interrupt-names: + items: + - const: ready + - const: low + - const: high + + vdd-supply: + description: + Dedicated, controllable supply-regulator to reset the device and + enter in command mode. + +required: + - compatible + - reg + - vdd-supply + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + humidity@28 { + compatible = "amphenol,cc2d23s", "amphenol,cc2d23"; + reg = <0x28>; + interrupt-parent = <&gpio>; + interrupts = <4 IRQ_TYPE_EDGE_RISING>, + <5 IRQ_TYPE_EDGE_RISING>, + <6 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ready", "low", "high"; + vdd-supply = <®_vdd>; + }; + }; diff --git a/Bindings/hwmon/aspeed,g6-pwm-tach.yaml b/Bindings/hwmon/aspeed,g6-pwm-tach.yaml new file mode 100644 index 00000000000..9e5ed901ae5 --- /dev/null +++ b/Bindings/hwmon/aspeed,g6-pwm-tach.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2023 Aspeed, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/aspeed,g6-pwm-tach.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED G6 PWM and Fan Tach controller + +maintainers: + - Billy Tsai + +description: | + The ASPEED PWM controller can support up to 16 PWM outputs. + The ASPEED Fan Tacho controller can support up to 16 fan tach input. + They are independent hardware blocks, which are different from the + previous version of the ASPEED chip. + +properties: + compatible: + enum: + - aspeed,ast2600-pwm-tach + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + "#pwm-cells": + const: 3 + +patternProperties: + "^fan-[0-9]+$": + $ref: fan-common.yaml# + unevaluatedProperties: false + required: + - tach-ch + +required: + - reg + - clocks + - resets + - "#pwm-cells" + - compatible + +additionalProperties: false + +examples: + - | + #include + pwm_tach: pwm-tach-controller@1e610000 { + compatible = "aspeed,ast2600-pwm-tach"; + reg = <0x1e610000 0x100>; + clocks = <&syscon ASPEED_CLK_AHB>; + resets = <&syscon ASPEED_RESET_PWM>; + #pwm-cells = <3>; + + fan-0 { + tach-ch = /bits/ 8 <0x0>; + pwms = <&pwm_tach 0 40000 0>; + }; + + fan-1 { + tach-ch = /bits/ 8 <0x1 0x2>; + pwms = <&pwm_tach 1 40000 0>; + }; + }; diff --git a/Bindings/hwmon/fan-common.yaml b/Bindings/hwmon/fan-common.yaml new file mode 100644 index 00000000000..0fb73808169 --- /dev/null +++ b/Bindings/hwmon/fan-common.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/fan-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common Fan Properties + +maintainers: + - Naresh Solanki + - Billy Tsai + +properties: + max-rpm: + description: + Max RPM supported by fan. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 100000 + + min-rpm: + description: + Min RPM supported by fan. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 1000 + + pulses-per-revolution: + description: + The number of pulse from fan sensor per revolution. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 4 + + tach-div: + description: + Divisor for the tach sampling clock, which determines the sensitivity of the tach pin. + $ref: /schemas/types.yaml#/definitions/uint32 + + target-rpm: + description: + The default desired fan speed in RPM. + $ref: /schemas/types.yaml#/definitions/uint32 + + fan-driving-mode: + description: + Select the driving mode of the fan.(DC, PWM and so on) + $ref: /schemas/types.yaml#/definitions/string + enum: [ dc, pwm ] + + pwms: + description: + PWM provider. + maxItems: 1 + + "#cooling-cells": + const: 2 + + cooling-levels: + description: + The control value which correspond to thermal cooling states. + $ref: /schemas/types.yaml#/definitions/uint32-array + + tach-ch: + description: + The tach channel used for the fan. + $ref: /schemas/types.yaml#/definitions/uint8-array + + label: + description: + Optional fan label + + fan-supply: + description: + Power supply for fan. + + reg: + maxItems: 1 + +additionalProperties: true + +... diff --git a/Bindings/hwmon/hwmon-common.yaml b/Bindings/hwmon/hwmon-common.yaml new file mode 100644 index 00000000000..dc86b5c72cf --- /dev/null +++ b/Bindings/hwmon/hwmon-common.yaml @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/hwmon-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hardware Monitoring Devices Common Properties + +maintainers: + - Guenter Roeck + +properties: + label: + description: A descriptive name for this device. + + shunt-resistor-micro-ohms: + description: The value of current sense resistor. + +additionalProperties: true diff --git a/Bindings/hwmon/lltc,ltc4151.yaml b/Bindings/hwmon/lltc,ltc4151.yaml index e62aff67047..8f0095bb7f6 100644 --- a/Bindings/hwmon/lltc,ltc4151.yaml +++ b/Bindings/hwmon/lltc,ltc4151.yaml @@ -25,7 +25,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: hwmon-common.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Bindings/hwmon/lltc,ltc4286.yaml b/Bindings/hwmon/lltc,ltc4286.yaml index 98ca163d348..853df9fef6c 100644 --- a/Bindings/hwmon/lltc,ltc4286.yaml +++ b/Bindings/hwmon/lltc,ltc4286.yaml @@ -25,15 +25,14 @@ properties: The default is 102.4 volts. type: boolean - shunt-resistor-micro-ohms: - description: - Resistor value micro-ohms. - required: - compatible - reg -additionalProperties: false +allOf: + - $ref: hwmon-common.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Bindings/hwmon/lm75.yaml b/Bindings/hwmon/lm75.yaml index ed269e428a3..29bd7460cc2 100644 --- a/Bindings/hwmon/lm75.yaml +++ b/Bindings/hwmon/lm75.yaml @@ -57,6 +57,7 @@ required: - reg allOf: + - $ref: hwmon-common.yaml# - if: not: properties: @@ -71,7 +72,7 @@ allOf: properties: interrupts: false -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Bindings/hwmon/nuvoton,nct6775.yaml b/Bindings/hwmon/nuvoton,nct6775.yaml index 358b262431f..e3db642878d 100644 --- a/Bindings/hwmon/nuvoton,nct6775.yaml +++ b/Bindings/hwmon/nuvoton,nct6775.yaml @@ -25,6 +25,7 @@ properties: - nuvoton,nct6796 - nuvoton,nct6797 - nuvoton,nct6798 + - nuvoton,nct6799 reg: maxItems: 1 diff --git a/Bindings/hwmon/pmbus/infineon,tda38640.yaml b/Bindings/hwmon/pmbus/infineon,tda38640.yaml index ded1c115764..5c4e52b472a 100644 --- a/Bindings/hwmon/pmbus/infineon,tda38640.yaml +++ b/Bindings/hwmon/pmbus/infineon,tda38640.yaml @@ -30,6 +30,23 @@ properties: unconnected(has internal pull-down). type: boolean + interrupts: + maxItems: 1 + + regulators: + type: object + description: + list of regulators provided by this controller. + + properties: + vout: + $ref: /schemas/regulator/regulator.yaml# + type: object + + unevaluatedProperties: false + + additionalProperties: false + required: - compatible - reg @@ -38,6 +55,7 @@ additionalProperties: false examples: - | + #include i2c { #address-cells = <1>; #size-cells = <0>; @@ -45,5 +63,15 @@ examples: tda38640@40 { compatible = "infineon,tda38640"; reg = <0x40>; + + interrupt-parent = <&smb_pex_cpu0_event>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + + regulators { + pvnn_main_cpu0: vout { + regulator-name = "pvnn_main_cpu0"; + regulator-enable-ramp-delay = <200>; + }; + }; }; }; diff --git a/Bindings/hwmon/pmbus/ti,lm25066.yaml b/Bindings/hwmon/pmbus/ti,lm25066.yaml index da8292bc32f..a20f140dc79 100644 --- a/Bindings/hwmon/pmbus/ti,lm25066.yaml +++ b/Bindings/hwmon/pmbus/ti,lm25066.yaml @@ -34,11 +34,26 @@ properties: Shunt (sense) resistor value in micro-Ohms default: 1000 + regulators: + type: object + + properties: + vout: + $ref: /schemas/regulator/regulator.yaml# + type: object + + unevaluatedProperties: false + + additionalProperties: false + required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/hwmon/hwmon-common.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Bindings/hwmon/ti,ina2xx.yaml b/Bindings/hwmon/ti,ina2xx.yaml index 378d1f6aeeb..df86c2c9203 100644 --- a/Bindings/hwmon/ti,ina2xx.yaml +++ b/Bindings/hwmon/ti,ina2xx.yaml @@ -28,10 +28,14 @@ properties: - ti,ina231 - ti,ina237 - ti,ina238 + - ti,ina260 reg: maxItems: 1 + "#io-channel-cells": + const: 1 + shunt-resistor: description: Shunt resistor value in micro-Ohm. @@ -66,7 +70,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: hwmon-common.yaml# + +unevaluatedProperties: false examples: - | @@ -77,6 +84,8 @@ examples: power-sensor@44 { compatible = "ti,ina220"; reg = <0x44>; + #io-channel-cells = <1>; + label = "vdd_3v0"; shunt-resistor = <1000>; vs-supply = <&vdd_3v0>; }; diff --git a/Bindings/hwmon/ti,tmp513.yaml b/Bindings/hwmon/ti,tmp513.yaml index cdd1489e0c5..227858e7605 100644 --- a/Bindings/hwmon/ti,tmp513.yaml +++ b/Bindings/hwmon/ti,tmp513.yaml @@ -72,7 +72,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: hwmon-common.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Bindings/hwmon/ti,tps23861.yaml b/Bindings/hwmon/ti,tps23861.yaml index ebc8d466c1a..f58248c29e2 100644 --- a/Bindings/hwmon/ti,tps23861.yaml +++ b/Bindings/hwmon/ti,tps23861.yaml @@ -35,7 +35,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: hwmon-common.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Bindings/i2c/atmel,at91sam-i2c.yaml b/Bindings/i2c/atmel,at91sam-i2c.yaml index 6adedd3ec39..b1c13bab247 100644 --- a/Bindings/i2c/atmel,at91sam-i2c.yaml +++ b/Bindings/i2c/atmel,at91sam-i2c.yaml @@ -25,7 +25,9 @@ properties: - atmel,sama5d2-i2c - microchip,sam9x60-i2c - items: - - const: microchip,sama7g5-i2c + - enum: + - microchip,sama7g5-i2c + - microchip,sam9x7-i2c - const: microchip,sam9x60-i2c reg: diff --git a/Bindings/i2c/i2c-demux-pinctrl.yaml b/Bindings/i2c/i2c-demux-pinctrl.yaml index 2c08f2a7cf1..b813f6d4810 100644 --- a/Bindings/i2c/i2c-demux-pinctrl.yaml +++ b/Bindings/i2c/i2c-demux-pinctrl.yaml @@ -32,7 +32,6 @@ description: | +-------------------------------+ allOf: - - $ref: i2c-mux.yaml - $ref: /schemas/i2c/i2c-controller.yaml# properties: @@ -41,6 +40,8 @@ properties: i2c-parent: $ref: /schemas/types.yaml#/definitions/phandle-array + items: + maxItems: 1 description: List of phandles of I2C masters available for selection. The first one will be used as default. diff --git a/Bindings/i2c/i2c-exynos5.yaml b/Bindings/i2c/i2c-exynos5.yaml index df9c57bca2a..cc8bba5537b 100644 --- a/Bindings/i2c/i2c-exynos5.yaml +++ b/Bindings/i2c/i2c-exynos5.yaml @@ -33,6 +33,7 @@ properties: - const: samsung,exynos7-hsi2c - items: - enum: + - google,gs101-hsi2c - samsung,exynos850-hsi2c - const: samsung,exynosautov9-hsi2c - const: samsung,exynos5-hsi2c # Exynos5250 and Exynos5420 diff --git a/Bindings/i2c/i2c-imx-lpi2c.yaml b/Bindings/i2c/i2c-imx-lpi2c.yaml index 4656f5112b8..54d500be6aa 100644 --- a/Bindings/i2c/i2c-imx-lpi2c.yaml +++ b/Bindings/i2c/i2c-imx-lpi2c.yaml @@ -24,6 +24,7 @@ properties: - fsl,imx8qm-lpi2c - fsl,imx8ulp-lpi2c - fsl,imx93-lpi2c + - fsl,imx95-lpi2c - const: fsl,imx7ulp-lpi2c reg: diff --git a/Bindings/i2c/i2c-mpc.yaml b/Bindings/i2c/i2c-mpc.yaml index 70fb69b923c..b1d7d14c0be 100644 --- a/Bindings/i2c/i2c-mpc.yaml +++ b/Bindings/i2c/i2c-mpc.yaml @@ -96,6 +96,6 @@ examples: interrupts = <43 2>; interrupt-parent = <&mpic>; clock-frequency = <400000>; - i2c-scl-clk-low-timeout-us = <10000>; + i2c-transfer-timeout-us = <10000>; }; ... diff --git a/Bindings/i2c/i2c-mux-pca954x.yaml b/Bindings/i2c/i2c-mux-pca954x.yaml index 2d7bb998b0e..9aa0585200c 100644 --- a/Bindings/i2c/i2c-mux-pca954x.yaml +++ b/Bindings/i2c/i2c-mux-pca954x.yaml @@ -71,6 +71,23 @@ properties: description: A voltage regulator supplying power to the chip. On PCA9846 the regulator supplies power to VDD2 (core logic) and optionally to VDD1. + maxim,isolate-stuck-channel: + type: boolean + description: Allows to use non faulty channels while a stuck channel is + isolated from the upstream bus. If not set all channels are isolated from + the upstream bus until the fault is cleared. + + maxim,send-flush-out-sequence: + type: boolean + description: Send a flush-out sequence to stuck auxiliary buses + automatically after a stuck channel is being detected. + + maxim,preconnection-wiggle-test-enable: + type: boolean + description: Send a STOP condition to the auxiliary buses when the switch + register activates a channel to detect a stuck high fault. On fault the + channel is isolated from the upstream bus. + required: - compatible - reg @@ -95,6 +112,19 @@ allOf: "#interrupt-cells": false interrupt-controller: false + - if: + not: + properties: + compatible: + contains: + enum: + - maxim,max7357 + then: + properties: + maxim,isolate-stuck-channel: false + maxim,send-flush-out-sequence: false + maxim,preconnection-wiggle-test-enable: false + unevaluatedProperties: false examples: diff --git a/Bindings/i2c/i2c-pxa.yaml b/Bindings/i2c/i2c-pxa.yaml index 31386a8d768..e89ee361741 100644 --- a/Bindings/i2c/i2c-pxa.yaml +++ b/Bindings/i2c/i2c-pxa.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Marvell MMP I2C controller maintainers: - - Rob Herring + - Rob Herring allOf: - $ref: /schemas/i2c/i2c-controller.yaml# diff --git a/Bindings/i2c/i2c.txt b/Bindings/i2c/i2c.txt deleted file mode 100644 index fc3dd7ec044..00000000000 --- a/Bindings/i2c/i2c.txt +++ /dev/null @@ -1,151 +0,0 @@ -Generic device tree bindings for I2C busses -=========================================== - -This document describes generic bindings which can be used to describe I2C -busses and their child devices in a device tree. - -Required properties (per bus) ------------------------------ - -- #address-cells - should be <1>. Read more about addresses below. -- #size-cells - should be <0>. -- compatible - name of I2C bus controller - -For other required properties e.g. to describe register sets, -clocks, etc. check the binding documentation of the specific driver. - -The cells properties above define that an address of children of an I2C bus -are described by a single value. - -Optional properties (per bus) ------------------------------ - -These properties may not be supported by all drivers. However, if a driver -wants to support one of the below features, it should adapt these bindings. - -- clock-frequency - frequency of bus clock in Hz. - -- i2c-bus - For I2C adapters that have child nodes that are a mixture of both I2C - devices and non-I2C devices, the 'i2c-bus' subnode can be used for - populating I2C devices. If the 'i2c-bus' subnode is present, only - subnodes of this will be considered as I2C slaves. The properties, - '#address-cells' and '#size-cells' must be defined under this subnode - if present. - -- i2c-scl-falling-time-ns - Number of nanoseconds the SCL signal takes to fall; t(f) in the I2C - specification. - -- i2c-scl-internal-delay-ns - Number of nanoseconds the IP core additionally needs to setup SCL. - -- i2c-scl-rising-time-ns - Number of nanoseconds the SCL signal takes to rise; t(r) in the I2C - specification. - -- i2c-sda-falling-time-ns - Number of nanoseconds the SDA signal takes to fall; t(f) in the I2C - specification. - -- i2c-analog-filter - Enable analog filter for i2c lines. - -- i2c-digital-filter - Enable digital filter for i2c lines. - -- i2c-digital-filter-width-ns - Width of spikes which can be filtered by digital filter - (i2c-digital-filter). This width is specified in nanoseconds. - -- i2c-analog-filter-cutoff-frequency - Frequency that the analog filter (i2c-analog-filter) uses to distinguish - which signal to filter. Signal with higher frequency than specified will - be filtered out. Only lower frequency will pass (this is applicable to - a low-pass analog filter). Typical value should be above the normal - i2c bus clock frequency (clock-frequency). - Specified in Hz. - -- multi-master - states that there is another master active on this bus. The OS can use - this information to adapt power management to keep the arbitration awake - all the time, for example. Can not be combined with 'single-master'. - -- pinctrl - add extra pinctrl to configure SCL/SDA pins to GPIO function for bus - recovery, call it "gpio" or "recovery" (deprecated) state - -- scl-gpios - specify the gpio related to SCL pin. Used for GPIO bus recovery. - -- sda-gpios - specify the gpio related to SDA pin. Optional for GPIO bus recovery. - -- single-master - states that there is no other master active on this bus. The OS can use - this information to detect a stalled bus more reliably, for example. - Can not be combined with 'multi-master'. - -- smbus - states that additional SMBus restrictions and features apply to this bus. - An example of feature is SMBusHostNotify. Examples of restrictions are - more reserved addresses and timeout definitions. - -- smbus-alert - states that the optional SMBus-Alert feature apply to this bus. - -- mctp-controller - indicates that the system is accessible via this bus as an endpoint for - MCTP over I2C transport. - -Required properties (per child device) --------------------------------------- - -- compatible - name of I2C slave device - -- reg - One or many I2C slave addresses. These are usually a 7 bit addresses. - However, flags can be attached to an address. I2C_TEN_BIT_ADDRESS is - used to mark a 10 bit address. It is needed to avoid the ambiguity - between e.g. a 7 bit address of 0x50 and a 10 bit address of 0x050 - which, in theory, can be on the same bus. - Another flag is I2C_OWN_SLAVE_ADDRESS to mark addresses on which we - listen to be devices ourselves. - -Optional properties (per child device) --------------------------------------- - -These properties may not be supported by all drivers. However, if a driver -wants to support one of the below features, it should adapt these bindings. - -- host-notify - device uses SMBus host notify protocol instead of interrupt line. - -- interrupts - interrupts used by the device. - -- interrupt-names - "irq", "wakeup" and "smbus_alert" names are recognized by I2C core, - other names are left to individual drivers. - -- reg-names - Names of map programmable addresses. - It can contain any map needing another address than default one. - -- wakeup-source - device can be used as a wakeup source. - -Binding may contain optional "interrupts" property, describing interrupts -used by the device. I2C core will assign "irq" interrupt (or the very first -interrupt if not using interrupt names) as primary interrupt for the slave. - -Alternatively, devices supporting SMBus Host Notify, and connected to -adapters that support this feature, may use "host-notify" property. I2C -core will create a virtual interrupt for Host Notify and assign it as -primary interrupt for the slave. - -Also, if device is marked as a wakeup source, I2C core will set up "wakeup" -interrupt for the device. If "wakeup" interrupt name is not present in the -binding, then primary interrupt will be used as wakeup interrupt. diff --git a/Bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml b/Bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml index b8319dcf3d8..8676335e9e9 100644 --- a/Bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml +++ b/Bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml @@ -21,8 +21,7 @@ description: | See ../firmware/nvidia,tegra186-bpmp.yaml for details of the BPMP binding. - This node represents an I2C controller. See ../i2c/i2c.txt for details - of the core I2C binding. + This node represents an I2C controller. properties: compatible: diff --git a/Bindings/i2c/qcom,i2c-cci.yaml b/Bindings/i2c/qcom,i2c-cci.yaml index 8386cfe2153..f0eabff8631 100644 --- a/Bindings/i2c/qcom,i2c-cci.yaml +++ b/Bindings/i2c/qcom,i2c-cci.yaml @@ -270,7 +270,7 @@ examples: port { ov7251_ep: endpoint { - data-lanes = <0 1>; + data-lanes = <0>; link-frequencies = /bits/ 64 <240000000 319200000>; remote-endpoint = <&csiphy3_ep>; }; diff --git a/Bindings/i2c/renesas,rcar-i2c.yaml b/Bindings/i2c/renesas,rcar-i2c.yaml index c4ace5585e1..51b220da461 100644 --- a/Bindings/i2c/renesas,rcar-i2c.yaml +++ b/Bindings/i2c/renesas,rcar-i2c.yaml @@ -53,6 +53,7 @@ properties: - renesas,i2c-r8a779a0 # R-Car V3U - renesas,i2c-r8a779f0 # R-Car S4-8 - renesas,i2c-r8a779g0 # R-Car V4H + - renesas,i2c-r8a779h0 # R-Car V4M - const: renesas,rcar-gen4-i2c # R-Car Gen4 reg: diff --git a/Bindings/i2c/st,nomadik-i2c.yaml b/Bindings/i2c/st,nomadik-i2c.yaml index 16024415a4a..44c54b162bb 100644 --- a/Bindings/i2c/st,nomadik-i2c.yaml +++ b/Bindings/i2c/st,nomadik-i2c.yaml @@ -14,9 +14,6 @@ description: The Nomadik I2C host controller began its life in the ST maintainers: - Linus Walleij -allOf: - - $ref: /schemas/i2c/i2c-controller.yaml# - # Need a custom select here or 'arm,primecell' will match on lots of nodes select: properties: @@ -24,21 +21,23 @@ select: contains: enum: - st,nomadik-i2c + - mobileye,eyeq5-i2c required: - compatible properties: compatible: oneOf: - # The variant found in STn8815 - items: - const: st,nomadik-i2c - const: arm,primecell - # The variant found in DB8500 - items: - const: stericsson,db8500-i2c - const: st,nomadik-i2c - const: arm,primecell + - items: + - const: mobileye,eyeq5-i2c + - const: arm,primecell reg: maxItems: 1 @@ -55,7 +54,7 @@ properties: - items: - const: mclk - const: apb_pclk - # Clock name in DB8500 + # Clock name in DB8500 or EyeQ5 - items: - const: i2cclk - const: apb_pclk @@ -70,6 +69,16 @@ properties: minimum: 1 maximum: 400000 + mobileye,olb: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to OLB system controller node. + - description: Platform-wide controller ID (integer starting from zero). + description: + The phandle pointing to OLB system controller node, with the I2C + controller index. + required: - compatible - reg @@ -79,6 +88,20 @@ required: unevaluatedProperties: false +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + - if: + properties: + compatible: + contains: + const: mobileye,eyeq5-i2c + then: + required: + - mobileye,olb + else: + properties: + mobileye,olb: false + examples: - | #include @@ -111,5 +134,19 @@ examples: clocks = <&i2c0clk>, <&pclki2c0>; clock-names = "mclk", "apb_pclk"; }; + - | + #include + i2c@300000 { + compatible = "mobileye,eyeq5-i2c", "arm,primecell"; + reg = <0x300000 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&i2c_ser_clk>, <&i2c_clk>; + clock-names = "i2cclk", "apb_pclk"; + mobileye,olb = <&olb 0>; + }; ... diff --git a/Bindings/i3c/aspeed,ast2600-i3c.yaml b/Bindings/i3c/aspeed,ast2600-i3c.yaml index fcc3dbff9c9..47be5d9a32d 100644 --- a/Bindings/i3c/aspeed,ast2600-i3c.yaml +++ b/Bindings/i3c/aspeed,ast2600-i3c.yaml @@ -57,7 +57,7 @@ examples: - | #include - i3c-master@2000 { + i3c@2000 { compatible = "aspeed,ast2600-i3c"; reg = <0x2000 0x1000>; #address-cells = <3>; diff --git a/Bindings/i3c/cdns,i3c-master.yaml b/Bindings/i3c/cdns,i3c-master.yaml index cc40d25358e..cad6d53d0e2 100644 --- a/Bindings/i3c/cdns,i3c-master.yaml +++ b/Bindings/i3c/cdns,i3c-master.yaml @@ -41,7 +41,7 @@ unevaluatedProperties: false examples: - | - i3c-master@d040000 { + i3c@d040000 { compatible = "cdns,i3c-master"; clocks = <&coreclock>, <&i3csysclock>; clock-names = "pclk", "sysclk"; diff --git a/Bindings/i3c/i3c.yaml b/Bindings/i3c/i3c.yaml index c816e295d56..113957ebe9f 100644 --- a/Bindings/i3c/i3c.yaml +++ b/Bindings/i3c/i3c.yaml @@ -17,7 +17,7 @@ description: | properties: $nodename: - pattern: "^i3c-master@[0-9a-f]+$" + pattern: "^i3c@[0-9a-f]+$" "#address-cells": const: 3 @@ -71,7 +71,7 @@ patternProperties: description: | I2C child, should be named: @ - All properties described in Documentation/devicetree/bindings/i2c/i2c.txt + All properties described in dtschema schemas/i2c/i2c-controller.yaml are valid here, except the reg property whose content is changed. properties: @@ -153,7 +153,7 @@ additionalProperties: true examples: - | - i3c-master@d040000 { + i3c@d040000 { compatible = "cdns,i3c-master"; clocks = <&coreclock>, <&i3csysclock>; clock-names = "pclk", "sysclk"; diff --git a/Bindings/i3c/mipi-i3c-hci.yaml b/Bindings/i3c/mipi-i3c-hci.yaml index 5dda8cb44cd..39bb1a1784c 100644 --- a/Bindings/i3c/mipi-i3c-hci.yaml +++ b/Bindings/i3c/mipi-i3c-hci.yaml @@ -43,7 +43,7 @@ unevaluatedProperties: false examples: - | - i3c-master@a0000000 { + i3c@a0000000 { compatible = "mipi-i3c-hci"; reg = <0xa0000000 0x2000>; interrupts = <89>; diff --git a/Bindings/i3c/silvaco,i3c-master.yaml b/Bindings/i3c/silvaco,i3c-master.yaml index 133855f11b4..c56ff77677f 100644 --- a/Bindings/i3c/silvaco,i3c-master.yaml +++ b/Bindings/i3c/silvaco,i3c-master.yaml @@ -48,7 +48,7 @@ unevaluatedProperties: false examples: - | - i3c-master@a0000000 { + i3c@a0000000 { compatible = "silvaco,i3c-master-v1"; clocks = <&zynqmp_clk 71>, <&fclk>, <&sclk>; clock-names = "pclk", "fast_clk", "slow_clk"; diff --git a/Bindings/i3c/snps,dw-i3c-master.yaml b/Bindings/i3c/snps,dw-i3c-master.yaml index 7a76fd32962..c0e805e531b 100644 --- a/Bindings/i3c/snps,dw-i3c-master.yaml +++ b/Bindings/i3c/snps,dw-i3c-master.yaml @@ -35,7 +35,7 @@ unevaluatedProperties: false examples: - | - i3c-master@2000 { + i3c@2000 { compatible = "snps,dw-i3c-master-1.00a"; #address-cells = <3>; #size-cells = <0>; diff --git a/Bindings/iio/adc/adc.yaml b/Bindings/iio/adc/adc.yaml index 26160172974..36775f8f71d 100644 --- a/Bindings/iio/adc/adc.yaml +++ b/Bindings/iio/adc/adc.yaml @@ -22,7 +22,6 @@ properties: maxItems: 1 label: - $ref: /schemas/types.yaml#/definitions/string description: Unique name to identify which channel this is. bipolar: diff --git a/Bindings/iio/adc/adi,ad9467.yaml b/Bindings/iio/adc/adi,ad9467.yaml index 7aa748d6b7a..eecd5fbab69 100644 --- a/Bindings/iio/adc/adi,ad9467.yaml +++ b/Bindings/iio/adc/adi,ad9467.yaml @@ -44,6 +44,9 @@ properties: Pin that controls the powerdown mode of the device. maxItems: 1 + io-backends: + maxItems: 1 + reset-gpios: description: Reset pin for the device. @@ -68,6 +71,7 @@ examples: reg = <0>; clocks = <&adc_clk>; clock-names = "adc-clk"; + io-backends = <&iio_backend>; }; }; ... diff --git a/Bindings/iio/adc/adi,axi-adc.yaml b/Bindings/iio/adc/adi,axi-adc.yaml index 9996dd93f84..3d49d21ad33 100644 --- a/Bindings/iio/adc/adi,axi-adc.yaml +++ b/Bindings/iio/adc/adi,axi-adc.yaml @@ -39,12 +39,15 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle description: A reference to a the actual ADC to which this FPGA ADC interfaces to. + deprecated: true + + '#io-backend-cells': + const: 0 required: - compatible - dmas - reg - - adi,adc-dev additionalProperties: false @@ -55,7 +58,6 @@ examples: reg = <0x44a00000 0x10000>; dmas = <&rx_dma 0>; dma-names = "rx"; - - adi,adc-dev = <&spi_adc>; + #io-backend-cells = <0>; }; ... diff --git a/Bindings/iio/adc/microchip,pac1934.yaml b/Bindings/iio/adc/microchip,pac1934.yaml new file mode 100644 index 00000000000..47a11a9ac95 --- /dev/null +++ b/Bindings/iio/adc/microchip,pac1934.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/microchip,pac1934.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PAC1934 Power Monitors with Accumulator + +maintainers: + - Marius Cristea + +description: | + This device is part of the Microchip family of Power Monitors with + Accumulator. + The datasheet for PAC1931, PAC1932, PAC1933 and PAC1934 can be found here: + https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/DataSheets/PAC1931-Family-Data-Sheet-DS20005850E.pdf + +properties: + compatible: + enum: + - microchip,pac1931 + - microchip,pac1932 + - microchip,pac1933 + - microchip,pac1934 + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + interrupts: + maxItems: 1 + + slow-io-gpios: + description: + A GPIO used to trigger a change is sampling rate (lowering the chip power + consumption). If configured in SLOW mode, if this pin is forced high, + sampling rate is forced to eight samples/second. When it is forced low, + the sampling rate is 1024 samples/second unless a different sample rate + has been programmed. + +patternProperties: + "^channel@[1-4]+$": + type: object + $ref: adc.yaml + description: + Represents the external channels which are connected to the ADC. + + properties: + reg: + items: + minimum: 1 + maximum: 4 + + shunt-resistor-micro-ohms: + description: + Value in micro Ohms of the shunt resistor connected between + the SENSE+ and SENSE- inputs, across which the current is measured. + Value is needed to compute the scaling of the measured current. + + required: + - reg + - shunt-resistor-micro-ohms + + unevaluatedProperties: false + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + power-monitor@10 { + compatible = "microchip,pac1934"; + reg = <0x10>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@1 { + reg = <0x1>; + shunt-resistor-micro-ohms = <24900000>; + label = "CPU"; + }; + + channel@2 { + reg = <0x2>; + shunt-resistor-micro-ohms = <49900000>; + label = "GPU"; + }; + + channel@3 { + reg = <0x3>; + shunt-resistor-micro-ohms = <75000000>; + label = "MEM"; + bipolar; + }; + + channel@4 { + reg = <0x4>; + shunt-resistor-micro-ohms = <100000000>; + label = "NET"; + bipolar; + }; + }; + }; + +... diff --git a/Bindings/iio/adc/nxp,imx93-adc.yaml b/Bindings/iio/adc/nxp,imx93-adc.yaml index dacc526dc69..dfc3f512918 100644 --- a/Bindings/iio/adc/nxp,imx93-adc.yaml +++ b/Bindings/iio/adc/nxp,imx93-adc.yaml @@ -31,7 +31,6 @@ properties: - description: normal conversion, include EOC (End of Conversion), ECH (End of Chain), JEOC (End of Injected Conversion) and JECH (End of injected Chain). - - description: Self-testing Interrupts. clocks: maxItems: 1 @@ -70,8 +69,7 @@ examples: reg = <0x44530000 0x10000>; interrupts = , , - , - ; + ; clocks = <&clk IMX93_CLK_ADC1_GATE>; clock-names = "ipg"; vref-supply = <®_vref_1v8>; diff --git a/Bindings/iio/adc/qcom,spmi-vadc.yaml b/Bindings/iio/adc/qcom,spmi-vadc.yaml index 40fa0710f1f..c28db0d635a 100644 --- a/Bindings/iio/adc/qcom,spmi-vadc.yaml +++ b/Bindings/iio/adc/qcom,spmi-vadc.yaml @@ -75,7 +75,6 @@ patternProperties: in the PMIC-specific files in include/dt-bindings/iio/. label: - $ref: /schemas/types.yaml#/definitions/string description: | ADC input of the platform as seen in the schematics. For thermistor inputs connected to generic AMUX or GPIO inputs diff --git a/Bindings/iio/adc/richtek,rtq6056.yaml b/Bindings/iio/adc/richtek,rtq6056.yaml index 88e008629ea..af2c3a67f88 100644 --- a/Bindings/iio/adc/richtek,rtq6056.yaml +++ b/Bindings/iio/adc/richtek,rtq6056.yaml @@ -25,7 +25,14 @@ description: | properties: compatible: - const: richtek,rtq6056 + oneOf: + - enum: + - richtek,rtq6056 + - richtek,rtq6059 + - items: + - enum: + - richtek,rtq6053 + - const: richtek,rtq6056 reg: maxItems: 1 diff --git a/Bindings/iio/adc/ti,ads1298.yaml b/Bindings/iio/adc/ti,ads1298.yaml new file mode 100644 index 00000000000..bf5a43a81d5 --- /dev/null +++ b/Bindings/iio/adc/ti,ads1298.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/ti,ads1298.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments' ads1298 medical ADC chips + +description: | + Datasheet at: https://www.ti.com/product/ADS1298 + Bindings for this chip aren't complete. + +maintainers: + - Mike Looijmans + +properties: + compatible: + enum: + - ti,ads1298 + + reg: + maxItems: 1 + + spi-cpha: true + + reset-gpios: + maxItems: 1 + + avdd-supply: + description: + Analog power supply, voltage between AVDD and AVSS. When providing a + symmetric +/- 2.5V, the regulator should report 5V. + + vref-supply: + description: + Optional reference voltage. If omitted, internal reference is used, + which is 2.4V when analog supply is below 4.4V, 4V otherwise. + + clocks: + description: Optional 2.048 MHz external source clock on CLK pin + maxItems: 1 + + interrupts: + description: Interrupt on DRDY pin, triggers on falling edge + maxItems: 1 + + label: true + +required: + - compatible + - reg + - avdd-supply + - interrupts + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@1 { + reg = <1>; + compatible = "ti,ads1298"; + label = "ads1298-1-ecg"; + avdd-supply = <®_iso_5v_a>; + clocks = <&clk_ads1298>; + interrupt-parent = <&gpio0>; + interrupts = <78 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <20000000>; + spi-cpha; + }; + }; +... diff --git a/Bindings/iio/afe/voltage-divider.yaml b/Bindings/iio/afe/voltage-divider.yaml index dddf97b5054..4151f99b42a 100644 --- a/Bindings/iio/afe/voltage-divider.yaml +++ b/Bindings/iio/afe/voltage-divider.yaml @@ -39,6 +39,17 @@ properties: description: | Channel node of a voltage io-channel. + '#io-channel-cells': + description: + In addition to consuming the measurement services of a voltage + output channel, the voltage divider can act as a provider of + measurement services to other devices. This is particularly + useful in scenarios wherein an ADC has an analog frontend, + such as a voltage divider, and then consuming its raw value + isn't interesting. In this case, the voltage before the divider + is desired. + const: 1 + output-ohms: description: Resistance Rout over which the output voltage is measured. See full-ohms. diff --git a/Bindings/iio/amplifiers/adi,hmc425a.yaml b/Bindings/iio/amplifiers/adi,hmc425a.yaml index 67de9d4e3a1..3a470459b96 100644 --- a/Bindings/iio/amplifiers/adi,hmc425a.yaml +++ b/Bindings/iio/amplifiers/adi,hmc425a.yaml @@ -21,6 +21,8 @@ description: | HMC540S 1 dB LSB Silicon MMIC 4-Bit Digital Positive Control Attenuator, 0.1 - 8 GHz https://www.analog.com/media/en/technical-documentation/data-sheets/hmc540s.pdf + LTC6373 is a 3-Bit precision instrumentation amplifier with fully differential outputs + https://www.analog.com/media/en/technical-documentation/data-sheets/ltc6373.pdf properties: compatible: @@ -28,16 +30,55 @@ properties: - adi,adrf5740 - adi,hmc425a - adi,hmc540s + - adi,ltc6373 vcc-supply: true ctrl-gpios: description: - Must contain an array of 6 GPIO specifiers, referring to the GPIO pins - connected to the control pins V1-V6. - minItems: 6 + Must contain an array of GPIO specifiers, referring to the GPIO pins + connected to the control pins. + ADRF5740 - 4 GPIO connected to D2-D5 + HMC540S - 4 GPIO connected to V1-V4 + HMC425A - 6 GPIO connected to V1-V6 + LTC6373 - 3 GPIO connected to A0-A2 + minItems: 1 maxItems: 6 +allOf: + - if: + properties: + compatible: + contains: + const: adi,hmc425a + then: + properties: + ctrl-gpios: + minItems: 6 + maxItems: 6 + - if: + properties: + compatible: + contains: + anyOf: + - const: adi,adrf5740 + - const: adi,hmc540s + then: + properties: + ctrl-gpios: + minItems: 4 + maxItems: 4 + - if: + properties: + compatible: + contains: + const: adi,ltc6373 + then: + properties: + ctrl-gpios: + minItems: 3 + maxItems: 3 + required: - compatible - ctrl-gpios diff --git a/Bindings/iio/frequency/adi,admfm2000.yaml b/Bindings/iio/frequency/adi,admfm2000.yaml new file mode 100644 index 00000000000..2bcf4bbc12e --- /dev/null +++ b/Bindings/iio/frequency/adi,admfm2000.yaml @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2024 Analog Devices Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/frequency/adi,admfm2000.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ADMFM2000 Dual Microwave Down Converter + +maintainers: + - Kim Seer Paller + +description: + Dual microwave down converter module with input RF and LO frequency ranges + from 0.5 to 32 GHz and an output IF frequency range from 0.1 to 8 GHz. + It consists of a LNA, mixer, IF filter, DSA, and IF amplifier for each down + conversion path. + +properties: + compatible: + enum: + - adi,admfm2000 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + "^channel@[0-1]$": + type: object + description: Represents a channel of the device. + + additionalProperties: false + + properties: + reg: + description: + The channel number. + minimum: 0 + maximum: 1 + + adi,mixer-mode: + description: + Enable mixer mode for the channel. It downconverts RF between 5 GHz + and 32 GHz to IF between 0.5 GHz and 8 GHz. If not present, the channel + is in direct IF mode which bypasses the mixer and downconverts RF + between 2 GHz and 8 GHz to IF between 0.5 GHz and 8 GHz. + type: boolean + + switch-gpios: + description: | + GPIOs to select the RF path for the channel. The same state of CTRL-A + and CTRL-B GPIOs is not permitted. + CTRL-A CTRL-B CH1 Status CH2 Status + 1 0 Direct IF mode Mixer mode + 0 1 Mixer mode Direct IF mode + + items: + - description: CTRL-A GPIO + - description: CTRL-B GPIO + + attenuation-gpios: + description: | + Choice of attenuation: + DSA-V4 DSA-V3 DSA-V2 DSA-V1 DSA-V0 + 1 1 1 1 1 0 dB + 1 1 1 1 0 -1 dB + 1 1 1 0 1 -2 dB + 1 1 0 1 1 -4 dB + 1 0 1 1 1 -8 dB + 0 1 1 1 1 -16 dB + 0 0 0 0 0 -31 dB + + items: + - description: DSA-V0 GPIO + - description: DSA-V1 GPIO + - description: DSA-V2 GPIO + - description: DSA-V3 GPIO + - description: DSA-V4 GPIO + + required: + - reg + - switch-gpios + - attenuation-gpios + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include + converter { + compatible = "adi,admfm2000"; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + switch-gpios = <&gpio 1 GPIO_ACTIVE_LOW>, + <&gpio 2 GPIO_ACTIVE_HIGH>; + + attenuation-gpios = <&gpio 17 GPIO_ACTIVE_LOW>, + <&gpio 22 GPIO_ACTIVE_LOW>, + <&gpio 23 GPIO_ACTIVE_LOW>, + <&gpio 24 GPIO_ACTIVE_LOW>, + <&gpio 25 GPIO_ACTIVE_LOW>; + }; + + channel@1 { + reg = <1>; + adi,mixer-mode; + switch-gpios = <&gpio 3 GPIO_ACTIVE_LOW>, + <&gpio 4 GPIO_ACTIVE_HIGH>; + + attenuation-gpios = <&gpio 0 GPIO_ACTIVE_LOW>, + <&gpio 5 GPIO_ACTIVE_LOW>, + <&gpio 6 GPIO_ACTIVE_LOW>, + <&gpio 16 GPIO_ACTIVE_LOW>, + <&gpio 26 GPIO_ACTIVE_LOW>; + }; + }; +... diff --git a/Bindings/iio/gyroscope/bosch,bmg160.yaml b/Bindings/iio/gyroscope/bosch,bmg160.yaml index 1414ba9977c..3c6fe74af0b 100644 --- a/Bindings/iio/gyroscope/bosch,bmg160.yaml +++ b/Bindings/iio/gyroscope/bosch,bmg160.yaml @@ -22,6 +22,9 @@ properties: vdd-supply: true vddio-supply: true + spi-max-frequency: + maximum: 10000000 + interrupts: minItems: 1 maxItems: 2 @@ -33,7 +36,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Bindings/iio/health/maxim,max30102.yaml b/Bindings/iio/health/maxim,max30102.yaml index c13c10c8d65..eed0df9d3a2 100644 --- a/Bindings/iio/health/maxim,max30102.yaml +++ b/Bindings/iio/health/maxim,max30102.yaml @@ -42,7 +42,7 @@ allOf: properties: compatible: contains: - const: maxim,max30100 + const: maxim,max30102 then: properties: maxim,green-led-current-microamp: false diff --git a/Bindings/iio/humidity/ti,hdc2010.yaml b/Bindings/iio/humidity/ti,hdc2010.yaml index 79e75a8675c..e3eca891751 100644 --- a/Bindings/iio/humidity/ti,hdc2010.yaml +++ b/Bindings/iio/humidity/ti,hdc2010.yaml @@ -27,6 +27,9 @@ properties: reg: maxItems: 1 + interrupts: + maxItems: 1 + required: - compatible - reg diff --git a/Bindings/iio/humidity/ti,hdc3020.yaml b/Bindings/iio/humidity/ti,hdc3020.yaml index 7f6d0f9edc7..8b5dedd1a59 100644 --- a/Bindings/iio/humidity/ti,hdc3020.yaml +++ b/Bindings/iio/humidity/ti,hdc3020.yaml @@ -43,6 +43,7 @@ additionalProperties: false examples: - | + #include i2c { #address-cells = <1>; #size-cells = <0>; @@ -51,5 +52,7 @@ examples: compatible = "ti,hdc3021", "ti,hdc3020"; reg = <0x47>; vdd-supply = <&vcc_3v3>; + interrupt-parent = <&gpio3>; + interrupts = <23 IRQ_TYPE_EDGE_RISING>; }; }; diff --git a/Bindings/iio/imu/st,lsm6dsx.yaml b/Bindings/iio/imu/st,lsm6dsx.yaml index 28b667a9cb7..c48a96d17f5 100644 --- a/Bindings/iio/imu/st,lsm6dsx.yaml +++ b/Bindings/iio/imu/st,lsm6dsx.yaml @@ -35,7 +35,9 @@ properties: - st,lsm6dsv - st,lsm6dso16is - items: - - const: st,asm330lhhx + - enum: + - st,asm330lhhx + - st,asm330lhhxg1 - const: st,lsm6dsr - items: - const: st,lsm6dstx diff --git a/Bindings/iio/light/ams,as73211.yaml b/Bindings/iio/light/ams,as73211.yaml index 0e8cd02759b..062a038aa0f 100644 --- a/Bindings/iio/light/ams,as73211.yaml +++ b/Bindings/iio/light/ams,as73211.yaml @@ -4,19 +4,22 @@ $id: http://devicetree.org/schemas/iio/light/ams,as73211.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: AMS AS73211 JENCOLOR(R) Digital XYZ Sensor +title: AMS AS73211 JENCOLOR(R) Digital XYZ Sensor and AMS AS7331 UV Sensor maintainers: - Christian Eggers description: | - XYZ True Color Sensor with I2C Interface + AMS AS73211 XYZ True Color Sensor with I2C Interface https://ams.com/documents/20143/36005/AS73211_DS000556_3-01.pdf/a65474c0-b302-c2fd-e30a-c98df87616df + AMS AS7331 UVA, UVB and UVC Sensor with I2C Interface + https://ams.com/documents/20143/9106314/AS7331_DS001047_4-00.pdf properties: compatible: enum: - ams,as73211 + - ams,as7331 reg: description: diff --git a/Bindings/iio/light/vishay,veml6075.yaml b/Bindings/iio/light/vishay,veml6075.yaml index abee04cd126..91c318746bf 100644 --- a/Bindings/iio/light/vishay,veml6075.yaml +++ b/Bindings/iio/light/vishay,veml6075.yaml @@ -21,6 +21,7 @@ properties: required: - compatible - reg + - vdd-supply additionalProperties: false diff --git a/Bindings/iio/magnetometer/voltafield,af8133j.yaml b/Bindings/iio/magnetometer/voltafield,af8133j.yaml new file mode 100644 index 00000000000..b6ab01a6914 --- /dev/null +++ b/Bindings/iio/magnetometer/voltafield,af8133j.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/magnetometer/voltafield,af8133j.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Voltafield AF8133J magnetometer sensor + +maintainers: + - Ondřej Jirman + +properties: + compatible: + const: voltafield,af8133j + + reg: + maxItems: 1 + + reset-gpios: + description: + A signal for active low reset input of the sensor. (optional; if not + used, software reset over I2C will be used instead) + + avdd-supply: + description: + A regulator that provides AVDD power (Working power, usually 3.3V) to + the sensor. + + dvdd-supply: + description: + A regulator that provides DVDD power (Digital IO power, 1.8V - AVDD) + to the sensor. + + mount-matrix: + description: An optional 3x3 mounting rotation matrix. + +required: + - compatible + - reg + - avdd-supply + - dvdd-supply + +additionalProperties: false + +examples: + - | + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + magnetometer@1c { + compatible = "voltafield,af8133j"; + reg = <0x1c>; + avdd-supply = <®_dldo1>; + dvdd-supply = <®_dldo1>; + reset-gpios = <&pio 1 1 GPIO_ACTIVE_LOW>; + }; + }; diff --git a/Bindings/iio/pressure/honeywell,hsc030pa.yaml b/Bindings/iio/pressure/honeywell,hsc030pa.yaml index 65a24ed67b3..89977b9f01c 100644 --- a/Bindings/iio/pressure/honeywell,hsc030pa.yaml +++ b/Bindings/iio/pressure/honeywell,hsc030pa.yaml @@ -99,6 +99,9 @@ required: - honeywell,transfer-function - honeywell,pressure-triplet +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml + additionalProperties: false dependentSchemas: diff --git a/Bindings/iio/pressure/honeywell,mprls0025pa.yaml b/Bindings/iio/pressure/honeywell,mprls0025pa.yaml index d9e903fbfd9..6994b30015b 100644 --- a/Bindings/iio/pressure/honeywell,mprls0025pa.yaml +++ b/Bindings/iio/pressure/honeywell,mprls0025pa.yaml @@ -8,25 +8,28 @@ title: Honeywell mprls0025pa pressure sensor maintainers: - Andreas Klinger + - Petre Rodan description: | Honeywell pressure sensor of model mprls0025pa. - This sensor has an I2C and SPI interface. Only the I2C interface is - implemented. + This sensor has an I2C and SPI interface. There are many models with different pressure ranges available. The vendor calls them "mpr series". All of them have the identical programming model and differ in the pressure range, unit and transfer function. - To support different models one need to specify the pressure range as well as - the transfer function. Pressure range needs to be converted from its unit to - pascal. + To support different models one need to specify its pressure triplet as well + as the transfer function. + + For custom silicon chips not covered by the Honeywell MPR series datasheet, + the pressure values can be specified manually via honeywell,pmin-pascal and + honeywell,pmax-pascal. + The minimal range value stands for the minimum pressure and the maximum value + also for the maximum pressure with linear relation inside the range. The transfer function defines the ranges of numerical values delivered by the - sensor. The minimal range value stands for the minimum pressure and the - maximum value also for the maximum pressure with linear relation inside the - range. + sensor. Specifications about the devices can be found at: https://prod-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/ @@ -42,6 +45,10 @@ properties: maxItems: 1 interrupts: + description: + Optional interrupt for indicating End-of-conversion. + If not present, the driver loops for a while until the received status + byte indicates correct measurement. maxItems: 1 reset-gpios: @@ -50,6 +57,27 @@ properties: If not present the device is not reset during the probe. maxItems: 1 + honeywell,transfer-function: + description: | + Transfer function which defines the range of valid values delivered by the + sensor. + 1 - A, 10% to 90% of 2^24 (1677722 .. 15099494) + 2 - B, 2.5% to 22.5% of 2^24 (419430 .. 3774874) + 3 - C, 20% to 80% of 2^24 (3355443 .. 13421773) + enum: [1, 2, 3] + $ref: /schemas/types.yaml#/definitions/uint32 + + honeywell,pressure-triplet: + description: | + Case-sensitive five character string that defines pressure range, unit + and type as part of the device nomenclature. In the unlikely case of a + custom chip, unset and provide pmin-pascal and pmax-pascal instead. + enum: [0001BA, 01.6BA, 02.5BA, 0060MG, 0100MG, 0160MG, 0250MG, 0400MG, + 0600MG, 0001BG, 01.6BG, 02.5BG, 0100KA, 0160KA, 0250KA, 0006KG, + 0010KG, 0016KG, 0025KG, 0040KG, 0060KG, 0100KG, 0160KG, 0250KG, + 0015PA, 0025PA, 0030PA, 0001PG, 0005PG, 0015PG, 0030PG, 0300YG] + $ref: /schemas/types.yaml#/definitions/string + honeywell,pmin-pascal: description: Minimum pressure value the sensor can measure in pascal. @@ -58,14 +86,8 @@ properties: description: Maximum pressure value the sensor can measure in pascal. - honeywell,transfer-function: - description: | - Transfer function which defines the range of valid values delivered by the - sensor. - 1 - A, 10% to 90% of 2^24 (1677722 .. 15099494) - 2 - B, 2.5% to 22.5% of 2^24 (419430 .. 3774874) - 3 - C, 20% to 80% of 2^24 (3355443 .. 13421773) - $ref: /schemas/types.yaml#/definitions/uint32 + spi-max-frequency: + maximum: 800000 vdd-supply: description: provide VDD power to the sensor. @@ -73,11 +95,26 @@ properties: required: - compatible - reg - - honeywell,pmin-pascal - - honeywell,pmax-pascal - honeywell,transfer-function - vdd-supply +oneOf: + - required: + - honeywell,pressure-triplet + - required: + - honeywell,pmin-pascal + - honeywell,pmax-pascal + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml + - if: + required: + - honeywell,pressure-triplet + then: + properties: + honeywell,pmin-pascal: false + honeywell,pmax-pascal: false + additionalProperties: false examples: @@ -93,10 +130,29 @@ examples: reg = <0x18>; reset-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; interrupt-parent = <&gpio3>; - interrupts = <21 IRQ_TYPE_EDGE_FALLING>; - honeywell,pmin-pascal = <0>; - honeywell,pmax-pascal = <172369>; + interrupts = <21 IRQ_TYPE_EDGE_RISING>; + + honeywell,pressure-triplet = "0025PA"; honeywell,transfer-function = <1>; vdd-supply = <&vcc_3v3>; }; }; + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + pressure@0 { + compatible = "honeywell,mprls0025pa"; + reg = <0>; + spi-max-frequency = <800000>; + reset-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio0>; + interrupts = <30 IRQ_TYPE_EDGE_RISING>; + + honeywell,pressure-triplet = "0015PA"; + honeywell,transfer-function = <1>; + vdd-supply = <&vcc_3v3>; + }; + }; +... diff --git a/Bindings/iio/temperature/ti,tmp117.yaml b/Bindings/iio/temperature/ti,tmp117.yaml index 8c6d7735e87..58aa1542776 100644 --- a/Bindings/iio/temperature/ti,tmp117.yaml +++ b/Bindings/iio/temperature/ti,tmp117.yaml @@ -24,9 +24,16 @@ properties: reg: maxItems: 1 + vcc-supply: + description: provide VCC power to the sensor. + + label: + description: Unique name to identify which device this is. + required: - compatible - reg + - vcc-supply additionalProperties: false @@ -39,5 +46,6 @@ examples: tmp117@48 { compatible = "ti,tmp117"; reg = <0x48>; + vcc-supply = <&pmic_reg_3v3>; }; }; diff --git a/Bindings/input/allwinner,sun4i-a10-lradc-keys.yaml b/Bindings/input/allwinner,sun4i-a10-lradc-keys.yaml index 5efceb31387..c384bf0bb25 100644 --- a/Bindings/input/allwinner,sun4i-a10-lradc-keys.yaml +++ b/Bindings/input/allwinner,sun4i-a10-lradc-keys.yaml @@ -49,7 +49,6 @@ patternProperties: $ref: input.yaml# properties: label: - $ref: /schemas/types.yaml#/definitions/string description: Descriptive name of the key linux,code: true diff --git a/Bindings/input/atmel,captouch.txt b/Bindings/input/atmel,captouch.txt deleted file mode 100644 index fe9ee5c53bc..00000000000 --- a/Bindings/input/atmel,captouch.txt +++ /dev/null @@ -1,36 +0,0 @@ -Device tree bindings for Atmel capacitive touch device, typically -an Atmel touch sensor connected to AtmegaXX MCU running firmware -based on Qtouch library. - -The node for this device must be a child of a I2C controller node, as the -device communicates via I2C. - -Required properties: - - compatible: Must be "atmel,captouch". - reg: The I2C slave address of the device. - interrupts: Property describing the interrupt line the device - is connected to. The device only has one interrupt - source. - linux,keycodes: Specifies an array of numeric keycode values to - be used for reporting button presses. The array can - contain up to 8 entries. - -Optional properties: - - autorepeat: Enables the Linux input system's autorepeat - feature on the input device. - -Example: - - atmel-captouch@51 { - compatible = "atmel,captouch"; - reg = <0x51>; - interrupt-parent = <&tlmm>; - interrupts = <67 IRQ_TYPE_EDGE_FALLING>; - linux,keycodes = , , - , , - , , - , ; - autorepeat; - }; diff --git a/Bindings/input/atmel,captouch.yaml b/Bindings/input/atmel,captouch.yaml new file mode 100644 index 00000000000..f7477091d5a --- /dev/null +++ b/Bindings/input/atmel,captouch.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/atmel,captouch.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel capacitive touch device + +maintainers: + - Dharma balasubiramani + +description: + Atmel capacitive touch device, typically an Atmel touch sensor connected to + AtmegaXX MCU running firmware based on Qtouch library. + +allOf: + - $ref: input.yaml# + +properties: + compatible: + const: atmel,captouch + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + linux,keycodes: + minItems: 1 + maxItems: 8 + +required: + - compatible + - reg + - interrupts + - linux,keycodes + +unevaluatedProperties: false + +examples: + - | + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + touch@51 { + compatible = "atmel,captouch"; + reg = <0x51>; + interrupt-parent = <&tlmm>; + interrupts = <67 IRQ_TYPE_EDGE_FALLING>; + linux,keycodes = , , + , , + , , + , ; + autorepeat; + }; + }; diff --git a/Bindings/input/da9062-onkey.txt b/Bindings/input/da9062-onkey.txt deleted file mode 100644 index e5eef59a93d..00000000000 --- a/Bindings/input/da9062-onkey.txt +++ /dev/null @@ -1,47 +0,0 @@ -* Dialog DA9061/62/63 OnKey Module - -This module is part of the DA9061/DA9062/DA9063. For more details about entire -DA9062 and DA9061 chips see Documentation/devicetree/bindings/mfd/da9062.txt -For DA9063 see Documentation/devicetree/bindings/mfd/dlg,da9063.yaml - -This module provides the KEY_POWER event. - -Required properties: - -- compatible: should be one of the following valid compatible string lines: - "dlg,da9061-onkey", "dlg,da9062-onkey" - "dlg,da9062-onkey" - "dlg,da9063-onkey" - -Optional properties: - -- dlg,disable-key-power : Disable power-down using a long key-press. If this - entry exists the OnKey driver will remove support for the KEY_POWER key - press when triggered using a long press of the OnKey. - -Example: DA9063 - - pmic0: da9063@58 { - onkey { - compatible = "dlg,da9063-onkey"; - dlg,disable-key-power; - }; - }; - -Example: DA9062 - - pmic0: da9062@58 { - onkey { - compatible = "dlg,da9062-onkey"; - dlg,disable-key-power; - }; - }; - -Example: DA9061 using a fall-back compatible for the DA9062 onkey driver - - pmic0: da9061@58 { - onkey { - compatible = "dlg,da9061-onkey", "dlg,da9062-onkey"; - dlg,disable-key-power; - }; - }; diff --git a/Bindings/input/dlg,da9062-onkey.yaml b/Bindings/input/dlg,da9062-onkey.yaml new file mode 100644 index 00000000000..1480d95421e --- /dev/null +++ b/Bindings/input/dlg,da9062-onkey.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/dlg,da9062-onkey.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Dialog DA9061/62/63 OnKey Module + +maintainers: + - Biju Das + +description: | + This module is part of the DA9061/DA9062/DA9063. For more details about entire + DA906{1,2,3} chips see Documentation/devicetree/bindings/mfd/dlg,da9063.yaml + + This module provides the KEY_POWER event. + +properties: + compatible: + oneOf: + - enum: + - dlg,da9062-onkey + - dlg,da9063-onkey + - items: + - const: dlg,da9061-onkey + - const: dlg,da9062-onkey + + dlg,disable-key-power: + type: boolean + description: + Disable power-down using a long key-press. If this entry exists + the OnKey driver will remove support for the KEY_POWER key press + when triggered using a long press of the OnKey. + +required: + - compatible + +additionalProperties: false diff --git a/Bindings/input/samsung,s3c6410-keypad.yaml b/Bindings/input/samsung,s3c6410-keypad.yaml new file mode 100644 index 00000000000..a53569aa0ee --- /dev/null +++ b/Bindings/input/samsung,s3c6410-keypad.yaml @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/samsung,s3c6410-keypad.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SoC series Keypad Controller + +description: + Samsung SoC Keypad controller is used to interface a SoC with a matrix-type + keypad device. The keypad controller supports multiple row and column lines. + A key can be placed at each intersection of a unique row and a unique column. + The keypad controller can sense a key-press and key-release and report the + event using a interrupt to the cpu. + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + enum: + - samsung,s3c6410-keypad + - samsung,s5pv210-keypad + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: keypad + + interrupts: + maxItems: 1 + + wakeup-source: true + + linux,input-no-autorepeat: + type: boolean + description: + Do no enable autorepeat feature. + + linux,input-wakeup: + type: boolean + deprecated: true + + samsung,keypad-num-columns: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Number of column lines connected to the keypad controller. + + samsung,keypad-num-rows: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Number of row lines connected to the keypad controller. + +patternProperties: + '^key-[0-9a-z]+$': + type: object + $ref: input.yaml# + additionalProperties: false + description: + Each key connected to the keypad controller is represented as a child + node to the keypad controller device node. + + properties: + keypad,column: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The column number to which the key is connected. + + keypad,row: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The row number to which the key is connected. + + linux,code: true + + required: + - keypad,column + - keypad,row + - linux,code + +required: + - compatible + - reg + - interrupts + - samsung,keypad-num-columns + - samsung,keypad-num-rows + +additionalProperties: false + +examples: + - | + #include + #include + + keypad@100a0000 { + compatible = "samsung,s5pv210-keypad"; + reg = <0x100a0000 0x100>; + interrupts = ; + clocks = <&clock CLK_KEYIF>; + clock-names = "keypad"; + + samsung,keypad-num-rows = <2>; + samsung,keypad-num-columns = <8>; + linux,input-no-autorepeat; + wakeup-source; + + key-1 { + keypad,row = <0>; + keypad,column = <3>; + linux,code = <2>; + }; + + key-2 { + keypad,row = <0>; + keypad,column = <4>; + linux,code = <3>; + }; + }; diff --git a/Bindings/input/samsung-keypad.txt b/Bindings/input/samsung-keypad.txt deleted file mode 100644 index 4c5c0a82586..00000000000 --- a/Bindings/input/samsung-keypad.txt +++ /dev/null @@ -1,77 +0,0 @@ -* Samsung's Keypad Controller device tree bindings - -Samsung's Keypad controller is used to interface a SoC with a matrix-type -keypad device. The keypad controller supports multiple row and column lines. -A key can be placed at each intersection of a unique row and a unique column. -The keypad controller can sense a key-press and key-release and report the -event using a interrupt to the cpu. - -Required SoC Specific Properties: -- compatible: should be one of the following - - "samsung,s3c6410-keypad": For controllers compatible with s3c6410 keypad - controller. - - "samsung,s5pv210-keypad": For controllers compatible with s5pv210 keypad - controller. - -- reg: physical base address of the controller and length of memory mapped - region. - -- interrupts: The interrupt number to the cpu. - -Required Board Specific Properties: -- samsung,keypad-num-rows: Number of row lines connected to the keypad - controller. - -- samsung,keypad-num-columns: Number of column lines connected to the - keypad controller. - -- Keys represented as child nodes: Each key connected to the keypad - controller is represented as a child node to the keypad controller - device node and should include the following properties. - - keypad,row: the row number to which the key is connected. - - keypad,column: the column number to which the key is connected. - - linux,code: the key-code to be reported when the key is pressed - and released. - -- pinctrl-0: Should specify pin control groups used for this controller. -- pinctrl-names: Should contain only one value - "default". - -Optional Properties: -- wakeup-source: use any event on keypad as wakeup event. - (Legacy property supported: "linux,input-wakeup") - -Optional Properties specific to linux: -- linux,keypad-no-autorepeat: do no enable autorepeat feature. - - -Example: - keypad@100a0000 { - compatible = "samsung,s5pv210-keypad"; - reg = <0x100A0000 0x100>; - interrupts = <173>; - samsung,keypad-num-rows = <2>; - samsung,keypad-num-columns = <8>; - linux,input-no-autorepeat; - wakeup-source; - - pinctrl-names = "default"; - pinctrl-0 = <&keypad_rows &keypad_columns>; - - key_1 { - keypad,row = <0>; - keypad,column = <3>; - linux,code = <2>; - }; - - key_2 { - keypad,row = <0>; - keypad,column = <4>; - linux,code = <3>; - }; - - key_3 { - keypad,row = <0>; - keypad,column = <5>; - linux,code = <4>; - }; - }; diff --git a/Bindings/input/touchscreen/fsl,imx6ul-tsc.yaml b/Bindings/input/touchscreen/fsl,imx6ul-tsc.yaml new file mode 100644 index 00000000000..678756ad0f9 --- /dev/null +++ b/Bindings/input/touchscreen/fsl,imx6ul-tsc.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/fsl,imx6ul-tsc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX6UL Touch Controller + +maintainers: + - Haibo Chen + - Shawn Guo + - Sascha Hauer + +properties: + compatible: + const: fsl,imx6ul-tsc + + reg: + items: + - description: touch controller address + - description: ADC2 address + + interrupts: + items: + - description: touch controller address + - description: ADC2 address + + clocks: + maxItems: 2 + + clock-names: + items: + - const: tsc + - const: adc + + xnur-gpios: + maxItems: 1 + description: + The X- gpio this controller connect to. This xnur-gpio returns to + low once the finger leave the touch screen (The last touch event + the touch controller capture). + + measure-delay-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The value of measure delay time. Before X-axis or Y-axis measurement, + the screen need some time before even potential distribution ready. + default: 0xffff + minimum: 0 + maximum: 0xffffff + + pre-charge-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The touch screen need some time to precharge. + default: 0xfff + minimum: 0 + maximum: 0xffffffff + + touchscreen-average-samples: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of data samples which are averaged for each read. + enum: [ 1, 4, 8, 16, 32 ] + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - xnur-gpios + +allOf: + - $ref: touchscreen.yaml# + +additionalProperties: false + +examples: + - | + #include + #include + #include + touchscreen@2040000 { + compatible = "fsl,imx6ul-tsc"; + reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; + interrupts = , + ; + clocks = <&clks IMX6UL_CLK_IPG>, + <&clks IMX6UL_CLK_ADC2>; + clock-names = "tsc", "adc"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + measure-delay-time = <0xfff>; + pre-charge-time = <0xffff>; + touchscreen-average-samples = <32>; + }; diff --git a/Bindings/input/touchscreen/goodix,gt9916.yaml b/Bindings/input/touchscreen/goodix,gt9916.yaml new file mode 100644 index 00000000000..d90f045ac06 --- /dev/null +++ b/Bindings/input/touchscreen/goodix,gt9916.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/goodix,gt9916.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Goodix Berlin series touchscreen controller + +description: The Goodix Berlin series of touchscreen controllers + be connected to either I2C or SPI buses. + +maintainers: + - Neil Armstrong + +allOf: + - $ref: touchscreen.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - goodix,gt9916 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + avdd-supply: + description: Analog power supply regulator on AVDD pin + + vddio-supply: + description: power supply regulator on VDDIO pin + + spi-max-frequency: true + touchscreen-inverted-x: true + touchscreen-inverted-y: true + touchscreen-size-x: true + touchscreen-size-y: true + touchscreen-swapped-x-y: true + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - avdd-supply + - touchscreen-size-x + - touchscreen-size-y + +examples: + - | + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + touchscreen@5d { + compatible = "goodix,gt9916"; + reg = <0x5d>; + interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + avdd-supply = <&ts_avdd>; + touchscreen-size-x = <1024>; + touchscreen-size-y = <768>; + }; + }; + - | + #include + #include + spi { + #address-cells = <1>; + #size-cells = <0>; + num-cs = <1>; + cs-gpios = <&gpio 2 GPIO_ACTIVE_HIGH>; + touchscreen@0 { + compatible = "goodix,gt9916"; + reg = <0>; + interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + avdd-supply = <&ts_avdd>; + spi-max-frequency = <1000000>; + touchscreen-size-x = <1024>; + touchscreen-size-y = <768>; + }; + }; + +... diff --git a/Bindings/input/touchscreen/goodix.yaml b/Bindings/input/touchscreen/goodix.yaml index 3d016b87c8d..2a2d86cfd10 100644 --- a/Bindings/input/touchscreen/goodix.yaml +++ b/Bindings/input/touchscreen/goodix.yaml @@ -37,8 +37,9 @@ properties: maxItems: 1 irq-gpios: - description: GPIO pin used for IRQ. The driver uses the interrupt gpio pin - as output to reset the device. + description: GPIO pin used for IRQ input. Additionally, this line is + sampled by the device on reset deassertion to select the I2C client + address, thus it can be driven by the host during the reset sequence. maxItems: 1 reset-gpios: diff --git a/Bindings/input/touchscreen/imagis,ist3038c.yaml b/Bindings/input/touchscreen/imagis,ist3038c.yaml index 0d6b033fd5f..77ba280b3bd 100644 --- a/Bindings/input/touchscreen/imagis,ist3038c.yaml +++ b/Bindings/input/touchscreen/imagis,ist3038c.yaml @@ -9,15 +9,14 @@ title: Imagis IST30XXC family touchscreen controller maintainers: - Markuss Broks -allOf: - - $ref: touchscreen.yaml# - properties: $nodename: pattern: "^touchscreen@[0-9a-f]+$" compatible: enum: + - imagis,ist3032c + - imagis,ist3038b - imagis,ist3038c reg: @@ -32,6 +31,10 @@ properties: vddio-supply: description: Power supply regulator for the I2C bus + linux,keycodes: + description: Keycodes for the touch keys + maxItems: 5 + touchscreen-size-x: true touchscreen-size-y: true touchscreen-fuzz-x: true @@ -42,6 +45,18 @@ properties: additionalProperties: false +allOf: + - $ref: touchscreen.yaml# + - if: + not: + properties: + compatible: + contains: + const: imagis,ist3032c + then: + properties: + linux,keycodes: false + required: - compatible - reg diff --git a/Bindings/input/touchscreen/imx6ul_tsc.txt b/Bindings/input/touchscreen/imx6ul_tsc.txt deleted file mode 100644 index 16491500442..00000000000 --- a/Bindings/input/touchscreen/imx6ul_tsc.txt +++ /dev/null @@ -1,38 +0,0 @@ -* Freescale i.MX6UL Touch Controller - -Required properties: -- compatible: must be "fsl,imx6ul-tsc". -- reg: this touch controller address and the ADC2 address. -- interrupts: the interrupt of this touch controller and ADC2. -- clocks: the root clock of touch controller and ADC2. -- clock-names; must be "tsc" and "adc". -- xnur-gpio: the X- gpio this controller connect to. - This xnur-gpio returns to low once the finger leave the touch screen (The - last touch event the touch controller capture). - -Optional properties: -- measure-delay-time: the value of measure delay time. - Before X-axis or Y-axis measurement, the screen need some time before - even potential distribution ready. - This value depends on the touch screen. -- pre-charge-time: the touch screen need some time to precharge. - This value depends on the touch screen. -- touchscreen-average-samples: Number of data samples which are averaged for - each read. Valid values are 1, 4, 8, 16 and 32. - -Example: - tsc: tsc@2040000 { - compatible = "fsl,imx6ul-tsc"; - reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6UL_CLK_IPG>, - <&clks IMX6UL_CLK_ADC2>; - clock-names = "tsc", "adc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc>; - xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; - measure-delay-time = <0xfff>; - pre-charge-time = <0xffff>; - touchscreen-average-samples = <32>; - }; diff --git a/Bindings/input/touchscreen/melfas,mms114.yaml b/Bindings/input/touchscreen/melfas,mms114.yaml index 07f9dd6b1c9..90ebd4f8354 100644 --- a/Bindings/input/touchscreen/melfas,mms114.yaml +++ b/Bindings/input/touchscreen/melfas,mms114.yaml @@ -17,13 +17,17 @@ properties: pattern: "^touchscreen(@.*)?$" compatible: - items: + oneOf: - enum: - melfas,mms114 - melfas,mms134s - melfas,mms136 - melfas,mms152 - melfas,mms345l + - items: + - enum: + - melfas,mms252 + - const: melfas,mms114 reg: description: I2C address diff --git a/Bindings/input/touchscreen/silead,gsl1680.yaml b/Bindings/input/touchscreen/silead,gsl1680.yaml index 95b554be25b..5381a96f494 100644 --- a/Bindings/input/touchscreen/silead,gsl1680.yaml +++ b/Bindings/input/touchscreen/silead,gsl1680.yaml @@ -31,7 +31,7 @@ properties: maxItems: 1 firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: > File basename for board specific firmware diff --git a/Bindings/interconnect/qcom,rpm.yaml b/Bindings/interconnect/qcom,rpm.yaml index 08c1c6b9d7c..5aaa92a7cef 100644 --- a/Bindings/interconnect/qcom,rpm.yaml +++ b/Bindings/interconnect/qcom,rpm.yaml @@ -23,6 +23,9 @@ properties: compatible: enum: + - qcom,msm8909-bimc + - qcom,msm8909-pcnoc + - qcom,msm8909-snoc - qcom,msm8916-bimc - qcom,msm8916-pcnoc - qcom,msm8916-snoc diff --git a/Bindings/interconnect/qcom,rpmh.yaml b/Bindings/interconnect/qcom,rpmh.yaml index 74ab080249f..9318b845ec3 100644 --- a/Bindings/interconnect/qcom,rpmh.yaml +++ b/Bindings/interconnect/qcom,rpmh.yaml @@ -8,7 +8,7 @@ title: Qualcomm RPMh Network-On-Chip Interconnect maintainers: - Georgi Djakov - - Odelu Kukatla + - Odelu Kukatla description: | RPMh interconnect providers support system bandwidth requirements through diff --git a/Bindings/interconnect/qcom,sm7150-rpmh.yaml b/Bindings/interconnect/qcom,sm7150-rpmh.yaml new file mode 100644 index 00000000000..b565d1a382f --- /dev/null +++ b/Bindings/interconnect/qcom,sm7150-rpmh.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,sm7150-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on SM7150 + +maintainers: + - Danila Tikhonov + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). + + See also:: include/dt-bindings/interconnect/qcom,sm7150-rpmh.h + +allOf: + - $ref: qcom,rpmh-common.yaml# + +properties: + compatible: + enum: + - qcom,sm7150-aggre1-noc + - qcom,sm7150-aggre2-noc + - qcom,sm7150-compute-noc + - qcom,sm7150-config-noc + - qcom,sm7150-dc-noc + - qcom,sm7150-gem-noc + - qcom,sm7150-mc-virt + - qcom,sm7150-mmss-noc + - qcom,sm7150-system-noc + + reg: + maxItems: 1 + +# Child node's properties +patternProperties: + '^interconnect-[0-9]+$': + type: object + description: + The interconnect providers do not have a separate QoS register space, + but share parent's space. + + allOf: + - $ref: qcom,rpmh-common.yaml# + + properties: + compatible: + enum: + - qcom,sm7150-camnoc-virt + + required: + - compatible + + unevaluatedProperties: false + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + mc_virt: interconnect@1380000 { + compatible = "qcom,sm7150-mc-virt"; + reg = <0x01380000 0x40000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + compatible = "qcom,sm7150-system-noc"; + reg = <0x01620000 0x40000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + + camnoc_virt: interconnect-0 { + compatible = "qcom,sm7150-camnoc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + }; diff --git a/Bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml b/Bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml index 3d06db98e97..a9374476378 100644 --- a/Bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml +++ b/Bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml @@ -36,6 +36,7 @@ properties: - amlogic,meson-a1-gpio-intc - amlogic,meson-s4-gpio-intc - amlogic,c3-gpio-intc + - amlogic,t7-gpio-intc - const: amlogic,meson-gpio-intc reg: diff --git a/Bindings/interrupt-controller/atmel,aic.txt b/Bindings/interrupt-controller/atmel,aic.txt deleted file mode 100644 index 7079d44bf3b..00000000000 --- a/Bindings/interrupt-controller/atmel,aic.txt +++ /dev/null @@ -1,43 +0,0 @@ -* Advanced Interrupt Controller (AIC) - -Required properties: -- compatible: Should be: - - "atmel,-aic" where can be "at91rm9200", "sama5d2", - "sama5d3" or "sama5d4" - - "microchip,-aic" where can be "sam9x60" - -- interrupt-controller: Identifies the node as an interrupt controller. -- #interrupt-cells: The number of cells to define the interrupts. It should be 3. - The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet). - The second cell is used to specify flags: - bits[3:0] trigger type and level flags: - 1 = low-to-high edge triggered. - 2 = high-to-low edge triggered. - 4 = active high level-sensitive. - 8 = active low level-sensitive. - Valid combinations are 1, 2, 3, 4, 8. - Default flag for internal sources should be set to 4 (active high). - The third cell is used to specify the irq priority from 0 (lowest) to 7 - (highest). -- reg: Should contain AIC registers location and length -- atmel,external-irqs: u32 array of external irqs. - -Examples: - /* - * AIC - */ - aic: interrupt-controller@fffff000 { - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0xfffff000 0x200>; - }; - - /* - * An interrupt generating device that is wired to an AIC. - */ - dma: dma-controller@ffffec00 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffec00 0x200>; - interrupts = <21 4 5>; - }; diff --git a/Bindings/interrupt-controller/atmel,aic.yaml b/Bindings/interrupt-controller/atmel,aic.yaml new file mode 100644 index 00000000000..d4658fe3867 --- /dev/null +++ b/Bindings/interrupt-controller/atmel,aic.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/atmel,aic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Advanced Interrupt Controller (AIC) + +maintainers: + - Nicolas Ferre + - Dharma balasubiramani + +description: + The Advanced Interrupt Controller (AIC) is an 8-level priority, individually + maskable, vectored interrupt controller providing handling of up to one + hundred and twenty-eight interrupt sources. + +properties: + compatible: + enum: + - atmel,at91rm9200-aic + - atmel,sama5d2-aic + - atmel,sama5d3-aic + - atmel,sama5d4-aic + - microchip,sam9x60-aic + + reg: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 3 + description: | + The 1st cell is the IRQ number (Peripheral IDentifier on datasheet). + The 2nd cell specifies flags: + bits[3:0] trigger type and level flags: + 1 = low-to-high edge triggered. + 2 = high-to-low edge triggered. + 4 = active high level-sensitive. + 8 = active low level-sensitive. + Valid combinations: 1, 2, 3, 4, 8. + Default for internal sources: 4 (active high). + The 3rd cell specifies irq priority from 0 (lowest) to 7 (highest). + + interrupts: + maxItems: 1 + + atmel,external-irqs: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: u32 array of external irqs. + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + - if: + properties: + compatible: + contains: + const: atmel,at91rm9200-aic + then: + properties: + atmel,external-irqs: + minItems: 1 + maxItems: 7 + else: + properties: + atmel,external-irqs: + minItems: 1 + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - "#interrupt-cells" + - atmel,external-irqs + +unevaluatedProperties: false + +examples: + - | + interrupt-controller@fffff000 { + compatible = "atmel,at91rm9200-aic"; + reg = <0xfffff000 0x200>; + interrupt-controller; + #interrupt-cells = <3>; + atmel,external-irqs = <31>; + }; +... diff --git a/Bindings/interrupt-controller/fsl,intmux.yaml b/Bindings/interrupt-controller/fsl,intmux.yaml index 985bfa4f6fd..78baa0a571c 100644 --- a/Bindings/interrupt-controller/fsl,intmux.yaml +++ b/Bindings/interrupt-controller/fsl,intmux.yaml @@ -37,6 +37,9 @@ properties: clock-names: const: ipg + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Bindings/interrupt-controller/mediatek,mt6577-sysirq.yaml b/Bindings/interrupt-controller/mediatek,mt6577-sysirq.yaml new file mode 100644 index 00000000000..e1a379c052e --- /dev/null +++ b/Bindings/interrupt-controller/mediatek,mt6577-sysirq.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/mediatek,mt6577-sysirq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek sysirq + +description: + MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI + interrupt. + +maintainers: + - Matthias Brugger + +properties: + compatible: + oneOf: + - const: mediatek,mt6577-sysirq + - items: + - enum: + - mediatek,mt2701-sysirq + - mediatek,mt2712-sysirq + - mediatek,mt6580-sysirq + - mediatek,mt6582-sysirq + - mediatek,mt6589-sysirq + - mediatek,mt6592-sysirq + - mediatek,mt6755-sysirq + - mediatek,mt6765-sysirq + - mediatek,mt6779-sysirq + - mediatek,mt6795-sysirq + - mediatek,mt6797-sysirq + - mediatek,mt7622-sysirq + - mediatek,mt7623-sysirq + - mediatek,mt7629-sysirq + - mediatek,mt8127-sysirq + - mediatek,mt8135-sysirq + - mediatek,mt8173-sysirq + - mediatek,mt8183-sysirq + - mediatek,mt8365-sysirq + - mediatek,mt8516-sysirq + - const: mediatek,mt6577-sysirq + + reg: + minItems: 1 + maxItems: 2 + + interrupt-controller: true + + "#interrupt-cells": + $ref: "arm,gic.yaml#/properties/#interrupt-cells" + +required: + - reg + - interrupt-controller + - "#interrupt-cells" + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + - if: + properties: + compatible: + contains: + const: mediatek,mt6797-sysirq + then: + properties: + reg: + minItems: 2 + else: + properties: + reg: + maxItems: 1 + +unevaluatedProperties: false + +examples: + - | + interrupt-controller@10200620 { + compatible = "mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq"; + reg = <0x10220620 0x20>, + <0x10220690 0x10>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <3>; + }; diff --git a/Bindings/interrupt-controller/mediatek,sysirq.txt b/Bindings/interrupt-controller/mediatek,sysirq.txt deleted file mode 100644 index 3ffc60184e4..00000000000 --- a/Bindings/interrupt-controller/mediatek,sysirq.txt +++ /dev/null @@ -1,44 +0,0 @@ -MediaTek sysirq - -MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI -interrupt. - -Required properties: -- compatible: should be - "mediatek,mt8516-sysirq", "mediatek,mt6577-sysirq": for MT8516 - "mediatek,mt8183-sysirq", "mediatek,mt6577-sysirq": for MT8183 - "mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq": for MT8173 - "mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135 - "mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127 - "mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622 - "mediatek,mt7623-sysirq", "mediatek,mt6577-sysirq": for MT7623 - "mediatek,mt7629-sysirq", "mediatek,mt6577-sysirq": for MT7629 - "mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795 - "mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797 - "mediatek,mt6779-sysirq", "mediatek,mt6577-sysirq": for MT6779 - "mediatek,mt6765-sysirq", "mediatek,mt6577-sysirq": for MT6765 - "mediatek,mt6755-sysirq", "mediatek,mt6577-sysirq": for MT6755 - "mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq": for MT6592 - "mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq": for MT6589 - "mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq": for MT6582 - "mediatek,mt6580-sysirq", "mediatek,mt6577-sysirq": for MT6580 - "mediatek,mt6577-sysirq": for MT6577 - "mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712 - "mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701 - "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq": for MT8365 -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt. -- reg: Physical base address of the intpol registers and length of memory - mapped region. Could be multiple bases here. Ex: mt6797 needs 2 reg, others - need 1. - -Example: - sysirq: intpol-controller@10200620 { - compatible = "mediatek,mt6797-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10220620 0 0x20>, - <0 0x10220690 0 0x10>; - }; diff --git a/Bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Bindings/interrupt-controller/renesas,rzg2l-irqc.yaml index d3b5aec0a3f..daef4ee06f4 100644 --- a/Bindings/interrupt-controller/renesas,rzg2l-irqc.yaml +++ b/Bindings/interrupt-controller/renesas,rzg2l-irqc.yaml @@ -44,7 +44,7 @@ properties: maxItems: 1 interrupts: - minItems: 41 + minItems: 45 items: - description: NMI interrupt - description: IRQ0 interrupt @@ -88,9 +88,15 @@ properties: - description: GPIO interrupt, TINT30 - description: GPIO interrupt, TINT31 - description: Bus error interrupt + - description: ECCRAM0 or combined ECCRAM0/1 1bit error interrupt + - description: ECCRAM0 or combined ECCRAM0/1 2bit error interrupt + - description: ECCRAM0 or combined ECCRAM0/1 error overflow interrupt + - description: ECCRAM1 1bit error interrupt + - description: ECCRAM1 2bit error interrupt + - description: ECCRAM1 error overflow interrupt interrupt-names: - minItems: 41 + minItems: 45 items: - const: nmi - const: irq0 @@ -134,6 +140,12 @@ properties: - const: tint30 - const: tint31 - const: bus-err + - const: ec7tie1-0 + - const: ec7tie2-0 + - const: ec7tiovf-0 + - const: ec7tie1-1 + - const: ec7tie2-1 + - const: ec7tiovf-1 clocks: maxItems: 2 @@ -156,6 +168,7 @@ required: - interrupt-controller - reg - interrupts + - interrupt-names - clocks - clock-names - power-domains @@ -169,16 +182,19 @@ allOf: compatible: contains: enum: - - renesas,r9a07g043u-irqc - renesas,r9a08g045-irqc then: properties: interrupts: - minItems: 42 + maxItems: 45 interrupt-names: - minItems: 42 - required: - - interrupt-names + maxItems: 45 + else: + properties: + interrupts: + minItems: 48 + interrupt-names: + minItems: 48 unevaluatedProperties: false @@ -233,7 +249,14 @@ examples: , , , - ; + , + , + , + , + , + , + , + ; interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3", "irq4", "irq5", "irq6", "irq7", @@ -244,7 +267,10 @@ examples: "tint16", "tint17", "tint18", "tint19", "tint20", "tint21", "tint22", "tint23", "tint24", "tint25", "tint26", "tint27", - "tint28", "tint29", "tint30", "tint31"; + "tint28", "tint29", "tint30", "tint31", + "bus-err", "ec7tie1-0", "ec7tie2-0", + "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1", + "ec7tiovf-1"; clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>, <&cpg CPG_MOD R9A07G044_IA55_PCLK>; clock-names = "clk", "pclk"; diff --git a/Bindings/interrupt-controller/starfive,jh8100-intc.yaml b/Bindings/interrupt-controller/starfive,jh8100-intc.yaml new file mode 100644 index 00000000000..ada5788602d --- /dev/null +++ b/Bindings/interrupt-controller/starfive,jh8100-intc.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/starfive,jh8100-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive External Interrupt Controller + +description: + StarFive SoC JH8100 contain a external interrupt controller. It can be used + to handle high-level input interrupt signals. It also send the output + interrupt signal to RISC-V PLIC. + +maintainers: + - Changhuang Liang + +properties: + compatible: + const: starfive,jh8100-intc + + reg: + maxItems: 1 + + clocks: + description: APB clock for the interrupt controller + maxItems: 1 + + resets: + description: APB reset for the interrupt controller + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - resets + - interrupts + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + interrupt-controller@12260000 { + compatible = "starfive,jh8100-intc"; + reg = <0x12260000 0x10000>; + clocks = <&syscrg_ne 76>; + resets = <&syscrg_ne 13>; + interrupts = <45>; + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/Bindings/iommu/arm,smmu.yaml b/Bindings/iommu/arm,smmu.yaml index a4042ae2477..5c130cf06a2 100644 --- a/Bindings/iommu/arm,smmu.yaml +++ b/Bindings/iommu/arm,smmu.yaml @@ -83,6 +83,7 @@ properties: - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500" items: - enum: + - qcom,qcm2290-smmu-500 - qcom,sa8775p-smmu-500 - qcom,sc7280-smmu-500 - qcom,sc8280xp-smmu-500 @@ -93,6 +94,7 @@ properties: - qcom,sm8350-smmu-500 - qcom,sm8450-smmu-500 - qcom,sm8550-smmu-500 + - qcom,sm8650-smmu-500 - const: qcom,adreno-smmu - const: qcom,smmu-500 - const: arm,mmu-500 @@ -462,6 +464,7 @@ allOf: compatible: items: - enum: + - qcom,qcm2290-smmu-500 - qcom,sm6115-smmu-500 - qcom,sm6125-smmu-500 - const: qcom,adreno-smmu @@ -484,7 +487,12 @@ allOf: - if: properties: compatible: - const: qcom,sm8450-smmu-500 + items: + - const: qcom,sm8450-smmu-500 + - const: qcom,adreno-smmu + - const: qcom,smmu-500 + - const: arm,mmu-500 + then: properties: clock-names: @@ -508,7 +516,13 @@ allOf: - if: properties: compatible: - const: qcom,sm8550-smmu-500 + items: + - enum: + - qcom,sm8550-smmu-500 + - qcom,sm8650-smmu-500 + - const: qcom,adreno-smmu + - const: qcom,smmu-500 + - const: arm,mmu-500 then: properties: clock-names: @@ -534,7 +548,6 @@ allOf: - cavium,smmu-v2 - marvell,ap806-smmu-500 - nvidia,smmu-500 - - qcom,qcm2290-smmu-500 - qcom,qdu1000-smmu-500 - qcom,sc7180-smmu-500 - qcom,sc8180x-smmu-500 @@ -544,7 +557,6 @@ allOf: - qcom,sdx65-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 - - qcom,sm8650-smmu-500 - qcom,x1e80100-smmu-500 then: properties: diff --git a/Bindings/leds/backlight/kinetic,ktd2801.yaml b/Bindings/leds/backlight/kinetic,ktd2801.yaml new file mode 100644 index 00000000000..b005065e0f4 --- /dev/null +++ b/Bindings/leds/backlight/kinetic,ktd2801.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/backlight/kinetic,ktd2801.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Kinetic Technologies KTD2801 one-wire backlight + +maintainers: + - Duje Mihanović + +description: | + The Kinetic Technologies KTD2801 is a LED backlight driver controlled + by a single GPIO line. The driver can be controlled with a PWM signal + or by pulsing the GPIO line to set the backlight level. This is called + "ExpressWire". + +allOf: + - $ref: common.yaml# + +properties: + compatible: + const: kinetic,ktd2801 + + ctrl-gpios: + maxItems: 1 + + default-brightness: true + max-brightness: true + +required: + - compatible + - ctrl-gpios + +additionalProperties: false + +examples: + - | + #include + + backlight { + compatible = "kinetic,ktd2801"; + ctrl-gpios = <&gpio 97 GPIO_ACTIVE_HIGH>; + max-brightness = <210>; + default-brightness = <100>; + }; diff --git a/Bindings/leds/backlight/qcom-wled.yaml b/Bindings/leds/backlight/qcom-wled.yaml index 5f1849bdabb..a8490781011 100644 --- a/Bindings/leds/backlight/qcom-wled.yaml +++ b/Bindings/leds/backlight/qcom-wled.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Technologies, Inc. WLED driver maintainers: - - Bjorn Andersson - - Kiran Gunda + - Bjorn Andersson + - Kiran Gunda description: | WLED (White Light Emitting Diode) driver is used for controlling display diff --git a/Bindings/leds/common.yaml b/Bindings/leds/common.yaml index 55a8d1385e2..8a3c2398b10 100644 --- a/Bindings/leds/common.yaml +++ b/Bindings/leds/common.yaml @@ -200,6 +200,18 @@ properties: #trigger-source-cells property in the source node. $ref: /schemas/types.yaml#/definitions/phandle-array + active-low: + type: boolean + description: + Makes LED active low. To turn the LED ON, line needs to be + set to low voltage instead of high. + + inactive-high-impedance: + type: boolean + description: + Set LED to high-impedance mode to turn the LED OFF. LED might also + describe this mode as tristate. + # Required properties for flash LED child nodes: flash-max-microamp: description: diff --git a/Bindings/leds/leds-bcm63138.yaml b/Bindings/leds/leds-bcm63138.yaml index 52252fb6bb3..bb20394fca5 100644 --- a/Bindings/leds/leds-bcm63138.yaml +++ b/Bindings/leds/leds-bcm63138.yaml @@ -52,10 +52,6 @@ patternProperties: maxItems: 1 description: LED pin number - active-low: - type: boolean - description: Makes LED active low - required: - reg diff --git a/Bindings/leds/leds-bcm6328.yaml b/Bindings/leds/leds-bcm6328.yaml index 51cc0d82c12..f3a3ef99292 100644 --- a/Bindings/leds/leds-bcm6328.yaml +++ b/Bindings/leds/leds-bcm6328.yaml @@ -78,10 +78,6 @@ patternProperties: - maximum: 23 description: LED pin number (only LEDs 0 to 23 are valid). - active-low: - type: boolean - description: Makes LED active low. - brcm,hardware-controlled: type: boolean description: Makes this LED hardware controlled. diff --git a/Bindings/leds/leds-bcm6358.txt b/Bindings/leds/leds-bcm6358.txt index 6e51c6b91ee..211ffc3c4a2 100644 --- a/Bindings/leds/leds-bcm6358.txt +++ b/Bindings/leds/leds-bcm6358.txt @@ -25,8 +25,6 @@ LED sub-node required properties: LED sub-node optional properties: - label : see Documentation/devicetree/bindings/leds/common.txt - - active-low : Boolean, makes LED active low. - Default : false - default-state : see Documentation/devicetree/bindings/leds/common.txt - linux,default-trigger : see diff --git a/Bindings/leds/leds-pwm-multicolor.yaml b/Bindings/leds/leds-pwm-multicolor.yaml index bd6ec04a872..a31a202afe5 100644 --- a/Bindings/leds/leds-pwm-multicolor.yaml +++ b/Bindings/leds/leds-pwm-multicolor.yaml @@ -41,9 +41,7 @@ properties: pwm-names: true - active-low: - description: For PWMs where the LED is wired to supply rather than ground. - type: boolean + active-low: true color: true diff --git a/Bindings/leds/leds-pwm.yaml b/Bindings/leds/leds-pwm.yaml index 7de6da58be3..113b7c21830 100644 --- a/Bindings/leds/leds-pwm.yaml +++ b/Bindings/leds/leds-pwm.yaml @@ -34,11 +34,6 @@ patternProperties: Maximum brightness possible for the LED $ref: /schemas/types.yaml#/definitions/uint32 - active-low: - description: - For PWMs where the LED is wired to supply rather than ground. - type: boolean - required: - pwms - max-brightness diff --git a/Bindings/leds/leds-qcom-lpg.yaml b/Bindings/leds/leds-qcom-lpg.yaml index ea84ad426df..54a428d3d46 100644 --- a/Bindings/leds/leds-qcom-lpg.yaml +++ b/Bindings/leds/leds-qcom-lpg.yaml @@ -11,7 +11,7 @@ maintainers: description: > The Qualcomm Light Pulse Generator consists of three different hardware blocks; - a ramp generator with lookup table, the light pulse generator and a three + a ramp generator with lookup table (LUT), the light pulse generator and a three channel current sink. These blocks are found in a wide range of Qualcomm PMICs. properties: @@ -63,6 +63,29 @@ properties: - description: dtest line to attach - description: flags for the attachment + nvmem: + description: > + This property is required for PMICs that supports PPG, which is when a + PMIC stores LPG per-channel data and pattern LUT in SDAM modules instead + of in a LUT peripheral. For PMICs, such as PM8350C, per-channel data + and pattern LUT is separated into 2 SDAM modules. In that case, phandles + to both SDAM modules need to be specified. + minItems: 1 + maxItems: 2 + + nvmem-names: + minItems: 1 + items: + - const: lpg_chan_sdam + - const: lut_sdam + + qcom,pbs: + $ref: /schemas/types.yaml#/definitions/phandle + description: > + Phandle of the Qualcomm Programmable Boot Sequencer node (PBS). + PBS node is used to trigger LPG pattern sequences for PMICs that support + single SDAM PPG. + multi-led: type: object $ref: leds-class-multicolor.yaml# @@ -106,6 +129,52 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,pm660l-lpg + - qcom,pm8150b-lpg + - qcom,pm8150l-lpg + - qcom,pm8916-pwm + - qcom,pm8941-lpg + - qcom,pm8994-lpg + - qcom,pmc8180c-lpg + - qcom,pmi8994-lpg + - qcom,pmi8998-lpg + - qcom,pmk8550-pwm + then: + properties: + nvmem: false + nvmem-names: false + + - if: + properties: + compatible: + contains: + const: qcom,pmi632-lpg + then: + properties: + nvmem: + maxItems: 1 + nvmem-names: + maxItems: 1 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pm8350c-pwm + then: + properties: + nvmem: + minItems: 2 + nvmem-names: + minItems: 2 + examples: - | #include @@ -191,4 +260,35 @@ examples: compatible = "qcom,pm8916-pwm"; #pwm-cells = <2>; }; + - | + #include + + led-controller { + compatible = "qcom,pmi632-lpg"; + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + nvmem-names = "lpg_chan_sdam"; + nvmem = <&pmi632_sdam_7>; + qcom,pbs = <&pmi632_pbs_client3>; + + led@1 { + reg = <1>; + color = ; + label = "red"; + }; + + led@2 { + reg = <2>; + color = ; + label = "green"; + }; + + led@3 { + reg = <3>; + color = ; + label = "blue"; + }; + }; + ... diff --git a/Bindings/leds/onnn,ncp5623.yaml b/Bindings/leds/onnn,ncp5623.yaml new file mode 100644 index 00000000000..9c9f3a682ba --- /dev/null +++ b/Bindings/leds/onnn,ncp5623.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/onnn,ncp5623.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ON Semiconductor NCP5623 multi-LED Driver + +maintainers: + - Abdel Alkuor + +description: + NCP5623 Triple Output I2C Controlled LED Driver. + https://www.onsemi.com/pdf/datasheet/ncp5623-d.pdf + +properties: + compatible: + enum: + - onnn,ncp5623 + + reg: + const: 0x38 + + multi-led: + type: object + $ref: leds-class-multicolor.yaml# + unevaluatedProperties: false + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^led@[0-2]$": + type: object + $ref: common.yaml# + unevaluatedProperties: false + + properties: + reg: + minimum: 0 + maximum: 2 + + required: + - reg + - color + + required: + - "#address-cells" + - "#size-cells" + +required: + - compatible + - reg + - multi-led + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + led-controller@38 { + compatible = "onnn,ncp5623"; + reg = <0x38>; + + multi-led { + color = ; + + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + }; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + }; + }; + }; diff --git a/Bindings/mailbox/fsl,mu.yaml b/Bindings/mailbox/fsl,mu.yaml index 12e7a7d536a..00631afcd51 100644 --- a/Bindings/mailbox/fsl,mu.yaml +++ b/Bindings/mailbox/fsl,mu.yaml @@ -29,8 +29,11 @@ properties: - const: fsl,imx8ulp-mu - const: fsl,imx8-mu-scu - const: fsl,imx8-mu-seco - - const: fsl,imx93-mu-s4 - const: fsl,imx8ulp-mu-s4 + - const: fsl,imx93-mu-s4 + - const: fsl,imx95-mu + - const: fsl,imx95-mu-ele + - const: fsl,imx95-mu-v2x - items: - const: fsl,imx93-mu - const: fsl,imx8ulp-mu @@ -95,6 +98,19 @@ properties: power-domains: maxItems: 1 + ranges: true + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + +patternProperties: + "^sram@[a-f0-9]+": + $ref: /schemas/sram/sram.yaml# + unevaluatedProperties: false + required: - compatible - reg @@ -122,6 +138,15 @@ allOf: required: - interrupt-names + - if: + not: + properties: + compatible: + const: fsl,imx95-mu + then: + patternProperties: + "^sram@[a-f0-9]+": false + additionalProperties: false examples: @@ -134,3 +159,34 @@ examples: interrupts = ; #mbox-cells = <2>; }; + + - | + #include + + mailbox@445b0000 { + compatible = "fsl,imx95-mu"; + reg = <0x445b0000 0x10000>; + ranges; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + #mbox-cells = <2>; + + sram@445b1000 { + compatible = "mmio-sram"; + reg = <0x445b1000 0x400>; + ranges = <0x0 0x445b1000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + scmi-sram-section@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x80>; + }; + + scmi-sram-section@80 { + compatible = "arm,scmi-shmem"; + reg = <0x80 0x80>; + }; + }; + }; diff --git a/Bindings/media/i2c/techwell,tw9900.yaml b/Bindings/media/i2c/techwell,tw9900.yaml index e37317f8107..c9673391afd 100644 --- a/Bindings/media/i2c/techwell,tw9900.yaml +++ b/Bindings/media/i2c/techwell,tw9900.yaml @@ -36,7 +36,7 @@ properties: properties: port@0: - $ref: /schemas/graph.yaml#/$defs/port-base + $ref: /schemas/graph.yaml#/properties/port description: Analog input port properties: diff --git a/Bindings/media/mediatek,vcodec-encoder.yaml b/Bindings/media/mediatek,vcodec-encoder.yaml index a2051b31fa2..b45743d0a9e 100644 --- a/Bindings/media/mediatek,vcodec-encoder.yaml +++ b/Bindings/media/mediatek,vcodec-encoder.yaml @@ -16,14 +16,18 @@ description: |+ properties: compatible: - enum: - - mediatek,mt8173-vcodec-enc-vp8 - - mediatek,mt8173-vcodec-enc - - mediatek,mt8183-vcodec-enc - - mediatek,mt8188-vcodec-enc - - mediatek,mt8192-vcodec-enc - - mediatek,mt8195-vcodec-enc - + oneOf: + - items: + - enum: + - mediatek,mt8173-vcodec-enc-vp8 + - mediatek,mt8173-vcodec-enc + - mediatek,mt8183-vcodec-enc + - mediatek,mt8188-vcodec-enc + - mediatek,mt8192-vcodec-enc + - mediatek,mt8195-vcodec-enc + - items: + - const: mediatek,mt8186-vcodec-enc + - const: mediatek,mt8183-vcodec-enc reg: maxItems: 1 @@ -109,10 +113,7 @@ allOf: properties: compatible: enum: - - mediatek,mt8173-vcodec-enc - - mediatek,mt8188-vcodec-enc - - mediatek,mt8192-vcodec-enc - - mediatek,mt8195-vcodec-enc + - mediatek,mt8173-vcodec-enc-vp8 then: properties: @@ -122,8 +123,8 @@ allOf: maxItems: 1 clock-names: items: - - const: venc_sel - else: # for vp8 hw encoder + - const: venc_lt_sel + else: properties: clock: items: @@ -131,7 +132,7 @@ allOf: maxItems: 1 clock-names: items: - - const: venc_lt_sel + - const: venc_sel additionalProperties: false diff --git a/Bindings/media/mediatek-jpeg-encoder.yaml b/Bindings/media/mediatek-jpeg-encoder.yaml index 37800e1908c..83c020a673d 100644 --- a/Bindings/media/mediatek-jpeg-encoder.yaml +++ b/Bindings/media/mediatek-jpeg-encoder.yaml @@ -38,7 +38,8 @@ properties: maxItems: 1 iommus: - maxItems: 2 + minItems: 2 + maxItems: 4 description: | Points to the respective IOMMU block with master port as argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. diff --git a/Bindings/media/rockchip-isp1.yaml b/Bindings/media/rockchip-isp1.yaml index afcaa427d48..6be00aca418 100644 --- a/Bindings/media/rockchip-isp1.yaml +++ b/Bindings/media/rockchip-isp1.yaml @@ -16,6 +16,7 @@ description: | properties: compatible: enum: + - fsl,imx8mp-isp - rockchip,px30-cif-isp - rockchip,rk3399-cif-isp @@ -36,9 +37,9 @@ properties: minItems: 3 items: # isp0 and isp1 - - description: ISP clock - - description: ISP AXI clock - - description: ISP AHB clock + - description: ISP clock (for imx8mp, clk) + - description: ISP AXI clock (for imx8mp, m_hclk) + - description: ISP AHB clock (for imx8mp, hclk) # only for isp1 - description: ISP Pixel clock @@ -52,6 +53,13 @@ properties: # only for isp1 - const: pclk + fsl,blk-ctrl: + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + description: + A phandle to the media block control for the ISP, followed by a cell + containing the index of the gasket. + iommus: maxItems: 1 @@ -113,9 +121,6 @@ required: - interrupts - clocks - clock-names - - iommus - - phys - - phy-names - power-domains - ports @@ -143,6 +148,26 @@ allOf: required: - interrupt-names + - if: + properties: + compatible: + contains: + const: fsl,imx8mp-isp + then: + properties: + iommus: false + phys: false + phy-names: false + required: + - fsl,blk-ctrl + else: + properties: + fsl,blk-ctrl: false + required: + - iommus + - phys + - phy-names + additionalProperties: false examples: diff --git a/Bindings/media/st,stm32mp25-video-codec.yaml b/Bindings/media/st,stm32mp25-video-codec.yaml new file mode 100644 index 00000000000..b8611bc8756 --- /dev/null +++ b/Bindings/media/st,stm32mp25-video-codec.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/st,stm32mp25-video-codec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32MP25 VDEC video decoder & VENC video encoder + +maintainers: + - Hugues Fruchet + +description: + The STMicroelectronics STM32MP25 SOCs embeds a VDEC video hardware + decoder peripheral based on Verisilicon VC8000NanoD IP (former Hantro G1) + and a VENC video hardware encoder peripheral based on Verisilicon + VC8000NanoE IP (former Hantro H1). + +properties: + compatible: + enum: + - st,stm32mp25-vdec + - st,stm32mp25-venc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + video-codec@580d0000 { + compatible = "st,stm32mp25-vdec"; + reg = <0x580d0000 0x3c8>; + interrupts = ; + clocks = <&ck_icn_p_vdec>; + }; diff --git a/Bindings/memory-controllers/fsl/fsl,imx-weim-peripherals.yaml b/Bindings/memory-controllers/fsl/fsl,imx-weim-peripherals.yaml new file mode 100644 index 00000000000..82fc5f4a1ed --- /dev/null +++ b/Bindings/memory-controllers/fsl/fsl,imx-weim-peripherals.yaml @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,imx-weim-peripherals.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX WEIM Bus Peripheral Nodes + +maintainers: + - Shawn Guo + - Sascha Hauer + +description: + This binding is meant for the child nodes of the WEIM node. The node + represents any device connected to the WEIM bus. It may be a Flash chip, + RAM chip or Ethernet controller, etc. These properties are meant for + configuring the WEIM settings/timings and will accompany the bindings + supported by the respective device. + +properties: + reg: true + + fsl,weim-cs-timing: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Timing values for the child node. + minItems: 2 + maxItems: 6 + +# the WEIM child will have its own native properties +additionalProperties: true diff --git a/Bindings/memory-controllers/fsl/fsl,imx-weim.yaml b/Bindings/memory-controllers/fsl/fsl,imx-weim.yaml new file mode 100644 index 00000000000..3f40ca5b13f --- /dev/null +++ b/Bindings/memory-controllers/fsl/fsl,imx-weim.yaml @@ -0,0 +1,204 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,imx-weim.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX Wireless External Interface Module (WEIM) + +maintainers: + - Shawn Guo + - Sascha Hauer + +description: + The term "wireless" does not imply that the WEIM is literally an interface + without wires. It simply means that this module was originally designed for + wireless and mobile applications that use low-power technology. The actual + devices are instantiated from the child nodes of a WEIM node. + +properties: + $nodename: + pattern: "^memory-controller@[0-9a-f]+$" + + compatible: + oneOf: + - enum: + - fsl,imx1-weim + - fsl,imx27-weim + - fsl,imx50-weim + - fsl,imx51-weim + - fsl,imx6q-weim + - items: + - enum: + - fsl,imx31-weim + - fsl,imx35-weim + - const: fsl,imx27-weim + - items: + - enum: + - fsl,imx6sx-weim + - fsl,imx6ul-weim + - const: fsl,imx6q-weim + + "#address-cells": + const: 2 + + "#size-cells": + const: 1 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + + ranges: true + + fsl,weim-cs-gpr: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + Phandle to the system General Purpose Register controller that contains + WEIM CS GPR register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0] + should be set up as one of the following 4 possible values depending on + the CS space configuration. + + IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3 + --------------------------------------------- + 05 128M 0M 0M 0M + 033 64M 64M 0M 0M + 0113 64M 32M 32M 0M + 01111 32M 32M 32M 32M + + In case that the property is absent, the reset value or what bootloader + sets up in IOMUXC_GPR1[11:0] will be used. + + fsl,burst-clk-enable: + type: boolean + description: + The presence of this property indicates that the weim bus should operate + in Burst Clock Mode. + + fsl,continuous-burst-clk: + type: boolean + description: + Make Burst Clock to output continuous clock. Without this option Burst + Clock will output clock only when necessary. + +patternProperties: + "^.*@[0-7],[0-9a-f]+$": + type: object + description: Devices attached to chip selects are represented as subnodes. + $ref: fsl,imx-weim-peripherals.yaml + additionalProperties: true + required: + - fsl,weim-cs-timing + +required: + - compatible + - reg + - clocks + - "#address-cells" + - "#size-cells" + - ranges + +allOf: + - if: + properties: + compatible: + not: + contains: + enum: + - fsl,imx50-weim + - fsl,imx6q-weim + then: + properties: + fsl,weim-cs-gpr: false + fsl,burst-clk-enable: false + - if: + not: + required: + - fsl,burst-clk-enable + then: + properties: + fsl,continuous-burst-clk: false + - if: + properties: + compatible: + contains: + const: fsl,imx1-weim + then: + patternProperties: + "^.*@[0-7],[0-9a-f]+$": + properties: + fsl,weim-cs-timing: + items: + items: + - description: CSxU + - description: CSxL + - if: + properties: + compatible: + contains: + enum: + - fsl,imx27-weim + - fsl,imx31-weim + - fsl,imx35-weim + then: + patternProperties: + "^.*@[0-7],[0-9a-f]+$": + properties: + fsl,weim-cs-timing: + items: + items: + - description: CSCRxU + - description: CSCRxL + - description: CSCRxA + - if: + properties: + compatible: + contains: + enum: + - fsl,imx50-weim + - fsl,imx51-weim + - fsl,imx6q-weim + - fsl,imx6sx-weim + - fsl,imx6ul-weim + then: + patternProperties: + "^.*@[0-7],[0-9a-f]+$": + properties: + fsl,weim-cs-timing: + items: + items: + - description: CSxGCR1 + - description: CSxGCR2 + - description: CSxRCR1 + - description: CSxRCR2 + - description: CSxWCR1 + - description: CSxWCR2 + +additionalProperties: false + +examples: + - | + memory-controller@21b8000 { + compatible = "fsl,imx6q-weim"; + reg = <0x021b8000 0x4000>; + clocks = <&clks 196>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x08000000 0x08000000>; + fsl,weim-cs-gpr = <&gpr>; + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x02000000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 + 0x0000c000 0x1404a38e 0x00000000>; + }; + }; diff --git a/Bindings/memory-controllers/mc-peripheral-props.yaml b/Bindings/memory-controllers/mc-peripheral-props.yaml index 8d9dae15ade..00deeb09f87 100644 --- a/Bindings/memory-controllers/mc-peripheral-props.yaml +++ b/Bindings/memory-controllers/mc-peripheral-props.yaml @@ -37,5 +37,6 @@ allOf: - $ref: ingenic,nemc-peripherals.yaml# - $ref: intel,ixp4xx-expansion-peripheral-props.yaml# - $ref: ti,gpmc-child.yaml# + - $ref: fsl/fsl,imx-weim-peripherals.yaml additionalProperties: true diff --git a/Bindings/memory-controllers/nvidia,tegra20-emc.yaml b/Bindings/memory-controllers/nvidia,tegra20-emc.yaml index f54e553e6c0..71896cb1069 100644 --- a/Bindings/memory-controllers/nvidia,tegra20-emc.yaml +++ b/Bindings/memory-controllers/nvidia,tegra20-emc.yaml @@ -145,7 +145,7 @@ patternProperties: "^emc-table@[0-9]+$": $ref: "#/$defs/emc-table" - "^emc-tables@[a-z0-9-]+$": + "^emc-tables@[a-f0-9-]+$": type: object properties: reg: diff --git a/Bindings/memory-controllers/renesas,rpc-if.yaml b/Bindings/memory-controllers/renesas,rpc-if.yaml index 25f3bb9890a..d7745dd53b5 100644 --- a/Bindings/memory-controllers/renesas,rpc-if.yaml +++ b/Bindings/memory-controllers/renesas,rpc-if.yaml @@ -45,6 +45,7 @@ properties: - items: - enum: - renesas,r8a779g0-rpc-if # R-Car V4H + - renesas,r8a779h0-rpc-if # R-Car V4M - const: renesas,rcar-gen4-rpc-if # a generic R-Car gen4 device - items: diff --git a/Bindings/memory-controllers/st,stm32-fmc2-ebi.yaml b/Bindings/memory-controllers/st,stm32-fmc2-ebi.yaml index 14f1833d37c..84ac6f50a6f 100644 --- a/Bindings/memory-controllers/st,stm32-fmc2-ebi.yaml +++ b/Bindings/memory-controllers/st,stm32-fmc2-ebi.yaml @@ -23,7 +23,9 @@ maintainers: properties: compatible: - const: st,stm32mp1-fmc2-ebi + enum: + - st,stm32mp1-fmc2-ebi + - st,stm32mp25-fmc2-ebi reg: maxItems: 1 @@ -34,6 +36,9 @@ properties: resets: maxItems: 1 + power-domains: + maxItems: 1 + "#address-cells": const: 2 diff --git a/Bindings/mfd/atmel,hlcdc.yaml b/Bindings/mfd/atmel,hlcdc.yaml new file mode 100644 index 00000000000..4aa36903e75 --- /dev/null +++ b/Bindings/mfd/atmel,hlcdc.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/atmel,hlcdc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel's HLCD Controller + +maintainers: + - Nicolas Ferre + - Alexandre Belloni + - Claudiu Beznea + +description: + The Atmel HLCDC (HLCD Controller) IP available on Atmel SoCs exposes two + subdevices, a PWM chip and a Display Controller. + +properties: + compatible: + enum: + - atmel,at91sam9n12-hlcdc + - atmel,at91sam9x5-hlcdc + - atmel,sama5d2-hlcdc + - atmel,sama5d3-hlcdc + - atmel,sama5d4-hlcdc + - microchip,sam9x60-hlcdc + - microchip,sam9x75-xlcdc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 3 + + clock-names: + items: + - const: periph_clk + - const: sys_clk + - const: slow_clk + - const: lvds_pll_clk + minItems: 3 + + display-controller: + $ref: /schemas/display/atmel/atmel,hlcdc-display-controller.yaml + + pwm: + $ref: /schemas/pwm/atmel,hlcdc-pwm.yaml + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + #include + + lcd_controller: lcd-controller@f0030000 { + compatible = "atmel,sama5d3-hlcdc"; + reg = <0xf0030000 0x2000>; + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names = "periph_clk", "sys_clk", "slow_clk"; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; + + display-controller { + compatible = "atmel,hlcdc-display-controller"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + hlcdc_panel_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; + }; + }; + + pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; + }; diff --git a/Bindings/mfd/atmel,sama5d2-flexcom.yaml b/Bindings/mfd/atmel,sama5d2-flexcom.yaml new file mode 100644 index 00000000000..0dc6a40b63f --- /dev/null +++ b/Bindings/mfd/atmel,sama5d2-flexcom.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/atmel,sama5d2-flexcom.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Flexcom (Flexible Serial Communication Unit) + +maintainers: + - Kavyasree Kotagiri + +description: + The Microchip Flexcom is just a wrapper which embeds a SPI controller, + an I2C controller and an USART. Only one function can be used at a + time and is chosen at boot time according to the device tree. + +properties: + compatible: + oneOf: + - const: atmel,sama5d2-flexcom + - items: + - const: microchip,sam9x7-flexcom + - const: atmel,sama5d2-flexcom + - items: + - const: microchip,sama7g5-flexcom + - const: atmel,sama5d2-flexcom + + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: + description: + One range for the full I/O register region. (including USART, + TWI and SPI registers). + items: + maxItems: 3 + + atmel,flexcom-mode: + description: | + Specifies the flexcom mode as follows: + 1: USART + 2: SPI + 3: I2C. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3] + +patternProperties: + "^serial@[0-9a-f]+$": + type: object + description: + Child node describing USART. See atmel-usart.txt for details + of USART bindings. + + "^spi@[0-9a-f]+$": + type: object + description: + Child node describing SPI. See ../spi/spi_atmel.txt for details + of SPI bindings. + + "^i2c@[0-9a-f]+$": + $ref: /schemas/i2c/atmel,at91sam-i2c.yaml + description: + Child node describing I2C. + +required: + - compatible + - reg + - clocks + - "#address-cells" + - "#size-cells" + - ranges + - atmel,flexcom-mode + +additionalProperties: false + +examples: + - | + #include + + flx0: flexcom@f8034000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xf8034000 0x200>; + clocks = <&flx0_clk>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8034000 0x800>; + atmel,flexcom-mode = <2>; + }; +... diff --git a/Bindings/mfd/atmel-flexcom.txt b/Bindings/mfd/atmel-flexcom.txt deleted file mode 100644 index af692e8833a..00000000000 --- a/Bindings/mfd/atmel-flexcom.txt +++ /dev/null @@ -1,64 +0,0 @@ -* Device tree bindings for Atmel Flexcom (Flexible Serial Communication Unit) - -The Atmel Flexcom is just a wrapper which embeds a SPI controller, an I2C -controller and an USART. Only one function can be used at a time and is chosen -at boot time according to the device tree. - -Required properties: -- compatible: Should be "atmel,sama5d2-flexcom" - or "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom" -- reg: Should be the offset/length value for Flexcom dedicated - I/O registers (without USART, TWI or SPI registers). -- clocks: Should be the Flexcom peripheral clock from PMC. -- #address-cells: Should be <1> -- #size-cells: Should be <1> -- ranges: Should be one range for the full I/O register region - (including USART, TWI and SPI registers). -- atmel,flexcom-mode: Should be one of the following values: - - <1> for USART - - <2> for SPI - - <3> for I2C - -Required child: -A single available child device of type matching the "atmel,flexcom-mode" -property. - -The phandle provided by the clocks property of the child is the same as one for -the Flexcom parent. - -For other properties, please refer to the documentations of the respective -device: -- ../serial/atmel-usart.txt -- ../spi/spi_atmel.txt -- ../i2c/i2c-at91.txt - -Example: - -flexcom@f8034000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8034000 0x200>; - clocks = <&flx0_clk>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8034000 0x800>; - atmel,flexcom-mode = <2>; - - spi@400 { - compatible = "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx0_default>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&flx0_clk>; - clock-names = "spi_clk"; - atmel,fifo-size = <32>; - - flash@0 { - compatible = "atmel,at25f512b"; - reg = <0>; - spi-max-frequency = <20000000>; - }; - }; -}; diff --git a/Bindings/mfd/atmel-hlcdc.txt b/Bindings/mfd/atmel-hlcdc.txt deleted file mode 100644 index 7de696eefae..00000000000 --- a/Bindings/mfd/atmel-hlcdc.txt +++ /dev/null @@ -1,56 +0,0 @@ -Device-Tree bindings for Atmel's HLCDC (High LCD Controller) MFD driver - -Required properties: - - compatible: value should be one of the following: - "atmel,at91sam9n12-hlcdc" - "atmel,at91sam9x5-hlcdc" - "atmel,sama5d2-hlcdc" - "atmel,sama5d3-hlcdc" - "atmel,sama5d4-hlcdc" - "microchip,sam9x60-hlcdc" - "microchip,sam9x75-xlcdc" - - reg: base address and size of the HLCDC device registers. - - clock-names: the name of the 3 clocks requested by the HLCDC device. - Should contain "periph_clk", "sys_clk" and "slow_clk". - - clocks: should contain the 3 clocks requested by the HLCDC device. - - interrupts: should contain the description of the HLCDC interrupt line - -The HLCDC IP exposes two subdevices: - - a PWM chip: see ../pwm/atmel-hlcdc-pwm.txt - - a Display Controller: see ../display/atmel/hlcdc-dc.txt - -Example: - - hlcdc: hlcdc@f0030000 { - compatible = "atmel,sama5d3-hlcdc"; - reg = <0xf0030000 0x2000>; - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; - clock-names = "periph_clk","sys_clk", "slow_clk"; - interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; - - hlcdc-display-controller { - compatible = "atmel,hlcdc-display-controller"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - hlcdc_panel_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwm>; - #pwm-cells = <3>; - }; - }; diff --git a/Bindings/mfd/da9062.txt b/Bindings/mfd/da9062.txt deleted file mode 100644 index e4eedd3bd23..00000000000 --- a/Bindings/mfd/da9062.txt +++ /dev/null @@ -1,124 +0,0 @@ -* Dialog DA9062 Power Management Integrated Circuit (PMIC) - -Product information for the DA9062 and DA9061 devices can be found here: -- https://www.dialog-semiconductor.com/products/da9062 -- https://www.dialog-semiconductor.com/products/da9061 - -The DA9062 PMIC consists of: - -Device Supply Names Description ------- ------------ ----------- -da9062-regulator : : LDOs & BUCKs -da9062-rtc : : Real-Time Clock -da9062-onkey : : On Key -da9062-watchdog : : Watchdog Timer -da9062-thermal : : Thermal -da9062-gpio : : GPIOs - -The DA9061 PMIC consists of: - -Device Supply Names Description ------- ------------ ----------- -da9062-regulator : : LDOs & BUCKs -da9062-onkey : : On Key -da9062-watchdog : : Watchdog Timer -da9062-thermal : : Thermal - -====== - -Required properties: - -- compatible : Should be - "dlg,da9062" for DA9062 - "dlg,da9061" for DA9061 -- reg : Specifies the I2C slave address (this defaults to 0x58 but it can be - modified to match the chip's OTP settings). - -Optional properties: - -- gpio-controller : Marks the device as a gpio controller. -- #gpio-cells : Should be two. The first cell is the pin number and the - second cell is used to specify the gpio polarity. - -See Documentation/devicetree/bindings/gpio/gpio.txt for further information on -GPIO bindings. - -- interrupts : IRQ line information. -- interrupt-controller - -See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for -further information on IRQ bindings. - -Sub-nodes: - -- regulators : This node defines the settings for the LDOs and BUCKs. - The DA9062 regulators are bound using their names listed below: - - buck1 : BUCK_1 - buck2 : BUCK_2 - buck3 : BUCK_3 - buck4 : BUCK_4 - ldo1 : LDO_1 - ldo2 : LDO_2 - ldo3 : LDO_3 - ldo4 : LDO_4 - - The DA9061 regulators are bound using their names listed below: - - buck1 : BUCK_1 - buck2 : BUCK_2 - buck3 : BUCK_3 - ldo1 : LDO_1 - ldo2 : LDO_2 - ldo3 : LDO_3 - ldo4 : LDO_4 - - The component follows the standard regulator framework and the bindings - details of individual regulator device can be found in: - Documentation/devicetree/bindings/regulator/regulator.txt - - regulator-initial-mode may be specified for buck regulators using mode values - from include/dt-bindings/regulator/dlg,da9063-regulator.h. - -- rtc : This node defines settings required for the Real-Time Clock associated - with the DA9062. There are currently no entries in this binding, however - compatible = "dlg,da9062-rtc" should be added if a node is created. - -- onkey : See ../input/da9062-onkey.txt - -- watchdog: See ../watchdog/da9062-wdt.txt - -- thermal : See ../thermal/da9062-thermal.txt - -Example: - - pmic0: da9062@58 { - compatible = "dlg,da9062"; - reg = <0x58>; - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - rtc { - compatible = "dlg,da9062-rtc"; - }; - - regulators { - DA9062_BUCK1: buck1 { - regulator-name = "BUCK1"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <500000>; - regulator-max-microamp = <2000000>; - regulator-initial-mode = ; - regulator-boot-on; - }; - DA9062_LDO1: ldo1 { - regulator-name = "LDO_1"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - regulator-boot-on; - }; - }; - }; - diff --git a/Bindings/mfd/dlg,da9063.yaml b/Bindings/mfd/dlg,da9063.yaml index c5a7e10d7d8..51612dc2274 100644 --- a/Bindings/mfd/dlg,da9063.yaml +++ b/Bindings/mfd/dlg,da9063.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mfd/dlg,da9063.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Dialog DA9063/DA9063L Power Management Integrated Circuit (PMIC) +title: Dialog DA906{3L,3,2,1} Power Management Integrated Circuit (PMIC) maintainers: - Steve Twiss @@ -17,10 +17,17 @@ description: | moment where all voltage monitors are disabled. Next, as da9063 only supports UV *and* OV monitoring, both must be set to the same severity and value (0: disable, 1: enable). + Product information for the DA906{3L,3,2,1} devices can be found here: + - https://www.dialog-semiconductor.com/products/da9063l + - https://www.dialog-semiconductor.com/products/da9063 + - https://www.dialog-semiconductor.com/products/da9062 + - https://www.dialog-semiconductor.com/products/da9061 properties: compatible: enum: + - dlg,da9061 + - dlg,da9062 - dlg,da9063 - dlg,da9063l @@ -35,20 +42,28 @@ properties: "#interrupt-cells": const: 2 - dlg,use-sw-pm: - type: boolean - description: - Disable the watchdog during suspend. - Only use this option if you can't use the watchdog automatic suspend - function during a suspend (see register CONTROL_B). + gpio-controller: true - watchdog: + "#gpio-cells": + const: 2 + + gpio: type: object - $ref: /schemas/watchdog/watchdog.yaml# - unevaluatedProperties: false + additionalProperties: false properties: compatible: - const: dlg,da9063-watchdog + const: dlg,da9062-gpio + + onkey: + $ref: /schemas/input/dlg,da9062-onkey.yaml + + regulators: + type: object + additionalProperties: false + patternProperties: + "^(ldo([1-9]|1[01])|bcore([1-2]|s-merged)|b(pro|mem|io|peri)|bmem-bio-merged|buck[1-4])$": + $ref: /schemas/regulator/regulator.yaml + unevaluatedProperties: false rtc: type: object @@ -56,37 +71,86 @@ properties: unevaluatedProperties: false properties: compatible: - const: dlg,da9063-rtc + enum: + - dlg,da9062-rtc + - dlg,da9063-rtc - onkey: + thermal: + $ref: /schemas/thermal/dlg,da9062-thermal.yaml + + watchdog: + $ref: /schemas/watchdog/dlg,da9062-watchdog.yaml + +patternProperties: + "^(.+-hog(-[0-9]+)?)$": type: object - $ref: /schemas/input/input.yaml# - unevaluatedProperties: false - properties: - compatible: - const: dlg,da9063-onkey - dlg,disable-key-power: - type: boolean - description: | - Disable power-down using a long key-press. - If this entry does not exist then by default the key-press triggered - power down is enabled and the OnKey will support both KEY_POWER and - KEY_SLEEP. - - regulators: - type: object - additionalProperties: false - patternProperties: - "^(ldo([1-9]|1[01])|bcore([1-2]|s-merged)|b(pro|mem|io|peri)|bmem-bio-merged)$": - $ref: /schemas/regulator/regulator.yaml - unevaluatedProperties: false + required: + - gpio-hog required: - compatible - reg - - interrupts - - interrupt-controller + +allOf: + - if: + properties: + compatible: + contains: + enum: + - dlg,da9063 + - dlg,da9063l + then: + properties: + gpio-controller: false + "#gpio-cells": false + gpio: false + regulators: + patternProperties: + "^buck[1-4]$": false + thermal: false + required: + - interrupts + - interrupt-controller + - '#interrupt-cells' + + - if: + properties: + compatible: + contains: + enum: + - dlg,da9062 + then: + properties: + regulators: + patternProperties: + "^(ldo([5-9]|10|11)|bcore([1-2]|s-merged)|b(pro|mem|io|peri)|bmem-bio-merged)$": false + required: + - gpio + - onkey + - rtc + - thermal + - watchdog + + - if: + properties: + compatible: + contains: + enum: + - dlg,da9061 + then: + properties: + gpio-controller: false + "#gpio-cells": false + gpio: false + regulators: + patternProperties: + "^(ldo([5-9]|10|11)|bcore([1-2]|s-merged)|b(pro|mem|io|peri)|bmem-bio-merged|buck4)$": false + rtc: false + required: + - onkey + - thermal + - watchdog additionalProperties: false @@ -99,10 +163,10 @@ examples: pmic@58 { compatible = "dlg,da9063"; reg = <0x58>; - #interrupt-cells = <2>; interrupt-parent = <&gpio6>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; + #interrupt-cells = <2>; rtc { compatible = "dlg,da9063-rtc"; @@ -143,4 +207,121 @@ examples: }; }; }; + + - | + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + pmic@58 { + compatible = "dlg,da9062"; + reg = <0x58>; + gpio-controller; + #gpio-cells = <2>; + + sd0-pwr-sel-hog { + gpio-hog; + gpios = <1 0>; + input; + line-name = "SD0_PWR_SEL"; + }; + + sd1-pwr-sel-hog { + gpio-hog; + gpios = <2 0>; + input; + line-name = "SD1_PWR_SEL"; + }; + + sw-et0-en-hog { + gpio-hog; + gpios = <3 0>; + input; + line-name = "SW_ET0_EN#"; + }; + + pmic-good-hog { + gpio-hog; + gpios = <4 0>; + output-high; + line-name = "PMIC_PGOOD"; + }; + + gpio { + compatible = "dlg,da9062-gpio"; + }; + + onkey { + compatible = "dlg,da9062-onkey"; + }; + + regulators { + buck1 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1380000>; + regulator-initial-mode = ; + regulator-always-on; + }; + buck2 { + regulator-name = "vdd_soc"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1380000>; + regulator-initial-mode = ; + regulator-always-on; + }; + buck3 { + regulator-name = "vdd_ddr3"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-initial-mode = ; + regulator-always-on; + }; + buck4 { + regulator-name = "vdd_eth"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + }; + ldo1 { + regulator-name = "vdd_snvs"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + ldo2 { + regulator-name = "vdd_high"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + ldo3 { + regulator-name = "vdd_eth_io"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + ldo4 { + regulator-name = "vdd_emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + + rtc { + compatible = "dlg,da9062-rtc"; + }; + + thermal { + compatible = "dlg,da9062-thermal"; + }; + + watchdog { + compatible = "dlg,da9062-watchdog"; + dlg,use-sw-pm; + }; + }; + }; ... diff --git a/Bindings/mfd/google,cros-ec.yaml b/Bindings/mfd/google,cros-ec.yaml index e1ca4f297c6..aac8819bd00 100644 --- a/Bindings/mfd/google,cros-ec.yaml +++ b/Bindings/mfd/google,cros-ec.yaml @@ -93,6 +93,11 @@ properties: '#size-cells': const: 0 + '#gpio-cells': + const: 2 + + gpio-controller: true + typec: $ref: /schemas/chrome/google,cros-ec-typec.yaml# @@ -275,6 +280,8 @@ examples: interrupts = <99 0>; interrupt-parent = <&gpio7>; spi-max-frequency = <5000000>; + #gpio-cells = <2>; + gpio-controller; proximity { compatible = "google,cros-ec-mkbp-proximity"; diff --git a/Bindings/mfd/iqs62x.yaml b/Bindings/mfd/iqs62x.yaml index 044cd7542c2..f438c237496 100644 --- a/Bindings/mfd/iqs62x.yaml +++ b/Bindings/mfd/iqs62x.yaml @@ -31,7 +31,7 @@ properties: maxItems: 1 firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: Specifies the name of the calibration and configuration file selected by the driver. If this property is omitted, the name is chosen based on the diff --git a/Bindings/mfd/qcom,tcsr.yaml b/Bindings/mfd/qcom,tcsr.yaml index 798705ab6a4..b97d7701533 100644 --- a/Bindings/mfd/qcom,tcsr.yaml +++ b/Bindings/mfd/qcom,tcsr.yaml @@ -19,6 +19,7 @@ properties: - enum: - qcom,msm8976-tcsr - qcom,msm8998-tcsr + - qcom,qcm2290-tcsr - qcom,qcs404-tcsr - qcom,sc7180-tcsr - qcom,sc7280-tcsr @@ -28,6 +29,7 @@ properties: - qcom,sdx55-tcsr - qcom,sdx65-tcsr - qcom,sm4450-tcsr + - qcom,sm6115-tcsr - qcom,sm8150-tcsr - qcom,sm8250-tcsr - qcom,sm8350-tcsr diff --git a/Bindings/mfd/syscon.yaml b/Bindings/mfd/syscon.yaml index 084b5c2a2a3..9d55bee155c 100644 --- a/Bindings/mfd/syscon.yaml +++ b/Bindings/mfd/syscon.yaml @@ -72,7 +72,10 @@ properties: - rockchip,rk3588-qos - rockchip,rv1126-qos - starfive,jh7100-sysmain + - ti,am62-usb-phy-ctrl - ti,am654-dss-oldi-io-ctrl + - ti,am654-serdes-ctrl + - ti,j784s4-pcie-ctrl - const: syscon diff --git a/Bindings/mfd/ti,twl.yaml b/Bindings/mfd/ti,twl.yaml index c04d57ba22b..52ed228fb1e 100644 --- a/Bindings/mfd/ti,twl.yaml +++ b/Bindings/mfd/ti,twl.yaml @@ -34,6 +34,8 @@ properties: interrupt-controller: true + system-power-controller: true + "#interrupt-cells": const: 1 diff --git a/Bindings/mips/cpus.yaml b/Bindings/mips/cpus.yaml index cf382dea392..a85137add66 100644 --- a/Bindings/mips/cpus.yaml +++ b/Bindings/mips/cpus.yaml @@ -23,22 +23,23 @@ properties: - brcm,bmips4380 - brcm,bmips5000 - brcm,bmips5200 - - ingenic,xburst-mxu1.0 + - img,i6500 - ingenic,xburst-fpu1.0-mxu1.1 - ingenic,xburst-fpu2.0-mxu2.0 + - ingenic,xburst-mxu1.0 - ingenic,xburst2-fpu2.1-mxu2.1-smt - loongson,gs264 - mips,m14Kc - - mips,mips4Kc - - mips,mips4KEc - - mips,mips24Kc - - mips,mips24KEc - - mips,mips74Kc - mips,mips1004Kc + - mips,mips24KEc + - mips,mips24Kc + - mips,mips4KEc + - mips,mips4Kc + - mips,mips74Kc - mti,interaptiv - - mti,mips24KEc - mti,mips14KEc - mti,mips14Kc + - mti,mips24KEc reg: maxItems: 1 diff --git a/Bindings/mips/mobileye.yaml b/Bindings/mips/mobileye.yaml new file mode 100644 index 00000000000..831975f6b47 --- /dev/null +++ b/Bindings/mips/mobileye.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +# Copyright 2023 Mobileye Vision Technologies Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/mobileye.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye SoC series + +maintainers: + - Vladimir Kondratiev + - Gregory CLEMENT + - Théo Lebrun + +description: + Boards with a Mobileye SoC shall have the following properties. + +properties: + $nodename: + const: '/' + + compatible: + oneOf: + - description: Boards with Mobileye EyeQ5 SoC + items: + - enum: + - mobileye,eyeq5-epm5 + - const: mobileye,eyeq5 + +additionalProperties: true + +... diff --git a/Bindings/misc/qcom,fastrpc.yaml b/Bindings/misc/qcom,fastrpc.yaml index 2dc3e245fa5..c27a8f33d8d 100644 --- a/Bindings/misc/qcom,fastrpc.yaml +++ b/Bindings/misc/qcom,fastrpc.yaml @@ -77,6 +77,8 @@ patternProperties: reg: maxItems: 1 + dma-coherent: true + iommus: minItems: 1 maxItems: 3 diff --git a/Bindings/misc/xlnx,sd-fec.txt b/Bindings/misc/xlnx,sd-fec.txt deleted file mode 100644 index e3289634fa3..00000000000 --- a/Bindings/misc/xlnx,sd-fec.txt +++ /dev/null @@ -1,58 +0,0 @@ -* Xilinx SDFEC(16nm) IP * - -The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block -which provides high-throughput LDPC and Turbo Code implementations. -The LDPC decode & encode functionality is capable of covering a range of -customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality -principally covers codes used by LTE. The FEC Engine offers significant -power and area savings versus implementations done in the FPGA fabric. - - -Required properties: -- compatible: Must be "xlnx,sd-fec-1.1" -- clock-names : List of input clock names from the following: - - "core_clk", Main processing clock for processing core (required) - - "s_axi_aclk", AXI4-Lite memory-mapped slave interface clock (required) - - "s_axis_din_aclk", DIN AXI4-Stream Slave interface clock (optional) - - "s_axis_din_words-aclk", DIN_WORDS AXI4-Stream Slave interface clock (optional) - - "s_axis_ctrl_aclk", Control input AXI4-Stream Slave interface clock (optional) - - "m_axis_dout_aclk", DOUT AXI4-Stream Master interface clock (optional) - - "m_axis_dout_words_aclk", DOUT_WORDS AXI4-Stream Master interface clock (optional) - - "m_axis_status_aclk", Status output AXI4-Stream Master interface clock (optional) -- clocks : Clock phandles (see clock_bindings.txt for details). -- reg: Should contain Xilinx SDFEC 16nm Hardened IP block registers - location and length. -- xlnx,sdfec-code : Should contain "ldpc" or "turbo" to describe the codes - being used. -- xlnx,sdfec-din-words : A value 0 indicates that the DIN_WORDS interface is - driven with a fixed value and is not present on the device, a value of 1 - configures the DIN_WORDS to be block based, while a value of 2 configures the - DIN_WORDS input to be supplied for each AXI transaction. -- xlnx,sdfec-din-width : Configures the DIN AXI stream where a value of 1 - configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width - of "4x128b". -- xlnx,sdfec-dout-words : A value 0 indicates that the DOUT_WORDS interface is - driven with a fixed value and is not present on the device, a value of 1 - configures the DOUT_WORDS to be block based, while a value of 2 configures the - DOUT_WORDS input to be supplied for each AXI transaction. -- xlnx,sdfec-dout-width : Configures the DOUT AXI stream where a value of 1 - configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width - of "4x128b". -Optional properties: -- interrupts: should contain SDFEC interrupt number - -Example ---------------------------------------- - sd_fec_0: sd-fec@a0040000 { - compatible = "xlnx,sd-fec-1.1"; - clock-names = "core_clk","s_axi_aclk","s_axis_ctrl_aclk","s_axis_din_aclk","m_axis_status_aclk","m_axis_dout_aclk"; - clocks = <&misc_clk_2>,<&misc_clk_0>,<&misc_clk_1>,<&misc_clk_1>,<&misc_clk_1>, <&misc_clk_1>; - reg = <0x0 0xa0040000 0x0 0x40000>; - interrupt-parent = <&axi_intc>; - interrupts = <1 0>; - xlnx,sdfec-code = "ldpc"; - xlnx,sdfec-din-words = <0>; - xlnx,sdfec-din-width = <2>; - xlnx,sdfec-dout-words = <0>; - xlnx,sdfec-dout-width = <1>; - }; diff --git a/Bindings/misc/xlnx,sd-fec.yaml b/Bindings/misc/xlnx,sd-fec.yaml new file mode 100644 index 00000000000..9bd21033742 --- /dev/null +++ b/Bindings/misc/xlnx,sd-fec.yaml @@ -0,0 +1,140 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/xlnx,sd-fec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx SDFEC(16nm) IP + +maintainers: + - Cvetic, Dragan + - Erim, Salih + +description: + The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block + which provides high-throughput LDPC and Turbo Code implementations. + The LDPC decode & encode functionality is capable of covering a range of + customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality + principally covers codes used by LTE. The FEC Engine offers significant + power and area savings versus implementations done in the FPGA fabric. + +properties: + compatible: + const: xlnx,sd-fec-1.1 + + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 8 + additionalItems: true + items: + - description: Main processing clock for processing core + - description: AXI4-Lite memory-mapped slave interface clock + - description: Control input AXI4-Stream Slave interface clock + - description: DIN AXI4-Stream Slave interface clock + - description: Status output AXI4-Stream Master interface clock + - description: DOUT AXI4-Stream Master interface clock + - description: DIN_WORDS AXI4-Stream Slave interface clock + - description: DOUT_WORDS AXI4-Stream Master interface clock + + clock-names: + allOf: + - minItems: 2 + maxItems: 8 + additionalItems: true + items: + - const: core_clk + - const: s_axi_aclk + - items: + enum: + - core_clk + - s_axi_aclk + - s_axis_ctrl_aclk + - s_axis_din_aclk + - m_axis_status_aclk + - m_axis_dout_aclk + - s_axis_din_words_aclk + - m_axis_dout_words_aclk + + interrupts: + maxItems: 1 + + xlnx,sdfec-code: + description: + The SD-FEC integrated block supports Low Density Parity Check (LDPC) + decoding and encoding and Turbo code decoding. The LDPC codes used are + highly configurable, and the specific code used can be specified on + a codeword-by-codeword basis. The Turbo code decoding is required by LTE + standard. + $ref: /schemas/types.yaml#/definitions/string + items: + enum: [ ldpc, turbo ] + + xlnx,sdfec-din-width: + description: + Configures the DIN AXI stream where a value of 1 + configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width + of "4x128b". + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 1, 2, 4 ] + + xlnx,sdfec-din-words: + description: + A value 0 indicates that the DIN_WORDS interface is + driven with a fixed value and is not present on the device, a value of 1 + configures the DIN_WORDS to be block based, while a value of 2 configures the + DIN_WORDS input to be supplied for each AXI transaction. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2 ] + + xlnx,sdfec-dout-width: + description: + Configures the DOUT AXI stream where a value of 1 configures a width of "1x128b", + 2 a width of "2x128b" and 4 configures a width of "4x128b". + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 1, 2, 4 ] + + xlnx,sdfec-dout-words: + description: + A value 0 indicates that the DOUT_WORDS interface is + driven with a fixed value and is not present on the device, a value of 1 + configures the DOUT_WORDS to be block based, while a value of 2 configures the + DOUT_WORDS input to be supplied for each AXI transaction. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2 ] + +required: + - compatible + - reg + - clocks + - clock-names + - xlnx,sdfec-code + - xlnx,sdfec-din-width + - xlnx,sdfec-din-words + - xlnx,sdfec-dout-width + - xlnx,sdfec-dout-words + +additionalProperties: false + +examples: + - | + #include + + sd-fec@a0040000 { + compatible = "xlnx,sd-fec-1.1"; + reg = <0xa0040000 0x40000>; + clocks = <&misc_clk_2>, <&misc_clk_0>, <&misc_clk_1>, <&misc_clk_1>, + <&misc_clk_1>, <&misc_clk_1>; + clock-names = "core_clk", "s_axi_aclk", "s_axis_ctrl_aclk", + "s_axis_din_aclk", "m_axis_status_aclk", + "m_axis_dout_aclk"; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + xlnx,sdfec-code = "ldpc"; + xlnx,sdfec-din-width = <2>; + xlnx,sdfec-din-words = <0>; + xlnx,sdfec-dout-width = <1>; + xlnx,sdfec-dout-words = <0>; + }; + diff --git a/Bindings/mmc/fsl-imx-esdhc.yaml b/Bindings/mmc/fsl-imx-esdhc.yaml index 82eb7a24c85..82f7ee8702c 100644 --- a/Bindings/mmc/fsl-imx-esdhc.yaml +++ b/Bindings/mmc/fsl-imx-esdhc.yaml @@ -55,8 +55,9 @@ properties: - enum: - fsl,imx8mn-usdhc - fsl,imx8mp-usdhc - - fsl,imx93-usdhc - fsl,imx8ulp-usdhc + - fsl,imx93-usdhc + - fsl,imx95-usdhc - const: fsl,imx8mm-usdhc - items: - enum: @@ -162,6 +163,9 @@ properties: - const: ahb - const: per + iommus: + maxItems: 1 + power-domains: maxItems: 1 @@ -173,6 +177,11 @@ properties: - const: state_100mhz - const: state_200mhz - const: sleep + - minItems: 2 + items: + - const: default + - const: state_100mhz + - const: sleep - minItems: 1 items: - const: default diff --git a/Bindings/mmc/fsl-imx-mmc.yaml b/Bindings/mmc/fsl-imx-mmc.yaml index 221f5bc047b..7911316fbd6 100644 --- a/Bindings/mmc/fsl-imx-mmc.yaml +++ b/Bindings/mmc/fsl-imx-mmc.yaml @@ -24,6 +24,14 @@ properties: reg: maxItems: 1 + clocks: + maxItems: 2 + + clock-names: + items: + - const: ipg + - const: per + interrupts: maxItems: 1 @@ -34,6 +42,8 @@ properties: const: rx-tx required: + - clocks + - clock-names - compatible - reg - interrupts @@ -46,6 +56,8 @@ examples: compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; reg = <0x10014000 0x1000>; interrupts = <11>; + clocks = <&clks 29>, <&clks 60>; + clock-names = "ipg", "per"; dmas = <&dma 7>; dma-names = "rx-tx"; bus-width = <4>; diff --git a/Bindings/mmc/hi3798cv200-dw-mshc.txt b/Bindings/mmc/hi3798cv200-dw-mshc.txt deleted file mode 100644 index a0693b7145f..00000000000 --- a/Bindings/mmc/hi3798cv200-dw-mshc.txt +++ /dev/null @@ -1,40 +0,0 @@ -* Hisilicon Hi3798CV200 specific extensions to the Synopsys Designware Mobile - Storage Host Controller - -Read synopsys-dw-mshc.txt for more details - -The Synopsys designware mobile storage host controller is used to interface -a SoC with storage medium such as eMMC or SD/MMC cards. This file documents -differences between the core Synopsys dw mshc controller properties described -by synopsys-dw-mshc.txt and the properties used by the Hisilicon Hi3798CV200 -specific extensions to the Synopsys Designware Mobile Storage Host Controller. - -Required Properties: -- compatible: Should contain "hisilicon,hi3798cv200-dw-mshc". -- clocks: A list of phandle + clock-specifier pairs for the clocks listed - in clock-names. -- clock-names: Should contain the following: - "ciu" - The ciu clock described in synopsys-dw-mshc.txt. - "biu" - The biu clock described in synopsys-dw-mshc.txt. - "ciu-sample" - Hi3798CV200 extended phase clock for ciu sampling. - "ciu-drive" - Hi3798CV200 extended phase clock for ciu driving. - -Example: - - emmc: mmc@9830000 { - compatible = "hisilicon,hi3798cv200-dw-mshc"; - reg = <0x9830000 0x10000>; - interrupts = ; - clocks = <&crg HISTB_MMC_CIU_CLK>, - <&crg HISTB_MMC_BIU_CLK>, - <&crg HISTB_MMC_SAMPLE_CLK>, - <&crg HISTB_MMC_DRV_CLK>; - clock-names = "ciu", "biu", "ciu-sample", "ciu-drive"; - fifo-depth = <256>; - clock-frequency = <200000000>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - bus-width = <8>; - }; diff --git a/Bindings/mmc/hisilicon,hi3798cv200-dw-mshc.yaml b/Bindings/mmc/hisilicon,hi3798cv200-dw-mshc.yaml new file mode 100644 index 00000000000..41c9b22523e --- /dev/null +++ b/Bindings/mmc/hisilicon,hi3798cv200-dw-mshc.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/hisilicon,hi3798cv200-dw-mshc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon HiSTB SoCs specific extensions to the Synopsys DWMMC controller + +maintainers: + - Yang Xiwen + +properties: + compatible: + enum: + - hisilicon,hi3798cv200-dw-mshc + - hisilicon,hi3798mv200-dw-mshc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: bus interface unit clock + - description: card interface unit clock + - description: card input sample phase clock + - description: controller output drive phase clock + + clock-names: + items: + - const: ciu + - const: biu + - const: ciu-sample + - const: ciu-drive + + hisilicon,sap-dll-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + DWMMC core on Hi3798MV2x SoCs has a delay-locked-loop(DLL) attached to card data input path. + It is integrated into CRG core on the SoC and has to be controlled during tuning. + items: + - description: A phandle pointed to the CRG syscon node + - description: Sample DLL register offset in CRG address space + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +allOf: + - $ref: synopsys-dw-mshc-common.yaml# + + - if: + properties: + compatible: + contains: + const: hisilicon,hi3798mv200-dw-mshc + then: + required: + - hisilicon,sap-dll-reg + else: + properties: + hisilicon,sap-dll-reg: false + +unevaluatedProperties: false + +examples: + - | + #include + #include + + mmc@9830000 { + compatible = "hisilicon,hi3798cv200-dw-mshc"; + reg = <0x9830000 0x10000>; + interrupts = ; + clocks = <&crg HISTB_MMC_CIU_CLK>, + <&crg HISTB_MMC_BIU_CLK>, + <&crg HISTB_MMC_SAMPLE_CLK>, + <&crg HISTB_MMC_DRV_CLK>; + clock-names = "ciu", "biu", "ciu-sample", "ciu-drive"; + resets = <&crg 0xa0 4>; + reset-names = "reset"; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins_1 &emmc_pins_2 + &emmc_pins_3 &emmc_pins_4>; + fifo-depth = <256>; + clock-frequency = <200000000>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + bus-width = <8>; + }; diff --git a/Bindings/mmc/renesas,sdhi.yaml b/Bindings/mmc/renesas,sdhi.yaml index f7a4c6bc70f..29f2400247e 100644 --- a/Bindings/mmc/renesas,sdhi.yaml +++ b/Bindings/mmc/renesas,sdhi.yaml @@ -67,6 +67,7 @@ properties: - renesas,sdhi-r8a779a0 # R-Car V3U - renesas,sdhi-r8a779f0 # R-Car S4-8 - renesas,sdhi-r8a779g0 # R-Car V4H + - renesas,sdhi-r8a779h0 # R-Car V4M - const: renesas,rcar-gen4-sdhi # R-Car Gen4 reg: diff --git a/Bindings/mmc/snps,dwcmshc-sdhci.yaml b/Bindings/mmc/snps,dwcmshc-sdhci.yaml index 42804d95529..4d3031d9965 100644 --- a/Bindings/mmc/snps,dwcmshc-sdhci.yaml +++ b/Bindings/mmc/snps,dwcmshc-sdhci.yaml @@ -19,6 +19,8 @@ properties: - rockchip,rk3568-dwcmshc - rockchip,rk3588-dwcmshc - snps,dwcmshc-sdhci + - sophgo,cv1800b-dwcmshc + - sophgo,sg2002-dwcmshc - thead,th1520-dwcmshc reg: diff --git a/Bindings/mtd/atmel-nand.txt b/Bindings/mtd/atmel-nand.txt index 50645828ac2..4598930851d 100644 --- a/Bindings/mtd/atmel-nand.txt +++ b/Bindings/mtd/atmel-nand.txt @@ -56,6 +56,7 @@ Required properties: "atmel,sama5d4-pmecc" "atmel,sama5d2-pmecc" "microchip,sam9x60-pmecc" + "microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc" - reg: should contain 2 register ranges. The first one is pointing to the PMECC block, and the second one to the PMECC_ERRLOC block. diff --git a/Bindings/mtd/brcm,brcmnand.yaml b/Bindings/mtd/brcm,brcmnand.yaml index f57e96374e6..064e840aeaa 100644 --- a/Bindings/mtd/brcm,brcmnand.yaml +++ b/Bindings/mtd/brcm,brcmnand.yaml @@ -9,6 +9,7 @@ title: Broadcom STB NAND Controller maintainers: - Brian Norris - Kamal Dasu + - William Zhang description: | The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND @@ -18,9 +19,10 @@ description: | supports basic PROGRAM and READ functions, among other features. This controller was originally designed for STB SoCs (BCM7xxx) but is now - available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and - iProc/Cygnus. Its history includes several similar (but not fully register - compatible) versions. + available on a variety of Broadcom SoCs, including some BCM3xxx, MIPS based + Broadband SoC (BCM63xx), ARM based Broadband SoC (BCMBCA) and iProc/Cygnus. + Its history includes several similar (but not fully register compatible) + versions. -- Additional SoC-specific NAND controller properties -- @@ -53,7 +55,7 @@ properties: - brcm,brcmnand-v7.2 - brcm,brcmnand-v7.3 - const: brcm,brcmnand - - description: BCM63138 SoC-specific NAND controller + - description: BCMBCA SoC-specific NAND controller items: - const: brcm,nand-bcm63138 - enum: @@ -111,6 +113,13 @@ properties: earlier versions of this core that include WP type: boolean + brcm,wp-not-connected: + description: + Use this property when WP pin is not physically wired to the NAND chip. + Write protection feature cannot be used. By default, controller assumes + the pin is connected and feature is used. + $ref: /schemas/types.yaml#/definitions/flag + patternProperties: "^nand@[a-f0-9]$": type: object @@ -137,6 +146,15 @@ patternProperties: layout. $ref: /schemas/types.yaml#/definitions/uint32 + brcm,nand-ecc-use-strap: + description: + This property requires the host system to get the ECC related + settings from the SoC NAND boot strap configuration instead of + the generic NAND ECC settings. This is a common hardware design + on BCMBCA based boards. This strap ECC option and generic NAND + ECC option can not be specified at the same time. + $ref: /schemas/types.yaml#/definitions/flag + unevaluatedProperties: false allOf: @@ -177,6 +195,8 @@ allOf: - const: iproc-idm - const: iproc-ext - if: + required: + - interrupts properties: interrupts: minItems: 2 @@ -184,12 +204,26 @@ allOf: required: - interrupt-names + - if: + patternProperties: + "^nand@[a-f0-9]$": + required: + - brcm,nand-ecc-use-strap + then: + patternProperties: + "^nand@[a-f0-9]$": + properties: + nand-ecc-strength: false + nand-ecc-step-size: false + nand-ecc-maximize: false + nand-ecc-algo: false + brcm,nand-oob-sector-size: false + unevaluatedProperties: false required: - reg - reg-names - - interrupts examples: - | diff --git a/Bindings/mtd/davinci-nand.txt b/Bindings/mtd/davinci-nand.txt index edebeae1f5b..eb8e2ff4dbd 100644 --- a/Bindings/mtd/davinci-nand.txt +++ b/Bindings/mtd/davinci-nand.txt @@ -68,7 +68,7 @@ Deprecated properties: false. Nand device bindings may contain additional sub-nodes describing partitions of -the address space. See partition.txt for more detail. The NAND Flash timing +the address space. See mtd.yaml for more detail. The NAND Flash timing values must be programmed in the chip select’s node of AEMIF memory-controller (see Documentation/devicetree/bindings/memory-controllers/ davinci-aemif.txt). diff --git a/Bindings/mtd/flctl-nand.txt b/Bindings/mtd/flctl-nand.txt index 427f46dc60a..51518399d73 100644 --- a/Bindings/mtd/flctl-nand.txt +++ b/Bindings/mtd/flctl-nand.txt @@ -15,7 +15,7 @@ The DMA fields are not used yet in the driver but are listed here for completing the bindings. The device tree may optionally contain sub-nodes describing partitions of the -address space. See partition.txt for more detail. +address space. See mtd.yaml for more detail. Example: diff --git a/Bindings/mtd/fsl-upm-nand.txt b/Bindings/mtd/fsl-upm-nand.txt index 25f07c1f9e4..530c017e014 100644 --- a/Bindings/mtd/fsl-upm-nand.txt +++ b/Bindings/mtd/fsl-upm-nand.txt @@ -22,7 +22,7 @@ Deprecated properties: (R/B# pins not connected). Each flash chip described may optionally contain additional sub-nodes -describing partitions of the address space. See partition.txt for more +describing partitions of the address space. See mtd.yaml for more detail. Examples: diff --git a/Bindings/mtd/gpio-control-nand.txt b/Bindings/mtd/gpio-control-nand.txt index 486a17d533d..0edf55d47ea 100644 --- a/Bindings/mtd/gpio-control-nand.txt +++ b/Bindings/mtd/gpio-control-nand.txt @@ -26,7 +26,7 @@ Optional properties: read to ensure that the GPIO accesses have completed. The device tree may optionally contain sub-nodes describing partitions of the -address space. See partition.txt for more detail. +address space. See mtd.yaml for more detail. Examples: diff --git a/Bindings/mtd/gpmi-nand.yaml b/Bindings/mtd/gpmi-nand.yaml index ba086c34626..021c0da0b07 100644 --- a/Bindings/mtd/gpmi-nand.yaml +++ b/Bindings/mtd/gpmi-nand.yaml @@ -12,7 +12,7 @@ maintainers: description: | The GPMI nand controller provides an interface to control the NAND flash chips. The device tree may optionally contain sub-nodes - describing partitions of the address space. See partition.txt for + describing partitions of the address space. See mtd.yaml for more detail. properties: diff --git a/Bindings/mtd/hisi504-nand.txt b/Bindings/mtd/hisi504-nand.txt index 8963983ae7c..362203e7d50 100644 --- a/Bindings/mtd/hisi504-nand.txt +++ b/Bindings/mtd/hisi504-nand.txt @@ -22,7 +22,7 @@ The following ECC strength and step size are currently supported: - nand-ecc-strength = <16>, nand-ecc-step-size = <1024> Flash chip may optionally contain additional sub-nodes describing partitions of -the address space. See partition.txt for more detail. +the address space. See mtd.yaml for more detail. Example: diff --git a/Bindings/mtd/jedec,spi-nor.yaml b/Bindings/mtd/jedec,spi-nor.yaml index 58f0cea160e..6e3afb42926 100644 --- a/Bindings/mtd/jedec,spi-nor.yaml +++ b/Bindings/mtd/jedec,spi-nor.yaml @@ -52,6 +52,9 @@ properties: minItems: 1 maxItems: 2 + interrupts: + maxItems: 1 + m25p,fast-read: type: boolean description: diff --git a/Bindings/mtd/mtd.yaml b/Bindings/mtd/mtd.yaml index f322290ee51..ee442ecb11c 100644 --- a/Bindings/mtd/mtd.yaml +++ b/Bindings/mtd/mtd.yaml @@ -10,6 +10,8 @@ maintainers: - Miquel Raynal - Richard Weinberger +select: false + properties: $nodename: pattern: "^(flash|.*sram|nand)(@.*)?$" diff --git a/Bindings/mtd/nvidia-tegra20-nand.txt b/Bindings/mtd/nvidia-tegra20-nand.txt index e737e5beb7b..4a00ec2b254 100644 --- a/Bindings/mtd/nvidia-tegra20-nand.txt +++ b/Bindings/mtd/nvidia-tegra20-nand.txt @@ -39,7 +39,7 @@ Optional children node properties: - wp-gpios: GPIO specifier for the write protect pin. Optional child node of NAND chip nodes: -Partitions: see partition.txt +Partitions: see mtd.yaml Example: nand-controller@70008000 { diff --git a/Bindings/mtd/orion-nand.txt b/Bindings/mtd/orion-nand.txt index 2d6ab660e60..b9997b1f13a 100644 --- a/Bindings/mtd/orion-nand.txt +++ b/Bindings/mtd/orion-nand.txt @@ -13,7 +13,7 @@ Optional properties: registers in usecs The device tree may optionally contain sub-nodes describing partitions of the -address space. See partition.txt for more detail. +address space. See mtd.yaml for more detail. Example: diff --git a/Bindings/mtd/partitions/linux,ubi.yaml b/Bindings/mtd/partitions/linux,ubi.yaml new file mode 100644 index 00000000000..27e1ac1f252 --- /dev/null +++ b/Bindings/mtd/partitions/linux,ubi.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/partitions/linux,ubi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Unsorted Block Images + +description: | + UBI ("Unsorted Block Images") is a volume management system for raw + flash devices which manages multiple logical volumes on a single + physical flash device and spreads the I/O load (i.e wear-leveling) + across the whole flash chip. + +maintainers: + - Daniel Golle + +allOf: + - $ref: partition.yaml# + +properties: + compatible: + const: linux,ubi + + volumes: + type: object + description: UBI Volumes + + patternProperties: + "^ubi-volume-.*$": + $ref: /schemas/mtd/partitions/ubi-volume.yaml# + + unevaluatedProperties: false + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x100000>; + label = "bootloader"; + read-only; + }; + + partition@100000 { + reg = <0x100000 0x1ff00000>; + label = "ubi"; + compatible = "linux,ubi"; + + volumes { + ubi-volume-caldata { + volid = <2>; + volname = "rf"; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom@0 { + reg = <0x0 0x1000>; + }; + }; + }; + }; + }; + }; diff --git a/Bindings/mtd/partitions/ubi-volume.yaml b/Bindings/mtd/partitions/ubi-volume.yaml new file mode 100644 index 00000000000..19736b26056 --- /dev/null +++ b/Bindings/mtd/partitions/ubi-volume.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/partitions/ubi-volume.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UBI volume + +description: | + This binding describes a single UBI volume. Volumes can be matches either + by their ID or their name, or both. + +maintainers: + - Daniel Golle + +properties: + volid: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Match UBI volume ID + + volname: + $ref: /schemas/types.yaml#/definitions/string + description: + Match UBI volume ID + + nvmem-layout: + $ref: /schemas/nvmem/layouts/nvmem-layout.yaml# + description: + This container may reference an NVMEM layout parser. + +anyOf: + - required: + - volid + + - required: + - volname + +# This is a generic file other binding inherit from and extend +additionalProperties: true diff --git a/Bindings/mtd/samsung-s3c2410.txt b/Bindings/mtd/samsung-s3c2410.txt index 09815c40fc8..63545535066 100644 --- a/Bindings/mtd/samsung-s3c2410.txt +++ b/Bindings/mtd/samsung-s3c2410.txt @@ -19,7 +19,7 @@ Optional child properties: Each child device node may optionally contain a 'partitions' sub-node, which further contains sub-nodes describing the flash partition mapping. -See partition.txt for more detail. +See mtd.yaml for more detail. Example: diff --git a/Bindings/mtd/st,stm32-fmc2-nand.yaml b/Bindings/mtd/st,stm32-fmc2-nand.yaml index e72cb5bacaf..b8ef9ba88e9 100644 --- a/Bindings/mtd/st,stm32-fmc2-nand.yaml +++ b/Bindings/mtd/st,stm32-fmc2-nand.yaml @@ -14,10 +14,11 @@ properties: enum: - st,stm32mp15-fmc2 - st,stm32mp1-fmc2-nfc + - st,stm32mp25-fmc2-nfc reg: minItems: 6 - maxItems: 7 + maxItems: 12 interrupts: maxItems: 1 @@ -92,6 +93,28 @@ allOf: - description: Chip select 1 command - description: Chip select 1 address space + - if: + properties: + compatible: + contains: + const: st,stm32mp25-fmc2-nfc + then: + properties: + reg: + items: + - description: Chip select 0 data + - description: Chip select 0 command + - description: Chip select 0 address space + - description: Chip select 1 data + - description: Chip select 1 command + - description: Chip select 1 address space + - description: Chip select 2 data + - description: Chip select 2 command + - description: Chip select 2 address space + - description: Chip select 3 data + - description: Chip select 3 command + - description: Chip select 3 address space + required: - compatible - reg diff --git a/Bindings/mux/mux-controller.yaml b/Bindings/mux/mux-controller.yaml index 8b943082a24..571ad9e13ec 100644 --- a/Bindings/mux/mux-controller.yaml +++ b/Bindings/mux/mux-controller.yaml @@ -74,7 +74,7 @@ select: properties: $nodename: - pattern: '^mux-controller(@.*|-[0-9a-f]+)?$' + pattern: '^mux-controller(@.*|-([0-9]|[1-9][0-9]+))?$' '#mux-control-cells': enum: [ 0, 1 ] diff --git a/Bindings/net/bluetooth/qualcomm-bluetooth.yaml b/Bindings/net/bluetooth/qualcomm-bluetooth.yaml index eba2f3026ab..055a3351880 100644 --- a/Bindings/net/bluetooth/qualcomm-bluetooth.yaml +++ b/Bindings/net/bluetooth/qualcomm-bluetooth.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Bluetooth Chips maintainers: - - Balakrishna Godavarthi - - Rocky Liao + - Balakrishna Godavarthi + - Rocky Liao description: This binding describes Qualcomm UART-attached bluetooth chips. @@ -94,6 +94,10 @@ properties: local-bd-address: true + qcom,local-bd-address-broken: + type: boolean + description: + boot firmware is incorrectly passing the address in big-endian order required: - compatible diff --git a/Bindings/net/brcm,asp-v2.0.yaml b/Bindings/net/brcm,asp-v2.0.yaml index 75d8138298f..660e2ca42da 100644 --- a/Bindings/net/brcm,asp-v2.0.yaml +++ b/Bindings/net/brcm,asp-v2.0.yaml @@ -15,6 +15,10 @@ description: Broadcom Ethernet controller first introduced with 72165 properties: compatible: oneOf: + - items: + - enum: + - brcm,bcm74165b0-asp + - const: brcm,asp-v2.2 - items: - enum: - brcm,bcm74165-asp diff --git a/Bindings/net/brcm,unimac-mdio.yaml b/Bindings/net/brcm,unimac-mdio.yaml index 6684810fcbf..23dfe0838dc 100644 --- a/Bindings/net/brcm,unimac-mdio.yaml +++ b/Bindings/net/brcm,unimac-mdio.yaml @@ -24,6 +24,7 @@ properties: - brcm,genet-mdio-v5 - brcm,asp-v2.0-mdio - brcm,asp-v2.1-mdio + - brcm,asp-v2.2-mdio - brcm,unimac-mdio reg: diff --git a/Bindings/net/can/fsl,flexcan.yaml b/Bindings/net/can/fsl,flexcan.yaml index 4162469c3c0..f197d9b516b 100644 --- a/Bindings/net/can/fsl,flexcan.yaml +++ b/Bindings/net/can/fsl,flexcan.yaml @@ -38,6 +38,9 @@ properties: - fsl,imx6ul-flexcan - fsl,imx6sx-flexcan - const: fsl,imx6q-flexcan + - items: + - const: fsl,imx95-flexcan + - const: fsl,imx93-flexcan - items: - enum: - fsl,ls1028ar1-flexcan diff --git a/Bindings/net/can/microchip,mpfs-can.yaml b/Bindings/net/can/microchip,mpfs-can.yaml index 45aa3de7cf0..01e4d4a54df 100644 --- a/Bindings/net/can/microchip,mpfs-can.yaml +++ b/Bindings/net/can/microchip,mpfs-can.yaml @@ -24,7 +24,9 @@ properties: maxItems: 1 clocks: - maxItems: 1 + items: + - description: AHB peripheral clock + - description: CAN bus clock required: - compatible @@ -39,7 +41,7 @@ examples: can@2010c000 { compatible = "microchip,mpfs-can"; reg = <0x2010c000 0x1000>; - clocks = <&clkcfg 17>; + clocks = <&clkcfg 17>, <&clkcfg 37>; interrupt-parent = <&plic>; interrupts = <56>; }; diff --git a/Bindings/net/can/tcan4x5x.txt b/Bindings/net/can/tcan4x5x.txt index 170e23f0610..20c0572c985 100644 --- a/Bindings/net/can/tcan4x5x.txt +++ b/Bindings/net/can/tcan4x5x.txt @@ -28,6 +28,8 @@ Optional properties: available with tcan4552/4553. - device-wake-gpios: Wake up GPIO to wake up the TCAN device. Not available with tcan4552/4553. + - wakeup-source: Leave the chip running when suspended, and configure + the RX interrupt to wake up the device. Example: tcan4x5x: tcan4x5x@0 { @@ -42,4 +44,5 @@ tcan4x5x: tcan4x5x@0 { device-state-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; device-wake-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; + wakeup-source; }; diff --git a/Bindings/net/can/xilinx,can.yaml b/Bindings/net/can/xilinx,can.yaml index 64d57c343e6..8d4e5af6fd6 100644 --- a/Bindings/net/can/xilinx,can.yaml +++ b/Bindings/net/can/xilinx,can.yaml @@ -49,6 +49,10 @@ properties: resets: maxItems: 1 + xlnx,has-ecc: + $ref: /schemas/types.yaml#/definitions/flag + description: CAN TX_OL, TX_TL and RX FIFOs have ECC support(AXI CAN) + required: - compatible - reg @@ -137,6 +141,7 @@ examples: interrupts = ; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + xlnx,has-ecc; }; - | diff --git a/Bindings/net/cdns,macb.yaml b/Bindings/net/cdns,macb.yaml index bf8894a0257..2c71e2cf3a2 100644 --- a/Bindings/net/cdns,macb.yaml +++ b/Bindings/net/cdns,macb.yaml @@ -59,6 +59,11 @@ properties: - cdns,gem # Generic - cdns,macb # Generic + - items: + - enum: + - microchip,sam9x7-gem # Microchip SAM9X7 gigabit ethernet interface + - const: microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface + reg: minItems: 1 items: diff --git a/Bindings/net/dsa/ar9331.txt b/Bindings/net/dsa/ar9331.txt deleted file mode 100644 index f824fdae0da..00000000000 --- a/Bindings/net/dsa/ar9331.txt +++ /dev/null @@ -1,147 +0,0 @@ -Atheros AR9331 built-in switch -============================= - -It is a switch built-in to Atheros AR9331 WiSoC and addressable over internal -MDIO bus. All PHYs are built-in as well. - -Required properties: - - - compatible: should be: "qca,ar9331-switch" - - reg: Address on the MII bus for the switch. - - resets : Must contain an entry for each entry in reset-names. - - reset-names : Must include the following entries: "switch" - - interrupt-parent: Phandle to the parent interrupt controller - - interrupts: IRQ line for the switch - - interrupt-controller: Indicates the switch is itself an interrupt - controller. This is used for the PHY interrupts. - - #interrupt-cells: must be 1 - - mdio: Container of PHY and devices on the switches MDIO bus. - -See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional -required and optional properties. -Examples: - -eth0: ethernet@19000000 { - compatible = "qca,ar9330-eth"; - reg = <0x19000000 0x200>; - interrupts = <4>; - - resets = <&rst 9>, <&rst 22>; - reset-names = "mac", "mdio"; - clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>; - clock-names = "eth", "mdio"; - - phy-mode = "mii"; - phy-handle = <&phy_port4>; -}; - -eth1: ethernet@1a000000 { - compatible = "qca,ar9330-eth"; - reg = <0x1a000000 0x200>; - interrupts = <5>; - resets = <&rst 13>, <&rst 23>; - reset-names = "mac", "mdio"; - clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>; - clock-names = "eth", "mdio"; - - phy-mode = "gmii"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch10: switch@10 { - #address-cells = <1>; - #size-cells = <0>; - - compatible = "qca,ar9331-switch"; - reg = <0x10>; - resets = <&rst 8>; - reset-names = "switch"; - - interrupt-parent = <&miscintc>; - interrupts = <12>; - - interrupt-controller; - #interrupt-cells = <1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - switch_port0: port@0 { - reg = <0x0>; - ethernet = <ð1>; - - phy-mode = "gmii"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - switch_port1: port@1 { - reg = <0x1>; - phy-handle = <&phy_port0>; - phy-mode = "internal"; - }; - - switch_port2: port@2 { - reg = <0x2>; - phy-handle = <&phy_port1>; - phy-mode = "internal"; - }; - - switch_port3: port@3 { - reg = <0x3>; - phy-handle = <&phy_port2>; - phy-mode = "internal"; - }; - - switch_port4: port@4 { - reg = <0x4>; - phy-handle = <&phy_port3>; - phy-mode = "internal"; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&switch10>; - - phy_port0: phy@0 { - reg = <0x0>; - interrupts = <0>; - }; - - phy_port1: phy@1 { - reg = <0x1>; - interrupts = <0>; - }; - - phy_port2: phy@2 { - reg = <0x2>; - interrupts = <0>; - }; - - phy_port3: phy@3 { - reg = <0x3>; - interrupts = <0>; - }; - - phy_port4: phy@4 { - reg = <0x4>; - interrupts = <0>; - }; - }; - }; - }; -}; diff --git a/Bindings/net/dsa/microchip,ksz.yaml b/Bindings/net/dsa/microchip,ksz.yaml index c963dc09e8e..52acc15ebcb 100644 --- a/Bindings/net/dsa/microchip,ksz.yaml +++ b/Bindings/net/dsa/microchip,ksz.yaml @@ -31,6 +31,7 @@ properties: - microchip,ksz9893 - microchip,ksz9563 - microchip,ksz8563 + - microchip,ksz8567 reset-gpios: description: diff --git a/Bindings/net/dsa/qca,ar9331.yaml b/Bindings/net/dsa/qca,ar9331.yaml new file mode 100644 index 00000000000..fd9ddc59d38 --- /dev/null +++ b/Bindings/net/dsa/qca,ar9331.yaml @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/dsa/qca,ar9331.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Atheros AR9331 built-in switch + +maintainers: + - Oleksij Rempel + +description: + Qualcomm Atheros AR9331 is a switch built-in to Atheros AR9331 WiSoC and + addressable over internal MDIO bus. All PHYs are built-in as well. + +properties: + compatible: + const: qca,ar9331-switch + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + mdio: + $ref: /schemas/net/mdio.yaml# + unevaluatedProperties: false + properties: + interrupt-parent: true + + patternProperties: + '(ethernet-)?phy@[0-4]+$': + type: object + unevaluatedProperties: false + + properties: + reg: true + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + items: + - const: switch + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - mdio + - ports + - resets + - reset-names + +allOf: + - $ref: dsa.yaml#/$defs/ethernet-ports + +unevaluatedProperties: false + +examples: + - | + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch10: switch@10 { + compatible = "qca,ar9331-switch"; + reg = <0x10>; + + interrupt-parent = <&miscintc>; + interrupts = <12>; + interrupt-controller; + #interrupt-cells = <1>; + + resets = <&rst 8>; + reset-names = "switch"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + ethernet = <ð1>; + + phy-mode = "gmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <0x1>; + phy-handle = <&phy_port0>; + phy-mode = "internal"; + }; + + port@2 { + reg = <0x2>; + phy-handle = <&phy_port1>; + phy-mode = "internal"; + }; + + port@3 { + reg = <0x3>; + phy-handle = <&phy_port2>; + phy-mode = "internal"; + }; + + port@4 { + reg = <0x4>; + phy-handle = <&phy_port3>; + phy-mode = "internal"; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&switch10>; + + phy_port0: ethernet-phy@0 { + reg = <0x0>; + interrupts = <0>; + }; + + phy_port1: ethernet-phy@1 { + reg = <0x1>; + interrupts = <0>; + }; + + phy_port2: ethernet-phy@2 { + reg = <0x2>; + interrupts = <0>; + }; + + phy_port3: ethernet-phy@3 { + reg = <0x3>; + interrupts = <0>; + }; + + phy_port4: ethernet-phy@4 { + reg = <0x4>; + interrupts = <0>; + }; + }; + }; + }; diff --git a/Bindings/net/dsa/realtek.yaml b/Bindings/net/dsa/realtek.yaml index cce692f57b0..70b6bda3cf9 100644 --- a/Bindings/net/dsa/realtek.yaml +++ b/Bindings/net/dsa/realtek.yaml @@ -59,6 +59,9 @@ properties: description: GPIO to be used to reset the whole device maxItems: 1 + resets: + maxItems: 1 + realtek,disable-leds: type: boolean description: | @@ -127,7 +130,6 @@ else: - mdc-gpios - mdio-gpios - mdio - - reset-gpios required: - compatible diff --git a/Bindings/net/ethernet-controller.yaml b/Bindings/net/ethernet-controller.yaml index d14d123ad7a..b2785b03139 100644 --- a/Bindings/net/ethernet-controller.yaml +++ b/Bindings/net/ethernet-controller.yaml @@ -14,7 +14,6 @@ properties: pattern: "^ethernet(@.*)?$" label: - $ref: /schemas/types.yaml#/definitions/string description: Human readable label on a port of a box. local-mac-address: diff --git a/Bindings/net/ethernet-phy-package.yaml b/Bindings/net/ethernet-phy-package.yaml new file mode 100644 index 00000000000..e567101e6f3 --- /dev/null +++ b/Bindings/net/ethernet-phy-package.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/ethernet-phy-package.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ethernet PHY Package Common Properties + +maintainers: + - Christian Marangi + +description: + PHY packages are multi-port Ethernet PHY of the same family + and each Ethernet PHY is affected by the global configuration + of the PHY package. + + Each reg of the PHYs defined in the PHY package node is + absolute and describe the real address of the Ethernet PHY on + the MDIO bus. + +properties: + $nodename: + pattern: "^ethernet-phy-package@[a-f0-9]+$" + + reg: + minimum: 0 + maximum: 31 + description: + The base ID number for the PHY package. + Commonly the ID of the first PHY in the PHY package. + + Some PHY in the PHY package might be not defined but + still occupy ID on the device (just not attached to + anything) hence the PHY package reg might correspond + to a not attached PHY (offset 0). + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + ^ethernet-phy@[a-f0-9]+$: + $ref: ethernet-phy.yaml# + +required: + - reg + - '#address-cells' + - '#size-cells' + +additionalProperties: true diff --git a/Bindings/net/fsl,fec.yaml b/Bindings/net/fsl,fec.yaml index 8948a11c994..5536c06139c 100644 --- a/Bindings/net/fsl,fec.yaml +++ b/Bindings/net/fsl,fec.yaml @@ -224,6 +224,9 @@ properties: Can be omitted thus no delay is observed. Delay is in range of 1ms to 1000ms. Other delays are invalid. + iommus: + maxItems: 1 + required: - compatible - reg diff --git a/Bindings/net/mediatek,net.yaml b/Bindings/net/mediatek,net.yaml index e74502a0afe..3202dc7967c 100644 --- a/Bindings/net/mediatek,net.yaml +++ b/Bindings/net/mediatek,net.yaml @@ -337,8 +337,8 @@ allOf: minItems: 4 clocks: - minItems: 34 - maxItems: 34 + minItems: 24 + maxItems: 24 clock-names: items: @@ -351,18 +351,6 @@ allOf: - const: ethwarp_wocpu1 - const: ethwarp_wocpu0 - const: esw - - const: netsys0 - - const: netsys1 - - const: sgmii_tx250m - - const: sgmii_rx250m - - const: sgmii2_tx250m - - const: sgmii2_rx250m - - const: top_usxgmii0_sel - - const: top_usxgmii1_sel - - const: top_sgm0_sel - - const: top_sgm1_sel - - const: top_xfi_phy0_xtal_sel - - const: top_xfi_phy1_xtal_sel - const: top_eth_gmii_sel - const: top_eth_refck_50m_sel - const: top_eth_sys_200m_sel @@ -375,16 +363,10 @@ allOf: - const: top_netsys_sync_250m_sel - const: top_netsys_ppefb_250m_sel - const: top_netsys_warp_sel - - const: wocpu1 - - const: wocpu0 - const: xgp1 - const: xgp2 - const: xgp3 - mediatek,sgmiisys: - minItems: 2 - maxItems: 2 - patternProperties: "^mac@[0-1]$": type: object diff --git a/Bindings/net/nfc/ti,trf7970a.yaml b/Bindings/net/nfc/ti,trf7970a.yaml index 9cc236ec42f..d0332eb76ad 100644 --- a/Bindings/net/nfc/ti,trf7970a.yaml +++ b/Bindings/net/nfc/ti,trf7970a.yaml @@ -73,7 +73,7 @@ examples: #include #include - i2c { + spi { #address-cells = <1>; #size-cells = <0>; diff --git a/Bindings/net/qca,qca808x.yaml b/Bindings/net/qca,qca808x.yaml new file mode 100644 index 00000000000..e2552655902 --- /dev/null +++ b/Bindings/net/qca,qca808x.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/qca,qca808x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Atheros QCA808X PHY + +maintainers: + - Christian Marangi + +description: + QCA808X PHYs can have up to 3 LEDs attached. + All 3 LEDs are disabled by default. + 2 LEDs have dedicated pins with the 3rd LED having the + double function of Interrupt LEDs/GPIO or additional LED. + + By default this special PIN is set to LED function. + +allOf: + - $ref: ethernet-phy.yaml# + +properties: + compatible: + enum: + - ethernet-phy-id004d.d101 + +unevaluatedProperties: false + +examples: + - | + #include + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + compatible = "ethernet-phy-id004d.d101"; + reg = <0>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_WAN; + default-state = "keep"; + }; + }; + }; + }; diff --git a/Bindings/net/qcom,ethqos.yaml b/Bindings/net/qcom,ethqos.yaml index 7bdb412a018..69a337c7e34 100644 --- a/Bindings/net/qcom,ethqos.yaml +++ b/Bindings/net/qcom,ethqos.yaml @@ -37,12 +37,14 @@ properties: items: - description: Combined signal for various interrupt events - description: The interrupt that occurs when Rx exits the LPI state + - description: The interrupt that occurs when HW safety error triggered interrupt-names: minItems: 1 items: - const: macirq - - const: eth_lpi + - enum: [eth_lpi, sfty] + - const: sfty clocks: maxItems: 4 @@ -89,8 +91,9 @@ examples: <&gcc GCC_ETH_PTP_CLK>, <&gcc GCC_ETH_RGMII_CLK>; interrupts = , - ; - interrupt-names = "macirq", "eth_lpi"; + , + ; + interrupt-names = "macirq", "eth_lpi", "sfty"; rx-fifo-depth = <4096>; tx-fifo-depth = <4096>; diff --git a/Bindings/net/qcom,ipa.yaml b/Bindings/net/qcom,ipa.yaml index c30218684cf..53cae71d995 100644 --- a/Bindings/net/qcom,ipa.yaml +++ b/Bindings/net/qcom,ipa.yaml @@ -159,7 +159,7 @@ properties: when the AP (not the modem) performs early initialization. firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: If present, name (or relative path) of the file within the firmware search path containing the firmware image used when diff --git a/Bindings/net/qcom,ipq4019-mdio.yaml b/Bindings/net/qcom,ipq4019-mdio.yaml index 3407e909e8a..0029e197a82 100644 --- a/Bindings/net/qcom,ipq4019-mdio.yaml +++ b/Bindings/net/qcom,ipq4019-mdio.yaml @@ -44,6 +44,21 @@ properties: items: - const: gcc_mdio_ahb_clk + clock-frequency: + description: + The MDIO bus clock that must be output by the MDIO bus hardware, if + absent, the default hardware values are used. + + MDC rate is feed by an external clock (fixed 100MHz) and is divider + internally. The default divider is /256 resulting in the default rate + applied of 390KHz. + + To follow 802.3 standard that instruct up to 2.5MHz by default, if + this property is not declared and the divider is set to /256, by + default 1.5625Mhz is select. + enum: [ 390625, 781250, 1562500, 3125000, 6250000, 12500000 ] + default: 1562500 + required: - compatible - reg diff --git a/Bindings/net/qcom,qca807x.yaml b/Bindings/net/qcom,qca807x.yaml new file mode 100644 index 00000000000..7290024024f --- /dev/null +++ b/Bindings/net/qcom,qca807x.yaml @@ -0,0 +1,184 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/qcom,qca807x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QCA807x Ethernet PHY + +maintainers: + - Christian Marangi + - Robert Marko + +description: | + Qualcomm QCA8072/5 Ethernet PHY is PHY package of 2 or 5 + IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and + 1000BASE-T PHY-s. + + They feature 2 SerDes, one for PSGMII or QSGMII connection with + MAC, while second one is SGMII for connection to MAC or fiber. + + Both models have a combo port that supports 1000BASE-X and + 100BASE-FX fiber. + + Each PHY inside of QCA807x series has 4 digitally controlled + output only pins that natively drive LED-s for up to 2 attached + LEDs. Some vendor also use these 4 output for GPIO usage without + attaching LEDs. + + Note that output pins can be set to drive LEDs OR GPIO, mixed + definition are not accepted. + +$ref: ethernet-phy-package.yaml# + +properties: + compatible: + enum: + - qcom,qca8072-package + - qcom,qca8075-package + + qcom,package-mode: + description: | + PHY package can be configured in 3 mode following this table: + + First Serdes mode Second Serdes mode + Option 1 PSGMII for copper Disabled + ports 0-4 + Option 2 PSGMII for copper 1000BASE-X / 100BASE-FX + ports 0-4 + Option 3 QSGMII for copper SGMII for + ports 0-3 copper port 4 + + PSGMII mode (option 1 or 2) is configured dynamically based on + the presence of a connected SFP device. + $ref: /schemas/types.yaml#/definitions/string + enum: + - qsgmii + - psgmii + default: psgmii + + qcom,tx-drive-strength-milliwatt: + description: set the TX Amplifier value in mv. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [140, 160, 180, 200, 220, + 240, 260, 280, 300, 320, + 400, 500, 600] + default: 600 + +patternProperties: + ^ethernet-phy@[a-f0-9]+$: + $ref: ethernet-phy.yaml# + + properties: + qcom,dac-full-amplitude: + description: + Set Analog MDI driver amplitude to FULL. + + With this not defined, amplitude is set to DSP. + (amplitude is adjusted based on cable length) + + With this enabled and qcom,dac-full-bias-current + and qcom,dac-disable-bias-current-tweak disabled, + bias current is half. + type: boolean + + qcom,dac-full-bias-current: + description: + Set Analog MDI driver bias current to FULL. + + With this not defined, bias current is set to DSP. + (bias current is adjusted based on cable length) + + Actual bias current might be different with + qcom,dac-disable-bias-current-tweak disabled. + type: boolean + + qcom,dac-disable-bias-current-tweak: + description: | + Set Analog MDI driver bias current to disable tweak + to bias current. + + With this not defined, bias current tweak are enabled + by default. + + With this enabled the following tweak are NOT applied: + - With both FULL amplitude and FULL bias current: bias current + is set to half. + - With only DSP amplitude: bias current is set to half and + is set to 1/4 with cable < 10m. + - With DSP bias current (included both DSP amplitude and + DSP bias current): bias current is half the detected current + with cable < 10m. + type: boolean + + gpio-controller: true + + '#gpio-cells': + const: 2 + + if: + required: + - gpio-controller + then: + properties: + leds: false + + unevaluatedProperties: false + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy-package@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,qca8075-package"; + reg = <0>; + + qcom,package-mode = "qsgmii"; + + ethernet-phy@0 { + reg = <0>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; + + ethernet-phy@1 { + reg = <1>; + }; + + ethernet-phy@2 { + reg = <2>; + + gpio-controller; + #gpio-cells = <2>; + }; + + ethernet-phy@3 { + reg = <3>; + }; + + ethernet-phy@4 { + reg = <4>; + }; + }; + }; diff --git a/Bindings/net/renesas,etheravb.yaml b/Bindings/net/renesas,etheravb.yaml index 890f7858d0d..de7ba7f345a 100644 --- a/Bindings/net/renesas,etheravb.yaml +++ b/Bindings/net/renesas,etheravb.yaml @@ -46,6 +46,7 @@ properties: - enum: - renesas,etheravb-r8a779a0 # R-Car V3U - renesas,etheravb-r8a779g0 # R-Car V4H + - renesas,etheravb-r8a779h0 # R-Car V4M - const: renesas,etheravb-rcar-gen4 # R-Car Gen4 - items: diff --git a/Bindings/net/snps,dwmac.yaml b/Bindings/net/snps,dwmac.yaml index 5c2769dc689..6b0341a8e0e 100644 --- a/Bindings/net/snps,dwmac.yaml +++ b/Bindings/net/snps,dwmac.yaml @@ -95,6 +95,7 @@ properties: - snps,dwmac-5.20 - snps,dwxgmac - snps,dwxgmac-2.10 + - starfive,jh7100-dwmac - starfive,jh7110-dwmac reg: @@ -107,13 +108,15 @@ properties: - description: Combined signal for various interrupt events - description: The interrupt to manage the remote wake-up packet detection - description: The interrupt that occurs when Rx exits the LPI state + - description: The interrupt that occurs when HW safety error triggered interrupt-names: minItems: 1 items: - const: macirq - - enum: [eth_wake_irq, eth_lpi] - - const: eth_lpi + - enum: [eth_wake_irq, eth_lpi, sfty] + - enum: [eth_wake_irq, eth_lpi, sfty] + - enum: [eth_wake_irq, eth_lpi, sfty] clocks: minItems: 1 @@ -144,10 +147,12 @@ properties: - description: AHB reset reset-names: - minItems: 1 - items: - - const: stmmaceth - - const: ahb + oneOf: + - items: + - enum: [stmmaceth, ahb] + - items: + - const: stmmaceth + - const: ahb power-domains: maxItems: 1 diff --git a/Bindings/net/starfive,jh7110-dwmac.yaml b/Bindings/net/starfive,jh7110-dwmac.yaml index 5e7cfbbebce..0d1962980f5 100644 --- a/Bindings/net/starfive,jh7110-dwmac.yaml +++ b/Bindings/net/starfive,jh7110-dwmac.yaml @@ -16,16 +16,20 @@ select: compatible: contains: enum: + - starfive,jh7100-dwmac - starfive,jh7110-dwmac required: - compatible properties: compatible: - items: - - enum: - - starfive,jh7110-dwmac - - const: snps,dwmac-5.20 + oneOf: + - items: + - const: starfive,jh7100-dwmac + - const: snps,dwmac + - items: + - const: starfive,jh7110-dwmac + - const: snps,dwmac-5.20 reg: maxItems: 1 @@ -46,24 +50,6 @@ properties: - const: tx - const: gtx - interrupts: - minItems: 3 - maxItems: 3 - - interrupt-names: - minItems: 3 - maxItems: 3 - - resets: - items: - - description: MAC Reset signal. - - description: AHB Reset signal. - - reset-names: - items: - - const: stmmaceth - - const: ahb - starfive,tx-use-rgmii-clk: description: Tx clock is provided by external rgmii clock. @@ -94,6 +80,48 @@ required: allOf: - $ref: snps,dwmac.yaml# + - if: + properties: + compatible: + contains: + const: starfive,jh7100-dwmac + then: + properties: + interrupts: + minItems: 2 + maxItems: 2 + + interrupt-names: + minItems: 2 + maxItems: 2 + + resets: + maxItems: 1 + + reset-names: + const: ahb + + - if: + properties: + compatible: + contains: + const: starfive,jh7110-dwmac + then: + properties: + interrupts: + minItems: 3 + maxItems: 3 + + interrupt-names: + minItems: 3 + maxItems: 3 + + resets: + minItems: 2 + + reset-names: + minItems: 2 + unevaluatedProperties: false examples: diff --git a/Bindings/net/ti,cpsw-switch.yaml b/Bindings/net/ti,cpsw-switch.yaml index f07ae3173b0..d5bd93ee4db 100644 --- a/Bindings/net/ti,cpsw-switch.yaml +++ b/Bindings/net/ti,cpsw-switch.yaml @@ -7,8 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: TI SoC Ethernet Switch Controller (CPSW) maintainers: - - Grygorii Strashko - - Sekhar Nori + - Siddharth Vadapalli + - Ravi Gunasekaran + - Roger Quadros description: The 3-port switch gigabit ethernet subsystem provides ethernet packet diff --git a/Bindings/net/ti,dp83822.yaml b/Bindings/net/ti,dp83822.yaml index db74474207e..784866ea392 100644 --- a/Bindings/net/ti,dp83822.yaml +++ b/Bindings/net/ti,dp83822.yaml @@ -62,6 +62,40 @@ properties: for the PHY. The internal delay for the PHY is fixed to 3.5ns relative to transmit data. + ti,cfg-dac-minus-one-bp: + description: | + DP83826 PHY only. + Sets the voltage ratio (with respect to the nominal value) + of the logical level -1 for the MLT-3 encoded TX data. + enum: [5000, 5625, 6250, 6875, 7500, 8125, 8750, 9375, 10000, + 10625, 11250, 11875, 12500, 13125, 13750, 14375, 15000] + default: 10000 + + ti,cfg-dac-plus-one-bp: + description: | + DP83826 PHY only. + Sets the voltage ratio (with respect to the nominal value) + of the logical level +1 for the MLT-3 encoded TX data. + enum: [5000, 5625, 6250, 6875, 7500, 8125, 8750, 9375, 10000, + 10625, 11250, 11875, 12500, 13125, 13750, 14375, 15000] + default: 10000 + + ti,rmii-mode: + description: | + If present, select the RMII operation mode. Two modes are + available: + - RMII master, where the PHY outputs a 50MHz reference clock which can + be connected to the MAC. + - RMII slave, where the PHY expects a 50MHz reference clock input + shared with the MAC. + The RMII operation mode can also be configured by its straps. + If the strap pin is not set correctly or not set at all, then this can be + used to configure it. + $ref: /schemas/types.yaml#/definitions/string + enum: + - master + - slave + required: - reg diff --git a/Bindings/net/ti,k3-am654-cpsw-nuss.yaml b/Bindings/net/ti,k3-am654-cpsw-nuss.yaml index c9c25132d15..73ed5951d29 100644 --- a/Bindings/net/ti,k3-am654-cpsw-nuss.yaml +++ b/Bindings/net/ti,k3-am654-cpsw-nuss.yaml @@ -7,8 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: The TI AM654x/J721E/AM642x SoC Gigabit Ethernet MAC (Media Access Controller) maintainers: - - Grygorii Strashko - - Sekhar Nori + - Siddharth Vadapalli + - Ravi Gunasekaran + - Roger Quadros description: The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports diff --git a/Bindings/net/ti,k3-am654-cpts.yaml b/Bindings/net/ti,k3-am654-cpts.yaml index 3e910d3b24a..b1c87532577 100644 --- a/Bindings/net/ti,k3-am654-cpts.yaml +++ b/Bindings/net/ti,k3-am654-cpts.yaml @@ -7,8 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: The TI AM654x/J721E Common Platform Time Sync (CPTS) module maintainers: - - Grygorii Strashko - - Sekhar Nori + - Siddharth Vadapalli + - Ravi Gunasekaran + - Roger Quadros description: |+ The TI AM654x/J721E CPTS module is used to facilitate host control of time diff --git a/Bindings/net/wireless/mediatek,mt76.yaml b/Bindings/net/wireless/mediatek,mt76.yaml index 252207adbc5..eabceb84953 100644 --- a/Bindings/net/wireless/mediatek,mt76.yaml +++ b/Bindings/net/wireless/mediatek,mt76.yaml @@ -19,9 +19,6 @@ description: | Alternatively, it can specify the wireless part of the MT7628/MT7688 or MT7622/MT7986 SoC. -allOf: - - $ref: ieee80211.yaml# - properties: compatible: enum: @@ -38,7 +35,12 @@ properties: MT7986 should contain 3 regions consys, dcm, and sku, in this order. interrupts: - maxItems: 1 + minItems: 1 + items: + - description: major interrupt for rings + - description: additional interrupt for ring 19 + - description: additional interrupt for ring 4 + - description: additional interrupt for ring 5 power-domains: maxItems: 1 @@ -217,6 +219,24 @@ required: - compatible - reg +allOf: + - $ref: ieee80211.yaml# + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt7981-wmac + - mediatek,mt7986-wmac + then: + properties: + interrupts: + minItems: 4 + else: + properties: + interrupts: + maxItems: 1 + unevaluatedProperties: false examples: @@ -293,7 +313,10 @@ examples: reg = <0x18000000 0x1000000>, <0x10003000 0x1000>, <0x11d10000 0x1000>; - interrupts = ; + interrupts = , + , + , + ; clocks = <&topckgen 50>, <&topckgen 62>; clock-names = "mcu", "ap2conn"; diff --git a/Bindings/net/wireless/qcom,ath10k.yaml b/Bindings/net/wireless/qcom,ath10k.yaml index 7758a55dd32..9b3ef4bc373 100644 --- a/Bindings/net/wireless/qcom,ath10k.yaml +++ b/Bindings/net/wireless/qcom,ath10k.yaml @@ -8,6 +8,7 @@ title: Qualcomm Technologies ath10k wireless devices maintainers: - Kalle Valo + - Jeff Johnson description: Qualcomm Technologies, Inc. IEEE 802.11ac devices. diff --git a/Bindings/net/wireless/qcom,ath11k-pci.yaml b/Bindings/net/wireless/qcom,ath11k-pci.yaml index 817f02a8b48..41d023797d7 100644 --- a/Bindings/net/wireless/qcom,ath11k-pci.yaml +++ b/Bindings/net/wireless/qcom,ath11k-pci.yaml @@ -9,6 +9,7 @@ title: Qualcomm Technologies ath11k wireless devices (PCIe) maintainers: - Kalle Valo + - Jeff Johnson description: | Qualcomm Technologies IEEE 802.11ax PCIe devices diff --git a/Bindings/net/wireless/qcom,ath11k.yaml b/Bindings/net/wireless/qcom,ath11k.yaml index 7d5f982a3d0..672282cdfc2 100644 --- a/Bindings/net/wireless/qcom,ath11k.yaml +++ b/Bindings/net/wireless/qcom,ath11k.yaml @@ -9,6 +9,7 @@ title: Qualcomm Technologies ath11k wireless devices maintainers: - Kalle Valo + - Jeff Johnson description: | These are dt entries for Qualcomm Technologies, Inc. IEEE 802.11ax diff --git a/Bindings/nvmem/layouts/fixed-cell.yaml b/Bindings/nvmem/layouts/fixed-cell.yaml index ac2381e6602..8b3826243dd 100644 --- a/Bindings/nvmem/layouts/fixed-cell.yaml +++ b/Bindings/nvmem/layouts/fixed-cell.yaml @@ -36,20 +36,18 @@ properties: allOf: - if: + properties: + compatible: + contains: + const: mac-base required: [ compatible ] then: - if: - properties: - compatible: - contains: - const: mac-base - then: - properties: - "#nvmem-cell-cells": - description: The first argument is a MAC address offset. - const: 1 - required: - - "#nvmem-cell-cells" + properties: + "#nvmem-cell-cells": + description: The first argument is a MAC address offset. + const: 1 + required: + - "#nvmem-cell-cells" required: - reg diff --git a/Bindings/nvmem/nvmem-provider.yaml b/Bindings/nvmem/nvmem-provider.yaml new file mode 100644 index 00000000000..4009a9a0384 --- /dev/null +++ b/Bindings/nvmem/nvmem-provider.yaml @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/nvmem-provider.yaml# +$schema: http://devicetree.org/meta-schemas/base.yaml# + +title: NVMEM (Non Volatile Memory) Provider + +maintainers: + - Srinivas Kandagatla + +select: true + +properties: + '#nvmem-cell-cells': + enum: [0, 1] + +additionalProperties: true diff --git a/Bindings/nvmem/xlnx,zynqmp-nvmem.txt b/Bindings/nvmem/xlnx,zynqmp-nvmem.txt deleted file mode 100644 index 4881561b3a0..00000000000 --- a/Bindings/nvmem/xlnx,zynqmp-nvmem.txt +++ /dev/null @@ -1,46 +0,0 @@ --------------------------------------------------------------------------- -= Zynq UltraScale+ MPSoC nvmem firmware driver binding = --------------------------------------------------------------------------- -The nvmem_firmware node provides access to the hardware related data -like soc revision, IDCODE... etc, By using the firmware interface. - -Required properties: -- compatible: should be "xlnx,zynqmp-nvmem-fw" - -= Data cells = -Are child nodes of silicon id, bindings of which as described in -bindings/nvmem/nvmem.txt - -------- - Example -------- -firmware { - zynqmp_firmware: zynqmp-firmware { - compatible = "xlnx,zynqmp-firmware"; - method = "smc"; - - nvmem_firmware { - compatible = "xlnx,zynqmp-nvmem-fw"; - #address-cells = <1>; - #size-cells = <1>; - - /* Data cells */ - soc_revision: soc_revision { - reg = <0x0 0x4>; - }; - }; - }; -}; - -= Data consumers = -Are device nodes which consume nvmem data cells. - -For example: - pcap { - ... - - nvmem-cells = <&soc_revision>; - nvmem-cell-names = "soc_revision"; - - ... - }; diff --git a/Bindings/nvmem/xlnx,zynqmp-nvmem.yaml b/Bindings/nvmem/xlnx,zynqmp-nvmem.yaml new file mode 100644 index 00000000000..917c40d5c38 --- /dev/null +++ b/Bindings/nvmem/xlnx,zynqmp-nvmem.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/xlnx,zynqmp-nvmem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Zynq UltraScale+ MPSoC Non Volatile Memory interface + +description: | + The ZynqMP MPSoC provides access to the hardware related data + like SOC revision, IDCODE and specific purpose efuses. + +maintainers: + - Kalyani Akula + - Praveen Teja Kundanala + +allOf: + - $ref: nvmem.yaml# + +properties: + compatible: + const: xlnx,zynqmp-nvmem-fw + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + nvmem { + compatible = "xlnx,zynqmp-nvmem-fw"; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + soc_revision: soc-revision@0 { + reg = <0x0 0x4>; + }; + }; + }; diff --git a/Bindings/opp/opp-v2-base.yaml b/Bindings/opp/opp-v2-base.yaml index e2f8f7af3cf..b1bb87c865e 100644 --- a/Bindings/opp/opp-v2-base.yaml +++ b/Bindings/opp/opp-v2-base.yaml @@ -57,8 +57,6 @@ patternProperties: specific binding. minItems: 1 maxItems: 32 - items: - maxItems: 1 opp-microvolt: description: | diff --git a/Bindings/pci/fsl,imx6q-pcie-common.yaml b/Bindings/pci/fsl,imx6q-pcie-common.yaml index d91b639ae7a..a8b34f58f8f 100644 --- a/Bindings/pci/fsl,imx6q-pcie-common.yaml +++ b/Bindings/pci/fsl,imx6q-pcie-common.yaml @@ -150,22 +150,6 @@ allOf: - {} - const: pcie_phy - const: pcie_aux - - if: - properties: - compatible: - not: - contains: - enum: - - fsl,imx6sx-pcie - - fsl,imx8mq-pcie - - fsl,imx6sx-pcie-ep - - fsl,imx8mq-pcie-ep - then: - properties: - clocks: - maxItems: 3 - clock-names: - maxItems: 3 - if: properties: @@ -223,6 +207,7 @@ allOf: - fsl,imx6sx-pcie - fsl,imx6q-pcie - fsl,imx6qp-pcie + - fsl,imx95-pcie - fsl,imx6sx-pcie-ep - fsl,imx6q-pcie-ep - fsl,imx6qp-pcie-ep diff --git a/Bindings/pci/fsl,imx6q-pcie-ep.yaml b/Bindings/pci/fsl,imx6q-pcie-ep.yaml index ee155ed5f18..a06f75df845 100644 --- a/Bindings/pci/fsl,imx6q-pcie-ep.yaml +++ b/Bindings/pci/fsl,imx6q-pcie-ep.yaml @@ -22,14 +22,7 @@ properties: - fsl,imx8mm-pcie-ep - fsl,imx8mq-pcie-ep - fsl,imx8mp-pcie-ep - - reg: - minItems: 2 - - reg-names: - items: - - const: dbi - - const: addr_space + - fsl,imx95-pcie-ep clocks: minItems: 3 @@ -66,7 +59,44 @@ allOf: properties: compatible: enum: + - fsl,imx8mm-pcie-ep - fsl,imx8mq-pcie-ep + - fsl,imx8mp-pcie-ep + then: + properties: + reg: + minItems: 2 + maxItems: 2 + reg-names: + items: + - const: dbi + - const: addr_space + + - if: + properties: + compatible: + enum: + - fsl,imx95-pcie-ep + then: + properties: + reg: + minItems: 6 + maxItems: 6 + reg-names: + items: + - const: dbi + - const: atu + - const: dbi2 + - const: app + - const: dma + - const: addr_space + + - if: + properties: + compatible: + enum: + - fsl,imx8mq-pcie-ep + - fsl,imx95-pcie-ep then: properties: clocks: diff --git a/Bindings/pci/fsl,imx6q-pcie.yaml b/Bindings/pci/fsl,imx6q-pcie.yaml index 81bbb8728f0..8b8d77b1154 100644 --- a/Bindings/pci/fsl,imx6q-pcie.yaml +++ b/Bindings/pci/fsl,imx6q-pcie.yaml @@ -29,16 +29,7 @@ properties: - fsl,imx8mq-pcie - fsl,imx8mm-pcie - fsl,imx8mp-pcie - - reg: - items: - - description: Data Bus Interface (DBI) registers. - - description: PCIe configuration space region. - - reg-names: - items: - - const: dbi - - const: config + - fsl,imx95-pcie clocks: minItems: 3 @@ -90,6 +81,43 @@ required: allOf: - $ref: /schemas/pci/snps,dw-pcie.yaml# - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml# + - if: + properties: + compatible: + enum: + - fsl,imx6q-pcie + - fsl,imx6sx-pcie + - fsl,imx6qp-pcie + - fsl,imx7d-pcie + - fsl,imx8mq-pcie + - fsl,imx8mm-pcie + - fsl,imx8mp-pcie + then: + properties: + reg: + maxItems: 2 + reg-names: + items: + - const: dbi + - const: config + + - if: + properties: + compatible: + enum: + - fsl,imx95-pcie + then: + properties: + reg: + minItems: 4 + maxItems: 4 + reg-names: + items: + - const: dbi + - const: config + - const: atu + - const: app + - if: properties: compatible: @@ -111,6 +139,7 @@ allOf: compatible: enum: - fsl,imx8mq-pcie + - fsl,imx95-pcie then: properties: clocks: diff --git a/Bindings/pci/qcom,pcie-common.yaml b/Bindings/pci/qcom,pcie-common.yaml new file mode 100644 index 00000000000..0d1b23523f6 --- /dev/null +++ b/Bindings/pci/qcom,pcie-common.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PCI Express Root Complex Common Properties + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +properties: + reg: + minItems: 4 + maxItems: 6 + + reg-names: + minItems: 4 + maxItems: 6 + + interrupts: + minItems: 1 + maxItems: 8 + + interrupt-names: + minItems: 1 + maxItems: 8 + + iommu-map: + minItems: 1 + maxItems: 16 + + clocks: + minItems: 3 + maxItems: 13 + + clock-names: + minItems: 3 + maxItems: 13 + + dma-coherent: true + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: pcie-mem + - const: cpu-pcie + + phys: + maxItems: 1 + + phy-names: + items: + - const: pciephy + + power-domains: + maxItems: 1 + + required-opps: + maxItems: 1 + + resets: + minItems: 1 + maxItems: 12 + + reset-names: + minItems: 1 + maxItems: 12 + + perst-gpios: + description: GPIO controlled connection to PERST# signal + maxItems: 1 + + wake-gpios: + description: GPIO controlled connection to WAKE# signal + maxItems: 1 + +required: + - reg + - reg-names + - interrupt-map-mask + - interrupt-map + - clocks + - clock-names + +anyOf: + - required: + - interrupts + - interrupt-names + - "#interrupt-cells" + - required: + - msi-map + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +additionalProperties: true diff --git a/Bindings/pci/qcom,pcie-sa8775p.yaml b/Bindings/pci/qcom,pcie-sa8775p.yaml new file mode 100644 index 00000000000..efde49d1bef --- /dev/null +++ b/Bindings/pci/qcom,pcie-sa8775p.yaml @@ -0,0 +1,166 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sa8775p.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SA8775p PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SA8775p SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-sa8775p + + reg: + minItems: 6 + maxItems: 6 + + reg-names: + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 5 + maxItems: 5 + + clock-names: + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + +required: + - interconnects + - interconnect-names + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c00000 { + compatible = "qcom,pcie-sa8775p"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf20>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x4000>, + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; + assigned-clock-rates = <19200000>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + dma-coherent; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; + + interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, + <0x100 &pcie_smmu 0x0001 0x1>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + power-domains = <&gcc PCIE_0_GDSC>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Bindings/pci/qcom,pcie-sc7280.yaml b/Bindings/pci/qcom,pcie-sc7280.yaml new file mode 100644 index 00000000000..634da24ec3e --- /dev/null +++ b/Bindings/pci/qcom,pcie-sc7280.yaml @@ -0,0 +1,166 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sc7280.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC7280 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SC7280 SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-sc7280 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 13 + maxItems: 13 + + clock-names: + items: + - const: pipe # PIPE clock + - const: pipe_mux # PIPE MUX + - const: phy_pipe # PIPE output clock + - const: ref # REFERENCE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock + + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: msi + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + + vddpe-3v3-supply: + description: PCIe endpoint power supply + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c08000 { + compatible = "qcom,pcie-sc7280"; + reg = <0 0x01c08000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <1>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates = <19200000>; + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, + <&pcie1_phy>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; + + clock-names = "pipe", + "pipe_mux", + "phy_pipe", + "ref", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu", + "aggre0", + "aggre1"; + + dma-coherent; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; + + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>; + + phys = <&pcie1_phy>; + phy-names = "pciephy"; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_clkreq_n>; + + power-domains = <&gcc GCC_PCIE_1_GDSC>; + + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + vddpe-3v3-supply = <&pp3300_ssd>; + }; + }; diff --git a/Bindings/pci/qcom,pcie-sc8180x.yaml b/Bindings/pci/qcom,pcie-sc8180x.yaml new file mode 100644 index 00000000000..baf1813ec0a --- /dev/null +++ b/Bindings/pci/qcom,pcie-sc8180x.yaml @@ -0,0 +1,170 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sc8180x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC8180x PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SC8180x SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-sc8180x + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 8 + maxItems: 8 + + clock-names: + items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ref # REFERENCE clock + - const: tbu # PCIe TBU clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c00000 { + compatible = "qcom,pcie-sc8180x"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config"; + ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; + assigned-clock-rates = <19200000>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref", + "tbu"; + + dma-coherent; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, + <0x100 &apps_smmu 0x1d81 0x1>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + power-domains = <&gcc PCIE_0_GDSC>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + }; + }; diff --git a/Bindings/pci/qcom,pcie-sc8280xp.yaml b/Bindings/pci/qcom,pcie-sc8280xp.yaml new file mode 100644 index 00000000000..25c9f13ae97 --- /dev/null +++ b/Bindings/pci/qcom,pcie-sc8280xp.yaml @@ -0,0 +1,180 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sc8280xp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC8280XP PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SC8280XP SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + enum: + - qcom,pcie-sa8540p + - qcom,pcie-sc8280xp + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 8 + maxItems: 9 + + clock-names: + minItems: 8 + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: noc_aggr_4 # NoC aggregate 4 clock + - const: noc_aggr_south_sf # NoC aggregate South SF clock + - const: cnoc_qx # Configuration NoC QX clock + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + + vddpe-3v3-supply: + description: A phandle to the PCIe endpoint power supply + +required: + - interconnects + - interconnect-names + +allOf: + - $ref: qcom,pcie-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sc8280xp + then: + properties: + interrupts: + minItems: 4 + maxItems: 4 + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + else: + properties: + interrupts: + maxItems: 1 + interrupt-names: + items: + - const: msi + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c20000 { + compatible = "qcom,pcie-sc8280xp"; + reg = <0x0 0x01c20000 0x0 0x3000>, + <0x0 0x3c000000 0x0 0xf1d>, + <0x0 0x3c000f20 0x0 0xa8>, + <0x0 0x3c001000 0x0 0x1000>, + <0x0 0x3c100000 0x0 0x100000>, + <0x0 0x01c23000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, + <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <2>; + num-lanes = <4>; + + #address-cells = <3>; + #size-cells = <2>; + + assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>; + assigned-clock-rates = <19200000>; + clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, + <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_2A_SLV_AXI_CLK>, + <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "noc_aggr_4", + "noc_aggr_south_sf"; + + dma-coherent; + + interrupts = , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; + + interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + phys = <&pcie2a_phy>; + phy-names = "pciephy"; + + pinctrl-0 = <&pcie2a_default>; + pinctrl-names = "default"; + + power-domains = <&gcc PCIE_2A_GDSC>; + + resets = <&gcc GCC_PCIE_2A_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; + vddpe-3v3-supply = <&vreg_nvme>; + }; + }; diff --git a/Bindings/pci/qcom,pcie-sm8150.yaml b/Bindings/pci/qcom,pcie-sm8150.yaml new file mode 100644 index 00000000000..9d569644fda --- /dev/null +++ b/Bindings/pci/qcom,pcie-sm8150.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8150.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8150 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SM8150 SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-sm8150 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 8 + maxItems: 8 + + clock-names: + items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ref # REFERENCE clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie@1c00000 { + compatible = "qcom,pcie-sm8150"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ref"; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, + <0x100 &apps_smmu 0x1d81 0x1>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + power-domains = <&gcc PCIE_0_GDSC>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Bindings/pci/qcom,pcie-sm8250.yaml b/Bindings/pci/qcom,pcie-sm8250.yaml new file mode 100644 index 00000000000..4d060bce6f9 --- /dev/null +++ b/Bindings/pci/qcom,pcie-sm8250.yaml @@ -0,0 +1,173 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8250.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8250 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SM8250 SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-sm8250 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 8 + maxItems: 9 + + clock-names: + # Unfortunately the "optional" ref clock is used in the middle of the list + oneOf: + - items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ref # REFERENCE clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c00000 { + compatible = "qcom,pcie-sm8250"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>, + <0 0x01c03000 0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu"; + + dma-coherent; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + power-domains = <&gcc PCIE_0_GDSC>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Bindings/pci/qcom,pcie-sm8350.yaml b/Bindings/pci/qcom,pcie-sm8350.yaml new file mode 100644 index 00000000000..9eb6e457b07 --- /dev/null +++ b/Bindings/pci/qcom,pcie-sm8350.yaml @@ -0,0 +1,184 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8350.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8350 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SM8350 SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-sm8350 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 8 + maxItems: 9 + + clock-names: + minItems: 8 + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock + - const: aggre0 # Aggre NoC PCIe0 AXI clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + +oneOf: + - properties: + interrupts: + maxItems: 1 + interrupt-names: + items: + - const: msi + + - properties: + interrupts: + minItems: 8 + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c00000 { + compatible = "qcom,pcie-sm8350"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu", + "aggre1", + "aggre0"; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + power-domains = <&gcc PCIE_0_GDSC>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Bindings/pci/qcom,pcie-sm8450.yaml b/Bindings/pci/qcom,pcie-sm8450.yaml new file mode 100644 index 00000000000..1496d6993ab --- /dev/null +++ b/Bindings/pci/qcom,pcie-sm8450.yaml @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8450.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8450 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SM8450 SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + enum: + - qcom,pcie-sm8450-pcie0 + - qcom,pcie-sm8450-pcie1 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 11 + maxItems: 12 + + clock-names: + minItems: 11 + items: + - const: pipe # PIPE clock + - const: pipe_mux # PIPE MUX + - const: phy_pipe # PIPE output clock + - const: ref # REFERENCE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - enum: [aggre0, aggre1] # Aggre NoC PCIe0/1 AXI clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c00000 { + compatible = "qcom,pcie-sm8450-pcie0"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + max-link-speed = <2>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, + <&pcie0_phy>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; + clock-names = "pipe", + "pipe_mux", + "phy_pipe", + "ref", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "aggre0", + "aggre1"; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + msi-map = <0x0 &gic_its 0x5981 0x1>, + <0x100 &gic_its 0x5980 0x1>; + msi-map-mask = <0xff00>; + + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + power-domains = <&gcc PCIE_0_GDSC>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Bindings/pci/qcom,pcie-sm8550.yaml b/Bindings/pci/qcom,pcie-sm8550.yaml new file mode 100644 index 00000000000..24cb3867358 --- /dev/null +++ b/Bindings/pci/qcom,pcie-sm8550.yaml @@ -0,0 +1,171 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8550.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8550 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SM8550 SoC (and compatible) PCIe root complex controller is based on + the Synopsys DesignWare PCIe IP. + +properties: + compatible: + oneOf: + - const: qcom,pcie-sm8550 + - items: + - enum: + - qcom,pcie-sm8650 + - const: qcom,pcie-sm8550 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 7 + maxItems: 8 + + clock-names: + minItems: 7 + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: noc_aggr # Aggre NoC PCIe AXI clock + - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + minItems: 1 + items: + - const: pci # PCIe core reset + - const: link_down # PCIe link down reset + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c00000 { + compatible = "qcom,pcie-sm8550"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "noc_aggr"; + + dma-coherent; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommu-map = <0x0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + power-domains = <&gcc PCIE_0_GDSC>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Bindings/pci/qcom,pcie-x1e80100.yaml b/Bindings/pci/qcom,pcie-x1e80100.yaml new file mode 100644 index 00000000000..1074310a8e7 --- /dev/null +++ b/Bindings/pci/qcom,pcie-x1e80100.yaml @@ -0,0 +1,165 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm X1E80100 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm X1E80100 SoC (and compatible) PCIe root complex controller is based on + the Synopsys DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-x1e80100 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 7 + maxItems: 7 + + clock-names: + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: noc_aggr # Aggre NoC PCIe AXI clock + - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + minItems: 1 + items: + - const: pci # PCIe core reset + - const: link_down # PCIe link down reset + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c08000 { + compatible = "qcom,pcie-x1e80100"; + reg = <0 0x01c08000 0 0x3000>, + <0 0x7c000000 0 0xf1d>, + <0 0x7c000f40 0 0xa8>, + <0 0x7c001000 0 0x1000>, + <0 0x7c100000 0 0x100000>, + <0 0x01c0b000 0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + clocks = <&gcc GCC_PCIE_4_AUX_CLK>, + <&gcc GCC_PCIE_4_CFG_AHB_CLK>, + <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_4_SLV_AXI_CLK>, + <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, + <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr", + "cnoc_sf_axi"; + + dma-coherent; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + interconnects = <&pcie_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_4 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommu-map = <0x0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>; + + phys = <&pcie4_phy>; + phy-names = "pciephy"; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + power-domains = <&gcc GCC_PCIE_4_GDSC>; + + resets = <&gcc GCC_PCIE_4_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Bindings/pci/qcom,pcie.yaml b/Bindings/pci/qcom,pcie.yaml index a93ab3b5406..cf9a6910b54 100644 --- a/Bindings/pci/qcom,pcie.yaml +++ b/Bindings/pci/qcom,pcie.yaml @@ -28,23 +28,8 @@ properties: - qcom,pcie-ipq8074-gen3 - qcom,pcie-msm8996 - qcom,pcie-qcs404 - - qcom,pcie-sa8540p - - qcom,pcie-sa8775p - - qcom,pcie-sc7280 - - qcom,pcie-sc8180x - - qcom,pcie-sc8280xp - qcom,pcie-sdm845 - qcom,pcie-sdx55 - - qcom,pcie-sm8150 - - qcom,pcie-sm8250 - - qcom,pcie-sm8350 - - qcom,pcie-sm8450-pcie0 - - qcom,pcie-sm8450-pcie1 - - qcom,pcie-sm8550 - - items: - - enum: - - qcom,pcie-sm8650 - - const: qcom,pcie-sm8550 - items: - const: qcom,pcie-msm8998 - const: qcom,pcie-msm8996 @@ -106,9 +91,6 @@ properties: vdda_refclk-supply: description: A phandle to the core analog power supply for IC which generates reference clock - vddpe-3v3-supply: - description: A phandle to the PCIe endpoint power supply - phys: maxItems: 1 @@ -123,6 +105,9 @@ properties: description: GPIO controlled connection to PERST# signal maxItems: 1 + required-opps: + maxItems: 1 + wake-gpios: description: GPIO controlled connection to WAKE# signal maxItems: 1 @@ -143,7 +128,6 @@ anyOf: - "#interrupt-cells" - required: - msi-map - - msi-map-mask allOf: - $ref: /schemas/pci/pci-bus.yaml# @@ -217,16 +201,7 @@ allOf: compatible: contains: enum: - - qcom,pcie-sa8775p - - qcom,pcie-sc7280 - - qcom,pcie-sc8180x - - qcom,pcie-sc8280xp - qcom,pcie-sdx55 - - qcom,pcie-sm8250 - - qcom,pcie-sm8350 - - qcom,pcie-sm8450-pcie0 - - qcom,pcie-sm8450-pcie1 - - qcom,pcie-sm8550 then: properties: reg: @@ -451,65 +426,6 @@ allOf: - const: pwr # PWR reset - const: ahb # AHB reset - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sc7280 - then: - properties: - clocks: - minItems: 13 - maxItems: 13 - clock-names: - items: - - const: pipe # PIPE clock - - const: pipe_mux # PIPE MUX - - const: phy_pipe # PIPE output clock - - const: ref # REFERENCE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: tbu # PCIe TBU clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock - - const: aggre1 # Aggre NoC PCIe1 AXI clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sc8180x - then: - properties: - clocks: - minItems: 8 - maxItems: 8 - clock-names: - items: - - const: pipe # PIPE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ref # REFERENCE clock - - const: tbu # PCIe TBU clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - if: properties: compatible: @@ -553,229 +469,6 @@ allOf: items: - const: pci # PCIe core reset - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8150 - then: - properties: - clocks: - minItems: 8 - maxItems: 8 - clock-names: - items: - - const: pipe # PIPE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: tbu # PCIe TBU clock - - const: ref # REFERENCE clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8250 - then: - oneOf: - # Unfortunately the "optional" ref clock is used in the middle of the list - - properties: - clocks: - minItems: 9 - maxItems: 9 - clock-names: - items: - - const: pipe # PIPE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ref # REFERENCE clock - - const: tbu # PCIe TBU clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - properties: - clocks: - minItems: 8 - maxItems: 8 - clock-names: - items: - - const: pipe # PIPE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: tbu # PCIe TBU clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - properties: - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8350 - then: - properties: - clocks: - minItems: 8 - maxItems: 9 - clock-names: - minItems: 8 - items: - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: tbu # PCIe TBU clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: aggre1 # Aggre NoC PCIe1 AXI clock - - const: aggre0 # Aggre NoC PCIe0 AXI clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8450-pcie0 - then: - properties: - clocks: - minItems: 12 - maxItems: 12 - clock-names: - items: - - const: pipe # PIPE clock - - const: pipe_mux # PIPE MUX - - const: phy_pipe # PIPE output clock - - const: ref # REFERENCE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: aggre0 # Aggre NoC PCIe0 AXI clock - - const: aggre1 # Aggre NoC PCIe1 AXI clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8450-pcie1 - then: - properties: - clocks: - minItems: 11 - maxItems: 11 - clock-names: - items: - - const: pipe # PIPE clock - - const: pipe_mux # PIPE MUX - - const: phy_pipe # PIPE output clock - - const: ref # REFERENCE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: aggre1 # Aggre NoC PCIe1 AXI clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8550 - then: - properties: - clocks: - minItems: 7 - maxItems: 8 - clock-names: - minItems: 7 - items: - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: noc_aggr # Aggre NoC PCIe AXI clock - - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock - resets: - minItems: 1 - maxItems: 2 - reset-names: - minItems: 1 - items: - - const: pci # PCIe core reset - - const: link_down # PCIe link down reset - - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sa8540p - - qcom,pcie-sc8280xp - then: - properties: - clocks: - minItems: 8 - maxItems: 9 - clock-names: - minItems: 8 - items: - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: noc_aggr_4 # NoC aggregate 4 clock - - const: noc_aggr_south_sf # NoC aggregate South SF clock - - const: cnoc_qx # Configuration NoC QX clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - if: properties: compatible: @@ -802,43 +495,6 @@ allOf: items: - const: pci # PCIe core reset - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sa8775p - then: - properties: - clocks: - minItems: 5 - maxItems: 5 - clock-names: - items: - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sa8540p - - qcom,pcie-sa8775p - - qcom,pcie-sc8280xp - then: - required: - - interconnects - - interconnect-names - - if: not: properties: @@ -874,16 +530,7 @@ allOf: contains: enum: - qcom,pcie-msm8996 - - qcom,pcie-sa8775p - - qcom,pcie-sc7280 - - qcom,pcie-sc8180x - qcom,pcie-sdm845 - - qcom,pcie-sm8150 - - qcom,pcie-sm8250 - - qcom,pcie-sm8350 - - qcom,pcie-sm8450-pcie0 - - qcom,pcie-sm8450-pcie1 - - qcom,pcie-sm8550 then: oneOf: - properties: @@ -906,24 +553,6 @@ allOf: - const: msi6 - const: msi7 - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sc8280xp - then: - properties: - interrupts: - minItems: 4 - maxItems: 4 - interrupt-names: - items: - - const: msi0 - - const: msi1 - - const: msi2 - - const: msi3 - - if: properties: compatible: @@ -938,7 +567,6 @@ allOf: - qcom,pcie-ipq8074 - qcom,pcie-ipq8074-gen3 - qcom,pcie-qcs404 - - qcom,pcie-sa8540p then: properties: interrupts: diff --git a/Bindings/perf/arm,coresight-pmu.yaml b/Bindings/perf/arm,coresight-pmu.yaml new file mode 100644 index 00000000000..985b62990f8 --- /dev/null +++ b/Bindings/perf/arm,coresight-pmu.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/perf/arm,coresight-pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm Coresight Performance Monitoring Unit Architecture + +maintainers: + - Robin Murphy + +properties: + compatible: + const: arm,coresight-pmu + + reg: + items: + - description: Register page 0 + - description: Register page 1, if the PMU implements the dual-page extension + minItems: 1 + + interrupts: + items: + - description: Overflow interrupt + + cpus: + description: If the PMU is associated with a particular CPU or subset of CPUs, + array of phandles to the appropriate CPU node(s) + + reg-io-width: + description: Granularity at which PMU register accesses are single-copy atomic + default: 4 + enum: [4, 8] + +required: + - compatible + - reg + +additionalProperties: false diff --git a/Bindings/perf/starfive,jh8100-starlink-pmu.yaml b/Bindings/perf/starfive,jh8100-starlink-pmu.yaml new file mode 100644 index 00000000000..915c6b81402 --- /dev/null +++ b/Bindings/perf/starfive,jh8100-starlink-pmu.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/perf/starfive,jh8100-starlink-pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 StarLink PMU + +maintainers: + - Ji Sheng Teoh + +description: + StarFive's JH8100 StarLink PMU integrates one or more CPU cores with a + shared L3 memory system. The PMU support overflow interrupt, up to + 16 programmable 64bit event counters, and an independent 64bit cycle + counter. StarFive's JH8100 StarLink PMU is accessed via MMIO. + +properties: + compatible: + const: starfive,jh8100-starlink-pmu + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pmu@12900000 { + compatible = "starfive,jh8100-starlink-pmu"; + reg = <0x0 0x12900000 0x0 0x10000>; + interrupts = <34>; + }; + }; diff --git a/Bindings/phy/mediatek,mt8365-csi-rx.yaml b/Bindings/phy/mediatek,mt8365-csi-rx.yaml new file mode 100644 index 00000000000..2127a5732f7 --- /dev/null +++ b/Bindings/phy/mediatek,mt8365-csi-rx.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2023 MediaTek, BayLibre +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/mediatek,mt8365-csi-rx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Sensor Interface MIPI CSI CD-PHY + +maintainers: + - Julien Stephan + - Andy Hsieh + +description: + The SENINF CD-PHY is a set of CD-PHY connected to the SENINF CSI-2 + receivers. The number of PHYs depends on the SoC model. + Depending on the SoC model, each PHYs can be either CD-PHY or D-PHY only + capable. + +properties: + compatible: + enum: + - mediatek,mt8365-csi-rx + + reg: + maxItems: 1 + + num-lanes: + enum: [2, 3, 4] + + '#phy-cells': + enum: [0, 1] + description: | + If the PHY doesn't support mode selection then #phy-cells must be 0 and + PHY mode is described using phy-type property. + If the PHY supports mode selection, then #phy-cells must be 1 and mode + is set in the PHY cells. Supported modes are: + - PHY_TYPE_DPHY + - PHY_TYPE_CPHY + See include/dt-bindings/phy/phy.h for constants. + + phy-type: + description: + If the PHY doesn't support mode selection then this set the operating mode. + See include/dt-bindings/phy/phy.h for constants. + const: 10 + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - num-lanes + - '#phy-cells' + +additionalProperties: false + +examples: + - | + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + + csi0_rx: phy@11c10000 { + compatible = "mediatek,mt8365-csi-rx"; + reg = <0 0x11c10000 0 0x2000>; + num-lanes = <2>; + #phy-cells = <1>; + }; + + csi1_rx: phy@11c12000 { + compatible = "mediatek,mt8365-csi-rx"; + reg = <0 0x11c12000 0 0x2000>; + phy-type = ; + num-lanes = <2>; + #phy-cells = <0>; + }; + }; +... diff --git a/Bindings/phy/phy-cadence-torrent.yaml b/Bindings/phy/phy-cadence-torrent.yaml index dfb31314fac..15dc8efe6ff 100644 --- a/Bindings/phy/phy-cadence-torrent.yaml +++ b/Bindings/phy/phy-cadence-torrent.yaml @@ -20,6 +20,7 @@ properties: compatible: enum: - cdns,torrent-phy + - ti,j7200-serdes-10g - ti,j721e-serdes-10g '#address-cells': @@ -35,14 +36,18 @@ properties: minItems: 1 maxItems: 2 description: - PHY reference clock for 1 item. Must contain an entry in clock-names. - Optional Parent to enable output reference clock. + PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1). + pll1_refclk is optional and used for multi-protocol configurations requiring + separate reference clock for each protocol. + Same refclk is used for both PLL0 and PLL1 if no separate pll1_refclk is used. + Optional parent clock (phy_en_refclk) to enable a reference clock output feature + on some platforms to output either derived or received reference clock. clock-names: minItems: 1 items: - const: refclk - - const: phy_en_refclk + - enum: [ pll1_refclk, phy_en_refclk ] reg: minItems: 1 diff --git a/Bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml b/Bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml new file mode 100644 index 00000000000..f1f4e4f8335 --- /dev/null +++ b/Bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml @@ -0,0 +1,184 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,msm8998-qmp-usb3-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QMP PHY controller (USB, MSM8998) + +maintainers: + - Vinod Koul + +description: + The QMP PHY controller supports physical layer functionality for USB-C on + several Qualcomm chipsets. + +properties: + compatible: + enum: + - qcom,msm8998-qmp-usb3-phy + - qcom,qcm2290-qmp-usb3-phy + - qcom,sdm660-qmp-usb3-phy + - qcom,sm6115-qmp-usb3-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + + clock-names: + maxItems: 4 + + resets: + maxItems: 2 + + reset-names: + items: + - const: phy + - const: phy_phy + + vdda-phy-supply: true + + vdda-pll-supply: true + + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + + "#phy-cells": + const: 0 + + orientation-switch: + description: + Flag the PHY as possible handler of USB Type-C orientation switching + type: boolean + + qcom,tcsr-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to TCSR hardware block + - description: offset of the VLS CLAMP register + description: Clamp register present in the TCSR + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Output endpoint of the PHY + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Incoming endpoint from the USB controller + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - vdda-phy-supply + - vdda-pll-supply + - "#clock-cells" + - clock-output-names + - "#phy-cells" + - qcom,tcsr-reg + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8998-qmp-usb3-phy + - qcom,sdm660-qmp-usb3-phy + then: + properties: + clocks: + maxItems: 4 + clock-names: + items: + - const: aux + - const: ref + - const: cfg_ahb + - const: pipe + + - if: + properties: + compatible: + contains: + enum: + - qcom,qcm2290-qmp-usb3-phy + - qcom,sm6115-qmp-usb3-phy + then: + properties: + clocks: + maxItems: 4 + clock-names: + items: + - const: cfg_ahb + - const: ref + - const: com_aux + - const: pipe + +additionalProperties: false + +examples: + - | + #include + #include + + phy@c010000 { + compatible = "qcom,msm8998-qmp-usb3-phy"; + reg = <0x0c010000 0x1000>; + + clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, + <&gcc GCC_USB3_CLKREF_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "cfg_ahb", + "pipe"; + clock-output-names = "usb3_phy_pipe_clk_src"; + #clock-cells = <0>; + #phy-cells = <0>; + + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "phy", + "phy_phy"; + + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l2a_1p2>; + + orientation-switch; + + qcom,tcsr-reg = <&tcsr_regs_1 0x6b244>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&pmic_typec_mux_in>; + }; + }; + + port@1 { + reg = <1>; + + endpoint { + remote-endpoint = <&usb_dwc3_ss>; + }; + }; + }; + }; diff --git a/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 6c03f2d5fca..ba966a78a12 100644 --- a/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -38,6 +38,8 @@ properties: - qcom,sm8550-qmp-gen4x2-pcie-phy - qcom,sm8650-qmp-gen3x2-pcie-phy - qcom,sm8650-qmp-gen4x2-pcie-phy + - qcom,x1e80100-qmp-gen3x2-pcie-phy + - qcom,x1e80100-qmp-gen4x2-pcie-phy reg: minItems: 1 @@ -151,6 +153,8 @@ allOf: - qcom,sm8550-qmp-gen4x2-pcie-phy - qcom,sm8650-qmp-gen3x2-pcie-phy - qcom,sm8650-qmp-gen4x2-pcie-phy + - qcom,x1e80100-qmp-gen3x2-pcie-phy + - qcom,x1e80100-qmp-gen4x2-pcie-phy then: properties: clocks: @@ -194,6 +198,8 @@ allOf: enum: - qcom,sm8550-qmp-gen4x2-pcie-phy - qcom,sm8650-qmp-gen4x2-pcie-phy + - qcom,x1e80100-qmp-gen3x2-pcie-phy + - qcom,x1e80100-qmp-gen4x2-pcie-phy then: properties: resets: diff --git a/Bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml index 8474eef8d0f..91a6cc38ff7 100644 --- a/Bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml +++ b/Bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml @@ -19,6 +19,7 @@ properties: - qcom,msm8996-qmp-ufs-phy - qcom,msm8998-qmp-ufs-phy - qcom,sa8775p-qmp-ufs-phy + - qcom,sc7180-qmp-ufs-phy - qcom,sc7280-qmp-ufs-phy - qcom,sc8180x-qmp-ufs-phy - qcom,sc8280xp-qmp-ufs-phy @@ -38,15 +39,12 @@ properties: maxItems: 1 clocks: - minItems: 1 + minItems: 2 maxItems: 3 clock-names: - minItems: 1 - items: - - const: ref - - const: ref_aux - - const: qref + minItems: 2 + maxItems: 3 power-domains: maxItems: 1 @@ -86,22 +84,9 @@ allOf: compatible: contains: enum: + - qcom,msm8998-qmp-ufs-phy - qcom,sa8775p-qmp-ufs-phy - qcom,sc7280-qmp-ufs-phy - - qcom,sm8450-qmp-ufs-phy - then: - properties: - clocks: - minItems: 3 - clock-names: - minItems: 3 - - - if: - properties: - compatible: - contains: - enum: - - qcom,msm8998-qmp-ufs-phy - qcom,sc8180x-qmp-ufs-phy - qcom,sc8280xp-qmp-ufs-phy - qcom,sdm845-qmp-ufs-phy @@ -112,14 +97,19 @@ allOf: - qcom,sm8150-qmp-ufs-phy - qcom,sm8250-qmp-ufs-phy - qcom,sm8350-qmp-ufs-phy + - qcom,sm8450-qmp-ufs-phy - qcom,sm8550-qmp-ufs-phy - qcom,sm8650-qmp-ufs-phy then: properties: clocks: - maxItems: 2 + minItems: 3 + maxItems: 3 clock-names: - maxItems: 2 + items: + - const: ref + - const: ref_aux + - const: qref - if: properties: @@ -130,22 +120,28 @@ allOf: then: properties: clocks: - maxItems: 1 + minItems: 2 + maxItems: 2 clock-names: - maxItems: 1 + items: + - const: ref + - const: qref additionalProperties: false examples: - | #include + #include ufs_mem_phy: phy@1d87000 { compatible = "qcom,sc8280xp-qmp-ufs-phy"; reg = <0x01d87000 0x1000>; - clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - clock-names = "ref", "ref_aux"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_REF_CLKREF_CLK>; + + clock-names = "ref", "ref_aux", "qref"; power-domains = <&gcc UFS_PHY_GDSC>; diff --git a/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml b/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml index 15d82c67f15..1e2d4ddc539 100644 --- a/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml +++ b/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml @@ -20,15 +20,12 @@ properties: - qcom,ipq8074-qmp-usb3-phy - qcom,ipq9574-qmp-usb3-phy - qcom,msm8996-qmp-usb3-phy - - qcom,msm8998-qmp-usb3-phy - - qcom,qcm2290-qmp-usb3-phy - qcom,sa8775p-qmp-usb3-uni-phy - qcom,sc8280xp-qmp-usb3-uni-phy - qcom,sdm845-qmp-usb3-uni-phy - qcom,sdx55-qmp-usb3-uni-phy - qcom,sdx65-qmp-usb3-uni-phy - qcom,sdx75-qmp-usb3-uni-phy - - qcom,sm6115-qmp-usb3-phy - qcom,sm8150-qmp-usb3-uni-phy - qcom,sm8250-qmp-usb3-uni-phy - qcom,sm8350-qmp-usb3-uni-phy @@ -93,7 +90,6 @@ allOf: - qcom,ipq8074-qmp-usb3-phy - qcom,ipq9574-qmp-usb3-phy - qcom,msm8996-qmp-usb3-phy - - qcom,msm8998-qmp-usb3-phy - qcom,sdx55-qmp-usb3-uni-phy - qcom,sdx65-qmp-usb3-uni-phy - qcom,sdx75-qmp-usb3-uni-phy @@ -108,24 +104,6 @@ allOf: - const: cfg_ahb - const: pipe - - if: - properties: - compatible: - contains: - enum: - - qcom,qcm2290-qmp-usb3-phy - - qcom,sm6115-qmp-usb3-phy - then: - properties: - clocks: - maxItems: 4 - clock-names: - items: - - const: cfg_ahb - - const: ref - - const: com_aux - - const: pipe - - if: properties: compatible: diff --git a/Bindings/phy/rockchip,rk3588-hdptx-phy.yaml b/Bindings/phy/rockchip,rk3588-hdptx-phy.yaml new file mode 100644 index 00000000000..54e822c715f --- /dev/null +++ b/Bindings/phy/rockchip,rk3588-hdptx-phy.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip,rk3588-hdptx-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip SoC HDMI/eDP Transmitter Combo PHY + +maintainers: + - Cristian Ciocaltea + +properties: + compatible: + enum: + - rockchip,rk3588-hdptx-phy + + reg: + maxItems: 1 + + clocks: + items: + - description: Reference clock + - description: APB clock + + clock-names: + items: + - const: ref + - const: apb + + "#phy-cells": + const: 0 + + resets: + items: + - description: PHY reset line + - description: APB reset line + - description: INIT reset line + - description: CMN reset line + - description: LANE reset line + - description: ROPLL reset line + - description: LCPLL reset line + + reset-names: + items: + - const: phy + - const: apb + - const: init + - const: cmn + - const: lane + - const: ropll + - const: lcpll + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: Some PHY related data is accessed through GRF regs. + +required: + - compatible + - reg + - clocks + - clock-names + - "#phy-cells" + - resets + - reset-names + - rockchip,grf + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + phy@fed60000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0xfed60000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; + clock-names = "ref", "apb"; + #phy-cells = <0>; + resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, + <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, + <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, + <&cru SRST_HDPTX0_LCPLL>; + reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", "lcpll"; + rockchip,grf = <&hdptxphy_grf>; + }; + }; diff --git a/Bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml b/Bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml index c7df4cd3419..d9e0b2c48e8 100644 --- a/Bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml +++ b/Bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml @@ -24,7 +24,7 @@ required: - compatible patternProperties: - "^bank@[0-9a-z]+$": + "^bank@[0-9a-f]+$": $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-gpio unevaluatedProperties: false diff --git a/Bindings/pinctrl/amlogic,meson-pinctrl-g12a-aobus.yaml b/Bindings/pinctrl/amlogic,meson-pinctrl-g12a-aobus.yaml index 0942ea60c6c..108719bde0d 100644 --- a/Bindings/pinctrl/amlogic,meson-pinctrl-g12a-aobus.yaml +++ b/Bindings/pinctrl/amlogic,meson-pinctrl-g12a-aobus.yaml @@ -21,7 +21,7 @@ required: - compatible patternProperties: - "^bank@[0-9a-z]+$": + "^bank@[0-9a-f]+$": $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-gpio unevaluatedProperties: false diff --git a/Bindings/pinctrl/amlogic,meson-pinctrl-g12a-periphs.yaml b/Bindings/pinctrl/amlogic,meson-pinctrl-g12a-periphs.yaml index e3c8bde3055..dc277f2e2ed 100644 --- a/Bindings/pinctrl/amlogic,meson-pinctrl-g12a-periphs.yaml +++ b/Bindings/pinctrl/amlogic,meson-pinctrl-g12a-periphs.yaml @@ -21,7 +21,7 @@ required: - compatible patternProperties: - "^bank@[0-9a-z]+$": + "^bank@[0-9a-f]+$": $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-gpio unevaluatedProperties: false diff --git a/Bindings/pinctrl/amlogic,meson8-pinctrl-aobus.yaml b/Bindings/pinctrl/amlogic,meson8-pinctrl-aobus.yaml index c1b03147e8e..add83c67632 100644 --- a/Bindings/pinctrl/amlogic,meson8-pinctrl-aobus.yaml +++ b/Bindings/pinctrl/amlogic,meson8-pinctrl-aobus.yaml @@ -29,7 +29,7 @@ required: - compatible patternProperties: - "^bank@[0-9a-z]+$": + "^bank@[0-9a-f]+$": $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-gpio unevaluatedProperties: false diff --git a/Bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml b/Bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml index 4ec85b8248f..412bbcc276f 100644 --- a/Bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml +++ b/Bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml @@ -29,7 +29,7 @@ required: - compatible patternProperties: - "^bank@[0-9a-z]+$": + "^bank@[0-9a-f]+$": $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-gpio unevaluatedProperties: false diff --git a/Bindings/pinctrl/atmel,at91-pinctrl.txt b/Bindings/pinctrl/atmel,at91-pinctrl.txt index e8abbdad7b5..0aa1a53012d 100644 --- a/Bindings/pinctrl/atmel,at91-pinctrl.txt +++ b/Bindings/pinctrl/atmel,at91-pinctrl.txt @@ -20,6 +20,7 @@ such as pull-up, multi drive, etc. Required properties for iomux controller: - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl" or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl" + or "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl" - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be configured in this periph mode. All the periph and bank need to be describe. @@ -120,6 +121,7 @@ Some requirements for using atmel,at91rm9200-pinctrl binding: For each bank the required properties are: - compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio" or "microchip,sam9x60-gpio" + or "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio" - reg: physical base address and length of the controller's registers - interrupts: interrupt outputs from the controller - interrupt-controller: marks the device node as an interrupt controller diff --git a/Bindings/pinctrl/awinic,aw9523-pinctrl.yaml b/Bindings/pinctrl/awinic,aw9523-pinctrl.yaml new file mode 100644 index 00000000000..98c310a3c63 --- /dev/null +++ b/Bindings/pinctrl/awinic,aw9523-pinctrl.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/awinic,aw9523-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Awinic AW9523/AW9523B I2C GPIO Expander + +maintainers: + - AngeloGioacchino Del Regno + +description: | + The Awinic AW9523/AW9523B I2C GPIO Expander featuring 16 multi-function + I/O, 256 steps PWM mode and interrupt support. + +properties: + compatible: + const: awinic,aw9523-pinctrl + + reg: + maxItems: 1 + + '#gpio-cells': + description: | + Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-controller: true + + gpio-ranges: + maxItems: 1 + + interrupt-controller: true + + interrupts: + maxItems: 1 + description: Specifies the INTN pin IRQ. + + '#interrupt-cells': + description: + Specifies the PIN numbers and Flags, as defined in defined in + include/dt-bindings/interrupt-controller/irq.h + const: 2 + + reset-gpios: + maxItems: 1 + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + List of gpio pins affected by the properties specified in + this subnode. + items: + pattern: "^gpio([0-9]|1[0-5])$" + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the + specified pins. + + enum: [ gpio, pwm ] + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-open-drain: true + drive-push-pull: true + input-enable: true + input-disable: true + output-high: true + output-low: true + + required: + - pins + - function + + additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + # Example configuration to drive pins for a keyboard matrix + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + aw9523: gpio-expander@58 { + compatible = "awinic,aw9523-pinctrl"; + reg = <0x58>; + interrupt-parent = <&tlmm>; + interrupts = <50 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 16>; + interrupt-controller; + #interrupt-cells = <2>; + reset-gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>; + + keyboard-matrix-col-pins { + pins = "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15"; + function = "gpio"; + input-disable; + output-low; + }; + + keyboard-matrix-row-pins { + pins = "gpio0", "gpio1", "gpio2", "gpio3", + "gpio4", "gpio5", "gpio6", "gpio7"; + function = "gpio"; + bias-pull-up; + drive-open-drain; + input-enable; + }; + }; + }; diff --git a/Bindings/pinctrl/cirrus,madera.yaml b/Bindings/pinctrl/cirrus,madera.yaml index bb61a30321a..482acda88e7 100644 --- a/Bindings/pinctrl/cirrus,madera.yaml +++ b/Bindings/pinctrl/cirrus,madera.yaml @@ -93,7 +93,8 @@ properties: input-schmitt-disable: true - input-debounce: true + input-debounce: + maxItems: 1 output-low: true diff --git a/Bindings/pinctrl/cypress,cy8c95x0.yaml b/Bindings/pinctrl/cypress,cy8c95x0.yaml index 7f30ec2f1e5..700ac86c26b 100644 --- a/Bindings/pinctrl/cypress,cy8c95x0.yaml +++ b/Bindings/pinctrl/cypress,cy8c95x0.yaml @@ -45,7 +45,8 @@ properties: maxItems: 1 gpio-reserved-ranges: - maxItems: 1 + minItems: 1 + maxItems: 60 vdd-supply: description: @@ -85,6 +86,8 @@ patternProperties: bias-disable: true + input-enable: true + output-high: true output-low: true @@ -133,6 +136,23 @@ examples: interrupts = ; interrupt-controller; vdd-supply = <&p3v3>; - gpio-reserved-ranges = <5 1>; + gpio-reserved-ranges = <1 2>, <6 1>, <10 1>, <15 1>; + + pinctrl-0 = <&U62160_pins>, <&U62160_ipins>; + pinctrl-names = "default"; + + U62160_pins: cfg-pins { + pins = "gp03", "gp16", "gp20", "gp50", "gp51"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + + U62160_ipins: icfg-pins { + pins = "gp04", "gp17", "gp21", "gp52", "gp53"; + function = "gpio"; + input-enable; + bias-pull-up; + }; }; }; diff --git a/Bindings/pinctrl/fsl,imx6ul-pinctrl.txt b/Bindings/pinctrl/fsl,imx6ul-pinctrl.txt deleted file mode 100644 index 7ca4f6118d9..00000000000 --- a/Bindings/pinctrl/fsl,imx6ul-pinctrl.txt +++ /dev/null @@ -1,37 +0,0 @@ -* Freescale i.MX6 UltraLite IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx6ul-iomuxc" for main IOMUX controller or - "fsl,imx6ull-iomuxc-snvs" for i.MX 6ULL's SNVS IOMUX controller. -- fsl,pins: each entry consists of 6 integers and represents the mux and config - setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in - imx6ul-pinfunc.h under device tree source folder. The last integer CONFIG is - the pad setting value like pull-up on this pin. Please refer to i.MX6 UltraLite - Reference Manual for detailed CONFIG settings. - -CONFIG bits definition: -PAD_CTL_HYS (1 << 16) -PAD_CTL_PUS_100K_DOWN (0 << 14) -PAD_CTL_PUS_47K_UP (1 << 14) -PAD_CTL_PUS_100K_UP (2 << 14) -PAD_CTL_PUS_22K_UP (3 << 14) -PAD_CTL_PUE (1 << 13) -PAD_CTL_PKE (1 << 12) -PAD_CTL_ODE (1 << 11) -PAD_CTL_SPEED_LOW (0 << 6) -PAD_CTL_SPEED_MED (1 << 6) -PAD_CTL_SPEED_HIGH (3 << 6) -PAD_CTL_DSE_DISABLE (0 << 3) -PAD_CTL_DSE_260ohm (1 << 3) -PAD_CTL_DSE_130ohm (2 << 3) -PAD_CTL_DSE_87ohm (3 << 3) -PAD_CTL_DSE_65ohm (4 << 3) -PAD_CTL_DSE_52ohm (5 << 3) -PAD_CTL_DSE_43ohm (6 << 3) -PAD_CTL_DSE_37ohm (7 << 3) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) diff --git a/Bindings/pinctrl/fsl,imx6ul-pinctrl.yaml b/Bindings/pinctrl/fsl,imx6ul-pinctrl.yaml new file mode 100644 index 00000000000..906b264a9e3 --- /dev/null +++ b/Bindings/pinctrl/fsl,imx6ul-pinctrl.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imx6ul-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale IMX6UL IOMUX Controller + +maintainers: + - Dong Aisheng + +description: + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory + for common binding part and usage. + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + enum: + - fsl,imx6ul-iomuxc + - fsl,imx6ull-iomuxc-snvs + + reg: + maxItems: 1 + +# Client device subnode's properties +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can + be found in . The last integer + CONFIG is the pad setting value like pull-up on this pin. Please + refer to i.MX6UL Reference Manual for detailed CONFIG settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "mux_reg" indicates the offset of mux register. + - description: | + "conf_reg" indicates the offset of pad configuration register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_val" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied: + PAD_CTL_HYS (1 << 16) + PAD_CTL_PUS_100K_DOWN (0 << 14) + PAD_CTL_PUS_47K_UP (1 << 14) + PAD_CTL_PUS_100K_UP (2 << 14) + PAD_CTL_PUS_22K_UP (3 << 14) + PAD_CTL_PUE (1 << 13) + PAD_CTL_PKE (1 << 12) + PAD_CTL_ODE (1 << 11) + PAD_CTL_SPEED_LOW (0 << 6) + PAD_CTL_SPEED_MED (1 << 6) + PAD_CTL_SPEED_HIGH (3 << 6) + PAD_CTL_DSE_DISABLE (0 << 3) + PAD_CTL_DSE_260ohm (1 << 3) + PAD_CTL_DSE_130ohm (2 << 3) + PAD_CTL_DSE_87ohm (3 << 3) + PAD_CTL_DSE_65ohm (4 << 3) + PAD_CTL_DSE_52ohm (5 << 3) + PAD_CTL_DSE_43ohm (6 << 3) + PAD_CTL_DSE_37ohm (7 << 3) + PAD_CTL_SRE_FAST (1 << 0) + PAD_CTL_SRE_SLOW (0 << 0) + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + iomuxc: pinctrl@20e0000 { + compatible = "fsl,imx6ul-iomuxc"; + reg = <0x020e0000 0x4000>; + + mux_uart: uartgrp { + fsl,pins = < + 0x0084 0x0310 0x0000 0 0 0x1b0b1 + 0x0088 0x0314 0x0624 0 3 0x1b0b1 + >; + }; + }; + - | + iomuxc_snvs: pinctrl@2290000 { + compatible = "fsl,imx6ull-iomuxc-snvs"; + reg = <0x02290000 0x4000>; + + pinctrl_snvs_usbc_det: snvsusbcdetgrp { + fsl,pins = < + 0x0010 0x0054 0x0000 0x5 0x0 0x130b0 + >; + }; + }; diff --git a/Bindings/pinctrl/mobileye,eyeq5-pinctrl.yaml b/Bindings/pinctrl/mobileye,eyeq5-pinctrl.yaml new file mode 100644 index 00000000000..5f00604bf48 --- /dev/null +++ b/Bindings/pinctrl/mobileye,eyeq5-pinctrl.yaml @@ -0,0 +1,242 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mobileye,eyeq5-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye EyeQ5 pin controller + +description: > + The EyeQ5 pin controller handles the two pin banks of the system. It belongs + to a system-controller block called OLB. + + Pin control is about bias (pull-down, pull-up), drive strength and muxing. Pin + muxing supports two functions for each pin: first is GPIO, second is + pin-dependent. + + Pins and groups are bijective. + +maintainers: + - Grégory Clement + - Théo Lebrun + - Vladimir Kondratiev + +$ref: pinctrl.yaml# + +properties: + compatible: + enum: + - mobileye,eyeq5-pinctrl + + reg: + maxItems: 1 + +patternProperties: + "-pins?$": + type: object + description: Pin muxing configuration. + $ref: pinmux-node.yaml# + additionalProperties: false + properties: + pins: true + function: + enum: [gpio, + # Bank A + timer0, timer1, timer2, timer5, uart0, uart1, can0, can1, spi0, + spi1, refclk0, + # Bank B + timer3, timer4, timer6, uart2, can2, spi2, spi3, mclk0] + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + required: + - pins + - function + allOf: + - if: + properties: + function: + const: gpio + then: + properties: + pins: + items: # PA0 - PA28, PB0 - PB22 + pattern: '^(P(A|B)1?[0-9]|PA2[0-8]|PB2[0-2])$' + - if: + properties: + function: + const: timer0 + then: + properties: + pins: + items: + enum: [PA0, PA1] + - if: + properties: + function: + const: timer1 + then: + properties: + pins: + items: + enum: [PA2, PA3] + - if: + properties: + function: + const: timer2 + then: + properties: + pins: + items: + enum: [PA4, PA5] + - if: + properties: + function: + const: timer5 + then: + properties: + pins: + items: + enum: [PA6, PA7, PA8, PA9] + - if: + properties: + function: + const: uart0 + then: + properties: + pins: + items: + enum: [PA10, PA11] + - if: + properties: + function: + const: uart1 + then: + properties: + pins: + items: + enum: [PA12, PA13] + - if: + properties: + function: + const: can0 + then: + properties: + pins: + items: + enum: [PA14, PA15] + - if: + properties: + function: + const: can1 + then: + properties: + pins: + items: + enum: [PA16, PA17] + - if: + properties: + function: + const: spi0 + then: + properties: + pins: + items: + enum: [PA18, PA19, PA20, PA21, PA22] + - if: + properties: + function: + const: spi1 + then: + properties: + pins: + items: + enum: [PA23, PA24, PA25, PA26, PA27] + - if: + properties: + function: + const: refclk0 + then: + properties: + pins: + items: + enum: [PA28] + - if: + properties: + function: + const: timer3 + then: + properties: + pins: + items: + enum: [PB0, PB1] + - if: + properties: + function: + const: timer4 + then: + properties: + pins: + items: + enum: [PB2, PB3] + - if: + properties: + function: + const: timer6 + then: + properties: + pins: + items: + enum: [PB4, PB5, PB6, PB7] + - if: + properties: + function: + const: uart2 + then: + properties: + pins: + items: + enum: [PB8, PB9] + - if: + properties: + function: + const: can2 + then: + properties: + pins: + items: + enum: [PB10, PB11] + - if: + properties: + function: + const: spi2 + then: + properties: + pins: + items: + enum: [PB12, PB13, PB14, PB15, PB16] + - if: + properties: + function: + const: spi3 + then: + properties: + pins: + items: + enum: [PB17, PB18, PB19, PB20, PB21] + - if: + properties: + function: + const: mclk0 + then: + properties: + pins: + items: + enum: [PB22] + +required: + - compatible + - reg + +additionalProperties: false diff --git a/Bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml b/Bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml index 3e847289880..b55d9c31665 100644 --- a/Bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml +++ b/Bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml @@ -152,7 +152,6 @@ patternProperties: description: Debouncing periods in microseconds, one period per interrupt bank found in the controller - $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 1 maxItems: 4 @@ -160,7 +159,6 @@ patternProperties: description: | 0: Low rate 1: High rate - $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1] drive-strength: diff --git a/Bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml b/Bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml index 7b7f840ffc4..08442c880f0 100644 --- a/Bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml +++ b/Bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml @@ -103,7 +103,8 @@ patternProperties: items: pattern: "^gpio1?[0-9]{1,2}$" - input-debounce: true + input-debounce: + maxItems: 1 additionalProperties: false diff --git a/Bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml b/Bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml index f3deda9f712..db8224dfba2 100644 --- a/Bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml +++ b/Bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml @@ -10,18 +10,21 @@ maintainers: - Thierry Reding - Jon Hunter -$ref: nvidia,tegra234-pinmux-common.yaml - properties: compatible: const: nvidia,tegra234-pinmux-aon + reg: + maxItems: 1 + patternProperties: "^pinmux(-[a-z0-9-]+)?$": type: object # pin groups additionalProperties: + $ref: nvidia,tegra234-pinmux-common.yaml + properties: nvidia,pins: items: diff --git a/Bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml b/Bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml index 4f9de78085e..8cf9e4c915f 100644 --- a/Bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml +++ b/Bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml @@ -10,57 +10,43 @@ maintainers: - Thierry Reding - Jon Hunter +$ref: nvidia,tegra-pinmux-common.yaml + properties: - reg: - items: - - description: pinmux registers + nvidia,function: + enum: [ gp, uartc, i2c8, spi2, i2c2, can1, can0, rsvd0, eth0, eth2, + eth1, dp, eth3, i2c4, i2c7, i2c9, eqos, pe2, pe1, pe0, pe3, + pe4, pe5, pe6, pe7, pe8, pe9, pe10, qspi0, qspi1, qpsi, + sdmmc1, sce, soc, gpio, hdmi, ufs0, spi3, spi1, uartb, uarte, + usb, extperiph2, extperiph1, i2c3, vi0, i2c5, uarta, uartd, + i2c1, i2s4, i2s6, aud, spi5, touch, uartj, rsvd1, wdt, tsc, + dmic3, led, vi0_alt, i2s5, nv, extperiph3, extperiph4, spi4, + ccla, i2s1, i2s2, i2s3, i2s8, rsvd2, dmic5, dca, displayb, + displaya, vi1, dcb, dmic1, dmic4, i2s7, dmic2, dspk0, rsvd3, + tsc_alt, istctrl, vi1_alt, dspk1, igpu ] -patternProperties: - "^pinmux(-[a-z0-9-]+)?$": - type: object - - # pin groups - additionalProperties: - $ref: nvidia,tegra-pinmux-common.yaml - # We would typically use unevaluatedProperties here but that has the - # downside that all the properties in the common bindings become valid - # for all chip generations. In this case, however, we want the per-SoC - # bindings to be able to override which of the common properties are - # allowed, since not all pinmux generations support the same sets of - # properties. This way, the common bindings define the format of the - # properties but the per-SoC bindings define which of them apply to a - # given chip. - additionalProperties: false - properties: - nvidia,function: - enum: [ gp, uartc, i2c8, spi2, i2c2, can1, can0, rsvd0, eth0, eth2, - eth1, dp, eth3, i2c4, i2c7, i2c9, eqos, pe2, pe1, pe0, pe3, - pe4, pe5, pe6, pe7, pe8, pe9, pe10, qspi0, qspi1, qpsi, - sdmmc1, sce, soc, gpio, hdmi, ufs0, spi3, spi1, uartb, uarte, - usb, extperiph2, extperiph1, i2c3, vi0, i2c5, uarta, uartd, - i2c1, i2s4, i2s6, aud, spi5, touch, uartj, rsvd1, wdt, tsc, - dmic3, led, vi0_alt, i2s5, nv, extperiph3, extperiph4, spi4, - ccla, i2s1, i2s2, i2s3, i2s8, rsvd2, dmic5, dca, displayb, - displaya, vi1, dcb, dmic1, dmic4, i2s7, dmic2, dspk0, rsvd3, - tsc_alt, istctrl, vi1_alt, dspk1, igpu ] - - # out of the common properties, only these are allowed for Tegra234 - nvidia,pins: true - nvidia,pull: true - nvidia,tristate: true - nvidia,schmitt: true - nvidia,enable-input: true - nvidia,open-drain: true - nvidia,lock: true - nvidia,drive-type: true - nvidia,io-hv: true - - required: - - nvidia,pins + # out of the common properties, only these are allowed for Tegra234 + nvidia,pins: true + nvidia,pull: true + nvidia,tristate: true + nvidia,schmitt: true + nvidia,enable-input: true + nvidia,open-drain: true + nvidia,lock: true + nvidia,drive-type: true + nvidia,io-hv: true required: - - compatible - - reg + - nvidia,pins + +# We would typically use unevaluatedProperties here but that has the +# downside that all the properties in the common bindings become valid +# for all chip generations. In this case, however, we want the per-SoC +# bindings to be able to override which of the common properties are +# allowed, since not all pinmux generations support the same sets of +# properties. This way, the common bindings define the format of the +# properties but the per-SoC bindings define which of them apply to a +# given chip. +additionalProperties: false -additionalProperties: true ... diff --git a/Bindings/pinctrl/nvidia,tegra234-pinmux.yaml b/Bindings/pinctrl/nvidia,tegra234-pinmux.yaml index 17b865ecfcd..f5a3a881dec 100644 --- a/Bindings/pinctrl/nvidia,tegra234-pinmux.yaml +++ b/Bindings/pinctrl/nvidia,tegra234-pinmux.yaml @@ -10,18 +10,21 @@ maintainers: - Thierry Reding - Jon Hunter -$ref: nvidia,tegra234-pinmux-common.yaml - properties: compatible: const: nvidia,tegra234-pinmux + reg: + maxItems: 1 + patternProperties: "^pinmux(-[a-z0-9-]+)?$": type: object # pin groups additionalProperties: + $ref: nvidia,tegra234-pinmux-common.yaml + properties: nvidia,pins: items: diff --git a/Bindings/pinctrl/pincfg-node.yaml b/Bindings/pinctrl/pincfg-node.yaml index be81ed22a03..d0af21a564b 100644 --- a/Bindings/pinctrl/pincfg-node.yaml +++ b/Bindings/pinctrl/pincfg-node.yaml @@ -97,7 +97,7 @@ properties: description: disable schmitt-trigger mode input-debounce: - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32-array description: Takes the debounce time in usec as argument or 0 to disable debouncing diff --git a/Bindings/pinctrl/qcom,sm4450-tlmm.yaml b/Bindings/pinctrl/qcom,sm4450-tlmm.yaml index bb08ca5a150..bb675c8ec22 100644 --- a/Bindings/pinctrl/qcom,sm4450-tlmm.yaml +++ b/Bindings/pinctrl/qcom,sm4450-tlmm.yaml @@ -17,7 +17,7 @@ allOf: properties: compatible: - const: qcom,sm4450-pinctrl + const: qcom,sm4450-tlmm reg: maxItems: 1 diff --git a/Bindings/pinctrl/renesas,pfc.yaml b/Bindings/pinctrl/renesas,pfc.yaml index 181cd1676c0..5d84364d135 100644 --- a/Bindings/pinctrl/renesas,pfc.yaml +++ b/Bindings/pinctrl/renesas,pfc.yaml @@ -46,6 +46,7 @@ properties: - renesas,pfc-r8a779a0 # R-Car V3U - renesas,pfc-r8a779f0 # R-Car S4-8 - renesas,pfc-r8a779g0 # R-Car V4H + - renesas,pfc-r8a779h0 # R-Car V4M - renesas,pfc-sh73a0 # SH-Mobile AG5 reg: diff --git a/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index d476de82e5c..4d5a957fa23 100644 --- a/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -120,7 +120,9 @@ additionalProperties: slew-rate: true gpio-hog: true gpios: true + input: true input-enable: true + output-enable: true output-high: true output-low: true line-name: true diff --git a/Bindings/pinctrl/xlnx,zynq-pinctrl.yaml b/Bindings/pinctrl/xlnx,pinctrl-zynq.yaml similarity index 98% rename from Bindings/pinctrl/xlnx,zynq-pinctrl.yaml rename to Bindings/pinctrl/xlnx,pinctrl-zynq.yaml index d2676f92ef5..de6c10ba36c 100644 --- a/Bindings/pinctrl/xlnx,zynq-pinctrl.yaml +++ b/Bindings/pinctrl/xlnx,pinctrl-zynq.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/xlnx,zynq-pinctrl.yaml# +$id: http://devicetree.org/schemas/pinctrl/xlnx,pinctrl-zynq.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx Zynq Pinctrl @@ -28,7 +28,7 @@ description: | properties: compatible: - const: xlnx,zynq-pinctrl + const: xlnx,pinctrl-zynq reg: description: Specifies the base address and size of the SLCR space. @@ -181,7 +181,7 @@ examples: - | #include pinctrl0: pinctrl@700 { - compatible = "xlnx,zynq-pinctrl"; + compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; syscon = <&slcr>; diff --git a/Bindings/power/qcom,rpmpd.yaml b/Bindings/power/qcom,rpmpd.yaml index 2ff246cf8b8..929b7ef9c1b 100644 --- a/Bindings/power/qcom,rpmpd.yaml +++ b/Bindings/power/qcom,rpmpd.yaml @@ -24,6 +24,8 @@ properties: - qcom,msm8917-rpmpd - qcom,msm8939-rpmpd - qcom,msm8953-rpmpd + - qcom,msm8974-rpmpd + - qcom,msm8974pro-pma8084-rpmpd - qcom,msm8976-rpmpd - qcom,msm8994-rpmpd - qcom,msm8996-rpmpd diff --git a/Bindings/power/renesas,rcar-sysc.yaml b/Bindings/power/renesas,rcar-sysc.yaml index 0720b54881c..e76fb273490 100644 --- a/Bindings/power/renesas,rcar-sysc.yaml +++ b/Bindings/power/renesas,rcar-sysc.yaml @@ -45,6 +45,7 @@ properties: - renesas,r8a779a0-sysc # R-Car V3U - renesas,r8a779f0-sysc # R-Car S4-8 - renesas,r8a779g0-sysc # R-Car V4H + - renesas,r8a779h0-sysc # R-Car V4M reg: maxItems: 1 diff --git a/Bindings/power/wakeup-source.txt b/Bindings/power/wakeup-source.txt index 75bc20b9568..a6c8978964a 100644 --- a/Bindings/power/wakeup-source.txt +++ b/Bindings/power/wakeup-source.txt @@ -27,7 +27,7 @@ List of legacy properties and respective binding document Documentation/devicetree/bindings/mfd/tc3589x.txt Documentation/devicetree/bindings/input/touchscreen/ads7846.txt 4. "linux,keypad-wakeup" Documentation/devicetree/bindings/input/qcom,pm8xxx-keypad.txt -5. "linux,input-wakeup" Documentation/devicetree/bindings/input/samsung-keypad.txt +5. "linux,input-wakeup" Documentation/devicetree/bindings/input/samsung,s3c6410-keypad.yaml 6. "nvidia,wakeup-source" Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt Examples diff --git a/Bindings/pwm/atmel,hlcdc-pwm.yaml b/Bindings/pwm/atmel,hlcdc-pwm.yaml new file mode 100644 index 00000000000..0e92868a2b6 --- /dev/null +++ b/Bindings/pwm/atmel,hlcdc-pwm.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/atmel,hlcdc-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel's HLCDC's PWM controller + +maintainers: + - Nicolas Ferre + - Alexandre Belloni + - Claudiu Beznea + +description: + The LCDC integrates a Pulse Width Modulation (PWM) Controller. This block + generates the LCD contrast control signal (LCD_PWM) that controls the + display's contrast by software. LCDC_PWM is an 8-bit PWM signal that can be + converted to an analog voltage with a simple passive filter. LCD display + panels have different backlight specifications in terms of minimum/maximum + values for PWM frequency. If the LCDC PWM frequency range does not match the + LCD display panel, it is possible to use the standalone PWM Controller to + drive the backlight. + +properties: + compatible: + const: atmel,hlcdc-pwm + + "#pwm-cells": + const: 3 + +required: + - compatible + - "#pwm-cells" + +additionalProperties: false diff --git a/Bindings/pwm/atmel-hlcdc-pwm.txt b/Bindings/pwm/atmel-hlcdc-pwm.txt deleted file mode 100644 index afa501bf7f9..00000000000 --- a/Bindings/pwm/atmel-hlcdc-pwm.txt +++ /dev/null @@ -1,29 +0,0 @@ -Device-Tree bindings for Atmel's HLCDC (High-end LCD Controller) PWM driver - -The Atmel HLCDC PWM is subdevice of the HLCDC MFD device. -See ../mfd/atmel-hlcdc.txt for more details. - -Required properties: - - compatible: value should be one of the following: - "atmel,hlcdc-pwm" - - pinctr-names: the pin control state names. Should contain "default". - - pinctrl-0: should contain the pinctrl states described by pinctrl - default. - - #pwm-cells: should be set to 3. This PWM chip use the default 3 cells - bindings defined in pwm.yaml in this directory. - -Example: - - hlcdc: hlcdc@f0030000 { - compatible = "atmel,sama5d3-hlcdc"; - reg = <0xf0030000 0x2000>; - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; - clock-names = "periph_clk","sys_clk", "slow_clk"; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwm>; - #pwm-cells = <3>; - }; - }; diff --git a/Bindings/pwm/marvell,pxa-pwm.yaml b/Bindings/pwm/marvell,pxa-pwm.yaml new file mode 100644 index 00000000000..ba6325575ea --- /dev/null +++ b/Bindings/pwm/marvell,pxa-pwm.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/marvell,pxa-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell PXA PWM + +maintainers: + - Duje Mihanović + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + enum: + - marvell,pxa250-pwm + - marvell,pxa270-pwm + - marvell,pxa168-pwm + - marvell,pxa910-pwm + + reg: + # Length should be 0x10 + maxItems: 1 + + "#pwm-cells": + # Used for specifying the period length in nanoseconds + const: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - "#pwm-cells" + - clocks + +additionalProperties: false + +examples: + - | + #include + + pwm0: pwm@40b00000 { + compatible = "marvell,pxa250-pwm"; + reg = <0x40b00000 0x10>; + #pwm-cells = <1>; + clocks = <&clks CLK_PWM0>; + }; diff --git a/Bindings/pwm/mediatek,mt2712-pwm.yaml b/Bindings/pwm/mediatek,mt2712-pwm.yaml index 0fbe8a6469e..a5c30880161 100644 --- a/Bindings/pwm/mediatek,mt2712-pwm.yaml +++ b/Bindings/pwm/mediatek,mt2712-pwm.yaml @@ -24,6 +24,7 @@ properties: - mediatek,mt7629-pwm - mediatek,mt7981-pwm - mediatek,mt7986-pwm + - mediatek,mt7988-pwm - mediatek,mt8183-pwm - mediatek,mt8365-pwm - mediatek,mt8516-pwm diff --git a/Bindings/pwm/mediatek,pwm-disp.yaml b/Bindings/pwm/mediatek,pwm-disp.yaml index afcdeed4e88..bc813fe74fa 100644 --- a/Bindings/pwm/mediatek,pwm-disp.yaml +++ b/Bindings/pwm/mediatek,pwm-disp.yaml @@ -52,6 +52,9 @@ properties: - const: main - const: mm + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Bindings/pwm/opencores,pwm.yaml b/Bindings/pwm/opencores,pwm.yaml new file mode 100644 index 00000000000..52a59d245cd --- /dev/null +++ b/Bindings/pwm/opencores,pwm.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/opencores,pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OpenCores PWM controller + +maintainers: + - William Qiu + +description: + The OpenCores PTC ip core contains a PWM controller. When operating in PWM + mode, the PTC core generates binary signal with user-programmable low and + high periods. All PTC counters and registers are 32-bit. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + items: + - enum: + - starfive,jh7100-pwm + - starfive,jh7110-pwm + - starfive,jh8100-pwm + - const: opencores,pwm-v1 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + pwm@12490000 { + compatible = "starfive,jh7110-pwm", "opencores,pwm-v1"; + reg = <0x12490000 0x10000>; + clocks = <&clkgen 181>; + resets = <&rstgen 109>; + #pwm-cells = <3>; + }; diff --git a/Bindings/pwm/pwm-amlogic.yaml b/Bindings/pwm/pwm-amlogic.yaml index 527864a4d85..1d71d4f8f32 100644 --- a/Bindings/pwm/pwm-amlogic.yaml +++ b/Bindings/pwm/pwm-amlogic.yaml @@ -9,9 +9,6 @@ title: Amlogic PWM maintainers: - Heiner Kallweit -allOf: - - $ref: pwm.yaml# - properties: compatible: oneOf: @@ -24,31 +21,40 @@ properties: - amlogic,meson-g12a-ee-pwm - amlogic,meson-g12a-ao-pwm-ab - amlogic,meson-g12a-ao-pwm-cd - - amlogic,meson-s4-pwm + deprecated: true - items: - const: amlogic,meson-gx-pwm - const: amlogic,meson-gxbb-pwm + deprecated: true - items: - const: amlogic,meson-gx-ao-pwm - const: amlogic,meson-gxbb-ao-pwm + deprecated: true - items: - const: amlogic,meson8-pwm - const: amlogic,meson8b-pwm + deprecated: true + - enum: + - amlogic,meson8-pwm-v2 + - amlogic,meson-s4-pwm + - items: + - enum: + - amlogic,meson8b-pwm-v2 + - amlogic,meson-gxbb-pwm-v2 + - amlogic,meson-axg-pwm-v2 + - amlogic,meson-g12-pwm-v2 + - const: amlogic,meson8-pwm-v2 reg: maxItems: 1 clocks: minItems: 1 - maxItems: 2 + maxItems: 4 clock-names: - oneOf: - - items: - - enum: [clkin0, clkin1] - - items: - - const: clkin0 - - const: clkin1 + minItems: 1 + maxItems: 2 "#pwm-cells": const: 3 @@ -57,6 +63,79 @@ required: - compatible - reg +allOf: + - $ref: pwm.yaml# + + - if: + properties: + compatible: + contains: + enum: + - amlogic,meson8-pwm + - amlogic,meson8b-pwm + - amlogic,meson-gxbb-pwm + - amlogic,meson-gxbb-ao-pwm + - amlogic,meson-axg-ee-pwm + - amlogic,meson-axg-ao-pwm + - amlogic,meson-g12a-ee-pwm + - amlogic,meson-g12a-ao-pwm-ab + - amlogic,meson-g12a-ao-pwm-cd + then: + # Obsolete historic bindings tied to the driver implementation + # The clocks provided here are meant to be matched with the input + # known (hard-coded) in the driver and used to select pwm clock + # source. Currently, the linux driver ignores this. + # This is kept to maintain ABI backward compatibility. + properties: + clocks: + maxItems: 2 + clock-names: + oneOf: + - items: + - enum: [clkin0, clkin1] + - items: + - const: clkin0 + - const: clkin1 + + # Newer binding where clock describe the actual clock inputs of the pwm + # block. These are necessary but some inputs may be grounded. + - if: + properties: + compatible: + contains: + enum: + - amlogic,meson8-pwm-v2 + then: + properties: + clocks: + minItems: 1 + items: + - description: input clock 0 of the pwm block + - description: input clock 1 of the pwm block + - description: input clock 2 of the pwm block + - description: input clock 3 of the pwm block + clock-names: false + required: + - clocks + + # Newer IP block take a single input per channel, instead of 4 inputs + # for both channels + - if: + properties: + compatible: + contains: + enum: + - amlogic,meson-s4-pwm + then: + properties: + clocks: + items: + - description: input clock of PWM channel A + - description: input clock of PWM channel B + clock-names: false + required: + - clocks + additionalProperties: false examples: @@ -68,3 +147,17 @@ examples: clock-names = "clkin0", "clkin1"; #pwm-cells = <3>; }; + - | + pwm@2000 { + compatible = "amlogic,meson8-pwm-v2"; + reg = <0x1000 0x10>; + clocks = <&xtal>, <0>, <&fdiv4>, <&fdiv5>; + #pwm-cells = <3>; + }; + - | + pwm@1000 { + compatible = "amlogic,meson-s4-pwm"; + reg = <0x1000 0x10>; + clocks = <&pwm_src_a>, <&pwm_src_b>; + #pwm-cells = <3>; + }; diff --git a/Bindings/pwm/pxa-pwm.txt b/Bindings/pwm/pxa-pwm.txt deleted file mode 100644 index 5ae9f1e3c33..00000000000 --- a/Bindings/pwm/pxa-pwm.txt +++ /dev/null @@ -1,30 +0,0 @@ -Marvell PWM controller - -Required properties: -- compatible: should be one or more of: - - "marvell,pxa250-pwm" - - "marvell,pxa270-pwm" - - "marvell,pxa168-pwm" - - "marvell,pxa910-pwm" -- reg: Physical base address and length of the registers used by the PWM channel - Note that one device instance must be created for each PWM that is used, so the - length covers only the register window for one PWM output, not that of the - entire PWM controller. Currently length is 0x10 for all supported devices. -- #pwm-cells: Should be 1. This cell is used to specify the period in - nanoseconds. - -Example PWM device node: - -pwm0: pwm@40b00000 { - compatible = "marvell,pxa250-pwm"; - reg = <0x40b00000 0x10>; - #pwm-cells = <1>; -}; - -Example PWM client node: - -backlight { - compatible = "pwm-backlight"; - pwms = <&pwm0 5000000>; - ... -} diff --git a/Bindings/regulator/gpio-regulator.yaml b/Bindings/regulator/gpio-regulator.yaml index f4c1f36e52e..a34e8575465 100644 --- a/Bindings/regulator/gpio-regulator.yaml +++ b/Bindings/regulator/gpio-regulator.yaml @@ -47,6 +47,7 @@ properties: 1: HIGH Default is LOW if nothing else is specified. $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 maxItems: 8 items: enum: [0, 1] @@ -57,7 +58,8 @@ properties: regulator and matching GPIO configurations to achieve them. If there are no states in the "states" array, use a fixed regulator instead. $ref: /schemas/types.yaml#/definitions/uint32-matrix - maxItems: 8 + minItems: 2 + maxItems: 256 items: items: - description: Voltage in microvolts diff --git a/Bindings/regulator/infineon,ir38060.yaml b/Bindings/regulator/infineon,ir38060.yaml new file mode 100644 index 00000000000..e6ffbc2a229 --- /dev/null +++ b/Bindings/regulator/infineon,ir38060.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/infineon,ir38060.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Infineon Buck Regulators with PMBUS interfaces + +maintainers: + - Not Me. + +allOf: + - $ref: regulator.yaml# + +properties: + compatible: + enum: + - infineon,ir38060 + - infineon,ir38064 + - infineon,ir38164 + - infineon,ir38263 + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + regulator@34 { + compatible = "infineon,ir38060"; + reg = <0x34>; + + regulator-min-microvolt = <437500>; + regulator-max-microvolt = <1387500>; + }; + }; diff --git a/Bindings/regulator/mcp16502-regulator.txt b/Bindings/regulator/mcp16502-regulator.txt deleted file mode 100644 index 451cc4e86b0..00000000000 --- a/Bindings/regulator/mcp16502-regulator.txt +++ /dev/null @@ -1,144 +0,0 @@ -MCP16502 PMIC - -Required properties: -- compatible: "microchip,mcp16502" -- reg: I2C slave address -- lpm-gpios: GPIO for LPM pin. Note that this GPIO *must* remain high during - suspend-to-ram, keeping the PMIC into HIBERNATE mode; this - property is optional; -- regulators: A node that houses a sub-node for each regulator within - the device. Each sub-node is identified using the node's - name. The content of each sub-node is defined by the - standard binding for regulators; see regulator.txt. - -Regulators of MCP16502 PMIC: -1) VDD_IO - Buck (1.2 - 3.7 V) -2) VDD_DDR - Buck (0.6 - 1.85 V) -3) VDD_CORE - Buck (0.6 - 1.85 V) -4) VDD_OTHER - BUCK (0.6 - 1.85 V) -5) LDO1 - LDO (1.2 - 3.7 V) -6) LDO2 - LDO (1.2 - 3.7 V) - -Regulator modes: -2 - FPWM: higher precision, higher consumption -4 - AutoPFM: lower precision, lower consumption - -Each regulator is defined using the standard binding for regulators. - -Example: - -mcp16502@5b { - compatible = "microchip,mcp16502"; - reg = <0x5b>; - status = "okay"; - lpm-gpios = <&pioBU 7 GPIO_ACTIVE_HIGH>; - - regulators { - VDD_IO { - regulator-name = "VDD_IO"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3700000>; - regulator-initial-mode = <2>; - regulator-allowed-modes = <2>, <4>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - regulator-mode = <4>; - }; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-mode = <4>; - }; - }; - - VDD_DDR { - regulator-name = "VDD_DDR"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1850000>; - regulator-initial-mode = <2>; - regulator-allowed-modes = <2>, <4>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - regulator-mode = <4>; - }; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = <4>; - }; - }; - - VDD_CORE { - regulator-name = "VDD_CORE"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1850000>; - regulator-initial-mode = <2>; - regulator-allowed-modes = <2>, <4>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - regulator-mode = <4>; - }; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-mode = <4>; - }; - }; - - VDD_OTHER { - regulator-name = "VDD_OTHER"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1850000>; - regulator-initial-mode = <2>; - regulator-allowed-modes = <2>, <4>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - regulator-mode = <4>; - }; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-mode = <4>; - }; - }; - - LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - }; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - LDO2 { - regulator-name = "LDO2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - }; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - }; -}; diff --git a/Bindings/regulator/microchip,mcp16502.yaml b/Bindings/regulator/microchip,mcp16502.yaml new file mode 100644 index 00000000000..1aca3646789 --- /dev/null +++ b/Bindings/regulator/microchip,mcp16502.yaml @@ -0,0 +1,180 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/microchip,mcp16502.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MCP16502 - High-Performance PMIC + +maintainers: + - Andrei Simion + +description: + The MCP16502 is an optimally integrated PMIC compatible + with Microchip's eMPUs(Embedded Microprocessor Units), + requiring Dynamic Voltage Scaling (DVS) with the use + of High-Performance mode (HPM). + +properties: + compatible: + const: microchip,mcp16502 + + lpm-gpios: + maxItems: 1 + description: GPIO for LPM pin. + Note that this GPIO must remain high during + suspend-to-ram, keeping the PMIC into HIBERNATE mode. + + reg: + maxItems: 1 + + regulators: + type: object + additionalProperties: false + description: List of regulators and its properties. + + patternProperties: + "^(VDD_(IO|CORE|DDR|OTHER)|LDO[1-2])$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + properties: + regulator-initial-mode: + enum: [2, 4] + default: 2 + description: Initial operating mode + + regulator-allowed-modes: + items: + enum: [2, 4] + description: Supported modes + 2 - FPWM higher precision, higher consumption + 4 - AutoPFM lower precision, lower consumption + +required: + - compatible + - reg + - regulators + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@5b { + compatible = "microchip,mcp16502"; + reg = <0x5b>; + + regulators { + VDD_IO { + regulator-name = "VDD_IO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + VDD_DDR { + regulator-name = "VDD_DDR"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + }; + + VDD_CORE { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + VDD_OTHER { + regulator-name = "VDD_OTHER"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1250000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + }; diff --git a/Bindings/regulator/qcom,usb-vbus-regulator.yaml b/Bindings/regulator/qcom,usb-vbus-regulator.yaml index 534f87e9871..33ae1f78680 100644 --- a/Bindings/regulator/qcom,usb-vbus-regulator.yaml +++ b/Bindings/regulator/qcom,usb-vbus-regulator.yaml @@ -19,8 +19,15 @@ allOf: properties: compatible: - enum: - - qcom,pm8150b-vbus-reg + oneOf: + - enum: + - qcom,pm8150b-vbus-reg + - items: + - enum: + - qcom,pm4125-vbus-reg + - qcom,pm6150-vbus-reg + - qcom,pmi632-vbus-reg + - const: qcom,pm8150b-vbus-reg reg: maxItems: 1 diff --git a/Bindings/regulator/ti,tps65132.yaml b/Bindings/regulator/ti,tps65132.yaml new file mode 100644 index 00000000000..6a6d1a3d6fa --- /dev/null +++ b/Bindings/regulator/ti,tps65132.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/ti,tps65132.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI TPS65132 Dual Output Power Regulators + +maintainers: + - devicetree@vger.kernel.org + +description: | + The TPS65132 is designed to supply positive/negative driven applications. + + Datasheet is available at: + https://www.ti.com/lit/gpn/tps65132 + +properties: + compatible: + enum: + - ti,tps65132 + + reg: + maxItems: 1 + +patternProperties: + "^out[pn]$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single regulator. + + properties: + enable-gpios: + maxItems: 1 + description: + GPIO specifier to enable the GPIO control (on/off) for regulator. + + active-discharge-gpios: + maxItems: 1 + description: + GPIO specifier to actively discharge the delay mechanism. + + ti,active-discharge-time-us: + description: Regulator active discharge time in microseconds. + + dependencies: + active-discharge-gpios: [ 'ti,active-discharge-time-us' ] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + regulator@3e { + compatible = "ti,tps65132"; + reg = <0x3e>; + + outp { + regulator-name = "outp"; + regulator-boot-on; + regulator-always-on; + enable-gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; + }; + + outn { + regulator-name = "outn"; + regulator-boot-on; + regulator-always-on; + regulator-active-discharge = <0>; + enable-gpios = <&gpio 40 GPIO_ACTIVE_HIGH>; + }; + }; + }; diff --git a/Bindings/regulator/tps65132-regulator.txt b/Bindings/regulator/tps65132-regulator.txt deleted file mode 100644 index 3a3505520c6..00000000000 --- a/Bindings/regulator/tps65132-regulator.txt +++ /dev/null @@ -1,46 +0,0 @@ -TPS65132 regulators - -Required properties: -- compatible: "ti,tps65132" -- reg: I2C slave address - -Optional Subnode: -Device supports two regulators OUTP and OUTN. A sub node within the - device node describe the properties of these regulators. The sub-node - names must be as follows: - -For regulator outp, the sub node name should be "outp". - -For regulator outn, the sub node name should be "outn". - --enable-gpios:(active high, output) Regulators are controlled by the input pins. - If it is connected to GPIO through host system then provide the - gpio number as per gpio.txt. --active-discharge-gpios: (active high, output) Some configurations use delay mechanisms - on the enable pin, to keep the regulator enabled for some time after - the enable signal goes low. This GPIO is used to actively discharge - the delay mechanism. Requires specification of ti,active-discharge-time-us --ti,active-discharge-time-us: how long the active discharge gpio should be - asserted for during active discharge, in microseconds. - -Each regulator is defined using the standard binding for regulators. - -Example: - - tps65132@3e { - compatible = "ti,tps65132"; - reg = <0x3e>; - - outp { - regulator-name = "outp"; - regulator-boot-on; - regulator-always-on; - enable-gpios = <&gpio 23 0>; - }; - - outn { - regulator-name = "outn"; - regulator-boot-on; - regulator-always-on; - regulator-active-discharge = <0>; - enable-gpios = <&gpio 40 0>; - }; - }; diff --git a/Bindings/remoteproc/mtk,scp.yaml b/Bindings/remoteproc/mtk,scp.yaml index 09102dda494..507f98f73d2 100644 --- a/Bindings/remoteproc/mtk,scp.yaml +++ b/Bindings/remoteproc/mtk,scp.yaml @@ -47,7 +47,7 @@ properties: maxItems: 1 firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: If present, name (or relative path) of the file within the firmware search path containing the firmware image used when @@ -115,7 +115,7 @@ patternProperties: maxItems: 1 firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: If present, name (or relative path) of the file within the firmware search path containing the firmware image used when diff --git a/Bindings/remoteproc/qcom,glink-rpm-edge.yaml b/Bindings/remoteproc/qcom,glink-rpm-edge.yaml index 884158bccd5..3766d4513b3 100644 --- a/Bindings/remoteproc/qcom,glink-rpm-edge.yaml +++ b/Bindings/remoteproc/qcom,glink-rpm-edge.yaml @@ -18,7 +18,6 @@ properties: const: qcom,glink-rpm label: - $ref: /schemas/types.yaml#/definitions/string description: Name of the edge, used for debugging and identification purposes. The node name will be used if this is not present. diff --git a/Bindings/remoteproc/qcom,qcs404-pas.yaml b/Bindings/remoteproc/qcom,qcs404-pas.yaml index eb868a7ff4c..ad45fd00ae3 100644 --- a/Bindings/remoteproc/qcom,qcs404-pas.yaml +++ b/Bindings/remoteproc/qcom,qcs404-pas.yaml @@ -46,7 +46,7 @@ properties: description: Reference to the reserved-memory for the Hexagon core firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: Firmware name for the Hexagon core required: diff --git a/Bindings/remoteproc/qcom,sc7180-pas.yaml b/Bindings/remoteproc/qcom,sc7180-pas.yaml index c054b84fdcd..66b455d0a8e 100644 --- a/Bindings/remoteproc/qcom,sc7180-pas.yaml +++ b/Bindings/remoteproc/qcom,sc7180-pas.yaml @@ -45,7 +45,7 @@ properties: smd-edge: false firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: Firmware name for the Hexagon core required: diff --git a/Bindings/remoteproc/qcom,sc7280-wpss-pil.yaml b/Bindings/remoteproc/qcom,sc7280-wpss-pil.yaml index b6bd3343858..9381c7022ff 100644 --- a/Bindings/remoteproc/qcom,sc7280-wpss-pil.yaml +++ b/Bindings/remoteproc/qcom,sc7280-wpss-pil.yaml @@ -80,7 +80,7 @@ properties: description: Reference to the reserved-memory for the Hexagon core firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: The name of the firmware which should be loaded for this remote processor. diff --git a/Bindings/remoteproc/qcom,sc8180x-pas.yaml b/Bindings/remoteproc/qcom,sc8180x-pas.yaml index 4744a37b2b5..45ee9fbe096 100644 --- a/Bindings/remoteproc/qcom,sc8180x-pas.yaml +++ b/Bindings/remoteproc/qcom,sc8180x-pas.yaml @@ -42,7 +42,7 @@ properties: description: Reference to the reserved-memory for the Hexagon core firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: Firmware name for the Hexagon core required: diff --git a/Bindings/remoteproc/qcom,sm6115-pas.yaml b/Bindings/remoteproc/qcom,sm6115-pas.yaml index 02828723591..758adb06c8d 100644 --- a/Bindings/remoteproc/qcom,sm6115-pas.yaml +++ b/Bindings/remoteproc/qcom,sm6115-pas.yaml @@ -47,7 +47,7 @@ properties: smd-edge: false firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: Firmware name for the Hexagon core required: diff --git a/Bindings/remoteproc/qcom,sm6350-pas.yaml b/Bindings/remoteproc/qcom,sm6350-pas.yaml index f7e40fb166d..c1a3cc308bd 100644 --- a/Bindings/remoteproc/qcom,sm6350-pas.yaml +++ b/Bindings/remoteproc/qcom,sm6350-pas.yaml @@ -42,7 +42,7 @@ properties: smd-edge: false firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: Firmware name for the Hexagon core required: diff --git a/Bindings/remoteproc/qcom,sm6375-pas.yaml b/Bindings/remoteproc/qcom,sm6375-pas.yaml index 3e4a03eb453..7286b2baa19 100644 --- a/Bindings/remoteproc/qcom,sm6375-pas.yaml +++ b/Bindings/remoteproc/qcom,sm6375-pas.yaml @@ -36,7 +36,7 @@ properties: description: Reference to the reserved-memory for the Hexagon core firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: Firmware name for the Hexagon core smd-edge: false diff --git a/Bindings/remoteproc/qcom,sm8150-pas.yaml b/Bindings/remoteproc/qcom,sm8150-pas.yaml index 238c6e5e67c..d67386c50fa 100644 --- a/Bindings/remoteproc/qcom,sm8150-pas.yaml +++ b/Bindings/remoteproc/qcom,sm8150-pas.yaml @@ -46,7 +46,7 @@ properties: smd-edge: false firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: Firmware name for the Hexagon core required: diff --git a/Bindings/remoteproc/qcom,sm8350-pas.yaml b/Bindings/remoteproc/qcom,sm8350-pas.yaml index 53cea8e53a3..4b9fb74fb9e 100644 --- a/Bindings/remoteproc/qcom,sm8350-pas.yaml +++ b/Bindings/remoteproc/qcom,sm8350-pas.yaml @@ -47,7 +47,7 @@ properties: description: Reference to the reserved-memory for the Hexagon core firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: Firmware name for the Hexagon core required: diff --git a/Bindings/remoteproc/qcom,sm8550-pas.yaml b/Bindings/remoteproc/qcom,sm8550-pas.yaml index 58120829fb0..73fda7565cd 100644 --- a/Bindings/remoteproc/qcom,sm8550-pas.yaml +++ b/Bindings/remoteproc/qcom,sm8550-pas.yaml @@ -19,6 +19,11 @@ properties: - qcom,sm8550-adsp-pas - qcom,sm8550-cdsp-pas - qcom,sm8550-mpss-pas + - qcom,sm8650-adsp-pas + - qcom,sm8650-cdsp-pas + - qcom,sm8650-mpss-pas + - qcom,x1e80100-adsp-pas + - qcom,x1e80100-cdsp-pas reg: maxItems: 1 @@ -49,6 +54,8 @@ properties: - description: Memory region for main Firmware authentication - description: Memory region for Devicetree Firmware authentication - description: DSM Memory region + - description: DSM Memory region 2 + - description: Memory region for Qlink Logging required: - compatible @@ -63,6 +70,9 @@ allOf: enum: - qcom,sm8550-adsp-pas - qcom,sm8550-cdsp-pas + - qcom,sm8650-adsp-pas + - qcom,x1e80100-adsp-pas + - qcom,x1e80100-cdsp-pas then: properties: interrupts: @@ -71,7 +81,26 @@ allOf: maxItems: 5 memory-region: maxItems: 2 - else: + - if: + properties: + compatible: + enum: + - qcom,sm8650-cdsp-pas + then: + properties: + interrupts: + maxItems: 5 + interrupt-names: + maxItems: 5 + memory-region: + minItems: 3 + maxItems: 3 + - if: + properties: + compatible: + enum: + - qcom,sm8550-mpss-pas + then: properties: interrupts: minItems: 6 @@ -79,12 +108,29 @@ allOf: minItems: 6 memory-region: minItems: 3 + maxItems: 3 + - if: + properties: + compatible: + enum: + - qcom,sm8650-mpss-pas + then: + properties: + interrupts: + minItems: 6 + interrupt-names: + minItems: 6 + memory-region: + minItems: 5 + maxItems: 5 - if: properties: compatible: enum: - qcom,sm8550-adsp-pas + - qcom,sm8650-adsp-pas + - qcom,x1e80100-adsp-pas then: properties: power-domains: @@ -101,6 +147,7 @@ allOf: compatible: enum: - qcom,sm8550-mpss-pas + - qcom,sm8650-mpss-pas then: properties: power-domains: @@ -116,6 +163,8 @@ allOf: compatible: enum: - qcom,sm8550-cdsp-pas + - qcom,sm8650-cdsp-pas + - qcom,x1e80100-cdsp-pas then: properties: power-domains: diff --git a/Bindings/remoteproc/qcom,wcnss-pil.yaml b/Bindings/remoteproc/qcom,wcnss-pil.yaml index 45eb42bd3c2..8e033b22d28 100644 --- a/Bindings/remoteproc/qcom,wcnss-pil.yaml +++ b/Bindings/remoteproc/qcom,wcnss-pil.yaml @@ -51,7 +51,7 @@ properties: - const: stop-ack firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: Relative firmware image path for the WCNSS core. Defaults to "wcnss.mdt". diff --git a/Bindings/remoteproc/ti,davinci-rproc.txt b/Bindings/remoteproc/ti,davinci-rproc.txt index 25f8658e216..48a49c516b6 100644 --- a/Bindings/remoteproc/ti,davinci-rproc.txt +++ b/Bindings/remoteproc/ti,davinci-rproc.txt @@ -1,9 +1,6 @@ TI Davinci DSP devices ======================= -Binding status: Unstable - Subject to changes for DT representation of clocks - and resets - The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that is used to offload some of the processor-intensive tasks or algorithms, for achieving various system level goals. diff --git a/Bindings/reset/mobileye,eyeq5-reset.yaml b/Bindings/reset/mobileye,eyeq5-reset.yaml new file mode 100644 index 00000000000..062b4518347 --- /dev/null +++ b/Bindings/reset/mobileye,eyeq5-reset.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/mobileye,eyeq5-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye EyeQ5 reset controller + +description: + The EyeQ5 reset driver handles three reset domains. Its registers live in a + shared region called OLB. + +maintainers: + - Grégory Clement + - Théo Lebrun + - Vladimir Kondratiev + +properties: + compatible: + const: mobileye,eyeq5-reset + + reg: + maxItems: 3 + + reg-names: + items: + - const: d0 + - const: d1 + - const: d2 + + "#reset-cells": + const: 2 + description: + The first cell is the domain (0 to 2 inclusive) and the second one is the + reset index inside that domain. + +required: + - compatible + - reg + - reg-names + - "#reset-cells" + +additionalProperties: false diff --git a/Bindings/reset/renesas,rst.yaml b/Bindings/reset/renesas,rst.yaml index e7e48724775..58b4a45d338 100644 --- a/Bindings/reset/renesas,rst.yaml +++ b/Bindings/reset/renesas,rst.yaml @@ -50,6 +50,7 @@ properties: - renesas,r8a779a0-rst # R-Car V3U - renesas,r8a779f0-rst # R-Car S4-8 - renesas,r8a779g0-rst # R-Car V4H + - renesas,r8a779h0-rst # R-Car V4M reg: maxItems: 1 diff --git a/Bindings/reset/sophgo,sg2042-reset.yaml b/Bindings/reset/sophgo,sg2042-reset.yaml new file mode 100644 index 00000000000..76e1931f090 --- /dev/null +++ b/Bindings/reset/sophgo,sg2042-reset.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/sophgo,sg2042-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 SoC Reset Controller + +maintainers: + - Chen Wang + +properties: + compatible: + const: sophgo,sg2042-reset + + reg: + maxItems: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - "#reset-cells" + +additionalProperties: false + +examples: + - | + rstgen: reset-controller@c00 { + compatible = "sophgo,sg2042-reset"; + reg = <0xc00 0xc>; + #reset-cells = <1>; + }; diff --git a/Bindings/riscv/cpus.yaml b/Bindings/riscv/cpus.yaml index 9d8670c00e3..d87dd50f1a4 100644 --- a/Bindings/riscv/cpus.yaml +++ b/Bindings/riscv/cpus.yaml @@ -75,6 +75,10 @@ properties: - riscv,sv57 - riscv,none + reg: + description: + The hart ID of this CPU node. + riscv,cbom-block-size: $ref: /schemas/types.yaml#/definitions/uint32 description: @@ -106,7 +110,11 @@ properties: const: 1 compatible: - const: riscv,cpu-intc + oneOf: + - items: + - const: andestech,cpu-intc + - const: riscv,cpu-intc + - const: riscv,cpu-intc interrupt-controller: true diff --git a/Bindings/riscv/extensions.yaml b/Bindings/riscv/extensions.yaml index 63d81dc895e..468c646247a 100644 --- a/Bindings/riscv/extensions.yaml +++ b/Bindings/riscv/extensions.yaml @@ -477,5 +477,12 @@ properties: latency, as ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. + - const: xandespmu + description: + The Andes Technology performance monitor extension for counter overflow + and privilege mode filtering. For more details, see Counter Related + Registers in the AX45MP datasheet. + https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf + additionalProperties: true ... diff --git a/Bindings/rng/atmel,at91-trng.yaml b/Bindings/rng/atmel,at91-trng.yaml index 3ce45456d86..b38f8252342 100644 --- a/Bindings/rng/atmel,at91-trng.yaml +++ b/Bindings/rng/atmel,at91-trng.yaml @@ -21,6 +21,10 @@ properties: - enum: - microchip,sama7g5-trng - const: atmel,at91sam9g45-trng + - items: + - enum: + - microchip,sam9x7-trng + - const: microchip,sam9x60-trng clocks: maxItems: 1 diff --git a/Bindings/rtc/abracon,abx80x.txt b/Bindings/rtc/abracon,abx80x.txt deleted file mode 100644 index 2405e35a1bc..00000000000 --- a/Bindings/rtc/abracon,abx80x.txt +++ /dev/null @@ -1,31 +0,0 @@ -Abracon ABX80X I2C ultra low power RTC/Alarm chip - -The Abracon ABX80X family consist of the ab0801, ab0803, ab0804, ab0805, ab1801, -ab1803, ab1804 and ab1805. The ab0805 is the superset of ab080x and the ab1805 -is the superset of ab180x. - -Required properties: - - - "compatible": should one of: - "abracon,abx80x" - "abracon,ab0801" - "abracon,ab0803" - "abracon,ab0804" - "abracon,ab0805" - "abracon,ab1801" - "abracon,ab1803" - "abracon,ab1804" - "abracon,ab1805" - "microcrystal,rv1805" - Using "abracon,abx80x" will enable chip autodetection. - - "reg": I2C bus address of the device - -Optional properties: - -The abx804 and abx805 have a trickle charger that is able to charge the -connected battery or supercap. Both the following properties have to be defined -and valid to enable charging: - - - "abracon,tc-diode": should be "standard" (0.6V) or "schottky" (0.3V) - - "abracon,tc-resistor": should be <0>, <3>, <6> or <11>. 0 disables the output - resistor, the other values are in kOhm. diff --git a/Bindings/rtc/abracon,abx80x.yaml b/Bindings/rtc/abracon,abx80x.yaml new file mode 100644 index 00000000000..355b0598411 --- /dev/null +++ b/Bindings/rtc/abracon,abx80x.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/abracon,abx80x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Abracon ABX80X I2C ultra low power RTC/Alarm chip + +maintainers: + - linux-rtc@vger.kernel.org + +properties: + compatible: + description: + The wildcard 'abracon,abx80x' may be used to support a mix + of different abracon rtc`s. In this case the driver + must perform auto-detection from ID register. + enum: + - abracon,abx80x + - abracon,ab0801 + - abracon,ab0803 + - abracon,ab0804 + - abracon,ab0805 + - abracon,ab1801 + - abracon,ab1803 + - abracon,ab1804 + - abracon,ab1805 + - microcrystal,rv1805 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + abracon,tc-diode: + description: + Trickle-charge diode type. + Required to enable charging backup battery. + + Supported are 'standard' diodes with a 0.6V drop + and 'schottky' diodes with a 0.3V drop. + $ref: /schemas/types.yaml#/definitions/string + enum: + - standard + - schottky + + abracon,tc-resistor: + description: + Trickle-charge resistor value in kOhm. + Required to enable charging backup battery. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 3, 6, 11] + +dependentRequired: + abracon,tc-diode: ["abracon,tc-resistor"] + abracon,tc-resistor: ["abracon,tc-diode"] + +required: + - compatible + - reg + +allOf: + - $ref: rtc.yaml# + - if: + properties: + compatible: + not: + contains: + enum: + - abracon,abx80x + - abracon,ab0804 + - abracon,ab1804 + - abracon,ab0805 + - abracon,ab1805 + then: + properties: + abracon,tc-diode: false + abracon,tc-resistor: false + +unevaluatedProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + rtc@69 { + compatible = "abracon,abx80x"; + reg = <0x69>; + abracon,tc-diode = "schottky"; + abracon,tc-resistor = <3>; + interrupts = <44 IRQ_TYPE_EDGE_FALLING>; + }; + }; diff --git a/Bindings/rtc/atmel,at91sam9260-rtt.yaml b/Bindings/rtc/atmel,at91sam9260-rtt.yaml index b80b85c394a..a7f6c1d1a08 100644 --- a/Bindings/rtc/atmel,at91sam9260-rtt.yaml +++ b/Bindings/rtc/atmel,at91sam9260-rtt.yaml @@ -19,7 +19,9 @@ properties: - items: - const: atmel,at91sam9260-rtt - items: - - const: microchip,sam9x60-rtt + - enum: + - microchip,sam9x60-rtt + - microchip,sam9x7-rtt - const: atmel,at91sam9260-rtt - items: - const: microchip,sama7g5-rtt diff --git a/Bindings/rtc/mediatek,mt2712-rtc.yaml b/Bindings/rtc/mediatek,mt2712-rtc.yaml new file mode 100644 index 00000000000..75624ddf6d4 --- /dev/null +++ b/Bindings/rtc/mediatek,mt2712-rtc.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/mediatek,mt2712-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT2712 on-SoC RTC + +allOf: + - $ref: rtc.yaml# + +maintainers: + - Ran Bi + +properties: + compatible: + const: mediatek,mt2712-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + + rtc@10011000 { + compatible = "mediatek,mt2712-rtc"; + reg = <0x10011000 0x1000>; + interrupts = ; + }; diff --git a/Bindings/rtc/mediatek,mt7622-rtc.yaml b/Bindings/rtc/mediatek,mt7622-rtc.yaml new file mode 100644 index 00000000000..e74dfc161cf --- /dev/null +++ b/Bindings/rtc/mediatek,mt7622-rtc.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/mediatek,mt7622-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT7622 on-SoC RTC + +allOf: + - $ref: rtc.yaml# + +maintainers: + - Sean Wang + +properties: + compatible: + items: + - const: mediatek,mt7622-rtc + - const: mediatek,soc-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: rtc + +required: + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + + rtc@10212800 { + compatible = "mediatek,mt7622-rtc", "mediatek,soc-rtc"; + reg = <0x10212800 0x200>; + interrupts = ; + clocks = <&topckgen CLK_TOP_RTC>; + clock-names = "rtc"; + }; diff --git a/Bindings/rtc/rtc-mt2712.txt b/Bindings/rtc/rtc-mt2712.txt deleted file mode 100644 index c33d87e5e75..00000000000 --- a/Bindings/rtc/rtc-mt2712.txt +++ /dev/null @@ -1,14 +0,0 @@ -Device-Tree bindings for MediaTek SoC based RTC - -Required properties: -- compatible : Should be "mediatek,mt2712-rtc" : for MT2712 SoC -- reg : Specifies base physical address and size of the registers; -- interrupts : Should contain the interrupt for RTC alarm; - -Example: - -rtc: rtc@10011000 { - compatible = "mediatek,mt2712-rtc"; - reg = <0 0x10011000 0 0x1000>; - interrupts = ; -}; diff --git a/Bindings/rtc/rtc-mt7622.txt b/Bindings/rtc/rtc-mt7622.txt deleted file mode 100644 index 09fe8f51476..00000000000 --- a/Bindings/rtc/rtc-mt7622.txt +++ /dev/null @@ -1,21 +0,0 @@ -Device-Tree bindings for MediaTek SoC based RTC - -Required properties: -- compatible : Should be - "mediatek,mt7622-rtc", "mediatek,soc-rtc" : for MT7622 SoC -- reg : Specifies base physical address and size of the registers; -- interrupts : Should contain the interrupt for RTC alarm; -- clocks : Specifies list of clock specifiers, corresponding to - entries in clock-names property; -- clock-names : Should contain "rtc" entries - -Example: - -rtc: rtc@10212800 { - compatible = "mediatek,mt7622-rtc", - "mediatek,soc-rtc"; - reg = <0 0x10212800 0 0x200>; - interrupts = ; - clocks = <&topckgen CLK_TOP_RTC>; - clock-names = "rtc"; -}; diff --git a/Bindings/rtc/sa1100-rtc.yaml b/Bindings/rtc/sa1100-rtc.yaml index a16c355dcd1..fcf52d2cac9 100644 --- a/Bindings/rtc/sa1100-rtc.yaml +++ b/Bindings/rtc/sa1100-rtc.yaml @@ -12,7 +12,7 @@ allOf: maintainers: - Alessandro Zummo - Alexandre Belloni - - Rob Herring + - Rob Herring properties: compatible: diff --git a/Bindings/rtc/xlnx,zynqmp-rtc.yaml b/Bindings/rtc/xlnx,zynqmp-rtc.yaml index d1f5eb996db..01cc90fee81 100644 --- a/Bindings/rtc/xlnx,zynqmp-rtc.yaml +++ b/Bindings/rtc/xlnx,zynqmp-rtc.yaml @@ -18,7 +18,13 @@ allOf: properties: compatible: - const: xlnx,zynqmp-rtc + oneOf: + - const: xlnx,zynqmp-rtc + - items: + - enum: + - xlnx,versal-rtc + - xlnx,versal-net-rtc + - const: xlnx,zynqmp-rtc reg: maxItems: 1 @@ -48,6 +54,9 @@ properties: default: 0x198233 deprecated: true + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Bindings/serial/atmel,at91-usart.yaml b/Bindings/serial/atmel,at91-usart.yaml index 65cb2e5c5ee..eb2992a447d 100644 --- a/Bindings/serial/atmel,at91-usart.yaml +++ b/Bindings/serial/atmel,at91-usart.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART) maintainers: - - Richard Genoud + - Richard Genoud properties: compatible: diff --git a/Bindings/serial/cdns,uart.yaml b/Bindings/serial/cdns,uart.yaml index e35ad1109ef..2129247d7c8 100644 --- a/Bindings/serial/cdns,uart.yaml +++ b/Bindings/serial/cdns,uart.yaml @@ -55,6 +55,7 @@ required: allOf: - $ref: serial.yaml# + - $ref: rs485.yaml# - if: properties: compatible: diff --git a/Bindings/serial/fsl-lpuart.yaml b/Bindings/serial/fsl-lpuart.yaml index 3a5b59f5d3e..3f9ace89dee 100644 --- a/Bindings/serial/fsl-lpuart.yaml +++ b/Bindings/serial/fsl-lpuart.yaml @@ -30,6 +30,7 @@ properties: - items: - enum: - fsl,imx93-lpuart + - fsl,imx95-lpuart - const: fsl,imx8ulp-lpuart - const: fsl,imx7ulp-lpuart - items: diff --git a/Bindings/serial/renesas,hscif.yaml b/Bindings/serial/renesas,hscif.yaml index 2046e2dc0a3..9480ed30915 100644 --- a/Bindings/serial/renesas,hscif.yaml +++ b/Bindings/serial/renesas,hscif.yaml @@ -59,6 +59,7 @@ properties: - renesas,hscif-r8a779a0 # R-Car V3U - renesas,hscif-r8a779f0 # R-Car S4-8 - renesas,hscif-r8a779g0 # R-Car V4H + - renesas,hscif-r8a779h0 # R-Car V4M - const: renesas,rcar-gen4-hscif # R-Car Gen4 - const: renesas,hscif # generic HSCIF compatible UART diff --git a/Bindings/serial/samsung_uart.yaml b/Bindings/serial/samsung_uart.yaml index 133259ed3a3..0f013102691 100644 --- a/Bindings/serial/samsung_uart.yaml +++ b/Bindings/serial/samsung_uart.yaml @@ -143,6 +143,8 @@ allOf: then: required: - samsung,uart-fifosize + properties: + reg-io-width: false unevaluatedProperties: false diff --git a/Bindings/serial/serial.yaml b/Bindings/serial/serial.yaml index 65804ca274a..ffc9198ae21 100644 --- a/Bindings/serial/serial.yaml +++ b/Bindings/serial/serial.yaml @@ -88,7 +88,7 @@ properties: TX FIFO threshold configuration (in bytes). patternProperties: - "^(bluetooth|bluetooth-gnss|gnss|gps|mcu)$": + "^(bluetooth|bluetooth-gnss|gnss|gps|mcu|onewire)$": if: type: object then: diff --git a/Bindings/serial/st,asc.yaml b/Bindings/serial/st,asc.yaml new file mode 100644 index 00000000000..f2083388f36 --- /dev/null +++ b/Bindings/serial/st,asc.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/st,asc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STi SoCs Serial Port + +maintainers: + - Patrice Chotard + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + const: st,asc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + st,hw-flow-ctrl: + description: When set, enable hardware flow control. + type: boolean + + st,force-m1: + description: When set, force asc to be in Mode-1. This is recommended for + high bit rates above 19.2K. + type: boolean + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + #include + serial@9830000 { + compatible = "st,asc"; + reg = <0x9830000 0x2c>; + interrupts = ; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + }; +... diff --git a/Bindings/serial/st,stm32-uart.yaml b/Bindings/serial/st,stm32-uart.yaml index 1df8ffe95fc..62f97da1b2f 100644 --- a/Bindings/serial/st,stm32-uart.yaml +++ b/Bindings/serial/st,stm32-uart.yaml @@ -58,6 +58,9 @@ properties: wakeup-source: true + power-domains: + maxItems: 1 + rx-threshold: description: If value is set to 1, RX FIFO threshold is disabled. diff --git a/Bindings/serial/st-asc.txt b/Bindings/serial/st-asc.txt deleted file mode 100644 index a1b9b6f3490..00000000000 --- a/Bindings/serial/st-asc.txt +++ /dev/null @@ -1,18 +0,0 @@ -*st-asc(Serial Port) - -Required properties: -- compatible : Should be "st,asc". -- reg, reg-names, interrupts, interrupt-names : Standard way to define device - resources with names. look in - Documentation/devicetree/bindings/resource-names.txt - -Optional properties: -- st,hw-flow-ctrl bool flag to enable hardware flow control. -- st,force-m1 bool flat to force asc to be in Mode-1 recommended - for high bit rates (above 19.2K) -Example: -serial@fe440000{ - compatible = "st,asc"; - reg = <0xfe440000 0x2c>; - interrupts = <0 209 0>; -}; diff --git a/Bindings/soc/fsl/fsl,layerscape-dcfg.yaml b/Bindings/soc/fsl/fsl,layerscape-dcfg.yaml index 397f75909b2..ce1a6505eb5 100644 --- a/Bindings/soc/fsl/fsl,layerscape-dcfg.yaml +++ b/Bindings/soc/fsl/fsl,layerscape-dcfg.yaml @@ -51,7 +51,7 @@ properties: ranges: true patternProperties: - "^clock-controller@[0-9a-z]+$": + "^clock-controller@[0-9a-f]+$": $ref: /schemas/clock/fsl,flexspi-clock.yaml# required: diff --git a/Bindings/soc/fsl/fsl,layerscape-scfg.yaml b/Bindings/soc/fsl/fsl,layerscape-scfg.yaml index 8d088b5fe82..a6a511b00a1 100644 --- a/Bindings/soc/fsl/fsl,layerscape-scfg.yaml +++ b/Bindings/soc/fsl/fsl,layerscape-scfg.yaml @@ -41,7 +41,7 @@ properties: ranges: true patternProperties: - "^interrupt-controller@[a-z0-9]+$": + "^interrupt-controller@[a-f0-9]+$": $ref: /schemas/interrupt-controller/fsl,ls-extirq.yaml# required: diff --git a/Bindings/soc/imx/fsl,imx-anatop.yaml b/Bindings/soc/imx/fsl,imx-anatop.yaml new file mode 100644 index 00000000000..c4ae4f28422 --- /dev/null +++ b/Bindings/soc/imx/fsl,imx-anatop.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx-anatop.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ANATOP register + +maintainers: + - Shawn Guo + - Sascha Hauer + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,imx6sl-anatop + - fsl,imx6sll-anatop + - fsl,imx6sx-anatop + - fsl,imx6ul-anatop + - fsl,imx7d-anatop + - const: fsl,imx6q-anatop + - const: syscon + - const: simple-mfd + - items: + - const: fsl,imx6q-anatop + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + interrupts: + items: + - description: Temperature sensor event + - description: Brown-out event on either of the support regulators + - description: Brown-out event on either the core, gpu or soc regulators + + tempmon: + type: object + unevaluatedProperties: false + $ref: /schemas/thermal/imx-thermal.yaml + +patternProperties: + "regulator-((1p1)|(2p5)|(3p0)|(vddcore)|(vddpu)|(vddsoc))$": + type: object + unevaluatedProperties: false + $ref: /schemas/regulator/anatop-regulator.yaml + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + #include + + anatop: anatop@20c8000 { + compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop", + "syscon", "simple-mfd"; + reg = <0x020c8000 0x1000>; + interrupts = , + , + ; + + reg_3p0: regulator-3p0 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd3p0"; + regulator-min-microvolt = <2625000>; + regulator-max-microvolt = <3400000>; + anatop-reg-offset = <0x120>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2625000>; + anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; + }; + + reg_arm: regulator-vddcore { + compatible = "fsl,anatop-regulator"; + regulator-name = "cpu"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <0>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <24>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + reg_soc: regulator-vddsoc { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddsoc"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <18>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <28>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + tempmon: tempmon { + compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; + interrupt-parent = <&gpc>; + interrupts = ; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; + #thermal-sensor-cells = <0>; + }; + }; diff --git a/Bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml b/Bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml index 1da1b758b4a..8451cb4dd87 100644 --- a/Bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml +++ b/Bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml @@ -17,7 +17,23 @@ properties: compatible: oneOf: - items: - - const: fsl,imx8mq-iomuxc-gpr + - enum: + - fsl,imx6q-iomuxc-gpr + - fsl,imx8mq-iomuxc-gpr + - const: syscon + - const: simple-mfd + - items: + - enum: + - fsl,imx6sl-iomuxc-gpr + - fsl,imx6sll-iomuxc-gpr + - fsl,imx6ul-iomuxc-gpr + - const: fsl,imx6q-iomuxc-gpr + - const: syscon + - items: + - enum: + - fsl,imx6sx-iomuxc-gpr + - fsl,imx7d-iomuxc-gpr + - const: fsl,imx6q-iomuxc-gpr - const: syscon - const: simple-mfd - items: diff --git a/Bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml b/Bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml index 1be4ce2a45e..bd1cdaa4f54 100644 --- a/Bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml +++ b/Bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml @@ -27,8 +27,8 @@ properties: const: 1 power-domains: - minItems: 8 - maxItems: 8 + minItems: 10 + maxItems: 10 power-domain-names: items: @@ -40,10 +40,12 @@ properties: - const: trng - const: hdmi-tx - const: hdmi-tx-phy + - const: hdcp + - const: hrv clocks: - minItems: 4 - maxItems: 4 + minItems: 5 + maxItems: 5 clock-names: items: @@ -51,6 +53,7 @@ properties: - const: axi - const: ref_266m - const: ref_24m + - const: fdcc interconnects: maxItems: 3 @@ -82,12 +85,15 @@ examples: clocks = <&clk IMX8MP_CLK_HDMI_APB>, <&clk IMX8MP_CLK_HDMI_ROOT>, <&clk IMX8MP_CLK_HDMI_REF_266M>, - <&clk IMX8MP_CLK_HDMI_24M>; - clock-names = "apb", "axi", "ref_266m", "ref_24m"; + <&clk IMX8MP_CLK_HDMI_24M>, + <&clk IMX8MP_CLK_HDMI_FDCC_TST>; + clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc"; power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>, - <&pgc_hdmimix>, <&pgc_hdmi_phy>; + <&pgc_hdmimix>, <&pgc_hdmi_phy>, + <&pgc_hdmimix>, <&pgc_hdmimix>; power-domain-names = "bus", "irqsteer", "lcdif", "pai", "pvi", "trng", - "hdmi-tx", "hdmi-tx-phy"; + "hdmi-tx", "hdmi-tx-phy", + "hdcp", "hrv"; #power-domain-cells = <1>; }; diff --git a/Bindings/soc/qcom/qcom,pbs.yaml b/Bindings/soc/qcom/qcom,pbs.yaml new file mode 100644 index 00000000000..b502ca72266 --- /dev/null +++ b/Bindings/soc/qcom/qcom,pbs.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,pbs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Programmable Boot Sequencer + +maintainers: + - Anjelique Melendez + +description: | + The Qualcomm Technologies, Inc. Programmable Boot Sequencer (PBS) + supports triggering power up and power down sequences for clients + upon request. + +properties: + compatible: + items: + - enum: + - qcom,pmi632-pbs + - const: qcom,pbs + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + pmic@0 { + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pbs@7400 { + compatible = "qcom,pmi632-pbs", "qcom,pbs"; + reg = <0x7400>; + }; + }; diff --git a/Bindings/soc/qcom/qcom,pmic-glink.yaml b/Bindings/soc/qcom/qcom,pmic-glink.yaml index 61df97ffe1e..4310bae6c58 100644 --- a/Bindings/soc/qcom/qcom,pmic-glink.yaml +++ b/Bindings/soc/qcom/qcom,pmic-glink.yaml @@ -23,6 +23,7 @@ properties: oneOf: - items: - enum: + - qcom,qcm6490-pmic-glink - qcom,sc8180x-pmic-glink - qcom,sc8280xp-pmic-glink - qcom,sm8350-pmic-glink @@ -32,6 +33,7 @@ properties: - items: - enum: - qcom,sm8650-pmic-glink + - qcom,x1e80100-pmic-glink - const: qcom,sm8550-pmic-glink - const: qcom,pmic-glink @@ -65,6 +67,7 @@ allOf: enum: - qcom,sm8450-pmic-glink - qcom,sm8550-pmic-glink + - qcom,x1e80100-pmic-glink then: properties: orientation-gpios: false diff --git a/Bindings/soc/qcom/qcom,rpm-master-stats.yaml b/Bindings/soc/qcom/qcom,rpm-master-stats.yaml index 031800985b5..9410404f87f 100644 --- a/Bindings/soc/qcom/qcom,rpm-master-stats.yaml +++ b/Bindings/soc/qcom/qcom,rpm-master-stats.yaml @@ -35,6 +35,8 @@ properties: description: Phandle to an RPM MSG RAM slice containing the master stats minItems: 1 maxItems: 5 + items: + maxItems: 1 qcom,master-names: $ref: /schemas/types.yaml#/definitions/string-array diff --git a/Bindings/soc/qcom/qcom,spm.yaml b/Bindings/soc/qcom/qcom,saw2.yaml similarity index 53% rename from Bindings/soc/qcom/qcom,spm.yaml rename to Bindings/soc/qcom/qcom,saw2.yaml index 20c8cd38ff0..ca4bce81727 100644 --- a/Bindings/soc/qcom/qcom,spm.yaml +++ b/Bindings/soc/qcom/qcom,saw2.yaml @@ -1,23 +1,33 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/soc/qcom/qcom,spm.yaml# +$id: http://devicetree.org/schemas/soc/qcom/qcom,saw2.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Subsystem Power Manager +title: Qualcomm Subsystem Power Manager / SPM AVS Wrapper 2 (SAW2) maintainers: - Andy Gross - Bjorn Andersson description: | - This binding describes the Qualcomm Subsystem Power Manager, used to control - the peripheral logic surrounding the application cores in Qualcomm platforms. + The Qualcomm Subsystem Power Manager is used to control the peripheral logic + surrounding the application cores in Qualcomm platforms. + + The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the + Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable + power-controller that transitions a piece of hardware (like a processor or + subsystem) into and out of low power modes via a direct connection to + the PMIC. It can also be wired up to interact with other processors in the + system, notifying them when a low power state is entered or exited. properties: compatible: items: - enum: + - qcom,ipq4019-saw2-cpu + - qcom,ipq4019-saw2-l2 + - qcom,ipq8064-saw2-cpu - qcom,sdm660-gold-saw2-v4.1-l2 - qcom,sdm660-silver-saw2-v4.1-l2 - qcom,msm8998-gold-saw2-v4.1-l2 @@ -26,16 +36,27 @@ properties: - qcom,msm8916-saw2-v3.0-cpu - qcom,msm8939-saw2-v3.0-cpu - qcom,msm8226-saw2-v2.1-cpu + - qcom,msm8226-saw2-v2.1-l2 + - qcom,msm8960-saw2-cpu - qcom,msm8974-saw2-v2.1-cpu + - qcom,msm8974-saw2-v2.1-l2 - qcom,msm8976-gold-saw2-v2.3-l2 - qcom,msm8976-silver-saw2-v2.3-l2 - qcom,apq8084-saw2-v2.1-cpu + - qcom,apq8084-saw2-v2.1-l2 - qcom,apq8064-saw2-v1.1-cpu - const: qcom,saw2 reg: - description: Base address and size of the SPM register region - maxItems: 1 + items: + - description: Base address and size of the SPM register region + - description: Base address and size of the alias register region + minItems: 1 + + regulator: + $ref: /schemas/regulator/regulator.yaml# + description: Indicates that this SPM device acts as a regulator device + device for the core (CPU or Cache) the SPM is attached to. required: - compatible @@ -82,4 +103,17 @@ examples: reg = <0x17912000 0x1000>; }; + - | + /* + * Example 3: SAW2 with the bundled regulator definition. + */ + power-manager@2089000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + + regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; + }; ... diff --git a/Bindings/soc/renesas/renesas-soc.yaml b/Bindings/soc/renesas/renesas-soc.yaml new file mode 100644 index 00000000000..5ddd31f30f2 --- /dev/null +++ b/Bindings/soc/renesas/renesas-soc.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/renesas-soc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SoC compatibles naming convention + +maintainers: + - Geert Uytterhoeven + - Niklas Söderlund + +description: | + Guidelines for new compatibles for SoC blocks/components. + When adding new compatibles in new bindings, use the format:: + renesas,SoC-IP + + For example:: + renesas,r8a77965-csi2 + + When adding new compatibles to existing bindings, use the format in the + existing binding, even if it contradicts the above. + +select: + properties: + compatible: + contains: + pattern: "^renesas,.+-.+$" + required: + - compatible + +properties: + compatible: + minItems: 1 + maxItems: 4 + items: + anyOf: + # Preferred naming style for compatibles of SoC components + - pattern: "^renesas,(emev2|r(7s|8a|9a)[a-z0-9]+|rcar|rmobile|rz[a-z0-9]*|sh(7[a-z0-9]+)?|mobile)-[a-z0-9-]+$" + - pattern: "^renesas,(condor|falcon|gr-peach|gray-hawk|salvator|sk-rz|smar(c(2)?)?|spider|white-hawk)(.*)?$" + + # Legacy compatibles + # + # New compatibles are not allowed. + - pattern: "^renesas,(can|cpg|dmac|du|(g)?ether(avb)?|gpio|hscif|(r)?i[i2]c|imr|intc|ipmmu|irqc|jpu|mmcif|msiof|mtu2|pci(e)?|pfc|pwm|[rq]spi|rcar_sound|sata|scif[ab]*|sdhi|thermal|tmu|tpu|usb(2|hs)?|vin|xhci)-[a-z0-9-]+$" + - pattern: "^renesas,(d|s)?bsc(3)?-(r8a73a4|r8a7740|sh73a0)$" + - pattern: "^renesas,em-(gio|sti|uart)$" + - pattern: "^renesas,fsi2-(r8a7740|sh73a0)$" + - pattern: "^renesas,hspi-r8a777[89]$" + - pattern: "^renesas,sysc-(r8a73a4|r8a7740|rmobile|sh73a0)$" + - enum: + - renesas,imr-lx4 + - renesas,mtu2-r7s72100 + + # None SoC component compatibles + # + # Compatibles with the Renesas vendor prefix that do not relate to any SoC + # component are OK. New compatibles are allowed. + - enum: + - renesas,smp-sram + + # Do not fail compatibles not matching the select pattern + # + # Some SoC components in addition to a Renesas compatible list + # compatibles not related to Renesas. The select pattern for this + # schema hits all compatibles that have at lest one Renesas compatible + # and try to validate all values in that compatible array, allow all + # that don't match the schema select pattern. For example, + # + # compatible = "renesas,r9a07g044-mali", "arm,mali-bifrost"; + - pattern: "^(?!renesas,.+-.+).+$" + +additionalProperties: true diff --git a/Bindings/soc/renesas/renesas.yaml b/Bindings/soc/renesas/renesas.yaml index 16ca3ff7b1a..c1ce4da2dc3 100644 --- a/Bindings/soc/renesas/renesas.yaml +++ b/Bindings/soc/renesas/renesas.yaml @@ -348,12 +348,25 @@ properties: - renesas,white-hawk-cpu # White Hawk CPU board (RTP8A779G0ASKB0FC0SA000) - const: renesas,r8a779g0 + - description: R-Car V4H (R8A779G2) + items: + - enum: + - renesas,white-hawk-single # White Hawk Single board (RTP8A779G2ASKB0F10SA001) + - const: renesas,r8a779g2 + - const: renesas,r8a779g0 + - items: - enum: - renesas,white-hawk-breakout # White Hawk BreakOut board (RTP8A779G0ASKB0SB0SA000) - const: renesas,white-hawk-cpu - const: renesas,r8a779g0 + - description: R-Car V4M (R8A779H0) + items: + - enum: + - renesas,gray-hawk-single # Gray Hawk Single board (RTP8A779H0ASKB0F10S) + - const: renesas,r8a779h0 + - description: R-Car H3e (R8A779M0) items: - enum: @@ -475,12 +488,6 @@ properties: - renesas,r9a07g054l2 # Dual Cortex-A55 RZ/V2L - const: renesas,r9a07g054 - - description: RZ/V2M (R9A09G011) - items: - - enum: - - renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0 - - const: renesas,r9a09g011 - - description: RZ/G3S (R9A08G045) items: - enum: @@ -500,6 +507,12 @@ properties: - const: renesas,r9a08g045s33 # PCIe support - const: renesas,r9a08g045 + - description: RZ/V2M (R9A09G011) + items: + - enum: + - renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0 + - const: renesas,r9a09g011 + additionalProperties: true ... diff --git a/Bindings/soc/rockchip/grf.yaml b/Bindings/soc/rockchip/grf.yaml index 9793ea6f0fe..79798c74747 100644 --- a/Bindings/soc/rockchip/grf.yaml +++ b/Bindings/soc/rockchip/grf.yaml @@ -22,12 +22,15 @@ properties: - rockchip,rk3568-usb2phy-grf - rockchip,rk3588-bigcore0-grf - rockchip,rk3588-bigcore1-grf + - rockchip,rk3588-hdptxphy-grf - rockchip,rk3588-ioc - rockchip,rk3588-php-grf - rockchip,rk3588-pipe-phy-grf - rockchip,rk3588-sys-grf - rockchip,rk3588-pcie3-phy-grf - rockchip,rk3588-pcie3-pipe-grf + - rockchip,rk3588-usb-grf + - rockchip,rk3588-usbdpphy-grf - rockchip,rk3588-vo-grf - rockchip,rk3588-vop-grf - rockchip,rv1108-usbgrf @@ -66,6 +69,9 @@ properties: reg: maxItems: 1 + clocks: + maxItems: 1 + "#address-cells": const: 1 @@ -165,6 +171,7 @@ allOf: unevaluatedProperties: false pcie-phy: + type: object description: Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt @@ -248,6 +255,22 @@ allOf: unevaluatedProperties: false + - if: + properties: + compatible: + contains: + enum: + - rockchip,rk3588-vo-grf + + then: + required: + - clocks + + else: + properties: + clocks: false + + examples: - | #include diff --git a/Bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Bindings/soc/samsung/samsung,exynos-sysreg.yaml index 1794e3799f2..c0c6ce8fc78 100644 --- a/Bindings/soc/samsung/samsung,exynos-sysreg.yaml +++ b/Bindings/soc/samsung/samsung,exynos-sysreg.yaml @@ -72,6 +72,8 @@ allOf: compatible: contains: enum: + - google,gs101-peric0-sysreg + - google,gs101-peric1-sysreg - samsung,exynos850-cmgp-sysreg - samsung,exynos850-peri-sysreg - samsung,exynos850-sysreg diff --git a/Bindings/soc/xilinx/xilinx.yaml b/Bindings/soc/xilinx/xilinx.yaml index d4c0fe1fe43..131aba5ed9f 100644 --- a/Bindings/soc/xilinx/xilinx.yaml +++ b/Bindings/soc/xilinx/xilinx.yaml @@ -117,20 +117,70 @@ properties: - const: xlnx,zynqmp - description: Xilinx Kria SOMs + minItems: 3 items: - - const: xlnx,zynqmp-sm-k26-rev1 - - const: xlnx,zynqmp-sm-k26-revB - - const: xlnx,zynqmp-sm-k26-revA - - const: xlnx,zynqmp-sm-k26 - - const: xlnx,zynqmp + enum: + - xlnx,zynqmp-sm-k26-rev2 + - xlnx,zynqmp-sm-k26-rev1 + - xlnx,zynqmp-sm-k26-revB + - xlnx,zynqmp-sm-k26-revA + - xlnx,zynqmp-sm-k26 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp + - contains: + const: xlnx,zynqmp-sm-k26 - description: Xilinx Kria SOMs (starter) + minItems: 3 items: - - const: xlnx,zynqmp-smk-k26-rev1 - - const: xlnx,zynqmp-smk-k26-revB - - const: xlnx,zynqmp-smk-k26-revA - - const: xlnx,zynqmp-smk-k26 - - const: xlnx,zynqmp + enum: + - xlnx,zynqmp-smk-k26-rev2 + - xlnx,zynqmp-smk-k26-rev1 + - xlnx,zynqmp-smk-k26-revB + - xlnx,zynqmp-smk-k26-revA + - xlnx,zynqmp-smk-k26 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp + - contains: + const: xlnx,zynqmp-smk-k26 + + - description: Xilinx Kria SOM KV260 revA/Y/Z + minItems: 3 + items: + enum: + - xlnx,zynqmp-sk-kv260-revA + - xlnx,zynqmp-sk-kv260-revY + - xlnx,zynqmp-sk-kv260-revZ + - xlnx,zynqmp-sk-kv260 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp-sk-kv260-revA + - contains: + const: xlnx,zynqmp-sk-kv260 + - contains: + const: xlnx,zynqmp + + - description: Xilinx Kria SOM KV260 rev2/1/B + minItems: 3 + items: + enum: + - xlnx,zynqmp-sk-kv260-rev2 + - xlnx,zynqmp-sk-kv260-rev1 + - xlnx,zynqmp-sk-kv260-revB + - xlnx,zynqmp-sk-kv260 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp-sk-kv260-revB + - contains: + const: xlnx,zynqmp-sk-kv260 + - contains: + const: xlnx,zynqmp - description: AMD MicroBlaze V (QEMU) items: diff --git a/Bindings/sound/atmel,asoc-wm8904.yaml b/Bindings/sound/atmel,asoc-wm8904.yaml new file mode 100644 index 00000000000..89a67f8e33b --- /dev/null +++ b/Bindings/sound/atmel,asoc-wm8904.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/atmel,asoc-wm8904.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel wm8904 audio codec complex + +maintainers: + - Dharma Balasubiramani + +description: + The ASoC audio complex configuration for Atmel with WM8904 audio codec. + +properties: + compatible: + const: atmel,asoc-wm8904 + + atmel,model: + $ref: /schemas/types.yaml#/definitions/string + description: The user-visible name of this sound complex. + + atmel,ssc-controller: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of the SSC controller. + + atmel,audio-codec: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of the WM8731 audio codec. + + atmel,audio-routing: + description: + A list of the connections between audio components. Each entry is a pair + of strings, the first being the connection's sink, the second being the + connection's source. + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + items: + enum: + # Board Connectors + - Headphone Jack + - Line In Jack + - Mic + # WM8904 CODEC Pins + - IN1L + - IN1R + - IN2L + - IN2R + - IN3L + - IN3R + - HPOUTL + - HPOUTR + - LINEOUTL + - LINEOUTR + - MICBIAS + +required: + - compatible + - atmel,model + - atmel,audio-routing + - atmel,ssc-controller + - atmel,audio-codec + +additionalProperties: false + +examples: + - | + sound { + compatible = "atmel,asoc-wm8904"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck0_as_mck>; + + atmel,model = "wm8904 @ AT91SAM9N12EK"; + + atmel,audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Mic", "MICBIAS", + "IN1L", "Mic"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8904>; + }; diff --git a/Bindings/sound/atmel,sam9x5-wm8731-audio.yaml b/Bindings/sound/atmel,sam9x5-wm8731-audio.yaml new file mode 100644 index 00000000000..33717b728f6 --- /dev/null +++ b/Bindings/sound/atmel,sam9x5-wm8731-audio.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/atmel,sam9x5-wm8731-audio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel at91sam9x5ek wm8731 audio complex + +maintainers: + - Dharma Balasubiramani + +description: + The audio complex configuration for Atmel at91sam9x5ek with WM8731 audio codec. + +properties: + compatible: + const: atmel,sam9x5-wm8731-audio + + atmel,model: + $ref: /schemas/types.yaml#/definitions/string + description: The user-visible name of this sound complex. + + atmel,ssc-controller: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of the SSC controller. + + atmel,audio-codec: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of the WM8731 audio codec. + + atmel,audio-routing: + description: + A list of the connections between audio components. Each entry is a pair + of strings, the first being the connection's sink, the second being the + connection's source. + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + items: + enum: + # Board Connectors + - Headphone Jack + - Line In Jack + + # CODEC Pins + - LOUT + - ROUT + - LHPOUT + - RHPOUT + - LLINEIN + - RLINEIN + - MICIN + +required: + - compatible + - atmel,model + - atmel,ssc-controller + - atmel,audio-codec + - atmel,audio-routing + +additionalProperties: false + +examples: + - | + sound { + compatible = "atmel,sam9x5-wm8731-audio"; + + atmel,model = "wm8731 @ AT91SAM9X5EK"; + + atmel,audio-routing = + "Headphone Jack", "RHPOUT", + "Headphone Jack", "LHPOUT", + "LLINEIN", "Line In Jack", + "RLINEIN", "Line In Jack"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8731>; + }; diff --git a/Bindings/sound/atmel,sama5d2-classd.yaml b/Bindings/sound/atmel,sama5d2-classd.yaml index 43d04702ac2..ae3162fcfe0 100644 --- a/Bindings/sound/atmel,sama5d2-classd.yaml +++ b/Bindings/sound/atmel,sama5d2-classd.yaml @@ -18,7 +18,12 @@ description: properties: compatible: - const: atmel,sama5d2-classd + oneOf: + - items: + - const: atmel,sama5d2-classd + - items: + - const: microchip,sam9x7-classd + - const: atmel,sama5d2-classd reg: maxItems: 1 diff --git a/Bindings/sound/atmel-sam9x5-wm8731-audio.txt b/Bindings/sound/atmel-sam9x5-wm8731-audio.txt deleted file mode 100644 index 8facbce53db..00000000000 --- a/Bindings/sound/atmel-sam9x5-wm8731-audio.txt +++ /dev/null @@ -1,35 +0,0 @@ -* Atmel at91sam9x5ek wm8731 audio complex - -Required properties: - - compatible: "atmel,sam9x5-wm8731-audio" - - atmel,model: The user-visible name of this sound complex. - - atmel,ssc-controller: The phandle of the SSC controller - - atmel,audio-codec: The phandle of the WM8731 audio codec - - atmel,audio-routing: A list of the connections between audio components. - Each entry is a pair of strings, the first being the connection's sink, - the second being the connection's source. - -Available audio endpoints for the audio-routing table: - -Board connectors: - * Headphone Jack - * Line In Jack - -wm8731 pins: -cf Documentation/devicetree/bindings/sound/wlf,wm8731.yaml - -Example: -sound { - compatible = "atmel,sam9x5-wm8731-audio"; - - atmel,model = "wm8731 @ AT91SAM9X5EK"; - - atmel,audio-routing = - "Headphone Jack", "RHPOUT", - "Headphone Jack", "LHPOUT", - "LLINEIN", "Line In Jack", - "RLINEIN", "Line In Jack"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8731>; -}; diff --git a/Bindings/sound/atmel-wm8904.txt b/Bindings/sound/atmel-wm8904.txt deleted file mode 100644 index 8bbe50c884b..00000000000 --- a/Bindings/sound/atmel-wm8904.txt +++ /dev/null @@ -1,55 +0,0 @@ -Atmel ASoC driver with wm8904 audio codec complex - -Required properties: - - compatible: "atmel,asoc-wm8904" - - atmel,model: The user-visible name of this sound complex. - - atmel,audio-routing: A list of the connections between audio components. - Each entry is a pair of strings, the first being the connection's sink, - the second being the connection's source. Valid names for sources and - sinks are the WM8904's pins, and the jacks on the board: - - WM8904 pins: - - * IN1L - * IN1R - * IN2L - * IN2R - * IN3L - * IN3R - * HPOUTL - * HPOUTR - * LINEOUTL - * LINEOUTR - * MICBIAS - - Board connectors: - - * Headphone Jack - * Line In Jack - * Mic - - - atmel,ssc-controller: The phandle of the SSC controller - - atmel,audio-codec: The phandle of the WM8904 audio codec - -Optional properties: - - pinctrl-names, pinctrl-0: Please refer to pinctrl-bindings.txt - -Example: -sound { - compatible = "atmel,asoc-wm8904"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck0_as_mck>; - - atmel,model = "wm8904 @ AT91SAM9N12EK"; - - atmel,audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "IN2L", "Line In Jack", - "IN2R", "Line In Jack", - "Mic", "MICBIAS", - "IN1L", "Mic"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8904>; -}; diff --git a/Bindings/sound/audio-graph-port.yaml b/Bindings/sound/audio-graph-port.yaml index b13c08de505..28b27e7e45d 100644 --- a/Bindings/sound/audio-graph-port.yaml +++ b/Bindings/sound/audio-graph-port.yaml @@ -51,7 +51,7 @@ definitions: - $ref: /schemas/types.yaml#/definitions/phandle clocks: description: Indicates system clock - $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 system-clock-frequency: $ref: simple-card.yaml#/definitions/system-clock-frequency system-clock-direction-out: diff --git a/Bindings/sound/cirrus,cs35l45.yaml b/Bindings/sound/cirrus,cs35l45.yaml index 4c9acb8d4c4..70f6c62aedc 100644 --- a/Bindings/sound/cirrus,cs35l45.yaml +++ b/Bindings/sound/cirrus,cs35l45.yaml @@ -25,6 +25,9 @@ properties: reg: maxItems: 1 + interrupts: + maxItems: 1 + '#sound-dai-cells': const: 1 diff --git a/Bindings/sound/cirrus,cs42l43.yaml b/Bindings/sound/cirrus,cs42l43.yaml index 7f9d8c7a635..99a536601cc 100644 --- a/Bindings/sound/cirrus,cs42l43.yaml +++ b/Bindings/sound/cirrus,cs42l43.yaml @@ -185,11 +185,12 @@ properties: gpio-ranges: items: - - description: A phandle to the CODEC pinctrl node - minimum: 0 - - const: 0 - - const: 0 - - const: 3 + - items: + - description: A phandle to the CODEC pinctrl node + minimum: 0 + - const: 0 + - const: 0 + - const: 3 patternProperties: "-state$": diff --git a/Bindings/sound/cs4341.txt b/Bindings/sound/cs4341.txt index 12b4aa8ef0d..c1d5c8ad1a3 100644 --- a/Bindings/sound/cs4341.txt +++ b/Bindings/sound/cs4341.txt @@ -9,7 +9,7 @@ Required properties: number for SPI. For required properties on I2C-bus, please consult -Documentation/devicetree/bindings/i2c/i2c.txt +dtschema schemas/i2c/i2c-controller.yaml For required properties on SPI-bus, please consult Documentation/devicetree/bindings/spi/spi-bus.txt diff --git a/Bindings/sound/everest,es8326.yaml b/Bindings/sound/everest,es8326.yaml index 07781408e78..8c82d47375e 100644 --- a/Bindings/sound/everest,es8326.yaml +++ b/Bindings/sound/everest,es8326.yaml @@ -38,6 +38,7 @@ properties: default: 0x0f everest,mic1-src: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint8 description: the value of reg 2A when headset plugged. @@ -46,6 +47,7 @@ properties: default: 0x22 everest,mic2-src: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint8 description: the value of reg 2A when headset unplugged. @@ -87,7 +89,7 @@ properties: 0 means the chip detect jack type again after button released. minimum: 0 maximum: 0x7f - default: 0x45 + default: 0x00 required: - compatible @@ -107,10 +109,8 @@ examples: clocks = <&clks 10>; clock-names = "mclk"; #sound-dai-cells = <0>; - everest,mic1-src = [22]; - everest,mic2-src = [44]; everest,jack-pol = [0e]; everest,interrupt-src = [08]; - everest,interrupt-clk = [45]; + everest,interrupt-clk = [00]; }; }; diff --git a/Bindings/sound/fsl,asrc.txt b/Bindings/sound/fsl,asrc.txt deleted file mode 100644 index 998b4c8a7f7..00000000000 --- a/Bindings/sound/fsl,asrc.txt +++ /dev/null @@ -1,80 +0,0 @@ -Freescale Asynchronous Sample Rate Converter (ASRC) Controller - -The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of a -signal associated with an input clock into a signal associated with a different -output clock. The driver currently works as a Front End of DPCM with other Back -Ends Audio controller such as ESAI, SSI and SAI. It has three pairs to support -three substreams within totally 10 channels. - -Required properties: - - - compatible : Compatible list, should contain one of the following - compatibles: - "fsl,imx35-asrc", - "fsl,imx53-asrc", - "fsl,imx8qm-asrc", - "fsl,imx8qxp-asrc", - - - reg : Offset and length of the register set for the device. - - - interrupts : Contains the spdif interrupt. - - - dmas : Generic dma devicetree binding as described in - Documentation/devicetree/bindings/dma/dma.txt. - - - dma-names : Contains "rxa", "rxb", "rxc", "txa", "txb" and "txc". - - - clocks : Contains an entry for each entry in clock-names. - - - clock-names : Contains the following entries - "mem" Peripheral access clock to access registers. - "ipg" Peripheral clock to driver module. - "asrck_<0-f>" Clock sources for input and output clock. - "spba" The spba clock is required when ASRC is placed as a - bus slave of the Shared Peripheral Bus and when two - or more bus masters (CPU, DMA or DSP) try to access - it. This property is optional depending on the SoC - design. - - - fsl,asrc-rate : Defines a mutual sample rate used by DPCM Back Ends. - - - fsl,asrc-width : Defines a mutual sample width used by DPCM Back Ends. - - - fsl,asrc-clk-map : Defines clock map used in driver. which is required - by imx8qm/imx8qxp platform - <0> - select the map for asrc0 in imx8qm/imx8qxp - <1> - select the map for asrc1 in imx8qm/imx8qxp - -Optional properties: - - - big-endian : If this property is absent, the little endian mode - will be in use as default. Otherwise, the big endian - mode will be in use for all the device registers. - - - fsl,asrc-format : Defines a mutual sample format used by DPCM Back - Ends, which can replace the fsl,asrc-width. - The value is 2 (S16_LE), or 6 (S24_LE). - -Example: - -asrc: asrc@2034000 { - compatible = "fsl,imx53-asrc"; - reg = <0x02034000 0x4000>; - interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 107>, <&clks 107>, <&clks 0>, - <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, - <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, - <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, - <&clks 107>, <&clks 0>, <&clks 0>; - clock-names = "mem", "ipg", "asrck0", - "asrck_1", "asrck_2", "asrck_3", "asrck_4", - "asrck_5", "asrck_6", "asrck_7", "asrck_8", - "asrck_9", "asrck_a", "asrck_b", "asrck_c", - "asrck_d", "asrck_e", "asrck_f"; - dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, - <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; - dma-names = "rxa", "rxb", "rxc", - "txa", "txb", "txc"; - fsl,asrc-rate = <48000>; - fsl,asrc-width = <16>; -}; diff --git a/Bindings/sound/fsl,easrc.yaml b/Bindings/sound/fsl,easrc.yaml index a680d7aff23..0782f3f9947 100644 --- a/Bindings/sound/fsl,easrc.yaml +++ b/Bindings/sound/fsl,easrc.yaml @@ -51,8 +51,8 @@ properties: - const: ctx3_tx firmware-name: - $ref: /schemas/types.yaml#/definitions/string - const: imx/easrc/easrc-imx8mn.bin + items: + - const: imx/easrc/easrc-imx8mn.bin description: The coefficient table for the filters fsl,asrc-rate: diff --git a/Bindings/sound/fsl,imx-asrc.yaml b/Bindings/sound/fsl,imx-asrc.yaml new file mode 100644 index 00000000000..bfef2fcb75b --- /dev/null +++ b/Bindings/sound/fsl,imx-asrc.yaml @@ -0,0 +1,162 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/fsl,imx-asrc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Asynchronous Sample Rate Converter (ASRC) Controller + +description: + The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of + a signal associated with an input clock into a signal associated with a + different output clock. The driver currently works as a Front End of DPCM + with other Back Ends Audio controller such as ESAI, SSI and SAI. It has + three pairs to support three substreams within totally 10 channels. + +maintainers: + - Shawn Guo + - Sascha Hauer + +properties: + compatible: + oneOf: + - enum: + - fsl,imx35-asrc + - fsl,imx53-asrc + - fsl,imx8qm-asrc + - fsl,imx8qxp-asrc + - items: + - enum: + - fsl,imx6sx-asrc + - fsl,imx6ul-asrc + - const: fsl,imx53-asrc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + dmas: + maxItems: 6 + + dma-names: + items: + - const: rxa + - const: rxb + - const: rxc + - const: txa + - const: txb + - const: txc + + clocks: + maxItems: 19 + + clock-names: + items: + - const: mem + - const: ipg + - const: asrck_0 + - const: asrck_1 + - const: asrck_2 + - const: asrck_3 + - const: asrck_4 + - const: asrck_5 + - const: asrck_6 + - const: asrck_7 + - const: asrck_8 + - const: asrck_9 + - const: asrck_a + - const: asrck_b + - const: asrck_c + - const: asrck_d + - const: asrck_e + - const: asrck_f + - const: spba + + fsl,asrc-rate: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The mutual sample rate used by DPCM Back Ends + + fsl,asrc-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The mutual sample width used by DPCM Back Ends + enum: [16, 24] + + fsl,asrc-clk-map: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines clock map used in driver + <0> - select the map for asrc0 in imx8qm/imx8qxp + <1> - select the map for asrc1 in imx8qm/imx8qxp + enum: [0, 1] + + big-endian: + type: boolean + description: + If this property is absent, the little endian mode will be in use as + default. Otherwise, the big endian mode will be in use for all the + device registers. + + fsl,asrc-format: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines a mutual sample format used by DPCM Back Ends, which can + replace the fsl,asrc-width. The value is 2 (S16_LE), or 6 (S24_LE). + enum: [2, 6] + +required: + - compatible + - reg + - interrupts + - dmas + - dma-names + - clocks + - clock-names + - fsl,asrc-rate + - fsl,asrc-width + +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8qm-asrc + - fsl,imx8qxp-asrc + then: + required: + - fsl,asrc-clk-map + else: + properties: + fsl,asrc-clk-map: false + +additionalProperties: false + +examples: + - | + #include + #include + asrc: asrc@2034000 { + compatible = "fsl,imx53-asrc"; + reg = <0x02034000 0x4000>; + interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_ASRC_IPG>, + <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>, + <&clks IMX6QDL_CLK_SPBA>; + clock-names = "mem", "ipg", "asrck_0", + "asrck_1", "asrck_2", "asrck_3", "asrck_4", + "asrck_5", "asrck_6", "asrck_7", "asrck_8", + "asrck_9", "asrck_a", "asrck_b", "asrck_c", + "asrck_d", "asrck_e", "asrck_f", "spba"; + dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, + <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <48000>; + fsl,asrc-width = <16>; + }; diff --git a/Bindings/sound/fsl,micfil.yaml b/Bindings/sound/fsl,micfil.yaml index b7e60583563..c1e9803fc11 100644 --- a/Bindings/sound/fsl,micfil.yaml +++ b/Bindings/sound/fsl,micfil.yaml @@ -15,10 +15,16 @@ description: | properties: compatible: - enum: - - fsl,imx8mm-micfil - - fsl,imx8mp-micfil - - fsl,imx93-micfil + oneOf: + - items: + - enum: + - fsl,imx95-micfil + - const: fsl,imx93-micfil + + - enum: + - fsl,imx8mm-micfil + - fsl,imx8mp-micfil + - fsl,imx93-micfil reg: maxItems: 1 diff --git a/Bindings/sound/fsl,sai.yaml b/Bindings/sound/fsl,sai.yaml index 088c26b001c..2456d958ade 100644 --- a/Bindings/sound/fsl,sai.yaml +++ b/Bindings/sound/fsl,sai.yaml @@ -39,6 +39,7 @@ properties: - fsl,imx8qm-sai - fsl,imx8ulp-sai - fsl,imx93-sai + - fsl,imx95-sai - fsl,vf610-sai reg: @@ -75,12 +76,17 @@ properties: - const: pll11k minItems: 4 + power-domains: + maxItems: 1 + dmas: + minItems: 1 items: - description: DMA controller phandle and request line for RX - description: DMA controller phandle and request line for TX dma-names: + minItems: 1 items: - const: rx - const: tx diff --git a/Bindings/sound/infineon,peb2466.yaml b/Bindings/sound/infineon,peb2466.yaml index 66993d378aa..5e11ce2c13a 100644 --- a/Bindings/sound/infineon,peb2466.yaml +++ b/Bindings/sound/infineon,peb2466.yaml @@ -51,7 +51,7 @@ properties: maxItems: 1 firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: Filters coefficients file to load. If this property is omitted, internal filters are disabled. diff --git a/Bindings/sound/microchip,sama7g5-i2smcc.yaml b/Bindings/sound/microchip,sama7g5-i2smcc.yaml index 651f61c7c25..fb630a18435 100644 --- a/Bindings/sound/microchip,sama7g5-i2smcc.yaml +++ b/Bindings/sound/microchip,sama7g5-i2smcc.yaml @@ -24,9 +24,14 @@ properties: const: 0 compatible: - enum: - - microchip,sam9x60-i2smcc - - microchip,sama7g5-i2smcc + oneOf: + - enum: + - microchip,sam9x60-i2smcc + - microchip,sama7g5-i2smcc + - items: + - enum: + - microchip,sam9x7-i2smcc + - const: microchip,sam9x60-i2smcc reg: maxItems: 1 diff --git a/Bindings/sound/qcom,q6usb.yaml b/Bindings/sound/qcom,q6usb.yaml new file mode 100644 index 00000000000..37161d2aa96 --- /dev/null +++ b/Bindings/sound/qcom,q6usb.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/qcom,q6usb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm ASoC DPCM USB backend DAI + +maintainers: + - Wesley Cheng + +description: + The USB port is a supported AFE path on the Q6 DSP. This ASoC DPCM + backend DAI will communicate the required settings to initialize the + XHCI host controller properly for enabling the offloaded audio stream. + Parameters defined under this node will carry settings, which will be + passed along during the QMI stream enable request and configuration of + the XHCI host controller. + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - qcom,q6usb + + iommus: + maxItems: 1 + + "#sound-dai-cells": + const: 1 + + qcom,usb-audio-intr-idx: + description: + Desired XHCI interrupter number to use. Depending on the audio DSP + on the platform, it will operate on a specific XHCI interrupter. + $ref: /schemas/types.yaml#/definitions/uint16 + maximum: 8 + +required: + - compatible + - "#sound-dai-cells" + - qcom,usb-audio-intr-idx + +additionalProperties: false + +examples: + - | + dais { + compatible = "qcom,q6usb"; + #sound-dai-cells = <1>; + iommus = <&apps_smmu 0x180f 0x0>; + qcom,usb-audio-intr-idx = /bits/ 16 <2>; + }; diff --git a/Bindings/sound/qcom,sm8250.yaml b/Bindings/sound/qcom,sm8250.yaml index 6f419747273..2ab6871e89e 100644 --- a/Bindings/sound/qcom,sm8250.yaml +++ b/Bindings/sound/qcom,sm8250.yaml @@ -107,7 +107,7 @@ patternProperties: properties: sound-dai: minItems: 1 - maxItems: 4 + maxItems: 8 required: - link-name diff --git a/Bindings/sound/qcom,wcd938x.yaml b/Bindings/sound/qcom,wcd938x.yaml index adbfa67f88e..cf6c3787adf 100644 --- a/Bindings/sound/qcom,wcd938x.yaml +++ b/Bindings/sound/qcom,wcd938x.yaml @@ -15,6 +15,7 @@ description: | allOf: - $ref: dai-common.yaml# + - $ref: qcom,wcd93xx-common.yaml# properties: compatible: @@ -22,92 +23,12 @@ properties: - qcom,wcd9380-codec - qcom,wcd9385-codec - reset-gpios: - description: GPIO spec for reset line to use - maxItems: 1 - us-euro-gpios: description: GPIO spec for swapping gnd and mic segments maxItems: 1 - vdd-buck-supply: - description: A reference to the 1.8V buck supply - - vdd-rxtx-supply: - description: A reference to the 1.8V rx supply - - vdd-io-supply: - description: A reference to the 1.8V I/O supply - - vdd-mic-bias-supply: - description: A reference to the 3.8V mic bias supply - - qcom,tx-device: - $ref: /schemas/types.yaml#/definitions/phandle-array - description: A reference to Soundwire tx device phandle - - qcom,rx-device: - $ref: /schemas/types.yaml#/definitions/phandle-array - description: A reference to Soundwire rx device phandle - - qcom,micbias1-microvolt: - description: micbias1 voltage - minimum: 1800000 - maximum: 2850000 - - qcom,micbias2-microvolt: - description: micbias2 voltage - minimum: 1800000 - maximum: 2850000 - - qcom,micbias3-microvolt: - description: micbias3 voltage - minimum: 1800000 - maximum: 2850000 - - qcom,micbias4-microvolt: - description: micbias4 voltage - minimum: 1800000 - maximum: 2850000 - - qcom,hphl-jack-type-normally-closed: - description: Indicates that HPHL jack switch type is normally closed - type: boolean - - qcom,ground-jack-type-normally-closed: - description: Indicates that Headset Ground switch type is normally closed - type: boolean - - qcom,mbhc-headset-vthreshold-microvolt: - description: Voltage threshold value for headset detection - minimum: 0 - maximum: 2850000 - - qcom,mbhc-headphone-vthreshold-microvolt: - description: Voltage threshold value for headphone detection - minimum: 0 - maximum: 2850000 - - qcom,mbhc-buttons-vthreshold-microvolt: - description: - Array of 8 Voltage threshold values corresponding to headset - button0 - button7 - minItems: 8 - maxItems: 8 - - '#sound-dai-cells': - const: 1 - required: - compatible - - reset-gpios - - qcom,tx-device - - qcom,rx-device - - qcom,micbias1-microvolt - - qcom,micbias2-microvolt - - qcom,micbias3-microvolt - - qcom,micbias4-microvolt - - "#sound-dai-cells" unevaluatedProperties: false diff --git a/Bindings/sound/qcom,wcd939x-sdw.yaml b/Bindings/sound/qcom,wcd939x-sdw.yaml new file mode 100644 index 00000000000..67ed7701b5d --- /dev/null +++ b/Bindings/sound/qcom,wcd939x-sdw.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/qcom,wcd939x-sdw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SoundWire devices on WCD9390/WCD9395 + +maintainers: + - Srinivas Kandagatla + +description: | + Qualcomm WCD9390/WCD9395 Codec is a standalone Hi-Fi audio codec IC. + It has RX and TX Soundwire devices. This bindings is for the devices. + +properties: + compatible: + const: sdw20217010e00 + + reg: + maxItems: 1 + + qcom,tx-port-mapping: + description: | + Specifies static port mapping between device and host tx ports. + In the order of the device port index. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 4 + maxItems: 4 + + qcom,rx-port-mapping: + description: | + Specifies static port mapping between device and host rx ports. + In the order of device port index. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 6 + maxItems: 6 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soundwire@3210000 { + #address-cells = <2>; + #size-cells = <0>; + reg = <0x03210000 0x2000>; + wcd938x_rx: codec@0,4 { + compatible = "sdw20217010e00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5 6>; + }; + }; + + soundwire@3230000 { + #address-cells = <2>; + #size-cells = <0>; + reg = <0x03230000 0x2000>; + wcd938x_tx: codec@0,3 { + compatible = "sdw20217010e00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 3 4 5>; + }; + }; + +... diff --git a/Bindings/sound/qcom,wcd939x.yaml b/Bindings/sound/qcom,wcd939x.yaml new file mode 100644 index 00000000000..6e76f6a8634 --- /dev/null +++ b/Bindings/sound/qcom,wcd939x.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/qcom,wcd939x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm WCD9380/WCD9385 Audio Codec + +maintainers: + - Srinivas Kandagatla + +description: | + Qualcomm WCD9390/WCD9395 Codec is a standalone Hi-Fi audio codec IC. + It has RX and TX Soundwire devices. + The WCD9390/WCD9395 IC has a functionally separate USB-C Mux subsystem + accessible over an I2C interface. + The Audio Headphone and Microphone data path between the Codec and the USB-C Mux + subsystems are external to the IC, thus requiring DT port-endpoint graph description + to handle USB-C altmode & orientation switching for Audio Accessory Mode. + +allOf: + - $ref: dai-common.yaml# + - $ref: qcom,wcd93xx-common.yaml# + +properties: + compatible: + oneOf: + - const: qcom,wcd9390-codec + - items: + - const: qcom,wcd9395-codec + - const: qcom,wcd9390-codec + + mode-switch: + description: Flag the port as possible handler of altmode switching + type: boolean + + orientation-switch: + description: Flag the port as possible handler of orientation switching + type: boolean + + port: + $ref: /schemas/graph.yaml#/properties/port + description: + A port node to link the WCD939x Codec node to USB MUX subsystems for the + purpose of handling altmode muxing and orientation switching to detect and + enable Audio Accessory Mode. + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + codec { + compatible = "qcom,wcd9390-codec"; + reset-gpios = <&tlmm 32 IRQ_TYPE_NONE>; + #sound-dai-cells = <1>; + qcom,tx-device = <&wcd939x_tx>; + qcom,rx-device = <&wcd939x_rx>; + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,hphl-jack-type-normally-closed; + qcom,ground-jack-type-normally-closed; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + }; + + /* ... */ + + soundwire@3210000 { + #address-cells = <2>; + #size-cells = <0>; + reg = <0x03210000 0x2000>; + wcd939x_rx: codec@0,4 { + compatible = "sdw20217010e00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5 6>; + }; + }; + + soundwire@3230000 { + #address-cells = <2>; + #size-cells = <0>; + reg = <0x03230000 0x2000>; + wcd938x_tx: codec@0,3 { + compatible = "sdw20217010e00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 3 4 5>; + }; + }; + +... diff --git a/Bindings/sound/qcom,wcd93xx-common.yaml b/Bindings/sound/qcom,wcd93xx-common.yaml new file mode 100644 index 00000000000..f78ba148ad2 --- /dev/null +++ b/Bindings/sound/qcom,wcd93xx-common.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/qcom,wcd93xx-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common properties for Qualcomm WCD93xx Audio Codec + +maintainers: + - Srinivas Kandagatla + +properties: + reset-gpios: + description: GPIO spec for reset line to use + maxItems: 1 + + vdd-buck-supply: + description: A reference to the 1.8V buck supply + + vdd-rxtx-supply: + description: A reference to the 1.8V rx supply + + vdd-io-supply: + description: A reference to the 1.8V I/O supply + + vdd-mic-bias-supply: + description: A reference to the 3.8V mic bias supply + + qcom,tx-device: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: A reference to Soundwire tx device phandle + + qcom,rx-device: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: A reference to Soundwire rx device phandle + + qcom,micbias1-microvolt: + description: micbias1 voltage + minimum: 1800000 + maximum: 2850000 + + qcom,micbias2-microvolt: + description: micbias2 voltage + minimum: 1800000 + maximum: 2850000 + + qcom,micbias3-microvolt: + description: micbias3 voltage + minimum: 1800000 + maximum: 2850000 + + qcom,micbias4-microvolt: + description: micbias4 voltage + minimum: 1800000 + maximum: 2850000 + + qcom,hphl-jack-type-normally-closed: + description: Indicates that HPHL jack switch type is normally closed + type: boolean + + qcom,ground-jack-type-normally-closed: + description: Indicates that Headset Ground switch type is normally closed + type: boolean + + qcom,mbhc-headset-vthreshold-microvolt: + description: Voltage threshold value for headset detection + minimum: 0 + maximum: 2850000 + + qcom,mbhc-headphone-vthreshold-microvolt: + description: Voltage threshold value for headphone detection + minimum: 0 + maximum: 2850000 + + qcom,mbhc-buttons-vthreshold-microvolt: + description: + Array of 8 Voltage threshold values corresponding to headset + button0 - button7 + minItems: 8 + maxItems: 8 + + '#sound-dai-cells': + const: 1 + +required: + - reset-gpios + - qcom,tx-device + - qcom,rx-device + - qcom,micbias1-microvolt + - qcom,micbias2-microvolt + - qcom,micbias3-microvolt + - qcom,micbias4-microvolt + - "#sound-dai-cells" + +additionalProperties: true diff --git a/Bindings/sound/qcom,wsa8840.yaml b/Bindings/sound/qcom,wsa8840.yaml index d717017b0fd..22798d22d98 100644 --- a/Bindings/sound/qcom,wsa8840.yaml +++ b/Bindings/sound/qcom,wsa8840.yaml @@ -28,6 +28,10 @@ properties: description: Powerdown/Shutdown line to use (pin SD_N) maxItems: 1 + reset-gpios: + description: Powerdown/Shutdown line to use (pin SD_N) + maxItems: 1 + '#sound-dai-cells': const: 0 @@ -37,11 +41,16 @@ properties: required: - compatible - reg - - powerdown-gpios - '#sound-dai-cells' - vdd-1p8-supply - vdd-io-supply +oneOf: + - required: + - powerdown-gpios + - required: + - reset-gpios + unevaluatedProperties: false examples: diff --git a/Bindings/sound/realtek,rt1015.yaml b/Bindings/sound/realtek,rt1015.yaml new file mode 100644 index 00000000000..880196081a6 --- /dev/null +++ b/Bindings/sound/realtek,rt1015.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/realtek,rt1015.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RT1015 Mono Class D Audio Amplifier + +maintainers: + - Jack Yu + +properties: + compatible: + enum: + - realtek,rt1015 + + reg: + maxItems: 1 + + realtek,power-up-delay-ms: + description: Set a delay time for flush work to be completed, + this vlaue is adjustable depending on platform. + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + codec@28 { + compatible = "realtek,rt1015"; + reg = <0x28>; + realtek,power-up-delay-ms = <50>; + }; + }; diff --git a/Bindings/sound/rt1015.txt b/Bindings/sound/rt1015.txt deleted file mode 100644 index e498966d436..00000000000 --- a/Bindings/sound/rt1015.txt +++ /dev/null @@ -1,23 +0,0 @@ -RT1015 Mono Class D Audio Amplifier - -This device supports I2C only. - -Required properties: - -- compatible : "realtek,rt1015". - -- reg : The I2C address of the device. - -Optional properties: - -- realtek,power-up-delay-ms - Set a delay time for flush work to be completed, - this value is adjustable depending on platform. - -Example: - -rt1015: codec@28 { - compatible = "realtek,rt1015"; - reg = <0x28>; - realtek,power-up-delay-ms = <50>; -}; diff --git a/Bindings/sound/rt5645.txt b/Bindings/sound/rt5645.txt index 41a62fd2ae1..c1fa379f5f3 100644 --- a/Bindings/sound/rt5645.txt +++ b/Bindings/sound/rt5645.txt @@ -20,6 +20,11 @@ Optional properties: a GPIO spec for the external headphone detect pin. If jd-mode = 0, we will get the JD status by getting the value of hp-detect-gpios. +- cbj-sleeve-gpios: + a GPIO spec to control the external combo jack circuit to tie the sleeve/ring2 + contacts to the ground or floating. It could avoid some electric noise from the + active speaker jacks. + - realtek,in2-differential Boolean. Indicate MIC2 input are differential, rather than single-ended. @@ -68,6 +73,7 @@ codec: rt5650@1a { compatible = "realtek,rt5650"; reg = <0x1a>; hp-detect-gpios = <&gpio 19 0>; + cbj-sleeve-gpios = <&gpio 20 0>; interrupt-parent = <&gpio>; interrupts = <7 IRQ_TYPE_EDGE_FALLING>; realtek,dmic-en = "true"; diff --git a/Bindings/sound/samsung,tm2.yaml b/Bindings/sound/samsung,tm2.yaml index 76059259914..cbc7ba37362 100644 --- a/Bindings/sound/samsung,tm2.yaml +++ b/Bindings/sound/samsung,tm2.yaml @@ -25,8 +25,11 @@ properties: description: Phandles to the codecs. $ref: /schemas/types.yaml#/definitions/phandle-array items: - - description: Phandle to the WM5110 audio codec. - - description: Phandle to the HDMI transmitter node. + - items: + - description: Phandle to the WM5110 audio codec. + - items: + - description: Phandle to the HDMI transmitter node. + samsung,audio-routing: description: | diff --git a/Bindings/spi/atmel,at91rm9200-spi.yaml b/Bindings/spi/atmel,at91rm9200-spi.yaml index 58367587bfb..32e7c14033c 100644 --- a/Bindings/spi/atmel,at91rm9200-spi.yaml +++ b/Bindings/spi/atmel,at91rm9200-spi.yaml @@ -22,7 +22,6 @@ properties: - const: atmel,at91rm9200-spi - items: - const: microchip,sam9x7-spi - - const: microchip,sam9x60-spi - const: atmel,at91rm9200-spi reg: diff --git a/Bindings/spi/samsung,spi.yaml b/Bindings/spi/samsung,spi.yaml index 79da99ca0e5..f681372da81 100644 --- a/Bindings/spi/samsung,spi.yaml +++ b/Bindings/spi/samsung,spi.yaml @@ -17,11 +17,13 @@ properties: compatible: oneOf: - enum: + - google,gs101-spi - samsung,s3c2443-spi # for S3C2443, S3C2416 and S3C2450 - samsung,s3c6410-spi - samsung,s5pv210-spi # for S5PV210 and S5PC110 - samsung,exynos4210-spi - samsung,exynos5433-spi + - samsung,exynos850-spi - samsung,exynosautov9-spi - tesla,fsd-spi - const: samsung,exynos7-spi @@ -74,8 +76,6 @@ required: - compatible - clocks - clock-names - - dmas - - dma-names - interrupts - reg diff --git a/Bindings/spi/spi-controller.yaml b/Bindings/spi/spi-controller.yaml index 524f6fe8c27..093150c0cb8 100644 --- a/Bindings/spi/spi-controller.yaml +++ b/Bindings/spi/spi-controller.yaml @@ -69,6 +69,21 @@ properties: Should be generally avoided and be replaced by spi-cs-high + ACTIVE_HIGH. + fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Size of the RX and TX data FIFOs in bytes. + + rx-fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Size of the RX data FIFO in bytes. + + tx-fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Size of the TX data FIFO in bytes. + num-cs: $ref: /schemas/types.yaml#/definitions/uint32 description: @@ -116,6 +131,10 @@ patternProperties: - compatible - reg +dependencies: + rx-fifo-depth: [ tx-fifo-depth ] + tx-fifo-depth: [ rx-fifo-depth ] + allOf: - if: not: @@ -129,6 +148,14 @@ allOf: properties: "#address-cells": const: 0 + - not: + required: + - fifo-depth + - rx-fifo-depth + - not: + required: + - fifo-depth + - tx-fifo-depth additionalProperties: true diff --git a/Bindings/spi/spi-fsl-lpspi.yaml b/Bindings/spi/spi-fsl-lpspi.yaml index 727c5346b8c..2ff17424479 100644 --- a/Bindings/spi/spi-fsl-lpspi.yaml +++ b/Bindings/spi/spi-fsl-lpspi.yaml @@ -22,6 +22,7 @@ properties: - enum: - fsl,imx8ulp-spi - fsl,imx93-spi + - fsl,imx95-spi - const: fsl,imx7ulp-spi reg: maxItems: 1 diff --git a/Bindings/spi/spi-nxp-fspi.yaml b/Bindings/spi/spi-nxp-fspi.yaml index 7fd59114548..4a5f41bde00 100644 --- a/Bindings/spi/spi-nxp-fspi.yaml +++ b/Bindings/spi/spi-nxp-fspi.yaml @@ -15,12 +15,18 @@ allOf: properties: compatible: - enum: - - nxp,imx8dxl-fspi - - nxp,imx8mm-fspi - - nxp,imx8mp-fspi - - nxp,imx8qxp-fspi - - nxp,lx2160a-fspi + oneOf: + - enum: + - nxp,imx8dxl-fspi + - nxp,imx8mm-fspi + - nxp,imx8mp-fspi + - nxp,imx8qxp-fspi + - nxp,lx2160a-fspi + - items: + - enum: + - nxp,imx93-fspi + - nxp,imx95-fspi + - const: nxp,imx8mm-fspi reg: items: diff --git a/Bindings/sram/allwinner,sun4i-a10-system-control.yaml b/Bindings/sram/allwinner,sun4i-a10-system-control.yaml index a1c96985951..cf07b8f787a 100644 --- a/Bindings/sram/allwinner,sun4i-a10-system-control.yaml +++ b/Bindings/sram/allwinner,sun4i-a10-system-control.yaml @@ -56,7 +56,7 @@ properties: ranges: true patternProperties: - "^sram@[a-z0-9]+": + "^sram@[a-f0-9]+": $ref: /schemas/sram/sram.yaml# unevaluatedProperties: false diff --git a/Bindings/submitting-patches.rst b/Bindings/submitting-patches.rst index 36a17b250cc..a64f21a5f29 100644 --- a/Bindings/submitting-patches.rst +++ b/Bindings/submitting-patches.rst @@ -15,6 +15,11 @@ I. For patch submitters "dt-bindings: : ..." + Few subsystems, like ASoC, media, regulators and SPI, expect reverse order + of the prefixes:: + + ": dt-bindings: ..." + The 80 characters of the subject are precious. It is recommended to not use "Documentation" or "doc" because that is implied. All bindings are docs. Repeating "binding" again should also be avoided. @@ -42,28 +47,18 @@ I. For patch submitters the code implementing the binding. 6) Any compatible strings used in a chip or board DTS file must be - previously documented in the corresponding DT binding text file + previously documented in the corresponding DT binding file in Documentation/devicetree/bindings. This rule applies even if the Linux device driver does not yet match on the compatible string. [ checkpatch will emit warnings if this step is not followed as of commit bff5da4335256513497cc8c79f9a9d1665e09864 ("checkpatch: add DT compatible string documentation checks"). ] - 7) The wildcard "" may be used in compatible strings, as in - the following example: - - - compatible: Must contain '"nvidia,-pcie", - "nvidia,tegra20-pcie"' where is tegra30, tegra132, ... - - As in the above example, the known values of "" should be - documented if it is used. - - 8) If a documented compatible string is not yet matched by the + 7) If a documented compatible string is not yet matched by the driver, the documentation should also include a compatible - string that is matched by the driver (as in the "nvidia,tegra20-pcie" - example above). + string that is matched by the driver. - 9) Bindings are actively used by multiple projects other than the Linux + 8) Bindings are actively used by multiple projects other than the Linux Kernel, extra care and consideration may need to be taken when making changes to existing bindings. diff --git a/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml b/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml index 9b2272a9ec1..6b3aea6d73b 100644 --- a/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml +++ b/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml @@ -21,6 +21,7 @@ properties: - allwinner,sun50i-a100-ths - allwinner,sun50i-h5-ths - allwinner,sun50i-h6-ths + - allwinner,sun50i-h616-ths clocks: minItems: 1 @@ -50,6 +51,10 @@ properties: nvmem-cell-names: const: calibration + allwinner,sram: + maxItems: 1 + description: phandle to device controlling temperate offset SYS_CFG register + # See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for details "#thermal-sensor-cells": enum: @@ -65,6 +70,7 @@ allOf: - allwinner,sun20i-d1-ths - allwinner,sun50i-a100-ths - allwinner,sun50i-h6-ths + - allwinner,sun50i-h616-ths then: properties: @@ -82,6 +88,17 @@ allOf: clock-names: minItems: 2 + - if: + not: + properties: + compatible: + contains: + const: allwinner,sun50i-h616-ths + + then: + properties: + allwinner,sram: false + - if: properties: compatible: @@ -101,17 +118,12 @@ allOf: const: 1 - if: - properties: - compatible: - contains: - enum: - - allwinner,sun8i-h3-ths - - allwinner,sun8i-r40-ths - - allwinner,sun20i-d1-ths - - allwinner,sun50i-a64-ths - - allwinner,sun50i-a100-ths - - allwinner,sun50i-h5-ths - - allwinner,sun50i-h6-ths + not: + properties: + compatible: + contains: + enum: + - allwinner,sun8i-a83t-ths then: required: diff --git a/Bindings/thermal/da9062-thermal.txt b/Bindings/thermal/da9062-thermal.txt deleted file mode 100644 index e241bb5a558..00000000000 --- a/Bindings/thermal/da9062-thermal.txt +++ /dev/null @@ -1,36 +0,0 @@ -* Dialog DA9062/61 TJUNC Thermal Module - -This module is part of the DA9061/DA9062. For more details about entire -DA9062 and DA9061 chips see Documentation/devicetree/bindings/mfd/da9062.txt - -Junction temperature thermal module uses an interrupt signal to identify -high THERMAL_TRIP_HOT temperatures for the PMIC device. - -Required properties: - -- compatible: should be one of the following valid compatible string lines: - "dlg,da9061-thermal", "dlg,da9062-thermal" - "dlg,da9062-thermal" - -Optional properties: - -- polling-delay-passive : Specify the polling period, measured in - milliseconds, between thermal zone device update checks. - -Example: DA9062 - - pmic0: da9062@58 { - thermal { - compatible = "dlg,da9062-thermal"; - polling-delay-passive = <3000>; - }; - }; - -Example: DA9061 using a fall-back compatible for the DA9062 onkey driver - - pmic0: da9061@58 { - thermal { - compatible = "dlg,da9061-thermal", "dlg,da9062-thermal"; - polling-delay-passive = <3000>; - }; - }; diff --git a/Bindings/thermal/dlg,da9062-thermal.yaml b/Bindings/thermal/dlg,da9062-thermal.yaml new file mode 100644 index 00000000000..e8b2cac4108 --- /dev/null +++ b/Bindings/thermal/dlg,da9062-thermal.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/dlg,da9062-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Dialog DA9062/61 TJUNC Thermal Module + +maintainers: + - Biju Das + +description: | + This module is part of the DA9061/DA9062. For more details about entire + DA906{1,2} chips see Documentation/devicetree/bindings/mfd/dlg,da9063.yaml + + Junction temperature thermal module uses an interrupt signal to identify + high THERMAL_TRIP_HOT temperatures for the PMIC device. + +properties: + compatible: + oneOf: + - const: dlg,da9062-thermal + - items: + - const: dlg,da9061-thermal + - const: dlg,da9062-thermal + + polling-delay-passive: + description: + Specify the polling period, measured in milliseconds, between + thermal zone device update checks. + +required: + - compatible + +additionalProperties: false diff --git a/Bindings/thermal/qoriq-thermal.yaml b/Bindings/thermal/qoriq-thermal.yaml index 14574402723..d155d6799da 100644 --- a/Bindings/thermal/qoriq-thermal.yaml +++ b/Bindings/thermal/qoriq-thermal.yaml @@ -33,7 +33,8 @@ properties: description: | The values to be programmed into TTRnCR, as specified by the SoC reference manual. The first cell is TTR0CR, the second is TTR1CR, etc. - maxItems: 4 + minItems: 2 + maxItems: 7 fsl,tmu-calibration: $ref: /schemas/types.yaml#/definitions/uint32-matrix diff --git a/Bindings/thermal/rcar-gen3-thermal.yaml b/Bindings/thermal/rcar-gen3-thermal.yaml index ecf276fd155..6a81cb6e11b 100644 --- a/Bindings/thermal/rcar-gen3-thermal.yaml +++ b/Bindings/thermal/rcar-gen3-thermal.yaml @@ -29,6 +29,7 @@ properties: - renesas,r8a779a0-thermal # R-Car V3U - renesas,r8a779f0-thermal # R-Car S4-8 - renesas,r8a779g0-thermal # R-Car V4H + - renesas,r8a779h0-thermal # R-Car V4M reg: true @@ -90,6 +91,7 @@ else: enum: - renesas,r8a779f0-thermal - renesas,r8a779g0-thermal + - renesas,r8a779h0-thermal then: required: - interrupts diff --git a/Bindings/thermal/thermal-zones.yaml b/Bindings/thermal/thermal-zones.yaml index dbd52620d29..68398e7e865 100644 --- a/Bindings/thermal/thermal-zones.yaml +++ b/Bindings/thermal/thermal-zones.yaml @@ -228,8 +228,6 @@ patternProperties: additionalProperties: false required: - - polling-delay - - polling-delay-passive - thermal-sensors - trips diff --git a/Bindings/timer/arm,arch_timer_mmio.yaml b/Bindings/timer/arm,arch_timer_mmio.yaml index 7a4a6ab8597..ab8f2899313 100644 --- a/Bindings/timer/arm,arch_timer_mmio.yaml +++ b/Bindings/timer/arm,arch_timer_mmio.yaml @@ -60,7 +60,7 @@ properties: be implemented in an always-on power domain." patternProperties: - '^frame@[0-9a-z]*$': + '^frame@[0-9a-f]+$': type: object additionalProperties: false description: A timer node has up to 8 frame sub-nodes, each with the following properties. diff --git a/Bindings/timer/cdns,ttc.yaml b/Bindings/timer/cdns,ttc.yaml index dbba780c9b0..da342464d32 100644 --- a/Bindings/timer/cdns,ttc.yaml +++ b/Bindings/timer/cdns,ttc.yaml @@ -32,12 +32,23 @@ properties: description: | Bit width of the timer, necessary if not 16. + "#pwm-cells": + const: 3 + required: - compatible - reg - - interrupts - clocks +allOf: + - if: + not: + required: + - "#pwm-cells" + then: + required: + - interrupts + additionalProperties: false examples: @@ -50,3 +61,12 @@ examples: clocks = <&cpu_clk 3>; timer-width = <32>; }; + + - | + pwm: pwm@f8002000 { + compatible = "cdns,ttc"; + reg = <0xf8002000 0x1000>; + clocks = <&cpu_clk 3>; + timer-width = <32>; + #pwm-cells = <3>; + }; diff --git a/Bindings/timer/mediatek,mtk-timer.txt b/Bindings/timer/mediatek,mtk-timer.txt deleted file mode 100644 index b3e797e8aa3..00000000000 --- a/Bindings/timer/mediatek,mtk-timer.txt +++ /dev/null @@ -1,48 +0,0 @@ -MediaTek Timers ---------------- - -MediaTek SoCs have different timers on different platforms, -- CPUX (ARM/ARM64 System Timer) -- GPT (General Purpose Timer) -- SYST (System Timer) - -The proper timer will be selected automatically by driver. - -Required properties: -- compatible should contain: - For those SoCs that use GPT - * "mediatek,mt2701-timer" for MT2701 compatible timers (GPT) - * "mediatek,mt6580-timer" for MT6580 compatible timers (GPT) - * "mediatek,mt6582-timer" for MT6582 compatible timers (GPT) - * "mediatek,mt6589-timer" for MT6589 compatible timers (GPT) - * "mediatek,mt7623-timer" for MT7623 compatible timers (GPT) - * "mediatek,mt8127-timer" for MT8127 compatible timers (GPT) - * "mediatek,mt8135-timer" for MT8135 compatible timers (GPT) - * "mediatek,mt8173-timer" for MT8173 compatible timers (GPT) - * "mediatek,mt8516-timer" for MT8516 compatible timers (GPT) - * "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT) - - For those SoCs that use SYST - * "mediatek,mt8183-timer" for MT8183 compatible timers (SYST) - * "mediatek,mt8186-timer" for MT8186 compatible timers (SYST) - * "mediatek,mt8188-timer" for MT8188 compatible timers (SYST) - * "mediatek,mt8192-timer" for MT8192 compatible timers (SYST) - * "mediatek,mt8195-timer" for MT8195 compatible timers (SYST) - * "mediatek,mt7629-timer" for MT7629 compatible timers (SYST) - * "mediatek,mt6765-timer" for MT6765 and all above compatible timers (SYST) - - For those SoCs that use CPUX - * "mediatek,mt6795-systimer" for MT6795 compatible timers (CPUX) - * "mediatek,mt8365-systimer" for MT8365 compatible timers (CPUX) - -- reg: Should contain location and length for timer register. -- clocks: Should contain system clock. - -Examples: - - timer@10008000 { - compatible = "mediatek,mt6577-timer"; - reg = <0x10008000 0x80>; - interrupts = ; - clocks = <&system_clk>; - }; diff --git a/Bindings/timer/mediatek,timer.yaml b/Bindings/timer/mediatek,timer.yaml new file mode 100644 index 00000000000..f68fc7050c5 --- /dev/null +++ b/Bindings/timer/mediatek,timer.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/mediatek,timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek SoC timers + +maintainers: + - Matthias Brugger + +description: + MediaTek SoCs have different timers on different platforms, + CPUX (ARM/ARM64 System Timer), GPT (General Purpose Timer) + and SYST (System Timer). + +properties: + compatible: + oneOf: + - items: + - enum: + - mediatek,mt6577-timer + - mediatek,mt6765-timer + - mediatek,mt6795-systimer + # GPT Timers + - items: + - enum: + - mediatek,mt2701-timer + - mediatek,mt6580-timer + - mediatek,mt6582-timer + - mediatek,mt6589-timer + - mediatek,mt7623-timer + - mediatek,mt8127-timer + - mediatek,mt8135-timer + - mediatek,mt8173-timer + - mediatek,mt8516-timer + - const: mediatek,mt6577-timer + # SYST Timers + - items: + - enum: + - mediatek,mt7629-timer + - mediatek,mt8183-timer + - mediatek,mt8186-timer + - mediatek,mt8188-timer + - mediatek,mt8192-timer + - mediatek,mt8195-timer + - mediatek,mt8365-systimer + - const: mediatek,mt6765-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: Timer clock + - description: RTC or bus clock + + clock-names: + minItems: 1 + maxItems: 2 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + timer@10008000 { + compatible = "mediatek,mt6577-timer"; + reg = <0x10008000 0x80>; + interrupts = ; + clocks = <&system_clk>; + }; diff --git a/Bindings/timer/mrvl,mmp-timer.yaml b/Bindings/timer/mrvl,mmp-timer.yaml index 1ee4aab695d..fe6bc417378 100644 --- a/Bindings/timer/mrvl,mmp-timer.yaml +++ b/Bindings/timer/mrvl,mmp-timer.yaml @@ -9,7 +9,7 @@ title: Marvell MMP Timer maintainers: - Daniel Lezcano - Thomas Gleixner - - Rob Herring + - Rob Herring properties: $nodename: diff --git a/Bindings/timer/nxp,sysctr-timer.yaml b/Bindings/timer/nxp,sysctr-timer.yaml index 2b9653dafab..891cca00952 100644 --- a/Bindings/timer/nxp,sysctr-timer.yaml +++ b/Bindings/timer/nxp,sysctr-timer.yaml @@ -18,7 +18,9 @@ description: | properties: compatible: - const: nxp,sysctr-timer + enum: + - nxp,imx95-sysctr-timer + - nxp,sysctr-timer reg: maxItems: 1 diff --git a/Bindings/timer/ralink,cevt-systick.yaml b/Bindings/timer/ralink,cevt-systick.yaml new file mode 100644 index 00000000000..59d97feddf4 --- /dev/null +++ b/Bindings/timer/ralink,cevt-systick.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/ralink,cevt-systick.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: System tick counter present in Ralink family SoCs + +maintainers: + - Sergio Paracuellos + +properties: + compatible: + const: ralink,cevt-systick + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + systick@d00 { + compatible = "ralink,cevt-systick"; + reg = <0xd00 0x10>; + + interrupt-parent = <&cpuintc>; + interrupts = <7>; + }; +... diff --git a/Bindings/timer/renesas,ostm.yaml b/Bindings/timer/renesas,ostm.yaml index 7207929e5cd..8b06a681764 100644 --- a/Bindings/timer/renesas,ostm.yaml +++ b/Bindings/timer/renesas,ostm.yaml @@ -23,7 +23,7 @@ properties: - enum: - renesas,r7s72100-ostm # RZ/A1H - renesas,r7s9210-ostm # RZ/A2M - - renesas,r9a07g043-ostm # RZ/G2UL + - renesas,r9a07g043-ostm # RZ/G2UL and RZ/Five - renesas,r9a07g044-ostm # RZ/G2{L,LC} - renesas,r9a07g054-ostm # RZ/V2L - const: renesas,ostm # Generic diff --git a/Bindings/timer/renesas,tmu.yaml b/Bindings/timer/renesas,tmu.yaml index a67e427a9e7..84bbe15028a 100644 --- a/Bindings/timer/renesas,tmu.yaml +++ b/Bindings/timer/renesas,tmu.yaml @@ -46,7 +46,19 @@ properties: interrupts: minItems: 2 - maxItems: 3 + items: + - description: Underflow interrupt, channel 0 + - description: Underflow interrupt, channel 1 + - description: Underflow interrupt, channel 2 + - description: Input capture interrupt, channel 2 + + interrupt-names: + minItems: 2 + items: + - const: tuni0 + - const: tuni1 + - const: tuni2 + - const: ticpi2 clocks: maxItems: 1 @@ -100,7 +112,9 @@ examples: reg = <0xffd80000 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&mstp0_clks R8A7779_CLK_TMU0>; clock-names = "fck"; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; diff --git a/Bindings/timer/samsung,exynos4210-mct.yaml b/Bindings/timer/samsung,exynos4210-mct.yaml index 829bd2227f7..774b7992a0c 100644 --- a/Bindings/timer/samsung,exynos4210-mct.yaml +++ b/Bindings/timer/samsung,exynos4210-mct.yaml @@ -26,6 +26,7 @@ properties: - items: - enum: - axis,artpec8-mct + - google,gs101-mct - samsung,exynos3250-mct - samsung,exynos5250-mct - samsung,exynos5260-mct @@ -127,6 +128,7 @@ allOf: contains: enum: - axis,artpec8-mct + - google,gs101-mct - samsung,exynos5260-mct - samsung,exynos5420-mct - samsung,exynos5433-mct diff --git a/Bindings/tpm/tcg,tpm_tis-spi.yaml b/Bindings/tpm/tcg,tpm_tis-spi.yaml index c3413b47ac3..6cb2de7cb56 100644 --- a/Bindings/tpm/tcg,tpm_tis-spi.yaml +++ b/Bindings/tpm/tcg,tpm_tis-spi.yaml @@ -20,6 +20,7 @@ properties: compatible: items: - enum: + - atmel,attpm20p - infineon,slb9670 - st,st33htpm-spi - st,st33zp24-spi diff --git a/Bindings/trivial-devices.yaml b/Bindings/trivial-devices.yaml index 79dcd92c4a4..e07be7bf839 100644 --- a/Bindings/trivial-devices.yaml +++ b/Bindings/trivial-devices.yaml @@ -28,6 +28,7 @@ properties: compatible: items: + # Entries are sorted alphanumerically by the compatible - enum: # Acbel fsg032 power supply - acbel,fsg032 @@ -47,14 +48,16 @@ properties: - adi,lt7182s # AMS iAQ-Core VOC Sensor - ams,iaq-core + # Temperature monitoring of Astera Labs PT5161L PCIe retimer + - asteralabs,pt5161l # i2c serial eeprom (24cxx) - at,24c08 + # i2c h/w elliptic curve crypto module + - atmel,atecc508a # ATSHA204 - i2c h/w symmetric crypto module - atmel,atsha204 # ATSHA204A - i2c h/w symmetric crypto module - atmel,atsha204a - # i2c h/w elliptic curve crypto module - - atmel,atecc508a # BPA-RS600: Power Supply - blutek,bpa-rs600 # Bosch Sensortec pressure, temperature, humididty and VOC sensor @@ -115,20 +118,6 @@ properties: - fsl,mpl3115 # MPR121: Proximity Capacitive Touch Sensor Controller - fsl,mpr121 - # Monolithic Power Systems Inc. multi-phase controller mp2856 - - mps,mp2856 - # Monolithic Power Systems Inc. multi-phase controller mp2857 - - mps,mp2857 - # Monolithic Power Systems Inc. multi-phase controller mp2888 - - mps,mp2888 - # Monolithic Power Systems Inc. multi-phase controller mp2971 - - mps,mp2971 - # Monolithic Power Systems Inc. multi-phase controller mp2973 - - mps,mp2973 - # Monolithic Power Systems Inc. multi-phase controller mp2975 - - mps,mp2975 - # Monolithic Power Systems Inc. multi-phase hot-swap controller mp5990 - - mps,mp5990 # Honeywell Humidicon HIH-6130 humidity/temperature sensor - honeywell,hi6130 # IBM Common Form Factor Power Supply Versions (all versions) @@ -137,16 +126,10 @@ properties: - ibm,cffps1 # IBM Common Form Factor Power Supply Versions 2 - ibm,cffps2 + # Infineon barometric pressure and temperature sensor + - infineon,dps310 # Infineon IR36021 digital POL buck controller - infineon,ir36021 - # Infineon IR38060 Voltage Regulator - - infineon,ir38060 - # Infineon IR38064 Voltage Regulator - - infineon,ir38064 - # Infineon IR38164 Voltage Regulator - - infineon,ir38164 - # Infineon IR38263 Voltage Regulator - - infineon,ir38263 # Infineon IRPS5401 Voltage Regulator (PMIC) - infineon,irps5401 # Infineon TLV493D-A1B6 I2C 3D Magnetic Sensor @@ -195,6 +178,8 @@ properties: - maxim,max1237 # Temperature Sensor, I2C interface - maxim,max1619 + # 3-Channel Remote Temperature Sensor + - maxim,max31730 # 10-bit 10 kOhm linear programmable voltage divider - maxim,max5481 # 10-bit 50 kOhm linear programmable voltage divider @@ -207,8 +192,6 @@ properties: - maxim,max6621 # 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface - maxim,max6625 - # 3-Channel Remote Temperature Sensor - - maxim,max31730 # mCube 3-axis 8-bit digital accelerometer - mcube,mc3230 # Measurement Specialities I2C temperature and humidity sensor @@ -239,8 +222,6 @@ properties: - memsic,mxc6655 # Menlo on-board CPLD trivial SPI device - menlo,m53cpld - # Micron SPI NOR Authenta - - micron,spi-authenta # Microchip differential I2C ADC, 1 Channel, 18 bit - microchip,mcp3421 # Microchip differential I2C ADC, 2 Channel, 18 bit @@ -257,40 +238,58 @@ properties: - microchip,mcp3427 # Microchip differential I2C ADC, 4 Channel, 16 bit - microchip,mcp3428 - # Microchip 7-bit Single I2C Digital POT (5k) - - microchip,mcp4017-502 # Microchip 7-bit Single I2C Digital POT (10k) - microchip,mcp4017-103 - # Microchip 7-bit Single I2C Digital POT (50k) - - microchip,mcp4017-503 # Microchip 7-bit Single I2C Digital POT (100k) - microchip,mcp4017-104 # Microchip 7-bit Single I2C Digital POT (5k) - - microchip,mcp4018-502 + - microchip,mcp4017-502 + # Microchip 7-bit Single I2C Digital POT (50k) + - microchip,mcp4017-503 # Microchip 7-bit Single I2C Digital POT (10k) - microchip,mcp4018-103 - # Microchip 7-bit Single I2C Digital POT (50k) - - microchip,mcp4018-503 # Microchip 7-bit Single I2C Digital POT (100k) - microchip,mcp4018-104 # Microchip 7-bit Single I2C Digital POT (5k) - - microchip,mcp4019-502 + - microchip,mcp4018-502 + # Microchip 7-bit Single I2C Digital POT (50k) + - microchip,mcp4018-503 # Microchip 7-bit Single I2C Digital POT (10k) - microchip,mcp4019-103 - # Microchip 7-bit Single I2C Digital POT (50k) - - microchip,mcp4019-503 # Microchip 7-bit Single I2C Digital POT (100k) - microchip,mcp4019-104 + # Microchip 7-bit Single I2C Digital POT (5k) + - microchip,mcp4019-502 + # Microchip 7-bit Single I2C Digital POT (50k) + - microchip,mcp4019-503 # PWM Fan Speed Controller With Fan Fault Detection - microchip,tc654 # PWM Fan Speed Controller With Fan Fault Detection - microchip,tc655 + # Micron SPI NOR Authenta + - micron,spi-authenta # MiraMEMS DA226 2-axis 14-bit digital accelerometer - miramems,da226 # MiraMEMS DA280 3-axis 14-bit digital accelerometer - miramems,da280 # MiraMEMS DA311 3-axis 12-bit digital accelerometer - miramems,da311 + # Monolithic Power Systems Inc. multi-phase controller mp2856 + - mps,mp2856 + # Monolithic Power Systems Inc. multi-phase controller mp2857 + - mps,mp2857 + # Monolithic Power Systems Inc. multi-phase controller mp2888 + - mps,mp2888 + # Monolithic Power Systems Inc. multi-phase controller mp2971 + - mps,mp2971 + # Monolithic Power Systems Inc. multi-phase controller mp2973 + - mps,mp2973 + # Monolithic Power Systems Inc. multi-phase controller mp2975 + - mps,mp2975 + # Monolithic Power Systems Inc. multi-phase hot-swap controller mp5990 + - mps,mp5990 + # Monolithic Power Systems Inc. synchronous step-down converter mpq8785 + - mps,mpq8785 # Temperature sensor with integrated fan control - national,lm63 # Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor @@ -321,12 +320,12 @@ properties: - samsung,exynos-sataphy-i2c # Semtech sx1301 baseband processor - semtech,sx1301 - # Sensirion low power multi-pixel gas sensor with I2C interface - - sensirion,sgpc3 # Sensirion multi-pixel gas sensor with I2C interface - sensirion,sgp30 # Sensirion gas sensor with I2C interface - sensirion,sgp40 + # Sensirion low power multi-pixel gas sensor with I2C interface + - sensirion,sgpc3 # Sensirion temperature & humidity sensor with I2C interface - sensirion,sht4x # Sensortek 3 axis accelerometer @@ -372,8 +371,6 @@ properties: - ti,lm74 # Temperature sensor with integrated fan control - ti,lm96000 - # I2C Touch-Screen Controller - - ti,tsc2003 # Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface - ti,tmp103 # Thermometer with SPI interface @@ -395,10 +392,12 @@ properties: - ti,tps544b25 - ti,tps544c20 - ti,tps544c25 - # Winbond/Nuvoton H/W Monitor - - winbond,w83793 + # I2C Touch-Screen Controller + - ti,tsc2003 # Vicor Corporation Digital Supervisor - vicor,pli1209bc + # Winbond/Nuvoton H/W Monitor + - winbond,w83793 required: - compatible diff --git a/Bindings/ufs/qcom,ufs.yaml b/Bindings/ufs/qcom,ufs.yaml index 10c146424ba..cd3680dc002 100644 --- a/Bindings/ufs/qcom,ufs.yaml +++ b/Bindings/ufs/qcom,ufs.yaml @@ -27,10 +27,13 @@ properties: - qcom,msm8996-ufshc - qcom,msm8998-ufshc - qcom,sa8775p-ufshc + - qcom,sc7180-ufshc - qcom,sc7280-ufshc + - qcom,sc8180x-ufshc - qcom,sc8280xp-ufshc - qcom,sdm845-ufshc - qcom,sm6115-ufshc + - qcom,sm6125-ufshc - qcom,sm6350-ufshc - qcom,sm8150-ufshc - qcom,sm8250-ufshc @@ -42,11 +45,11 @@ properties: - const: jedec,ufs-2.0 clocks: - minItems: 8 + minItems: 7 maxItems: 11 clock-names: - minItems: 8 + minItems: 7 maxItems: 11 dma-coherent: true @@ -112,6 +115,31 @@ required: allOf: - $ref: ufs-common.yaml + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7180-ufshc + then: + properties: + clocks: + minItems: 7 + maxItems: 7 + clock-names: + items: + - const: core_clk + - const: bus_aggr_clk + - const: iface_clk + - const: core_clk_unipro + - const: ref_clk + - const: tx_lane0_sync_clk + - const: rx_lane0_sync_clk + reg: + maxItems: 1 + reg-names: + maxItems: 1 + - if: properties: compatible: @@ -120,6 +148,7 @@ allOf: - qcom,msm8998-ufshc - qcom,sa8775p-ufshc - qcom,sc7280-ufshc + - qcom,sc8180x-ufshc - qcom,sc8280xp-ufshc - qcom,sm8250-ufshc - qcom,sm8350-ufshc @@ -215,6 +244,7 @@ allOf: contains: enum: - qcom,sm6115-ufshc + - qcom,sm6125-ufshc then: properties: clocks: @@ -248,7 +278,7 @@ allOf: reg: maxItems: 1 clocks: - minItems: 8 + minItems: 7 maxItems: 8 else: properties: @@ -256,7 +286,7 @@ allOf: minItems: 1 maxItems: 2 clocks: - minItems: 8 + minItems: 7 maxItems: 11 unevaluatedProperties: false diff --git a/Bindings/usb/analogix,anx7411.yaml b/Bindings/usb/analogix,anx7411.yaml index e4d893369d5..3f5857aee3b 100644 --- a/Bindings/usb/analogix,anx7411.yaml +++ b/Bindings/usb/analogix,anx7411.yaml @@ -23,24 +23,11 @@ properties: connector: type: object $ref: ../connector/usb-connector.yaml - unevaluatedProperties: false - - description: - Properties for usb c connector. properties: compatible: const: usb-c-connector - power-role: true - - data-role: true - - try-power-role: true - - required: - - compatible - required: - compatible - reg diff --git a/Bindings/usb/ci-hdrc-usb2.yaml b/Bindings/usb/ci-hdrc-usb2.yaml index b7e664f7395..3b56e0edb1c 100644 --- a/Bindings/usb/ci-hdrc-usb2.yaml +++ b/Bindings/usb/ci-hdrc-usb2.yaml @@ -313,7 +313,7 @@ properties: usb-phy: description: phandle for the PHY device. Use "phys" instead. - $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 deprecated: true fsl,usbphy: diff --git a/Bindings/usb/cypress,hx3.yaml b/Bindings/usb/cypress,hx3.yaml index 47add0d85fb..28096619a88 100644 --- a/Bindings/usb/cypress,hx3.yaml +++ b/Bindings/usb/cypress,hx3.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/usb/cypress,hx3.yaml# diff --git a/Bindings/usb/fcs,fsa4480.yaml b/Bindings/usb/fcs,fsa4480.yaml index f9410eb76a6..8b25b9a01ce 100644 --- a/Bindings/usb/fcs,fsa4480.yaml +++ b/Bindings/usb/fcs,fsa4480.yaml @@ -27,13 +27,8 @@ properties: vcc-supply: description: power supply (2.7V-5.5V) - mode-switch: - description: Flag the port as possible handle of altmode switching - type: boolean - - orientation-switch: - description: Flag the port as possible handler of orientation switching - type: boolean + mode-switch: true + orientation-switch: true port: $ref: /schemas/graph.yaml#/$defs/port-base @@ -79,6 +74,9 @@ required: - reg - port +allOf: + - $ref: usb-switch.yaml# + additionalProperties: false examples: diff --git a/Bindings/usb/generic-ehci.yaml b/Bindings/usb/generic-ehci.yaml index 87986c45be8..2ed178f16a7 100644 --- a/Bindings/usb/generic-ehci.yaml +++ b/Bindings/usb/generic-ehci.yaml @@ -77,6 +77,7 @@ properties: - const: usb-ehci - enum: - generic-ehci + - marvell,ac5-ehci - marvell,armada-3700-ehci - marvell,orion-ehci - nuvoton,npcm750-ehci diff --git a/Bindings/usb/gpio-sbu-mux.yaml b/Bindings/usb/gpio-sbu-mux.yaml index d3b2b666ec2..88e1607cf05 100644 --- a/Bindings/usb/gpio-sbu-mux.yaml +++ b/Bindings/usb/gpio-sbu-mux.yaml @@ -33,13 +33,8 @@ properties: vcc-supply: description: power supply - mode-switch: - description: Flag the port as possible handle of altmode switching - type: boolean - - orientation-switch: - description: Flag the port as possible handler of orientation switching - type: boolean + mode-switch: true + orientation-switch: true port: $ref: /schemas/graph.yaml#/properties/port @@ -54,6 +49,9 @@ required: - orientation-switch - port +allOf: + - $ref: usb-switch.yaml# + additionalProperties: false examples: diff --git a/Bindings/usb/hisilicon,hi3798mv200-dwc3.yaml b/Bindings/usb/hisilicon,hi3798mv200-dwc3.yaml new file mode 100644 index 00000000000..f3011694393 --- /dev/null +++ b/Bindings/usb/hisilicon,hi3798mv200-dwc3.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/hisilicon,hi3798mv200-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon Hi3798MV200 DWC3 USB SoC controller + +maintainers: + - Yang Xiwen + +properties: + compatible: + const: hisilicon,hi3798mv200-dwc3 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + ranges: true + + clocks: + items: + - description: Controller bus clock + - description: Controller suspend clock + - description: Controller reference clock + - description: Controller gm clock + - description: Controller gs clock + - description: Controller utmi clock + - description: Controller pipe clock + + clock-names: + items: + - const: bus + - const: suspend + - const: ref + - const: gm + - const: gs + - const: utmi + - const: pipe + + resets: + maxItems: 1 + + reset-names: + const: soft + +patternProperties: + '^usb@[0-9a-f]+$': + $ref: snps,dwc3.yaml# + +required: + - compatible + - ranges + - '#address-cells' + - '#size-cells' + - clocks + - clock-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include + + usb { + compatible = "hisilicon,hi3798mv200-dwc3"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&clk_bus>, + <&clk_suspend>, + <&clk_ref>, + <&clk_gm>, + <&clk_gs>, + <&clk_utmi>, + <&clk_pipe>; + clock-names = "bus", "suspend", "ref", "gm", "gs", "utmi", "pipe"; + resets = <&crg 0xb0 12>; + reset-names = "soft"; + + usb@98a0000 { + compatible = "snps,dwc3"; + reg = <0x98a0000 0x10000>; + interrupts = ; + clocks = <&clk_bus>, + <&clk_suspend>, + <&clk_ref>; + clock-names = "bus_early", "suspend", "ref"; + phys = <&usb2_phy1_port2>, <&combphy0 0>; + phy-names = "usb2-phy", "usb3-phy"; + maximum-speed = "super-speed"; + dr_mode = "host"; + }; + }; diff --git a/Bindings/usb/ite,it5205.yaml b/Bindings/usb/ite,it5205.yaml new file mode 100644 index 00000000000..36ec4251b5f --- /dev/null +++ b/Bindings/usb/ite,it5205.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/ite,it5205.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ITE IT5202 Type-C USB Alternate Mode Passive MUX + +maintainers: + - AngeloGioacchino Del Regno + - Tianping Fang + +properties: + compatible: + const: ite,it5205 + + reg: + maxItems: 1 + + vcc-supply: + description: Power supply for VCC pin (3.3V) + + mode-switch: + description: Flag the port as possible handle of altmode switching + type: boolean + + orientation-switch: + description: Flag the port as possible handler of orientation switching + type: boolean + + ite,ovp-enable: + description: Enable Over Voltage Protection functionality + type: boolean + + port: + $ref: /schemas/graph.yaml#/properties/port + description: + A port node to link the IT5205 to a TypeC controller for the purpose of + handling altmode muxing and orientation switching. + +required: + - compatible + - reg + - orientation-switch + - port + +additionalProperties: false + +examples: + - | + #include + i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + typec-mux@48 { + compatible = "ite,it5205"; + reg = <0x48>; + + mode-switch; + orientation-switch; + + vcc-supply = <&mt6359_vibr_ldo_reg>; + + port { + it5205_usbss_sbu: endpoint { + remote-endpoint = <&typec_controller>; + }; + }; + }; + }; +... diff --git a/Bindings/usb/mediatek,mtu3.yaml b/Bindings/usb/mediatek,mtu3.yaml index a59d91243ac..d4e187c78a0 100644 --- a/Bindings/usb/mediatek,mtu3.yaml +++ b/Bindings/usb/mediatek,mtu3.yaml @@ -185,7 +185,10 @@ properties: 2 - used by mt2712 etc, revision 2 with following IPM rule; 101 - used by mt8183, specific 1.01; 102 - used by mt8192, specific 1.02; - enum: [1, 2, 101, 102] + 103 - used by mt8195, IP0, specific 1.03; + 105 - used by mt8195, IP2, specific 1.05; + 106 - used by mt8195, IP3, specific 1.06; + enum: [1, 2, 101, 102, 103, 105, 106] mediatek,u3p-dis-msk: $ref: /schemas/types.yaml#/definitions/uint32 diff --git a/Bindings/usb/microchip,usb5744.yaml b/Bindings/usb/microchip,usb5744.yaml index 445183d9d6d..e2a72deae77 100644 --- a/Bindings/usb/microchip,usb5744.yaml +++ b/Bindings/usb/microchip,usb5744.yaml @@ -72,8 +72,6 @@ allOf: i2c-bus: false else: $ref: /schemas/usb/usb-device.yaml - required: - - peer-hub additionalProperties: false diff --git a/Bindings/usb/nxp,ptn36502.yaml b/Bindings/usb/nxp,ptn36502.yaml index eee548ac1ab..d805dde8079 100644 --- a/Bindings/usb/nxp,ptn36502.yaml +++ b/Bindings/usb/nxp,ptn36502.yaml @@ -20,13 +20,8 @@ properties: vdd18-supply: description: Power supply for VDD18 pin - retimer-switch: - description: Flag the port as possible handle of SuperSpeed signals retiming - type: boolean - - orientation-switch: - description: Flag the port as possible handler of orientation switching - type: boolean + orientation-switch: true + retimer-switch: true ports: $ref: /schemas/graph.yaml#/properties/ports @@ -49,6 +44,9 @@ required: - compatible - reg +allOf: + - $ref: usb-switch.yaml# + additionalProperties: false examples: diff --git a/Bindings/usb/nxp,ptn5110.yaml b/Bindings/usb/nxp,ptn5110.yaml index eaedb4cc6b6..65a8632b4d9 100644 --- a/Bindings/usb/nxp,ptn5110.yaml +++ b/Bindings/usb/nxp,ptn5110.yaml @@ -11,7 +11,9 @@ maintainers: properties: compatible: - const: nxp,ptn5110 + items: + - const: nxp,ptn5110 + - const: tcpci reg: maxItems: 1 @@ -41,7 +43,7 @@ examples: #size-cells = <0>; tcpci@50 { - compatible = "nxp,ptn5110"; + compatible = "nxp,ptn5110", "tcpci"; reg = <0x50>; interrupt-parent = <&gpio3>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; diff --git a/Bindings/usb/onnn,nb7vpq904m.yaml b/Bindings/usb/onnn,nb7vpq904m.yaml index c0201da002f..589914d22bf 100644 --- a/Bindings/usb/onnn,nb7vpq904m.yaml +++ b/Bindings/usb/onnn,nb7vpq904m.yaml @@ -21,14 +21,8 @@ properties: description: power supply (1.8V) enable-gpios: true - - retimer-switch: - description: Flag the port as possible handle of SuperSpeed signals retiming - type: boolean - - orientation-switch: - description: Flag the port as possible handler of orientation switching - type: boolean + orientation-switch: true + retimer-switch: true ports: $ref: /schemas/graph.yaml#/properties/ports @@ -95,6 +89,9 @@ required: - compatible - reg +allOf: + - $ref: usb-switch.yaml# + additionalProperties: false examples: diff --git a/Bindings/usb/qcom,dwc3.yaml b/Bindings/usb/qcom,dwc3.yaml index 63d150b216c..38a3404ec71 100644 --- a/Bindings/usb/qcom,dwc3.yaml +++ b/Bindings/usb/qcom,dwc3.yaml @@ -102,7 +102,7 @@ properties: description: | Different types of interrupts are used based on HS PHY used on target: - pwr_event: Used for wakeup based on other power events. - - hs_phY_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is + - hs_phy_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is hs_phy_irq which is not triggered by default and its functionality is mutually exclusive to that of {dp/dm}_hs_phy_irq and qusb2_phy_irq. diff --git a/Bindings/usb/qcom,pmic-typec.yaml b/Bindings/usb/qcom,pmic-typec.yaml index 55df3129a0b..d9694570c41 100644 --- a/Bindings/usb/qcom,pmic-typec.yaml +++ b/Bindings/usb/qcom,pmic-typec.yaml @@ -14,8 +14,19 @@ description: properties: compatible: - enum: - - qcom,pm8150b-typec + oneOf: + - enum: + - qcom,pmi632-typec + - qcom,pm8150b-typec + - items: + - enum: + - qcom,pm6150-typec + - const: qcom,pm8150b-typec + - items: + - enum: + - qcom,pm4125-typec + - const: qcom,pmi632-typec + connector: type: object @@ -24,9 +35,11 @@ properties: reg: description: Type-C port and pdphy SPMI register base offsets + minItems: 1 maxItems: 2 interrupts: + minItems: 8 items: - description: Type-C CC attach notification, VBUS error, tCCDebounce done - description: Type-C VCONN powered @@ -46,6 +59,7 @@ properties: - description: Power Domain Fast Role Swap event interrupt-names: + minItems: 8 items: - const: or-rid-detect-change - const: vpd-detect @@ -81,7 +95,33 @@ required: - interrupts - interrupt-names - vdd-vbus-supply - - vdd-pdphy-supply + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,pmi632-typec + then: + properties: + reg: + maxItems: 1 + interrupts: + maxItems: 8 + interrupt-names: + maxItems: 8 + vdd-pdphy-supply: false + else: + properties: + reg: + maxItems: 2 + interrupts: + minItems: 16 + interrupt-names: + maxItems: 16 + required: + - vdd-pdphy-supply additionalProperties: false diff --git a/Bindings/usb/qcom,wcd939x-usbss.yaml b/Bindings/usb/qcom,wcd939x-usbss.yaml index 7ddfd3313a1..96346723f3e 100644 --- a/Bindings/usb/qcom,wcd939x-usbss.yaml +++ b/Bindings/usb/qcom,wcd939x-usbss.yaml @@ -35,13 +35,8 @@ properties: vdd-supply: description: USBSS VDD power supply - mode-switch: - description: Flag the port as possible handle of altmode switching - type: boolean - - orientation-switch: - description: Flag the port as possible handler of orientation switching - type: boolean + mode-switch: true + orientation-switch: true ports: $ref: /schemas/graph.yaml#/properties/ports @@ -63,6 +58,9 @@ required: - reg - ports +allOf: + - $ref: usb-switch.yaml# + additionalProperties: false examples: diff --git a/Bindings/usb/realtek,rts5411.yaml b/Bindings/usb/realtek,rts5411.yaml index f0784d2e86d..0874fc21f66 100644 --- a/Bindings/usb/realtek,rts5411.yaml +++ b/Bindings/usb/realtek,rts5411.yaml @@ -21,6 +21,12 @@ properties: reg: true + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + vdd-supply: description: phandle to the regulator that provides power to the hub. @@ -30,6 +36,36 @@ properties: description: phandle to the peer hub on the controller. + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + 1st downstream facing USB port + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: + 2nd downstream facing USB port + + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: + 3rd downstream facing USB port + + port@4: + $ref: /schemas/graph.yaml#/properties/port + description: + 4th downstream facing USB port + +patternProperties: + '^.*@[1-4]$': + description: The hard wired USB devices + type: object + $ref: /schemas/usb/usb-device.yaml + required: - peer-hub - compatible @@ -50,6 +86,13 @@ examples: reg = <1>; vdd-supply = <&pp3300_hub>; peer-hub = <&hub_3_0>; + #address-cells = <1>; + #size-cells = <0>; + /* USB 2.0 device on port 2 */ + device@2 { + compatible = "usb123,4567"; + reg = <2>; + }; }; /* 3.0 hub on port 2 */ @@ -58,5 +101,17 @@ examples: reg = <2>; vdd-supply = <&pp3300_hub>; peer-hub = <&hub_2_0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + /* Type-A connector on port 4 */ + port@4 { + reg = <4>; + endpoint { + remote-endpoint = <&usb_a0_ss>; + }; + }; + }; }; }; diff --git a/Bindings/usb/ti,am62-usb.yaml b/Bindings/usb/ti,am62-usb.yaml index fec5651f560..f6e6d084d1c 100644 --- a/Bindings/usb/ti,am62-usb.yaml +++ b/Bindings/usb/ti,am62-usb.yaml @@ -14,7 +14,10 @@ properties: const: ti,am62-usb reg: - maxItems: 1 + minItems: 1 + items: + - description: USB CFG register space + - description: USB PHY2 register space ranges: true @@ -82,7 +85,8 @@ examples: usbss1: usb@f910000 { compatible = "ti,am62-usb"; - reg = <0x00 0x0f910000 0x00 0x800>; + reg = <0x00 0x0f910000 0x00 0x800>, + <0x00 0x0f918000 0x00 0x400>; clocks = <&k3_clks 162 3>; clock-names = "ref"; ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>; diff --git a/Bindings/usb/ti,usb8020b.yaml b/Bindings/usb/ti,usb8020b.yaml new file mode 100644 index 00000000000..8ef117793e1 --- /dev/null +++ b/Bindings/usb/ti,usb8020b.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/ti,usb8020b.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI USB8020B USB 3.0 hub controller + +maintainers: + - Macpaul Lin + +allOf: + - $ref: usb-device.yaml# + +properties: + compatible: + enum: + - usb451,8025 + - usb451,8027 + + reg: true + + reset-gpios: + items: + - description: GPIO specifier for GRST# pin. + + vdd-supply: + description: + VDD power supply to the hub + + peer-hub: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the peer hub on the controller. + +required: + - compatible + - reg + - peer-hub + +additionalProperties: false + +examples: + - | + #include + + usb { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb451,8027"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + vdd-supply = <&usb_hub_fixed_3v3>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb451,8025"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + vdd-supply = <&usb_hub_fixed_3v3>; + }; + }; diff --git a/Bindings/usb/usb-nop-xceiv.yaml b/Bindings/usb/usb-nop-xceiv.yaml index 6734f4d3aa7..9b3ea23654a 100644 --- a/Bindings/usb/usb-nop-xceiv.yaml +++ b/Bindings/usb/usb-nop-xceiv.yaml @@ -37,10 +37,11 @@ properties: description: Should specify the GPIO detecting a VBus insertion maxItems: 1 - vbus-regulator: - description: Should specify the regulator supplying current drawn from - the VBus line. - $ref: /schemas/types.yaml#/definitions/phandle + vbus-supply: + description: regulator supplying VBUS. It will be enabled and disabled + dynamically in OTG mode. If the regulator is controlled by a + GPIO line, this should be modeled as a regulator-fixed and + referenced by this supply. wakeup-source: description: @@ -65,7 +66,7 @@ examples: vcc-supply = <&hsusb1_vcc_regulator>; reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; vbus-detect-gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; - vbus-regulator = <&vbus_regulator>; + vbus-supply = <&vbus_regulator>; #phy-cells = <0>; }; diff --git a/Bindings/usb/usb-switch.yaml b/Bindings/usb/usb-switch.yaml new file mode 100644 index 00000000000..da76118e73a --- /dev/null +++ b/Bindings/usb/usb-switch.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/usb-switch.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: USB Orientation and Mode Switches Common Properties + +maintainers: + - Greg Kroah-Hartman + +description: + Common properties for devices handling USB mode and orientation switching. + +properties: + mode-switch: + description: Possible handler of altmode switching + type: boolean + + orientation-switch: + description: Possible handler of orientation switching + type: boolean + + retimer-switch: + description: Possible handler of SuperSpeed signals retiming + type: boolean + + port: + $ref: /schemas/graph.yaml#/properties/port + description: + A port node to link the device to a TypeC controller for the purpose of + handling altmode muxing and orientation switching. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Super Speed (SS) Output endpoint to the Type-C connector + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + description: + Super Speed (SS) Input endpoint from the Super-Speed PHY + unevaluatedProperties: false + + properties: + endpoint: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + unevaluatedProperties: false + properties: + data-lanes: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 8 + uniqueItems: true + items: + maximum: 8 + +oneOf: + - required: + - port + - required: + - ports + +additionalProperties: true diff --git a/Bindings/usb/usb.yaml b/Bindings/usb/usb.yaml index 326b14f05d1..1761b7aa92f 100644 --- a/Bindings/usb/usb.yaml +++ b/Bindings/usb/usb.yaml @@ -25,6 +25,8 @@ properties: usb-phy: $ref: /schemas/types.yaml#/definitions/phandle-array + items: + maxItems: 1 description: List of all the USB PHYs on this HCD to be accepted by the legacy USB Physical Layer subsystem. diff --git a/Bindings/vendor-prefixes.yaml b/Bindings/vendor-prefixes.yaml index 1a0dc04f1db..b97d298b3eb 100644 --- a/Bindings/vendor-prefixes.yaml +++ b/Bindings/vendor-prefixes.yaml @@ -39,6 +39,8 @@ patternProperties: description: ShenZhen Asia Better Technology Ltd. "^acbel,.*": description: Acbel Polytech Inc. + "^acelink,.*": + description: Acelink Technology Co., Ltd. "^acer,.*": description: Acer Inc. "^acme,.*": @@ -61,6 +63,8 @@ patternProperties: description: Analog Devices, Inc. "^adieng,.*": description: ADI Engineering, Inc. + "^admatec,.*": + description: admatec GmbH "^advantech,.*": description: Advantech Corporation "^aeroflexgaisler,.*": @@ -107,6 +111,8 @@ patternProperties: description: Amlogic, Inc. "^ampere,.*": description: Ampere Computing LLC + "^amphenol,.*": + description: Amphenol Advanced Sensors "^ampire,.*": description: Ampire Co., Ltd. "^ams,.*": @@ -159,6 +165,8 @@ patternProperties: description: ASPEED Technology Inc. "^asrock,.*": description: ASRock Inc. + "^asteralabs,.*": + description: Astera Labs, Inc. "^asus,.*": description: AsusTek Computer Inc. "^atheros,.*": @@ -230,6 +238,8 @@ patternProperties: description: ByteDance Ltd. "^calamp,.*": description: CalAmp Corp. + "^calao,.*": + description: CALAO Systems SAS "^calaosystems,.*": description: CALAO Systems SAS "^calxeda,.*": @@ -478,6 +488,9 @@ patternProperties: description: EZchip Semiconductor "^facebook,.*": description: Facebook + "^fairchild,.*": + description: Fairchild Semiconductor (deprecated, use 'onnn') + deprecated: true "^fairphone,.*": description: Fairphone B.V. "^faraday,.*": @@ -500,6 +513,8 @@ patternProperties: description: FocalTech Systems Co.,Ltd "^forlinx,.*": description: Baoding Forlinx Embedded Technology Co., Ltd. + "^freebox,.*": + description: Freebox SAS "^freecom,.*": description: Freecom Gmbh "^frida,.*": @@ -542,6 +557,8 @@ patternProperties: description: Giantec Semiconductor, Inc. "^giantplus,.*": description: Giantplus Technology Co., Ltd. + "^glinet,.*": + description: GL Intelligence, Inc. "^globalscale,.*": description: Globalscale Technologies, Inc. "^globaltop,.*": @@ -601,6 +618,8 @@ patternProperties: description: Honestar Technologies Co., Ltd. "^honeywell,.*": description: Honeywell + "^hoperf,.*": + description: Shenzhen Hope Microelectronics Co., Ltd. "^hoperun,.*": description: Jiangsu HopeRun Software Co., Ltd. "^hp,.*": @@ -631,12 +650,16 @@ patternProperties: description: Hyundai Technology "^i2se,.*": description: I2SE GmbH + "^IBM,.*": + description: International Business Machines (IBM) "^ibm,.*": description: International Business Machines (IBM) "^icplus,.*": description: IC Plus Corp. "^idt,.*": description: Integrated Device Technologies, Inc. + "^iei,.*": + description: IEI Integration Corp. "^ifi,.*": description: Ingenieurburo Fur Ic-Technologie (I/F/I) "^ilitek,.*": @@ -719,6 +742,8 @@ patternProperties: description: JetHome (IP Sokolov P.A.) "^jianda,.*": description: Jiandangjing Technology Co., Ltd. + "^jide,.*": + description: Jide Tech "^joz,.*": description: JOZ BV "^kam,.*": @@ -821,6 +846,8 @@ patternProperties: description: LSI Corp. (LSI Logic) "^lunzn,.*": description: Shenzhen Lunzn Technology Co., Ltd. + "^luxul,.*": + description: Lagrand | AV "^lwn,.*": description: Liebherr-Werk Nenzing GmbH "^lxa,.*": @@ -899,6 +926,9 @@ patternProperties: description: Miniand Tech "^minix,.*": description: MINIX Technology Ltd. + "^mips,.*": + description: MIPS Technology (deprecated, use 'mti' or 'img') + deprecated: true "^miramems,.*": description: MiraMEMS Sensing Technology Co., Ltd. "^mitsubishi,.*": @@ -911,6 +941,8 @@ patternProperties: description: Miyoo "^mntre,.*": description: MNT Research GmbH + "^mobileye,.*": + description: Mobileye Vision Technologies Ltd. "^modtronix,.*": description: Modtronix Engineering "^moortec,.*": @@ -993,6 +1025,9 @@ patternProperties: description: Novatek "^novtech,.*": description: NovTech, Inc. + "^numonyx,.*": + description: Numonyx (deprecated, use micron) + deprecated: true "^nutsboard,.*": description: NutsBoard "^nuvoton,.*": @@ -1297,6 +1332,8 @@ patternProperties: description: Skyworks Solutions, Inc. "^smartlabs,.*": description: SmartLabs LLC + "^smartrg,.*": + description: SmartRG, Inc. "^smi,.*": description: Silicon Motion Technology Corporation "^smsc,.*": @@ -1484,6 +1521,8 @@ patternProperties: description: Ufi Space Co., Ltd. "^ugoos,.*": description: Ugoos Industrial Co., Ltd. + "^uni-t,.*": + description: Uni-Trend Technology (China) Co., Ltd. "^uniwest,.*": description: United Western Technologies Corp (UniWest) "^upisemi,.*": @@ -1534,10 +1573,16 @@ patternProperties: description: VoCore Studio "^voipac,.*": description: Voipac Technologies s.r.o. + "^voltafield,.*": + description: Voltafield Technology Corp. "^vot,.*": description: Vision Optical Technology Co., Ltd. + "^vscom,.*": + description: VS Visions Systems GmbH "^vxt,.*": description: VXT Ltd + "^wacom,.*": + description: Wacom "^wanchanglong,.*": description: Wanchanglong Electronics Technology（SHENZHEN）Co.，Ltd. "^wand,.*": diff --git a/Bindings/w1/w1-uart.yaml b/Bindings/w1/w1-uart.yaml new file mode 100644 index 00000000000..bd7c62d780b --- /dev/null +++ b/Bindings/w1/w1-uart.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/w1/w1-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UART 1-Wire Bus + +maintainers: + - Christoph Winklhofer + +description: | + UART 1-wire bus. Utilizes the UART interface via the Serial Device Bus + to create the 1-Wire timing patterns. + + The UART peripheral must support full-duplex and operate in open-drain + mode. The timing patterns are generated by a specific combination of + baud-rate and transmitted byte, which corresponds to a 1-Wire read bit, + write bit or reset pulse. + + The default baud-rate for reset and presence detection is 9600 and for + a 1-Wire read or write operation 115200. In case the actual baud-rate + is different from the requested one, the transmitted byte is adapted + to generate the 1-Wire timing patterns. + + https://www.analog.com/en/technical-articles/using-a-uart-to-implement-a-1wire-bus-master.html + +properties: + compatible: + const: w1-uart + + reset-bps: + default: 9600 + description: + The baud rate for the 1-Wire reset and presence detect. + + write-0-bps: + default: 115200 + description: + The baud rate for the 1-Wire write-0 cycle. + + write-1-bps: + default: 115200 + description: + The baud rate for the 1-Wire write-1 and read cycle. + +required: + - compatible + +additionalProperties: + type: object + +examples: + - | + serial { + onewire { + compatible = "w1-uart"; + }; + }; diff --git a/Bindings/watchdog/arm,sp805.yaml b/Bindings/watchdog/arm,sp805.yaml index 7aea255b301..bd7c09ed193 100644 --- a/Bindings/watchdog/arm,sp805.yaml +++ b/Bindings/watchdog/arm,sp805.yaml @@ -50,6 +50,10 @@ properties: - const: wdog_clk - const: apb_pclk + resets: + maxItems: 1 + description: WDOGRESn input reset signal for sp805 module. + required: - compatible - reg @@ -67,4 +71,5 @@ examples: interrupts = ; clocks = <&wdt_clk>, <&apb_pclk>; clock-names = "wdog_clk", "apb_pclk"; + resets = <&wdt_rst>; }; diff --git a/Bindings/watchdog/atmel,sama5d4-wdt.yaml b/Bindings/watchdog/atmel,sama5d4-wdt.yaml index 816f85ee2c7..cdf87db3618 100644 --- a/Bindings/watchdog/atmel,sama5d4-wdt.yaml +++ b/Bindings/watchdog/atmel,sama5d4-wdt.yaml @@ -14,10 +14,14 @@ allOf: properties: compatible: - enum: - - atmel,sama5d4-wdt - - microchip,sam9x60-wdt - - microchip,sama7g5-wdt + oneOf: + - enum: + - atmel,sama5d4-wdt + - microchip,sam9x60-wdt + - microchip,sama7g5-wdt + - items: + - const: microchip,sam9x7-wdt + - const: microchip,sam9x60-wdt reg: maxItems: 1 diff --git a/Bindings/watchdog/brcm,bcm2835-pm-wdog.txt b/Bindings/watchdog/brcm,bcm2835-pm-wdog.txt deleted file mode 100644 index f801d71de1c..00000000000 --- a/Bindings/watchdog/brcm,bcm2835-pm-wdog.txt +++ /dev/null @@ -1,18 +0,0 @@ -BCM2835 Watchdog timer - -Required properties: - -- compatible : should be "brcm,bcm2835-pm-wdt" -- reg : Specifies base physical address and size of the registers. - -Optional properties: - -- timeout-sec : Contains the watchdog timeout in seconds - -Example: - -watchdog { - compatible = "brcm,bcm2835-pm-wdt"; - reg = <0x7e100000 0x28>; - timeout-sec = <10>; -}; diff --git a/Bindings/watchdog/qcom-wdt.yaml b/Bindings/watchdog/qcom-wdt.yaml index a4f35c598cd..47587971fb0 100644 --- a/Bindings/watchdog/qcom-wdt.yaml +++ b/Bindings/watchdog/qcom-wdt.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Krait Processor Sub-system (KPSS) Watchdog timer maintainers: - - Sai Prakash Ranjan + - Rajendra Nayak properties: $nodename: diff --git a/Bindings/watchdog/renesas,wdt.yaml b/Bindings/watchdog/renesas,wdt.yaml index 951a7d54135..ffb17add491 100644 --- a/Bindings/watchdog/renesas,wdt.yaml +++ b/Bindings/watchdog/renesas,wdt.yaml @@ -71,6 +71,7 @@ properties: - renesas,r8a779a0-wdt # R-Car V3U - renesas,r8a779f0-wdt # R-Car S4-8 - renesas,r8a779g0-wdt # R-Car V4H + - renesas,r8a779h0-wdt # R-Car V4M - const: renesas,rcar-gen4-wdt # R-Car Gen4 reg: diff --git a/Bindings/watchdog/sprd,sp9860-wdt.yaml b/Bindings/watchdog/sprd,sp9860-wdt.yaml new file mode 100644 index 00000000000..730d9a3a3cc --- /dev/null +++ b/Bindings/watchdog/sprd,sp9860-wdt.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/sprd,sp9860-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Spreadtrum SP9860 watchdog timer + +maintainers: + - Orson Zhai + - Baolin Wang + - Chunyan Zhang + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + const: sprd,sp9860-wdt + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: enable + - const: rtc_enable + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - timeout-sec + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + watchdog@40310000 { + compatible = "sprd,sp9860-wdt"; + reg = <0 0x40310000 0 0x1000>; + interrupts = ; + clocks = <&aon_gate CLK_APCPU_WDG_EB>, <&aon_gate CLK_AP_WDG_RTC_EB>; + clock-names = "enable", "rtc_enable"; + timeout-sec = <12>; + }; + }; +... diff --git a/Bindings/watchdog/sprd-wdt.txt b/Bindings/watchdog/sprd-wdt.txt deleted file mode 100644 index aeaf3e0caf4..00000000000 --- a/Bindings/watchdog/sprd-wdt.txt +++ /dev/null @@ -1,19 +0,0 @@ -Spreadtrum SoCs Watchdog timer - -Required properties: -- compatible : Should be "sprd,sp9860-wdt". -- reg : Specifies base physical address and size of the registers. -- interrupts : Exactly one interrupt specifier. -- timeout-sec : Contain the default watchdog timeout in seconds. -- clock-names : Contain the input clock names. -- clocks : Phandles to input clocks. - -Example: - watchdog: watchdog@40310000 { - compatible = "sprd,sp9860-wdt"; - reg = <0 0x40310000 0 0x1000>; - interrupts = ; - timeout-sec = <12>; - clock-names = "enable", "rtc_enable"; - clocks = <&clk_aon_apb_gates1 8>, <&clk_aon_apb_rtc_gates 9>; - }; diff --git a/Bindings/watchdog/starfive,jh7100-wdt.yaml b/Bindings/watchdog/starfive,jh7100-wdt.yaml index 68f3f6fd08a..e21f807b0b6 100644 --- a/Bindings/watchdog/starfive,jh7100-wdt.yaml +++ b/Bindings/watchdog/starfive,jh7100-wdt.yaml @@ -19,14 +19,16 @@ description: isn't cleared, the watchdog will reset the system unless the watchdog reset is disabled. -allOf: - - $ref: watchdog.yaml# - properties: compatible: - enum: - - starfive,jh7100-wdt - - starfive,jh7110-wdt + oneOf: + - enum: + - starfive,jh7100-wdt + - starfive,jh7110-wdt + - items: + - enum: + - starfive,jh8100-wdt + - const: starfive,jh7110-wdt reg: maxItems: 1 @@ -45,9 +47,8 @@ properties: - const: core resets: - items: - - description: APB reset - - description: Core reset + minItems: 1 + maxItems: 2 required: - compatible @@ -56,6 +57,27 @@ required: - clock-names - resets +allOf: + - $ref: watchdog.yaml# + + - if: + properties: + compatible: + contains: + enum: + - starfive,jh8100-wdt + then: + properties: + resets: + items: + - description: Core reset + else: + properties: + resets: + items: + - description: APB reset + - description: Core reset + unevaluatedProperties: false examples: diff --git a/Bindings/writing-schema.rst b/Bindings/writing-schema.rst index 0a6cf19a145..7e71cdd1d6d 100644 --- a/Bindings/writing-schema.rst +++ b/Bindings/writing-schema.rst @@ -31,7 +31,7 @@ $schema Indicates the meta-schema the schema file adheres to. title - A one-line description on the contents of the binding schema. + A one-line description of the hardware being described in the binding schema. maintainers A DT specific property. Contains a list of email address(es) @@ -39,7 +39,7 @@ maintainers description Optional. A multi-line text block containing any detailed - information about this binding. It should contain things such as what the block + information about this hardware. It should contain things such as what the block or device does, standards the device conforms to, and links to datasheets for more information. @@ -71,9 +71,31 @@ required A list of DT properties from the 'properties' section that must always be present. +additionalProperties / unevaluatedProperties + Keywords controlling how schema will validate properties not matched by this + schema's 'properties' or 'patternProperties'. Each schema is supposed to + have exactly one of these keywords in top-level part, so either + additionalProperties or unevaluatedProperties. Nested nodes, so properties + being objects, are supposed to have one as well. + + * additionalProperties: false + Most common case, where no additional schema is referenced or if this + binding allows subset of properties from other referenced schemas. + + * unevaluatedProperties: false + Used when this binding references other schema whose all properties + should be allowed. + + * additionalProperties: true + Rare case, used for schemas implementing common set of properties. Such + schemas are supposed to be referenced by other schemas, which then use + 'unevaluatedProperties: false'. Typically bus or common-part schemas. + examples - Optional. A list of one or more DTS hunks implementing the - binding. Note: YAML doesn't allow leading tabs, so spaces must be used instead. + Optional. A list of one or more DTS hunks implementing this binding only. + Example should not contain unrelated device nodes, e.g. consumer nodes in a + provider binding, other nodes referenced by phandle. + Note: YAML doesn't allow leading tabs, so spaces must be used instead. Unless noted otherwise, all properties are required. diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index 51e0f605941..19ac7b36f60 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -252,8 +252,11 @@ #define QCOM_ID_IPQ9510 521 #define QCOM_ID_QRB4210 523 #define QCOM_ID_QRB2210 524 +#define QCOM_ID_SM8475 530 +#define QCOM_ID_SM8475P 531 #define QCOM_ID_SA8775P 534 #define QCOM_ID_QRU1000 539 +#define QCOM_ID_SM8475_2 540 #define QCOM_ID_QDU1000 545 #define QCOM_ID_SM8650 557 #define QCOM_ID_SM4450 568 @@ -265,6 +268,8 @@ #define QCOM_ID_IPQ5322 593 #define QCOM_ID_IPQ5312 594 #define QCOM_ID_IPQ5302 595 +#define QCOM_ID_QCS8550 603 +#define QCOM_ID_QCM8550 604 #define QCOM_ID_IPQ5300 624 /* diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h index 712782177c9..7ae96c7bd72 100644 --- a/include/dt-bindings/clock/ast2600-clock.h +++ b/include/dt-bindings/clock/ast2600-clock.h @@ -86,6 +86,7 @@ #define ASPEED_CLK_MAC3RCLK 69 #define ASPEED_CLK_MAC4RCLK 70 #define ASPEED_CLK_I3C 71 +#define ASPEED_CLK_FSI 72 /* Only list resets here that are not part of a clock gate + reset pair */ #define ASPEED_RESET_ADC 55 diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h index 3090e09c9a5..7666241520f 100644 --- a/include/dt-bindings/clock/exynos850.h +++ b/include/dt-bindings/clock/exynos850.h @@ -88,6 +88,18 @@ #define CLK_MOUT_G3D_SWITCH 76 #define CLK_GOUT_G3D_SWITCH 77 #define CLK_DOUT_G3D_SWITCH 78 +#define CLK_MOUT_CPUCL0_DBG 79 +#define CLK_MOUT_CPUCL0_SWITCH 80 +#define CLK_GOUT_CPUCL0_DBG 81 +#define CLK_GOUT_CPUCL0_SWITCH 82 +#define CLK_DOUT_CPUCL0_DBG 83 +#define CLK_DOUT_CPUCL0_SWITCH 84 +#define CLK_MOUT_CPUCL1_DBG 85 +#define CLK_MOUT_CPUCL1_SWITCH 86 +#define CLK_GOUT_CPUCL1_DBG 87 +#define CLK_GOUT_CPUCL1_SWITCH 88 +#define CLK_DOUT_CPUCL1_DBG 89 +#define CLK_DOUT_CPUCL1_SWITCH 90 /* CMU_APM */ #define CLK_RCO_I3C_PMIC 1 @@ -195,6 +207,48 @@ #define CLK_GOUT_CMGP_USI1_PCLK 14 #define CLK_GOUT_SYSREG_CMGP_PCLK 15 +/* CMU_CPUCL0 */ +#define CLK_FOUT_CPUCL0_PLL 1 +#define CLK_MOUT_PLL_CPUCL0 2 +#define CLK_MOUT_CPUCL0_SWITCH_USER 3 +#define CLK_MOUT_CPUCL0_DBG_USER 4 +#define CLK_MOUT_CPUCL0_PLL 5 +#define CLK_DOUT_CPUCL0_CPU 6 +#define CLK_DOUT_CPUCL0_CMUREF 7 +#define CLK_DOUT_CPUCL0_PCLK 8 +#define CLK_DOUT_CLUSTER0_ACLK 9 +#define CLK_DOUT_CLUSTER0_ATCLK 10 +#define CLK_DOUT_CLUSTER0_PCLKDBG 11 +#define CLK_DOUT_CLUSTER0_PERIPHCLK 12 +#define CLK_GOUT_CLUSTER0_ATCLK 13 +#define CLK_GOUT_CLUSTER0_PCLK 14 +#define CLK_GOUT_CLUSTER0_PERIPHCLK 15 +#define CLK_GOUT_CLUSTER0_SCLK 16 +#define CLK_GOUT_CPUCL0_CMU_CPUCL0_PCLK 17 +#define CLK_GOUT_CLUSTER0_CPU 18 +#define CLK_CLUSTER0_SCLK 19 + +/* CMU_CPUCL1 */ +#define CLK_FOUT_CPUCL1_PLL 1 +#define CLK_MOUT_PLL_CPUCL1 2 +#define CLK_MOUT_CPUCL1_SWITCH_USER 3 +#define CLK_MOUT_CPUCL1_DBG_USER 4 +#define CLK_MOUT_CPUCL1_PLL 5 +#define CLK_DOUT_CPUCL1_CPU 6 +#define CLK_DOUT_CPUCL1_CMUREF 7 +#define CLK_DOUT_CPUCL1_PCLK 8 +#define CLK_DOUT_CLUSTER1_ACLK 9 +#define CLK_DOUT_CLUSTER1_ATCLK 10 +#define CLK_DOUT_CLUSTER1_PCLKDBG 11 +#define CLK_DOUT_CLUSTER1_PERIPHCLK 12 +#define CLK_GOUT_CLUSTER1_ATCLK 13 +#define CLK_GOUT_CLUSTER1_PCLK 14 +#define CLK_GOUT_CLUSTER1_PERIPHCLK 15 +#define CLK_GOUT_CLUSTER1_SCLK 16 +#define CLK_GOUT_CPUCL1_CMU_CPUCL1_PCLK 17 +#define CLK_GOUT_CLUSTER1_CPU 18 +#define CLK_CLUSTER1_SCLK 19 + /* CMU_G3D */ #define CLK_FOUT_G3D_PLL 1 #define CLK_MOUT_G3D_PLL 2 @@ -320,6 +374,8 @@ #define CLK_GOUT_SSS_PCLK 12 #define CLK_GOUT_GPIO_CORE_PCLK 13 #define CLK_GOUT_SYSREG_CORE_PCLK 14 +#define CLK_GOUT_PDMA_CORE_ACLK 15 +#define CLK_GOUT_SPDMA_CORE_ACLK 16 /* CMU_DPU */ #define CLK_MOUT_DPU_USER 1 diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h index 21adec22387..3dac3577788 100644 --- a/include/dt-bindings/clock/google,gs101.h +++ b/include/dt-bindings/clock/google,gs101.h @@ -389,4 +389,133 @@ #define CLK_GOUT_MISC_WDT_CLUSTER1_PCLK 73 #define CLK_GOUT_MISC_XIU_D_MISC_ACLK 74 +/* CMU_PERIC0 */ +#define CLK_MOUT_PERIC0_BUS_USER 1 +#define CLK_MOUT_PERIC0_I3C_USER 2 +#define CLK_MOUT_PERIC0_USI0_UART_USER 3 +#define CLK_MOUT_PERIC0_USI14_USI_USER 4 +#define CLK_MOUT_PERIC0_USI1_USI_USER 5 +#define CLK_MOUT_PERIC0_USI2_USI_USER 6 +#define CLK_MOUT_PERIC0_USI3_USI_USER 7 +#define CLK_MOUT_PERIC0_USI4_USI_USER 8 +#define CLK_MOUT_PERIC0_USI5_USI_USER 9 +#define CLK_MOUT_PERIC0_USI6_USI_USER 10 +#define CLK_MOUT_PERIC0_USI7_USI_USER 11 +#define CLK_MOUT_PERIC0_USI8_USI_USER 12 +#define CLK_DOUT_PERIC0_I3C 13 +#define CLK_DOUT_PERIC0_USI0_UART 14 +#define CLK_DOUT_PERIC0_USI14_USI 15 +#define CLK_DOUT_PERIC0_USI1_USI 16 +#define CLK_DOUT_PERIC0_USI2_USI 17 +#define CLK_DOUT_PERIC0_USI3_USI 18 +#define CLK_DOUT_PERIC0_USI4_USI 19 +#define CLK_DOUT_PERIC0_USI5_USI 20 +#define CLK_DOUT_PERIC0_USI6_USI 21 +#define CLK_DOUT_PERIC0_USI7_USI 22 +#define CLK_DOUT_PERIC0_USI8_USI 23 +#define CLK_GOUT_PERIC0_IP 24 +#define CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK 25 +#define CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK 26 +#define CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK 27 +#define CLK_GOUT_PERIC0_GPC_PERIC0_PCLK 28 +#define CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK 29 +#define CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK 30 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0 31 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1 32 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10 33 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11 34 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12 35 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13 36 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14 37 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15 38 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2 39 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3 40 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4 41 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5 42 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6 43 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7 44 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8 45 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9 46 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0 47 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1 48 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10 49 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11 50 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12 51 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13 52 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14 53 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15 54 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2 55 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3 56 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4 57 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5 58 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6 59 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7 60 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8 61 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9 62 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0 63 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2 64 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0 65 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2 66 +#define CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK 67 +#define CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK 68 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK 69 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK 70 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK 71 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CLK 72 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CLK 73 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CLK 74 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CLK 75 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CLK 76 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CLK 77 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK 78 +#define CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK 79 + +/* CMU_PERIC1 */ +#define CLK_MOUT_PERIC1_BUS_USER 1 +#define CLK_MOUT_PERIC1_I3C_USER 2 +#define CLK_MOUT_PERIC1_USI0_USI_USER 3 +#define CLK_MOUT_PERIC1_USI10_USI_USER 4 +#define CLK_MOUT_PERIC1_USI11_USI_USER 5 +#define CLK_MOUT_PERIC1_USI12_USI_USER 6 +#define CLK_MOUT_PERIC1_USI13_USI_USER 7 +#define CLK_MOUT_PERIC1_USI9_USI_USER 8 +#define CLK_DOUT_PERIC1_I3C 9 +#define CLK_DOUT_PERIC1_USI0_USI 10 +#define CLK_DOUT_PERIC1_USI10_USI 11 +#define CLK_DOUT_PERIC1_USI11_USI 12 +#define CLK_DOUT_PERIC1_USI12_USI 13 +#define CLK_DOUT_PERIC1_USI13_USI 14 +#define CLK_DOUT_PERIC1_USI9_USI 15 +#define CLK_GOUT_PERIC1_IP 16 +#define CLK_GOUT_PERIC1_PCLK 17 +#define CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK 18 +#define CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK 19 +#define CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK 20 +#define CLK_GOUT_PERIC1_GPC_PERIC1_PCLK 21 +#define CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK 22 +#define CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK 23 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1 24 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2 25 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3 26 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4 27 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5 28 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6 29 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8 30 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1 31 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15 32 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2 33 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3 34 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4 35 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5 36 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6 37 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8 38 +#define CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK 39 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK 40 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK 41 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK 42 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK 43 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK 44 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK 45 +#define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 46 + #endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */ diff --git a/include/dt-bindings/clock/microchip,mpfs-clock.h b/include/dt-bindings/clock/microchip,mpfs-clock.h index 79775a5134c..b52f19a2b48 100644 --- a/include/dt-bindings/clock/microchip,mpfs-clock.h +++ b/include/dt-bindings/clock/microchip,mpfs-clock.h @@ -44,6 +44,11 @@ #define CLK_RTCREF 33 #define CLK_MSSPLL 34 +#define CLK_MSSPLL0 34 +#define CLK_MSSPLL1 35 +#define CLK_MSSPLL2 36 +#define CLK_MSSPLL3 37 +/* 38 is reserved for MSS PLL internals */ /* Clock Conditioning Circuitry Clock IDs */ diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bindings/clock/mobileye,eyeq5-clk.h new file mode 100644 index 00000000000..26d8930335e --- /dev/null +++ b/include/dt-bindings/clock/mobileye,eyeq5-clk.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2024 Mobileye Vision Technologies Ltd. + */ + +#ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H +#define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H + +#define EQ5C_PLL_CPU 0 +#define EQ5C_PLL_VMP 1 +#define EQ5C_PLL_PMA 2 +#define EQ5C_PLL_VDI 3 +#define EQ5C_PLL_DDR0 4 +#define EQ5C_PLL_PCI 5 +#define EQ5C_PLL_PER 6 +#define EQ5C_PLL_PMAC 7 +#define EQ5C_PLL_MPC 8 +#define EQ5C_PLL_DDR1 9 + +#define EQ5C_DIV_OSPI 10 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-msm8953.h b/include/dt-bindings/clock/qcom,gcc-msm8953.h index 783162da614..13b4a62877e 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8953.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8953.h @@ -218,6 +218,10 @@ #define GCC_USB3PHY_PHY_BCR 3 #define GCC_USB3_PHY_BCR 4 #define GCC_USB_30_BCR 5 +#define GCC_MDSS_BCR 6 +#define GCC_CRYPTO_BCR 7 +#define GCC_SDCC1_BCR 8 +#define GCC_SDCC2_BCR 9 /* GDSCs */ #define CPP_GDSC 0 diff --git a/include/dt-bindings/clock/qcom,gcc-sc8180x.h b/include/dt-bindings/clock/qcom,gcc-sc8180x.h index e893415ae13..90c6e021a03 100644 --- a/include/dt-bindings/clock/qcom,gcc-sc8180x.h +++ b/include/dt-bindings/clock/qcom,gcc-sc8180x.h @@ -246,6 +246,8 @@ #define GCC_PCIE_3_CLKREF_CLK 236 #define GCC_USB3_PRIM_CLKREF_CLK 237 #define GCC_USB3_SEC_CLKREF_CLK 238 +#define GCC_UFS_MEM_CLKREF_EN 239 +#define GCC_UFS_CARD_CLKREF_EN 240 #define GCC_EMAC_BCR 0 #define GCC_GPU_BCR 1 diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h index dfefd5e8bf6..921a33f24d3 100644 --- a/include/dt-bindings/clock/qcom,gcc-sm8150.h +++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h @@ -239,6 +239,9 @@ #define GCC_USB30_PRIM_BCR 26 #define GCC_USB30_SEC_BCR 27 #define GCC_USB_PHY_CFG_AHB2PHY_BCR 28 +#define GCC_VIDEO_AXIC_CLK_BCR 29 +#define GCC_VIDEO_AXI0_CLK_BCR 30 +#define GCC_VIDEO_AXI1_CLK_BCR 31 /* GCC GDSCRs */ #define PCIE_0_GDSC 0 diff --git a/include/dt-bindings/clock/qcom,x1e80100-camcc.h b/include/dt-bindings/clock/qcom,x1e80100-camcc.h new file mode 100644 index 00000000000..d72fdfb06a7 --- /dev/null +++ b/include/dt-bindings/clock/qcom,x1e80100-camcc.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_X1E80100_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_X1E80100_H + +/* CAM_CC clocks */ +#define CAM_CC_BPS_AHB_CLK 0 +#define CAM_CC_BPS_CLK 1 +#define CAM_CC_BPS_CLK_SRC 2 +#define CAM_CC_BPS_FAST_AHB_CLK 3 +#define CAM_CC_CAMNOC_AXI_NRT_CLK 4 +#define CAM_CC_CAMNOC_AXI_RT_CLK 5 +#define CAM_CC_CAMNOC_AXI_RT_CLK_SRC 6 +#define CAM_CC_CAMNOC_DCD_XO_CLK 7 +#define CAM_CC_CAMNOC_XO_CLK 8 +#define CAM_CC_CCI_0_CLK 9 +#define CAM_CC_CCI_0_CLK_SRC 10 +#define CAM_CC_CCI_1_CLK 11 +#define CAM_CC_CCI_1_CLK_SRC 12 +#define CAM_CC_CORE_AHB_CLK 13 +#define CAM_CC_CPAS_AHB_CLK 14 +#define CAM_CC_CPAS_BPS_CLK 15 +#define CAM_CC_CPAS_FAST_AHB_CLK 16 +#define CAM_CC_CPAS_IFE_0_CLK 17 +#define CAM_CC_CPAS_IFE_1_CLK 18 +#define CAM_CC_CPAS_IFE_LITE_CLK 19 +#define CAM_CC_CPAS_IPE_NPS_CLK 20 +#define CAM_CC_CPAS_SFE_0_CLK 21 +#define CAM_CC_CPHY_RX_CLK_SRC 22 +#define CAM_CC_CSI0PHYTIMER_CLK 23 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 24 +#define CAM_CC_CSI1PHYTIMER_CLK 25 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 26 +#define CAM_CC_CSI2PHYTIMER_CLK 27 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 28 +#define CAM_CC_CSI3PHYTIMER_CLK 29 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 30 +#define CAM_CC_CSI4PHYTIMER_CLK 31 +#define CAM_CC_CSI4PHYTIMER_CLK_SRC 32 +#define CAM_CC_CSI5PHYTIMER_CLK 33 +#define CAM_CC_CSI5PHYTIMER_CLK_SRC 34 +#define CAM_CC_CSID_CLK 35 +#define CAM_CC_CSID_CLK_SRC 36 +#define CAM_CC_CSID_CSIPHY_RX_CLK 37 +#define CAM_CC_CSIPHY0_CLK 38 +#define CAM_CC_CSIPHY1_CLK 39 +#define CAM_CC_CSIPHY2_CLK 40 +#define CAM_CC_CSIPHY3_CLK 41 +#define CAM_CC_CSIPHY4_CLK 42 +#define CAM_CC_CSIPHY5_CLK 43 +#define CAM_CC_FAST_AHB_CLK_SRC 44 +#define CAM_CC_GDSC_CLK 45 +#define CAM_CC_ICP_AHB_CLK 46 +#define CAM_CC_ICP_CLK 47 +#define CAM_CC_ICP_CLK_SRC 48 +#define CAM_CC_IFE_0_CLK 49 +#define CAM_CC_IFE_0_CLK_SRC 50 +#define CAM_CC_IFE_0_DSP_CLK 51 +#define CAM_CC_IFE_0_FAST_AHB_CLK 52 +#define CAM_CC_IFE_1_CLK 53 +#define CAM_CC_IFE_1_CLK_SRC 54 +#define CAM_CC_IFE_1_DSP_CLK 55 +#define CAM_CC_IFE_1_FAST_AHB_CLK 56 +#define CAM_CC_IFE_LITE_AHB_CLK 57 +#define CAM_CC_IFE_LITE_CLK 58 +#define CAM_CC_IFE_LITE_CLK_SRC 59 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 60 +#define CAM_CC_IFE_LITE_CSID_CLK 61 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 62 +#define CAM_CC_IPE_NPS_AHB_CLK 63 +#define CAM_CC_IPE_NPS_CLK 64 +#define CAM_CC_IPE_NPS_CLK_SRC 65 +#define CAM_CC_IPE_NPS_FAST_AHB_CLK 66 +#define CAM_CC_IPE_PPS_CLK 67 +#define CAM_CC_IPE_PPS_FAST_AHB_CLK 68 +#define CAM_CC_JPEG_CLK 69 +#define CAM_CC_JPEG_CLK_SRC 70 +#define CAM_CC_MCLK0_CLK 71 +#define CAM_CC_MCLK0_CLK_SRC 72 +#define CAM_CC_MCLK1_CLK 73 +#define CAM_CC_MCLK1_CLK_SRC 74 +#define CAM_CC_MCLK2_CLK 75 +#define CAM_CC_MCLK2_CLK_SRC 76 +#define CAM_CC_MCLK3_CLK 77 +#define CAM_CC_MCLK3_CLK_SRC 78 +#define CAM_CC_MCLK4_CLK 79 +#define CAM_CC_MCLK4_CLK_SRC 80 +#define CAM_CC_MCLK5_CLK 81 +#define CAM_CC_MCLK5_CLK_SRC 82 +#define CAM_CC_MCLK6_CLK 83 +#define CAM_CC_MCLK6_CLK_SRC 84 +#define CAM_CC_MCLK7_CLK 85 +#define CAM_CC_MCLK7_CLK_SRC 86 +#define CAM_CC_PLL0 87 +#define CAM_CC_PLL0_OUT_EVEN 88 +#define CAM_CC_PLL0_OUT_ODD 89 +#define CAM_CC_PLL1 90 +#define CAM_CC_PLL1_OUT_EVEN 91 +#define CAM_CC_PLL2 92 +#define CAM_CC_PLL3 93 +#define CAM_CC_PLL3_OUT_EVEN 94 +#define CAM_CC_PLL4 95 +#define CAM_CC_PLL4_OUT_EVEN 96 +#define CAM_CC_PLL6 97 +#define CAM_CC_PLL6_OUT_EVEN 98 +#define CAM_CC_PLL8 99 +#define CAM_CC_PLL8_OUT_EVEN 100 +#define CAM_CC_SFE_0_CLK 101 +#define CAM_CC_SFE_0_CLK_SRC 102 +#define CAM_CC_SFE_0_FAST_AHB_CLK 103 +#define CAM_CC_SLEEP_CLK 104 +#define CAM_CC_SLEEP_CLK_SRC 105 +#define CAM_CC_SLOW_AHB_CLK_SRC 106 +#define CAM_CC_XO_CLK_SRC 107 + +/* CAM_CC power domains */ +#define CAM_CC_BPS_GDSC 0 +#define CAM_CC_IFE_0_GDSC 1 +#define CAM_CC_IFE_1_GDSC 2 +#define CAM_CC_IPE_0_GDSC 3 +#define CAM_CC_SFE_0_GDSC 4 +#define CAM_CC_TITAN_TOP_GDSC 5 + +/* CAM_CC resets */ +#define CAM_CC_BPS_BCR 0 +#define CAM_CC_ICP_BCR 1 +#define CAM_CC_IFE_0_BCR 2 +#define CAM_CC_IFE_1_BCR 3 +#define CAM_CC_IPE_0_BCR 4 +#define CAM_CC_SFE_0_BCR 5 + +#endif diff --git a/include/dt-bindings/clock/qcom,x1e80100-dispcc.h b/include/dt-bindings/clock/qcom,x1e80100-dispcc.h new file mode 100644 index 00000000000..d4a83e4fd0d --- /dev/null +++ b/include/dt-bindings/clock/qcom,x1e80100-dispcc.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_DISP_CC_H +#define _DT_BINDINGS_CLK_QCOM_X1E80100_DISP_CC_H + +/* DISP_CC clocks */ +#define DISP_CC_MDSS_ACCU_CLK 0 +#define DISP_CC_MDSS_AHB1_CLK 1 +#define DISP_CC_MDSS_AHB_CLK 2 +#define DISP_CC_MDSS_AHB_CLK_SRC 3 +#define DISP_CC_MDSS_BYTE0_CLK 4 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 5 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 7 +#define DISP_CC_MDSS_BYTE1_CLK 8 +#define DISP_CC_MDSS_BYTE1_CLK_SRC 9 +#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 10 +#define DISP_CC_MDSS_BYTE1_INTF_CLK 11 +#define DISP_CC_MDSS_DPTX0_AUX_CLK 12 +#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 13 +#define DISP_CC_MDSS_DPTX0_LINK_CLK 14 +#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 15 +#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 16 +#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 17 +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 18 +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 19 +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 20 +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 21 +#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 22 +#define DISP_CC_MDSS_DPTX1_AUX_CLK 23 +#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 24 +#define DISP_CC_MDSS_DPTX1_LINK_CLK 25 +#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 26 +#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 27 +#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 28 +#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 29 +#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 30 +#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 31 +#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 32 +#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 33 +#define DISP_CC_MDSS_DPTX2_AUX_CLK 34 +#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 35 +#define DISP_CC_MDSS_DPTX2_LINK_CLK 36 +#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 37 +#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 38 +#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 39 +#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 40 +#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 41 +#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 42 +#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 43 +#define DISP_CC_MDSS_DPTX2_USB_ROUTER_LINK_INTF_CLK 44 +#define DISP_CC_MDSS_DPTX3_AUX_CLK 45 +#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 46 +#define DISP_CC_MDSS_DPTX3_LINK_CLK 47 +#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 48 +#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 49 +#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 50 +#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 51 +#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 52 +#define DISP_CC_MDSS_ESC0_CLK 53 +#define DISP_CC_MDSS_ESC0_CLK_SRC 54 +#define DISP_CC_MDSS_ESC1_CLK 55 +#define DISP_CC_MDSS_ESC1_CLK_SRC 56 +#define DISP_CC_MDSS_MDP1_CLK 57 +#define DISP_CC_MDSS_MDP_CLK 58 +#define DISP_CC_MDSS_MDP_CLK_SRC 59 +#define DISP_CC_MDSS_MDP_LUT1_CLK 60 +#define DISP_CC_MDSS_MDP_LUT_CLK 61 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 62 +#define DISP_CC_MDSS_PCLK0_CLK 63 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 64 +#define DISP_CC_MDSS_PCLK1_CLK 65 +#define DISP_CC_MDSS_PCLK1_CLK_SRC 66 +#define DISP_CC_MDSS_RSCC_AHB_CLK 67 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK 68 +#define DISP_CC_MDSS_VSYNC1_CLK 69 +#define DISP_CC_MDSS_VSYNC_CLK 70 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 71 +#define DISP_CC_PLL0 72 +#define DISP_CC_PLL1 73 +#define DISP_CC_SLEEP_CLK 74 +#define DISP_CC_SLEEP_CLK_SRC 75 +#define DISP_CC_XO_CLK 76 +#define DISP_CC_XO_CLK_SRC 77 + +/* DISP_CC resets */ +#define DISP_CC_MDSS_CORE_BCR 0 +#define DISP_CC_MDSS_CORE_INT2_BCR 1 +#define DISP_CC_MDSS_RSCC_BCR 2 + +/* DISP_CC GDSCR */ +#define MDSS_GDSC 0 +#define MDSS_INT2_GDSC 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,x1e80100-gpucc.h b/include/dt-bindings/clock/qcom,x1e80100-gpucc.h new file mode 100644 index 00000000000..61a3a8f3ac4 --- /dev/null +++ b/include/dt-bindings/clock/qcom,x1e80100-gpucc.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_GPU_CC_H +#define _DT_BINDINGS_CLK_QCOM_X1E80100_GPU_CC_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CB_CLK 1 +#define GPU_CC_CRC_AHB_CLK 2 +#define GPU_CC_CX_FF_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CXO_AON_CLK 5 +#define GPU_CC_CXO_CLK 6 +#define GPU_CC_DEMET_CLK 7 +#define GPU_CC_DEMET_DIV_CLK_SRC 8 +#define GPU_CC_FF_CLK_SRC 9 +#define GPU_CC_FREQ_MEASURE_CLK 10 +#define GPU_CC_GMU_CLK_SRC 11 +#define GPU_CC_GX_GMU_CLK 12 +#define GPU_CC_GX_VSENSE_CLK 13 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14 +#define GPU_CC_HUB_AON_CLK 15 +#define GPU_CC_HUB_CLK_SRC 16 +#define GPU_CC_HUB_CX_INT_CLK 17 +#define GPU_CC_MEMNOC_GFX_CLK 18 +#define GPU_CC_MND1X_0_GFX3D_CLK 19 +#define GPU_CC_MND1X_1_GFX3D_CLK 20 +#define GPU_CC_PLL0 21 +#define GPU_CC_PLL1 22 +#define GPU_CC_SLEEP_CLK 23 +#define GPU_CC_XO_CLK_SRC 24 +#define GPU_CC_XO_DIV_CLK_SRC 25 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,x1e80100-tcsr.h b/include/dt-bindings/clock/qcom,x1e80100-tcsr.h new file mode 100644 index 00000000000..bae2c4654ee --- /dev/null +++ b/include/dt-bindings/clock/qcom,x1e80100-tcsr.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_TCSR_CC_H +#define _DT_BINDINGS_CLK_QCOM_X1E80100_TCSR_CC_H + +/* TCSR CC clocks */ +#define TCSR_PCIE_2L_4_CLKREF_EN 0 +#define TCSR_PCIE_2L_5_CLKREF_EN 1 +#define TCSR_PCIE_8L_CLKREF_EN 2 +#define TCSR_USB3_MP0_CLKREF_EN 3 +#define TCSR_USB3_MP1_CLKREF_EN 4 +#define TCSR_USB2_1_CLKREF_EN 5 +#define TCSR_UFS_PHY_CLKREF_EN 6 +#define TCSR_USB4_1_CLKREF_EN 7 +#define TCSR_USB4_2_CLKREF_EN 8 +#define TCSR_USB2_2_CLKREF_EN 9 +#define TCSR_PCIE_4L_CLKREF_EN 10 +#define TCSR_EDP_CLKREF_EN 11 + +#endif diff --git a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h index 754c54a6eb0..7850cdc62e2 100644 --- a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h @@ -86,5 +86,6 @@ #define R8A779G0_CLK_CPEX 74 #define R8A779G0_CLK_CBFUSA 75 #define R8A779G0_CLK_R 76 +#define R8A779G0_CLK_CP 77 #endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h b/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h new file mode 100644 index 00000000000..7ab6cfbaf90 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ + +#include + +/* r8a779h0 CPG Core Clocks */ + +#define R8A779H0_CLK_ZX 0 +#define R8A779H0_CLK_ZD 1 +#define R8A779H0_CLK_ZS 2 +#define R8A779H0_CLK_ZT 3 +#define R8A779H0_CLK_ZTR 4 +#define R8A779H0_CLK_S0D2 5 +#define R8A779H0_CLK_S0D3 6 +#define R8A779H0_CLK_S0D4 7 +#define R8A779H0_CLK_S0D1_VIO 8 +#define R8A779H0_CLK_S0D2_VIO 9 +#define R8A779H0_CLK_S0D4_VIO 10 +#define R8A779H0_CLK_S0D8_VIO 11 +#define R8A779H0_CLK_VIOBUSD1 12 +#define R8A779H0_CLK_VIOBUSD2 13 +#define R8A779H0_CLK_S0D1_VC 14 +#define R8A779H0_CLK_S0D2_VC 15 +#define R8A779H0_CLK_S0D4_VC 16 +#define R8A779H0_CLK_VCBUSD1 17 +#define R8A779H0_CLK_VCBUSD2 18 +#define R8A779H0_CLK_S0D2_MM 19 +#define R8A779H0_CLK_S0D4_MM 20 +#define R8A779H0_CLK_S0D2_U3DG 21 +#define R8A779H0_CLK_S0D4_U3DG 22 +#define R8A779H0_CLK_S0D2_RT 23 +#define R8A779H0_CLK_S0D3_RT 24 +#define R8A779H0_CLK_S0D4_RT 25 +#define R8A779H0_CLK_S0D6_RT 26 +#define R8A779H0_CLK_S0D2_PER 27 +#define R8A779H0_CLK_S0D3_PER 28 +#define R8A779H0_CLK_S0D4_PER 29 +#define R8A779H0_CLK_S0D6_PER 30 +#define R8A779H0_CLK_S0D12_PER 31 +#define R8A779H0_CLK_S0D24_PER 32 +#define R8A779H0_CLK_S0D1_HSC 33 +#define R8A779H0_CLK_S0D2_HSC 34 +#define R8A779H0_CLK_S0D4_HSC 35 +#define R8A779H0_CLK_S0D8_HSC 36 +#define R8A779H0_CLK_SVD1_IR 37 +#define R8A779H0_CLK_SVD2_IR 38 +#define R8A779H0_CLK_IMPAD1 39 +#define R8A779H0_CLK_IMPAD4 40 +#define R8A779H0_CLK_IMPB 41 +#define R8A779H0_CLK_SVD1_VIP 42 +#define R8A779H0_CLK_SVD2_VIP 43 +#define R8A779H0_CLK_CL 44 +#define R8A779H0_CLK_CL16M 45 +#define R8A779H0_CLK_CL16M_MM 46 +#define R8A779H0_CLK_CL16M_RT 47 +#define R8A779H0_CLK_CL16M_PER 48 +#define R8A779H0_CLK_CL16M_HSC 49 +#define R8A779H0_CLK_ZC0 50 +#define R8A779H0_CLK_ZC1 51 +#define R8A779H0_CLK_ZC2 52 +#define R8A779H0_CLK_ZC3 53 +#define R8A779H0_CLK_ZB3 54 +#define R8A779H0_CLK_ZB3D2 55 +#define R8A779H0_CLK_ZB3D4 56 +#define R8A779H0_CLK_ZG 57 +#define R8A779H0_CLK_SD0H 58 +#define R8A779H0_CLK_SD0 59 +#define R8A779H0_CLK_RPC 60 +#define R8A779H0_CLK_RPCD2 61 +#define R8A779H0_CLK_MSO 62 +#define R8A779H0_CLK_CANFD 63 +#define R8A779H0_CLK_CSI 64 +#define R8A779H0_CLK_FRAY 65 +#define R8A779H0_CLK_IPC 66 +#define R8A779H0_CLK_SASYNCRT 67 +#define R8A779H0_CLK_SASYNCPERD1 68 +#define R8A779H0_CLK_SASYNCPERD2 69 +#define R8A779H0_CLK_SASYNCPERD4 70 +#define R8A779H0_CLK_DSIEXT 71 +#define R8A779H0_CLK_DSIREF 72 +#define R8A779H0_CLK_ADGH 73 +#define R8A779H0_CLK_OSC 74 +#define R8A779H0_CLK_ZR0 75 +#define R8A779H0_CLK_ZR1 76 +#define R8A779H0_CLK_ZR2 77 +#define R8A779H0_CLK_RGMII 78 +#define R8A779H0_CLK_CPEX 79 +#define R8A779H0_CLK_CP 80 +#define R8A779H0_CLK_CBFUSA 81 +#define R8A779H0_CLK_R 82 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/rockchip,rk3588-cru.h b/include/dt-bindings/clock/rockchip,rk3588-cru.h index 5790b139120..0c7d3ca2d5b 100644 --- a/include/dt-bindings/clock/rockchip,rk3588-cru.h +++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h @@ -733,8 +733,7 @@ #define ACLK_AV1_PRE 718 #define PCLK_AV1_PRE 719 #define HCLK_SDIO_PRE 720 - -#define CLK_NR_CLKS (HCLK_SDIO_PRE + 1) +#define PCLK_VO1GRF 721 /* scmi-clocks indices */ diff --git a/include/dt-bindings/input/linux-event-codes.h b/include/dt-bindings/input/linux-event-codes.h index 022a520e31f..03edf2ccdf6 100644 --- a/include/dt-bindings/input/linux-event-codes.h +++ b/include/dt-bindings/input/linux-event-codes.h @@ -602,6 +602,7 @@ #define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */ #define KEY_ROTATE_LOCK_TOGGLE 0x231 /* Display rotation lock */ +#define KEY_REFRESH_RATE_TOGGLE 0x232 /* Display refresh rate toggle */ #define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */ #define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */ diff --git a/include/dt-bindings/interconnect/qcom,msm8909.h b/include/dt-bindings/interconnect/qcom,msm8909.h new file mode 100644 index 00000000000..76365d8aec2 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,msm8909.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Qualcomm MSM8909 interconnect IDs + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8909_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8909_H + +/* BIMC fabric */ +#define MAS_APPS_PROC 0 +#define MAS_OXILI 1 +#define MAS_SNOC_BIMC_0 2 +#define MAS_SNOC_BIMC_1 3 +#define MAS_TCU_0 4 +#define MAS_TCU_1 5 +#define SLV_EBI 6 +#define SLV_BIMC_SNOC 7 + +/* PCNOC fabric */ +#define MAS_AUDIO 0 +#define MAS_SPDM 1 +#define MAS_DEHR 2 +#define MAS_QPIC 3 +#define MAS_BLSP_1 4 +#define MAS_USB_HS 5 +#define MAS_CRYPTO 6 +#define MAS_SDCC_1 7 +#define MAS_SDCC_2 8 +#define MAS_SNOC_PCNOC 9 +#define PCNOC_M_0 10 +#define PCNOC_M_1 11 +#define PCNOC_INT_0 12 +#define PCNOC_INT_1 13 +#define PCNOC_S_0 14 +#define PCNOC_S_1 15 +#define PCNOC_S_2 16 +#define PCNOC_S_3 17 +#define PCNOC_S_4 18 +#define PCNOC_S_5 19 +#define PCNOC_S_7 20 +#define SLV_TCSR 21 +#define SLV_SDCC_1 22 +#define SLV_BLSP_1 23 +#define SLV_CRYPTO_0_CFG 24 +#define SLV_MESSAGE_RAM 25 +#define SLV_PDM 26 +#define SLV_PRNG 27 +#define SLV_USB_HS 28 +#define SLV_QPIC 29 +#define SLV_SPDM 30 +#define SLV_SDCC_2 31 +#define SLV_AUDIO 32 +#define SLV_DEHR_CFG 33 +#define SLV_SNOC_CFG 34 +#define SLV_QDSS_CFG 35 +#define SLV_USB_PHY 36 +#define SLV_CAMERA_SS_CFG 37 +#define SLV_DISP_SS_CFG 38 +#define SLV_VENUS_CFG 39 +#define SLV_TLMM 40 +#define SLV_GPU_CFG 41 +#define SLV_IMEM_CFG 42 +#define SLV_BIMC_CFG 43 +#define SLV_PMIC_ARB 44 +#define SLV_TCU 45 +#define SLV_PCNOC_SNOC 46 + +/* SNOC fabric */ +#define MAS_QDSS_BAM 0 +#define MAS_BIMC_SNOC 1 +#define MAS_MDP 2 +#define MAS_PCNOC_SNOC 3 +#define MAS_VENUS 4 +#define MAS_VFE 5 +#define MAS_QDSS_ETR 6 +#define MM_INT_0 7 +#define MM_INT_1 8 +#define MM_INT_2 9 +#define MM_INT_BIMC 10 +#define QDSS_INT 11 +#define SNOC_INT_0 12 +#define SNOC_INT_1 13 +#define SNOC_INT_BIMC 14 +#define SLV_KPSS_AHB 15 +#define SLV_SNOC_BIMC_0 16 +#define SLV_SNOC_BIMC_1 17 +#define SLV_IMEM 18 +#define SLV_SNOC_PCNOC 19 +#define SLV_QDSS_STM 20 +#define SLV_CATS_0 21 +#define SLV_CATS_1 22 + +#endif /* __DT_BINDINGS_INTERCONNECT_QCOM_MSM8909_H */ diff --git a/include/dt-bindings/interconnect/qcom,sm7150-rpmh.h b/include/dt-bindings/interconnect/qcom,sm7150-rpmh.h new file mode 100644 index 00000000000..1f610eb832a --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sm7150-rpmh.h @@ -0,0 +1,150 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Qualcomm SM7150 interconnect IDs + * + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Danila Tikhonov + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM7150_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SM7150_H + +#define MASTER_A1NOC_CFG 0 +#define MASTER_QUP_0 1 +#define MASTER_TSIF 2 +#define MASTER_EMMC 3 +#define MASTER_SDCC_2 4 +#define MASTER_SDCC_4 5 +#define MASTER_UFS_MEM 6 +#define A1NOC_SNOC_SLV 7 +#define SLAVE_SERVICE_A1NOC 8 + +#define MASTER_A2NOC_CFG 0 +#define MASTER_QDSS_BAM 1 +#define MASTER_QUP_1 2 +#define MASTER_CNOC_A2NOC 3 +#define MASTER_CRYPTO_CORE_0 4 +#define MASTER_IPA 5 +#define MASTER_PCIE 6 +#define MASTER_QDSS_ETR 7 +#define MASTER_USB3 8 +#define A2NOC_SNOC_SLV 9 +#define SLAVE_ANOC_PCIE_GEM_NOC 10 +#define SLAVE_SERVICE_A2NOC 11 + +#define MASTER_CAMNOC_HF0_UNCOMP 0 +#define MASTER_CAMNOC_RT_UNCOMP 1 +#define MASTER_CAMNOC_SF_UNCOMP 2 +#define MASTER_CAMNOC_NRT_UNCOMP 3 +#define SLAVE_CAMNOC_UNCOMP 4 + +#define MASTER_NPU 0 +#define SLAVE_CDSP_GEM_NOC 1 + +#define MASTER_SPDM 0 +#define SNOC_CNOC_MAS 1 +#define MASTER_QDSS_DAP 2 +#define SLAVE_A1NOC_CFG 3 +#define SLAVE_A2NOC_CFG 4 +#define SLAVE_AHB2PHY_NORTH 5 +#define SLAVE_AHB2PHY_SOUTH 6 +#define SLAVE_AHB2PHY_WEST 7 +#define SLAVE_AOP 8 +#define SLAVE_AOSS 9 +#define SLAVE_CAMERA_CFG 10 +#define SLAVE_CAMERA_NRT_THROTTLE_CFG 11 +#define SLAVE_CAMERA_RT_THROTTLE_CFG 12 +#define SLAVE_CLK_CTL 13 +#define SLAVE_CDSP_CFG 14 +#define SLAVE_RBCPR_CX_CFG 15 +#define SLAVE_RBCPR_MX_CFG 16 +#define SLAVE_CRYPTO_0_CFG 17 +#define SLAVE_CNOC_DDRSS 18 +#define SLAVE_DISPLAY_CFG 19 +#define SLAVE_DISPLAY_THROTTLE_CFG 20 +#define SLAVE_EMMC_CFG 21 +#define SLAVE_GLM 22 +#define SLAVE_GRAPHICS_3D_CFG 23 +#define SLAVE_IMEM_CFG 24 +#define SLAVE_IPA_CFG 25 +#define SLAVE_CNOC_MNOC_CFG 26 +#define SLAVE_PCIE_CFG 27 +#define SLAVE_PDM 28 +#define SLAVE_PIMEM_CFG 29 +#define SLAVE_PRNG 30 +#define SLAVE_QDSS_CFG 31 +#define SLAVE_QUP_0 32 +#define SLAVE_QUP_1 33 +#define SLAVE_SDCC_2 34 +#define SLAVE_SDCC_4 35 +#define SLAVE_SNOC_CFG 36 +#define SLAVE_SPDM_WRAPPER 37 +#define SLAVE_TCSR 38 +#define SLAVE_TLMM_NORTH 39 +#define SLAVE_TLMM_SOUTH 40 +#define SLAVE_TLMM_WEST 41 +#define SLAVE_TSIF 42 +#define SLAVE_UFS_MEM_CFG 43 +#define SLAVE_USB3 44 +#define SLAVE_VENUS_CFG 45 +#define SLAVE_VENUS_CVP_THROTTLE_CFG 46 +#define SLAVE_VENUS_THROTTLE_CFG 47 +#define SLAVE_VSENSE_CTRL_CFG 48 +#define SLAVE_CNOC_A2NOC 49 +#define SLAVE_SERVICE_CNOC 50 + +#define MASTER_CNOC_DC_NOC 0 +#define SLAVE_GEM_NOC_CFG 1 +#define SLAVE_LLCC_CFG 2 + +#define MASTER_AMPSS_M0 0 +#define MASTER_SYS_TCU 1 +#define MASTER_GEM_NOC_CFG 2 +#define MASTER_COMPUTE_NOC 3 +#define MASTER_MNOC_HF_MEM_NOC 4 +#define MASTER_MNOC_SF_MEM_NOC 5 +#define MASTER_GEM_NOC_PCIE_SNOC 6 +#define MASTER_SNOC_GC_MEM_NOC 7 +#define MASTER_SNOC_SF_MEM_NOC 8 +#define MASTER_GRAPHICS_3D 9 +#define SLAVE_MSS_PROC_MS_MPU_CFG 10 +#define SLAVE_GEM_NOC_SNOC 11 +#define SLAVE_LLCC 12 +#define SLAVE_SERVICE_GEM_NOC 13 + + +#define MASTER_LLCC 0 +#define SLAVE_EBI_CH0 1 + +#define MASTER_CNOC_MNOC_CFG 0 +#define MASTER_CAMNOC_HF0 1 +#define MASTER_CAMNOC_NRT 2 +#define MASTER_CAMNOC_RT 3 +#define MASTER_CAMNOC_SF 4 +#define MASTER_MDP_PORT0 5 +#define MASTER_MDP_PORT1 6 +#define MASTER_ROTATOR 7 +#define MASTER_VIDEO_P0 8 +#define MASTER_VIDEO_P1 9 +#define MASTER_VIDEO_PROC 10 +#define SLAVE_MNOC_SF_MEM_NOC 11 +#define SLAVE_MNOC_HF_MEM_NOC 12 +#define SLAVE_SERVICE_MNOC 13 + +#define MASTER_SNOC_CFG 0 +#define A1NOC_SNOC_MAS 1 +#define A2NOC_SNOC_MAS 2 +#define MASTER_GEM_NOC_SNOC 3 +#define MASTER_PIMEM 4 +#define MASTER_GIC 5 +#define SLAVE_APPSS 6 +#define SNOC_CNOC_SLV 7 +#define SLAVE_SNOC_GEM_NOC_GC 8 +#define SLAVE_SNOC_GEM_NOC_SF 9 +#define SLAVE_OCIMEM 10 +#define SLAVE_PIMEM 11 +#define SLAVE_SERVICE_SNOC 12 +#define SLAVE_QDSS_STM 13 +#define SLAVE_TCU 14 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h b/include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h index a38c3472698..7d971088114 100644 --- a/include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h +++ b/include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h @@ -112,11 +112,6 @@ #define SLAVE_GEM_NOC_CNOC 12 #define SLAVE_LLCC 13 #define SLAVE_MEM_NOC_PCIE_SNOC 14 -#define MASTER_MNOC_HF_MEM_NOC_DISP 15 -#define MASTER_ANOC_PCIE_GEM_NOC_DISP 16 -#define SLAVE_LLCC_DISP 17 -#define MASTER_ANOC_PCIE_GEM_NOC_PCIE 18 -#define SLAVE_LLCC_PCIE 19 #define MASTER_LPIAON_NOC 0 #define SLAVE_LPASS_GEM_NOC 1 @@ -129,10 +124,6 @@ #define MASTER_LLCC 0 #define SLAVE_EBI1 1 -#define MASTER_LLCC_DISP 2 -#define SLAVE_EBI1_DISP 3 -#define MASTER_LLCC_PCIE 4 -#define SLAVE_EBI1_PCIE 5 #define MASTER_AV1_ENC 0 #define MASTER_CAMNOC_HF 1 @@ -147,8 +138,6 @@ #define SLAVE_MNOC_HF_MEM_NOC 10 #define SLAVE_MNOC_SF_MEM_NOC 11 #define SLAVE_SERVICE_MNOC 12 -#define MASTER_MDP_DISP 13 -#define SLAVE_MNOC_HF_MEM_NOC_DISP 14 #define MASTER_CDSP_PROC 0 #define SLAVE_CDSP_MEM_NOC 1 @@ -156,18 +145,11 @@ #define MASTER_PCIE_NORTH 0 #define MASTER_PCIE_SOUTH 1 #define SLAVE_ANOC_PCIE_GEM_NOC 2 -#define MASTER_PCIE_NORTH_PCIE 3 -#define MASTER_PCIE_SOUTH_PCIE 4 -#define SLAVE_ANOC_PCIE_GEM_NOC_PCIE 5 #define MASTER_PCIE_3 0 #define MASTER_PCIE_4 1 #define MASTER_PCIE_5 2 #define SLAVE_PCIE_NORTH 3 -#define MASTER_PCIE_3_PCIE 4 -#define MASTER_PCIE_4_PCIE 5 -#define MASTER_PCIE_5_PCIE 6 -#define SLAVE_PCIE_NORTH_PCIE 7 #define MASTER_PCIE_0 0 #define MASTER_PCIE_1 1 @@ -175,12 +157,6 @@ #define MASTER_PCIE_6A 3 #define MASTER_PCIE_6B 4 #define SLAVE_PCIE_SOUTH 5 -#define MASTER_PCIE_0_PCIE 6 -#define MASTER_PCIE_1_PCIE 7 -#define MASTER_PCIE_2_PCIE 8 -#define MASTER_PCIE_6A_PCIE 9 -#define MASTER_PCIE_6B_PCIE 10 -#define SLAVE_PCIE_SOUTH_PCIE 11 #define MASTER_A1NOC_SNOC 0 #define MASTER_A2NOC_SNOC 1 diff --git a/include/dt-bindings/leds/common.h b/include/dt-bindings/leds/common.h index 9a0d33d027f..ecea167930d 100644 --- a/include/dt-bindings/leds/common.h +++ b/include/dt-bindings/leds/common.h @@ -100,7 +100,11 @@ #define LED_FUNCTION_TX "tx" #define LED_FUNCTION_USB "usb" #define LED_FUNCTION_WAN "wan" +#define LED_FUNCTION_WAN_ONLINE "wan-online" #define LED_FUNCTION_WLAN "wlan" +#define LED_FUNCTION_WLAN_2GHZ "wlan-2ghz" +#define LED_FUNCTION_WLAN_5GHZ "wlan-5ghz" +#define LED_FUNCTION_WLAN_6GHZ "wlan-6ghz" #define LED_FUNCTION_WPS "wps" #endif /* __DT_BINDINGS_LEDS_H */ diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h index 8d73a9c51e2..a4e4f927139 100644 --- a/include/dt-bindings/mfd/stm32f7-rcc.h +++ b/include/dt-bindings/mfd/stm32f7-rcc.h @@ -108,6 +108,7 @@ #define STM32F7_RCC_APB2_SAI1 22 #define STM32F7_RCC_APB2_SAI2 23 #define STM32F7_RCC_APB2_LTDC 26 +#define STM32F7_RCC_APB2_DSI 27 #define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8)) #define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0) diff --git a/include/dt-bindings/power/amlogic,c3-pwrc.h b/include/dt-bindings/power/amlogic,c3-pwrc.h index 1d98a25b08a..61759df4b2e 100644 --- a/include/dt-bindings/power/amlogic,c3-pwrc.h +++ b/include/dt-bindings/power/amlogic,c3-pwrc.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (c) 2023 Amlogic, Inc. * Author: hongyu chen1 diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 7f4e2983a4c..608087fb9a3 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -308,6 +308,13 @@ #define MSM8953_VDDMX 5 #define MSM8953_VDDMX_AO 6 +/* MSM8974 Power Domain Indexes */ +#define MSM8974_VDDCX 0 +#define MSM8974_VDDCX_AO 1 +#define MSM8974_VDDCX_VFC 2 +#define MSM8974_VDDGFX 3 +#define MSM8974_VDDGFX_VFC 4 + /* MSM8976 Power Domain Indexes */ #define MSM8976_VDDCX 0 #define MSM8976_VDDCX_AO 1 diff --git a/include/dt-bindings/power/renesas,r8a779h0-sysc.h b/include/dt-bindings/power/renesas,r8a779h0-sysc.h new file mode 100644 index 00000000000..f27976f523e --- /dev/null +++ b/include/dt-bindings/power/renesas,r8a779h0-sysc.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ +#define __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ + +/* + * These power domain indices match the Power Domain Register Numbers (PDR) + */ + +#define R8A779H0_PD_A1E0D0C0 0 +#define R8A779H0_PD_A1E0D0C1 1 +#define R8A779H0_PD_A1E0D0C2 2 +#define R8A779H0_PD_A1E0D0C3 3 +#define R8A779H0_PD_A2E0D0 16 +#define R8A779H0_PD_A3CR0 21 +#define R8A779H0_PD_A3CR1 22 +#define R8A779H0_PD_A3CR2 23 +#define R8A779H0_PD_A33DGA 24 +#define R8A779H0_PD_A23DGB 25 +#define R8A779H0_PD_C4 31 +#define R8A779H0_PD_A1DSP0 33 +#define R8A779H0_PD_A2IMP01 34 +#define R8A779H0_PD_A2PSC 35 +#define R8A779H0_PD_A2CV0 36 +#define R8A779H0_PD_A2CV1 37 +#define R8A779H0_PD_A3IMR0 38 +#define R8A779H0_PD_A3IMR1 39 +#define R8A779H0_PD_A3VC 40 +#define R8A779H0_PD_A2CN0 42 +#define R8A779H0_PD_A1CN0 44 +#define R8A779H0_PD_A1DSP1 45 +#define R8A779H0_PD_A2DMA 47 +#define R8A779H0_PD_A2CV2 48 +#define R8A779H0_PD_A2CV3 49 +#define R8A779H0_PD_A3IMR2 50 +#define R8A779H0_PD_A3IMR3 51 +#define R8A779H0_PD_A3PCI 52 +#define R8A779H0_PD_A2PCIPHY 53 +#define R8A779H0_PD_A3VIP0 56 +#define R8A779H0_PD_A3VIP2 58 +#define R8A779H0_PD_A3ISP0 60 +#define R8A779H0_PD_A3DUL 62 + +/* Always-on power area */ +#define R8A779H0_PD_ALWAYS_ON 64 + +#endif /* __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ */ diff --git a/include/dt-bindings/reset/mediatek,mt7988-resets.h b/include/dt-bindings/reset/mediatek,mt7988-resets.h index 49330197136..0eb152889a8 100644 --- a/include/dt-bindings/reset/mediatek,mt7988-resets.h +++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h @@ -10,4 +10,10 @@ /* ETHWARP resets */ #define MT7988_ETHWARP_RST_SWITCH 0 +/* INFRA resets */ +#define MT7988_INFRA_RST0_PEXTP_MAC_SWRST 0 +#define MT7988_INFRA_RST1_THERM_CTRL_SWRST 1 + + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */ + diff --git a/include/dt-bindings/reset/qcom,x1e80100-gpucc.h b/include/dt-bindings/reset/qcom,x1e80100-gpucc.h new file mode 100644 index 00000000000..32b43e71a16 --- /dev/null +++ b/include/dt-bindings/reset/qcom,x1e80100-gpucc.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_RESET_QCOM_X1E80100_GPU_CC_H +#define _DT_BINDINGS_RESET_QCOM_X1E80100_GPU_CC_H + +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CB_BCR 1 +#define GPUCC_GPU_CC_CX_BCR 2 +#define GPUCC_GPU_CC_FAST_HUB_BCR 3 +#define GPUCC_GPU_CC_FF_BCR 4 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 5 +#define GPUCC_GPU_CC_GMU_BCR 6 +#define GPUCC_GPU_CC_GX_BCR 7 +#define GPUCC_GPU_CC_XO_BCR 8 + +#endif diff --git a/include/dt-bindings/reset/sophgo,sg2042-reset.h b/include/dt-bindings/reset/sophgo,sg2042-reset.h new file mode 100644 index 00000000000..9ab0980625c --- /dev/null +++ b/include/dt-bindings/reset/sophgo,sg2042-reset.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved. + */ + +#ifndef __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ +#define __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ + +#define RST_MAIN_AP 0 +#define RST_RISCV_CPU 1 +#define RST_RISCV_LOW_SPEED_LOGIC 2 +#define RST_RISCV_CMN 3 +#define RST_HSDMA 4 +#define RST_SYSDMA 5 +#define RST_EFUSE0 6 +#define RST_EFUSE1 7 +#define RST_RTC 8 +#define RST_TIMER 9 +#define RST_WDT 10 +#define RST_AHB_ROM0 11 +#define RST_AHB_ROM1 12 +#define RST_I2C0 13 +#define RST_I2C1 14 +#define RST_I2C2 15 +#define RST_I2C3 16 +#define RST_GPIO0 17 +#define RST_GPIO1 18 +#define RST_GPIO2 19 +#define RST_PWM 20 +#define RST_AXI_SRAM0 21 +#define RST_AXI_SRAM1 22 +#define RST_SF0 23 +#define RST_SF1 24 +#define RST_LPC 25 +#define RST_ETH0 26 +#define RST_EMMC 27 +#define RST_SD 28 +#define RST_UART0 29 +#define RST_UART1 30 +#define RST_UART2 31 +#define RST_UART3 32 +#define RST_SPI0 33 +#define RST_SPI1 34 +#define RST_DBG_I2C 35 +#define RST_PCIE0 36 +#define RST_PCIE1 37 +#define RST_DDR0 38 +#define RST_DDR1 39 +#define RST_DDR2 40 +#define RST_DDR3 41 +#define RST_FAU0 42 +#define RST_FAU1 43 +#define RST_FAU2 44 +#define RST_RXU0 45 +#define RST_RXU1 46 +#define RST_RXU2 47 +#define RST_RXU3 48 +#define RST_RXU4 49 +#define RST_RXU5 50 +#define RST_RXU6 51 +#define RST_RXU7 52 +#define RST_RXU8 53 +#define RST_RXU9 54 +#define RST_RXU10 55 +#define RST_RXU11 56 +#define RST_RXU12 57 +#define RST_RXU13 58 +#define RST_RXU14 59 +#define RST_RXU15 60 +#define RST_RXU16 61 +#define RST_RXU17 62 +#define RST_RXU18 63 +#define RST_RXU19 64 +#define RST_RXU20 65 +#define RST_RXU21 66 +#define RST_RXU22 67 +#define RST_RXU23 68 +#define RST_RXU24 69 +#define RST_RXU25 70 +#define RST_RXU26 71 +#define RST_RXU27 72 +#define RST_RXU28 73 +#define RST_RXU29 74 +#define RST_RXU30 75 +#define RST_RXU31 76 + +#endif /* __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ */ diff --git a/src/arc/axc003.dtsi b/src/arc/axc003.dtsi index 3434c8131ec..c0a812674ce 100644 --- a/src/arc/axc003.dtsi +++ b/src/arc/axc003.dtsi @@ -119,9 +119,9 @@ /* * The DW APB ICTL intc on MB is connected to CPU intc via a * DT "invisible" DW APB GPIO block, configured to simply pass thru - * interrupts - setup accordinly in platform init (plat-axs10x/ax10x.c) + * interrupts - setup accordingly in platform init (plat-axs10x/ax10x.c) * - * So here we mimic a direct connection betwen them, ignoring the + * So here we mimic a direct connection between them, ignoring the * ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core) * instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO) * diff --git a/src/arc/hsdk.dts b/src/arc/hsdk.dts index 6691f425507..41b980df862 100644 --- a/src/arc/hsdk.dts +++ b/src/arc/hsdk.dts @@ -205,7 +205,6 @@ }; gmac: ethernet@8000 { - #interrupt-cells = <1>; compatible = "snps,dwmac"; reg = <0x8000 0x2000>; interrupts = <10>; diff --git a/src/arc/vdk_axs10x_mb.dtsi b/src/arc/vdk_axs10x_mb.dtsi index 90a412026e6..0e0e2d337bf 100644 --- a/src/arc/vdk_axs10x_mb.dtsi +++ b/src/arc/vdk_axs10x_mb.dtsi @@ -113,7 +113,7 @@ /* * Embedded Vision subsystem UIO mappings; only relevant for EV VDK * - * This node is intentionally put outside of MB above becase + * This node is intentionally put outside of MB above because * it maps areas outside of MB's 0xez-0xfz. */ uio_ev: uio@d0000000 { diff --git a/src/arm/allwinner/sun8i-r40-feta40i.dtsi b/src/arm/allwinner/sun8i-r40-feta40i.dtsi index 9f39b5a2bb3..c12361d0317 100644 --- a/src/arm/allwinner/sun8i-r40-feta40i.dtsi +++ b/src/arm/allwinner/sun8i-r40-feta40i.dtsi @@ -42,6 +42,13 @@ vcc-pg-supply = <®_dldo1>; }; +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3-tv-usb"; +}; + ®_aldo2 { regulator-always-on; regulator-min-microvolt = <1800000>; diff --git a/src/arm/amlogic/meson.dtsi b/src/arm/amlogic/meson.dtsi index 8e3860d5d91..8cb0fc78b2a 100644 --- a/src/arm/amlogic/meson.dtsi +++ b/src/arm/amlogic/meson.dtsi @@ -23,7 +23,7 @@ #size-cells = <1>; ranges; - cbus: cbus@c1100000 { + cbus: bus@c1100000 { compatible = "simple-bus"; reg = <0xc1100000 0x200000>; #address-cells = <1>; @@ -206,7 +206,7 @@ }; }; - aobus: aobus@c8100000 { + aobus: bus@c8100000 { compatible = "simple-bus"; reg = <0xc8100000 0x100000>; #address-cells = <1>; @@ -302,7 +302,7 @@ reg = <0xd9040000 0x10000>; }; - secbus: secbus@da000000 { + secbus: bus@da000000 { compatible = "simple-bus"; reg = <0xda000000 0x6000>; #address-cells = <1>; diff --git a/src/arm/amlogic/meson8.dtsi b/src/arm/amlogic/meson8.dtsi index 59932fbfd5d..f57be9ae150 100644 --- a/src/arm/amlogic/meson8.dtsi +++ b/src/arm/amlogic/meson8.dtsi @@ -645,7 +645,6 @@ }; &hwrng { - compatible = "amlogic,meson8-rng", "amlogic,meson-rng"; clocks = <&clkc CLKID_RNG0>; clock-names = "core"; }; diff --git a/src/arm/amlogic/meson8b.dtsi b/src/arm/amlogic/meson8b.dtsi index 5198f5177c2..2d9d24d3a95 100644 --- a/src/arm/amlogic/meson8b.dtsi +++ b/src/arm/amlogic/meson8b.dtsi @@ -620,7 +620,6 @@ }; &hwrng { - compatible = "amlogic,meson8b-rng", "amlogic,meson-rng"; clocks = <&clkc CLKID_RNG0>; clock-names = "core"; }; diff --git a/src/arm/arm/arm-realview-pb1176.dts b/src/arm/arm/arm-realview-pb1176.dts index efed325af88..d99bac02232 100644 --- a/src/arm/arm/arm-realview-pb1176.dts +++ b/src/arm/arm/arm-realview-pb1176.dts @@ -451,7 +451,7 @@ /* Direct-mapped development chip ROM */ pb1176_rom@10200000 { - compatible = "direct-mapped"; + compatible = "mtd-rom"; reg = <0x10200000 0x4000>; bank-width = <1>; }; diff --git a/src/arm/arm/integratorap-im-pd1.dts b/src/arm/arm/integratorap-im-pd1.dts index 7072a70da00..367850ea091 100644 --- a/src/arm/arm/integratorap-im-pd1.dts +++ b/src/arm/arm/integratorap-im-pd1.dts @@ -129,8 +129,6 @@ bridge { compatible = "ti,ths8134b", "ti,ths8134"; - #address-cells = <1>; - #size-cells = <0>; ports { #address-cells = <1>; @@ -154,6 +152,7 @@ vga { compatible = "vga-connector"; + label = "J30"; port { vga_con_in: endpoint { diff --git a/src/arm/arm/versatile-ab.dts b/src/arm/arm/versatile-ab.dts index f31dcf7e586..de45aa99e26 100644 --- a/src/arm/arm/versatile-ab.dts +++ b/src/arm/arm/versatile-ab.dts @@ -32,8 +32,6 @@ bridge { compatible = "ti,ths8134b", "ti,ths8134"; - #address-cells = <1>; - #size-cells = <0>; ports { #address-cells = <1>; @@ -59,6 +57,7 @@ vga { compatible = "vga-connector"; + label = "J1"; port { vga_con_in: endpoint { diff --git a/src/arm/arm/vexpress-v2p-ca9.dts b/src/arm/arm/vexpress-v2p-ca9.dts index 5916e4877ea..8bf35666412 100644 --- a/src/arm/arm/vexpress-v2p-ca9.dts +++ b/src/arm/arm/vexpress-v2p-ca9.dts @@ -20,7 +20,9 @@ #address-cells = <1>; #size-cells = <1>; - chosen { }; + chosen { + stdout-path = &v2m_serial0; + }; aliases { serial0 = &v2m_serial0; diff --git a/src/arm/broadcom/bcm47622.dtsi b/src/arm/broadcom/bcm47622.dtsi index 7cd38de118c..485863f9c42 100644 --- a/src/arm/broadcom/bcm47622.dtsi +++ b/src/arm/broadcom/bcm47622.dtsi @@ -138,6 +138,20 @@ status = "disabled"; }; + nand_controller: nand-controller@1800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x1800 0x600>, <0x2000 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/src/arm/broadcom/bcm63138.dtsi b/src/arm/broadcom/bcm63138.dtsi index 4ef02283612..e74ba6bf370 100644 --- a/src/arm/broadcom/bcm63138.dtsi +++ b/src/arm/broadcom/bcm63138.dtsi @@ -229,7 +229,12 @@ reg-names = "nand", "nand-int-base"; status = "disabled"; interrupts = ; - interrupt-names = "nand"; + interrupt-names = "nand_ctlrdy"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; }; serial@4400 { diff --git a/src/arm/broadcom/bcm63148.dtsi b/src/arm/broadcom/bcm63148.dtsi index 24431de1810..53703827ee3 100644 --- a/src/arm/broadcom/bcm63148.dtsi +++ b/src/arm/broadcom/bcm63148.dtsi @@ -119,5 +119,19 @@ num-cs = <8>; status = "disabled"; }; + + nand_controller: nand-controller@2000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x2000 0x600>, <0xf0 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; }; }; diff --git a/src/arm/broadcom/bcm63178.dtsi b/src/arm/broadcom/bcm63178.dtsi index 3f9aed96bab..6d8d3349898 100644 --- a/src/arm/broadcom/bcm63178.dtsi +++ b/src/arm/broadcom/bcm63178.dtsi @@ -129,6 +129,20 @@ status = "disabled"; }; + nand_controller: nand-controller@1800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x1800 0x600>, <0x2000 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/src/arm/broadcom/bcm6756.dtsi b/src/arm/broadcom/bcm6756.dtsi index 1d8d957d65d..6433f8fa5ef 100644 --- a/src/arm/broadcom/bcm6756.dtsi +++ b/src/arm/broadcom/bcm6756.dtsi @@ -139,6 +139,20 @@ status = "disabled"; }; + nand_controller: nand-controller@1800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x1800 0x600>, <0x2000 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/src/arm/broadcom/bcm6846.dtsi b/src/arm/broadcom/bcm6846.dtsi index cf92cf8c469..ee361cb00b7 100644 --- a/src/arm/broadcom/bcm6846.dtsi +++ b/src/arm/broadcom/bcm6846.dtsi @@ -119,5 +119,19 @@ num-cs = <8>; status = "disabled"; }; + + nand_controller: nand-controller@1800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x1800 0x600>, <0x2000 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; }; }; diff --git a/src/arm/broadcom/bcm6855.dtsi b/src/arm/broadcom/bcm6855.dtsi index 52d6bc89f9f..52915ec6f33 100644 --- a/src/arm/broadcom/bcm6855.dtsi +++ b/src/arm/broadcom/bcm6855.dtsi @@ -129,6 +129,20 @@ status = "disabled"; }; + nand_controller: nand-controller@1800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x1800 0x600>, <0x2000 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/src/arm/broadcom/bcm6878.dtsi b/src/arm/broadcom/bcm6878.dtsi index 2c5d706bac7..70cf23a65fd 100644 --- a/src/arm/broadcom/bcm6878.dtsi +++ b/src/arm/broadcom/bcm6878.dtsi @@ -120,6 +120,20 @@ status = "disabled"; }; + nand_controller: nand-controller@1800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x1800 0x600>, <0x2000 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/src/arm/broadcom/bcm947622.dts b/src/arm/broadcom/bcm947622.dts index 93b8ce22678..6241485408d 100644 --- a/src/arm/broadcom/bcm947622.dts +++ b/src/arm/broadcom/bcm947622.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/src/arm/broadcom/bcm963138.dts b/src/arm/broadcom/bcm963138.dts index 1b405c24921..7fd87e05ec2 100644 --- a/src/arm/broadcom/bcm963138.dts +++ b/src/arm/broadcom/bcm963138.dts @@ -29,3 +29,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/src/arm/broadcom/bcm963138dvt.dts b/src/arm/broadcom/bcm963138dvt.dts index b5af61853a0..f60d09908ab 100644 --- a/src/arm/broadcom/bcm963138dvt.dts +++ b/src/arm/broadcom/bcm963138dvt.dts @@ -32,15 +32,15 @@ }; &nand_controller { + brcm,wp-not-connected; status = "okay"; +}; - nand@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - brcm,nand-oob-sectors-size = <16>; - }; +&nandcs { + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + brcm,nand-oob-sector-size = <16>; + nand-on-flash-bbt; }; &ahci { diff --git a/src/arm/broadcom/bcm963148.dts b/src/arm/broadcom/bcm963148.dts index 1f5d6d783f0..44bca063a32 100644 --- a/src/arm/broadcom/bcm963148.dts +++ b/src/arm/broadcom/bcm963148.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/src/arm/broadcom/bcm963178.dts b/src/arm/broadcom/bcm963178.dts index d036e99dd8d..098a222cd71 100644 --- a/src/arm/broadcom/bcm963178.dts +++ b/src/arm/broadcom/bcm963178.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/src/arm/broadcom/bcm96756.dts b/src/arm/broadcom/bcm96756.dts index 8b104f3fb14..402038d3cd0 100644 --- a/src/arm/broadcom/bcm96756.dts +++ b/src/arm/broadcom/bcm96756.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/src/arm/broadcom/bcm96846.dts b/src/arm/broadcom/bcm96846.dts index 55852c22960..943896afb7c 100644 --- a/src/arm/broadcom/bcm96846.dts +++ b/src/arm/broadcom/bcm96846.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/src/arm/broadcom/bcm96855.dts b/src/arm/broadcom/bcm96855.dts index 2ad880af210..571663d9a1e 100644 --- a/src/arm/broadcom/bcm96855.dts +++ b/src/arm/broadcom/bcm96855.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/src/arm/broadcom/bcm96878.dts b/src/arm/broadcom/bcm96878.dts index b7af8ade7a9..8d6eddd54c6 100644 --- a/src/arm/broadcom/bcm96878.dts +++ b/src/arm/broadcom/bcm96878.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/src/arm/gemini/gemini-dlink-dir-685.dts b/src/arm/gemini/gemini-dlink-dir-685.dts index 39614966429..b4dbcf8f168 100644 --- a/src/arm/gemini/gemini-dlink-dir-685.dts +++ b/src/arm/gemini/gemini-dlink-dir-685.dts @@ -27,10 +27,10 @@ gpio_keys { compatible = "gpio-keys"; - button-esc { + button-reset { debounce-interval = <100>; wakeup-source; - linux,code = ; + linux,code = ; label = "reset"; /* Collides with LPC_LAD[0], UART DCD, SSP 97RST */ gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; @@ -187,7 +187,7 @@ }; /* This is a RealTek RTL8366RB switch and PHY using SMI over GPIO */ - switch { + ethernet-switch { compatible = "realtek,rtl8366rb"; /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */ mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; @@ -204,36 +204,36 @@ #interrupt-cells = <1>; }; - ports { + ethernet-ports { #address-cells = <1>; #size-cells = <0>; - port@0 { + ethernet-port@0 { reg = <0>; label = "lan0"; phy-handle = <&phy0>; }; - port@1 { + ethernet-port@1 { reg = <1>; label = "lan1"; phy-handle = <&phy1>; }; - port@2 { + ethernet-port@2 { reg = <2>; label = "lan2"; phy-handle = <&phy2>; }; - port@3 { + ethernet-port@3 { reg = <3>; label = "lan3"; phy-handle = <&phy3>; }; - port@4 { + ethernet-port@4 { reg = <4>; label = "wan"; phy-handle = <&phy4>; }; - rtl8366rb_cpu_port: port@5 { + rtl8366rb_cpu_port: ethernet-port@5 { reg = <5>; label = "cpu"; ethernet = <&gmac0>; @@ -252,27 +252,27 @@ #address-cells = <1>; #size-cells = <0>; - phy0: phy@0 { + phy0: ethernet-phy@0 { reg = <0>; interrupt-parent = <&switch_intc>; interrupts = <0>; }; - phy1: phy@1 { + phy1: ethernet-phy@1 { reg = <1>; interrupt-parent = <&switch_intc>; interrupts = <1>; }; - phy2: phy@2 { + phy2: ethernet-phy@2 { reg = <2>; interrupt-parent = <&switch_intc>; interrupts = <2>; }; - phy3: phy@3 { + phy3: ethernet-phy@3 { reg = <3>; interrupt-parent = <&switch_intc>; interrupts = <3>; }; - phy4: phy@4 { + phy4: ethernet-phy@4 { reg = <4>; interrupt-parent = <&switch_intc>; interrupts = <12>; diff --git a/src/arm/gemini/gemini-dlink-dns-313.dts b/src/arm/gemini/gemini-dlink-dns-313.dts index 138c47e1ac1..8c54d3a5a72 100644 --- a/src/arm/gemini/gemini-dlink-dns-313.dts +++ b/src/arm/gemini/gemini-dlink-dns-313.dts @@ -33,10 +33,10 @@ gpio_keys { compatible = "gpio-keys"; - button-esc { + button-reset { debounce-interval = <100>; wakeup-source; - linux,code = ; + linux,code = ; label = "reset"; gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; }; diff --git a/src/arm/gemini/gemini-sl93512r.dts b/src/arm/gemini/gemini-sl93512r.dts index 91c19e8ebfe..4992ec276de 100644 --- a/src/arm/gemini/gemini-sl93512r.dts +++ b/src/arm/gemini/gemini-sl93512r.dts @@ -43,7 +43,7 @@ button-setup { debounce-interval = <50>; wakeup-source; - linux,code = ; + linux,code = ; label = "factory reset"; /* Conflict with NAND flash */ gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; @@ -93,7 +93,7 @@ cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; num-chipselects = <1>; - switch@0 { + ethernet-switch@0 { compatible = "vitesse,vsc7385"; reg = <0>; /* Specified for 2.5 MHz or below */ @@ -101,27 +101,27 @@ gpio-controller; #gpio-cells = <2>; - ports { + ethernet-ports { #address-cells = <1>; #size-cells = <0>; - port@0 { + ethernet-port@0 { reg = <0>; label = "lan1"; }; - port@1 { + ethernet-port@1 { reg = <1>; label = "lan2"; }; - port@2 { + ethernet-port@2 { reg = <2>; label = "lan3"; }; - port@3 { + ethernet-port@3 { reg = <3>; label = "lan4"; }; - vsc: port@6 { + vsc: ethernet-port@6 { reg = <6>; label = "cpu"; ethernet = <&gmac1>; diff --git a/src/arm/gemini/gemini-sq201.dts b/src/arm/gemini/gemini-sq201.dts index d0efd76695d..f8c6f6e5cde 100644 --- a/src/arm/gemini/gemini-sq201.dts +++ b/src/arm/gemini/gemini-sq201.dts @@ -30,7 +30,7 @@ button-setup { debounce-interval = <100>; wakeup-source; - linux,code = ; + linux,code = ; label = "factory reset"; /* Conflict with NAND flash */ gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; @@ -78,7 +78,7 @@ cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; num-chipselects = <1>; - switch@0 { + ethernet-switch@0 { compatible = "vitesse,vsc7395"; reg = <0>; /* Specified for 2.5 MHz or below */ @@ -86,27 +86,27 @@ gpio-controller; #gpio-cells = <2>; - ports { + ethernet-ports { #address-cells = <1>; #size-cells = <0>; - port@0 { + ethernet-port@0 { reg = <0>; label = "lan1"; }; - port@1 { + ethernet-port@1 { reg = <1>; label = "lan2"; }; - port@2 { + ethernet-port@2 { reg = <2>; label = "lan3"; }; - port@3 { + ethernet-port@3 { reg = <3>; label = "lan4"; }; - vsc: port@6 { + vsc: ethernet-port@6 { reg = <6>; label = "cpu"; ethernet = <&gmac1>; diff --git a/src/arm/gemini/gemini-wbd111.dts b/src/arm/gemini/gemini-wbd111.dts index 3c88c59ab48..6a0c89e0c91 100644 --- a/src/arm/gemini/gemini-wbd111.dts +++ b/src/arm/gemini/gemini-wbd111.dts @@ -10,7 +10,7 @@ / { model = "Wiliboard WBD-111"; - compatible = "wiliboard,wbd111", "cortina,gemini"; + compatible = "wiligear,wiliboard-wbd111", "cortina,gemini"; #address-cells = <1>; #size-cells = <1>; @@ -28,10 +28,10 @@ gpio_keys { compatible = "gpio-keys"; - button-setup { + button-reset { debounce-interval = <100>; wakeup-source; - linux,code = ; + linux,code = ; label = "reset"; /* Conflict with ICE */ gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; diff --git a/src/arm/gemini/gemini-wbd222.dts b/src/arm/gemini/gemini-wbd222.dts index ff72bbc4db3..d8b34ebad4b 100644 --- a/src/arm/gemini/gemini-wbd222.dts +++ b/src/arm/gemini/gemini-wbd222.dts @@ -10,7 +10,7 @@ / { model = "Wiliboard WBD-222"; - compatible = "wiliboard,wbd222", "cortina,gemini"; + compatible = "wiligear,wiliboard-wbd222", "cortina,gemini"; #address-cells = <1>; #size-cells = <1>; @@ -27,10 +27,10 @@ gpio_keys { compatible = "gpio-keys"; - button-setup { + button-reset { debounce-interval = <100>; wakeup-source; - linux,code = ; + linux,code = ; label = "reset"; /* Conflict with ICE */ gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; diff --git a/src/arm/marvell/armada-385-clearfog-gtr-l8.dts b/src/arm/marvell/armada-385-clearfog-gtr-l8.dts index 1707d1b0154..cb85f8e31df 100644 --- a/src/arm/marvell/armada-385-clearfog-gtr-l8.dts +++ b/src/arm/marvell/armada-385-clearfog-gtr-l8.dts @@ -4,6 +4,18 @@ / { model = "SolidRun Clearfog GTR L8"; + compatible = "solidrun,clearfog-gtr-l8", "marvell,armada385", + "marvell,armada380"; + + /* CON25 */ + sfp1: sfp-1 { + compatible = "sff,sfp"; + pinctrl-0 = <&cf_gtr_sfp1_pins>; + pinctrl-names = "default"; + i2c-bus = <&i2c0>; + mod-def0-gpio = <&gpio0 24 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; + }; }; &mdio { @@ -20,57 +32,65 @@ ethernet-port@1 { reg = <1>; - label = "lan8"; + label = "lan1"; phy-handle = <&switch0phy0>; }; ethernet-port@2 { reg = <2>; - label = "lan7"; + label = "lan2"; phy-handle = <&switch0phy1>; }; ethernet-port@3 { reg = <3>; - label = "lan6"; + label = "lan3"; phy-handle = <&switch0phy2>; }; ethernet-port@4 { reg = <4>; - label = "lan5"; + label = "lan4"; phy-handle = <&switch0phy3>; }; ethernet-port@5 { reg = <5>; - label = "lan4"; + label = "lan5"; phy-handle = <&switch0phy4>; }; ethernet-port@6 { reg = <6>; - label = "lan3"; + label = "lan6"; phy-handle = <&switch0phy5>; }; ethernet-port@7 { reg = <7>; - label = "lan2"; + label = "lan7"; phy-handle = <&switch0phy6>; }; ethernet-port@8 { reg = <8>; - label = "lan1"; + label = "lan8"; phy-handle = <&switch0phy7>; }; + ethernet-port@9 { + reg = <9>; + label = "lan-sfp"; + phy-mode = "sgmii"; + sfp = <&sfp1>; + managed = "in-band-status"; + }; + ethernet-port@10 { reg = <10>; phy-mode = "2500base-x"; - ethernet = <ð1>; + fixed-link { speed = <2500>; full-duplex; diff --git a/src/arm/marvell/armada-385-clearfog-gtr-s4.dts b/src/arm/marvell/armada-385-clearfog-gtr-s4.dts index a7678a784c1..5f83d981449 100644 --- a/src/arm/marvell/armada-385-clearfog-gtr-s4.dts +++ b/src/arm/marvell/armada-385-clearfog-gtr-s4.dts @@ -4,6 +4,8 @@ / { model = "SolidRun Clearfog GTR S4"; + compatible = "solidrun,clearfog-gtr-s4", "marvell,armada385", + "marvell,armada380"; }; &sfp0 { diff --git a/src/arm/marvell/armada-385-clearfog-gtr.dtsi b/src/arm/marvell/armada-385-clearfog-gtr.dtsi index d1452a04e90..f3a3cb6ac31 100644 --- a/src/arm/marvell/armada-385-clearfog-gtr.dtsi +++ b/src/arm/marvell/armada-385-clearfog-gtr.dtsi @@ -141,6 +141,77 @@ }; pinctrl@18000 { + cf_gtr_fan_pwm: cf-gtr-fan-pwm { + marvell,pins = "mpp23"; + marvell,function = "gpio"; + }; + + cf_gtr_front_button_pins: cf-gtr-front-button-pins { + marvell,pins = "mpp53"; + marvell,function = "gpio"; + }; + + cf_gtr_i2c1_pins: i2c1-pins { + /* SFP */ + marvell,pins = "mpp26", "mpp27"; + marvell,function = "i2c1"; + }; + + cf_gtr_isolation_pins: cf-gtr-isolation-pins { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + + cf_gtr_led_pins: led-pins { + marvell,pins = "mpp42", "mpp52"; + marvell,function = "gpio"; + }; + + cf_gtr_lte_disable_pins: lte-disable-pins { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + + cf_gtr_pci_pins: pci-pins { + // pci reset + marvell,pins = "mpp33", "mpp35", "mpp44"; + marvell,function = "gpio"; + }; + + cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + + cf_gtr_rear_button_pins: cf-gtr-rear-button-pins { + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + + cf_gtr_sdhci_pins: cf-gtr-sdhci-pins { + marvell,pins = "mpp21", "mpp28", + "mpp37", "mpp38", + "mpp39", "mpp40"; + marvell,function = "sd0"; + }; + + cf_gtr_sfp0_pins: sfp0-pins { + /* sfp modabs, txdisable */ + marvell,pins = "mpp25", "mpp46"; + marvell,function = "gpio"; + }; + + cf_gtr_sfp1_pins: sfp1-pins { + /* sfp modabs, txdisable */ + marvell,pins = "mpp24", "mpp54"; + marvell,function = "gpio"; + }; + + cf_gtr_spi1_cs_pins: spi1-cs-pins { + marvell,pins = "mpp59"; + marvell,function = "spi1"; + }; + cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins { marvell,pins = "mpp18"; marvell,function = "gpio"; @@ -151,46 +222,8 @@ marvell,function = "gpio"; }; - cf_gtr_fan_pwm: cf-gtr-fan-pwm { - marvell,pins = "mpp23"; - marvell,function = "gpio"; - }; - - cf_gtr_i2c1_pins: i2c1-pins { - /* SFP */ - marvell,pins = "mpp26", "mpp27"; - marvell,function = "i2c1"; - }; - - cf_gtr_sdhci_pins: cf-gtr-sdhci-pins { - marvell,pins = "mpp21", "mpp28", - "mpp37", "mpp38", - "mpp39", "mpp40"; - marvell,function = "sd0"; - }; - - cf_gtr_isolation_pins: cf-gtr-isolation-pins { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - - cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - - cf_gtr_spi1_cs_pins: spi1-cs-pins { - marvell,pins = "mpp59"; - marvell,function = "spi1"; - }; - - cf_gtr_front_button_pins: cf-gtr-front-button-pins { - marvell,pins = "mpp53"; - marvell,function = "gpio"; - }; - - cf_gtr_rear_button_pins: cf-gtr-rear-button-pins { - marvell,pins = "mpp36"; + cf_gtr_wifi_disable_pins: wifi-disable-pins { + marvell,pins = "mpp30", "mpp31"; marvell,function = "gpio"; }; }; @@ -221,21 +254,26 @@ }; pcie { + pinctrl-0 = <&cf_gtr_pci_pins>; + pinctrl-names = "default"; status = "okay"; /* * The PCIe units are accessible through * the mini-PCIe connectors on the board. */ + /* CON3 - serdes 0 */ pcie@1,0 { reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; status = "okay"; }; + /* CON4 - serdes 2 */ pcie@2,0 { reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; status = "okay"; }; + /* CON2 - serdes 4 */ pcie@3,0 { reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; status = "okay"; @@ -243,10 +281,12 @@ }; }; - sfp0: sfp { + /* CON5 */ + sfp0: sfp-0 { compatible = "sff,sfp"; + pinctrl-0 = <&cf_gtr_sfp0_pins>; + pinctrl-names = "default"; i2c-bus = <&i2c1>; - los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>; tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; }; @@ -273,6 +313,8 @@ gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = <&cf_gtr_led_pins>; + pinctrl-names = "default"; led1 { function = LED_FUNCTION_CPU; @@ -408,7 +450,7 @@ }; &gpio0 { - pinctrl-0 = <&cf_gtr_fan_pwm>; + pinctrl-0 = <&cf_gtr_fan_pwm &cf_gtr_wifi_disable_pins>; pinctrl-names = "default"; wifi-disable { @@ -420,7 +462,7 @@ }; &gpio1 { - pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins>; + pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins &cf_gtr_lte_disable_pins>; pinctrl-names = "default"; lte-disable { diff --git a/src/arm/marvell/armada-388-clearfog.dts b/src/arm/marvell/armada-388-clearfog.dts index 3290ccad237..09bf2e6d4ed 100644 --- a/src/arm/marvell/armada-388-clearfog.dts +++ b/src/arm/marvell/armada-388-clearfog.dts @@ -10,8 +10,9 @@ / { model = "SolidRun Clearfog A1"; - compatible = "solidrun,clearfog-a1", "marvell,armada388", - "marvell,armada385", "marvell,armada380"; + compatible = "solidrun,clearfog-pro-a1", "solidrun,clearfog-a1", + "marvell,armada388", "marvell,armada385", + "marvell,armada380"; soc { internal-regs { diff --git a/src/arm/marvell/dove-cubox.dts b/src/arm/marvell/dove-cubox.dts index bfde99486a8..bcaaf8320c4 100644 --- a/src/arm/marvell/dove-cubox.dts +++ b/src/arm/marvell/dove-cubox.dts @@ -101,7 +101,7 @@ /* connect xtal input as source of pll0 and pll1 */ silabs,pll-source = <0 0>, <1 0>; - clkout0 { + clkout@0 { reg = <0>; silabs,drive-strength = <8>; silabs,multisynth-source = <0>; @@ -109,7 +109,7 @@ silabs,pll-master; }; - clkout2 { + clkout@2 { reg = <2>; silabs,drive-strength = <8>; silabs,multisynth-source = <1>; diff --git a/src/arm/marvell/mmp2-brownstone.dts b/src/arm/marvell/mmp2-brownstone.dts index 04f1ae1382e..bc64348b821 100644 --- a/src/arm/marvell/mmp2-brownstone.dts +++ b/src/arm/marvell/mmp2-brownstone.dts @@ -28,7 +28,7 @@ &twsi1 { status = "okay"; pmic: max8925@3c { - compatible = "maxium,max8925"; + compatible = "maxim,max8925"; reg = <0x3c>; interrupts = <1>; interrupt-parent = <&intcmux4>; diff --git a/src/arm/microchip/at91-sama7g54_curiosity.dts b/src/arm/microchip/at91-sama7g54_curiosity.dts new file mode 100644 index 00000000000..009d2c83242 --- /dev/null +++ b/src/arm/microchip/at91-sama7g54_curiosity.dts @@ -0,0 +1,482 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sama7g54_curiosity.dts - Device Tree file for SAMA7G54 Curiosity Board + * + * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries + * + * Author: Mihai Sain + * + */ +/dts-v1/; +#include "sama7g5-pinfunc.h" +#include "sama7g5.dtsi" +#include +#include +#include +#include + +/ { + model = "Microchip SAMA7G54 Curiosity"; + compatible = "microchip,sama7g54-curiosity", "microchip,sama7g5", "microchip,sama7"; + + aliases { + serial0 = &uart3; + i2c0 = &i2c10; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio_default>; + + button-user { + label = "user-button"; + gpios = <&pioA PIN_PD19 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_gpio_default>; + + led-red { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&pioA PIN_PD13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-green { + color = ; + function = LED_FUNCTION_BOOT; + gpios = <&pioA PIN_PD14 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-blue { + color = ; + function = LED_FUNCTION_CPU; + gpios = <&pioA PIN_PB15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x10000000>; /* 256 MiB DDR3L-1066 16-bit */ + }; +}; + +&adc { + vddana-supply = <&vddout25>; + vref-supply = <&vddout25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_an_default &pinctrl_mikrobus2_an_default>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vddcpu>; +}; + +&dma0 { + status = "okay"; +}; + +&dma1 { + status = "okay"; +}; + +&dma2 { + status = "okay"; +}; + +&ebi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand_default>; + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "nand: at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "nand: u-boot"; + reg = <0x40000 0x100000>; + }; + + bootloaderenv@140000 { + label = "nand: u-boot env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "nand: device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "nand: kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "nand: rootfs"; + reg = <0x800000 0x1f800000>; + }; + }; + }; + }; +}; + +&flx3 { + atmel,flexcom-mode = ; + status = "okay"; + + uart3: serial@200 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx3_default>; + status = "okay"; + }; +}; + +&flx10 { + atmel,flexcom-mode = ; + status = "okay"; + + i2c10: i2c@600 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx10_default>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + size = <256>; + vcc-supply = <&vdd_3v3>; + }; + + pmic@5b { + compatible = "microchip,mcp16502"; + reg = <0x5b>; + + regulators { + vdd_3v3: VDD_IO { + regulator-name = "VDD_IO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + vddioddr: VDD_DDR { + regulator-name = "VDD_DDR"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1350000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1350000>; + regulator-mode = <4>; + }; + }; + + vddcore: VDD_CORE { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1150000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + vddcpu: VDD_OTHER { + regulator-name = "VDD_OTHER"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1250000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-ramp-delay = <3125>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1050000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + vldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-standby { + regulator-suspend-microvolt = <1800000>; + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + regulator-state-standby { + regulator-suspend-microvolt = <3300000>; + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + }; +}; + +&main_xtal { + clock-frequency = <24000000>; +}; + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_default>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <100000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + }; +}; + +&pioA { + pinctrl_flx3_default: flx3-default { + pinmux = , + ; + bias-pull-up; + }; + + pinctrl_flx10_default: flx10-default { + pinmux = , + ; + bias-pull-up; + }; + + pinctrl_key_gpio_default: key-gpio-default { + pinmux = ; + bias-pull-up; + }; + + pinctrl_led_gpio_default: led-gpio-default { + pinmux = , + , + ; + bias-pull-up; + }; + + pinctrl_mikrobus1_an_default: mikrobus1-an-default { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_an_default: mikrobus2-an-default { + pinmux = ; + bias-disable; + }; + + pinctrl_nand_default: nand-default { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + bias-disable; + slew-rate = <0>; + }; + + pinctrl_qspi1_default: qspi1-default { + pinmux = , + , + , + , + , + ; + bias-pull-up; + slew-rate = <0>; + }; + + pinctrl_sdmmc0_default: sdmmc0-default { + pinmux = , + , + , + , + , + , + ; + bias-pull-up; + slew-rate = <0>; + }; + + pinctrl_sdmmc1_default: sdmmc1-default { + pinmux = , + , + , + , + , + , + ; + bias-pull-up; + slew-rate = <0>; + }; +}; + +&rtt { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; +}; + +/* M.2 slot for wireless card */ +&sdmmc0 { + bus-width = <4>; + cd-gpios = <&pioA 31 GPIO_ACTIVE_LOW>; + disable-wp; + sdhci-caps-mask = <0x0 0x00200000>; + vmmc-supply = <&vdd_3v3>; + vqmmc-supply = <&vdd_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_default>; + status = "okay"; +}; + +/* micro SD socket */ +&sdmmc1 { + bus-width = <4>; + disable-wp; + sdhci-caps-mask = <0x0 0x00200000>; + vmmc-supply = <&vdd_3v3>; + vqmmc-supply = <&vdd_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc1_default>; + status = "okay"; +}; + +&slow_xtal { + clock-frequency = <32768>; +}; + +&shdwc { + debounce-delay-us = <976>; + status = "okay"; + + input@0 { + reg = <0>; + }; +}; + +&tcb0 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + +&trng { + status = "okay"; +}; + +&vddout25 { + vin-supply = <&vdd_3v3>; + status = "okay"; +}; diff --git a/src/arm/microchip/at91-sama7g5ek.dts b/src/arm/microchip/at91-sama7g5ek.dts index 217e9b96c61..20b2497657a 100644 --- a/src/arm/microchip/at91-sama7g5ek.dts +++ b/src/arm/microchip/at91-sama7g5ek.dts @@ -293,7 +293,7 @@ regulator-state-standby { regulator-on-in-suspend; - regulator-suspend-voltage = <1150000>; + regulator-suspend-microvolt = <1150000>; regulator-mode = <4>; }; @@ -314,7 +314,7 @@ regulator-state-standby { regulator-on-in-suspend; - regulator-suspend-voltage = <1050000>; + regulator-suspend-microvolt = <1050000>; regulator-mode = <4>; }; @@ -331,7 +331,7 @@ regulator-always-on; regulator-state-standby { - regulator-suspend-voltage = <1800000>; + regulator-suspend-microvolt = <1800000>; regulator-on-in-suspend; }; @@ -346,7 +346,7 @@ regulator-max-microvolt = <3700000>; regulator-state-standby { - regulator-suspend-voltage = <1800000>; + regulator-suspend-microvolt = <1800000>; regulator-on-in-suspend; }; diff --git a/src/arm/microchip/at91sam9g25-gardena-smart-gateway.dts b/src/arm/microchip/at91sam9g25-gardena-smart-gateway.dts index 92f2c05c873..af70eb8a3a0 100644 --- a/src/arm/microchip/at91sam9g25-gardena-smart-gateway.dts +++ b/src/arm/microchip/at91sam9g25-gardena-smart-gateway.dts @@ -121,6 +121,8 @@ }; &usart3 { + atmel,use-dma-rx; + atmel,use-dma-tx; status = "okay"; pinctrl-0 = <&pinctrl_usart3 diff --git a/src/arm/microchip/at91sam9x5ek.dtsi b/src/arm/microchip/at91sam9x5ek.dtsi index 5f4eaa618ab..9618b8d965b 100644 --- a/src/arm/microchip/at91sam9x5ek.dtsi +++ b/src/arm/microchip/at91sam9x5ek.dtsi @@ -39,6 +39,8 @@ }; &dbgu { + atmel,use-dma-rx; + atmel,use-dma-tx; status = "okay"; }; diff --git a/src/arm/microchip/sam9x60.dtsi b/src/arm/microchip/sam9x60.dtsi index 73d570a1726..291540e5d81 100644 --- a/src/arm/microchip/sam9x60.dtsi +++ b/src/arm/microchip/sam9x60.dtsi @@ -179,7 +179,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(8))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(9))>; @@ -202,7 +202,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(8))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(9))>; @@ -220,7 +220,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(8))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(9))>; @@ -248,7 +248,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(10))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(11))>; @@ -271,7 +271,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(10))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(11))>; @@ -289,7 +289,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(10))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(11))>; @@ -377,7 +377,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(22))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(23))>; @@ -399,7 +399,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(22))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(23))>; @@ -426,7 +426,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(24))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; @@ -448,7 +448,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(24))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; @@ -583,7 +583,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(12))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(13))>; @@ -605,7 +605,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(12))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(13))>; @@ -632,7 +632,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(14))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(15))>; @@ -654,7 +654,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(14))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(15))>; @@ -681,7 +681,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(16))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(17))>; @@ -703,7 +703,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(16))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(17))>; @@ -730,7 +730,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(0))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(1))>; @@ -753,7 +753,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(0))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(1))>; @@ -771,7 +771,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(0))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(1))>; @@ -798,7 +798,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(2))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(3))>; @@ -821,7 +821,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(2))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(3))>; @@ -839,7 +839,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(2))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(3))>; @@ -866,7 +866,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(4))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(5))>; @@ -889,7 +889,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(4))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(5))>; @@ -907,7 +907,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(4))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(5))>; @@ -934,7 +934,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(6))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(7))>; @@ -957,7 +957,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(6))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(7))>; @@ -975,7 +975,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(6))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(7))>; @@ -1057,7 +1057,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(18))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(19))>; @@ -1079,7 +1079,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(18))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(19))>; @@ -1106,7 +1106,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(20))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(21))>; @@ -1128,7 +1128,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(20))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(21))>; diff --git a/src/arm/microchip/sama7g5.dtsi b/src/arm/microchip/sama7g5.dtsi index 269e0a3ca26..75778be126a 100644 --- a/src/arm/microchip/sama7g5.dtsi +++ b/src/arm/microchip/sama7g5.dtsi @@ -698,7 +698,7 @@ }; flx0: flexcom@e1818000 { - compatible = "atmel,sama5d2-flexcom"; + compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe1818000 0x200>; clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; #address-cells = <1>; @@ -714,7 +714,7 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; clock-names = "usart"; dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, - <&dma1 AT91_XDMAC_DT_PERID(5)>; + <&dma1 AT91_XDMAC_DT_PERID(5)>; dma-names = "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; @@ -723,7 +723,7 @@ }; flx1: flexcom@e181c000 { - compatible = "atmel,sama5d2-flexcom"; + compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe181c000 0x200>; clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; #address-cells = <1>; @@ -740,14 +740,14 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; atmel,fifo-size = <32>; dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, - <&dma0 AT91_XDMAC_DT_PERID(7)>; + <&dma0 AT91_XDMAC_DT_PERID(7)>; dma-names = "tx", "rx"; status = "disabled"; }; }; flx3: flexcom@e1824000 { - compatible = "atmel,sama5d2-flexcom"; + compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe1824000 0x200>; clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; #address-cells = <1>; @@ -763,7 +763,7 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; clock-names = "usart"; dmas = <&dma1 AT91_XDMAC_DT_PERID(12)>, - <&dma1 AT91_XDMAC_DT_PERID(11)>; + <&dma1 AT91_XDMAC_DT_PERID(11)>; dma-names = "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; @@ -791,7 +791,7 @@ }; flx4: flexcom@e2018000 { - compatible = "atmel,sama5d2-flexcom"; + compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe2018000 0x200>; clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; #address-cells = <1>; @@ -807,7 +807,7 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; clock-names = "usart"; dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, - <&dma1 AT91_XDMAC_DT_PERID(13)>; + <&dma1 AT91_XDMAC_DT_PERID(13)>; dma-names = "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; @@ -817,7 +817,7 @@ }; flx7: flexcom@e2024000 { - compatible = "atmel,sama5d2-flexcom"; + compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe2024000 0x200>; clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; #address-cells = <1>; @@ -833,7 +833,7 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; clock-names = "usart"; dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, - <&dma1 AT91_XDMAC_DT_PERID(19)>; + <&dma1 AT91_XDMAC_DT_PERID(19)>; dma-names = "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; @@ -911,7 +911,7 @@ }; flx8: flexcom@e2818000 { - compatible = "atmel,sama5d2-flexcom"; + compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe2818000 0x200>; clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; #address-cells = <1>; @@ -928,14 +928,14 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; atmel,fifo-size = <32>; dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, - <&dma0 AT91_XDMAC_DT_PERID(21)>; + <&dma0 AT91_XDMAC_DT_PERID(21)>; dma-names = "tx", "rx"; status = "disabled"; }; }; flx9: flexcom@e281c000 { - compatible = "atmel,sama5d2-flexcom"; + compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe281c000 0x200>; clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; #address-cells = <1>; @@ -952,14 +952,38 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; atmel,fifo-size = <32>; dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, - <&dma0 AT91_XDMAC_DT_PERID(23)>; + <&dma0 AT91_XDMAC_DT_PERID(23)>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + flx10: flexcom@e2820000 { + compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe2820000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 48>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe2820000 0x800>; + status = "disabled"; + + i2c10: i2c@600 { + compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 48>; + atmel,fifo-size = <32>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(26)>, + <&dma0 AT91_XDMAC_DT_PERID(25)>; dma-names = "tx", "rx"; status = "disabled"; }; }; flx11: flexcom@e2824000 { - compatible = "atmel,sama5d2-flexcom"; + compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe2824000 0x200>; clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; #address-cells = <1>; @@ -977,7 +1001,7 @@ #size-cells = <0>; atmel,fifo-size = <32>; dmas = <&dma0 AT91_XDMAC_DT_PERID(28)>, - <&dma0 AT91_XDMAC_DT_PERID(27)>; + <&dma0 AT91_XDMAC_DT_PERID(27)>; dma-names = "tx", "rx"; status = "disabled"; }; diff --git a/src/arm/nvidia/tegra124-nyan.dtsi b/src/arm/nvidia/tegra124-nyan.dtsi index a2ee3718020..8125c1b3e8d 100644 --- a/src/arm/nvidia/tegra124-nyan.dtsi +++ b/src/arm/nvidia/tegra124-nyan.dtsi @@ -338,6 +338,7 @@ interrupt-parent = <&gpio>; interrupts = ; reg = <0>; + wakeup-source; google,cros-ec-spi-msg-delay = <2000>; diff --git a/src/arm/nvidia/tegra124-venice2.dts b/src/arm/nvidia/tegra124-venice2.dts index 3924ee385de..df98dc2a67b 100644 --- a/src/arm/nvidia/tegra124-venice2.dts +++ b/src/arm/nvidia/tegra124-venice2.dts @@ -857,6 +857,7 @@ interrupt-parent = <&gpio>; interrupts = ; reg = <0>; + wakeup-source; google,cros-ec-spi-msg-delay = <2000>; diff --git a/src/arm/nvidia/tegra30-asus-nexus7-grouper-common.dtsi b/src/arm/nvidia/tegra30-asus-nexus7-grouper-common.dtsi index a9342e04b14..15f53babdc2 100644 --- a/src/arm/nvidia/tegra30-asus-nexus7-grouper-common.dtsi +++ b/src/arm/nvidia/tegra30-asus-nexus7-grouper-common.dtsi @@ -915,6 +915,9 @@ reg = <0x1c>; realtek,dmic1-data-pin = <1>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "mclk"; }; nct72: temperature-sensor@4c { diff --git a/src/arm/nvidia/tegra30-lg-p880.dts b/src/arm/nvidia/tegra30-lg-p880.dts new file mode 100644 index 00000000000..2f7754fd42a --- /dev/null +++ b/src/arm/nvidia/tegra30-lg-p880.dts @@ -0,0 +1,489 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-lg-x3.dtsi" + +/ { + model = "LG Optimus 4X HD P880"; + compatible = "lg,p880", "nvidia,tegra30"; + + aliases { + mmc1 = &sdmmc3; /* uSD slot */ + mmc2 = &sdmmc1; /* WiFi */ + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* WLAN SDIO pinmux */ + host-wlan-wake { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GNSS UART-B pinmux */ + uartb-rxd { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uartb-txd { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gps-reset { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MicroSD pinmux */ + sdmmc3-clk { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3-data { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + microsd-detect { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GPIO keys pinmux */ + volume-up { + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Sensors pinmux */ + current-alert-irq { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* AUDIO pinmux */ + sub-mic-ldo { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + i2c@7000c400 { + touchscreen@20 { + rmi4-f11@11 { + syna,clip-x-high = <1110>; + syna,clip-y-high = <1973>; + + touchscreen-inverted-y; + }; + }; + }; + + memory-controller@7000f000 { + emc-timings-0 { + /* SAMSUNG 1GB K4P8G304EB FGC1 533MHz */ + nvidia,ram-code = <0>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < 0x00050001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x77230303 0x001f0000 >; + }; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-266500000 { + clock-frequency = <266500000>; + + nvidia,emem-configuration = < 0x00000004 0xC0000030 + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000006 0x00000001 0x00000002 0x00000005 + 0x00000001 0x00000000 0x00000003 0x00000003 + 0x03030001 0x00090608 0x70040c09 0x001f0000 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emem-configuration = < 0x00000008 0xC0000060 + 0x00000003 0x00000004 0x00000010 0x0000000a + 0x0000000d 0x00000002 0x00000002 0x00000008 + 0x00000002 0x00000000 0x00000004 0x00000005 + 0x05040002 0x00110b10 0x70281811 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + /* SAMSUNG 1GB K4P8G304EB FGC1 533MHz */ + nvidia,ram-code = <0>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000000 + 0x00000001 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x0000002f 0x00000000 0x0000000b + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000002 0x00000002 + 0x00000003 0x00000008 0x00000004 0x00000001 + 0x00000002 0x00000036 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000009 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000164 0xe0000000 0xff00ff00 >; + }; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000001 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000001 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000001 + 0x00000002 0x000001a9 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000025 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000c + 0x0000000a 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000001 + 0x00000002 0x00000351 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x004400a4 + 0x00008000 0x00070000 0x00070000 0x00070000 + 0x00070000 0x00070000 0x00070000 0x00070000 + 0x00070000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000e0220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000004a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; + }; + + timing-266500000 { + clock-frequency = <266500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020002>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000018>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000f + 0x00000022 0x0000000b 0x00000004 0x00000005 + 0x00000005 0x00000001 0x00000007 0x00000004 + 0x00000004 0x00000002 0x00000002 0x00000000 + 0x00000002 0x00000005 0x00000002 0x0000000c + 0x0000000b 0x000003ef 0x00000000 0x000000fb + 0x00000001 0x00000001 0x00000004 0x00000000 + 0x00000001 0x00000009 0x00000026 0x00000026 + 0x00000004 0x0000000e 0x00000006 0x00000001 + 0x00000002 0x00000455 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00006282 0x003200a4 + 0x00008000 0x00050000 0x00050000 0x00050000 + 0x00050000 0x00050000 0x00050000 0x00050000 + 0x00050000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00060000 0x00060000 0x00060000 + 0x00060000 0x000b0220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000060 0x000a000a 0xa0f10000 0x00000000 + 0x00000000 0x800008ee 0xe0000000 0xff00ff00 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x000100c2>; + nvidia,emc-mode-2 = <0x00020006>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000030>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000045 0x00000016 0x00000009 0x00000008 + 0x00000009 0x00000003 0x0000000d 0x00000009 + 0x00000009 0x00000005 0x00000003 0x00000000 + 0x00000004 0x00000009 0x00000006 0x0000000d + 0x00000010 0x000007df 0x00000000 0x000001f7 + 0x00000003 0x00000003 0x00000009 0x00000000 + 0x00000001 0x0000000f 0x0000004b 0x0000004b + 0x00000008 0x0000001b 0x0000000c 0x00000001 + 0x00000002 0x000008aa 0x00000000 0x00000006 + 0x00000000 0x00000000 0x00006282 0xf0120091 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00090220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x000000c0 0x000e000e 0xa0f10000 0x00000000 + 0x00000000 0x800010d9 0xe0000000 0xff00ff88 >; + }; + }; + }; + + sdmmc3: mmc@78000400 { + status = "okay"; + + cd-gpios = <&gpio TEGRA_GPIO(W, 5) GPIO_ACTIVE_LOW>; + bus-width = <4>; + + vmmc-supply = <&vdd_usd>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + battery: battery-cell { + compatible = "simple-battery"; + device-chemistry = "lithium-ion"; + charge-full-design-microamp-hours = <2150000>; + energy-full-design-microwatt-hours = <8200000>; + operating-range-celsius = <0 45>; + }; + + gpio-keys { + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(O, 7) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + }; + + sound { + compatible = "lg,tegra-audio-max98089-p880", + "nvidia,tegra-audio-max98089"; + nvidia,model = "LG Optimus 4X HD MAX98089"; + + nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/src/arm/nvidia/tegra30-lg-p895.dts b/src/arm/nvidia/tegra30-lg-p895.dts new file mode 100644 index 00000000000..e32fafc7f5e --- /dev/null +++ b/src/arm/nvidia/tegra30-lg-p895.dts @@ -0,0 +1,496 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-lg-x3.dtsi" + +/ { + model = "LG Optimus Vu P895"; + compatible = "lg,p895", "nvidia,tegra30"; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* GNSS UART-B pinmux */ + uartb-cts-rxd { + nvidia,pins = "uart2_cts_n_pj5", + "uart2_rxd_pc3"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uartb-rts-txd { + nvidia,pins = "uart2_rts_n_pj6", + "uart2_txd_pc2"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gps-reset { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GPIO keys pinmux */ + memo-key { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + volume-up { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Sensors pinmux */ + current-alert-irq { + nvidia,pins = "spi1_cs0_n_px6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Panel pinmux */ + panel-vdd { + nvidia,pins = "pbb0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* AUDIO pinmux */ + sub-mic-ldo { + nvidia,pins = "gmi_dqs_pi2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Modem pinmux */ + usim-detect { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GPIO power/drive control */ + drive-sdmmc4 { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + }; + + i2c@7000c400 { + touchscreen@20 { + rmi4-f11@11 { + syna,clip-x-high = <1535>; + syna,clip-y-high = <2047>; + }; + }; + }; + + memory-controller@7000f000 { + emc-timings-2 { + /* Hynix 1GB H9TCNNN8JDMMPR LPDDR2 533MHz */ + nvidia,ram-code = <2>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x77230303 0x001f0000 >; + }; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00030003 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010003 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000006 0xc0000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-266500000 { + clock-frequency = <266500000>; + + nvidia,emem-configuration = < 0x00000008 0xc0000030 + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000006 0x00000001 0x00000002 0x00000005 + 0x00000001 0x00000000 0x00000003 0x00000003 + 0x03030001 0x00090608 0x70040c09 0x001f0000 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emem-configuration = < 0x0000000f 0xc0000060 + 0x00000003 0x00000004 0x00000010 0x0000000a + 0x0000000d 0x00000002 0x00000002 0x00000008 + 0x00000002 0x00000000 0x00000004 0x00000005 + 0x05040002 0x00110b10 0x70281811 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-2 { + /* Hynix 1GB H9TCNNN8JDMMPR LPDDR2 533MHz */ + nvidia,ram-code = <2>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000000 + 0x00000001 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x0000002f 0x00000000 0x0000000b + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000002 0x00000002 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x00000036 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000009 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000164 0xe0000000 0xff00ff00 >; + }; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xd0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xd0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000001a9 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000025 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xd0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000004 0x00000001 0x0000000c + 0x0000000a 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000004 + 0x00000002 0x00000351 0x00000005 0x00000004 + 0x00000000 0x00000000 0x00004282 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00072000 0x00072000 0x00072000 + 0x00072000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000e0220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000004a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; + }; + + timing-266500000 { + clock-frequency = <266500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020002>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000018>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000f + 0x00000022 0x0000000b 0x00000004 0x00000005 + 0x00000005 0x00000001 0x00000007 0x00000004 + 0x00000004 0x00000002 0x00000002 0x00000000 + 0x00000002 0x00000005 0x00000002 0x0000000c + 0x0000000b 0x000003ef 0x00000000 0x000000fb + 0x00000001 0x00000001 0x00000004 0x00000000 + 0x00000001 0x00000009 0x00000026 0x00000026 + 0x00000004 0x0000000e 0x00000006 0x00000004 + 0x00000002 0x00000455 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00006282 0x003200a4 + 0x00008000 0x00070000 0x00070000 0x00070000 + 0x00070000 0x00072000 0x00072000 0x00072000 + 0x00072000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080002 0x00080002 0x00080002 + 0x00080002 0x000e0220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000060 0x000a000a 0xa0f10000 0x00000000 + 0x00000000 0x800008ee 0xe0000000 0xff00ff00 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x000100c2>; + nvidia,emc-mode-2 = <0x00020006>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000030>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000045 0x00000016 0x00000009 0x00000008 + 0x00000009 0x00000003 0x0000000d 0x00000009 + 0x00000009 0x00000005 0x00000003 0x00000000 + 0x00000004 0x0000000a 0x00000006 0x0000000d + 0x00000010 0x000007df 0x00000000 0x000001f7 + 0x00000003 0x00000003 0x00000009 0x00000000 + 0x00000001 0x0000000f 0x0000004b 0x0000004b + 0x00000008 0x0000001b 0x0000000c 0x00000004 + 0x00000002 0x000008aa 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00006282 0xf0120091 + 0x00008000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x000c0220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x000000c0 0x000e000e 0xa0f10000 0x00000000 + 0x00000000 0x800010d9 0xe0000000 0xff00ff88 >; + }; + }; + }; + + battery: battery-cell { + compatible = "simple-battery"; + device-chemistry = "lithium-ion"; + charge-full-design-microamp-hours = <2080000>; + energy-full-design-microwatt-hours = <7700000>; + operating-range-celsius = <0 45>; + }; + + gpio-keys { + key-memo { + label = "Memo"; + gpios = <&gpio TEGRA_GPIO(B, 6) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + }; + + gpio-leds { + led-power { + label = "power::white"; + gpios = <&gpio TEGRA_GPIO(R, 3) GPIO_ACTIVE_HIGH>; + + linux,default-trigger = "battery-charging"; + + color = ; + function = LED_FUNCTION_CHARGING; + }; + }; + + regulator-lcd3v { + gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "lg,tegra-audio-max98089-p895", + "nvidia,tegra-audio-max98089"; + nvidia,model = "LG Optimus Vu MAX98089"; + + nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(I, 2) GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/src/arm/nvidia/tegra30-lg-x3.dtsi b/src/arm/nvidia/tegra30-lg-x3.dtsi new file mode 100644 index 00000000000..909260a5d0f --- /dev/null +++ b/src/arm/nvidia/tegra30-lg-x3.dtsi @@ -0,0 +1,1812 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include + +#include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" + +/ { + chassis-type = "handset"; + + aliases { + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc1; /* WiFi */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + serial0 = &uartd; /* Console */ + serial1 = &uartc; /* Bluetooth */ + serial2 = &uartb; /* GPS */ + }; + + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen { }; + + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma@80000000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x80000000 0x30000000>; + size = <0x10000000>; /* 256MiB */ + linux,cma-default; + reusable; + }; + + ramoops@bed00000 { + compatible = "ramoops"; + reg = <0xbed00000 0x10000>; /* 64kB */ + console-size = <0x8000>; /* 32kB */ + record-size = <0x400>; /* 1kB */ + ecc-size = <16>; + }; + + trustzone@bfe00000 { + reg = <0xbfe00000 0x200000>; /* 2MB */ + no-map; + }; + }; + + vde@6001a000 { + assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>; + assigned-clock-rates = <408000000>; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* WLAN SDIO pinmux */ + sdmmc1-clk { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1-cmd { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + wlan-reset { + nvidia,pins = "pv3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + wlan-host-wake { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GNSS UART-B pinmux */ + gps-pwr-en { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gps-ldo-en { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gps-clk-ref { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Bluetooth UART-C pinmux */ + uartc-cts-rxd { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uartc-rts-txd { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + bt-reset { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + bt-dev-wake { + nvidia,pins = "kb_row11_ps3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + bt-host-wake { + nvidia,pins = "kb_row12_ps4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + bt-pcm-dap4 { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* EMMC pinmux */ + sdmmc4-clk { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-data { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-reset { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* I2C pinmux */ + gen1-i2c { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = ; + }; + gen2-i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = ; + }; + cam-i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = ; + }; + ddc-i2c { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + }; + pwr-i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = ; + }; + mhl-i2c { + nvidia,pins = "kb_col6_pq6", + "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GPIO keys pinmux */ + power-key { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + volume-down { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "spi3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Sensors pinmux */ + sen-vdd { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + proxi-vdd { + nvidia,pins = "spi2_miso_px1"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sen-vio { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + nct-irq { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + bat-irq { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + charger-irq { + nvidia,pins = "gmi_cs1_n_pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + mpu-irq { + nvidia,pins = "gmi_ad12_ph4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + compass-irq { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + light-irq { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* LED pinmux */ + backlight-en { + nvidia,pins = "lcd_dc0_pn6"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + flash-led-en { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + keypad-led { + nvidia,pins = "kb_row2_pr2", + "kb_row3_pr3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* NFC pinmux */ + nfc-irq { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + nfc-ven { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + nfc-firm { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* DC pinmux */ + lcd-pwr { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pwr1_pc1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd-wr-n { + nvidia,pins = "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd-id { + nvidia,pins = "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd-pclk { + nvidia,pins = "lcd_pclk_pb3", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_vsync_pj4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd-rgb-blue { + nvidia,pins = "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d18_pm2", + "lcd_d19_pm3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd-rgb-green { + nvidia,pins = "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d20_pm4", + "lcd_d21_pm5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd-rgb-red { + nvidia,pins = "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d22_pm6", + "lcd_d23_pm7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Bridge pinmux */ + bridge-reset { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "spi3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + rgb-ic-en { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + bridge-clk { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + rgb-bridge { + nvidia,pins = "lcd_sdin_pz2", + "lcd_sdout_pn5", + "lcd_cs0_n_pn4", + "lcd_sck_pz4"; + nvidia,function = "spi5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Panel pinmux */ + panel-reset { + nvidia,pins = "lcd_cs1_n_pw0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + panel-vio { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Touchscreen pinmux */ + touch-vdd { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + touch-vio { + nvidia,pins = "spi1_mosi_px4"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + touch-irq-n { + nvidia,pins = "kb_col3_pq3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + touch-rst-n { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "spi3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + touch-maker-id { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MHL pinmux */ + mhl-vio { + nvidia,pins = "pv2"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + mhl-rst-n { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + mhl-irq { + nvidia,pins = "crt_vsync_pv7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + mhl-sel { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi-hpd { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* AUDIO pinmux */ + hp-detect { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hp-hook { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ear-mic-en { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + audio-irq { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + audio-mclk { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap-i2s0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap-i2s1 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MUIC pinmux */ + muic-irq { + nvidia,pins = "gmi_cs0_n_pj0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + muic-dp2t { + nvidia,pins = "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + muic-usif { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ifx-usb-vbus-en { + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcb-rev { + nvidia,pins = "gmi_wait_pi7", + "gmi_rst_n_pi4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + jtag-rtck { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Camera pinmux */ + cam-mclk { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam-pmic-en { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + front-cam-rst { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + front-cam-vio { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + rear-cam-rst { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + rear-cam-eprom-pr { + nvidia,pins = "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + rear-cam-vcm-pwdn { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Haptic pinmux */ + haptic-en { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + haptic-osc { + nvidia,pins = "gmi_ad11_ph3"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Modem pinmux */ + cp2ap-ack1-host-active { + nvidia,pins = "pu5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cp2ap-ack2-host-wakeup { + nvidia,pins = "pv0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ap2cp-ack2-suspend-req { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ap2cp-ack1-slave-wakeup { + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cp-kkp { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cp-crash-irq { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ap2cp-uarta-tx-ipc { + nvidia,pins = "pu0"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ap2cp-uarta-rx-ipc { + nvidia,pins = "pu1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + fota-ap-cts-cp-rts { + nvidia,pins = "pu2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + fota-ap-rts-cp-cts { + nvidia,pins = "pu3"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + modem-enable { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "hsi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + modem-reset { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap-i2s2 { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1", + "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GPIO power/drive control */ + drive-i2c { + nvidia,pins = "drive_dbg", + "drive_at5", + "drive_gme", + "drive_ddc", + "drive_ao1"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive-uart3 { + nvidia,pins = "drive_uart3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive-gmi { + nvidia,pins = "drive_at3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + }; + + uartb: serial@70006040 { + compatible = "nvidia,tegra30-hsuart"; + reset-names = "serial"; + /delete-property/ reg-shift; + status = "okay"; + + /* GNSS GSD5T */ + }; + + uartc: serial@70006200 { + compatible = "nvidia,tegra30-hsuart"; + reset-names = "serial"; + /delete-property/ reg-shift; + status = "okay"; + + nvidia,adjust-baud-rates = <0 9600 100>, + <9600 115200 200>, + <1000000 4000000 136>; + + /* BCM4330B1 37.4 MHz Class 1.5 ExtLNA */ + bluetooth { + compatible = "brcm,bcm4330-bt"; + max-speed = <4000000>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "txco"; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wakeup"; + + device-wakeup-gpios = <&gpio TEGRA_GPIO(S, 3) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>; + + vbat-supply = <&vdd_3v3_vbat>; + vddio-supply = <&vdd_1v8_vio>; + }; + }; + + uartd: serial@70006300 { + /delete-property/ dmas; + /delete-property/ dma-names; + status = "okay"; + + /* Console */ + }; + + pwm@7000a000 { + status = "okay"; + }; + + gen1_i2c: i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + /* Aichi AMI306 digital compass */ + magnetometer@e { + compatible = "asahi-kasei,ak8974"; + reg = <0x0e>; + + interrupt-parent = <&gpio>; + interrupts = ; + + avdd-supply = <&vdd_3v0_sen>; + dvdd-supply = <&vdd_1v8_vio>; + + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + }; + + max98089: audio-codec@10 { + compatible = "maxim,max98089"; + reg = <0x10>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "mclk"; + + assigned-clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_EXTERN1>; + }; + + nfc@28 { + compatible = "nxp,pn544-i2c"; + reg = <0x28>; + + interrupt-parent = <&gpio>; + interrupts = ; + + enable-gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_HIGH>; + firmware-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; + }; + + imu@68 { + compatible = "invensense,mpu6050"; + reg = <0x68>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_3v0_sen>; + vddio-supply = <&vdd_1v8_sen>; + + mount-matrix = "1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + }; + }; + + gen2_i2c: i2c@7000c400 { + status = "okay"; + clock-frequency = <400000>; + + /* Synaptics RMI4 S3203B touchcreen */ + touchscreen@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_3v0_touch>; + vio-supply = <&vdd_1v8_touch>; + + syna,reset-delay-ms = <20>; + syna,startup-delay-ms = <200>; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f11@11 { + reg = <0x11>; + syna,sensor-type = <1>; + + syna,clip-x-low = <0>; + syna,clip-y-low = <0>; + }; + }; + }; + + cam_i2c: i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + + dw9714: coil@c { + compatible = "dongwoon,dw9714"; + reg = <0x0c>; + + enable-gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_HIGH>; + + vcc-supply = <&vcc_focuser>; + }; + + camera-pmic@7d { + compatible = "ti,lp8720"; + reg = <0x7d>; + + enable-gpios = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; + + vt_1v2_front: ldo1 { + regulator-name = "vt_1v2_dig"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vt_2v7_front: ldo2 { + regulator-name = "vt_2v7_vana"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + vdd_2v7_rear: ldo3 { + regulator-name = "8m_2v7_vana"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + }; + + vio_1v8_rear: ldo4 { + regulator-name = "vio_1v8_cam"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_focuser: ldo5 { + regulator-name = "8m_2v8_vcm"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vdd_1v2_rear: buck { + regulator-name = "8m_1v2_cam"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + }; + }; + + hdmi_ddc: i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: max77663@1c { + compatible = "maxim,max77663"; + reg = <0x1c>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + + #gpio-cells = <2>; + gpio-controller; + + system-power-controller; + + pinctrl-names = "default"; + pinctrl-0 = <&max77663_default>; + + max77663_default: pinmux { + gpio1 { + pins = "gpio1"; + function = "gpio"; + drive-open-drain = <1>; + }; + + gpio4 { + pins = "gpio4"; + function = "32k-out1"; + }; + }; + + fps { + fps0 { + maxim,fps-event-source = ; + }; + + fps1 { + maxim,fps-event-source = ; + }; + + fps2 { + maxim,fps-event-source = ; + }; + }; + + regulators { + in-sd0-supply = <&vdd_5v0_vbus>; + in-sd1-supply = <&vdd_5v0_vbus>; + in-sd2-supply = <&vdd_5v0_vbus>; + in-sd3-supply = <&vdd_5v0_vbus>; + + in-ldo0-1-supply = <&vdd_1v8_vio>; + in-ldo2-supply = <&vdd_3v3_vbat>; + in-ldo3-5-supply = <&vdd_3v3_vbat>; + in-ldo4-6-supply = <&vdd_3v3_vbat>; + in-ldo7-8-supply = <&vdd_1v8_vio>; + + vdd_cpu: sd0 { + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-coupled-with = <&vdd_core>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-cpu-regulator; + maxim,active-fps-source = ; + }; + + vdd_core: sd1 { + regulator-name = "vdd_core"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-coupled-with = <&vdd_cpu>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-core-regulator; + maxim,active-fps-source = ; + }; + + vdd_1v8_vio: sd2 { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = ; + }; + + sd3 { + regulator-name = "vddio_ddr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = ; + }; + + ldo0 { + regulator-name = "avdd_pll"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = ; + }; + + ldo1 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = ; + }; + + avdd_3v3_periph: ldo2 { + regulator-name = "avdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + maxim,active-fps-source = ; + }; + + vdd_usd: ldo3 { + regulator-name = "vdd_sdmmc3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + + maxim,active-fps-source = ; + }; + + ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = ; + }; + + vcore_emmc: ldo5 { + regulator-name = "vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = ; + }; + + avdd_1v8_hdmi_pll: ldo6 { + regulator-name = "avdd_osc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = ; + }; + + vdd_1v2_mhl: ldo7 { + regulator-name = "vdd_1v2_mhl"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1250000>; + + maxim,active-fps-source = ; + }; + + ldo8 { + regulator-name = "avdd_dsi_csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + maxim,active-fps-source = ; + }; + }; + }; + + fuel-gauge@36 { + compatible = "maxim,max17043"; + reg = <0x36>; + + interrupt-parent = <&gpio>; + interrupts = ; + + monitored-battery = <&battery>; + + maxim,alert-low-soc-level = <10>; + wakeup-source; + }; + + power-sensor@40 { + compatible = "ti,ina230"; + reg = <0x40>; + + vs-supply = <&vdd_3v0_sen>; + }; + + nct72: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vcc-supply = <&vdd_3v0_sen>; + #thermal-sensor-cells = <1>; + }; + }; + + i2c-mhl { + compatible = "i2c-gpio"; + + sda-gpios = <&gpio TEGRA_GPIO(Q, 7) (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio TEGRA_GPIO(Q, 6) (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + i2c-gpio,delay-us = <5>; + + #address-cells = <1>; + #size-cells = <0>; + }; + + spi@7000dc00 { + status = "okay"; + spi-max-frequency = <25000000>; + + /* DSI bridge */ + }; + + pmc@7000e400 { + status = "okay"; + nvidia,invert-interrupt; + nvidia,suspend-mode = <2>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <200>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <0>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x1c>; + nvidia,reg-addr = <0x41>; + nvidia,reg-data = <0x02>; + }; + }; + + hda@70030000 { + status = "okay"; + }; + + ahub@70080000 { + /* HIFI CODEC */ + i2s@70080300 { /* i2s0 */ + status = "okay"; + }; + + /* BASEBAND */ + i2s@70080500 { /* i2s2 */ + status = "okay"; + }; + + /* BT SCO */ + i2s@70080600 { /* i2s3 */ + status = "okay"; + }; + }; + + sdmmc1: mmc@78000000 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + + max-frequency = <50000000>; + keep-power-in-suspend; + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&brcm_wifi_pwrseq>; + vmmc-supply = <&vdd_3v3_vbat>; + vqmmc-supply = <&vdd_1v8_vio>; + + /* BCM4330B1 37.4 MHz Class 1.5 ExtLNA */ + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wake"; + }; + }; + + sdmmc4: mmc@78000600 { + status = "okay"; + bus-width = <8>; + + non-removable; + mmc-ddr-1_8v; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + /* Micro USB */ + usb@7d000000 { + compatible = "nvidia,tegra30-udc"; + status = "okay"; + dr_mode = "peripheral"; + }; + + usb-phy@7d000000 { + status = "okay"; + dr_mode = "peripheral"; + nvidia,hssync-start-delay = <0>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + vbus-supply = <&avdd_3v3_periph>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + gps_refclk: clock-gps { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + clock-accuracy = <100>; + #clock-cells = <0>; + }; + + gps_osc: clock-gps-osc-gate { + compatible = "gpio-gate-clock"; + enable-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>; + clocks = <&gps_refclk>; + #clock-cells = <0>; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu1: cpu@1 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu2: cpu@2 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu3: cpu@3 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(O, 4) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-keypad { + label = "keypad::white"; + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>; + + color = ; + function = LED_FUNCTION_KBD_BACKLIGHT; + }; + }; + + opp-table-actmon { + /delete-node/ opp-625000000; + /delete-node/ opp-667000000; + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; + }; + + opp-table-emc { + /delete-node/ opp-625000000-1200; + /delete-node/ opp-625000000-1250; + /delete-node/ opp-667000000-1200; + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; + }; + + brcm_wifi_pwrseq: pwrseq-wifi { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; + + vdd_5v0_vbus: regulator-vbus { + compatible = "regulator-fixed"; + regulator-name = "vdd_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_3v3_vbat: regulator-vbat { + compatible = "regulator-fixed"; + regulator-name = "vdd_vbat"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_5v0_vbus>; + }; + + vdd_3v0_sen: regulator-sen3v { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v0_sensor"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + + vdd_3v0_proxi: regulator-proxi { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v0_proxi"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + + vdd_1v8_sen: regulator-sen1v8 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_sensor"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + + vcc_3v0_lcd: regulator-lcd3v { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v0_lcd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + vin-supply = <&vdd_3v3_vbat>; + }; + + iovcc_1v8_lcd: regulator-lcd1v8 { + compatible = "regulator-fixed"; + regulator-name = "iovcc_1v8_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + + vio_1v8_mhl: regulator-mhl1v8 { + compatible = "regulator-fixed"; + regulator-name = "vio_1v8_mhl"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + + vdd_3v0_touch: regulator-touchpwr { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v0_touch"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + + vdd_1v8_touch: regulator-touchvio { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_touch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(X, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + + vcc_1v8_gps: regulator-gps { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8_gps"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(Y, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + + vio_1v8_front: regulator-frontvio { + compatible = "regulator-fixed"; + regulator-name = "vt_1v8_cam_vio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio TEGRA_GPIO(Y, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + + sound { + nvidia,audio-routing = + "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "Int Spk", "SPKL", + "Int Spk", "SPKR", + "Earpiece", "RECL", + "Earpiece", "RECR", + "INA1", "Mic Jack", + "MIC1", "MICBIAS", + "MICBIAS", "Internal Mic 1", + "MIC2", "Internal Mic 2"; + + nvidia,i2s-controller = <&tegra_i2s0>; + nvidia,audio-codec = <&max98089>; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(BB, 6) GPIO_ACTIVE_LOW>; + nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_HIGH>; + nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>; + nvidia,coupled-mic-hp-det; + + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; + }; + + thermal-zones { + /* + * NCT72 has two sensors: + * + * 0: internal that monitors ambient/skin temperature + * 1: external that is connected to the CPU's diode + * + * Ideally we should use userspace thermal governor, + * but it's a much more complex solution. The "skin" + * zone exists as a simpler solution which prevents + * this device from getting too hot from a user's + * tactile perspective. The CPU zone is intended to + * protect silicon from damage. + */ + + skin-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct72 0>; + + trips { + trip0: skin-alert { + /* throttle at 50C until temperature drops to 49.8C */ + temperature = <50000>; + hysteresis = <200>; + type = "passive"; + }; + + trip1: skin-crit { + /* shut down at 60C */ + temperature = <60000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct72 1>; + + trips { + trip2: cpu-alert { + /* throttle at 75C until temperature drops to 74.8C */ + temperature = <75000>; + hysteresis = <200>; + type = "passive"; + }; + + trip3: cpu-crit { + /* shut down at 90C */ + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map1 { + trip = <&trip2>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; diff --git a/src/arm/nxp/imx/imx1-apf9328.dts b/src/arm/nxp/imx/imx1-apf9328.dts index e66eef87a7a..058e9435524 100644 --- a/src/arm/nxp/imx/imx1-apf9328.dts +++ b/src/arm/nxp/imx/imx1-apf9328.dts @@ -54,7 +54,7 @@ #size-cells = <1>; }; - eth: eth@4,c00000 { + eth: ethernet@4,c00000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eth>; compatible = "davicom,dm9000"; diff --git a/src/arm/nxp/imx/imx1.dtsi b/src/arm/nxp/imx/imx1.dtsi index 1ac10965fdf..389ecb1ebf8 100644 --- a/src/arm/nxp/imx/imx1.dtsi +++ b/src/arm/nxp/imx/imx1.dtsi @@ -251,7 +251,7 @@ }; }; - weim: weim@220000 { + weim: memory-controller@220000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,imx1-weim"; diff --git a/src/arm/nxp/imx/imx27.dtsi b/src/arm/nxp/imx/imx27.dtsi index ec472695c71..ec3ccc8f409 100644 --- a/src/arm/nxp/imx/imx27.dtsi +++ b/src/arm/nxp/imx/imx27.dtsi @@ -568,7 +568,7 @@ status = "disabled"; }; - weim: weim@d8002000 { + weim: memory-controller@d8002000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,imx27-weim"; diff --git a/src/arm/nxp/imx/imx31.dtsi b/src/arm/nxp/imx/imx31.dtsi index e1ae7c175f7..00006c90d9a 100644 --- a/src/arm/nxp/imx/imx31.dtsi +++ b/src/arm/nxp/imx/imx31.dtsi @@ -352,7 +352,7 @@ status = "disabled"; }; - weim: weim@b8002000 { + weim: memory-controller@b8002000 { compatible = "fsl,imx31-weim", "fsl,imx27-weim"; reg = <0xb8002000 0x1000>; clocks = <&clks 56>; diff --git a/src/arm/nxp/imx/imx35.dtsi b/src/arm/nxp/imx/imx35.dtsi index 2d20e5541ac..442dc15677b 100644 --- a/src/arm/nxp/imx/imx35.dtsi +++ b/src/arm/nxp/imx/imx35.dtsi @@ -374,7 +374,7 @@ status = "disabled"; }; - weim: weim@b8002000 { + weim: memory-controller@b8002000 { #address-cells = <2>; #size-cells = <1>; clocks = <&clks 0>; diff --git a/src/arm/nxp/imx/imx51.dtsi b/src/arm/nxp/imx/imx51.dtsi index c96d6311dfa..4efce49022e 100644 --- a/src/arm/nxp/imx/imx51.dtsi +++ b/src/arm/nxp/imx/imx51.dtsi @@ -578,7 +578,7 @@ reg = <0x83fd8000 0x1000>; }; - weim: weim@83fda000 { + weim: memory-controller@83fda000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,imx51-weim"; diff --git a/src/arm/nxp/imx/imx53-qsb-hdmi.dtso b/src/arm/nxp/imx/imx53-qsb-hdmi.dtso new file mode 100644 index 00000000000..c84e9b05252 --- /dev/null +++ b/src/arm/nxp/imx/imx53-qsb-hdmi.dtso @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * DT overlay for MCIMXHDMICARD as used with the iMX53 QSB or QSRB boards + */ + +#include +#include + +/dts-v1/; +/plugin/; + +&{/} { + /delete-node/ panel; + + hdmi: connector-hdmi { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&sii9022_out>; + }; + }; + }; + + reg_1p2v: regulator-1p2v { + compatible = "regulator-fixed"; + regulator-name = "1P2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + vin-supply = <®_3p2v>; + }; +}; + +&display0 { + status = "okay"; +}; + +&display0 { + port@1 { + display0_out: endpoint { + remote-endpoint = <&sii9022_in>; + }; + }; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + sii9022: bridge-hdmi@39 { + compatible = "sil,sii9022"; + reg = <0x39>; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + interrupts-extended = <&gpio3 31 IRQ_TYPE_LEVEL_LOW>; + iovcc-supply = <®_3p2v>; + #sound-dai-cells = <0>; + sil,i2s-data-lanes = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in: endpoint { + remote-endpoint = <&display0_out>; + }; + }; + + port@1 { + reg = <1>; + + sii9022_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&tve { + status = "disabled"; +}; diff --git a/src/arm/nxp/imx/imx6dl-sielaff.dts b/src/arm/nxp/imx/imx6dl-sielaff.dts new file mode 100644 index 00000000000..7de8d5f2651 --- /dev/null +++ b/src/arm/nxp/imx/imx6dl-sielaff.dts @@ -0,0 +1,533 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2022 Kontron Electronics GmbH + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include +#include +#include + +/ { + model = "Sielaff i.MX6 Solo"; + compatible = "sielaff,imx6dl-board", "fsl,imx6dl"; + + chosen { + stdout-path = &uart2; + }; + + backlight: pwm-backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + pwms = <&pwm3 0 50000 0>; + brightness-levels = <0 0 64 88 112 136 184 232 255>; + default-brightness-level = <4>; + enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + power-supply = <®_backlight>; + }; + + cec { + compatible = "cec-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + cec-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + hdmi-phandle = <&hdmi>; + }; + + enet_ref: clock-enet-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "enet-ref"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + key-0 { + gpios = <&gpio2 16 0>; + debounce-interval = <10>; + linux,code = <1>; + }; + + key-1 { + gpios = <&gpio3 27 0>; + debounce-interval = <10>; + linux,code = <2>; + }; + + key-2 { + gpios = <&gpio5 4 0>; + debounce-interval = <10>; + linux,code = <3>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-debug { + label = "debug-led"; + gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + device_type = "memory"; + }; + + osc_eth_phy: clock-osc-eth-phy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "osc-eth-phy"; + }; + + panel { + compatible = "lg,lb070wv8"; + backlight = <&backlight>; + power-supply = <®_3v3>; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out>; + }; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_backlight: regulator-backlight { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_backlight>; + enable-active-high; + gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; + regulator-name = "backlight"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + enable-active-high; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&fec { + /* + * Set PTP clock to external instead of internal reference, as the + * REF_CLK from the PHY is fed back into the i.MX6 and the GPR + * register needs to be set accordingly (see mach-imx6q.c). + */ + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&enet_ref>, + <&clks IMX6QDL_CLK_ENET_REF>; + clock-names = "ipg", "ahb", "ptp", "enet_out"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-connection-type = "rmii"; + phy-handle = <ðphy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@1 { + reg = <1>; + clocks = <&osc_eth_phy>; + clock-names = "rmii-ref"; + micrel,led-mode = <1>; + reset-assert-us = <500>; + reset-deassert-us = <100>; + reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "key-out", "key-in", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "lan9500a-rst", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c4>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <100000>; + status = "okay"; + + touchscreen@55 { + compatible = "sitronix,st1633"; + reg = <0x55>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio5>; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + status = "disabled"; + }; + + touchscreen@5d { + compatible = "goodix,gt928"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio5>; + irq-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + clock-frequency = <100000>; + status = "okay"; +}; + +&ldb { + status = "okay"; + + lvds: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds_out: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + usb1@1 { + compatible = "usb4b4,6570"; + reg = <1>; + clocks = <&clks IMX6QDL_CLK_CKO>; + + assigned-clocks = <&clks IMX6QDL_CLK_CKO>, + <&clks IMX6QDL_CLK_CKO2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>, + <&clks IMX6QDL_CLK_OSC>; + assigned-clock-rates = <12000000 0>; + }; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + dr_mode = "host"; + over-current-active-low; + vbus-supply = <®_usb_otg_vbus>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3v3>; + voltage-ranges = <3300 3300>; + no-1-8-v; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x1b0b0 /* PMIC_IRQ */ + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 + >; + }; + + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x100b1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b080 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b080 + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b080 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_backlight: regbacklightgrp { + fsl,pins = < + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b1 + >; + }; + + pinctrl_reg_usbotg_vbus: regusbotgvbusgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b1 + >; + }; + + pinctrl_touch: touchgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b1 + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x1b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b1 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x100b1 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/src/arm/nxp/imx/imx6dl-yapp4-common.dtsi b/src/arm/nxp/imx/imx6dl-yapp4-common.dtsi index 3be38a3c4bb..c32ea040fec 100644 --- a/src/arm/nxp/imx/imx6dl-yapp4-common.dtsi +++ b/src/arm/nxp/imx/imx6dl-yapp4-common.dtsi @@ -117,17 +117,9 @@ #address-cells = <1>; #size-cells = <0>; - phy_port2: phy@1 { - reg = <1>; - }; - - phy_port3: phy@2 { - reg = <2>; - }; - switch@10 { compatible = "qca,qca8334"; - reg = <10>; + reg = <0x10>; reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; switch_ports: ports { @@ -149,15 +141,30 @@ eth2: port@2 { reg = <2>; label = "eth2"; + phy-mode = "internal"; phy-handle = <&phy_port2>; }; eth1: port@3 { reg = <3>; label = "eth1"; + phy-mode = "internal"; phy-handle = <&phy_port3>; }; }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port2: ethernet-phy@1 { + reg = <1>; + }; + + phy_port3: ethernet-phy@2 { + reg = <2>; + }; + }; }; }; }; diff --git a/src/arm/nxp/imx/imx6q-apalis-eval-v1.2.dts b/src/arm/nxp/imx/imx6q-apalis-eval-v1.2.dts new file mode 100644 index 00000000000..15d4a98ee97 --- /dev/null +++ b/src/arm/nxp/imx/imx6q-apalis-eval-v1.2.dts @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 Toradex + */ + +/dts-v1/; + +#include "imx6q-apalis-eval.dtsi" + +/ { + model = "Toradex Apalis iMX6Q/D Module on Apalis Evaluation Board v1.2"; + compatible = "toradex,apalis_imx6q-eval-v1.2", "toradex,apalis_imx6q", + "fsl,imx6q"; + + reg_3v3_mmc: regulator-3v3-mmc { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_3v3_mmc>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3.3V_MMC"; + startup-delay-us = <10000>; + }; + + reg_3v3_sd: regulator-3v3-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_3v3_sd>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3.3V_SD"; + startup-delay-us = <10000>; + }; + + reg_can1: regulator-can1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_can1_power>; + regulator-name = "5V_SW_CAN1"; + startup-delay-us = <10000>; + }; + + reg_can2: regulator-can2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_can2_power>; + regulator-name = "5V_SW_CAN2"; + startup-delay-us = <10000>; + }; + + sound-carrier { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,name = "apalis-nau8822"; + simple-audio-card,routing = + "Headphones", "LHP", + "Headphones", "RHP", + "Speaker", "LSPK", + "Speaker", "RSPK", + "Line Out", "AUXOUT1", + "Line Out", "AUXOUT2", + "LAUX", "Line In", + "RAUX", "Line In", + "LMICP", "Mic In", + "RMICP", "Mic In"; + simple-audio-card,widgets = + "Headphones", "Headphones", + "Line Out", "Line Out", + "Speaker", "Speaker", + "Microphone", "Mic In", + "Line", "Line In"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&nau8822_1a>; + system-clock-frequency = <12288000>; + }; + + simple-audio-card,cpu { + sound-dai = <&ssi2>; + }; + }; +}; + +&can1 { + xceiver-supply = <®_can1>; + status = "okay"; +}; + +&can2 { + xceiver-supply = <®_can2>; + status = "okay"; +}; + +/* I2C1_SDA/SCL on MXM3 209/211 */ +&i2c1 { + /* Audio Codec */ + nau8822_1a: audio-codec@1a { + compatible = "nuvoton,nau8822"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nau8822>; + #sound-dai-cells = <0>; + }; + + /* Current measurement into module VCC */ + hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + + /* Temperature Sensor */ + temperature-sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + /* EEPROM */ + eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + size = <256>; + }; +}; + +&pcie { + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +/* MMC1 */ +&usdhc1 { + bus-width = <4>; + pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_mmc_cd>; + vmmc-supply = <®_3v3_mmc>; + status = "okay"; +}; + +/* SD1 */ +&usdhc2 { + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>; + vmmc-supply = <®_3v3_sd>; + status = "okay"; +}; + +&iomuxc { + pinctrl_enable_3v3_mmc: enable3v3mmcgrp { + fsl,pins = < + /* MMC1_PWR_CTRL */ + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + >; + }; + + pinctrl_enable_3v3_sd: enable3v3sdgrp { + fsl,pins = < + /* SD1_PWR_CTRL */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + >; + }; + + pinctrl_enable_can1_power: enablecan1powergrp { + fsl,pins = < + /* CAN1_PWR_EN */ + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + >; + }; + + pinctrl_enable_can2_power: enablecan2powergrp { + fsl,pins = < + /* CAN2_PWR_EN */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + >; + }; + + pinctrl_nau8822: nau8822grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x130b0 + MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + >; + }; +}; diff --git a/src/arm/nxp/imx/imx6q-apalis-eval.dts b/src/arm/nxp/imx/imx6q-apalis-eval.dts index 3fc079dfd61..e1077e2da5f 100644 --- a/src/arm/nxp/imx/imx6q-apalis-eval.dts +++ b/src/arm/nxp/imx/imx6q-apalis-eval.dts @@ -7,29 +7,13 @@ /dts-v1/; -#include -#include -#include -#include "imx6q.dtsi" -#include "imx6qdl-apalis.dtsi" +#include "imx6q-apalis-eval.dtsi" / { model = "Toradex Apalis iMX6Q/D Module on Apalis Evaluation Board"; compatible = "toradex,apalis_imx6q-eval", "toradex,apalis_imx6q", "fsl,imx6q"; - aliases { - i2c0 = &i2c1; - i2c1 = &i2c3; - i2c2 = &i2c2; - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - reg_pcie_switch: regulator-pcie-switch { compatible = "regulator-fixed"; enable-active-high; @@ -40,14 +24,6 @@ startup-delay-us = <100000>; status = "okay"; }; - - reg_3v3_sw: regulator-3v3-sw { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "3.3V_SW"; - }; }; &can1 { @@ -62,102 +38,22 @@ /* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ &i2c1 { - status = "okay"; - + /* PCIe Switch */ pcie-switch@58 { compatible = "plx,pex8605"; reg = <0x58>; }; - - /* M41T0M6 real time clock on carrier board */ - rtc_i2c: rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; -}; - -/* - * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier - * board) - */ -&i2c3 { - status = "okay"; }; &pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reset_moci>; - /* active-high meaning opposite of regular PERST# active-low polarity */ - reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; - reset-gpio-active-high; vpcie-supply = <®_pcie_switch>; status = "okay"; }; -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&pwm4 { - status = "okay"; -}; - -®_usb_host_vbus { - status = "okay"; -}; - -®_usb_otg_vbus { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - &sound_spdif { status = "okay"; }; -&spdif { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usbh1 { - disable-over-current; - vbus-supply = <®_usb_host_vbus>; - status = "okay"; -}; - -&usbotg { - disable-over-current; - vbus-supply = <®_usb_otg_vbus>; - status = "okay"; -}; - /* MMC1 */ &usdhc1 { status = "okay"; diff --git a/src/arm/nxp/imx/imx6q-apalis-eval.dtsi b/src/arm/nxp/imx/imx6q-apalis-eval.dtsi new file mode 100644 index 00000000000..b6c45ad3f43 --- /dev/null +++ b/src/arm/nxp/imx/imx6q-apalis-eval.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2014-2024 Toradex + */ + +#include +#include +#include +#include "imx6q.dtsi" +#include "imx6qdl-apalis.dtsi" + +/ { + aliases { + i2c0 = &i2c1; + i2c1 = &i2c3; + i2c2 = &i2c2; + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_3v3_sw: regulator-3v3-sw { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3.3V_SW"; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +/* + * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier + * board) + */ +&i2c3 { + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_moci>; + /* active-high meaning opposite of regular PERST# active-low polarity */ + reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; + reset-gpio-active-high; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +®_usb_host_vbus { + status = "okay"; +}; + +®_usb_otg_vbus { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&spdif { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbh1 { + disable-over-current; + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +&usbotg { + disable-over-current; + vbus-supply = <®_usb_otg_vbus>; + status = "okay"; +}; diff --git a/src/arm/nxp/imx/imx6qdl-hummingboard.dtsi b/src/arm/nxp/imx/imx6qdl-hummingboard.dtsi index bfade714908..a955c77cd49 100644 --- a/src/arm/nxp/imx/imx6qdl-hummingboard.dtsi +++ b/src/arm/nxp/imx/imx6qdl-hummingboard.dtsi @@ -41,6 +41,11 @@ #include / { + aliases { + rtc0 = &carrier_rtc; + rtc1 = &snvs_rtc; + }; + /* Will be filled by the bootloader */ memory@10000000 { device_type = "memory"; @@ -187,7 +192,7 @@ status = "okay"; /* Pro baseboard model */ - rtc@68 { + carrier_rtc: rtc@68 { compatible = "nxp,pcf8523"; reg = <0x68>; }; diff --git a/src/arm/nxp/imx/imx6qdl-hummingboard2.dtsi b/src/arm/nxp/imx/imx6qdl-hummingboard2.dtsi index 0883ef99cde..e6017f9bf64 100644 --- a/src/arm/nxp/imx/imx6qdl-hummingboard2.dtsi +++ b/src/arm/nxp/imx/imx6qdl-hummingboard2.dtsi @@ -41,6 +41,11 @@ #include / { + aliases { + rtc0 = &pcf8523; + rtc1 = &snvs_rtc; + }; + /* Will be filled by the bootloader */ memory@10000000 { device_type = "memory"; diff --git a/src/arm/nxp/imx/imx6qdl-skov-cpu.dtsi b/src/arm/nxp/imx/imx6qdl-skov-cpu.dtsi index 2731faede1c..d59d5d0e1d1 100644 --- a/src/arm/nxp/imx/imx6qdl-skov-cpu.dtsi +++ b/src/arm/nxp/imx/imx6qdl-skov-cpu.dtsi @@ -13,10 +13,14 @@ aliases { can0 = &can1; can1 = &can2; + ethernet0 = &fec; + ethernet1 = &lan1; + ethernet2 = &lan2; mdio-gpio0 = &mdio; nand = &gpmi; rtc0 = &i2c_rtc; rtc1 = &snvs; + switch0 = &switch; usb0 = &usbh1; usb1 = &usbotg; }; @@ -60,7 +64,7 @@ gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>, <&gpio1 22 GPIO_ACTIVE_HIGH>; - switch@0 { + switch: switch@0 { compatible = "microchip,ksz8873"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_switch>; @@ -73,13 +77,13 @@ #address-cells = <1>; #size-cells = <0>; - ports@0 { + lan1: ports@0 { reg = <0>; phy-mode = "internal"; label = "lan1"; }; - ports@1 { + lan2: ports@1 { reg = <1>; phy-mode = "internal"; label = "lan2"; diff --git a/src/arm/nxp/imx/imx6qdl.dtsi b/src/arm/nxp/imx/imx6qdl.dtsi index 81142c523fa..8431b8a994f 100644 --- a/src/arm/nxp/imx/imx6qdl.dtsi +++ b/src/arm/nxp/imx/imx6qdl.dtsi @@ -1158,7 +1158,7 @@ status = "disabled"; }; - weim: weim@21b8000 { + weim: memory-controller@21b8000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,imx6q-weim"; diff --git a/src/arm/nxp/imx/imx6sl-tolino-shine2hd.dts b/src/arm/nxp/imx/imx6sl-tolino-shine2hd.dts index 815119c12bd..5636fb3661e 100644 --- a/src/arm/nxp/imx/imx6sl-tolino-shine2hd.dts +++ b/src/arm/nxp/imx/imx6sl-tolino-shine2hd.dts @@ -141,8 +141,10 @@ interrupts = <6 IRQ_TYPE_EDGE_FALLING>; vdd-supply = <&ldo1_reg>; reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - x-size = <1072>; - y-size = <1448>; + touchscreen-size-x = <1072>; + touchscreen-size-y = <1448>; + touchscreen-swapped-x-y; + touchscreen-inverted-x; }; /* TODO: TPS65185 PMIC for E Ink at 0x68 */ diff --git a/src/arm/nxp/imx/imx6sl.dtsi b/src/arm/nxp/imx/imx6sl.dtsi index 28111efb19a..6aa61235e39 100644 --- a/src/arm/nxp/imx/imx6sl.dtsi +++ b/src/arm/nxp/imx/imx6sl.dtsi @@ -949,7 +949,7 @@ clocks = <&clks IMX6SL_CLK_DUMMY>; }; - weim: weim@21b8000 { + weim: memory-controller@21b8000 { #address-cells = <2>; #size-cells = <1>; reg = <0x021b8000 0x4000>; diff --git a/src/arm/nxp/imx/imx6sx.dtsi b/src/arm/nxp/imx/imx6sx.dtsi index df3a375f0a3..0de359d62a4 100644 --- a/src/arm/nxp/imx/imx6sx.dtsi +++ b/src/arm/nxp/imx/imx6sx.dtsi @@ -1107,7 +1107,7 @@ status = "disabled"; }; - weim: weim@21b8000 { + weim: memory-controller@21b8000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim"; diff --git a/src/arm/nxp/imx/imx6ul-14x14-evk.dtsi b/src/arm/nxp/imx/imx6ul-14x14-evk.dtsi index 2ac40d69425..f10f0525490 100644 --- a/src/arm/nxp/imx/imx6ul-14x14-evk.dtsi +++ b/src/arm/nxp/imx/imx6ul-14x14-evk.dtsi @@ -321,7 +321,7 @@ &tsc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tsc>; - xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; measure-delay-time = <0xffff>; pre-charge-time = <0xfff>; status = "okay"; diff --git a/src/arm/nxp/imx/imx6ul-geam.dts b/src/arm/nxp/imx/imx6ul-geam.dts index 875ae699c5c..2ca18f3dad0 100644 --- a/src/arm/nxp/imx/imx6ul-geam.dts +++ b/src/arm/nxp/imx/imx6ul-geam.dts @@ -203,7 +203,7 @@ &tsc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tsc>; - xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; }; &sai2 { diff --git a/src/arm/nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi b/src/arm/nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi index 18cac19aa9b..af337f18a26 100644 --- a/src/arm/nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi +++ b/src/arm/nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi @@ -156,7 +156,7 @@ &tsc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tsc>; - xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; measure-delay-time = <0xffff>; pre-charge-time = <0xffff>; status = "okay"; diff --git a/src/arm/nxp/imx/imx6ul.dtsi b/src/arm/nxp/imx/imx6ul.dtsi index a27a7554c2e..235aa676618 100644 --- a/src/arm/nxp/imx/imx6ul.dtsi +++ b/src/arm/nxp/imx/imx6ul.dtsi @@ -370,7 +370,7 @@ }; }; - tsc: tsc@2040000 { + tsc: touchscreen@2040000 { compatible = "fsl,imx6ul-tsc"; reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; interrupts = , @@ -538,6 +538,8 @@ fsl,num-rx-queues = <1>; fsl,stop-mode = <&gpr 0x10 4>; fsl,magic-packet; + nvmem-cells = <&fec2_mac_addr>; + nvmem-cell-names = "mac-address"; status = "disabled"; }; @@ -638,6 +640,7 @@ nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; nvmem-cell-names = "calib", "temp_grade"; clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; + #thermal-sensor-cells = <0>; }; }; @@ -855,7 +858,6 @@ clocks = <&clks IMX6UL_CLK_USBOH3>; fsl,usbphy = <&usbphy1>; fsl,usbmisc = <&usbmisc 0>; - fsl,anatop = <&anatop>; ahb-burst-config = <0x0>; tx-burst-size-dword = <0x10>; rx-burst-size-dword = <0x10>; @@ -897,6 +899,8 @@ fsl,num-rx-queues = <1>; fsl,stop-mode = <&gpr 0x10 3>; fsl,magic-packet; + nvmem-cells = <&fec1_mac_addr>; + nvmem-cell-names = "mac-address"; status = "disabled"; }; @@ -975,7 +979,7 @@ clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>; }; - weim: weim@21b8000 { + weim: memory-controller@21b8000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim"; @@ -1004,6 +1008,14 @@ cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; + + fec1_mac_addr: mac-addr@88 { + reg = <0x88 6>; + }; + + fec2_mac_addr: mac-addr@8e { + reg = <0x8e 6>; + }; }; csi: csi@21c4000 { diff --git a/src/arm/nxp/imx/imx6ull-dhcom-som-cfg-sdcard.dtsi b/src/arm/nxp/imx/imx6ull-dhcom-som-cfg-sdcard.dtsi index 040421f9c97..5e39f8dc135 100644 --- a/src/arm/nxp/imx/imx6ull-dhcom-som-cfg-sdcard.dtsi +++ b/src/arm/nxp/imx/imx6ull-dhcom-som-cfg-sdcard.dtsi @@ -14,10 +14,12 @@ */ /* - * To use usdhc1 as SD card, the WiFi node must be deleted. + * To use usdhc1 as SD card, the WiFi node must be deleted. The associated + * pwrseq node is also deleted in order to ensure that GPIO H is released. * BT is also not available, so remove BT from the UART node. */ /delete-node/ &brcmf; +/delete-node/ &usdhc1_pwrseq; /delete-node/ &bluetooth; / { diff --git a/src/arm/nxp/imx/imx6ull-dhcom-som.dtsi b/src/arm/nxp/imx/imx6ull-dhcom-som.dtsi index 830b5a5064f..a74f5273f9b 100644 --- a/src/arm/nxp/imx/imx6ull-dhcom-som.dtsi +++ b/src/arm/nxp/imx/imx6ull-dhcom-som.dtsi @@ -52,7 +52,7 @@ }; /* SoM with WiFi/BT: WiFi pin WL_REG_ON is connected to a DHCOM GPIO */ - /omit-if-no-ref/ usdhc1_pwrseq: usdhc1-pwrseq { + usdhc1_pwrseq: usdhc1-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; /* GPIO H */ }; @@ -273,7 +273,7 @@ pinctrl-names = "default"; pre-charge-time = <0xfff>; touchscreen-average-samples = <32>; - xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; }; /* DHCOM UART1 */ diff --git a/src/arm/nxp/imx/imx6ull-dhcor-som.dtsi b/src/arm/nxp/imx/imx6ull-dhcor-som.dtsi index 45315adfaa8..75486e1b0c1 100644 --- a/src/arm/nxp/imx/imx6ull-dhcor-som.dtsi +++ b/src/arm/nxp/imx/imx6ull-dhcor-som.dtsi @@ -28,10 +28,14 @@ /* * Due to the design as a solderable SOM, there are no capacitors * below the SoC, therefore higher voltages are required. + * Due to CPU lifetime consideration of the SoC manufacturer and + * the preferred area of operation in the industrial related + * environment, set the maximum frequency for each DHCOM i.MX6ULL + * to 792MHz, as with the industrial type. */ + clock-frequency = <792000000>; operating-points = < /* kHz uV */ - 900000 1275000 792000 1250000 /* Voltage increased */ 528000 1175000 396000 1025000 @@ -39,7 +43,6 @@ >; fsl,soc-operating-points = < /* KHz uV */ - 900000 1250000 792000 1250000 /* Voltage increased */ 528000 1175000 396000 1175000 diff --git a/src/arm/nxp/imx/imx6ull-tarragon-common.dtsi b/src/arm/nxp/imx/imx6ull-tarragon-common.dtsi index 3fdece5bd31..5248a058230 100644 --- a/src/arm/nxp/imx/imx6ull-tarragon-common.dtsi +++ b/src/arm/nxp/imx/imx6ull-tarragon-common.dtsi @@ -805,6 +805,7 @@ &pinctrl_usb_pwr>; dr_mode = "host"; power-active-high; + over-current-active-low; disable-over-current; status = "okay"; }; diff --git a/src/arm/nxp/imx/imx6ull.dtsi b/src/arm/nxp/imx/imx6ull.dtsi index 2bccd45e9fc..8a1776067ec 100644 --- a/src/arm/nxp/imx/imx6ull.dtsi +++ b/src/arm/nxp/imx/imx6ull.dtsi @@ -75,7 +75,7 @@ clocks = <&clks IMX6UL_CLK_DUMMY>; }; - iomuxc_snvs: iomuxc-snvs@2290000 { + iomuxc_snvs: pinctrl@2290000 { compatible = "fsl,imx6ull-iomuxc-snvs"; reg = <0x02290000 0x4000>; }; diff --git a/src/arm/nxp/imx/imx7-mba7.dtsi b/src/arm/nxp/imx/imx7-mba7.dtsi index 3df6dff7734..52869e68f83 100644 --- a/src/arm/nxp/imx/imx7-mba7.dtsi +++ b/src/arm/nxp/imx/imx7-mba7.dtsi @@ -18,6 +18,8 @@ mmc0 = &usdhc3; mmc1 = &usdhc1; /delete-property/ mmc2; + rtc0 = &ds1339; + rtc1 = &snvs_rtc; }; beeper { @@ -32,11 +34,18 @@ gpio_buttons: gpio-keys { compatible = "gpio-keys"; + /* + * NOTE: These buttons are attached to a GPIO-expander. + * Enabling wakeup-source, enables wakeup on all inputs. + * If PE_GPIO[3..6] are used as inputs, they cause a + * wakeup as well. + */ button-0 { /* #SWITCH_A */ label = "S11"; linux,code = ; gpios = <&pca9555 13 GPIO_ACTIVE_LOW>; + wakeup-source; }; button-1 { @@ -44,6 +53,7 @@ label = "S12"; linux,code = ; gpios = <&pca9555 14 GPIO_ACTIVE_LOW>; + wakeup-source; }; button-2 { @@ -51,6 +61,7 @@ label = "S13"; linux,code = ; gpios = <&pca9555 15 GPIO_ACTIVE_LOW>; + wakeup-source; }; }; @@ -171,6 +182,14 @@ regulator-always-on; }; + reg_vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + sound { compatible = "fsl,imx-audio-tlv320aic32x4"; model = "imx-audio-tlv320aic32x4"; @@ -198,9 +217,9 @@ &ecspi1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; + pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_ss0>; cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>, - <&gpio4 2 GPIO_ACTIVE_LOW>; + <&gpio4 2 GPIO_ACTIVE_LOW>, <&gpio4 19 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -214,8 +233,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; phy-supply = <®_fec1_pwdn>; phy-handle = <ðphy1_0>; fsl,magic-packet; @@ -228,10 +245,15 @@ ethphy1_0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1_phy>; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; ti,clk-output-sel = ; + reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <500>; }; }; }; @@ -290,13 +312,17 @@ lm75: temperature-sensor@49 { compatible = "national,lm75"; reg = <0x49>; + vs-supply = <®_vcc_3v3>; }; }; &i2c2 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_recovery>; + scl-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; tlv320aic32x4: audio-codec@18 { @@ -319,13 +345,17 @@ interrupts = <12 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; + vcc-supply = <®_vcc_3v3>; }; }; &i2c3 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_recovery>; + scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -334,213 +364,213 @@ pinctrl-0 = <&pinctrl_hog_mba7_1>; pinctrl_ecspi1: ecspi1grp { + fsl,pins = + , + , + , + , + , + ; + }; + + pinctrl_ecspi1_ss0: ecspi1ss0grp { fsl,pins = < - MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x7c - MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x74 - MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x74 - MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x74 - MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x74 - MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x74 + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x74 >; }; pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c - MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74 - MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74 - MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x74 - >; + fsl,pins = + , + , + , + ; }; pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x02 - MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x00 - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71 - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71 - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71 - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x79 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79 - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x79 - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x79 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79 + fsl,pins = + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_enet1_phy: enet1phygrp { + fsl,pins = /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */ - MX7D_PAD_ENET1_COL__GPIO7_IO15 0x40000070 + , /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */ - MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x40000078 - >; + ; }; pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x5a - MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x52 - >; + fsl,pins = + , + ; }; pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x5a - MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x52 - >; + fsl,pins = + , + ; }; pinctrl_hog_mba7_1: hogmba71grp { - fsl,pins = < + fsl,pins = /* Limitation: WDOG2_B / WDOG2_RESET not usable */ - MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x4000007c - MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x40000074 + , + , /* #BOOT_EN */ - MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x40000010 - >; + ; }; pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000078 - MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000078 - >; + fsl,pins = + , + ; + }; + + pinctrl_i2c2_recovery: i2c2recoverygrp { + fsl,pins = + , + ; }; pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX7D_PAD_I2C3_SCL__I2C3_SCL 0x40000078 - MX7D_PAD_I2C3_SDA__I2C3_SDA 0x40000078 - >; + fsl,pins = + , + ; + }; + + pinctrl_i2c3_recovery: i2c3recoverygrp { + fsl,pins = + , + ; }; pinctrl_pca9555: pca95550grp { - fsl,pins = < - MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x78 - >; + fsl,pins = + ; }; pinctrl_sai1: sai1grp { - fsl,pins = < - MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x11 - MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x1c - MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1c - MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x1c + fsl,pins = + , + , + , + , - MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1c - MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x14 - MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x14 - >; + , + , + ; }; pinctrl_uart3: uart3grp { - fsl,pins = < - MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x7e - MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x76 - MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x76 - MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x7e - >; + fsl,pins = + , + , + , + ; }; pinctrl_uart4: uart4grp { - fsl,pins = < - MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e - MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76 - MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x76 - MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x7e - >; + fsl,pins = + , + , + , + ; }; pinctrl_uart5: uart5grp { - fsl,pins = < - MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x7e - MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x76 - >; + fsl,pins = + , + ; }; pinctrl_uart6: uart6grp { - fsl,pins = < - MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x7d - MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x75 - MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x75 - MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x7d - >; + fsl,pins = + , + , + , + ; }; pinctrl_uart7: uart7grp { - fsl,pins = < - MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x7e - MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x76 - MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x76 + fsl,pins = + , + , + , /* Limitation: RTS is not connected */ - MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x7e - >; + ; }; - pinctrl_usdhc1_gpio: usdhc1grp_gpio { - fsl,pins = < + pinctrl_usdhc1_gpio: usdhc1_gpiogrp { + fsl,pins = /* WP */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x7c + , /* CD */ - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x7c + , /* VSELECT */ - MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 - >; + ; }; pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5e - MX7D_PAD_SD1_CLK__SD1_CLK 0x57 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5e - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5e - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5e - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5e - >; + fsl,pins = + , + , + , + , + , + ; }; - pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5a - MX7D_PAD_SD1_CLK__SD1_CLK 0x57 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a - >; + pinctrl_usdhc1_100mhz: usdhc1_100mhzgrp { + fsl,pins = + , + , + , + , + , + ; }; - pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5b - MX7D_PAD_SD1_CLK__SD1_CLK 0x57 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b - >; + pinctrl_usdhc1_200mhz: usdhc1_200mhzgrp { + fsl,pins = + , + , + , + , + , + ; }; }; &iomuxc_lpsr { pinctrl_pwm1: pwm1grp { - fsl,pins = < + fsl,pins = /* LCD_CONTRAST */ - MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x50 - >; + ; }; pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x5c - MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59 - >; + fsl,pins = + , + ; }; pinctrl_wdog1: wdog1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30 - >; + fsl,pins = + ; }; }; @@ -560,6 +590,10 @@ status = "okay"; }; +&snvs_pwrkey { + status = "okay"; +}; + &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; @@ -605,6 +639,7 @@ }; &usbh { + disable-over-current; status = "okay"; }; @@ -630,6 +665,8 @@ vmmc-supply = <®_sd1_vmmc>; bus-width = <4>; no-1-8-v; + no-sdio; + no-mmc; status = "okay"; }; diff --git a/src/arm/nxp/imx/imx7-tqma7.dtsi b/src/arm/nxp/imx/imx7-tqma7.dtsi index 3fc3130f9de..028961eb710 100644 --- a/src/arm/nxp/imx/imx7-tqma7.dtsi +++ b/src/arm/nxp/imx/imx7-tqma7.dtsi @@ -30,8 +30,11 @@ }; &i2c1 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_recovery>; + scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <100000>; status = "okay"; @@ -109,7 +112,7 @@ }; vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; + regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; @@ -135,7 +138,7 @@ }; /* NXP SE97BTP with temperature sensor + eeprom, TQMa7x 02xx */ - se97b: temperature-sensor-eeprom@1e { + se97b: temperature-sensor@1e { compatible = "nxp,se97b", "jedec,jc-42.4-temp"; reg = <0x1e>; }; @@ -143,15 +146,18 @@ /* ST M24C64 */ m24c64: eeprom@50 { compatible = "atmel,24c64"; + read-only; reg = <0x50>; pagesize = <32>; + vcc-supply = <&vgen4_reg>; status = "okay"; }; at24c02: eeprom@56 { - compatible = "atmel,24c02"; + compatible = "nxp,se97b", "atmel,24c02"; reg = <0x56>; pagesize = <16>; + vcc-supply = <&vgen4_reg>; status = "okay"; }; @@ -163,91 +169,89 @@ &iomuxc { pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_I2C1_SDA__I2C1_SDA 0x40000078 - MX7D_PAD_I2C1_SCL__I2C1_SCL 0x40000078 - >; + fsl,pins = + , + ; + }; + + pinctrl_i2c1_recovery: i2c1recoverygrp { + fsl,pins = + , + ; }; pinctrl_pmic1: pmic1grp { - fsl,pins = < - MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x4000005C - >; + fsl,pins = + ; }; pinctrl_qspi: qspigrp { - fsl,pins = < - MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x5A - MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x5A - MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x5A - MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x5A - MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x11 - MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x54 - MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x54 - >; + fsl,pins = + , + , + , + , + , + , + ; }; pinctrl_qspi_reset: qspi_resetgrp { - fsl,pins = < + fsl,pins = /* #QSPI_RESET */ - MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x52 - >; + ; }; pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x56 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 - >; + fsl,pins = + , + , + , + , + , + , + , + , + , + , + ; }; - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5a - MX7D_PAD_SD3_CLK__SD3_CLK 0x51 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a - >; + pinctrl_usdhc3_100mhz: usdhc3_100mhzgrp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + ; }; - pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5b - MX7D_PAD_SD3_CLK__SD3_CLK 0x51 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b - >; + pinctrl_usdhc3_200mhz: usdhc3_200mhzgrp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + ; }; }; &iomuxc_lpsr { pinctrl_wdog1: wdog1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30 - >; + fsl,pins = + ; }; }; @@ -265,10 +269,6 @@ }; }; -&sdma { - status = "okay"; -}; - &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; @@ -278,6 +278,8 @@ assigned-clock-rates = <400000000>; bus-width = <8>; non-removable; + no-sd; + no-sdio; vmmc-supply = <&vgen4_reg>; vqmmc-supply = <&sw2_reg>; status = "okay"; diff --git a/src/arm/nxp/imx/imx7d-mba7.dts b/src/arm/nxp/imx/imx7d-mba7.dts index 32bf9fa9d00..0443faa3dfa 100644 --- a/src/arm/nxp/imx/imx7d-mba7.dts +++ b/src/arm/nxp/imx/imx7d-mba7.dts @@ -21,8 +21,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2>; phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; phy-supply = <®_fec2_pwdn>; phy-handle = <ðphy2_0>; fsl,magic-packet; @@ -35,59 +33,85 @@ ethphy2_0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2_phy>; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; ti,clk-output-sel = ; + reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <500>; }; }; }; +&gpio2 { + pcie-dis-hog { + gpio-hog; + gpios = <29 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "pcie-dis"; + }; + + pcie-rst-hog { + gpio-hog; + gpios = <12 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "pcie-rst"; + }; +}; + &iomuxc { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog_mba7_1>; + pinctrl-0 = <&pinctrl_hog_mba7_1>, <&pinctrl_hog_pcie>; pinctrl_enet2: enet2grp { - fsl,pins = < - MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x02 - MX7D_PAD_SD2_WP__ENET2_MDC 0x00 - MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x71 - MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x71 - MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x71 - MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x71 - MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x71 - MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x71 - MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x79 - MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x79 - MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x79 - MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x79 - MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x79 - MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x79 + fsl,pins = + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_enet2_phy: enet2phygrp { + fsl,pins = /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */ - MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x40000070 + , /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */ - MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x40000078 - >; + ; + }; + + pinctrl_hog_pcie: hogpciegrp { + fsl,pins = + /* #pcie_rst */ + , + /* #pcie_dis */ + ; }; pinctrl_pcie: pciegrp { - fsl,pins = < + fsl,pins = /* #pcie_wake */ - MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x70 - /* #pcie_rst */ - MX7D_PAD_SD2_CLK__GPIO5_IO12 0x70 - /* #pcie_dis */ - MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x70 - >; + ; }; }; &iomuxc_lpsr { pinctrl_usbotg2: usbotg2grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c - MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59 - >; + fsl,pins = + , + ; }; }; @@ -98,16 +122,14 @@ /* probe deferral not supported */ /* pcie-bus-supply = <®_mpcie_1v5>; */ reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; - status = "okay"; + status = "disabled"; }; &usbotg2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg2>; vbus-supply = <®_usb_otg2_vbus>; - srp-disable; - hnp-disable; - adp-disable; + disable-over-current; dr_mode = "host"; status = "okay"; }; diff --git a/src/arm/nxp/imx/imx7s-warp.dts b/src/arm/nxp/imx/imx7s-warp.dts index ba7231b364b..7bab113ca6d 100644 --- a/src/arm/nxp/imx/imx7s-warp.dts +++ b/src/arm/nxp/imx/imx7s-warp.dts @@ -210,6 +210,7 @@ remote-endpoint = <&mipi_from_sensor>; clock-lanes = <0>; data-lanes = <1>; + link-frequencies = /bits/ 64 <330000000>; }; }; }; diff --git a/src/arm/nxp/ls/ls1021a.dtsi b/src/arm/nxp/ls/ls1021a.dtsi index d471cc5efa9..e86998ca77d 100644 --- a/src/arm/nxp/ls/ls1021a.dtsi +++ b/src/arm/nxp/ls/ls1021a.dtsi @@ -808,7 +808,9 @@ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; + usb3-lpm-capable; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; }; pcie@3400000 { diff --git a/src/arm/nxp/mxs/imx28-evk.dts b/src/arm/nxp/mxs/imx28-evk.dts index 9ebb7371e23..330d3aff6b6 100644 --- a/src/arm/nxp/mxs/imx28-evk.dts +++ b/src/arm/nxp/mxs/imx28-evk.dts @@ -198,7 +198,7 @@ clocks = <&saif0>; }; - at24@51 { + eeprom@51 { compatible = "atmel,24c32"; pagesize = <32>; reg = <0x51>; diff --git a/src/arm/qcom/qcom-apq8026-lg-lenok.dts b/src/arm/qcom/qcom-apq8026-lg-lenok.dts index 0a1fd5eb3c6..a70de21bf13 100644 --- a/src/arm/qcom/qcom-apq8026-lg-lenok.dts +++ b/src/arm/qcom/qcom-apq8026-lg-lenok.dts @@ -7,6 +7,7 @@ #include "qcom-msm8226.dtsi" #include "pm8226.dtsi" +#include /delete-node/ &adsp_region; @@ -56,6 +57,29 @@ pinctrl-names = "default"; pinctrl-0 = <&wlan_regulator_default_state>; }; + + pwm_vibrator: pwm { + compatible = "clk-pwm"; + clocks = <&mmcc CAMSS_GP0_CLK>; + + pinctrl-0 = <&vibrator_clk_default_state>; + pinctrl-names = "default"; + + #pwm-cells = <2>; + }; + + vibrator { + compatible = "pwm-vibrator"; + + pwms = <&pwm_vibrator 0 10000>; + pwm-names = "enable"; + + vcc-supply = <&pm8226_l28>; + enable-gpios = <&tlmm 62 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&vibrator_en_default_state>; + pinctrl-names = "default"; + }; }; &adsp { @@ -330,6 +354,20 @@ }; }; + vibrator_clk_default_state: vibrator-clk-default-state { + pins = "gpio33"; + function = "gp0_clk"; + drive-strength = <2>; + bias-disable; + }; + + vibrator_en_default_state: vibrator-en-default-state { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + wlan_hostwake_default_state: wlan-hostwake-default-state { pins = "gpio37"; function = "gpio"; diff --git a/src/arm/qcom/qcom-apq8026-samsung-matisse-wifi.dts b/src/arm/qcom/qcom-apq8026-samsung-matisse-wifi.dts index cffc069712b..da3be658e82 100644 --- a/src/arm/qcom/qcom-apq8026-samsung-matisse-wifi.dts +++ b/src/arm/qcom/qcom-apq8026-samsung-matisse-wifi.dts @@ -5,142 +5,13 @@ /dts-v1/; -#include -#include "qcom-msm8226.dtsi" -#include "pm8226.dtsi" - -/delete-node/ &adsp_region; -/delete-node/ &smem_region; +#include "qcom-msm8226-samsung-matisse-common.dtsi" / { model = "Samsung Galaxy Tab 4 10.1"; compatible = "samsung,matisse-wifi", "qcom,apq8026"; chassis-type = "tablet"; - aliases { - mmc0 = &sdhc_1; /* SDC1 eMMC slot */ - mmc1 = &sdhc_2; /* SDC2 SD card slot */ - display0 = &framebuffer0; - }; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - stdout-path = "display0"; - - framebuffer0: framebuffer@3200000 { - compatible = "simple-framebuffer"; - reg = <0x03200000 0x800000>; - width = <1280>; - height = <800>; - stride = <(1280 * 3)>; - format = "r8g8b8"; - }; - }; - - gpio-hall-sensor { - compatible = "gpio-keys"; - - event-hall-sensor { - label = "Hall Effect Sensor"; - gpios = <&tlmm 110 GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - debounce-interval = <15>; - linux,can-disable; - wakeup-source; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - key-home { - label = "Home"; - gpios = <&tlmm 108 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <15>; - }; - - key-volume-down { - label = "Volume Down"; - gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <15>; - }; - - key-volume-up { - label = "Volume Up"; - gpios = <&tlmm 106 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <15>; - }; - }; - - i2c-backlight { - compatible = "i2c-gpio"; - sda-gpios = <&tlmm 20 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&tlmm 21 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - - pinctrl-0 = <&backlight_i2c_default_state>; - pinctrl-names = "default"; - - i2c-gpio,delay-us = <4>; - - #address-cells = <1>; - #size-cells = <0>; - - backlight@2c { - compatible = "ti,lp8556"; - reg = <0x2c>; - - dev-ctrl = /bits/ 8 <0x80>; - init-brt = /bits/ 8 <0x3f>; - - pwms = <&backlight_pwm 0 100000>; - pwm-names = "lp8556"; - - rom-a0h { - rom-addr = /bits/ 8 <0xa0>; - rom-val = /bits/ 8 <0x44>; - }; - - rom-a1h { - rom-addr = /bits/ 8 <0xa1>; - rom-val = /bits/ 8 <0x6c>; - }; - - rom-a5h { - rom-addr = /bits/ 8 <0xa5>; - rom-val = /bits/ 8 <0x24>; - }; - }; - }; - - backlight_pwm: pwm { - compatible = "clk-pwm"; - #pwm-cells = <2>; - clocks = <&mmcc CAMSS_GP0_CLK>; - pinctrl-0 = <&backlight_pwm_default_state>; - pinctrl-names = "default"; - }; - - reg_tsp_1p8v: regulator-tsp-1p8v { - compatible = "regulator-fixed"; - regulator-name = "tsp_1p8v"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&tsp_en_default_state>; - }; - reg_tsp_3p3v: regulator-tsp-3p3v { compatible = "regulator-fixed"; regulator-name = "tsp_3p3v"; @@ -153,74 +24,6 @@ pinctrl-names = "default"; pinctrl-0 = <&tsp_en1_default_state>; }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer@3200000 { - reg = <0x03200000 0x800000>; - no-map; - }; - - mpss@8400000 { - reg = <0x08400000 0x1f00000>; - no-map; - }; - - mba@a300000 { - reg = <0x0a300000 0x100000>; - no-map; - }; - - reserved@cb00000 { - reg = <0x0cb00000 0x700000>; - no-map; - }; - - wcnss@d200000 { - reg = <0x0d200000 0x700000>; - no-map; - }; - - adsp_region: adsp@d900000 { - reg = <0x0d900000 0x1800000>; - no-map; - }; - - venus@f100000 { - reg = <0x0f100000 0x500000>; - no-map; - }; - - smem_region: smem@fa00000 { - reg = <0x0fa00000 0x100000>; - no-map; - }; - - reserved@fb00000 { - reg = <0x0fb00000 0x260000>; - no-map; - }; - - rfsa@fd60000 { - reg = <0x0fd60000 0x20000>; - no-map; - }; - - rmtfs@fd80000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0fd80000 0x180000>; - no-map; - - qcom,client-id = <1>; - }; - }; -}; - -&adsp { - status = "okay"; }; &blsp1_i2c2 { @@ -243,21 +46,6 @@ }; }; -&blsp1_i2c4 { - status = "okay"; - - muic: usb-switch@25 { - compatible = "siliconmitus,sm5502-muic"; - reg = <0x25>; - - interrupt-parent = <&tlmm>; - interrupts = <67 IRQ_TYPE_EDGE_FALLING>; - - pinctrl-names = "default"; - pinctrl-0 = <&muic_int_default_state>; - }; -}; - &blsp1_i2c5 { status = "okay"; @@ -268,6 +56,13 @@ interrupt-parent = <&tlmm>; interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + linux,keycodes = , + , + , + , + , + ; + pinctrl-names = "default"; pinctrl-0 = <&tsp_int_rst_default_state>; @@ -278,242 +73,19 @@ }; }; -&rpm_requests { - regulators { - compatible = "qcom,rpm-pm8226-regulators"; - - pm8226_s3: s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; - }; - - pm8226_s4: s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8226_s5: s5 { - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - }; - - pm8226_l1: l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - pm8226_l2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8226_l3: l3 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1337500>; - regulator-always-on; - }; - - pm8226_l4: l4 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8226_l5: l5 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8226_l6: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - pm8226_l7: l7 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <1850000>; - }; - - pm8226_l8: l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - pm8226_l9: l9 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - pm8226_l10: l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8226_l12: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8226_l14: l14 { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <2750000>; - }; - - pm8226_l15: l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - pm8226_l16: l16 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3350000>; - }; - - pm8226_l17: l17 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-system-load = <200000>; - regulator-allow-set-load; - regulator-always-on; - }; - - pm8226_l18: l18 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - }; - - pm8226_l19: l19 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3000000>; - }; - - pm8226_l20: l20 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - pm8226_l21: l21 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pm8226_l22: l22 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - - pm8226_l23: l23 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - pm8226_l24: l24 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1350000>; - }; - - pm8226_l25: l25 { - regulator-min-microvolt = <1775000>; - regulator-max-microvolt = <2125000>; - }; - - pm8226_l26: l26 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1300000>; - }; - - pm8226_l27: l27 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8226_l28: l28 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pm8226_lvs1: lvs1 {}; - }; +&pm8226_l3 { + regulator-max-microvolt = <1337500>; }; -&sdhc_1 { - vmmc-supply = <&pm8226_l17>; - vqmmc-supply = <&pm8226_l6>; - - bus-width = <8>; - non-removable; - - status = "okay"; -}; - -&sdhc_2 { - vmmc-supply = <&pm8226_l18>; - vqmmc-supply = <&pm8226_l21>; - - bus-width = <4>; - cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; - - status = "okay"; +&pm8226_s4 { + regulator-max-microvolt = <1800000>; }; &tlmm { - accel_int_default_state: accel-int-default-state { - pins = "gpio54"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - backlight_i2c_default_state: backlight-i2c-default-state { - pins = "gpio20", "gpio21"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - backlight_pwm_default_state: backlight-pwm-default-state { - pins = "gpio33"; - function = "gp0_clk"; - }; - - muic_int_default_state: muic-int-default-state { - pins = "gpio67"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - tsp_en_default_state: tsp-en-default-state { - pins = "gpio31"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - tsp_en1_default_state: tsp-en1-default-state { pins = "gpio73"; function = "gpio"; drive-strength = <2>; bias-disable; }; - - tsp_int_rst_default_state: tsp-int-rst-default-state { - pins = "gpio17"; - function = "gpio"; - drive-strength = <10>; - bias-pull-up; - }; -}; - -&usb { - extcon = <&muic>, <&muic>; - status = "okay"; -}; - -&usb_hs_phy { - extcon = <&muic>; - v1p8-supply = <&pm8226_l10>; - v3p3-supply = <&pm8226_l20>; }; diff --git a/src/arm/qcom/qcom-apq8064.dtsi b/src/arm/qcom/qcom-apq8064.dtsi index 3faf57035d5..9a5ba978775 100644 --- a/src/arm/qcom/qcom-apq8064.dtsi +++ b/src/arm/qcom/qcom-apq8064.dtsi @@ -190,7 +190,7 @@ cpu-pmu { compatible = "qcom,krait-pmu"; - interrupts = <1 10 0x304>; + interrupts = ; }; clocks { @@ -244,7 +244,7 @@ modem_smsm: modem@1 { reg = <1>; - interrupts = <0 38 IRQ_TYPE_EDGE_RISING>; + interrupts = ; interrupt-controller; #interrupt-cells = <2>; @@ -252,7 +252,7 @@ q6_smsm: q6@2 { reg = <2>; - interrupts = <0 89 IRQ_TYPE_EDGE_RISING>; + interrupts = ; interrupt-controller; #interrupt-cells = <2>; @@ -260,7 +260,7 @@ wcnss_smsm: wcnss@3 { reg = <3>; - interrupts = <0 204 IRQ_TYPE_EDGE_RISING>; + interrupts = ; interrupt-controller; #interrupt-cells = <2>; @@ -268,7 +268,7 @@ dsps_smsm: dsps@4 { reg = <4>; - interrupts = <0 137 IRQ_TYPE_EDGE_RISING>; + interrupts = ; interrupt-controller; #interrupt-cells = <2>; @@ -299,7 +299,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&ps_hold>; @@ -321,9 +321,9 @@ timer@200a000 { compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer", "qcom,msm-timer"; - interrupts = <1 1 0x301>, - <1 2 0x301>, - <1 3 0x301>; + interrupts = , + , + ; reg = <0x0200a000 0x100>; clock-frequency = <27000000>; cpu-offset = <0x80000>; @@ -365,28 +365,44 @@ #clock-cells = <0>; }; - saw0: power-controller@2089000 { + saw0: power-manager@2089000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw0_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; - saw1: power-controller@2099000 { + saw1: power-manager@2099000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw1_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; - saw2: power-controller@20a9000 { + saw2: power-manager@20a9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw2_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; - saw3: power-controller@20b9000 { + saw3: power-manager@20b9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw3_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; sps_sic_non_secure: sps-sic-non-secure@12100000 { @@ -411,7 +427,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x12450000 0x100>, <0x12400000 0x03>; - interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -423,7 +439,7 @@ pinctrl-1 = <&i2c1_pins_sleep>; pinctrl-names = "default", "sleep"; reg = <0x12460000 0x1000>; - interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; @@ -452,7 +468,7 @@ pinctrl-0 = <&i2c2_pins>; pinctrl-1 = <&i2c2_pins_sleep>; pinctrl-names = "default", "sleep"; - interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; @@ -539,7 +555,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x1a240000 0x100>, <0x1a200000 0x03>; - interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -548,7 +564,7 @@ gsbi5_spi: spi@1a280000 { compatible = "qcom,spi-qup-v1.1.1"; reg = <0x1a280000 0x1000>; - interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; pinctrl-0 = <&spi5_default>; pinctrl-1 = <&spi5_sleep>; pinctrl-names = "default", "sleep"; @@ -575,7 +591,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16540000 0x100>, <0x16500000 0x03>; - interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -611,7 +627,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16640000 0x1000>, <0x16600000 0x1000>; - interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -908,7 +924,7 @@ sdcc3bam: dma-controller@12182000 { compatible = "qcom,bam-v1.3.0"; reg = <0x12182000 0x8000>; - interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&gcc SDC3_H_CLK>; clock-names = "bam_clk"; #dma-cells = <1>; @@ -936,7 +952,7 @@ sdcc4bam: dma-controller@121c2000 { compatible = "qcom,bam-v1.3.0"; reg = <0x121c2000 0x8000>; - interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&gcc SDC4_H_CLK>; clock-names = "bam_clk"; #dma-cells = <1>; @@ -965,7 +981,7 @@ sdcc1bam: dma-controller@12402000 { compatible = "qcom,bam-v1.3.0"; reg = <0x12402000 0x8000>; - interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&gcc SDC1_H_CLK>; clock-names = "bam_clk"; #dma-cells = <1>; diff --git a/src/arm/qcom/qcom-apq8084.dtsi b/src/arm/qcom/qcom-apq8084.dtsi index 2b1f9d0fb51..8204e64d9a9 100644 --- a/src/arm/qcom/qcom-apq8084.dtsi +++ b/src/arm/qcom/qcom-apq8084.dtsi @@ -629,30 +629,29 @@ }; }; - saw0: power-controller@f9089000 { + saw0: power-manager@f9089000 { compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; }; - saw1: power-controller@f9099000 { + saw1: power-manager@f9099000 { compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; }; - saw2: power-controller@f90a9000 { + saw2: power-manager@f90a9000 { compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; }; - saw3: power-controller@f90b9000 { + saw3: power-manager@f90b9000 { compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; }; - saw_l2: power-controller@f9012000 { - compatible = "qcom,saw2"; + saw_l2: power-manager@f9012000 { + compatible = "qcom,apq8084-saw2-v2.1-l2", "qcom,saw2"; reg = <0xf9012000 0x1000>; - regulator; }; acc0: power-manager@f9088000 { diff --git a/src/arm/qcom/qcom-ipq4019-ap.dk01.1.dtsi b/src/arm/qcom/qcom-ipq4019-ap.dk01.1.dtsi index 0505270cf50..f7ac8f9d0b6 100644 --- a/src/arm/qcom/qcom-ipq4019-ap.dk01.1.dtsi +++ b/src/arm/qcom/qcom-ipq4019-ap.dk01.1.dtsi @@ -27,87 +27,83 @@ chosen { stdout-path = "serial0:115200n8"; }; +}; - soc { - rng@22000 { - status = "okay"; +&prng { + status = "okay"; +}; + +&tlmm { + serial_pins: serial_pinmux { + mux { + pins = "gpio60", "gpio61"; + function = "blsp_uart0"; + bias-disable; }; + }; - pinctrl@1000000 { - serial_pins: serial_pinmux { - mux { - pins = "gpio60", "gpio61"; - function = "blsp_uart0"; - bias-disable; - }; - }; - - spi_0_pins: spi_0_pinmux { - pinmux { - function = "blsp_spi0"; - pins = "gpio55", "gpio56", "gpio57"; - }; - pinmux_cs { - function = "gpio"; - pins = "gpio54"; - }; - pinconf { - pins = "gpio55", "gpio56", "gpio57"; - drive-strength = <12>; - bias-disable; - }; - pinconf_cs { - pins = "gpio54"; - drive-strength = <2>; - bias-disable; - output-high; - }; - }; + spi_0_pins: spi_0_pinmux { + pinmux { + function = "blsp_spi0"; + pins = "gpio55", "gpio56", "gpio57"; }; - - blsp_dma: dma-controller@7884000 { - status = "okay"; + pinmux_cs { + function = "gpio"; + pins = "gpio54"; }; - - spi@78b5000 { - pinctrl-0 = <&spi_0_pins>; - pinctrl-names = "default"; - status = "okay"; - cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>; - - mx25l25635e@0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - compatible = "mx25l25635e"; - spi-max-frequency = <24000000>; - }; + pinconf { + pins = "gpio55", "gpio56", "gpio57"; + drive-strength = <12>; + bias-disable; }; - - serial@78af000 { - pinctrl-0 = <&serial_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - cryptobam: dma-controller@8e04000 { - status = "okay"; - }; - - crypto@8e3a000 { - status = "okay"; - }; - - watchdog@b017000 { - status = "okay"; - }; - - wifi@a000000 { - status = "okay"; - }; - - wifi@a800000 { - status = "okay"; + pinconf_cs { + pins = "gpio54"; + drive-strength = <2>; + bias-disable; + output-high; }; }; }; + +&blsp_dma { + status = "okay"; +}; + +&blsp1_spi1 { + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + status = "okay"; + cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>; + + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <24000000>; + }; +}; + +&blsp1_uart1 { + pinctrl-0 = <&serial_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&cryptobam { + status = "okay"; +}; + +&crypto { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&wifi0 { + status = "okay"; +}; + +&wifi1 { + status = "okay"; +}; diff --git a/src/arm/qcom/qcom-ipq4019.dtsi b/src/arm/qcom/qcom-ipq4019.dtsi index f989bd741cd..681cb3fc808 100644 --- a/src/arm/qcom/qcom-ipq4019.dtsi +++ b/src/arm/qcom/qcom-ipq4019.dtsi @@ -162,10 +162,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts = <1 2 0xf08>, - <1 3 0xf08>, - <1 4 0xf08>, - <1 1 0xf08>; + interrupts = , + , + , + ; clock-frequency = <48000000>; always-on; }; @@ -350,34 +350,29 @@ reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; }; - saw0: regulator@b089000 { - compatible = "qcom,saw2"; + saw0: power-manager@b089000 { + compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>; - regulator; }; - saw1: regulator@b099000 { - compatible = "qcom,saw2"; + saw1: power-manager@b099000 { + compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; - regulator; }; - saw2: regulator@b0a9000 { - compatible = "qcom,saw2"; + saw2: power-manager@b0a9000 { + compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; - regulator; }; - saw3: regulator@b0b9000 { - compatible = "qcom,saw2"; + saw3: power-manager@b0b9000 { + compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; - regulator; }; - saw_l2: regulator@b012000 { - compatible = "qcom,saw2"; + saw_l2: power-manager@b012000 { + compatible = "qcom,ipq4019-saw2-l2", "qcom,saw2"; reg = <0xb012000 0x1000>; - regulator; }; blsp1_uart1: serial@78af000 { @@ -684,7 +679,7 @@ clocks = <&gcc GCC_USB2_MASTER_CLK>, <&gcc GCC_USB2_SLEEP_CLK>, <&gcc GCC_USB2_MOCK_UTMI_CLK>; - clock-names = "master", "sleep", "mock_utmi"; + clock-names = "core", "sleep", "mock_utmi"; ranges; status = "disabled"; diff --git a/src/arm/qcom/qcom-ipq8064.dtsi b/src/arm/qcom/qcom-ipq8064.dtsi index 6a7f4dd0f77..2eb6758b6a3 100644 --- a/src/arm/qcom/qcom-ipq8064.dtsi +++ b/src/arm/qcom/qcom-ipq8064.dtsi @@ -586,10 +586,9 @@ #clock-cells = <0>; }; - saw0: regulator@2089000 { - compatible = "qcom,saw2"; + saw0: power-manager@2089000 { + compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; }; acc1: clock-controller@2098000 { @@ -601,10 +600,9 @@ #clock-cells = <0>; }; - saw1: regulator@2099000 { - compatible = "qcom,saw2"; + saw1: power-manager@2099000 { + compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; }; nss_common: syscon@3000000 { @@ -623,7 +621,6 @@ ranges; resets = <&gcc USB30_0_MASTER_RESET>; - reset-names = "master"; status = "disabled"; @@ -669,7 +666,6 @@ ranges; resets = <&gcc USB30_1_MASTER_RESET>; - reset-names = "master"; status = "disabled"; diff --git a/src/arm/qcom/qcom-msm8226-samsung-matisse-common.dtsi b/src/arm/qcom/qcom-msm8226-samsung-matisse-common.dtsi new file mode 100644 index 00000000000..a15a44fc018 --- /dev/null +++ b/src/arm/qcom/qcom-msm8226-samsung-matisse-common.dtsi @@ -0,0 +1,457 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Matti Lehtimäki + */ + +#include +#include "qcom-msm8226.dtsi" +#include "pm8226.dtsi" + +/delete-node/ &adsp_region; +/delete-node/ &smem_region; + +/ { + aliases { + mmc0 = &sdhc_1; /* SDC1 eMMC slot */ + mmc1 = &sdhc_2; /* SDC2 SD card slot */ + display0 = &framebuffer0; + }; + + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + stdout-path = "display0"; + + framebuffer0: framebuffer@3200000 { + compatible = "simple-framebuffer"; + reg = <0x03200000 0x800000>; + width = <1280>; + height = <800>; + stride = <(1280 * 3)>; + format = "r8g8b8"; + }; + }; + + gpio-hall-sensor { + compatible = "gpio-keys"; + + event-hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&tlmm 110 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + key-home { + label = "Home"; + gpios = <&tlmm 108 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&tlmm 106 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + }; + + i2c-backlight { + compatible = "i2c-gpio"; + sda-gpios = <&tlmm 20 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 21 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-0 = <&backlight_i2c_default_state>; + pinctrl-names = "default"; + + i2c-gpio,delay-us = <4>; + + #address-cells = <1>; + #size-cells = <0>; + + backlight@2c { + compatible = "ti,lp8556"; + reg = <0x2c>; + + dev-ctrl = /bits/ 8 <0x80>; + init-brt = /bits/ 8 <0x3f>; + + pwms = <&backlight_pwm 0 100000>; + pwm-names = "lp8556"; + + rom-a0h { + rom-addr = /bits/ 8 <0xa0>; + rom-val = /bits/ 8 <0x44>; + }; + + rom-a1h { + rom-addr = /bits/ 8 <0xa1>; + rom-val = /bits/ 8 <0x6c>; + }; + + rom-a5h { + rom-addr = /bits/ 8 <0xa5>; + rom-val = /bits/ 8 <0x24>; + }; + }; + }; + + backlight_pwm: pwm { + compatible = "clk-pwm"; + #pwm-cells = <2>; + clocks = <&mmcc CAMSS_GP0_CLK>; + pinctrl-0 = <&backlight_pwm_default_state>; + pinctrl-names = "default"; + }; + + reg_tsp_1p8v: regulator-tsp-1p8v { + compatible = "regulator-fixed"; + regulator-name = "tsp_1p8v"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&tsp_en_default_state>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer@3200000 { + reg = <0x03200000 0x800000>; + no-map; + }; + + mpss@8400000 { + reg = <0x08400000 0x1f00000>; + no-map; + }; + + mba@a300000 { + reg = <0x0a300000 0x100000>; + no-map; + }; + + reserved@cb00000 { + reg = <0x0cb00000 0x700000>; + no-map; + }; + + wcnss@d200000 { + reg = <0x0d200000 0x700000>; + no-map; + }; + + adsp_region: adsp@d900000 { + reg = <0x0d900000 0x1800000>; + no-map; + }; + + venus@f100000 { + reg = <0x0f100000 0x500000>; + no-map; + }; + + smem_region: smem@fa00000 { + reg = <0x0fa00000 0x100000>; + no-map; + }; + + reserved@fb00000 { + reg = <0x0fb00000 0x260000>; + no-map; + }; + + rfsa@fd60000 { + reg = <0x0fd60000 0x20000>; + no-map; + }; + + rmtfs@fd80000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0fd80000 0x180000>; + no-map; + + qcom,client-id = <1>; + }; + }; +}; + +&adsp { + status = "okay"; +}; + +&blsp1_i2c4 { + status = "okay"; + + muic: usb-switch@25 { + compatible = "siliconmitus,sm5502-muic"; + reg = <0x25>; + + interrupt-parent = <&tlmm>; + interrupts = <67 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&muic_int_default_state>; + }; +}; + +&blsp1_uart3 { + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8226-regulators"; + + pm8226_s3: s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + pm8226_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2200000>; + }; + + pm8226_s5: s5 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + }; + + pm8226_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8226_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l3: l3 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + pm8226_l4: l4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l5: l5 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8226_l7: l7 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1850000>; + }; + + pm8226_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8226_l9: l9 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8226_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l14: l14 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + }; + + pm8226_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8226_l16: l16 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3350000>; + }; + + pm8226_l17: l17 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + regulator-system-load = <200000>; + regulator-allow-set-load; + regulator-always-on; + }; + + pm8226_l18: l18 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l19: l19 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3000000>; + }; + + pm8226_l20: l20 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pm8226_l21: l21 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l22: l22 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + + pm8226_l23: l23 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8226_l24: l24 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; + }; + + pm8226_l25: l25 { + regulator-min-microvolt = <1775000>; + regulator-max-microvolt = <2125000>; + }; + + pm8226_l26: l26 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1300000>; + }; + + pm8226_l27: l27 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l28: l28 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_lvs1: lvs1 {}; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8226_l17>; + vqmmc-supply = <&pm8226_l6>; + + bus-width = <8>; + non-removable; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&pm8226_l18>; + vqmmc-supply = <&pm8226_l21>; + + bus-width = <4>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&tlmm { + accel_int_default_state: accel-int-default-state { + pins = "gpio54"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + backlight_i2c_default_state: backlight-i2c-default-state { + pins = "gpio20", "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + backlight_pwm_default_state: backlight-pwm-default-state { + pins = "gpio33"; + function = "gp0_clk"; + }; + + muic_int_default_state: muic-int-default-state { + pins = "gpio67"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_en_default_state: tsp-en-default-state { + pins = "gpio31"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_int_rst_default_state: tsp-int-rst-default-state { + pins = "gpio17"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + }; +}; + +&usb { + extcon = <&muic>, <&muic>; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&muic>; + v1p8-supply = <&pm8226_l10>; + v3p3-supply = <&pm8226_l20>; +}; diff --git a/src/arm/qcom/qcom-msm8226.dtsi b/src/arm/qcom/qcom-msm8226.dtsi index b492c95e5d3..270973e8562 100644 --- a/src/arm/qcom/qcom-msm8226.dtsi +++ b/src/arm/qcom/qcom-msm8226.dtsi @@ -20,11 +20,6 @@ chosen { }; - memory@0 { - device_type = "memory"; - reg = <0x0 0x0>; - }; - clocks { xo_board: xo_board { compatible = "fixed-clock"; @@ -39,6 +34,57 @@ }; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + compatible = "arm,cortex-a7"; + enable-method = "qcom,msm8226-smp"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; + }; + + CPU1: cpu@1 { + compatible = "arm,cortex-a7"; + enable-method = "qcom,msm8226-smp"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; + }; + + CPU2: cpu@2 { + compatible = "arm,cortex-a7"; + enable-method = "qcom,msm8226-smp"; + device_type = "cpu"; + reg = <2>; + next-level-cache = <&L2>; + qcom,acc = <&acc2>; + qcom,saw = <&saw2>; + }; + + CPU3: cpu@3 { + compatible = "arm,cortex-a7"; + enable-method = "qcom,msm8226-smp"; + device_type = "cpu"; + reg = <3>; + next-level-cache = <&L2>; + qcom,acc = <&acc3>; + qcom,saw = <&saw3>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + firmware { scm { compatible = "qcom,scm-msm8226", "qcom,scm"; @@ -47,6 +93,11 @@ }; }; + memory@0 { + device_type = "memory"; + reg = <0x0 0x0>; + }; + pmu { compatible = "arm,cortex-a7-pmu"; interrupts = ; }; + saw_l2: power-manager@f9012000 { + compatible = "qcom,msm8226-saw2-v2.1-l2", "qcom,saw2"; + reg = <0xf9012000 0x1000>; + }; + + watchdog@f9017000 { + compatible = "qcom,apss-wdt-msm8226", "qcom,kpss-wdt"; + reg = <0xf9017000 0x1000>; + interrupts = , + ; + clocks = <&sleep_clk>; + }; + + timer@f9020000 { + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + frame@f9021000 { + frame-number = <0>; + interrupts = , + ; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = ; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = ; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = ; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = ; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = ; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = ; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + }; + + acc0: power-manager@f9088000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; + }; + + saw0: power-manager@f9089000 { + compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf9089000 0x1000>; + }; + + acc1: power-manager@f9098000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; + }; + + saw1: power-manager@f9099000 { + compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf9099000 0x1000>; + }; + + acc2: power-manager@f90a8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; + }; + + saw2: power-manager@f90a9000 { + compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf90a9000 0x1000>; + }; + + acc3: power-manager@f90b8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; + }; + + saw3: power-manager@f90b9000 { + compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf90b9000 0x1000>; + }; + sdhc_1: mmc@f9824900 { compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; @@ -201,22 +363,6 @@ status = "disabled"; }; - sdhc_2: mmc@f98a4900 { - compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc", "core"; - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_AHB_CLK>, - <&gcc GCC_SDCC2_APPS_CLK>, - <&rpmcc RPM_SMD_XO_CLK_SRC>; - clock-names = "iface", "core", "xo"; - pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_default_state>; - status = "disabled"; - }; - sdhc_3: mmc@f9864900 { compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; @@ -233,6 +379,22 @@ status = "disabled"; }; + sdhc_2: mmc@f98a4900 { + compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc", "core"; + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "core", "xo"; + pinctrl-names = "default"; + pinctrl-0 = <&sdhc2_default_state>; + status = "disabled"; + }; + blsp1_uart1: serial@f991d000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf991d000 0x1000>; @@ -272,7 +434,6 @@ }; blsp1_i2c1: i2c@f9923000 { - status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; reg = <0xf9923000 0x1000>; interrupts = ; @@ -282,10 +443,10 @@ pinctrl-0 = <&blsp1_i2c1_pins>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; blsp1_i2c2: i2c@f9924000 { - status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; reg = <0xf9924000 0x1000>; interrupts = ; @@ -295,10 +456,10 @@ pinctrl-0 = <&blsp1_i2c2_pins>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; blsp1_i2c3: i2c@f9925000 { - status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; reg = <0xf9925000 0x1000>; interrupts = ; @@ -308,10 +469,10 @@ pinctrl-0 = <&blsp1_i2c3_pins>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; blsp1_i2c4: i2c@f9926000 { - status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; reg = <0xf9926000 0x1000>; interrupts = ; @@ -321,10 +482,10 @@ pinctrl-0 = <&blsp1_i2c4_pins>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; blsp1_i2c5: i2c@f9927000 { - status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; reg = <0xf9927000 0x1000>; interrupts = ; @@ -334,6 +495,7 @@ pinctrl-0 = <&blsp1_i2c5_pins>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; blsp1_i2c6: i2c@f9928000 { @@ -351,33 +513,6 @@ status = "disabled"; }; - cci: cci@fda0c000 { - compatible = "qcom,msm8226-cci"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfda0c000 0x1000>; - interrupts = ; - clocks = <&mmcc CAMSS_TOP_AHB_CLK>, - <&mmcc CAMSS_CCI_CCI_AHB_CLK>, - <&mmcc CAMSS_CCI_CCI_CLK>; - clock-names = "camss_top_ahb", - "cci_ahb", - "cci"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cci_default>; - pinctrl-1 = <&cci_sleep>; - - status = "disabled"; - - cci_i2c0: i2c-bus@0 { - reg = <0>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - usb: usb@f9a55000 { compatible = "qcom,ci-hdrc"; reg = <0xf9a55000 0x200>, @@ -417,6 +552,18 @@ }; }; + rng@f9bff000 { + compatible = "qcom,prng"; + reg = <0xf9bff000 0x200>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + + sram@fc190000 { + compatible = "qcom,msm8226-rpm-stats"; + reg = <0xfc190000 0x10000>; + }; + gcc: clock-controller@fc400000 { compatible = "qcom,gcc-msm8226"; reg = <0xfc400000 0x4000>; @@ -430,146 +577,28 @@ "sleep_clk"; }; - mmcc: clock-controller@fd8c0000 { - compatible = "qcom,mmcc-msm8226"; - reg = <0xfd8c0000 0x6000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; + rpm_msg_ram: sram@fc428000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0xfc428000 0x4000>; - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, - <&gcc GCC_MMSS_GPLL0_CLK_SRC>, - <&gcc GPLL0_VOTE>, - <&gcc GPLL1_VOTE>, - <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi0_phy 0>; - clock-names = "xo", - "mmss_gpll0_vote", - "gpll0_vote", - "gpll1_vote", - "gfx3d_clk_src", - "dsi0pll", - "dsi0pllbyte"; - }; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfc428000 0x4000>; - tlmm: pinctrl@fd510000 { - compatible = "qcom,msm8226-pinctrl"; - reg = <0xfd510000 0x4000>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&tlmm 0 0 117>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - - blsp1_i2c1_pins: blsp1-i2c1-state { - pins = "gpio2", "gpio3"; - function = "blsp_i2c1"; - drive-strength = <2>; - bias-disable; + apss_master_stats: sram@150 { + reg = <0x150 0x14>; }; - blsp1_i2c2_pins: blsp1-i2c2-state { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - drive-strength = <2>; - bias-disable; + mpss_master_stats: sram@b50 { + reg = <0xb50 0x14>; }; - blsp1_i2c3_pins: blsp1-i2c3-state { - pins = "gpio10", "gpio11"; - function = "blsp_i2c3"; - drive-strength = <2>; - bias-disable; + lpss_master_stats: sram@1550 { + reg = <0x1550 0x14>; }; - blsp1_i2c4_pins: blsp1-i2c4-state { - pins = "gpio14", "gpio15"; - function = "blsp_i2c4"; - drive-strength = <2>; - bias-disable; - }; - - blsp1_i2c5_pins: blsp1-i2c5-state { - pins = "gpio18", "gpio19"; - function = "blsp_i2c5"; - drive-strength = <2>; - bias-disable; - }; - - blsp1_i2c6_pins: blsp1-i2c6-state { - pins = "gpio22", "gpio23"; - function = "blsp_i2c6"; - drive-strength = <2>; - bias-disable; - }; - - cci_default: cci-default-state { - pins = "gpio29", "gpio30"; - function = "cci_i2c0"; - - drive-strength = <2>; - bias-disable; - }; - - cci_sleep: cci-sleep-state { - pins = "gpio29", "gpio30"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - sdhc1_default_state: sdhc1-default-state { - clk-pins { - pins = "sdc1_clk"; - drive-strength = <10>; - bias-disable; - }; - - cmd-data-pins { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdhc2_default_state: sdhc2-default-state { - clk-pins { - pins = "sdc2_clk"; - drive-strength = <10>; - bias-disable; - }; - - cmd-data-pins { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdhc3_default_state: sdhc3-default-state { - clk-pins { - pins = "gpio44"; - function = "sdc3"; - drive-strength = <8>; - bias-disable; - }; - - cmd-pins { - pins = "gpio43"; - function = "sdc3"; - drive-strength = <8>; - bias-pull-up; - }; - - data-pins { - pins = "gpio39", "gpio40", "gpio41", "gpio42"; - function = "sdc3"; - drive-strength = <8>; - bias-pull-up; - }; + pronto_master_stats: sram@1f50 { + reg = <0x1f50 0x14>; }; }; @@ -714,170 +743,153 @@ #interrupt-cells = <4>; }; - rng@f9bff000 { - compatible = "qcom,prng"; - reg = <0xf9bff000 0x200>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - }; - - timer@f9020000 { - compatible = "arm,armv7-timer-mem"; - reg = <0xf9020000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - frame@f9021000 { - frame-number = <0>; - interrupts = , - ; - reg = <0xf9021000 0x1000>, - <0xf9022000 0x1000>; - }; - - frame@f9023000 { - frame-number = <1>; - interrupts = ; - reg = <0xf9023000 0x1000>; - status = "disabled"; - }; - - frame@f9024000 { - frame-number = <2>; - interrupts = ; - reg = <0xf9024000 0x1000>; - status = "disabled"; - }; - - frame@f9025000 { - frame-number = <3>; - interrupts = ; - reg = <0xf9025000 0x1000>; - status = "disabled"; - }; - - frame@f9026000 { - frame-number = <4>; - interrupts = ; - reg = <0xf9026000 0x1000>; - status = "disabled"; - }; - - frame@f9027000 { - frame-number = <5>; - interrupts = ; - reg = <0xf9027000 0x1000>; - status = "disabled"; - }; - - frame@f9028000 { - frame-number = <6>; - interrupts = ; - reg = <0xf9028000 0x1000>; - status = "disabled"; - }; - }; - - sram@fc190000 { - compatible = "qcom,msm8226-rpm-stats"; - reg = <0xfc190000 0x10000>; - }; - - rpm_msg_ram: sram@fc428000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0xfc428000 0x4000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xfc428000 0x4000>; - - apss_master_stats: sram@150 { - reg = <0x150 0x14>; - }; - - mpss_master_stats: sram@b50 { - reg = <0xb50 0x14>; - }; - - lpss_master_stats: sram@1550 { - reg = <0x1550 0x14>; - }; - - pronto_master_stats: sram@1f50 { - reg = <0x1f50 0x14>; - }; - }; - tcsr_mutex: hwlock@fd484000 { compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex"; reg = <0xfd484000 0x1000>; #hwlock-cells = <1>; }; - adsp: remoteproc@fe200000 { - compatible = "qcom,msm8226-adsp-pil"; - reg = <0xfe200000 0x100>; + tlmm: pinctrl@fd510000 { + compatible = "qcom,msm8226-pinctrl"; + reg = <0xfd510000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 117>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; - interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + blsp1_i2c1_pins: blsp1-i2c1-state { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + drive-strength = <2>; + bias-disable; + }; - power-domains = <&rpmpd MSM8226_VDDCX>; - power-domain-names = "cx"; + blsp1_i2c2_pins: blsp1-i2c2-state { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + drive-strength = <2>; + bias-disable; + }; - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; - clock-names = "xo"; + blsp1_i2c3_pins: blsp1-i2c3-state { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + drive-strength = <2>; + bias-disable; + }; - memory-region = <&adsp_region>; + blsp1_i2c4_pins: blsp1-i2c4-state { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + drive-strength = <2>; + bias-disable; + }; - qcom,smem-states = <&adsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; + blsp1_i2c5_pins: blsp1-i2c5-state { + pins = "gpio18", "gpio19"; + function = "blsp_i2c5"; + drive-strength = <2>; + bias-disable; + }; - status = "disabled"; + blsp1_i2c6_pins: blsp1-i2c6-state { + pins = "gpio22", "gpio23"; + function = "blsp_i2c6"; + drive-strength = <2>; + bias-disable; + }; - smd-edge { - interrupts = ; + cci_default: cci-default-state { + pins = "gpio29", "gpio30"; + function = "cci_i2c0"; - qcom,ipc = <&apcs 8 8>; - qcom,smd-edge = <1>; + drive-strength = <2>; + bias-disable; + }; - label = "lpass"; + cci_sleep: cci-sleep-state { + pins = "gpio29", "gpio30"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + sdhc1_default_state: sdhc1-default-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <10>; + bias-disable; + }; + + cmd-data-pins { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdhc2_default_state: sdhc2-default-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <10>; + bias-disable; + }; + + cmd-data-pins { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdhc3_default_state: sdhc3-default-state { + clk-pins { + pins = "gpio44"; + function = "sdc3"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "gpio43"; + function = "sdc3"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "gpio39", "gpio40", "gpio41", "gpio42"; + function = "sdc3"; + drive-strength = <8>; + bias-pull-up; + }; }; }; - sram@fdd00000 { - compatible = "qcom,msm8226-ocmem"; - reg = <0xfdd00000 0x2000>, - <0xfec00000 0x20000>; - reg-names = "ctrl", "mem"; - ranges = <0 0xfec00000 0x20000>; - clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>; - clock-names = "core"; + mmcc: clock-controller@fd8c0000 { + compatible = "qcom,mmcc-msm8226"; + reg = <0xfd8c0000 0x6000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - - gmu_sram: gmu-sram@0 { - reg = <0x0 0x20000>; - }; - }; - - sram@fe805000 { - compatible = "qcom,msm8226-imem", "syscon", "simple-mfd"; - reg = <0xfe805000 0x1000>; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x65c>; - - mode-bootloader = <0x77665500>; - mode-normal = <0x77665501>; - mode-recovery = <0x77665502>; - }; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_MMSS_GPLL0_CLK_SRC>, + <&gcc GPLL0_VOTE>, + <&gcc GPLL1_VOTE>, + <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>; + clock-names = "xo", + "mmss_gpll0_vote", + "gpll0_vote", + "gpll1_vote", + "gfx3d_clk_src", + "dsi0pll", + "dsi0pllbyte"; }; mdss: display-subsystem@fd900000 { @@ -1007,6 +1019,33 @@ }; }; + cci: cci@fda0c000 { + compatible = "qcom,msm8226-cci"; + reg = <0xfda0c000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&mmcc CAMSS_TOP_AHB_CLK>, + <&mmcc CAMSS_CCI_CCI_AHB_CLK>, + <&mmcc CAMSS_CCI_CCI_CLK>; + clock-names = "camss_top_ahb", + "cci_ahb", + "cci"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cci_default>; + pinctrl-1 = <&cci_sleep>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + gpu: adreno@fdb00000 { compatible = "qcom,adreno-305.18", "qcom,adreno"; reg = <0xfdb00000 0x10000>; @@ -1046,6 +1085,71 @@ }; }; }; + + sram@fdd00000 { + compatible = "qcom,msm8226-ocmem"; + reg = <0xfdd00000 0x2000>, + <0xfec00000 0x20000>; + reg-names = "ctrl", "mem"; + ranges = <0 0xfec00000 0x20000>; + clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>; + clock-names = "core"; + + #address-cells = <1>; + #size-cells = <1>; + + gmu_sram: gmu-sram@0 { + reg = <0x0 0x20000>; + }; + }; + + adsp: remoteproc@fe200000 { + compatible = "qcom,msm8226-adsp-pil"; + reg = <0xfe200000 0x100>; + + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + + power-domains = <&rpmpd MSM8226_VDDCX>; + power-domain-names = "cx"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + memory-region = <&adsp_region>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + smd-edge { + interrupts = ; + + qcom,ipc = <&apcs 8 8>; + qcom,smd-edge = <1>; + + label = "lpass"; + }; + }; + + sram@fe805000 { + compatible = "qcom,msm8226-imem", "syscon", "simple-mfd"; + reg = <0xfe805000 0x1000>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x65c>; + + mode-bootloader = <0x77665500>; + mode-normal = <0x77665501>; + mode-recovery = <0x77665502>; + }; + }; }; thermal-zones { diff --git a/src/arm/qcom/qcom-msm8660.dtsi b/src/arm/qcom/qcom-msm8660.dtsi index a7c245b9c8f..455ba4bf1bf 100644 --- a/src/arm/qcom/qcom-msm8660.dtsi +++ b/src/arm/qcom/qcom-msm8660.dtsi @@ -47,7 +47,7 @@ cpu-pmu { compatible = "qcom,scorpion-mp-pmu"; - interrupts = <1 9 0x304>; + interrupts = ; }; clocks { @@ -89,12 +89,11 @@ timer@2000000 { compatible = "qcom,scss-timer", "qcom,msm-timer"; - interrupts = <1 0 0x301>, - <1 1 0x301>, - <1 2 0x301>; + interrupts = , + , + ; reg = <0x02000000 0x100>; - clock-frequency = <27000000>, - <32768>; + clock-frequency = <27000000>; cpu-offset = <0x40000>; }; @@ -105,7 +104,7 @@ gpio-controller; gpio-ranges = <&tlmm 0 0 173>; #gpio-cells = <2>; - interrupts = <0 16 0x4>; + interrupts = ; interrupt-controller; #interrupt-cells = <2>; @@ -283,7 +282,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x19c40000 0x1000>, <0x19c00000 0x1000>; - interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -292,7 +291,7 @@ gsbi12_i2c: i2c@19c80000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x19c80000 0x1000>; - interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; diff --git a/src/arm/qcom/qcom-msm8926-htc-memul.dts b/src/arm/qcom/qcom-msm8926-htc-memul.dts index ed328b24335..3037344eb24 100644 --- a/src/arm/qcom/qcom-msm8926-htc-memul.dts +++ b/src/arm/qcom/qcom-msm8926-htc-memul.dts @@ -107,7 +107,20 @@ }; unknown@fb00000 { - reg = <0x0fb00000 0x1b00000>; + reg = <0x0fb00000 0x280000>; + no-map; + }; + + rmtfs@fd80000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0fd80000 0x180000>; + no-map; + + qcom,client-id = <1>; + }; + + unknown@ff00000 { + reg = <0x0ff00000 0x1700000>; no-map; }; }; diff --git a/src/arm/qcom/qcom-msm8926-samsung-matisselte.dts b/src/arm/qcom/qcom-msm8926-samsung-matisselte.dts new file mode 100644 index 00000000000..d0e1bc39f8e --- /dev/null +++ b/src/arm/qcom/qcom-msm8926-samsung-matisselte.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Matti Lehtimäki + * Copyright (c) 2023, Stefan Hansson + */ + +/dts-v1/; + +#include "qcom-msm8226-samsung-matisse-common.dtsi" + +/ { + model = "Samsung Galaxy Tab 4 10.1 LTE"; + compatible = "samsung,matisselte", "qcom,msm8926", "qcom,msm8226"; + chassis-type = "tablet"; + + reg_tsp_3p3v: regulator-tsp-3p3v { + compatible = "regulator-fixed"; + regulator-name = "tsp_3p3v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 32 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&tsp_en1_default_state>; + }; +}; + +&tlmm { + tsp_en1_default_state: tsp-en1-default-state { + pins = "gpio32"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; diff --git a/src/arm/qcom/qcom-msm8960-pins.dtsi b/src/arm/qcom/qcom-msm8960-pins.dtsi new file mode 100644 index 00000000000..4fa98277128 --- /dev/null +++ b/src/arm/qcom/qcom-msm8960-pins.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only + +&msmgpio { + i2c3_default_state: i2c3-default-state { + i2c3-pins { + pins = "gpio16", "gpio17"; + function = "gsbi3"; + drive-strength = <8>; + bias-disable; + }; + }; + + i2c3_sleep_state: i2c3-sleep-state { + i2c3-pins { + pins = "gpio16", "gpio17"; + function = "gpio"; + drive-strength = <2>; + bias-bus-hold; + }; + }; +}; diff --git a/src/arm/qcom/qcom-msm8960-samsung-expressatt.dts b/src/arm/qcom/qcom-msm8960-samsung-expressatt.dts index 1a5116336ff..af6cc6393d7 100644 --- a/src/arm/qcom/qcom-msm8960-samsung-expressatt.dts +++ b/src/arm/qcom/qcom-msm8960-samsung-expressatt.dts @@ -4,6 +4,9 @@ #include "qcom-msm8960.dtsi" #include "pm8921.dtsi" +#include +#include +#include / { model = "Samsung Galaxy Express SGH-I437"; @@ -19,6 +22,36 @@ chosen { stdout-path = "serial0:115200n8"; }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pin_a>; + + key-home { + label = "Home"; + gpios = <&msmgpio 40 GPIO_ACTIVE_LOW>; + debounce-interval = <5>; + linux,code = ; + wakeup-event-action = ; + wakeup-source; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&msmgpio 50 GPIO_ACTIVE_LOW>; + debounce-interval = <5>; + linux,code = ; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&msmgpio 81 GPIO_ACTIVE_LOW>; + debounce-interval = <5>; + linux,code = ; + }; + }; }; &gsbi5 { @@ -52,6 +85,27 @@ status = "okay"; }; +&gsbi3 { + qcom,mode = ; + status = "okay"; +}; + +&gsbi3_i2c { + status = "okay"; + + // Atmel mXT224S touchscreen + touchscreen@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + interrupt-parent = <&msmgpio>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + vdda-supply = <&pm8921_lvs6>; + vdd-supply = <&pm8921_l17>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen>; + }; +}; + &msmgpio { spi1_default: spi1-default-state { mosi-pins { @@ -83,6 +137,21 @@ bias-disable; }; }; + + gpio_keys_pin_a: gpio-keys-active-state { + pins = "gpio40", "gpio50", "gpio81"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + touchscreen: touchscreen-int-state { + pins = "gpio11"; + function = "gpio"; + output-enable; + bias-disable; + drive-strength = <2>; + }; }; &pm8921 { @@ -245,7 +314,7 @@ }; pm8921_l17: l17 { - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; bias-pull-down; }; diff --git a/src/arm/qcom/qcom-msm8960.dtsi b/src/arm/qcom/qcom-msm8960.dtsi index f420740e068..922f9e49468 100644 --- a/src/arm/qcom/qcom-msm8960.dtsi +++ b/src/arm/qcom/qcom-msm8960.dtsi @@ -220,16 +220,24 @@ #clock-cells = <0>; }; - saw0: regulator@2089000 { - compatible = "qcom,saw2"; + saw0: power-manager@2089000 { + compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw0_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; - saw1: regulator@2099000 { - compatible = "qcom,saw2"; + saw1: power-manager@2099000 { + compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw1_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; gsbi5: gsbi@16400000 { @@ -359,5 +367,33 @@ }; }; }; + + gsbi3: gsbi@16200000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x16200000 0x100>; + ranges; + cell-index = <3>; + clocks = <&gcc GSBI3_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + gsbi3_i2c: i2c@16280000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16280000 0x1000>; + pinctrl-0 = <&i2c3_default_state>; + pinctrl-1 = <&i2c3_sleep_state>; + pinctrl-names = "default", "sleep"; + interrupts = ; + clocks = <&gcc GSBI3_QUP_CLK>, + <&gcc GSBI3_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; }; }; +#include "qcom-msm8960-pins.dtsi" diff --git a/src/arm/qcom/qcom-msm8974.dtsi b/src/arm/qcom/qcom-msm8974.dtsi index b1413983787..5efc38d712c 100644 --- a/src/arm/qcom/qcom-msm8974.dtsi +++ b/src/arm/qcom/qcom-msm8974.dtsi @@ -31,7 +31,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; CPU0: cpu@0 { compatible = "qcom,krait"; @@ -110,7 +110,7 @@ pmu { compatible = "qcom,krait-pmu"; - interrupts = ; + interrupts = ; }; rpm: remoteproc { @@ -346,10 +346,9 @@ reg = <0xf9011000 0x1000>; }; - saw_l2: power-controller@f9012000 { - compatible = "qcom,saw2"; + saw_l2: power-manager@f9012000 { + compatible = "qcom,msm8974-saw2-v2.1-l2", "qcom,saw2"; reg = <0xf9012000 0x1000>; - regulator; }; watchdog@f9017000 { @@ -424,7 +423,7 @@ reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; }; - saw0: power-controller@f9089000 { + saw0: power-manager@f9089000 { compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; }; @@ -434,7 +433,7 @@ reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; }; - saw1: power-controller@f9099000 { + saw1: power-manager@f9099000 { compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; }; @@ -444,7 +443,7 @@ reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; }; - saw2: power-controller@f90a9000 { + saw2: power-manager@f90a9000 { compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; }; @@ -454,7 +453,7 @@ reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; }; - saw3: power-controller@f90b9000 { + saw3: power-manager@f90b9000 { compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; }; @@ -538,7 +537,7 @@ status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; reg = <0xf9923000 0x1000>; - interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; @@ -566,7 +565,7 @@ status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; reg = <0xf9925000 0x1000>; - interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; @@ -666,7 +665,7 @@ status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; reg = <0xf9968000 0x1000>; - interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; @@ -1234,7 +1233,7 @@ qfprom: qfprom@fc4bc000 { compatible = "qcom,msm8974-qfprom", "qcom,qfprom"; - reg = <0xfc4bc000 0x1000>; + reg = <0xfc4bc000 0x2100>; #address-cells = <1>; #size-cells = <1>; @@ -2403,10 +2402,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; clock-frequency = <19200000>; }; }; diff --git a/src/arm/qcom/qcom-sdx55.dtsi b/src/arm/qcom/qcom-sdx55.dtsi index 27429d0fedf..edc9aaf828c 100644 --- a/src/arm/qcom/qcom-sdx55.dtsi +++ b/src/arm/qcom/qcom-sdx55.dtsi @@ -580,12 +580,16 @@ <&gcc GCC_USB30_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 51 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 10 IRQ_TYPE_EDGE_BOTH>, <&pdc 11 IRQ_TYPE_EDGE_BOTH>, - <&pdc 10 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + <&pdc 51 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_GDSC>; @@ -727,57 +731,57 @@ frame@17821000 { frame-number = <0>; - interrupts = , - ; + interrupts = , + ; reg = <0x17821000 0x1000>, <0x17822000 0x1000>; }; frame@17823000 { frame-number = <1>; - interrupts = ; + interrupts = ; reg = <0x17823000 0x1000>; status = "disabled"; }; frame@17824000 { frame-number = <2>; - interrupts = ; + interrupts = ; reg = <0x17824000 0x1000>; status = "disabled"; }; frame@17825000 { frame-number = <3>; - interrupts = ; + interrupts = ; reg = <0x17825000 0x1000>; status = "disabled"; }; frame@17826000 { frame-number = <4>; - interrupts = ; + interrupts = ; reg = <0x17826000 0x1000>; status = "disabled"; }; frame@17827000 { frame-number = <5>; - interrupts = ; + interrupts = ; reg = <0x17827000 0x1000>; status = "disabled"; }; frame@17828000 { frame-number = <6>; - interrupts = ; + interrupts = ; reg = <0x17828000 0x1000>; status = "disabled"; }; frame@17829000 { frame-number = <7>; - interrupts = ; + interrupts = ; reg = <0x17829000 0x1000>; status = "disabled"; }; diff --git a/src/arm/qcom/qcom-sdx65.dtsi b/src/arm/qcom/qcom-sdx65.dtsi index 40591a4da6a..a949454212e 100644 --- a/src/arm/qcom/qcom-sdx65.dtsi +++ b/src/arm/qcom/qcom-sdx65.dtsi @@ -492,23 +492,25 @@ clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, <&gcc GCC_USB30_MASTER_CLK>, <&gcc GCC_USB30_MSTR_AXI_CLK>, - <&gcc GCC_USB30_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SLEEP_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep"; + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", "core", "iface", "sleep", + "mock_utmi"; assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, <&gcc GCC_USB30_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 76 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 19 IRQ_TYPE_EDGE_BOTH>, <&pdc 18 IRQ_TYPE_EDGE_BOTH>, - <&pdc 19 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", - "ss_phy_irq", + <&pdc 76 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", - "dp_hs_phy_irq"; + "ss_phy_irq"; power-domains = <&gcc USB30_GDSC>; @@ -667,57 +669,57 @@ frame@17821000 { frame-number = <0>; - interrupts = , - ; + interrupts = , + ; reg = <0x17821000 0x1000>, <0x17822000 0x1000>; }; frame@17823000 { frame-number = <1>; - interrupts = ; + interrupts = ; reg = <0x17823000 0x1000>; status = "disabled"; }; frame@17824000 { frame-number = <2>; - interrupts = ; + interrupts = ; reg = <0x17824000 0x1000>; status = "disabled"; }; frame@17825000 { frame-number = <3>; - interrupts = ; + interrupts = ; reg = <0x17825000 0x1000>; status = "disabled"; }; frame@17826000 { frame-number = <4>; - interrupts = ; + interrupts = ; reg = <0x17826000 0x1000>; status = "disabled"; }; frame@17827000 { frame-number = <5>; - interrupts = ; + interrupts = ; reg = <0x17827000 0x1000>; status = "disabled"; }; frame@17828000 { frame-number = <6>; - interrupts = ; + interrupts = ; reg = <0x17828000 0x1000>; status = "disabled"; }; frame@17829000 { frame-number = <7>; - interrupts = ; + interrupts = ; reg = <0x17829000 0x1000>; status = "disabled"; }; @@ -804,10 +806,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 12 0xf08>, - <1 10 0xf08>, - <1 11 0xf08>; + interrupts = , + , + , + ; clock-frequency = <19200000>; }; }; diff --git a/src/arm/renesas/r8a73a4-ape6evm.dts b/src/arm/renesas/r8a73a4-ape6evm.dts index ed75c01dbee..3d02f065f71 100644 --- a/src/arm/renesas/r8a73a4-ape6evm.dts +++ b/src/arm/renesas/r8a73a4-ape6evm.dts @@ -209,6 +209,18 @@ status = "okay"; }; +&extal1_clk { + clock-frequency = <26000000>; +}; + +&extal2_clk { + clock-frequency = <48000000>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + &pfc { scifa0_pins: scifa0 { groups = "scifa0_data"; diff --git a/src/arm/renesas/r8a73a4.dtsi b/src/arm/renesas/r8a73a4.dtsi index c3906696705..ac654ff45d0 100644 --- a/src/arm/renesas/r8a73a4.dtsi +++ b/src/arm/renesas/r8a73a4.dtsi @@ -450,17 +450,20 @@ extalr_clk: extalr { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <32768>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; extal1_clk: extal1 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <25000000>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; extal2_clk: extal2 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <48000000>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; fsiack_clk: fsiack { compatible = "fixed-clock"; @@ -621,6 +624,13 @@ clock-div = <2>; clock-mult = <1>; }; + cp_clk: cp { + compatible = "fixed-factor-clock"; + clocks = <&main_div2_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; pll0_div2_clk: pll0_div2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A73A4_CLK_PLL0>; @@ -686,9 +696,8 @@ mstp4_clks: mstp4_clks@e6150140 { compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>, - <&main_div2_clk>, - <&cpg_clocks R8A73A4_CLK_HP>, + clocks = <&cp_clk>, <&cpg_clocks R8A73A4_CLK_ZS>, + <&cp_clk>, <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks R8A73A4_CLK_HP>; #clock-cells = <1>; clock-indices = < @@ -702,7 +711,7 @@ mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>; + clocks = <&cp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; #clock-cells = <1>; clock-indices = < R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8 diff --git a/src/arm/renesas/r8a7740.dtsi b/src/arm/renesas/r8a7740.dtsi index 55884ec701f..d13ab86c3ab 100644 --- a/src/arm/renesas/r8a7740.dtsi +++ b/src/arm/renesas/r8a7740.dtsi @@ -459,6 +459,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&mstp1_clks R8A7740_CLK_TMU0>; clock-names = "fck"; power-domains = <&pd_a4r>; @@ -474,6 +475,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&mstp1_clks R8A7740_CLK_TMU1>; clock-names = "fck"; power-domains = <&pd_a4r>; diff --git a/src/arm/renesas/r8a7778.dtsi b/src/arm/renesas/r8a7778.dtsi index 8d4530ed2fc..b80e832c927 100644 --- a/src/arm/renesas/r8a7778.dtsi +++ b/src/arm/renesas/r8a7778.dtsi @@ -199,7 +199,9 @@ reg = <0xffd80000 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&mstp0_clks R8A7778_CLK_TMU0>; clock-names = "fck"; power-domains = <&cpg_clocks>; @@ -214,7 +216,9 @@ reg = <0xffd81000 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&mstp0_clks R8A7778_CLK_TMU1>; clock-names = "fck"; power-domains = <&cpg_clocks>; @@ -230,6 +234,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&mstp0_clks R8A7778_CLK_TMU2>; clock-names = "fck"; power-domains = <&cpg_clocks>; @@ -250,6 +255,8 @@ reg = <0xffd90000 0x1000>, /* SRU */ <0xffd91000 0x240>, /* SSI */ <0xfffe0000 0x24>; /* ADG */ + reg-names = "sru", "ssi", "adg"; + clocks = <&mstp3_clks R8A7778_CLK_SSI8>, <&mstp3_clks R8A7778_CLK_SSI7>, <&mstp3_clks R8A7778_CLK_SSI6>, diff --git a/src/arm/renesas/r8a7779.dtsi b/src/arm/renesas/r8a7779.dtsi index 7743af5e2a6..1944703cba4 100644 --- a/src/arm/renesas/r8a7779.dtsi +++ b/src/arm/renesas/r8a7779.dtsi @@ -402,7 +402,9 @@ reg = <0xffd80000 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&mstp0_clks R8A7779_CLK_TMU0>; clock-names = "fck"; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; @@ -417,7 +419,9 @@ reg = <0xffd81000 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&mstp0_clks R8A7779_CLK_TMU1>; clock-names = "fck"; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; @@ -433,6 +437,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&mstp0_clks R8A7779_CLK_TMU2>; clock-names = "fck"; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; diff --git a/src/arm/rockchip/rk3128-xpi-3128.dts b/src/arm/rockchip/rk3128-xpi-3128.dts index 03a97881519..21c1678f4e9 100644 --- a/src/arm/rockchip/rk3128-xpi-3128.dts +++ b/src/arm/rockchip/rk3128-xpi-3128.dts @@ -47,6 +47,17 @@ regulator-boot-on; }; + hdmi-connnector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_connector_out>; + }; + }; + }; + /* * This is a vbus-supply, which also supplies the GL852G usb hub, * thus has to be always-on @@ -239,6 +250,10 @@ cpu-supply = <&vdd_arm>; }; +&display_subsystem { + status = "okay"; +}; + &emmc { bus-width = <8>; vmmc-supply = <&vcc_io>; @@ -328,6 +343,16 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_connector_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + &mdio { phy0: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; @@ -423,3 +448,7 @@ &usb2phy_otg { status = "okay"; }; + +&vop { + status = "okay"; +}; diff --git a/src/arm/rockchip/rk3128.dtsi b/src/arm/rockchip/rk3128.dtsi index e2264c40b92..fb98873fd94 100644 --- a/src/arm/rockchip/rk3128.dtsi +++ b/src/arm/rockchip/rk3128.dtsi @@ -115,6 +115,12 @@ }; }; + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + status = "disabled"; + }; + gpu_opp_table: opp-table-1 { compatible = "operating-points-v2"; @@ -246,6 +252,32 @@ }; }; + vop: vop@1010e000 { + compatible = "rockchip,rk3126-vop"; + reg = <0x1010e000 0x300>; + interrupts = ; + clocks = <&cru ACLK_LCDC0>, <&cru DCLK_VOP>, + <&cru HCLK_LCDC0>; + clock-names = "aclk_vop", "dclk_vop", + "hclk_vop"; + resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, + <&cru SRST_VOP_D>; + reset-names = "axi", "ahb", + "dclk"; + power-domains = <&power RK3128_PD_VIO>; + status = "disabled"; + + vop_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vop>; + }; + }; + }; + qos_gpu: qos@1012d000 { compatible = "rockchip,rk3128-qos", "syscon"; reg = <0x1012d000 0x20>; @@ -436,6 +468,34 @@ }; }; + hdmi: hdmi@20034000 { + compatible = "rockchip,rk3128-inno-hdmi"; + reg = <0x20034000 0x4000>; + interrupts = ; + clocks = <&cru PCLK_HDMI>, <&cru DCLK_VOP>; + clock-names = "pclk", "ref"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; + power-domains = <&power RK3128_PD_VIO>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + hdmi_in_vop: endpoint { + remote-endpoint = <&vop_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + timer0: timer@20044000 { compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; reg = <0x20044000 0x20>; diff --git a/src/arm/rockchip/rk322x.dtsi b/src/arm/rockchip/rk322x.dtsi index 831561fc181..96421355c27 100644 --- a/src/arm/rockchip/rk322x.dtsi +++ b/src/arm/rockchip/rk322x.dtsi @@ -736,14 +736,20 @@ status = "disabled"; ports { - hdmi_in: port { - #address-cells = <1>; - #size-cells = <0>; - hdmi_in_vop: endpoint@0 { - reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + + hdmi_in_vop: endpoint { remote-endpoint = <&vop_out_hdmi>; }; }; + + hdmi_out: port@1 { + reg = <1>; + }; }; }; diff --git a/src/arm/rockchip/rk3288.dtsi b/src/arm/rockchip/rk3288.dtsi index ead343dc3df..3f1d640afaf 100644 --- a/src/arm/rockchip/rk3288.dtsi +++ b/src/arm/rockchip/rk3288.dtsi @@ -1240,27 +1240,37 @@ compatible = "rockchip,rk3288-dw-hdmi"; reg = <0x0 0xff980000 0x0 0x20000>; reg-io-width = <4>; - #sound-dai-cells = <0>; - rockchip,grf = <&grf>; interrupts = ; clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; clock-names = "iahb", "isfr", "cec"; power-domains = <&power RK3288_PD_VIO>; + rockchip,grf = <&grf>; + #sound-dai-cells = <0>; status = "disabled"; ports { - hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; #address-cells = <1>; #size-cells = <0>; + hdmi_in_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb_out_hdmi>; }; + hdmi_in_vopl: endpoint@1 { reg = <1>; remote-endpoint = <&vopl_out_hdmi>; }; }; + + hdmi_out: port@1 { + reg = <1>; + }; }; }; diff --git a/src/arm/rockchip/rv1126-sonoff-ihost.dtsi b/src/arm/rockchip/rv1126-sonoff-ihost.dtsi index 32b329e87a0..9a87dc0d5f6 100644 --- a/src/arm/rockchip/rv1126-sonoff-ihost.dtsi +++ b/src/arm/rockchip/rv1126-sonoff-ihost.dtsi @@ -8,6 +8,8 @@ aliases { ethernet0 = &gmac; mmc0 = &emmc; + mmc1 = &sdio; + mmc2 = &sdmmc; }; chosen { @@ -325,7 +327,7 @@ pmuio1-supply = <&vcc3v3_sys>; vccio1-supply = <&vcc_1v8>; vccio2-supply = <&vccio_sd>; - vccio3-supply = <&vcc_1v8>; + vccio3-supply = <&vcc3v3_sd>; vccio4-supply = <&vcc_dovdd>; vccio5-supply = <&vcc_1v8>; vccio6-supply = <&vcc_1v8>; @@ -343,14 +345,14 @@ cap-sd-highspeed; cap-sdio-irq; keep-power-in-suspend; - max-frequency = <100000000>; + max-frequency = <50000000>; mmc-pwrseq = <&sdio_pwrseq>; non-removable; pinctrl-names = "default"; pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>; rockchip,default-sample-phase = <90>; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_sys>; + sd-uhs-sdr50; + vmmc-supply = <&vcc3v3_sd>; vqmmc-supply = <&vcc_1v8>; status = "okay"; }; diff --git a/src/arm/samsung/exynos4412-i9300.dts b/src/arm/samsung/exynos4412-i9300.dts index 61aca5798f3..b79d456e976 100644 --- a/src/arm/samsung/exynos4412-i9300.dts +++ b/src/arm/samsung/exynos4412-i9300.dts @@ -18,7 +18,7 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x40000000>; + reg = <0x40000000 0x3fc00000>; }; }; diff --git a/src/arm/samsung/exynos4412-i9305.dts b/src/arm/samsung/exynos4412-i9305.dts index 77083f1a827..1048ef5d9bc 100644 --- a/src/arm/samsung/exynos4412-i9305.dts +++ b/src/arm/samsung/exynos4412-i9305.dts @@ -11,7 +11,7 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x80000000>; + reg = <0x40000000 0x7fc00000>; }; }; diff --git a/src/arm/samsung/exynos4412-n710x.dts b/src/arm/samsung/exynos4412-n710x.dts index 0a151437fc7..eee1000dea9 100644 --- a/src/arm/samsung/exynos4412-n710x.dts +++ b/src/arm/samsung/exynos4412-n710x.dts @@ -9,7 +9,7 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x80000000>; + reg = <0x40000000 0x7fc00000>; }; /* bootargs are passed in by bootloader */ diff --git a/src/arm/samsung/exynos4412-p4note.dtsi b/src/arm/samsung/exynos4412-p4note.dtsi index 0b89d5682f8..28a60580273 100644 --- a/src/arm/samsung/exynos4412-p4note.dtsi +++ b/src/arm/samsung/exynos4412-p4note.dtsi @@ -23,7 +23,7 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x80000000>; + reg = <0x40000000 0x7fc00000>; }; aliases { @@ -362,6 +362,39 @@ status = "okay"; }; +&i2c_1 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + pinctrl-0 = <&i2c1_bus>; + pinctrl-names = "default"; + status = "okay"; + + accelerometer@19 { + compatible = "st,lsm330dlc-accel"; + reg = <0x19>; + interrupt-parent = <&gpx0>; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; + pinctrl-0 = <&accelerometer_irq>; + pinctrl-names = "default"; + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; + }; + + gyro@6b { + compatible = "st,lsm330dlc-gyro"; + reg = <0x6b>; + interrupt-parent = <&gpx0>; + interrupts = <6 IRQ_TYPE_EDGE_RISING>; + pinctrl-0 = <&gyro_data_enable &gyro_irq>; + pinctrl-names = "default"; + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; + }; +}; + &i2c_3 { samsung,i2c-sda-delay = <100>; samsung,i2c-slave-addr = <0x10>; @@ -844,6 +877,12 @@ samsung,pin-pud = ; }; + gyro_data_enable: gyro-data-enable-pins { + samsung,pins = "gpl2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + uart_sel: uart-sel-pins { samsung,pins = "gpl2-7"; samsung,pin-function = ; @@ -894,12 +933,24 @@ samsung,pin-pud = ; }; + accelerometer_irq: accelerometer-irq-pins { + samsung,pins = "gpx0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + stmpe_adc_irq: stmpe-adc-irq-pins { samsung,pins = "gpx0-1"; samsung,pin-function = ; samsung,pin-pud = ; }; + gyro_irq: gyro-irq-pins { + samsung,pins = "gpx0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + max77686_irq: max77686-irq-pins { samsung,pins = "gpx0-7"; samsung,pin-pud = ; diff --git a/src/arm/samsung/exynos5420-galaxy-tab-common.dtsi b/src/arm/samsung/exynos5420-galaxy-tab-common.dtsi index f525b2f5e4e..24604096708 100644 --- a/src/arm/samsung/exynos5420-galaxy-tab-common.dtsi +++ b/src/arm/samsung/exynos5420-galaxy-tab-common.dtsi @@ -30,6 +30,7 @@ aliases { mmc0 = &mmc_0; + mmc1 = &mmc_1; mmc2 = &mmc_2; }; @@ -39,7 +40,7 @@ memory@20000000 { device_type = "memory"; - reg = <0x20000000 0xc0000000>; + reg = <0x20000000 0xbfa00000>; }; firmware@2073000 { @@ -87,6 +88,13 @@ linux,code = ; }; }; + + mmc1_pwrseq: pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpy7 7 GPIO_ACTIVE_LOW>; + clocks = <&s2mps11_osc S2MPS11_CLK_BT>; + clock-names = "ext_clock"; + }; }; &cci { @@ -620,6 +628,25 @@ vqmmc-supply = <&ldo3_reg>; }; +/* WiFi */ +&mmc_1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + card-detect-delay = <200>; + keep-power-in-suspend; + mmc-pwrseq = <&mmc1_pwrseq>; + non-removable; + pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_int>, <&sd1_bus1>, + <&sd1_bus4>, <&wifi_en>; + pinctrl-names = "default"; + vqmmc-supply = <&ldo2_reg>; + samsung,dw-mshc-ciu-div = <1>; + samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-sdr-timing = <0 1>; + status = "okay"; +}; + /* External sdcard */ &mmc_2 { status = "okay"; @@ -649,6 +676,11 @@ samsung,pin-pud = ; samsung,pin-drv = ; }; + + wifi_en: wifi-en-pins { + samsung,pins = "gpy7-7"; + samsung,pin-pud = ; + }; }; &rtc { diff --git a/src/arm/samsung/exynos5420-peach-pit.dts b/src/arm/samsung/exynos5420-peach-pit.dts index 4e757b6e28e..3759742d38c 100644 --- a/src/arm/samsung/exynos5420-peach-pit.dts +++ b/src/arm/samsung/exynos5420-peach-pit.dts @@ -967,6 +967,7 @@ reg = <0>; spi-max-frequency = <3125000>; google,has-vbc-nvram; + wakeup-source; controller-data { samsung,spi-feedback-delay = <1>; diff --git a/src/arm/samsung/exynos5422-odroidxu3-common.dtsi b/src/arm/samsung/exynos5422-odroidxu3-common.dtsi index b4a851aa888..4a4c55a4beb 100644 --- a/src/arm/samsung/exynos5422-odroidxu3-common.dtsi +++ b/src/arm/samsung/exynos5422-odroidxu3-common.dtsi @@ -55,7 +55,7 @@ thermal-zones { cpu0_thermal: cpu0-thermal { thermal-sensors = <&tmu_cpu0>; - polling-delay-passive = <250>; + polling-delay-passive = <0>; polling-delay = <0>; trips { cpu0_alert0: cpu-alert-0 { @@ -78,12 +78,6 @@ hysteresis = <0>; /* millicelsius */ type = "critical"; }; - /* - * Exynos542x supports only 4 trip-points - * so for these polling mode is required. - * Start polling at temperature level of last - * interrupt-driven trip: cpu0_alert2 - */ cpu0_alert3: cpu-alert-3 { temperature = <70000>; /* millicelsius */ hysteresis = <10000>; /* millicelsius */ @@ -144,7 +138,7 @@ }; cpu1_thermal: cpu1-thermal { thermal-sensors = <&tmu_cpu1>; - polling-delay-passive = <250>; + polling-delay-passive = <0>; polling-delay = <0>; trips { cpu1_alert0: cpu-alert-0 { @@ -217,7 +211,7 @@ }; cpu2_thermal: cpu2-thermal { thermal-sensors = <&tmu_cpu2>; - polling-delay-passive = <250>; + polling-delay-passive = <0>; polling-delay = <0>; trips { cpu2_alert0: cpu-alert-0 { @@ -290,7 +284,7 @@ }; cpu3_thermal: cpu3-thermal { thermal-sensors = <&tmu_cpu3>; - polling-delay-passive = <250>; + polling-delay-passive = <0>; polling-delay = <0>; trips { cpu3_alert0: cpu-alert-0 { @@ -363,7 +357,7 @@ }; gpu_thermal: gpu-thermal { thermal-sensors = <&tmu_gpu>; - polling-delay-passive = <250>; + polling-delay-passive = <0>; polling-delay = <0>; trips { gpu_alert0: gpu-alert-0 { diff --git a/src/arm/samsung/exynos5800-peach-pi.dts b/src/arm/samsung/exynos5800-peach-pi.dts index f91bc4ae008..9bbbdce9103 100644 --- a/src/arm/samsung/exynos5800-peach-pi.dts +++ b/src/arm/samsung/exynos5800-peach-pi.dts @@ -949,6 +949,7 @@ reg = <0>; spi-max-frequency = <3125000>; google,has-vbc-nvram; + wakeup-source; controller-data { samsung,spi-feedback-delay = <1>; diff --git a/src/arm/st/stih407-pinctrl.dtsi b/src/arm/st/stih407-pinctrl.dtsi index 7815669fe81..dcb821f567f 100644 --- a/src/arm/st/stih407-pinctrl.dtsi +++ b/src/arm/st/stih407-pinctrl.dtsi @@ -462,14 +462,14 @@ serial0 { pinctrl_serial0: serial0-0 { st,pins { - tx = <&pio17 0 ALT1 OUT>; - rx = <&pio17 1 ALT1 IN>; + tx = <&pio17 0 ALT1 OUT>; + rx = <&pio17 1 ALT1 IN>; }; }; pinctrl_serial0_hw_flowctrl: serial0-0_hw_flowctrl { st,pins { - tx = <&pio17 0 ALT1 OUT>; - rx = <&pio17 1 ALT1 IN>; + tx = <&pio17 0 ALT1 OUT>; + rx = <&pio17 1 ALT1 IN>; cts = <&pio17 2 ALT1 IN>; rts = <&pio17 3 ALT1 OUT>; }; diff --git a/src/arm/st/stm32f769-disco-mb1166-reva09.dts b/src/arm/st/stm32f769-disco-mb1166-reva09.dts new file mode 100644 index 00000000000..ff7ff32371d --- /dev/null +++ b/src/arm/st/stm32f769-disco-mb1166-reva09.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Dario Binacchi + */ + +#include "stm32f769-disco.dts" + +&panel0 { + compatible = "frida,frd400b25025", "novatek,nt35510"; + vddi-supply = <&vcc_3v3>; + vdd-supply = <&vcc_3v3>; + /delete-property/power-supply; +}; diff --git a/src/arm/st/stm32f769-disco.dts b/src/arm/st/stm32f769-disco.dts index 5d12ae25b32..52c5baf58ab 100644 --- a/src/arm/st/stm32f769-disco.dts +++ b/src/arm/st/stm32f769-disco.dts @@ -41,7 +41,7 @@ */ /dts-v1/; -#include "stm32f746.dtsi" +#include "stm32f769.dtsi" #include "stm32f769-pinctrl.dtsi" #include #include @@ -60,6 +60,19 @@ reg = <0xC0000000 0x1000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,dma { + compatible = "shared-dma-pool"; + linux,dma-default; + no-map; + size = <0x100000>; + }; + }; + aliases { serial0 = &usart1; }; @@ -92,9 +105,9 @@ clock-names = "main_clk"; }; - mmc_vcard: mmc_vcard { + vcc_3v3: vcc-3v3 { compatible = "regulator-fixed"; - regulator-name = "mmc_vcard"; + regulator-name = "vcc_3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; @@ -114,6 +127,45 @@ clock-frequency = <25000000>; }; +&dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&dsi_panel_in>; + }; + }; + }; + + panel0: panel@0 { + compatible = "orisetech,otm8009a"; + reg = <0>; /* dsi virtual channel (0..3) */ + reset-gpios = <&gpioj 15 GPIO_ACTIVE_LOW>; + power-supply = <&vcc_3v3>; + status = "okay"; + + port { + dsi_panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + &i2c1 { pinctrl-0 = <&i2c1_pins_b>; pinctrl-names = "default"; @@ -122,13 +174,23 @@ status = "okay"; }; +<dc { + status = "okay"; + + port { + ltdc_out_dsi: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; +}; + &rtc { status = "okay"; }; &sdio2 { status = "okay"; - vmmc-supply = <&mmc_vcard>; + vmmc-supply = <&vcc_3v3>; cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>; broken-cd; pinctrl-names = "default", "opendrain", "sleep"; diff --git a/src/arm/st/stm32f769.dtsi b/src/arm/st/stm32f769.dtsi new file mode 100644 index 00000000000..4e7d9032149 --- /dev/null +++ b/src/arm/st/stm32f769.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Dario Binacchi + */ + +#include "stm32f746.dtsi" + +/ { + soc { + dsi: dsi@40016c00 { + compatible = "st,stm32-dsi"; + reg = <0x40016c00 0x800>; + clocks = <&rcc 1 CLK_F769_DSI>, <&clk_hse>; + clock-names = "pclk", "ref"; + resets = <&rcc STM32F7_APB2_RESET(DSI)>; + reset-names = "apb"; + status = "disabled"; + }; + }; +}; diff --git a/src/arm/st/stm32mp131.dtsi b/src/arm/st/stm32mp131.dtsi index b04d24c939c..3900f32da79 100644 --- a/src/arm/st/stm32mp131.dtsi +++ b/src/arm/st/stm32mp131.dtsi @@ -1315,6 +1315,13 @@ status = "disabled"; }; + crc1: crc@58009000 { + compatible = "st,stm32f7-crc"; + reg = <0x58009000 0x400>; + clocks = <&rcc CRC1>; + status = "disabled"; + }; + usbh_ohci: usb@5800c000 { compatible = "generic-ohci"; reg = <0x5800c000 0x1000>; diff --git a/src/arm/st/stm32mp135f-dk.dts b/src/arm/st/stm32mp135f-dk.dts index eea740d097c..52171214a30 100644 --- a/src/arm/st/stm32mp135f-dk.dts +++ b/src/arm/st/stm32mp135f-dk.dts @@ -93,6 +93,14 @@ }; }; +&crc1 { + status = "okay"; +}; + +&cryp { + status = "okay"; +}; + &i2c1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_pins_a>; diff --git a/src/arm/st/stm32mp157.dtsi b/src/arm/st/stm32mp157.dtsi index 6197d878894..97cd24227ce 100644 --- a/src/arm/st/stm32mp157.dtsi +++ b/src/arm/st/stm32mp157.dtsi @@ -20,7 +20,7 @@ dsi: dsi@5a000000 { compatible = "st,stm32-dsi"; reg = <0x5a000000 0x800>; - clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; + clocks = <&rcc DSI>, <&clk_hse>, <&rcc DSI_PX>; clock-names = "pclk", "ref", "px_clk"; phy-dsi-supply = <®18>; resets = <&rcc DSI_R>; diff --git a/src/arm/st/stm32mp157a-dk1-scmi.dts b/src/arm/st/stm32mp157a-dk1-scmi.dts index ce5937270aa..306e1bc2a51 100644 --- a/src/arm/st/stm32mp157a-dk1-scmi.dts +++ b/src/arm/st/stm32mp157a-dk1-scmi.dts @@ -30,7 +30,7 @@ }; &dsi { - clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; + clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; }; &gpioz { diff --git a/src/arm/st/stm32mp157c-dk2-scmi.dts b/src/arm/st/stm32mp157c-dk2-scmi.dts index c20a73841c1..956da5f26c1 100644 --- a/src/arm/st/stm32mp157c-dk2-scmi.dts +++ b/src/arm/st/stm32mp157c-dk2-scmi.dts @@ -36,7 +36,7 @@ &dsi { phy-dsi-supply = <&scmi_reg18>; - clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; + clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; }; &gpioz { diff --git a/src/arm/st/stm32mp157c-ed1-scmi.dts b/src/arm/st/stm32mp157c-ed1-scmi.dts index 5e2eaf57ce2..8e4b0db198c 100644 --- a/src/arm/st/stm32mp157c-ed1-scmi.dts +++ b/src/arm/st/stm32mp157c-ed1-scmi.dts @@ -35,7 +35,7 @@ }; &dsi { - clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; + clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; }; &gpioz { diff --git a/src/arm/st/stm32mp157c-ev1-scmi.dts b/src/arm/st/stm32mp157c-ev1-scmi.dts index 3226fb945a8..72b9cab2d99 100644 --- a/src/arm/st/stm32mp157c-ev1-scmi.dts +++ b/src/arm/st/stm32mp157c-ev1-scmi.dts @@ -36,7 +36,7 @@ &dsi { phy-dsi-supply = <&scmi_reg18>; - clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; + clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; }; &gpioz { diff --git a/src/arm/st/stm32mp157c-lxa-tac-gen2.dts b/src/arm/st/stm32mp157c-lxa-tac-gen2.dts index 8a34d15e900..4cc17703166 100644 --- a/src/arm/st/stm32mp157c-lxa-tac-gen2.dts +++ b/src/arm/st/stm32mp157c-lxa-tac-gen2.dts @@ -148,7 +148,7 @@ compatible = "ti,lmp92064"; reg = <0>; - reset-gpios = <&gpioa 4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpioa 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; shunt-resistor-micro-ohms = <15000>; spi-max-frequency = <5000000>; vdd-supply = <®_pb_3v3>; diff --git a/src/arm/st/stm32mp15xc-lxa-tac.dtsi b/src/arm/st/stm32mp15xc-lxa-tac.dtsi index fc3a2386dbb..cfaf8adde31 100644 --- a/src/arm/st/stm32mp15xc-lxa-tac.dtsi +++ b/src/arm/st/stm32mp15xc-lxa-tac.dtsi @@ -409,7 +409,7 @@ baseboard_eeprom: &sip_eeprom { &spi2 { pinctrl-names = "default"; pinctrl-0 = <&spi2_pins_c>; - cs-gpios = <&gpiof 12 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpiof 12 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -471,6 +471,10 @@ baseboard_eeprom: &sip_eeprom { interrupt-parent = <&gpioa>; interrupts = <6 IRQ_TYPE_EDGE_RISING>; + /* Reduce RGMII EMI emissions by reducing drive strength */ + microchip,hi-drive-strength-microamp = <2000>; + microchip,lo-drive-strength-microamp = <8000>; + ports { #address-cells = <1>; #size-cells = <0>; diff --git a/src/arm/ti/davinci/da850.dtsi b/src/arm/ti/davinci/da850.dtsi index f759fdfe1b1..1d3fb5397ce 100644 --- a/src/arm/ti/davinci/da850.dtsi +++ b/src/arm/ti/davinci/da850.dtsi @@ -536,7 +536,7 @@ reg = <0x40000 0x1000>; cap-sd-highspeed; cap-mmc-highspeed; - interrupts = <16>; + interrupts = <16>, <17>; dmas = <&edma0 16 0>, <&edma0 17 0>; dma-names = "rx", "tx"; clocks = <&psc0 5>; @@ -566,7 +566,7 @@ reg = <0x21b000 0x1000>; cap-sd-highspeed; cap-mmc-highspeed; - interrupts = <72>; + interrupts = <72>, <73>; dmas = <&edma1 28 0>, <&edma1 29 0>; dma-names = "rx", "tx"; clocks = <&psc1 18>; diff --git a/src/arm/ti/keystone/keystone-clocks.dtsi b/src/arm/ti/keystone/keystone-clocks.dtsi index 0397c3423d2..20bab90ee0b 100644 --- a/src/arm/ti/keystone/keystone-clocks.dtsi +++ b/src/arm/ti/keystone/keystone-clocks.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for Keystone 2 clock tree * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ */ clocks { diff --git a/src/arm/ti/keystone/keystone-k2e-clocks.dtsi b/src/arm/ti/keystone/keystone-k2e-clocks.dtsi index cf30e007fea..74720dbf311 100644 --- a/src/arm/ti/keystone/keystone-k2e-clocks.dtsi +++ b/src/arm/ti/keystone/keystone-k2e-clocks.dtsi @@ -2,7 +2,7 @@ /* * Keystone 2 Edison SoC specific device tree * - * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/ */ clocks { diff --git a/src/arm/ti/keystone/keystone-k2e-evm.dts b/src/arm/ti/keystone/keystone-k2e-evm.dts index 6978d6a362f..58099ce8d44 100644 --- a/src/arm/ti/keystone/keystone-k2e-evm.dts +++ b/src/arm/ti/keystone/keystone-k2e-evm.dts @@ -2,7 +2,7 @@ /* * Keystone 2 Edison EVM device tree * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm/ti/keystone/keystone-k2e-netcp.dtsi b/src/arm/ti/keystone/keystone-k2e-netcp.dtsi index 5c88a90903b..e586350ae4d 100644 --- a/src/arm/ti/keystone/keystone-k2e-netcp.dtsi +++ b/src/arm/ti/keystone/keystone-k2e-netcp.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for Keystone 2 Edison Netcp driver * - * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/ */ qmss: qmss@2a40000 { diff --git a/src/arm/ti/keystone/keystone-k2e.dtsi b/src/arm/ti/keystone/keystone-k2e.dtsi index 65c32946c52..662aa33cba1 100644 --- a/src/arm/ti/keystone/keystone-k2e.dtsi +++ b/src/arm/ti/keystone/keystone-k2e.dtsi @@ -2,7 +2,7 @@ /* * Keystone 2 Edison soc device tree * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ */ #include diff --git a/src/arm/ti/keystone/keystone-k2g-evm.dts b/src/arm/ti/keystone/keystone-k2g-evm.dts index f0ddbbcdc97..bf5f67d7023 100644 --- a/src/arm/ti/keystone/keystone-k2g-evm.dts +++ b/src/arm/ti/keystone/keystone-k2g-evm.dts @@ -2,7 +2,7 @@ /* * Device Tree Source for K2G EVM * - * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm/ti/keystone/keystone-k2g-ice.dts b/src/arm/ti/keystone/keystone-k2g-ice.dts index 6ceb0d5c638..264e1e0d23c 100644 --- a/src/arm/ti/keystone/keystone-k2g-ice.dts +++ b/src/arm/ti/keystone/keystone-k2g-ice.dts @@ -2,7 +2,7 @@ /* * Device Tree Source for K2G Industrial Communication Engine EVM * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm/ti/keystone/keystone-k2g-netcp.dtsi b/src/arm/ti/keystone/keystone-k2g-netcp.dtsi index 7109ca03161..974c8f2fa74 100644 --- a/src/arm/ti/keystone/keystone-k2g-netcp.dtsi +++ b/src/arm/ti/keystone/keystone-k2g-netcp.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for K2G Netcp driver * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ */ qmss: qmss@4020000 { diff --git a/src/arm/ti/keystone/keystone-k2g.dtsi b/src/arm/ti/keystone/keystone-k2g.dtsi index 102d59694d9..790b29ab0fa 100644 --- a/src/arm/ti/keystone/keystone-k2g.dtsi +++ b/src/arm/ti/keystone/keystone-k2g.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for K2G SOC * - * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/ */ #include diff --git a/src/arm/ti/keystone/keystone-k2hk-clocks.dtsi b/src/arm/ti/keystone/keystone-k2hk-clocks.dtsi index 4ba6912176e..3ca4722087c 100644 --- a/src/arm/ti/keystone/keystone-k2hk-clocks.dtsi +++ b/src/arm/ti/keystone/keystone-k2hk-clocks.dtsi @@ -2,7 +2,7 @@ /* * Keystone 2 Kepler/Hawking SoC clock nodes * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ */ clocks { diff --git a/src/arm/ti/keystone/keystone-k2hk-evm.dts b/src/arm/ti/keystone/keystone-k2hk-evm.dts index 8dfb5429502..b824fad9a4e 100644 --- a/src/arm/ti/keystone/keystone-k2hk-evm.dts +++ b/src/arm/ti/keystone/keystone-k2hk-evm.dts @@ -2,7 +2,7 @@ /* * Keystone 2 Kepler/Hawking EVM device tree * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm/ti/keystone/keystone-k2hk-netcp.dtsi b/src/arm/ti/keystone/keystone-k2hk-netcp.dtsi index c2ee775eab6..3ab1b5d6f9b 100644 --- a/src/arm/ti/keystone/keystone-k2hk-netcp.dtsi +++ b/src/arm/ti/keystone/keystone-k2hk-netcp.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for Keystone 2 Hawking Netcp driver * - * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/ */ qmss: qmss@2a40000 { diff --git a/src/arm/ti/keystone/keystone-k2hk.dtsi b/src/arm/ti/keystone/keystone-k2hk.dtsi index da6d3934c2e..4fdf4b30384 100644 --- a/src/arm/ti/keystone/keystone-k2hk.dtsi +++ b/src/arm/ti/keystone/keystone-k2hk.dtsi @@ -2,7 +2,7 @@ /* * Keystone 2 Kepler/Hawking soc specific device tree * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ */ #include diff --git a/src/arm/ti/keystone/keystone-k2l-clocks.dtsi b/src/arm/ti/keystone/keystone-k2l-clocks.dtsi index 635528064de..fcfc2fb6cc2 100644 --- a/src/arm/ti/keystone/keystone-k2l-clocks.dtsi +++ b/src/arm/ti/keystone/keystone-k2l-clocks.dtsi @@ -2,7 +2,7 @@ /* * Keystone 2 lamarr SoC clock nodes * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ */ clocks { diff --git a/src/arm/ti/keystone/keystone-k2l-evm.dts b/src/arm/ti/keystone/keystone-k2l-evm.dts index be619e39a16..ccda63ab12f 100644 --- a/src/arm/ti/keystone/keystone-k2l-evm.dts +++ b/src/arm/ti/keystone/keystone-k2l-evm.dts @@ -2,7 +2,7 @@ /* * Keystone 2 Lamarr EVM device tree * - * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm/ti/keystone/keystone-k2l-netcp.dtsi b/src/arm/ti/keystone/keystone-k2l-netcp.dtsi index 1afebd7458c..b8f880faaa3 100644 --- a/src/arm/ti/keystone/keystone-k2l-netcp.dtsi +++ b/src/arm/ti/keystone/keystone-k2l-netcp.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for Keystone 2 Lamarr Netcp driver * - * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/ */ qmss: qmss@2a40000 { diff --git a/src/arm/ti/keystone/keystone-k2l.dtsi b/src/arm/ti/keystone/keystone-k2l.dtsi index 2062fe56164..330b437b667 100644 --- a/src/arm/ti/keystone/keystone-k2l.dtsi +++ b/src/arm/ti/keystone/keystone-k2l.dtsi @@ -2,7 +2,7 @@ /* * Keystone 2 Lamarr SoC specific device tree * - * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/ */ #include diff --git a/src/arm/ti/keystone/keystone.dtsi b/src/arm/ti/keystone/keystone.dtsi index 1fd04bb37a1..ff16428860a 100644 --- a/src/arm/ti/keystone/keystone.dtsi +++ b/src/arm/ti/keystone/keystone.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ */ #include diff --git a/src/arm/ti/omap/am335x-baltos-ir2110.dts b/src/arm/ti/omap/am335x-baltos-ir2110.dts index ea5882ed701..f82d2231dfa 100644 --- a/src/arm/ti/omap/am335x-baltos-ir2110.dts +++ b/src/arm/ti/omap/am335x-baltos-ir2110.dts @@ -5,7 +5,7 @@ /* * VScom OnRISC - * http://www.vscom.de + * https://www.vscom.de */ /dts-v1/; diff --git a/src/arm/ti/omap/am335x-baltos-ir3220.dts b/src/arm/ti/omap/am335x-baltos-ir3220.dts index ea4f8dde642..74a2191af14 100644 --- a/src/arm/ti/omap/am335x-baltos-ir3220.dts +++ b/src/arm/ti/omap/am335x-baltos-ir3220.dts @@ -5,7 +5,7 @@ /* * VScom OnRISC - * http://www.vscom.de + * https://www.vscom.de */ /dts-v1/; diff --git a/src/arm/ti/omap/am335x-baltos-ir5221.dts b/src/arm/ti/omap/am335x-baltos-ir5221.dts index ec914f27d11..723ff88f76a 100644 --- a/src/arm/ti/omap/am335x-baltos-ir5221.dts +++ b/src/arm/ti/omap/am335x-baltos-ir5221.dts @@ -5,7 +5,7 @@ /* * VScom OnRISC - * http://www.vscom.de + * https://www.vscom.de */ /dts-v1/; diff --git a/src/arm/ti/omap/am335x-baltos-leds.dtsi b/src/arm/ti/omap/am335x-baltos-leds.dtsi index 6a52e42b9e8..049fd8e1b40 100644 --- a/src/arm/ti/omap/am335x-baltos-leds.dtsi +++ b/src/arm/ti/omap/am335x-baltos-leds.dtsi @@ -5,7 +5,7 @@ /* * VScom OnRISC - * http://www.vscom.de + * https://www.vscom.de */ /*#include "am33xx.dtsi"*/ diff --git a/src/arm/ti/omap/am335x-baltos.dtsi b/src/arm/ti/omap/am335x-baltos.dtsi index c14d5b70c72..a4beb718559 100644 --- a/src/arm/ti/omap/am335x-baltos.dtsi +++ b/src/arm/ti/omap/am335x-baltos.dtsi @@ -5,7 +5,7 @@ /* * VScom OnRISC - * http://www.vscom.de + * https://www.vscom.de */ #include "am33xx.dtsi" diff --git a/src/arm/ti/omap/am335x-base0033.dts b/src/arm/ti/omap/am335x-base0033.dts index eba843e22ea..46078af4b7a 100644 --- a/src/arm/ti/omap/am335x-base0033.dts +++ b/src/arm/ti/omap/am335x-base0033.dts @@ -2,7 +2,7 @@ /* * am335x-base0033.dts - Device Tree file for IGEP AQUILA EXPANSION * - * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz + * Copyright (C) 2013 ISEE 2007 SL - https://www.isee.biz */ #include "am335x-igep0033.dtsi" diff --git a/src/arm/ti/omap/am335x-bone-common.dtsi b/src/arm/ti/omap/am335x-bone-common.dtsi index 96451c8a815..2d0216840ff 100644 --- a/src/arm/ti/omap/am335x-bone-common.dtsi +++ b/src/arm/ti/omap/am335x-bone-common.dtsi @@ -289,8 +289,8 @@ * For details, see linux-omap mailing list May 2015 thread * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller * In particular, messages: - * http://www.spinics.net/lists/linux-omap/msg118585.html - * http://www.spinics.net/lists/linux-omap/msg118615.html + * https://www.spinics.net/lists/linux-omap/msg118585.html + * https://www.spinics.net/lists/linux-omap/msg118615.html * * You can override this later with * &tps { /delete-property/ ti,pmic-shutdown-controller; } diff --git a/src/arm/ti/omap/am335x-cm-t335.dts b/src/arm/ti/omap/am335x-cm-t335.dts index 72990e7ffe1..06767ea164b 100644 --- a/src/arm/ti/omap/am335x-cm-t335.dts +++ b/src/arm/ti/omap/am335x-cm-t335.dts @@ -2,7 +2,7 @@ /* * am335x-cm-t335.dts - Device Tree file for Compulab CM-T335 * - * Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/ + * Copyright (C) 2014 - 2015 CompuLab Ltd. - https://www.compulab.co.il/ */ /dts-v1/; diff --git a/src/arm/ti/omap/am335x-evmsk.dts b/src/arm/ti/omap/am335x-evmsk.dts index 57f78846c42..eba888dcd60 100644 --- a/src/arm/ti/omap/am335x-evmsk.dts +++ b/src/arm/ti/omap/am335x-evmsk.dts @@ -5,7 +5,7 @@ /* * AM335x Starter Kit - * http://www.ti.com/tool/tmdssk3358 + * https://www.ti.com/tool/tmdssk3358 */ /dts-v1/; diff --git a/src/arm/ti/omap/am335x-guardian.dts b/src/arm/ti/omap/am335x-guardian.dts index 205fe0ed735..56e5d954a49 100644 --- a/src/arm/ti/omap/am335x-guardian.dts +++ b/src/arm/ti/omap/am335x-guardian.dts @@ -303,8 +303,8 @@ * For details, see linux-omap mailing list May 2015 thread * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller * In particular, messages: - * http://www.spinics.net/lists/linux-omap/msg118585.html - * http://www.spinics.net/lists/linux-omap/msg118615.html + * https://www.spinics.net/lists/linux-omap/msg118585.html + * https://www.spinics.net/lists/linux-omap/msg118615.html * * You can override this later with * &tps { /delete-property/ ti,pmic-shutdown-controller; } diff --git a/src/arm/ti/omap/am335x-icev2.dts b/src/arm/ti/omap/am335x-icev2.dts index 3c4228927f5..6f0f4fba043 100644 --- a/src/arm/ti/omap/am335x-icev2.dts +++ b/src/arm/ti/omap/am335x-icev2.dts @@ -5,7 +5,7 @@ /* * AM335x ICE V2 board - * http://www.ti.com/tool/tmdsice3359 + * https://www.ti.com/tool/tmdsice3359 */ /dts-v1/; diff --git a/src/arm/ti/omap/am335x-igep0033.dtsi b/src/arm/ti/omap/am335x-igep0033.dtsi index e85c33fd42f..c7a4a547648 100644 --- a/src/arm/ti/omap/am335x-igep0033.dtsi +++ b/src/arm/ti/omap/am335x-igep0033.dtsi @@ -2,7 +2,7 @@ /* * am335x-igep0033.dtsi - Device Tree file for IGEP COM AQUILA AM335x * - * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz + * Copyright (C) 2013 ISEE 2007 SL - https://www.isee.biz */ /dts-v1/; diff --git a/src/arm/ti/omap/am335x-myirtech-myc.dtsi b/src/arm/ti/omap/am335x-myirtech-myc.dtsi index 58459926921..9c9359844a2 100644 --- a/src/arm/ti/omap/am335x-myirtech-myc.dtsi +++ b/src/arm/ti/omap/am335x-myirtech-myc.dtsi @@ -2,7 +2,7 @@ /* SPDX-FileCopyrightText: Alexander Shiyan, */ /* Based on code by myc_c335x.dts, MYiRtech.com */ -/* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */ +/* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm/ti/omap/am335x-myirtech-myd.dts b/src/arm/ti/omap/am335x-myirtech-myd.dts index d3bba79b935..fd91a3c01a6 100644 --- a/src/arm/ti/omap/am335x-myirtech-myd.dts +++ b/src/arm/ti/omap/am335x-myirtech-myd.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* SPDX-FileCopyrightText: Alexander Shiyan, */ /* Based on code by myd_c335x.dts, MYiRtech.com */ -/* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */ +/* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm/ti/omap/am335x-nano.dts b/src/arm/ti/omap/am335x-nano.dts index a475c0d9130..26b5510cb3d 100644 --- a/src/arm/ti/omap/am335x-nano.dts +++ b/src/arm/ti/omap/am335x-nano.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/ + * Copyright (C) 2013 Newflow Ltd - https://www.newflow.co.uk/ */ /dts-v1/; diff --git a/src/arm/ti/omap/am335x-netcan-plus-1xx.dts b/src/arm/ti/omap/am335x-netcan-plus-1xx.dts index f7fad48e36e..546e88f8fba 100644 --- a/src/arm/ti/omap/am335x-netcan-plus-1xx.dts +++ b/src/arm/ti/omap/am335x-netcan-plus-1xx.dts @@ -5,7 +5,7 @@ /* * VScom OnRISC - * http://www.vscom.de + * https://www.vscom.de */ /dts-v1/; diff --git a/src/arm/ti/omap/am335x-netcom-plus-2xx.dts b/src/arm/ti/omap/am335x-netcom-plus-2xx.dts index 76751a324ad..f66d57bb685 100644 --- a/src/arm/ti/omap/am335x-netcom-plus-2xx.dts +++ b/src/arm/ti/omap/am335x-netcom-plus-2xx.dts @@ -5,7 +5,7 @@ /* * VScom OnRISC - * http://www.vscom.de + * https://www.vscom.de */ /dts-v1/; diff --git a/src/arm/ti/omap/am335x-netcom-plus-8xx.dts b/src/arm/ti/omap/am335x-netcom-plus-8xx.dts index 5a9fcec040f..5fb2c629f35 100644 --- a/src/arm/ti/omap/am335x-netcom-plus-8xx.dts +++ b/src/arm/ti/omap/am335x-netcom-plus-8xx.dts @@ -5,7 +5,7 @@ /* * VScom OnRISC - * http://www.vscom.de + * https://www.vscom.de */ /dts-v1/; diff --git a/src/arm/ti/omap/am335x-pdu001.dts b/src/arm/ti/omap/am335x-pdu001.dts index 3c9444e98c1..f38f5bff2b9 100644 --- a/src/arm/ti/omap/am335x-pdu001.dts +++ b/src/arm/ti/omap/am335x-pdu001.dts @@ -3,7 +3,7 @@ * * EETS GmbH PDU001 board device tree file * - * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ + * Copyright (C) 2018 EETS GmbH - https://www.eets.ch/ * * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ * diff --git a/src/arm/ti/omap/am335x-sancloud-bbe-extended-wifi.dts b/src/arm/ti/omap/am335x-sancloud-bbe-extended-wifi.dts index 5522759def2..7c9f65126c6 100644 --- a/src/arm/ti/omap/am335x-sancloud-bbe-extended-wifi.dts +++ b/src/arm/ti/omap/am335x-sancloud-bbe-extended-wifi.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2021 Sancloud Ltd - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm/ti/omap/am335x-sancloud-bbe-lite.dts b/src/arm/ti/omap/am335x-sancloud-bbe-lite.dts index b1b400226d8..c6c96f6182a 100644 --- a/src/arm/ti/omap/am335x-sancloud-bbe-lite.dts +++ b/src/arm/ti/omap/am335x-sancloud-bbe-lite.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * Copyright (C) 2021 SanCloud Ltd */ /dts-v1/; diff --git a/src/arm/ti/omap/am335x-sbc-t335.dts b/src/arm/ti/omap/am335x-sbc-t335.dts index 596774c8474..2841e95d9a0 100644 --- a/src/arm/ti/omap/am335x-sbc-t335.dts +++ b/src/arm/ti/omap/am335x-sbc-t335.dts @@ -2,7 +2,7 @@ /* * am335x-sbc-t335.dts - Device Tree file for Compulab SBC-T335 * - * Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/ + * Copyright (C) 2014 - 2015 CompuLab Ltd. - https://www.compulab.co.il/ */ #include "am335x-cm-t335.dts" diff --git a/src/arm/ti/omap/am335x-sl50.dts b/src/arm/ti/omap/am335x-sl50.dts index 1115c812f6c..757ebd96b3f 100644 --- a/src/arm/ti/omap/am335x-sl50.dts +++ b/src/arm/ti/omap/am335x-sl50.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2015 Toby Churchill - http://www.toby-churchill.com/ + * Copyright (C) 2015 Toby Churchill - https://www.toby-churchill.com/ + * url above is defunct */ /dts-v1/; diff --git a/src/arm/ti/omap/am33xx-clocks.dtsi b/src/arm/ti/omap/am33xx-clocks.dtsi index d34483ae177..99b62c6b4ce 100644 --- a/src/arm/ti/omap/am33xx-clocks.dtsi +++ b/src/arm/ti/omap/am33xx-clocks.dtsi @@ -108,30 +108,31 @@ compatible = "ti,clksel"; reg = <0x664>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - ehrpwm0_tbclk: clock-ehrpwm0-tbclk { + ehrpwm0_tbclk: clock-ehrpwm0-tbclk@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,gate-clock"; clock-output-names = "ehrpwm0_tbclk"; clocks = <&l4ls_gclk>; - ti,bit-shift = <0>; }; - ehrpwm1_tbclk: clock-ehrpwm1-tbclk { + ehrpwm1_tbclk: clock-ehrpwm1-tbclk@1 { + reg = <1>; #clock-cells = <0>; compatible = "ti,gate-clock"; clock-output-names = "ehrpwm1_tbclk"; clocks = <&l4ls_gclk>; - ti,bit-shift = <1>; }; - ehrpwm2_tbclk: clock-ehrpwm2-tbclk { + ehrpwm2_tbclk: clock-ehrpwm2-tbclk@2 { + reg = <2>; #clock-cells = <0>; compatible = "ti,gate-clock"; clock-output-names = "ehrpwm2_tbclk"; clocks = <&l4ls_gclk>; - ti,bit-shift = <2>; }; }; }; @@ -566,17 +567,19 @@ compatible = "ti,clksel"; reg = <0x52c>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - gfx_fclk_clksel_ck: clock-gfx-fclk-clksel { + gfx_fclk_clksel_ck: clock-gfx-fclk-clksel@1 { + reg = <1>; #clock-cells = <0>; compatible = "ti,mux-clock"; clock-output-names = "gfx_fclk_clksel_ck"; clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>; - ti,bit-shift = <1>; }; - gfx_fck_div_ck: clock-gfx-fck-div { + gfx_fck_div_ck: clock-gfx-fck-div@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "gfx_fck_div_ck"; @@ -589,30 +592,32 @@ compatible = "ti,clksel"; reg = <0x700>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - sysclkout_pre_ck: clock-sysclkout-pre { + sysclkout_pre_ck: clock-sysclkout-pre@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,mux-clock"; clock-output-names = "sysclkout_pre_ck"; clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>; }; - clkout2_div_ck: clock-clkout2-div { + clkout2_div_ck: clock-clkout2-div@3 { + reg = <3>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "clkout2_div_ck"; clocks = <&sysclkout_pre_ck>; - ti,bit-shift = <3>; ti,max-div = <8>; }; - clkout2_ck: clock-clkout2 { + clkout2_ck: clock-clkout2@7 { + reg = <7>; #clock-cells = <0>; compatible = "ti,gate-clock"; clock-output-names = "clkout2_ck"; clocks = <&clkout2_div_ck>; - ti,bit-shift = <7>; }; }; }; diff --git a/src/arm/ti/omap/am33xx.dtsi b/src/arm/ti/omap/am33xx.dtsi index 5b9e01a8aa5..989d5a6edee 100644 --- a/src/arm/ti/omap/am33xx.dtsi +++ b/src/arm/ti/omap/am33xx.dtsi @@ -640,10 +640,11 @@ #size-cells = <1>; ranges = <0 0x56000000 0x1000000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + gpu@0 { + compatible = "ti,omap3630-gpu", "img,powervr-sgx530"; + reg = <0x0 0x10000>; /* 64kB */ + interrupts = <37>; + }; }; }; }; diff --git a/src/arm/ti/omap/am3517.dtsi b/src/arm/ti/omap/am3517.dtsi index 77e58e686fb..19aad715dff 100644 --- a/src/arm/ti/omap/am3517.dtsi +++ b/src/arm/ti/omap/am3517.dtsi @@ -162,12 +162,13 @@ clock-names = "fck", "ick"; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x50000000 0x4000>; + ranges = <0 0x50000000 0x10000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + gpu@0 { + compatible = "ti,omap3430-gpu", "img,powervr-sgx530"; + reg = <0x0 0x10000>; /* 64kB */ + interrupts = <21>; + }; }; }; }; diff --git a/src/arm/ti/omap/am35xx-clocks.dtsi b/src/arm/ti/omap/am35xx-clocks.dtsi index 0ee7afaa0e8..b521139e6f5 100644 --- a/src/arm/ti/omap/am35xx-clocks.dtsi +++ b/src/arm/ti/omap/am35xx-clocks.dtsi @@ -66,22 +66,23 @@ compatible = "ti,clksel"; reg = <0xa10>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - ipss_ick: clock-ipss-ick { + ipss_ick: clock-ipss-ick@4 { + reg = <4>; #clock-cells = <0>; compatible = "ti,am35xx-interface-clock"; clock-output-names = "ipss_ick"; clocks = <&core_l3_ick>; - ti,bit-shift = <4>; }; - uart4_ick_am35xx: clock-uart4-ick-am35xx { + uart4_ick_am35xx: clock-uart4-ick-am35xx@23 { + reg = <23>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "uart4_ick_am35xx"; clocks = <&core_l4_ick>; - ti,bit-shift = <23>; }; }; @@ -101,14 +102,15 @@ compatible = "ti,clksel"; reg = <0xa00>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - uart4_fck_am35xx: clock-uart4-fck-am35xx { + uart4_fck_am35xx: clock-uart4-fck-am35xx@23 { + reg = <23>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "uart4_fck_am35xx"; clocks = <&core_48m_fck>; - ti,bit-shift = <23>; }; }; }; diff --git a/src/arm/ti/omap/am4372.dtsi b/src/arm/ti/omap/am4372.dtsi index 9d2c064534f..5fd1b380ece 100644 --- a/src/arm/ti/omap/am4372.dtsi +++ b/src/arm/ti/omap/am4372.dtsi @@ -719,6 +719,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 0x56000000 0x1000000>; + + gpu@0 { + compatible = "ti,omap3630-gpu", "img,powervr-sgx530"; + reg = <0x0 0x10000>; /* 64kB */ + interrupts = ; + }; }; }; }; diff --git a/src/arm/ti/omap/am437x-cm-t43.dts b/src/arm/ti/omap/am437x-cm-t43.dts index 9ec75d03eaf..172516a7667 100644 --- a/src/arm/ti/omap/am437x-cm-t43.dts +++ b/src/arm/ti/omap/am437x-cm-t43.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/ + * Copyright (C) 2015 CompuLab, Ltd. - https://www.compulab.co.il/ */ /dts-v1/; diff --git a/src/arm/ti/omap/am437x-sbc-t43.dts b/src/arm/ti/omap/am437x-sbc-t43.dts index 34a5407bee1..5ec57dcb065 100644 --- a/src/arm/ti/omap/am437x-sbc-t43.dts +++ b/src/arm/ti/omap/am437x-sbc-t43.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/ + * Copyright (C) 2015 CompuLab, Ltd. - https://www.compulab.co.il/ */ #include "am437x-cm-t43.dts" diff --git a/src/arm/ti/omap/am5729-beagleboneai.dts b/src/arm/ti/omap/am5729-beagleboneai.dts index 3e834fc7e37..eb1ec85aba2 100644 --- a/src/arm/ti/omap/am5729-beagleboneai.dts +++ b/src/arm/ti/omap/am5729-beagleboneai.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2014-2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014-2019 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm/ti/omap/am57xx-cl-som-am57x.dts b/src/arm/ti/omap/am57xx-cl-som-am57x.dts index 4fd831ff206..d6e3152b02f 100644 --- a/src/arm/ti/omap/am57xx-cl-som-am57x.dts +++ b/src/arm/ti/omap/am57xx-cl-som-am57x.dts @@ -2,7 +2,7 @@ /* * Support for CompuLab CL-SOM-AM57x System-on-Module * - * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/ + * Copyright (C) 2015 CompuLab Ltd. - https://www.compulab.co.il/ * Author: Dmitry Lifshitz */ diff --git a/src/arm/ti/omap/am57xx-sbc-am57x.dts b/src/arm/ti/omap/am57xx-sbc-am57x.dts index 363115afb0a..64675f4edb6 100644 --- a/src/arm/ti/omap/am57xx-sbc-am57x.dts +++ b/src/arm/ti/omap/am57xx-sbc-am57x.dts @@ -2,7 +2,7 @@ /* * Support for CompuLab SBC-AM57x single board computer * - * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/ + * Copyright (C) 2015 CompuLab Ltd. - https://www.compulab.co.il/ * Author: Dmitry Lifshitz */ diff --git a/src/arm/ti/omap/compulab-sb-som.dtsi b/src/arm/ti/omap/compulab-sb-som.dtsi index f5e6216718d..8a8fa1b2b26 100644 --- a/src/arm/ti/omap/compulab-sb-som.dtsi +++ b/src/arm/ti/omap/compulab-sb-som.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/ + * Copyright (C) 2015 CompuLab, Ltd. - https://www.compulab.co.il/ */ / { diff --git a/src/arm/ti/omap/dra7-l4.dtsi b/src/arm/ti/omap/dra7-l4.dtsi index 5733e3a4ea8..6e67d99832a 100644 --- a/src/arm/ti/omap/dra7-l4.dtsi +++ b/src/arm/ti/omap/dra7-l4.dtsi @@ -80,7 +80,7 @@ }; }; - phy_gmii_sel: phy-gmii-sel { + phy_gmii_sel: phy-gmii-sel@554 { compatible = "ti,dra7xx-phy-gmii-sel"; reg = <0x554 0x4>; #phy-cells = <1>; diff --git a/src/arm/ti/omap/dra7.dtsi b/src/arm/ti/omap/dra7.dtsi index 6509c742fb5..164fa88c459 100644 --- a/src/arm/ti/omap/dra7.dtsi +++ b/src/arm/ti/omap/dra7.dtsi @@ -638,7 +638,7 @@ }; }; - abb_mpu: regulator-abb-mpu { + abb_mpu: regulator-abb-mpu@4ae07ddc { compatible = "ti,abb-v3"; regulator-name = "abb_mpu"; #address-cells = <0>; @@ -671,7 +671,7 @@ >; }; - abb_ivahd: regulator-abb-ivahd { + abb_ivahd: regulator-abb-ivahd@4ae07e34 { compatible = "ti,abb-v3"; regulator-name = "abb_ivahd"; #address-cells = <0>; @@ -704,7 +704,7 @@ >; }; - abb_dspeve: regulator-abb-dspeve { + abb_dspeve: regulator-abb-dspeve@4ae07e30 { compatible = "ti,abb-v3"; regulator-name = "abb_dspeve"; #address-cells = <0>; @@ -737,7 +737,7 @@ >; }; - abb_gpu: regulator-abb-gpu { + abb_gpu: regulator-abb-gpu@4ae07de4 { compatible = "ti,abb-v3"; regulator-name = "abb_gpu"; #address-cells = <0>; @@ -850,12 +850,19 @@ ; ti,sysc-sidle = , , - ; + , + ; clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x56000000 0x2000000>; + + gpu@0 { + compatible = "ti,am5728-gpu", "img,powervr-sgx544"; + reg = <0x0 0x10000>; /* 64kB */ + interrupts = ; + }; }; crossbar_mpu: crossbar@4a002a48 { diff --git a/src/arm/ti/omap/dra74x-p.dtsi b/src/arm/ti/omap/dra74x-p.dtsi index 006189dad7a..bb5239ae164 100644 --- a/src/arm/ti/omap/dra74x-p.dtsi +++ b/src/arm/ti/omap/dra74x-p.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/src/arm/ti/omap/dra7xx-clocks.dtsi b/src/arm/ti/omap/dra7xx-clocks.dtsi index 04a7a6d1d52..06466d36caa 100644 --- a/src/arm/ti/omap/dra7xx-clocks.dtsi +++ b/src/arm/ti/omap/dra7xx-clocks.dtsi @@ -1685,7 +1685,7 @@ reg = <0x0558>; }; - sys_32k_ck: clock-sys-32k { + sys_32k_ck: clock-sys-32k@6c4 { #clock-cells = <0>; compatible = "ti,mux-clock"; clock-output-names = "sys_32k_ck"; diff --git a/src/arm/ti/omap/omap3430es1-clocks.dtsi b/src/arm/ti/omap/omap3430es1-clocks.dtsi index 24adfac26be..6e754d265f1 100644 --- a/src/arm/ti/omap/omap3430es1-clocks.dtsi +++ b/src/arm/ti/omap/omap3430es1-clocks.dtsi @@ -50,30 +50,31 @@ compatible = "ti,clksel"; reg = <0xa00>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - d2d_26m_fck: clock-d2d-26m-fck { + d2d_26m_fck: clock-d2d-26m-fck@3 { + reg = <3>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "d2d_26m_fck"; clocks = <&sys_ck>; - ti,bit-shift = <3>; }; - fshostusb_fck: clock-fshostusb-fck { + fshostusb_fck: clock-fshostusb-fck@5 { + reg = <5>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "fshostusb_fck"; clocks = <&core_48m_fck>; - ti,bit-shift = <5>; }; - ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1 { + ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clock-output-names = "ssi_ssr_gate_fck_3430es1"; clocks = <&corex2_fck>; - ti,bit-shift = <0>; }; }; @@ -81,23 +82,24 @@ compatible = "ti,clksel"; reg = <0xa40>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1 { + ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1@8 { + reg = <8>; #clock-cells = <0>; compatible = "ti,composite-divider-clock"; clock-output-names = "ssi_ssr_div_fck_3430es1"; clocks = <&corex2_fck>; - ti,bit-shift = <8>; ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; }; - usb_l4_div_ick: clock-usb-l4-div-ick { + usb_l4_div_ick: clock-usb-l4-div-ick@4 { + reg = <4>; #clock-cells = <0>; compatible = "ti,composite-divider-clock"; clock-output-names = "usb_l4_div_ick"; clocks = <&l4_ick>; - ti,bit-shift = <4>; ti,max-div = <1>; ti,index-starts-at-one; }; @@ -121,38 +123,39 @@ compatible = "ti,clksel"; reg = <0xa10>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1 { + hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1@4 { + reg = <4>; #clock-cells = <0>; compatible = "ti,omap3-no-wait-interface-clock"; clock-output-names = "hsotgusb_ick_3430es1"; clocks = <&core_l3_ick>; - ti,bit-shift = <4>; }; - fac_ick: clock-fac-ick { + fac_ick: clock-fac-ick@8 { + reg = <8>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "fac_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <8>; }; - ssi_ick: clock-ssi-ick-3430es1 { + ssi_ick: clock-ssi-ick-3430es1@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,omap3-no-wait-interface-clock"; clock-output-names = "ssi_ick_3430es1"; clocks = <&ssi_l4_ick>; - ti,bit-shift = <0>; }; - usb_l4_gate_ick: clock-usb-l4-gate-ick { + usb_l4_gate_ick: clock-usb-l4-gate-ick@5 { + reg = <5>; #clock-cells = <0>; compatible = "ti,composite-interface-clock"; clock-output-names = "usb_l4_gate_ick"; clocks = <&l4_ick>; - ti,bit-shift = <5>; }; }; @@ -174,14 +177,15 @@ compatible = "ti,clksel"; reg = <0xe00>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - dss1_alwon_fck: clock-dss1-alwon-fck-3430es1 { + dss1_alwon_fck: clock-dss1-alwon-fck-3430es1@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,gate-clock"; clock-output-names = "dss1_alwon_fck_3430es1"; clocks = <&dpll4_m4x2_ck>; - ti,bit-shift = <0>; ti,set-rate-parent; }; }; diff --git a/src/arm/ti/omap/omap34xx-omap36xx-clocks.dtsi b/src/arm/ti/omap/omap34xx-omap36xx-clocks.dtsi index 8374532f20e..ca6372711ba 100644 --- a/src/arm/ti/omap/omap34xx-omap36xx-clocks.dtsi +++ b/src/arm/ti/omap/omap34xx-omap36xx-clocks.dtsi @@ -17,46 +17,47 @@ compatible = "ti,clksel"; reg = <0xa14>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - aes1_ick: clock-aes1-ick { + aes1_ick: clock-aes1-ick@3 { + reg = <3>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "aes1_ick"; clocks = <&security_l4_ick2>; - ti,bit-shift = <3>; }; - rng_ick: clock-rng-ick { + rng_ick: clock-rng-ick@2 { + reg = <2>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "rng_ick"; clocks = <&security_l4_ick2>; - ti,bit-shift = <2>; }; - sha11_ick: clock-sha11-ick { + sha11_ick: clock-sha11-ick@1 { + reg = <1>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "sha11_ick"; clocks = <&security_l4_ick2>; - ti,bit-shift = <1>; }; - des1_ick: clock-des1-ick { + des1_ick: clock-des1-ick@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "des1_ick"; clocks = <&security_l4_ick2>; - ti,bit-shift = <0>; }; - pka_ick: clock-pka-ick { + pka_ick: clock-pka-ick@4 { + reg = <4>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "pka_ick"; clocks = <&security_l3_ick>; - ti,bit-shift = <4>; }; }; @@ -65,23 +66,24 @@ compatible = "ti,clksel"; reg = <0xf00>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - cam_mclk: clock-cam-mclk { + cam_mclk: clock-cam-mclk@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,gate-clock"; clock-output-names = "cam_mclk"; clocks = <&dpll4_m5x2_ck>; - ti,bit-shift = <0>; ti,set-rate-parent; }; - csi2_96m_fck: clock-csi2-96m-fck { + csi2_96m_fck: clock-csi2-96m-fck@1 { + reg = <1>; #clock-cells = <0>; compatible = "ti,gate-clock"; clock-output-names = "csi2_96m_fck"; clocks = <&core_96m_fck>; - ti,bit-shift = <1>; }; }; @@ -105,46 +107,47 @@ compatible = "ti,clksel"; reg = <0xa10>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - icr_ick: clock-icr-ick { + icr_ick: clock-icr-ick@29 { + reg = <29>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "icr_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <29>; }; - des2_ick: clock-des2-ick { + des2_ick: clock-des2-ick@26 { + reg = <26>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "des2_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <26>; }; - mspro_ick: clock-mspro-ick { + mspro_ick: clock-mspro-ick@23 { + reg = <23>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mspro_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <23>; }; - mailboxes_ick: clock-mailboxes-ick { + mailboxes_ick: clock-mailboxes-ick@7 { + reg = <7>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mailboxes_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <7>; }; - sad2d_ick: clock-sad2d-ick { + sad2d_ick: clock-sad2d-ick@3 { + reg = <3>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "sad2d_ick"; clocks = <&l3_ick>; - ti,bit-shift = <3>; }; }; @@ -160,22 +163,23 @@ compatible = "ti,clksel"; reg = <0xc00>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - sr1_fck: clock-sr1-fck { + sr1_fck: clock-sr1-fck@6 { + reg = <6>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "sr1_fck"; clocks = <&sys_ck>; - ti,bit-shift = <6>; }; - sr2_fck: clock-sr2-fck { + sr2_fck: clock-sr2-fck@7 { + reg = <7>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "sr2_fck"; clocks = <&sys_ck>; - ti,bit-shift = <7>; }; }; @@ -228,22 +232,23 @@ compatible = "ti,clksel"; reg = <0xa00>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - modem_fck: clock-modem-fck { + modem_fck: clock-modem-fck@31 { + reg = <31>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "modem_fck"; clocks = <&sys_ck>; - ti,bit-shift = <31>; }; - mspro_fck: clock-mspro-fck { + mspro_fck: clock-mspro-fck@23 { + reg = <23>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "mspro_fck"; clocks = <&core_96m_fck>; - ti,bit-shift = <23>; }; }; @@ -252,14 +257,15 @@ compatible = "ti,clksel"; reg = <0xa18>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #ssize-cells = <0>; - mad2d_ick: clock-mad2d-ick { + mad2d_ick: clock-mad2d-ick@3 { + reg = <3>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mad2d_ick"; clocks = <&l3_ick>; - ti,bit-shift = <3>; }; }; diff --git a/src/arm/ti/omap/omap34xx.dtsi b/src/arm/ti/omap/omap34xx.dtsi index fc7233ac183..acdd0ee3442 100644 --- a/src/arm/ti/omap/omap34xx.dtsi +++ b/src/arm/ti/omap/omap34xx.dtsi @@ -164,12 +164,13 @@ clock-names = "fck", "ick"; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x50000000 0x4000>; + ranges = <0 0x50000000 0x10000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + gpu@0 { + compatible = "ti,omap3430-gpu", "img,powervr-sgx530"; + reg = <0x0 0x10000>; /* 64kB */ + interrupts = <21>; + }; }; }; diff --git a/src/arm/ti/omap/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/src/arm/ti/omap/omap36xx-am35xx-omap3430es2plus-clocks.dtsi index dcc5cfcd1fe..656cf80f878 100644 --- a/src/arm/ti/omap/omap36xx-am35xx-omap3430es2plus-clocks.dtsi +++ b/src/arm/ti/omap/omap36xx-am35xx-omap3430es2plus-clocks.dtsi @@ -138,14 +138,15 @@ compatible = "ti,clksel"; reg = <0xa18>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - usbtll_ick: clock-usbtll-ick { + usbtll_ick: clock-usbtll-ick@2 { + reg = <2>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "usbtll_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <2>; }; }; @@ -153,14 +154,15 @@ compatible = "ti,clksel"; reg = <0xa10>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - mmchs3_ick: clock-mmchs3-ick { + mmchs3_ick: clock-mmchs3-ick@30 { + reg = <30>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mmchs3_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <30>; }; }; @@ -168,14 +170,15 @@ compatible = "ti,clksel"; reg = <0xa00>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - mmchs3_fck: clock-mmchs3-fck { + mmchs3_fck: clock-mmchs3-fck@30 { + reg = <30>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "mmchs3_fck"; clocks = <&core_96m_fck>; - ti,bit-shift = <30>; }; }; @@ -183,14 +186,15 @@ compatible = "ti,clksel"; reg = <0xe00>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - dss1_alwon_fck: clock-dss1-alwon-fck-3430es2 { + dss1_alwon_fck: clock-dss1-alwon-fck-3430es2@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,dss-gate-clock"; clock-output-names = "dss1_alwon_fck_3430es2"; clocks = <&dpll4_m4x2_ck>; - ti,bit-shift = <0>; ti,set-rate-parent; }; }; diff --git a/src/arm/ti/omap/omap36xx-clocks.dtsi b/src/arm/ti/omap/omap36xx-clocks.dtsi index c5fdb2bd765..1e90f2b1ef8 100644 --- a/src/arm/ti/omap/omap36xx-clocks.dtsi +++ b/src/arm/ti/omap/omap36xx-clocks.dtsi @@ -62,14 +62,15 @@ compatible = "ti,clksel"; reg = <0x1000>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - uart4_fck: clock-uart4-fck { + uart4_fck: clock-uart4-fck@18 { + reg = <18>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "uart4_fck"; clocks = <&per_48m_fck>; - ti,bit-shift = <18>; }; }; }; diff --git a/src/arm/ti/omap/omap36xx-omap3430es2plus-clocks.dtsi b/src/arm/ti/omap/omap36xx-omap3430es2plus-clocks.dtsi index c94eb86d3da..798acb839db 100644 --- a/src/arm/ti/omap/omap36xx-omap3430es2plus-clocks.dtsi +++ b/src/arm/ti/omap/omap36xx-omap3430es2plus-clocks.dtsi @@ -9,14 +9,15 @@ compatible = "ti,clksel"; reg = <0xa00>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2 { + ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clock-output-names = "ssi_ssr_gate_fck_3430es2"; clocks = <&corex2_fck>; - ti,bit-shift = <0>; }; }; @@ -24,14 +25,15 @@ compatible = "ti,clksel"; reg = <0xa40>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2 { + ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2@8 { + reg = <8>; #clock-cells = <0>; compatible = "ti,composite-divider-clock"; clock-output-names = "ssi_ssr_div_fck_3430es2"; clocks = <&corex2_fck>; - ti,bit-shift = <8>; ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; }; }; @@ -54,22 +56,23 @@ compatible = "ti,clksel"; reg = <0xa10>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - hsotgusb_ick_3430es2: clock-hsotgusb-ick-3430es2 { + hsotgusb_ick_3430es2: clock-hsotgusb-ick-3430es2@4 { + reg = <4>; #clock-cells = <0>; compatible = "ti,omap3-hsotgusb-interface-clock"; clock-output-names = "hsotgusb_ick_3430es2"; clocks = <&core_l3_ick>; - ti,bit-shift = <4>; }; - ssi_ick: clock-ssi-ick-3430es2 { + ssi_ick: clock-ssi-ick-3430es2@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,omap3-ssi-interface-clock"; clock-output-names = "ssi_ick_3430es2"; clocks = <&ssi_l4_ick>; - ti,bit-shift = <0>; }; }; @@ -85,14 +88,15 @@ compatible = "ti,clksel"; reg = <0xc00>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - usim_gate_fck: clock-usim-gate-fck { + usim_gate_fck: clock-usim-gate-fck@9 { + reg = <9>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "usim_gate_fck"; clocks = <&omap_96m_fck>; - ti,bit-shift = <9>; }; }; @@ -172,14 +176,15 @@ compatible = "ti,clksel"; reg = <0xc40>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - usim_mux_fck: clock-usim-mux-fck { + usim_mux_fck: clock-usim-mux-fck@3 { + reg = <3>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "usim_mux_fck"; clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>; - ti,bit-shift = <3>; ti,index-starts-at-one; }; }; @@ -194,14 +199,15 @@ compatible = "ti,clksel"; reg = <0xc10>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - usim_ick: clock-usim-ick { + usim_ick: clock-usim-ick@9 { + reg = <9>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "usim_ick"; clocks = <&wkup_l4_ick>; - ti,bit-shift = <9>; }; }; }; diff --git a/src/arm/ti/omap/omap36xx.dtsi b/src/arm/ti/omap/omap36xx.dtsi index e6d8070c1bf..c3d79ecd56e 100644 --- a/src/arm/ti/omap/omap36xx.dtsi +++ b/src/arm/ti/omap/omap36xx.dtsi @@ -211,10 +211,11 @@ #size-cells = <1>; ranges = <0 0x50000000 0x2000000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + gpu@0 { + compatible = "ti,omap3630-gpu", "img,powervr-sgx530"; + reg = <0x0 0x2000000>; /* 32MB */ + interrupts = <21>; + }; }; }; diff --git a/src/arm/ti/omap/omap3xxx-clocks.dtsi b/src/arm/ti/omap/omap3xxx-clocks.dtsi index 2e13ca11cee..901ee79a66f 100644 --- a/src/arm/ti/omap/omap3xxx-clocks.dtsi +++ b/src/arm/ti/omap/omap3xxx-clocks.dtsi @@ -83,29 +83,31 @@ compatible = "ti,clksel"; reg = <0x68>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - mcbsp5_mux_fck: clock-mcbsp5-mux-fck { + mcbsp5_mux_fck: clock-mcbsp5-mux-fck@4 { + reg = <4>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "mcbsp5_mux_fck"; clocks = <&core_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <4>; }; - mcbsp3_mux_fck: clock-mcbsp3-mux-fck { + mcbsp3_mux_fck: clock-mcbsp3-mux-fck@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "mcbsp3_mux_fck"; clocks = <&per_96m_fck>, <&mcbsp_clks>; }; - mcbsp4_mux_fck: clock-mcbsp4-mux-fck { + mcbsp4_mux_fck: clock-mcbsp4-mux-fck@2 { + reg = <2>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "mcbsp4_mux_fck"; clocks = <&per_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <2>; }; }; @@ -120,22 +122,23 @@ compatible = "ti,clksel"; reg = <0x4>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - mcbsp1_mux_fck: clock-mcbsp1-mux-fck { + mcbsp1_mux_fck: clock-mcbsp1-mux-fck@2 { + reg = <2>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "mcbsp1_mux_fck"; clocks = <&core_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <2>; }; - mcbsp2_mux_fck: clock-mcbsp2-mux-fck { + mcbsp2_mux_fck: clock-mcbsp2-mux-fck@6 { + reg = <6>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "mcbsp2_mux_fck"; clocks = <&per_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <6>; }; }; @@ -259,79 +262,81 @@ compatible = "ti,clksel"; reg = <0x1140>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - dpll3_m3_ck: clock-dpll3-m3 { + dpll3_m3_ck: clock-dpll3-m3@16 { + reg = <16>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "dpll3_m3_ck"; clocks = <&dpll3_ck>; - ti,bit-shift = <16>; ti,max-div = <31>; ti,index-starts-at-one; }; - dpll4_m6_ck: clock-dpll4-m6 { + dpll4_m6_ck: clock-dpll4-m6@24 { + reg = <24>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "dpll4_m6_ck"; clocks = <&dpll4_ck>; - ti,bit-shift = <24>; ti,max-div = <63>; ti,index-starts-at-one; }; - emu_src_mux_ck: clock-emu-src-mux { + emu_src_mux_ck: clock-emu-src-mux@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,mux-clock"; clock-output-names = "emu_src_mux_ck"; clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; }; - pclk_fck: clock-pclk-fck { + pclk_fck: clock-pclk-fck@8 { + reg = <8>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "pclk_fck"; clocks = <&emu_src_ck>; - ti,bit-shift = <8>; ti,max-div = <7>; ti,index-starts-at-one; }; - pclkx2_fck: clock-pclkx2-fck { + pclkx2_fck: clock-pclkx2-fck@6 { + reg = <6>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "pclkx2_fck"; clocks = <&emu_src_ck>; - ti,bit-shift = <6>; ti,max-div = <3>; ti,index-starts-at-one; }; - atclk_fck: clock-atclk-fck { + atclk_fck: clock-atclk-fck@4 { + reg = <4>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "atclk_fck"; clocks = <&emu_src_ck>; - ti,bit-shift = <4>; ti,max-div = <3>; ti,index-starts-at-one; }; - traceclk_src_fck: clock-traceclk-src-fck { + traceclk_src_fck: clock-traceclk-src-fck@2 { + reg = <2>; #clock-cells = <0>; compatible = "ti,mux-clock"; clock-output-names = "traceclk_src_fck"; clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; - ti,bit-shift = <2>; }; - traceclk_fck: clock-traceclk-fck { + traceclk_fck: clock-traceclk-fck@11 { + reg = <11>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "traceclk_fck"; clocks = <&traceclk_src_fck>; - ti,bit-shift = <11>; ti,max-div = <7>; ti,index-starts-at-one; }; @@ -429,40 +434,41 @@ compatible = "ti,clksel"; reg = <0xd40>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - dpll3_m2_ck: clock-dpll3-m2 { + dpll3_m2_ck: clock-dpll3-m2@27 { + reg = <27>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "dpll3_m2_ck"; clocks = <&dpll3_ck>; - ti,bit-shift = <27>; ti,max-div = <31>; ti,index-starts-at-one; }; - omap_96m_fck: clock-omap-96m-fck { + omap_96m_fck: clock-omap-96m-fck@6 { + reg = <6>; #clock-cells = <0>; compatible = "ti,mux-clock"; clock-output-names = "omap_96m_fck"; clocks = <&cm_96m_fck>, <&sys_ck>; - ti,bit-shift = <6>; }; - omap_54m_fck: clock-omap-54m-fck { + omap_54m_fck: clock-omap-54m-fck@5 { + reg = <5>; #clock-cells = <0>; compatible = "ti,mux-clock"; clock-output-names = "omap_54m_fck"; clocks = <&dpll4_m3x2_ck>, <&sys_altclk>; - ti,bit-shift = <5>; }; - omap_48m_fck: clock-omap-48m-fck { + omap_48m_fck: clock-omap-48m-fck@3 { + reg = <3>; #clock-cells = <0>; compatible = "ti,mux-clock"; clock-output-names = "omap_48m_fck"; clocks = <&cm_96m_d2_fck>, <&sys_altclk>; - ti,bit-shift = <3>; }; }; @@ -471,19 +477,21 @@ compatible = "ti,clksel"; reg = <0xe40>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - dpll4_m3_ck: clock-dpll4-m3 { + dpll4_m3_ck: clock-dpll4-m3@8 { + reg = <8>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "dpll4_m3_ck"; clocks = <&dpll4_ck>; - ti,bit-shift = <8>; ti,max-div = <32>; ti,index-starts-at-one; }; - dpll4_m4_ck: clock-dpll4-m4 { + dpll4_m4_ck: clock-dpll4-m4@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "dpll4_m4_ck"; @@ -603,29 +611,31 @@ compatible = "ti,clksel"; reg = <0xd70>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - clkout2_src_gate_ck: clock-clkout2-src-gate { + clkout2_src_gate_ck: clock-clkout2-src-gate@7 { + reg = <7>; #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clock-output-names = "clkout2_src_gate_ck"; clocks = <&core_ck>; - ti,bit-shift = <7>; }; - clkout2_src_mux_ck: clock-clkout2-src-mux { + clkout2_src_mux_ck: clock-clkout2-src-mux@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "clkout2_src_mux_ck"; clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>; }; - sys_clkout2: clock-sys-clkout2 { + sys_clkout2: clock-sys-clkout2@3 { + reg = <3>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "sys_clkout2"; clocks = <&clkout2_src_ck>; - ti,bit-shift = <3>; ti,max-div = <64>; ti,index-power-of-two; }; @@ -666,9 +676,11 @@ compatible = "ti,clksel"; reg = <0xa40>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - l3_ick: clock-l3-ick { + l3_ick: clock-l3-ick@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "l3_ick"; @@ -677,30 +689,30 @@ ti,index-starts-at-one; }; - l4_ick: clock-l4-ick { + l4_ick: clock-l4-ick@2 { + reg = <2>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "l4_ick"; clocks = <&l3_ick>; - ti,bit-shift = <2>; ti,max-div = <3>; ti,index-starts-at-one; }; - gpt10_mux_fck: clock-gpt10-mux-fck { + gpt10_mux_fck: clock-gpt10-mux-fck@6 { + reg = <6>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "gpt10_mux_fck"; clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <6>; }; - gpt11_mux_fck: clock-gpt11-mux-fck { + gpt11_mux_fck: clock-gpt11-mux-fck@7 { + reg = <7>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "gpt11_mux_fck"; clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <7>; }; }; @@ -709,19 +721,21 @@ compatible = "ti,clksel"; reg = <0xc40>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - rm_ick: clock-rm-ick { + rm_ick: clock-rm-ick@1 { + reg = <1>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "rm_ick"; clocks = <&l4_ick>; - ti,bit-shift = <1>; ti,max-div = <3>; ti,index-starts-at-one; }; - gpt1_mux_fck: clock-gpt1-mux-fck { + gpt1_mux_fck: clock-gpt1-mux-fck@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "gpt1_mux_fck"; @@ -734,134 +748,135 @@ compatible = "ti,clksel"; reg = <0xa00>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - gpt10_gate_fck: clock-gpt10-gate-fck { + gpt10_gate_fck: clock-gpt10-gate-fck@11 { + reg = <11>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "gpt10_gate_fck"; clocks = <&sys_ck>; - ti,bit-shift = <11>; }; - gpt11_gate_fck: clock-gpt11-gate-fck { + gpt11_gate_fck: clock-gpt11-gate-fck@12 { + reg = <12>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "gpt11_gate_fck"; clocks = <&sys_ck>; - ti,bit-shift = <12>; }; - mmchs2_fck: clock-mmchs2-fck { + mmchs2_fck: clock-mmchs2-fck@25 { + reg = <25>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "mmchs2_fck"; clocks = <&core_96m_fck>; - ti,bit-shift = <25>; }; - mmchs1_fck: clock-mmchs1-fck { + mmchs1_fck: clock-mmchs1-fck@24 { + reg = <24>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "mmchs1_fck"; clocks = <&core_96m_fck>; - ti,bit-shift = <24>; }; - i2c3_fck: clock-i2c3-fck { + i2c3_fck: clock-i2c3-fck@17 { + reg = <17>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "i2c3_fck"; clocks = <&core_96m_fck>; - ti,bit-shift = <17>; }; - i2c2_fck: clock-i2c2-fck { + i2c2_fck: clock-i2c2-fck@16 { + reg = <16>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "i2c2_fck"; clocks = <&core_96m_fck>; - ti,bit-shift = <16>; }; - i2c1_fck: clock-i2c1-fck { + i2c1_fck: clock-i2c1-fck@15 { + reg = <15>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "i2c1_fck"; clocks = <&core_96m_fck>; - ti,bit-shift = <15>; }; - mcbsp5_gate_fck: clock-mcbsp5-gate-fck { + mcbsp5_gate_fck: clock-mcbsp5-gate-fck@10 { + reg = <10>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "mcbsp5_gate_fck"; clocks = <&mcbsp_clks>; - ti,bit-shift = <10>; }; - mcbsp1_gate_fck: clock-mcbsp1-gate-fck { + mcbsp1_gate_fck: clock-mcbsp1-gate-fck@9 { + reg = <9>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "mcbsp1_gate_fck"; clocks = <&mcbsp_clks>; - ti,bit-shift = <9>; }; - mcspi4_fck: clock-mcspi4-fck { + mcspi4_fck: clock-mcspi4-fck@21 { + reg = <21>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "mcspi4_fck"; clocks = <&core_48m_fck>; - ti,bit-shift = <21>; }; - mcspi3_fck: clock-mcspi3-fck { + mcspi3_fck: clock-mcspi3-fck@20 { + reg = <20>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "mcspi3_fck"; clocks = <&core_48m_fck>; - ti,bit-shift = <20>; }; - mcspi2_fck: clock-mcspi2-fck { + mcspi2_fck: clock-mcspi2-fck@19 { + reg = <19>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "mcspi2_fck"; clocks = <&core_48m_fck>; - ti,bit-shift = <19>; }; - mcspi1_fck: clock-mcspi1-fck { + mcspi1_fck: clock-mcspi1-fck@18 { + reg = <18>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "mcspi1_fck"; clocks = <&core_48m_fck>; - ti,bit-shift = <18>; }; - uart2_fck: clock-uart2-fck { + uart2_fck: clock-uart2-fck@14 { + reg = <14>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "uart2_fck"; clocks = <&core_48m_fck>; - ti,bit-shift = <14>; }; - uart1_fck: clock-uart1-fck { + uart1_fck: clock-uart1-fck@13 { + reg = <13>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "uart1_fck"; clocks = <&core_48m_fck>; - ti,bit-shift = <13>; }; - hdq_fck: clock-hdq-fck { + hdq_fck: clock-hdq-fck@22 { + reg = <22>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "hdq_fck"; clocks = <&core_12m_fck>; - ti,bit-shift = <22>; }; }; @@ -914,166 +929,167 @@ compatible = "ti,clksel"; reg = <0xa10>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - sdrc_ick: clock-sdrc-ick { + sdrc_ick: clock-sdrc-ick@1 { + reg = <1>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "sdrc_ick"; clocks = <&core_l3_ick>; - ti,bit-shift = <1>; }; - mmchs2_ick: clock-mmchs2-ick { + mmchs2_ick: clock-mmchs2-ick@25 { + reg = <25>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mmchs2_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <25>; }; - mmchs1_ick: clock-mmchs1-ick { + mmchs1_ick: clock-mmchs1-ick@24 { + reg = <24>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mmchs1_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <24>; }; - hdq_ick: clock-hdq-ick { + hdq_ick: clock-hdq-ick@22 { + reg = <22>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "hdq_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <22>; }; - mcspi4_ick: clock-mcspi4-ick { + mcspi4_ick: clock-mcspi4-ick@21 { + reg = <21>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mcspi4_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <21>; }; - mcspi3_ick: clock-mcspi3-ick { + mcspi3_ick: clock-mcspi3-ick@20 { + reg = <20>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mcspi3_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <20>; }; - mcspi2_ick: clock-mcspi2-ick { + mcspi2_ick: clock-mcspi2-ick@19 { + reg = <19>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mcspi2_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <19>; }; - mcspi1_ick: clock-mcspi1-ick { + mcspi1_ick: clock-mcspi1-ick@18 { + reg = <18>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mcspi1_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <18>; }; - i2c3_ick: clock-i2c3-ick { + i2c3_ick: clock-i2c3-ick@17 { + reg = <17>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "i2c3_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <17>; }; - i2c2_ick: clock-i2c2-ick { + i2c2_ick: clock-i2c2-ick@16 { + reg = <16>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "i2c2_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <16>; }; - i2c1_ick: clock-i2c1-ick { + i2c1_ick: clock-i2c1-ick@15 { + reg = <15>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "i2c1_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <15>; }; - uart2_ick: clock-uart2-ick { + uart2_ick: clock-uart2-ick@14 { + reg = <14>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "uart2_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <14>; }; - uart1_ick: clock-uart1-ick { + uart1_ick: clock-uart1-ick@13 { + reg = <13>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "uart1_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <13>; }; - gpt11_ick: clock-gpt11-ick { + gpt11_ick: clock-gpt11-ick@12 { + reg = <12>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpt11_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <12>; }; - gpt10_ick: clock-gpt10-ick { + gpt10_ick: clock-gpt10-ick@11 { + reg = <11>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpt10_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <11>; }; - mcbsp5_ick: clock-mcbsp5-ick { + mcbsp5_ick: clock-mcbsp5-ick@10 { + reg = <10>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mcbsp5_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <10>; }; - mcbsp1_ick: clock-mcbsp1-ick { + mcbsp1_ick: clock-mcbsp1-ick@9 { + reg = <9>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mcbsp1_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <9>; }; - omapctrl_ick: clock-omapctrl-ick { + omapctrl_ick: clock-omapctrl-ick@6 { + reg = <6>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "omapctrl_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <6>; }; - aes2_ick: clock-aes2-ick { + aes2_ick: clock-aes2-ick@28 { + reg = <28>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "aes2_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <28>; }; - sha12_ick: clock-sha12-ick { + sha12_ick: clock-sha12-ick@27 { + reg = <27>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "sha12_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <27>; }; }; @@ -1136,30 +1152,31 @@ compatible = "ti,clksel"; reg = <0xc00>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - gpt1_gate_fck: clock-gpt1-gate-fck { + gpt1_gate_fck: clock-gpt1-gate-fck@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "gpt1_gate_fck"; clocks = <&sys_ck>; - ti,bit-shift = <0>; }; - gpio1_dbck: clock-gpio1-dbck { + gpio1_dbck: clock-gpio1-dbck@3 { + reg = <3>; #clock-cells = <0>; compatible = "ti,gate-clock"; clock-output-names = "gpio1_dbck"; clocks = <&wkup_32k_fck>; - ti,bit-shift = <3>; }; - wdt2_fck: clock-wdt2-fck { + wdt2_fck: clock-wdt2-fck@5 { + reg = <5>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "wdt2_fck"; clocks = <&wkup_32k_fck>; - ti,bit-shift = <5>; }; }; @@ -1182,54 +1199,55 @@ compatible = "ti,clksel"; reg = <0xc10>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - wdt2_ick: clock-wdt2-ick { + wdt2_ick: clock-wdt2-ick@5 { + reg = <5>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "wdt2_ick"; clocks = <&wkup_l4_ick>; - ti,bit-shift = <5>; }; - wdt1_ick: clock-wdt1-ick { + wdt1_ick: clock-wdt1-ick@4 { + reg = <4>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "wdt1_ick"; clocks = <&wkup_l4_ick>; - ti,bit-shift = <4>; }; - gpio1_ick: clock-gpio1-ick { + gpio1_ick: clock-gpio1-ick@3 { + reg = <3>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpio1_ick"; clocks = <&wkup_l4_ick>; - ti,bit-shift = <3>; }; - omap_32ksync_ick: clock-omap-32ksync-ick { + omap_32ksync_ick: clock-omap-32ksync-ick@2 { + reg = <2>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "omap_32ksync_ick"; clocks = <&wkup_l4_ick>; - ti,bit-shift = <2>; }; - gpt12_ick: clock-gpt12-ick { + gpt12_ick: clock-gpt12-ick@1 { + reg = <1>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpt12_ick"; clocks = <&wkup_l4_ick>; - ti,bit-shift = <1>; }; - gpt1_ick: clock-gpt1-ick { + gpt1_ick: clock-gpt1-ick@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpt1_ick"; clocks = <&wkup_l4_ick>; - ti,bit-shift = <0>; }; }; @@ -1254,150 +1272,151 @@ compatible = "ti,clksel"; reg = <0x1000>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - uart3_fck: clock-uart3-fck { + uart3_fck: clock-uart3-fck@11 { + reg = <11>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "uart3_fck"; clocks = <&per_48m_fck>; - ti,bit-shift = <11>; }; - gpt2_gate_fck: clock-gpt2-gate-fck { + gpt2_gate_fck: clock-gpt2-gate-fck@3 { + reg = <3>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "gpt2_gate_fck"; clocks = <&sys_ck>; - ti,bit-shift = <3>; }; - gpt3_gate_fck: clock-gpt3-gate-fck { + gpt3_gate_fck: clock-gpt3-gate-fck@4 { + reg = <4>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "gpt3_gate_fck"; clocks = <&sys_ck>; - ti,bit-shift = <4>; }; - gpt4_gate_fck: clock-gpt4-gate-fck { + gpt4_gate_fck: clock-gpt4-gate-fck@5 { + reg = <5>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "gpt4_gate_fck"; clocks = <&sys_ck>; - ti,bit-shift = <5>; }; - gpt5_gate_fck: clock-gpt5-gate-fck { + gpt5_gate_fck: clock-gpt5-gate-fck@6 { + reg = <6>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "gpt5_gate_fck"; clocks = <&sys_ck>; - ti,bit-shift = <6>; }; - gpt6_gate_fck: clock-gpt6-gate-fck { + gpt6_gate_fck: clock-gpt6-gate-fck@7 { + reg = <7>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "gpt6_gate_fck"; clocks = <&sys_ck>; - ti,bit-shift = <7>; }; - gpt7_gate_fck: clock-gpt7-gate-fck { + gpt7_gate_fck: clock-gpt7-gate-fck@8 { + reg = <8>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "gpt7_gate_fck"; clocks = <&sys_ck>; - ti,bit-shift = <8>; }; - gpt8_gate_fck: clock-gpt8-gate-fck { + gpt8_gate_fck: clock-gpt8-gate-fck@9 { + reg = <9>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "gpt8_gate_fck"; clocks = <&sys_ck>; - ti,bit-shift = <9>; }; - gpt9_gate_fck: clock-gpt9-gate-fck { + gpt9_gate_fck: clock-gpt9-gate-fck@10 { + reg = <10>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "gpt9_gate_fck"; clocks = <&sys_ck>; - ti,bit-shift = <10>; }; - gpio6_dbck: clock-gpio6-dbck { + gpio6_dbck: clock-gpio6-dbck@17 { + reg = <17>; #clock-cells = <0>; compatible = "ti,gate-clock"; clock-output-names = "gpio6_dbck"; clocks = <&per_32k_alwon_fck>; - ti,bit-shift = <17>; }; - gpio5_dbck: clock-gpio5-dbck { + gpio5_dbck: clock-gpio5-dbck@16 { + reg = <16>; #clock-cells = <0>; compatible = "ti,gate-clock"; clock-output-names = "gpio5_dbck"; clocks = <&per_32k_alwon_fck>; - ti,bit-shift = <16>; }; - gpio4_dbck: clock-gpio4-dbck { + gpio4_dbck: clock-gpio4-dbck@15 { + reg = <15>; #clock-cells = <0>; compatible = "ti,gate-clock"; clock-output-names = "gpio4_dbck"; clocks = <&per_32k_alwon_fck>; - ti,bit-shift = <15>; }; - gpio3_dbck: clock-gpio3-dbck { + gpio3_dbck: clock-gpio3-dbck@14 { + reg = <14>; #clock-cells = <0>; compatible = "ti,gate-clock"; clock-output-names = "gpio3_dbck"; clocks = <&per_32k_alwon_fck>; - ti,bit-shift = <14>; }; - gpio2_dbck: clock-gpio2-dbck { + gpio2_dbck: clock-gpio2-dbck@13 { + reg = <13>; #clock-cells = <0>; compatible = "ti,gate-clock"; clock-output-names = "gpio2_dbck"; clocks = <&per_32k_alwon_fck>; - ti,bit-shift = <13>; }; - wdt3_fck: clock-wdt3-fck { + wdt3_fck: clock-wdt3-fck@12 { + reg = <12>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "wdt3_fck"; clocks = <&per_32k_alwon_fck>; - ti,bit-shift = <12>; }; - mcbsp2_gate_fck: clock-mcbsp2-gate-fck { + mcbsp2_gate_fck: clock-mcbsp2-gate-fck@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "mcbsp2_gate_fck"; clocks = <&mcbsp_clks>; - ti,bit-shift = <0>; }; - mcbsp3_gate_fck: clock-mcbsp3-gate-fck { + mcbsp3_gate_fck: clock-mcbsp3-gate-fck@1 { + reg = <1>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "mcbsp3_gate_fck"; clocks = <&mcbsp_clks>; - ti,bit-shift = <1>; }; - mcbsp4_gate_fck: clock-mcbsp4-gate-fck { + mcbsp4_gate_fck: clock-mcbsp4-gate-fck@2 { + reg = <2>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "mcbsp4_gate_fck"; clocks = <&mcbsp_clks>; - ti,bit-shift = <2>; }; }; @@ -1406,69 +1425,71 @@ compatible = "ti,clksel"; reg = <0x1040>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - gpt2_mux_fck: clock-gpt2-mux-fck { + gpt2_mux_fck: clock-gpt2-mux-fck@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "gpt2_mux_fck"; clocks = <&omap_32k_fck>, <&sys_ck>; }; - gpt3_mux_fck: clock-gpt3-mux-fck { + gpt3_mux_fck: clock-gpt3-mux-fck@1 { + reg = <1>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "gpt3_mux_fck"; clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <1>; }; - gpt4_mux_fck: clock-gpt4-mux-fck { + gpt4_mux_fck: clock-gpt4-mux-fck@2 { + reg = <2>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "gpt4_mux_fck"; clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <2>; }; - gpt5_mux_fck: clock-gpt5-mux-fck { + gpt5_mux_fck: clock-gpt5-mux-fck@3 { + reg = <3>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "gpt5_mux_fck"; clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <3>; }; - gpt6_mux_fck: clock-gpt6-mux-fck { + gpt6_mux_fck: clock-gpt6-mux-fck@4 { + reg = <4>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "gpt6_mux_fck"; clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <4>; }; - gpt7_mux_fck: clock-gpt7-mux-fck { + gpt7_mux_fck: clock-gpt7-mux-fck@5 { + reg = <5>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "gpt7_mux_fck"; clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <5>; }; - gpt8_mux_fck: clock-gpt8-mux-fck { + gpt8_mux_fck: clock-gpt8-mux-fck@6 { + reg = <6>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "gpt8_mux_fck"; clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <6>; }; - gpt9_mux_fck: clock-gpt9-mux-fck { + gpt9_mux_fck: clock-gpt9-mux-fck@7 { + reg = <7>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "gpt9_mux_fck"; clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <7>; }; }; @@ -1541,158 +1562,159 @@ compatible = "ti,clksel"; reg = <0x1010>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - gpio6_ick: clock-gpio6-ick { + gpio6_ick: clock-gpio6-ick@17 { + reg = <17>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpio6_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <17>; }; - gpio5_ick: clock-gpio5-ick { + gpio5_ick: clock-gpio5-ick@16 { + reg = <16>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpio5_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <16>; }; - gpio4_ick: clock-gpio4-ick { + gpio4_ick: clock-gpio4-ick@15 { + reg = <15>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpio4_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <15>; }; - gpio3_ick: clock-gpio3-ick { + gpio3_ick: clock-gpio3-ick@14 { + reg = <14>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpio3_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <14>; }; - gpio2_ick: clock-gpio2-ick { + gpio2_ick: clock-gpio2-ick@13 { + reg = <13>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpio2_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <13>; }; - wdt3_ick: clock-wdt3-ick { + wdt3_ick: clock-wdt3-ick@12 { + reg = <12>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "wdt3_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <12>; }; - uart3_ick: clock-uart3-ick { + uart3_ick: clock-uart3-ick@11 { + reg = <11>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "uart3_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <11>; }; - uart4_ick: clock-uart4-ick { + uart4_ick: clock-uart4-ick@18 { + reg = <18>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "uart4_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <18>; }; - gpt9_ick: clock-gpt9-ick { + gpt9_ick: clock-gpt9-ick@10 { + reg = <10>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpt9_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <10>; }; - gpt8_ick: clock-gpt8-ick { + gpt8_ick: clock-gpt8-ick@9 { + reg = <9>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpt8_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <9>; }; - gpt7_ick: clock-gpt7-ick { + gpt7_ick: clock-gpt7-ick@8 { + reg = <8>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpt7_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <8>; }; - gpt6_ick: clock-gpt6-ick { + gpt6_ick: clock-gpt6-ick@7 { + reg = <7>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpt6_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <7>; }; - gpt5_ick: clock-gpt5-ick { + gpt5_ick: clock-gpt5-ick@6 { + reg = <6>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpt5_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <6>; }; - gpt4_ick: clock-gpt4-ick { + gpt4_ick: clock-gpt4-ick@5 { + reg = <5>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpt4_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <5>; }; - gpt3_ick: clock-gpt3-ick { + gpt3_ick: clock-gpt3-ick@4 { + reg = <4>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpt3_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <4>; }; - gpt2_ick: clock-gpt2-ick { + gpt2_ick: clock-gpt2-ick@3 { + reg = <3>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpt2_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <3>; }; - mcbsp2_ick: clock-mcbsp2-ick { + mcbsp2_ick: clock-mcbsp2-ick@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mcbsp2_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <0>; }; - mcbsp3_ick: clock-mcbsp3-ick { + mcbsp3_ick: clock-mcbsp3-ick@1 { + reg = <1>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mcbsp3_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <1>; }; - mcbsp4_ick: clock-mcbsp4-ick { + mcbsp4_ick: clock-mcbsp4-ick@2 { + reg = <2>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mcbsp4_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <2>; }; }; diff --git a/src/arm/ti/omap/omap4-epson-embt2ws.dts b/src/arm/ti/omap/omap4-epson-embt2ws.dts index 24f7d0285f7..339e52ba361 100644 --- a/src/arm/ti/omap/omap4-epson-embt2ws.dts +++ b/src/arm/ti/omap/omap4-epson-embt2ws.dts @@ -85,6 +85,7 @@ interrupts = ; /* IRQ_SYS_1N cascaded to gic */ interrupt-controller; #interrupt-cells = <1>; + system-power-controller; rtc { compatible = "ti,twl4030-rtc"; diff --git a/src/arm/ti/omap/omap4-panda-common.dtsi b/src/arm/ti/omap/omap4-panda-common.dtsi index f528511c253..97706d6296a 100644 --- a/src/arm/ti/omap/omap4-panda-common.dtsi +++ b/src/arm/ti/omap/omap4-panda-common.dtsi @@ -408,6 +408,7 @@ reg = <0x48>; /* IRQ# = 7 */ interrupts = ; /* IRQ_SYS_1N cascaded to gic */ + system-power-controller; }; twl6040: twl@4b { diff --git a/src/arm/ti/omap/omap4-sdp.dts b/src/arm/ti/omap/omap4-sdp.dts index b2cb93edbc3..b535d24c614 100644 --- a/src/arm/ti/omap/omap4-sdp.dts +++ b/src/arm/ti/omap/omap4-sdp.dts @@ -439,7 +439,7 @@ /* * Ambient Light Sensor - * http://www.rohm.com/products/databook/sensor/pdf/bh1780gli-e.pdf + * https://www.rohm.com/products/databook/sensor/pdf/bh1780gli-e.pdf (defunct) */ bh1780@29 { compatible = "rohm,bh1780"; diff --git a/src/arm/ti/omap/omap4.dtsi b/src/arm/ti/omap/omap4.dtsi index 2bbff9032be..559b2bfe4ca 100644 --- a/src/arm/ti/omap/omap4.dtsi +++ b/src/arm/ti/omap/omap4.dtsi @@ -501,10 +501,11 @@ #size-cells = <1>; ranges = <0 0x56000000 0x2000000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + gpu@0 { + compatible = "ti,omap4430-gpu", "img,powervr-sgx540"; + reg = <0x0 0x2000000>; /* 32MB */ + interrupts = ; + }; }; /* diff --git a/src/arm/ti/omap/omap5-igep0050.dts b/src/arm/ti/omap/omap5-igep0050.dts index d4ca2e3a14d..0368e32f67e 100644 --- a/src/arm/ti/omap/omap5-igep0050.dts +++ b/src/arm/ti/omap/omap5-igep0050.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz/ + * Copyright (C) 2013 ISEE 2007 SL - https://www.isee.biz/ */ /dts-v1/; diff --git a/src/arm/ti/omap/omap5.dtsi b/src/arm/ti/omap/omap5.dtsi index bac6fa83879..6a66214ad0e 100644 --- a/src/arm/ti/omap/omap5.dtsi +++ b/src/arm/ti/omap/omap5.dtsi @@ -453,10 +453,11 @@ #size-cells = <1>; ranges = <0 0x56000000 0x2000000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + gpu@0 { + compatible = "ti,omap5432-gpu", "img,powervr-sgx544"; + reg = <0x0 0x2000000>; /* 32MB */ + interrupts = ; + }; }; target-module@58000000 { diff --git a/src/arm/ti/omap/twl4030.dtsi b/src/arm/ti/omap/twl4030.dtsi index 93e07c18781..a5d9c573831 100644 --- a/src/arm/ti/omap/twl4030.dtsi +++ b/src/arm/ti/omap/twl4030.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ /* diff --git a/src/arm/ti/omap/twl6030.dtsi b/src/arm/ti/omap/twl6030.dtsi index 9d588cfaa5c..8da969035c4 100644 --- a/src/arm/ti/omap/twl6030.dtsi +++ b/src/arm/ti/omap/twl6030.dtsi @@ -1,11 +1,11 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ /* * Integrated Power Management Chip - * http://www.ti.com/lit/ds/symlink/twl6030.pdf + * https://www.ti.com/lit/ds/symlink/twl6030.pdf */ &twl { compatible = "ti,twl6030"; diff --git a/src/arm64/allwinner/sun50i-h6-beelink-gs1.dts b/src/arm64/allwinner/sun50i-h6-beelink-gs1.dts index 9ec49ac2f6f..381d58cea09 100644 --- a/src/arm64/allwinner/sun50i-h6-beelink-gs1.dts +++ b/src/arm64/allwinner/sun50i-h6-beelink-gs1.dts @@ -291,6 +291,8 @@ }; &spdif { + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pin>; status = "okay"; }; diff --git a/src/arm64/allwinner/sun50i-h6-tanix.dtsi b/src/arm64/allwinner/sun50i-h6-tanix.dtsi index 4903d635811..855b7d43bc5 100644 --- a/src/arm64/allwinner/sun50i-h6-tanix.dtsi +++ b/src/arm64/allwinner/sun50i-h6-tanix.dtsi @@ -166,6 +166,8 @@ }; &spdif { + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pin>; status = "okay"; }; diff --git a/src/arm64/allwinner/sun50i-h6.dtsi b/src/arm64/allwinner/sun50i-h6.dtsi index ca1d287a0a0..d11e5041bae 100644 --- a/src/arm64/allwinner/sun50i-h6.dtsi +++ b/src/arm64/allwinner/sun50i-h6.dtsi @@ -406,6 +406,7 @@ function = "spi1"; }; + /omit-if-no-ref/ spdif_tx_pin: spdif-tx-pin { pins = "PH7"; function = "spdif"; @@ -655,10 +656,8 @@ clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; clock-names = "apb", "spdif"; resets = <&ccu RST_BUS_SPDIF>; - dmas = <&dma 2>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; + dmas = <&dma 2>, <&dma 2>; + dma-names = "rx", "tx"; status = "disabled"; }; diff --git a/src/arm64/allwinner/sun50i-h616-bigtreetech-cb1-manta.dts b/src/arm64/allwinner/sun50i-h616-bigtreetech-cb1-manta.dts index dbce61b355d..4bfb52609c9 100644 --- a/src/arm64/allwinner/sun50i-h616-bigtreetech-cb1-manta.dts +++ b/src/arm64/allwinner/sun50i-h616-bigtreetech-cb1-manta.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (C) 2023 Martin Botka . */ diff --git a/src/arm64/allwinner/sun50i-h616-bigtreetech-cb1.dtsi b/src/arm64/allwinner/sun50i-h616-bigtreetech-cb1.dtsi index 1fed2b46cfe..af421ba24ce 100644 --- a/src/arm64/allwinner/sun50i-h616-bigtreetech-cb1.dtsi +++ b/src/arm64/allwinner/sun50i-h616-bigtreetech-cb1.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (C) 2023 Martin Botka . */ @@ -93,7 +93,7 @@ interrupt-controller; #interrupt-cells = <1>; - regulators{ + regulators { reg_dcdc1: dcdc1 { regulator-name = "vdd-gpu-sys"; regulator-min-microvolt = <810000>; diff --git a/src/arm64/allwinner/sun50i-h616-bigtreetech-pi.dts b/src/arm64/allwinner/sun50i-h616-bigtreetech-pi.dts index 832f08b2b26..ff84a379447 100644 --- a/src/arm64/allwinner/sun50i-h616-bigtreetech-pi.dts +++ b/src/arm64/allwinner/sun50i-h616-bigtreetech-pi.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (C) 2023 Martin Botka . */ diff --git a/src/arm64/allwinner/sun50i-h616.dtsi b/src/arm64/allwinner/sun50i-h616.dtsi index d549d277d97..b2e85e52d1a 100644 --- a/src/arm64/allwinner/sun50i-h616.dtsi +++ b/src/arm64/allwinner/sun50i-h616.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include / { interrupt-parent = <&gic>; @@ -133,11 +134,28 @@ #reset-cells = <1>; }; + dma: dma-controller@3002000 { + compatible = "allwinner,sun50i-h616-dma", + "allwinner,sun50i-a100-dma"; + reg = <0x03002000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; + clock-names = "bus", "mbus"; + dma-channels = <16>; + dma-requests = <49>; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + }; + sid: efuse@3006000 { compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid"; reg = <0x03006000 0x1000>; #address-cells = <1>; #size-cells = <1>; + + ths_calibration: thermal-sensor-calibration@14 { + reg = <0x14 0x8>; + }; }; watchdog: watchdog@30090a0 { @@ -240,6 +258,11 @@ function = "spi1"; }; + spdif_tx_pin: spdif-tx-pin { + pins = "PH4"; + function = "spdif"; + }; + uart0_ph_pins: uart0-ph-pins { pins = "PH0", "PH1"; function = "uart0"; @@ -256,6 +279,12 @@ pins = "PG8", "PG9"; function = "uart1"; }; + + /omit-if-no-ref/ + x32clk_fanout_pin: x32clk-fanout-pin { + pins = "PG10"; + function = "clock"; + }; }; gic: interrupt-controller@3021000 { @@ -339,6 +368,8 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART0>; + dmas = <&dma 14>, <&dma 14>; + dma-names = "tx", "rx"; resets = <&ccu RST_BUS_UART0>; status = "disabled"; }; @@ -350,6 +381,8 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART1>; + dmas = <&dma 15>, <&dma 15>; + dma-names = "tx", "rx"; resets = <&ccu RST_BUS_UART1>; status = "disabled"; }; @@ -361,6 +394,8 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART2>; + dmas = <&dma 16>, <&dma 16>; + dma-names = "tx", "rx"; resets = <&ccu RST_BUS_UART2>; status = "disabled"; }; @@ -372,6 +407,8 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART3>; + dmas = <&dma 17>, <&dma 17>; + dma-names = "tx", "rx"; resets = <&ccu RST_BUS_UART3>; status = "disabled"; }; @@ -383,6 +420,8 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART4>; + dmas = <&dma 18>, <&dma 18>; + dma-names = "tx", "rx"; resets = <&ccu RST_BUS_UART4>; status = "disabled"; }; @@ -394,6 +433,8 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART5>; + dmas = <&dma 19>, <&dma 19>; + dma-names = "tx", "rx"; resets = <&ccu RST_BUS_UART5>; status = "disabled"; }; @@ -405,6 +446,8 @@ reg = <0x05002000 0x400>; interrupts = ; clocks = <&ccu CLK_BUS_I2C0>; + dmas = <&dma 43>, <&dma 43>; + dma-names = "rx", "tx"; resets = <&ccu RST_BUS_I2C0>; pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; @@ -420,6 +463,8 @@ reg = <0x05002400 0x400>; interrupts = ; clocks = <&ccu CLK_BUS_I2C1>; + dmas = <&dma 44>, <&dma 44>; + dma-names = "rx", "tx"; resets = <&ccu RST_BUS_I2C1>; status = "disabled"; #address-cells = <1>; @@ -433,6 +478,8 @@ reg = <0x05002800 0x400>; interrupts = ; clocks = <&ccu CLK_BUS_I2C2>; + dmas = <&dma 45>, <&dma 45>; + dma-names = "rx", "tx"; resets = <&ccu RST_BUS_I2C2>; status = "disabled"; #address-cells = <1>; @@ -446,6 +493,8 @@ reg = <0x05002c00 0x400>; interrupts = ; clocks = <&ccu CLK_BUS_I2C3>; + dmas = <&dma 46>, <&dma 46>; + dma-names = "rx", "tx"; resets = <&ccu RST_BUS_I2C3>; status = "disabled"; #address-cells = <1>; @@ -459,6 +508,8 @@ reg = <0x05003000 0x400>; interrupts = ; clocks = <&ccu CLK_BUS_I2C4>; + dmas = <&dma 47>, <&dma 47>; + dma-names = "rx", "tx"; resets = <&ccu RST_BUS_I2C4>; status = "disabled"; #address-cells = <1>; @@ -472,6 +523,8 @@ interrupts = ; clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; clock-names = "ahb", "mod"; + dmas = <&dma 22>, <&dma 22>; + dma-names = "rx", "tx"; resets = <&ccu RST_BUS_SPI0>; status = "disabled"; #address-cells = <1>; @@ -485,6 +538,8 @@ interrupts = ; clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; resets = <&ccu RST_BUS_SPI1>; status = "disabled"; #address-cells = <1>; @@ -511,6 +566,34 @@ }; }; + spdif: spdif@5093000 { + compatible = "allwinner,sun50i-h616-spdif"; + reg = <0x05093000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; + clock-names = "apb", "spdif"; + resets = <&ccu RST_BUS_SPDIF>; + dmas = <&dma 2>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pin>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ths: thermal-sensor@5070400 { + compatible = "allwinner,sun50i-h616-ths"; + reg = <0x05070400 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_THS>; + clock-names = "bus"; + resets = <&ccu RST_BUS_THS>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + allwinner,sram = <&syscon>; + #thermal-sensor-cells = <1>; + }; + usbotg: usb@5100000 { compatible = "allwinner,sun50i-h616-musb", "allwinner,sun8i-h3-musb"; @@ -734,6 +817,8 @@ reg = <0x07081400 0x400>; interrupts = ; clocks = <&r_ccu CLK_R_APB2_I2C>; + dmas = <&dma 48>, <&dma 48>; + dma-names = "rx", "tx"; resets = <&r_ccu RST_R_APB2_I2C>; status = "disabled"; #address-cells = <1>; @@ -755,4 +840,74 @@ #size-cells = <0>; }; }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <500>; + polling-delay = <1000>; + thermal-sensors = <&ths 2>; + sustainable-power = <1000>; + + trips { + cpu_threshold: cpu-trip-0 { + temperature = <60000>; + type = "passive"; + hysteresis = <0>; + }; + cpu_target: cpu-trip-1 { + temperature = <70000>; + type = "passive"; + hysteresis = <0>; + }; + cpu_critical: cpu-trip-2 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <500>; + polling-delay = <1000>; + thermal-sensors = <&ths 0>; + sustainable-power = <1100>; + + trips { + gpu_temp_critical: gpu-trip-0 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + }; + + ve-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 1>; + + trips { + ve_temp_critical: ve-trip-0 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + }; + + ddr-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 3>; + + trips { + ddr_temp_critical: ddr-trip-0 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + }; + }; }; diff --git a/src/arm64/allwinner/sun50i-h618-longan-module-3h.dtsi b/src/arm64/allwinner/sun50i-h618-longan-module-3h.dtsi new file mode 100644 index 00000000000..8c1263a3939 --- /dev/null +++ b/src/arm64/allwinner/sun50i-h618-longan-module-3h.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) Jisheng Zhang + */ + +#include "sun50i-h616.dtsi" + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_aldo1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + status = "okay"; +}; + +&r_i2c { + status = "okay"; + + axp313: pmic@36 { + compatible = "x-powers,axp313a"; + reg = <0x36>; + #interrupt-cells = <1>; + interrupt-controller; + + regulators { + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-1v8-pll"; + }; + + reg_dldo1: dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3-io"; + }; + + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <990000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-dram"; + }; + }; + }; +}; + +&pio { + vcc-pc-supply = <®_dldo1>; + vcc-pf-supply = <®_dldo1>; + vcc-pg-supply = <®_aldo1>; + vcc-ph-supply = <®_dldo1>; + vcc-pi-supply = <®_dldo1>; +}; diff --git a/src/arm64/allwinner/sun50i-h618-longanpi-3h.dts b/src/arm64/allwinner/sun50i-h618-longanpi-3h.dts new file mode 100644 index 00000000000..18b29c6b867 --- /dev/null +++ b/src/arm64/allwinner/sun50i-h618-longanpi-3h.dts @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) Jisheng Zhang + */ + +/dts-v1/; + +#include "sun50i-h618-longan-module-3h.dtsi" + +#include +#include +#include + +/ { + model = "Sipeed Longan Pi 3H"; + compatible = "sipeed,longan-pi-3h", "sipeed,longan-module-3h", "allwinner,sun50i-h618"; + + aliases { + ethernet0 = &emac0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <0>; + gpios = <&pio 6 2 GPIO_ACTIVE_LOW>; /* PG2 */ + }; + + led-1 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + gpios = <&pio 6 4 GPIO_ACTIVE_LOW>; /* PG4 */ + }; + }; + + reg_vcc5v: regulator-vcc5v { + /* board wide 5V supply directly from the USB-C socket */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_vcc3v3: regulator-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_vcc5v>; + }; +}; + +&axp313 { + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; +}; + +&ehci1 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +/* WiFi & BT combo module is connected to this Host */ +&ehci3 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&emac0 { + pinctrl-names = "default"; + pinctrl-0 = <&ext_rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + allwinner,rx-delay-ps = <3100>; + allwinner,tx-delay-ps = <700>; + phy-supply = <®_vcc3v3>; + status = "okay"; +}; + +&mdio0 { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mmc0 { + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + vmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usbotg { + /* + * PHY0 pins are connected to a USB-C socket, but a role switch + * is not implemented: both CC pins are pulled to GND. + * The VBUS pins power the device, so a fixed peripheral mode + * is the best choice. + * The board can be powered via GPIOs, in this case port0 *can* + * act as a host (with a cable/adapter ignoring CC), as VBUS is + * then provided by the GPIOs. Any user of this setup would + * need to adjust the DT accordingly: dr_mode set to "host", + * enabling OHCI0 and EHCI0. + */ + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_vcc5v>; + usb2_vbus-supply = <®_vcc5v>; + status = "okay"; +}; diff --git a/src/arm64/allwinner/sun50i-h618-transpeed-8k618-t.dts b/src/arm64/allwinner/sun50i-h618-transpeed-8k618-t.dts index 8ea1fd41aeb..ac0a2b7ea6f 100644 --- a/src/arm64/allwinner/sun50i-h618-transpeed-8k618-t.dts +++ b/src/arm64/allwinner/sun50i-h618-transpeed-8k618-t.dts @@ -15,6 +15,7 @@ compatible = "transpeed,8k618-t", "allwinner,sun50i-h618"; aliases { + ethernet1 = &sdio_wifi; serial0 = &uart0; }; @@ -39,6 +40,15 @@ regulator-max-microvolt = <3300000>; regulator-always-on; }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "ext_clock"; + pinctrl-0 = <&x32clk_fanout_pin>; + pinctrl-names = "default"; + reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ + }; }; &ehci0 { @@ -60,6 +70,19 @@ status = "okay"; }; +&mmc1 { + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_aldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + sdio_wifi: wifi@1 { + reg = <1>; + }; +}; + &mmc2 { vmmc-supply = <®_dldo1>; vqmmc-supply = <®_aldo1>; diff --git a/src/arm64/allwinner/sun50i-h64-remix-mini-pc.dts b/src/arm64/allwinner/sun50i-h64-remix-mini-pc.dts new file mode 100644 index 00000000000..b6e3c169797 --- /dev/null +++ b/src/arm64/allwinner/sun50i-h64-remix-mini-pc.dts @@ -0,0 +1,356 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2023 ARM Ltd. + +/dts-v1/; + +#include "sun50i-a64.dtsi" +#include "sun50i-a64-cpu-opp.dtsi" + +#include + +/ { + model = "Remix Mini PC"; + compatible = "jide,remix-mini-pc", "allwinner,sun50i-h64", + "allwinner,sun50i-a64"; + + aliases { + ethernet1 = &rtl8723bs; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + reg_vcc5v: regulator-5v { + /* board wide 5V supply directly from the DC input */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ + post-power-on-delay-ms = <200>; + }; +}; + +&codec { + status = "okay"; +}; + +&codec_analog { + cpvdd-supply = <®_eldo1>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu1 { + cpu-supply = <®_dcdc2>; +}; + +&cpu2 { + cpu-supply = <®_dcdc2>; +}; + +&cpu3 { + cpu-supply = <®_dcdc2>; +}; + +&dai { + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&hdmi { + hvcc-supply = <®_dldo1>; + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +/* Connects to the AC200 chip */ +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; +}; + +&i2c0_pins { + bias-pull-up; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_dcdc1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + disable-wp; + bus-width = <4>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <®_aldo1>; + vqmmc-supply = <®_dldo4>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8723bs: wifi@1 { + reg = <1>; + interrupt-parent = <&r_pio>; + interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */ + interrupt-names = "host-wake"; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>, <&mmc2_ds_pin>; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_eldo1>; + bus-width = <8>; + non-removable; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-hw-reset; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + vcc-pb-supply = <®_dcdc1>; + vcc-pc-supply = <®_dcdc1>; + vcc-pd-supply = <®_dcdc1>; + vcc-pe-supply = <®_dcdc1>; + vcc-pf-supply = <®_dcdc1>; + vcc-pg-supply = <®_dldo4>; + vcc-ph-supply = <®_dcdc1>; +}; + +&r_ir { + status = "okay"; +}; + +&r_pio { + /* + * We cannot add that supply for now since it would create a circular + * dependency between pinctrl, the regulator and the RSB Bus. + * + * vcc-pl-supply = <®_aldo2>; + */ +}; + +&r_rsb { + status = "okay"; + + axp803: pmic@3a3 { + compatible = "x-powers,axp803"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = ; + x-powers,drive-vbus-en; + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + vin5-supply = <®_vcc5v>; + vin6-supply = <®_vcc5v>; + aldoin-supply = <®_vcc5v>; + dldoin-supply = <®_vcc5v>; + eldoin-supply = <®_vcc5v>; + fldoin-supply = <®_vcc5v>; + drivevbus-supply = <®_vcc5v>; + ips-supply = <®_vcc5v>; + + status = "okay"; + }; +}; + +#include "axp803.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1040000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-cpux"; +}; + +/* DCDC3 is polyphased with DCDC2 */ + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +/* Deviates from the reset default of 1.1V. */ +®_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd-sys"; +}; + +®_aldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_aldo2 { + /* Specifying R_PIO consumer would create circular dependency. */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-pll-avcc"; +}; + +/* AC200 power supply */ +®_dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-ave-33"; +}; + +®_dldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-io"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +®_eldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-cpvdd-dram-emmc"; +}; + +/* Supplies the arisc management core, needed by TF-A to power off cores. */ +®_fldo2 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +&simplefb_hdmi { + vcc-hdmi-supply = <®_dcdc1>; +}; + +&sound { + simple-audio-card,aux-devs = <&codec_analog>; + simple-audio-card,widgets = "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Left DAC", "DACL", + "Right DAC", "DACR", + "Headphone Jack", "HP", + "ADCL", "Left ADC", + "ADCR", "Right ADC", + "MIC2", "Microphone Jack"; + status = "okay"; +}; + +/* On the (unpopulated) UART pads. */ +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8723bs-bt"; + enable-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ + max-speed = <1500000>; + }; +}; + +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + usb0_vbus-supply = <®_drivevbus>; + usb1_vbus-supply = <®_drivevbus>; + status = "okay"; +}; diff --git a/src/arm64/amlogic/amlogic-c3.dtsi b/src/arm64/amlogic/amlogic-c3.dtsi index 2ad1f8eef19..32a754fe799 100644 --- a/src/arm64/amlogic/amlogic-c3.dtsi +++ b/src/arm64/amlogic/amlogic-c3.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { cpus { @@ -81,6 +82,12 @@ #size-cells = <2>; ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + reset: reset-controller@2000 { + compatible = "amlogic,c3-reset"; + reg = <0x0 0x2000 0x0 0x98>; + #reset-cells = <1>; + }; + watchdog@2100 { compatible = "amlogic,c3-wdt", "amlogic,t7-wdt"; reg = <0x0 0x2100 0x0 0x10>; diff --git a/src/arm64/amlogic/amlogic-t7.dtsi b/src/arm64/amlogic/amlogic-t7.dtsi index a03c7667d2b..5248bdf824e 100644 --- a/src/arm64/amlogic/amlogic-t7.dtsi +++ b/src/arm64/amlogic/amlogic-t7.dtsi @@ -54,7 +54,7 @@ enable-method = "psci"; }; - cpu101: cpu@101{ + cpu101: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x101>; @@ -171,6 +171,16 @@ }; }; + gpio_intc: interrupt-controller@4080 { + compatible = "amlogic,t7-gpio-intc", + "amlogic,meson-gpio-intc"; + reg = <0x0 0x4080 0x0 0x20>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = + <10 11 12 13 14 15 16 17 18 19 20 21>; + }; + uart_a: serial@78000 { compatible = "amlogic,t7-uart", "amlogic,meson-s4-uart"; reg = <0x0 0x78000 0x0 0x18>; diff --git a/src/arm64/amlogic/meson-a1-ad402.dts b/src/arm64/amlogic/meson-a1-ad402.dts index 1c20516fa65..4bc30af0584 100644 --- a/src/arm64/amlogic/meson-a1-ad402.dts +++ b/src/arm64/amlogic/meson-a1-ad402.dts @@ -106,7 +106,7 @@ pinctrl-0 = <&spifc_pins>; pinctrl-names = "default"; - spi_nand@0 { + flash@0 { compatible = "spi-nand"; status = "okay"; reg = <0>; diff --git a/src/arm64/amlogic/meson-a1.dtsi b/src/arm64/amlogic/meson-a1.dtsi index 648e7f49424..c03e207ea6c 100644 --- a/src/arm64/amlogic/meson-a1.dtsi +++ b/src/arm64/amlogic/meson-a1.dtsi @@ -450,6 +450,8 @@ <&clkc_periphs CLKID_USB_BUS>, <&clkc_periphs CLKID_USB_CTRL_IN>; clock-names = "usb_ctrl", "usb_bus", "xtal_usb_ctrl"; + assigned-clocks = <&clkc_periphs CLKID_USB_BUS>; + assigned-clock-rates = <64000000>; resets = <&reset RESET_USBCTRL>; reset-name = "usb_ctrl"; diff --git a/src/arm64/amlogic/meson-axg-jethome-jethub-j1xx.dtsi b/src/arm64/amlogic/meson-axg-jethome-jethub-j1xx.dtsi index db605f3a22b..9b65ae818e2 100644 --- a/src/arm64/amlogic/meson-axg-jethome-jethub-j1xx.dtsi +++ b/src/arm64/amlogic/meson-axg-jethome-jethub-j1xx.dtsi @@ -35,7 +35,7 @@ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; @@ -44,7 +44,7 @@ regulator-always-on; }; - vcc_5v: regulator-vcc_5v { + vcc_5v: regulator-vcc-5v { compatible = "regulator-fixed"; regulator-name = "VCC5V"; regulator-min-microvolt = <5000000>; @@ -52,7 +52,7 @@ regulator-always-on; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; @@ -61,7 +61,7 @@ regulator-always-on; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; @@ -70,7 +70,7 @@ regulator-always-on; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <3300000>; @@ -79,7 +79,7 @@ regulator-always-on; }; - vccq_1v8: regulator-vccq_1v8 { + vccq_1v8: regulator-vccq-1v8 { compatible = "regulator-fixed"; regulator-name = "VCCQ_1V8"; regulator-min-microvolt = <1800000>; @@ -88,7 +88,7 @@ regulator-always-on; }; - usb_pwr: regulator-usb_pwr { + usb_pwr: regulator-usb-pwr { compatible = "regulator-fixed"; regulator-name = "USB_PWR"; regulator-min-microvolt = <5000000>; @@ -332,19 +332,3 @@ "", "", "", "", "", // 80 - 84 "", ""; // 85-86 }; - -&cpu0 { - #cooling-cells = <2>; -}; - -&cpu1 { - #cooling-cells = <2>; -}; - -&cpu2 { - #cooling-cells = <2>; -}; - -&cpu3 { - #cooling-cells = <2>; -}; diff --git a/src/arm64/amlogic/meson-axg-s400.dts b/src/arm64/amlogic/meson-axg-s400.dts index c8905663bc7..7ed526f4517 100644 --- a/src/arm64/amlogic/meson-axg-s400.dts +++ b/src/arm64/amlogic/meson-axg-s400.dts @@ -12,7 +12,7 @@ compatible = "amlogic,s400", "amlogic,a113d", "amlogic,meson-axg"; model = "Amlogic Meson AXG S400 Development Board"; - adc_keys { + keys { compatible = "adc-keys"; io-channels = <&saradc 0>; io-channel-names = "buttons"; @@ -111,7 +111,7 @@ reg = <0x0 0x0 0x0 0x40000000>; }; - main_12v: regulator-main_12v { + main_12v: regulator-main-12v { compatible = "regulator-fixed"; regulator-name = "12V"; regulator-min-microvolt = <12000000>; @@ -119,7 +119,7 @@ regulator-always-on; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; @@ -128,7 +128,7 @@ regulator-always-on; }; - vcc_5v: regulator-vcc_5v { + vcc_5v: regulator-vcc-5v { compatible = "regulator-fixed"; regulator-name = "VCC5V"; regulator-min-microvolt = <5000000>; @@ -139,7 +139,7 @@ enable-active-high; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; @@ -148,7 +148,7 @@ regulator-always-on; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; @@ -157,7 +157,7 @@ regulator-always-on; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; @@ -166,7 +166,7 @@ regulator-always-on; }; - usb_pwr: regulator-usb_pwr { + usb_pwr: regulator-usb-pwr { compatible = "regulator-fixed"; regulator-name = "USB_PWR"; regulator-min-microvolt = <5000000>; diff --git a/src/arm64/amlogic/meson-axg.dtsi b/src/arm64/amlogic/meson-axg.dtsi index 7e5ac9db93f..6d12b760b90 100644 --- a/src/arm64/amlogic/meson-axg.dtsi +++ b/src/arm64/amlogic/meson-axg.dtsi @@ -74,6 +74,8 @@ enable-method = "psci"; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; + dynamic-power-coefficient = <140>; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -83,6 +85,8 @@ enable-method = "psci"; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; + dynamic-power-coefficient = <140>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -92,6 +96,8 @@ enable-method = "psci"; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; + dynamic-power-coefficient = <140>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -101,6 +107,8 @@ enable-method = "psci"; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; + dynamic-power-coefficient = <140>; + #cooling-cells = <2>; }; l2: l2-cache0 { diff --git a/src/arm64/amlogic/meson-g12-common.dtsi b/src/arm64/amlogic/meson-g12-common.dtsi index ff68b911b72..9d5eab6595d 100644 --- a/src/arm64/amlogic/meson-g12-common.dtsi +++ b/src/arm64/amlogic/meson-g12-common.dtsi @@ -2502,6 +2502,9 @@ clocks = <&clkc CLKID_NNA_CORE_CLK>, <&clkc CLKID_NNA_AXI_CLK>; clock-names = "core", "bus"; + assigned-clocks = <&clkc CLKID_NNA_CORE_CLK>, + <&clkc CLKID_NNA_AXI_CLK>; + assigned-clock-rates = <800000000>, <800000000>; resets = <&reset RESET_NNA>; status = "disabled"; }; diff --git a/src/arm64/amlogic/meson-g12a-fbx8am-brcm.dtso b/src/arm64/amlogic/meson-g12a-fbx8am-brcm.dtso new file mode 100644 index 00000000000..9591fdc31ee --- /dev/null +++ b/src/arm64/amlogic/meson-g12a-fbx8am-brcm.dtso @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2024 Freebox SAS + +/dts-v1/; +/plugin/; + +#include +#include + +&uart_A { + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + max-speed = <2000000>; + clocks = <&wifi32k>; + clock-names = "lpo"; + vbat-supply = <&vddao_3v3>; + vddio-supply = <&vddio_ao1v8>; + }; +}; + +&sd_emmc_a { + /* Per mmc-controller.yaml */ + #address-cells = <1>; + #size-cells = <0>; + /* NB: may be either AP6398S or AP6398SR3 wifi module */ + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; diff --git a/src/arm64/amlogic/meson-g12a-fbx8am-realtek.dtso b/src/arm64/amlogic/meson-g12a-fbx8am-realtek.dtso new file mode 100644 index 00000000000..55fff35b09a --- /dev/null +++ b/src/arm64/amlogic/meson-g12a-fbx8am-realtek.dtso @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2024 Freebox SAS + +/dts-v1/; +/plugin/; + +#include +#include + +&uart_A { + bluetooth { + compatible = "realtek,rtl8822cs-bt"; + enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; + device-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>; + }; +}; + +&sd_emmc_a { + /* No explicit compatible for rtl8822cs sdio */ +}; diff --git a/src/arm64/amlogic/meson-g12a-fbx8am.dts b/src/arm64/amlogic/meson-g12a-fbx8am.dts new file mode 100644 index 00000000000..af211d8f395 --- /dev/null +++ b/src/arm64/amlogic/meson-g12a-fbx8am.dts @@ -0,0 +1,462 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2024 Freebox SAS + +/* + * SEI codename: SEI530FB (based on SEI510) + * Freebox codename: fbx8am + * Commercial names: Freebox Pop, Player TV Free 4K + */ + +/dts-v1/; + +#include "meson-g12a.dtsi" +#include +#include +#include +#include + +/ { + compatible = "freebox,fbx8am", "amlogic,g12a"; + model = "Freebox Player Pop"; + chassis-type = "embedded"; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + /* Physical user-accessible reset button near USB port */ + power-button { + label = "Reset"; + linux,code = ; + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + }; + }; + + spdif_dit: audio-codec-2 { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + status = "okay"; + sound-name-prefix = "DIT"; + }; + + aliases { + serial0 = &uart_AO; + ethernet0 = ðmac; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + ao_5v: regulator-ao-5v { + compatible = "regulator-fixed"; + regulator-name = "AO_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_in>; + regulator-always-on; + }; + + dc_in: regulator-dc-in { + compatible = "regulator-fixed"; + regulator-name = "DC_IN"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + emmc_1v8: regulator-emmc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "EMMC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vddao_3v3: regulator-vddao-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&ao_5v>; + regulator-always-on; + }; + + vddao_3v3_t: regulator-vddao-3v3-t { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3_T"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vddao_3v3>; + gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; + enable-active-high; + }; + + vddcpu: regulator-vddcpu { + /* + * SY8120B1ABC DC/DC Regulator. + */ + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU"; + regulator-min-microvolt = <721000>; + regulator-max-microvolt = <1022000>; + + pwm-supply = <&ao_5v>; + + pwms = <&pwm_AO_cd 1 1250 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; + + vddio_ao1v8: regulator-vddio-ao1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <10>; /* required for 43752 */ + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "fbx8am"; + audio-aux-devs = <&tdmout_b>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT", + "SPDIFOUT_A IN 0", "FRDDR_A OUT 3", + "SPDIFOUT_A IN 1", "FRDDR_B OUT 3", + "SPDIFOUT_A IN 2", "FRDDR_C OUT 3"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-3 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + }; + + /* spdif hdmi or toslink interface */ + dai-link-4 { + sound-dai = <&spdifout_a>; + + codec-0 { + sound-dai = <&spdif_dit>; + }; + + codec-1 { + sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_A>; + }; + }; + + /* spdif hdmi interface */ + dai-link-5 { + sound-dai = <&spdifout_b>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_B>; + }; + }; + + /* hdmi glue */ + dai-link-6 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&arb { + status = "okay"; +}; + +&cecb_AO { + pinctrl-0 = <&cec_ao_b_h_pins>; + pinctrl-names = "default"; + status = "okay"; + hdmi-phandle = <&hdmi_tx>; +}; + +&clkc_audio { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu1 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu2 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu3 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +ðmac { + status = "okay"; + phy-handle = <&internal_ephy>; + phy-mode = "rmii"; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +&spdifout_a { + pinctrl-0 = <&spdif_out_h_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&spdifout_b { + status = "okay"; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; + pinctrl-names = "default"; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +&pwm_AO_cd { + pinctrl-0 = <&pwm_ao_d_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin1"; + status = "okay"; +}; + +&pwm_ef { + status = "okay"; + pinctrl-0 = <&pwm_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin0"; +}; + +&pdm { + pinctrl-0 = <&pdm_din0_z_pins>, <&pdm_din1_z_pins>, + <&pdm_din2_z_pins>, <&pdm_din3_z_pins>, + <&pdm_dclk_z_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao1v8>; +}; + +/* SDIO */ +&sd_emmc_a { + status = "okay"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr50; + max-frequency = <100000000>; + + non-removable; + disable-wp; + + /* WiFi firmware requires power to be kept while in suspend */ + keep-power-in-suspend; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_ao1v8>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_c_pins>; + pinctrl-1 = <&sdcard_clk_gate_c_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <50000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddao_3v3>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&emmc_1v8>; +}; + +&tdmif_b { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; + +&uart_A { + status = "okay"; + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&usb { + status = "okay"; + dr_mode = "host"; +}; diff --git a/src/arm64/amlogic/meson-g12a-radxa-zero.dts b/src/arm64/amlogic/meson-g12a-radxa-zero.dts index fcd7e1d8e16..15b9bc28070 100644 --- a/src/arm64/amlogic/meson-g12a-radxa-zero.dts +++ b/src/arm64/amlogic/meson-g12a-radxa-zero.dts @@ -60,7 +60,7 @@ clock-names = "ext_clock"; }; - ao_5v: regulator-ao_5v { + ao_5v: regulator-ao-5v { compatible = "regulator-fixed"; regulator-name = "AO_5V"; regulator-min-microvolt = <5000000>; @@ -68,7 +68,7 @@ regulator-always-on; }; - vcc_1v8: regulator-vcc_1v8 { + vcc_1v8: regulator-vcc-1v8 { compatible = "regulator-fixed"; regulator-name = "VCC_1V8"; regulator-min-microvolt = <1800000>; @@ -77,7 +77,7 @@ regulator-always-on; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; @@ -86,7 +86,7 @@ regulator-always-on; }; - hdmi_pw: regulator-hdmi_pw { + hdmi_pw: regulator-hdmi-pw { compatible = "regulator-fixed"; regulator-name = "HDMI_PW"; regulator-min-microvolt = <5000000>; @@ -95,7 +95,7 @@ regulator-always-on; }; - vddao_1v8: regulator-vddao_1v8 { + vddao_1v8: regulator-vddao-1v8 { compatible = "regulator-fixed"; regulator-name = "VDDAO_1V8"; regulator-min-microvolt = <1800000>; @@ -104,7 +104,7 @@ regulator-always-on; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; diff --git a/src/arm64/amlogic/meson-g12a-sei510.dts b/src/arm64/amlogic/meson-g12a-sei510.dts index 4c4550dd471..61cb8135a39 100644 --- a/src/arm64/amlogic/meson-g12a-sei510.dts +++ b/src/arm64/amlogic/meson-g12a-sei510.dts @@ -15,7 +15,7 @@ compatible = "seirobotics,sei510", "amlogic,g12a"; model = "SEI Robotics SEI510"; - adc_keys { + keys { compatible = "adc-keys"; io-channels = <&saradc 0>; io-channel-names = "buttons"; @@ -83,7 +83,7 @@ reg = <0x0 0x0 0x0 0x40000000>; }; - ao_5v: regulator-ao_5v { + ao_5v: regulator-ao-5v { compatible = "regulator-fixed"; regulator-name = "AO_5V"; regulator-min-microvolt = <5000000>; @@ -92,7 +92,7 @@ regulator-always-on; }; - dc_in: regulator-dc_in { + dc_in: regulator-dc-in { compatible = "regulator-fixed"; regulator-name = "DC_IN"; regulator-min-microvolt = <5000000>; @@ -100,7 +100,7 @@ regulator-always-on; }; - emmc_1v8: regulator-emmc_1v8 { + emmc_1v8: regulator-emmc-1v8 { compatible = "regulator-fixed"; regulator-name = "EMMC_1V8"; regulator-min-microvolt = <1800000>; @@ -109,7 +109,7 @@ regulator-always-on; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; @@ -118,7 +118,7 @@ regulator-always-on; }; - vddao_3v3_t: regultor-vddao_3v3_t { + vddao_3v3_t: regulator-vddao-3v3-t { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3_T"; regulator-min-microvolt = <3300000>; @@ -147,7 +147,7 @@ regulator-always-on; }; - vddio_ao1v8: regulator-vddio_ao1v8 { + vddio_ao1v8: regulator-vddio-ao1v8 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO1V8"; regulator-min-microvolt = <1800000>; diff --git a/src/arm64/amlogic/meson-g12a-u200.dts b/src/arm64/amlogic/meson-g12a-u200.dts index 8355ddd7e9a..3da7922d83f 100644 --- a/src/arm64/amlogic/meson-g12a-u200.dts +++ b/src/arm64/amlogic/meson-g12a-u200.dts @@ -75,7 +75,7 @@ reg = <0x0 0x0 0x0 0x40000000>; }; - flash_1v8: regulator-flash_1v8 { + flash_1v8: regulator-flash-1v8 { compatible = "regulator-fixed"; regulator-name = "FLASH_1V8"; regulator-min-microvolt = <1800000>; @@ -84,7 +84,7 @@ regulator-always-on; }; - main_12v: regulator-main_12v { + main_12v: regulator-main-12v { compatible = "regulator-fixed"; regulator-name = "12V"; regulator-min-microvolt = <12000000>; @@ -92,7 +92,7 @@ regulator-always-on; }; - usb_pwr_en: regulator-usb_pwr_en { + usb_pwr_en: regulator-usb-pwr-en { compatible = "regulator-fixed"; regulator-name = "USB_PWR_EN"; regulator-min-microvolt = <5000000>; @@ -103,7 +103,7 @@ enable-active-high; }; - vcc_1v8: regulator-vcc_1v8 { + vcc_1v8: regulator-vcc-1v8 { compatible = "regulator-fixed"; regulator-name = "VCC_1V8"; regulator-min-microvolt = <1800000>; @@ -112,7 +112,7 @@ regulator-always-on; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; @@ -122,7 +122,7 @@ /* FIXME: actually controlled by VDDCPU_B_EN */ }; - vcc_5v: regulator-vcc_5v { + vcc_5v: regulator-vcc-5v { compatible = "regulator-fixed"; regulator-name = "VCC_5V"; regulator-min-microvolt = <5000000>; @@ -133,7 +133,7 @@ enable-active-high; }; - vddao_1v8: regulator-vddao_1v8 { + vddao_1v8: regulator-vddao-1v8 { compatible = "regulator-fixed"; regulator-name = "VDDAO_1V8"; regulator-min-microvolt = <1800000>; @@ -142,7 +142,7 @@ regulator-always-on; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; diff --git a/src/arm64/amlogic/meson-g12a-x96-max.dts b/src/arm64/amlogic/meson-g12a-x96-max.dts index 9b55982b6a6..05c7a1e3f1b 100644 --- a/src/arm64/amlogic/meson-g12a-x96-max.dts +++ b/src/arm64/amlogic/meson-g12a-x96-max.dts @@ -66,7 +66,7 @@ clock-names = "ext_clock"; }; - flash_1v8: regulator-flash_1v8 { + flash_1v8: regulator-flash-1v8 { compatible = "regulator-fixed"; regulator-name = "FLASH_1V8"; regulator-min-microvolt = <1800000>; @@ -75,7 +75,7 @@ regulator-always-on; }; - dc_in: regulator-dc_in { + dc_in: regulator-dc-in { compatible = "regulator-fixed"; regulator-name = "DC_IN"; regulator-min-microvolt = <5000000>; @@ -83,7 +83,7 @@ regulator-always-on; }; - vcc_1v8: regulator-vcc_1v8 { + vcc_1v8: regulator-vcc-1v8 { compatible = "regulator-fixed"; regulator-name = "VCC_1V8"; regulator-min-microvolt = <1800000>; @@ -92,7 +92,7 @@ regulator-always-on; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; @@ -102,7 +102,7 @@ /* FIXME: actually controlled by VDDCPU_B_EN */ }; - vcc_5v: regulator-vcc_5v { + vcc_5v: regulator-vcc-5v { compatible = "regulator-fixed"; regulator-name = "VCC_5V"; regulator-min-microvolt = <5000000>; @@ -112,7 +112,7 @@ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; }; - vddao_1v8: regulator-vddao_1v8 { + vddao_1v8: regulator-vddao-1v8 { compatible = "regulator-fixed"; regulator-name = "VDDAO_1V8"; regulator-min-microvolt = <1800000>; @@ -121,7 +121,7 @@ regulator-always-on; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; diff --git a/src/arm64/amlogic/meson-g12b-odroid-n2.dtsi b/src/arm64/amlogic/meson-g12b-odroid-n2.dtsi index 91c9769fda2..d80dd9a3da3 100644 --- a/src/arm64/amlogic/meson-g12b-odroid-n2.dtsi +++ b/src/arm64/amlogic/meson-g12b-odroid-n2.dtsi @@ -19,7 +19,7 @@ status = "okay"; }; - hub_5v: regulator-hub_5v { + hub_5v: regulator-hub-5v { compatible = "regulator-fixed"; regulator-name = "HUB_5V"; regulator-min-microvolt = <5000000>; diff --git a/src/arm64/amlogic/meson-g12b-odroid.dtsi b/src/arm64/amlogic/meson-g12b-odroid.dtsi index 9e12a34b284..09d959aefb1 100644 --- a/src/arm64/amlogic/meson-g12b-odroid.dtsi +++ b/src/arm64/amlogic/meson-g12b-odroid.dtsi @@ -48,7 +48,7 @@ }; }; - tflash_vdd: regulator-tflash_vdd { + tflash_vdd: regulator-tflash-vdd { compatible = "regulator-fixed"; regulator-name = "TFLASH_VDD"; @@ -60,7 +60,7 @@ regulator-always-on; }; - tf_io: gpio-regulator-tf_io { + tf_io: gpio-regulator-tf-io { compatible = "regulator-gpio"; regulator-name = "TF_IO"; @@ -74,7 +74,7 @@ <1800000 1>; }; - flash_1v8: regulator-flash_1v8 { + flash_1v8: regulator-flash-1v8 { compatible = "regulator-fixed"; regulator-name = "FLASH_1V8"; regulator-min-microvolt = <1800000>; @@ -83,7 +83,7 @@ regulator-always-on; }; - main_12v: regulator-main_12v { + main_12v: regulator-main-12v { compatible = "regulator-fixed"; regulator-name = "12V"; regulator-min-microvolt = <12000000>; @@ -91,7 +91,7 @@ regulator-always-on; }; - usb_pwr_en: regulator-usb_pwr_en { + usb_pwr_en: regulator-usb-pwr-en { compatible = "regulator-fixed"; regulator-name = "USB_PWR_EN"; regulator-min-microvolt = <5000000>; @@ -103,7 +103,7 @@ enable-active-high; }; - vcc_5v: regulator-vcc_5v { + vcc_5v: regulator-vcc-5v { compatible = "regulator-fixed"; regulator-name = "5V"; regulator-min-microvolt = <5000000>; @@ -114,7 +114,7 @@ enable-active-high; }; - vcc_1v8: regulator-vcc_1v8 { + vcc_1v8: regulator-vcc-1v8 { compatible = "regulator-fixed"; regulator-name = "VCC_1V8"; regulator-min-microvolt = <1800000>; @@ -123,7 +123,7 @@ regulator-always-on; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; @@ -171,7 +171,7 @@ regulator-always-on; }; - vddao_1v8: regulator-vddao_1v8 { + vddao_1v8: regulator-vddao-1v8 { compatible = "regulator-fixed"; regulator-name = "VDDAO_1V8"; regulator-min-microvolt = <1800000>; @@ -180,7 +180,7 @@ regulator-always-on; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; diff --git a/src/arm64/amlogic/meson-g12b-w400.dtsi b/src/arm64/amlogic/meson-g12b-w400.dtsi index ac8b7178257..4cb6930ffb1 100644 --- a/src/arm64/amlogic/meson-g12b-w400.dtsi +++ b/src/arm64/amlogic/meson-g12b-w400.dtsi @@ -39,7 +39,7 @@ clock-names = "ext_clock"; }; - flash_1v8: regulator-flash_1v8 { + flash_1v8: regulator-flash-1v8 { compatible = "regulator-fixed"; regulator-name = "FLASH_1V8"; regulator-min-microvolt = <1800000>; @@ -48,7 +48,7 @@ regulator-always-on; }; - main_12v: regulator-main_12v { + main_12v: regulator-main-12v { compatible = "regulator-fixed"; regulator-name = "12V"; regulator-min-microvolt = <12000000>; @@ -56,7 +56,7 @@ regulator-always-on; }; - vcc_5v: regulator-vcc_5v { + vcc_5v: regulator-vcc-5v { compatible = "regulator-fixed"; regulator-name = "VCC_5V"; regulator-min-microvolt = <5000000>; @@ -67,7 +67,7 @@ enable-active-high; }; - vcc_1v8: regulator-vcc_1v8 { + vcc_1v8: regulator-vcc-1v8 { compatible = "regulator-fixed"; regulator-name = "VCC_1V8"; regulator-min-microvolt = <1800000>; @@ -76,7 +76,7 @@ regulator-always-on; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; diff --git a/src/arm64/amlogic/meson-gx-libretech-pc.dtsi b/src/arm64/amlogic/meson-gx-libretech-pc.dtsi index 5e7b9273b06..efd662a452e 100644 --- a/src/arm64/amlogic/meson-gx-libretech-pc.dtsi +++ b/src/arm64/amlogic/meson-gx-libretech-pc.dtsi @@ -84,7 +84,7 @@ reg = <0x0 0x0 0x0 0x80000000>; }; - ao_5v: regulator-ao_5v { + ao_5v: regulator-ao-5v { compatible = "regulator-fixed"; regulator-name = "AO_5V"; regulator-min-microvolt = <5000000>; @@ -93,7 +93,7 @@ regulator-always-on; }; - dc_in: regulator-dc_in { + dc_in: regulator-dc-in { compatible = "regulator-fixed"; regulator-name = "DC_IN"; regulator-min-microvolt = <5000000>; @@ -120,7 +120,7 @@ }; }; - vcc_card: regulator-vcc_card { + vcc_card: regulator-vcc-card { compatible = "regulator-fixed"; regulator-name = "VCC_CARD"; regulator-min-microvolt = <3300000>; @@ -141,7 +141,7 @@ gpio = <&gpio GPIOH_3 GPIO_OPEN_DRAIN>; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; @@ -150,7 +150,7 @@ regulator-always-on; }; - vddio_ao3v3: regulator-vddio_ao3v3 { + vddio_ao3v3: regulator-vddio-ao3v3 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO3V3"; regulator-min-microvolt = <3300000>; @@ -159,7 +159,7 @@ regulator-always-on; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; diff --git a/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi b/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi index e59c3c92b1e..08d6b69ba46 100644 --- a/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi +++ b/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi @@ -50,28 +50,28 @@ regulator-always-on; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; diff --git a/src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts b/src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts index 4aab1ab705b..cca129ce2c5 100644 --- a/src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts +++ b/src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts @@ -78,21 +78,21 @@ <3300000 1>; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; diff --git a/src/arm64/amlogic/meson-gxbb-odroidc2.dts b/src/arm64/amlogic/meson-gxbb-odroidc2.dts index e6d2de7c45a..c431986e6a3 100644 --- a/src/arm64/amlogic/meson-gxbb-odroidc2.dts +++ b/src/arm64/amlogic/meson-gxbb-odroidc2.dts @@ -67,7 +67,7 @@ regulator-always-on; }; - hdmi_p5v0: regulator-hdmi_p5v0 { + hdmi_p5v0: regulator-hdmi-p5v0 { compatible = "regulator-fixed"; regulator-name = "HDMI_P5V0"; regulator-min-microvolt = <5000000>; @@ -76,7 +76,7 @@ vin-supply = <&p5v0>; }; - tflash_vdd: regulator-tflash_vdd { + tflash_vdd: regulator-tflash-vdd { compatible = "regulator-fixed"; regulator-name = "TFLASH_VDD"; @@ -92,7 +92,7 @@ vin-supply = <&vddio_ao3v3>; }; - tf_io: gpio-regulator-tf_io { + tf_io: gpio-regulator-tf-io { compatible = "regulator-gpio"; regulator-name = "TF_IO"; @@ -148,7 +148,7 @@ vin-supply = <&p5v0>; }; - ddr3_1v5: regulator-ddr3_1v5 { + ddr3_1v5: regulator-ddr3-1v5 { compatible = "regulator-fixed"; regulator-name = "DDR3_1V5"; regulator-min-microvolt = <1500000>; diff --git a/src/arm64/amlogic/meson-gxbb-p200.dts b/src/arm64/amlogic/meson-gxbb-p200.dts index 591455c50e8..7f94716876d 100644 --- a/src/arm64/amlogic/meson-gxbb-p200.dts +++ b/src/arm64/amlogic/meson-gxbb-p200.dts @@ -21,14 +21,14 @@ sound-name-prefix = "DIT"; }; - avdd18_usb_adc: regulator-avdd18_usb_adc { + avdd18_usb_adc: regulator-avdd18-usb-adc { compatible = "regulator-fixed"; regulator-name = "AVDD18_USB_ADC"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - adc_keys { + keys { compatible = "adc-keys"; io-channels = <&saradc 0>; io-channel-names = "buttons"; diff --git a/src/arm64/amlogic/meson-gxbb-p20x.dtsi b/src/arm64/amlogic/meson-gxbb-p20x.dtsi index e803a466fe4..52d57773a77 100644 --- a/src/arm64/amlogic/meson-gxbb-p20x.dtsi +++ b/src/arm64/amlogic/meson-gxbb-p20x.dtsi @@ -53,21 +53,21 @@ regulator-settling-time-down-us = <150000>; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; diff --git a/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi b/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi index 74df3253423..255e93a0b36 100644 --- a/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi +++ b/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi @@ -47,28 +47,28 @@ enable-active-high; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; diff --git a/src/arm64/amlogic/meson-gxbb-wetek.dtsi b/src/arm64/amlogic/meson-gxbb-wetek.dtsi index 94dafb95530..deb29522718 100644 --- a/src/arm64/amlogic/meson-gxbb-wetek.dtsi +++ b/src/arm64/amlogic/meson-gxbb-wetek.dtsi @@ -49,21 +49,21 @@ enable-active-high; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; @@ -71,7 +71,7 @@ regulator-always-on; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; diff --git a/src/arm64/amlogic/meson-gxl-s805x-libretech-ac.dts b/src/arm64/amlogic/meson-gxl-s805x-libretech-ac.dts index a29b49f051a..90ef9c17d80 100644 --- a/src/arm64/amlogic/meson-gxl-s805x-libretech-ac.dts +++ b/src/arm64/amlogic/meson-gxl-s805x-libretech-ac.dts @@ -42,7 +42,7 @@ }; }; - dc_5v: regulator-dc_5v { + dc_5v: regulator-dc-5v { compatible = "regulator-fixed"; regulator-name = "DC_5V"; regulator-min-microvolt = <5000000>; @@ -89,7 +89,7 @@ regulator-always-on; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; @@ -98,7 +98,7 @@ regulator-always-on; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; @@ -107,7 +107,7 @@ regulator-always-on; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; diff --git a/src/arm64/amlogic/meson-gxl-s805x-p241.dts b/src/arm64/amlogic/meson-gxl-s805x-p241.dts index c0d6eb55100..08a4718219b 100644 --- a/src/arm64/amlogic/meson-gxl-s805x-p241.dts +++ b/src/arm64/amlogic/meson-gxl-s805x-p241.dts @@ -64,28 +64,28 @@ reg = <0x0 0x0 0x0 0x20000000>; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; diff --git a/src/arm64/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts b/src/arm64/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts index a18d6d241a5..2b94b6e5285 100644 --- a/src/arm64/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts +++ b/src/arm64/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts @@ -37,28 +37,28 @@ stdout-path = "serial0:115200n8"; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; diff --git a/src/arm64/amlogic/meson-gxl-s905x-hwacom-amazetv.dts b/src/arm64/amlogic/meson-gxl-s905x-hwacom-amazetv.dts index c8d74e61dec..89fe5110f7a 100644 --- a/src/arm64/amlogic/meson-gxl-s905x-hwacom-amazetv.dts +++ b/src/arm64/amlogic/meson-gxl-s905x-hwacom-amazetv.dts @@ -42,21 +42,21 @@ <3300000 1>; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; diff --git a/src/arm64/amlogic/meson-gxl-s905x-libretech-cc-v2.dts b/src/arm64/amlogic/meson-gxl-s905x-libretech-cc-v2.dts index 2825db91e46..63b20860067 100644 --- a/src/arm64/amlogic/meson-gxl-s905x-libretech-cc-v2.dts +++ b/src/arm64/amlogic/meson-gxl-s905x-libretech-cc-v2.dts @@ -67,7 +67,7 @@ reg = <0x0 0x0 0x0 0x80000000>; }; - ao_5v: regulator-ao_5v { + ao_5v: regulator-ao-5v { compatible = "regulator-fixed"; regulator-name = "AO_5V"; regulator-min-microvolt = <5000000>; @@ -76,7 +76,7 @@ regulator-always-on; }; - dc_in: regulator-dc_in { + dc_in: regulator-dc-in { compatible = "regulator-fixed"; regulator-name = "DC_IN"; regulator-min-microvolt = <5000000>; @@ -93,7 +93,7 @@ regulator-always-on; }; - vcc_card: regulator-vcc_card { + vcc_card: regulator-vcc-card { compatible = "regulator-fixed"; regulator-name = "VCC_CARD"; regulator-min-microvolt = <3300000>; @@ -114,7 +114,7 @@ gpio = <&gpio GPIOH_3 GPIO_OPEN_DRAIN>; }; - vddio_ao3v3: regulator-vddio_ao3v3 { + vddio_ao3v3: regulator-vddio-ao3v3 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO3V3"; regulator-min-microvolt = <3300000>; @@ -139,7 +139,7 @@ regulator-settling-time-down-us = <50000>; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; @@ -148,7 +148,7 @@ regulator-always-on; }; - vcc_1v8: regulator-vcc_1v8 { + vcc_1v8: regulator-vcc-1v8 { compatible = "regulator-fixed"; regulator-name = "VCC 1V8"; regulator-min-microvolt = <1800000>; diff --git a/src/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts b/src/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts index 27093e6ac9e..8b26c9661be 100644 --- a/src/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts +++ b/src/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts @@ -93,7 +93,7 @@ regulator-always-on; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; @@ -117,7 +117,7 @@ regulator-settling-time-down-us = <50000>; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; @@ -125,7 +125,7 @@ }; /* This is provided by LDOs on the eMMC daugther card */ - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; diff --git a/src/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts b/src/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts index f1acca5c443..c79f9f2099b 100644 --- a/src/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts +++ b/src/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts @@ -42,21 +42,21 @@ <3300000 1>; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; diff --git a/src/arm64/amlogic/meson-gxl-s905x-p212.dtsi b/src/arm64/amlogic/meson-gxl-s905x-p212.dtsi index a150cc0e18f..7e7dc87ede2 100644 --- a/src/arm64/amlogic/meson-gxl-s905x-p212.dtsi +++ b/src/arm64/amlogic/meson-gxl-s905x-p212.dtsi @@ -39,28 +39,28 @@ regulator-always-on; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; diff --git a/src/arm64/amlogic/meson-gxm-khadas-vim2.dts b/src/arm64/amlogic/meson-gxm-khadas-vim2.dts index 860f307494c..07e7c3bedea 100644 --- a/src/arm64/amlogic/meson-gxm-khadas-vim2.dts +++ b/src/arm64/amlogic/meson-gxm-khadas-vim2.dts @@ -112,28 +112,28 @@ regulator-always-on; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; diff --git a/src/arm64/amlogic/meson-gxm-s912-libretech-pc.dts b/src/arm64/amlogic/meson-gxm-s912-libretech-pc.dts index 4eda9f634c4..a66f19851ac 100644 --- a/src/arm64/amlogic/meson-gxm-s912-libretech-pc.dts +++ b/src/arm64/amlogic/meson-gxm-s912-libretech-pc.dts @@ -14,7 +14,7 @@ "amlogic,meson-gxm"; model = "Libre Computer AML-S912-PC"; - typec2_vbus: regulator-typec2_vbus { + typec2_vbus: regulator-typec2-vbus { compatible = "regulator-fixed"; regulator-name = "TYPEC2_VBUS"; regulator-min-microvolt = <5000000>; diff --git a/src/arm64/amlogic/meson-khadas-vim3.dtsi b/src/arm64/amlogic/meson-khadas-vim3.dtsi index 514a6dd4b12..e78cc9b577a 100644 --- a/src/arm64/amlogic/meson-khadas-vim3.dtsi +++ b/src/arm64/amlogic/meson-khadas-vim3.dtsi @@ -80,7 +80,7 @@ clock-names = "ext_clock"; }; - dc_in: regulator-dc_in { + dc_in: regulator-dc-in { compatible = "regulator-fixed"; regulator-name = "DC_IN"; regulator-min-microvolt = <5000000>; @@ -88,7 +88,7 @@ regulator-always-on; }; - vcc_5v: regulator-vcc_5v { + vcc_5v: regulator-vcc-5v { compatible = "regulator-fixed"; regulator-name = "VCC_5V"; regulator-min-microvolt = <5000000>; @@ -99,7 +99,7 @@ enable-active-high; }; - vcc_1v8: regulator-vcc_1v8 { + vcc_1v8: regulator-vcc-1v8 { compatible = "regulator-fixed"; regulator-name = "VCC_1V8"; regulator-min-microvolt = <1800000>; @@ -108,7 +108,7 @@ regulator-always-on; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; @@ -118,7 +118,7 @@ /* FIXME: actually controlled by VDDCPU_B_EN */ }; - vddao_1v8: regulator-vddao_1v8 { + vddao_1v8: regulator-vddao-1v8 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO1V8"; regulator-min-microvolt = <1800000>; @@ -127,7 +127,7 @@ regulator-always-on; }; - emmc_1v8: regulator-emmc_1v8 { + emmc_1v8: regulator-emmc-1v8 { compatible = "regulator-fixed"; regulator-name = "EMMC_AO1V8"; regulator-min-microvolt = <1800000>; @@ -136,7 +136,7 @@ regulator-always-on; }; - vsys_3v3: regulator-vsys_3v3 { + vsys_3v3: regulator-vsys-3v3 { compatible = "regulator-fixed"; regulator-name = "VSYS_3V3"; regulator-min-microvolt = <3300000>; @@ -145,7 +145,7 @@ regulator-always-on; }; - usb_pwr: regulator-usb_pwr { + usb_pwr: regulator-usb-pwr { compatible = "regulator-fixed"; regulator-name = "USB_PWR"; regulator-min-microvolt = <5000000>; diff --git a/src/arm64/amlogic/meson-libretech-cottonwood.dtsi b/src/arm64/amlogic/meson-libretech-cottonwood.dtsi index 35e8f5bae99..082b72703cd 100644 --- a/src/arm64/amlogic/meson-libretech-cottonwood.dtsi +++ b/src/arm64/amlogic/meson-libretech-cottonwood.dtsi @@ -150,7 +150,7 @@ gpio-open-drain; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; @@ -171,7 +171,7 @@ pwm-dutycycle-range = <100 0>; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; @@ -180,7 +180,7 @@ vin-supply = <&vddao_3v3>; }; - vddio_c: regulator-vddio_c { + vddio_c: regulator-vddio-c { compatible = "regulator-gpio"; regulator-name = "VDDIO_C"; regulator-min-microvolt = <1800000>; diff --git a/src/arm64/amlogic/meson-sm1-ac2xx.dtsi b/src/arm64/amlogic/meson-sm1-ac2xx.dtsi index 46a34731f7e..d1fa8b8bf79 100644 --- a/src/arm64/amlogic/meson-sm1-ac2xx.dtsi +++ b/src/arm64/amlogic/meson-sm1-ac2xx.dtsi @@ -54,7 +54,7 @@ reg = <0x0 0x0 0x0 0x40000000>; }; - ao_5v: regulator-ao_5v { + ao_5v: regulator-ao-5v { compatible = "regulator-fixed"; regulator-name = "AO_5V"; regulator-min-microvolt = <5000000>; @@ -63,7 +63,7 @@ regulator-always-on; }; - dc_in: regulator-dc_in { + dc_in: regulator-dc-in { compatible = "regulator-fixed"; regulator-name = "DC_IN"; regulator-min-microvolt = <5000000>; @@ -71,7 +71,7 @@ regulator-always-on; }; - emmc_1v8: regulator-emmc_1v8 { + emmc_1v8: regulator-emmc-1v8 { compatible = "regulator-fixed"; regulator-name = "EMMC_1V8"; regulator-min-microvolt = <1800000>; @@ -80,7 +80,7 @@ regulator-always-on; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; @@ -105,7 +105,7 @@ regulator-always-on; }; - vddio_ao1v8: regulator-vddio_ao1v8 { + vddio_ao1v8: regulator-vddio-ao1v8 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO1V8"; regulator-min-microvolt = <1800000>; diff --git a/src/arm64/amlogic/meson-sm1-bananapi.dtsi b/src/arm64/amlogic/meson-sm1-bananapi.dtsi index 62404743e62..81dce862902 100644 --- a/src/arm64/amlogic/meson-sm1-bananapi.dtsi +++ b/src/arm64/amlogic/meson-sm1-bananapi.dtsi @@ -82,7 +82,7 @@ reg = <0x0 0x0 0x0 0x40000000>; }; - emmc_1v8: regulator-emmc_1v8 { + emmc_1v8: regulator-emmc-1v8 { compatible = "regulator-fixed"; regulator-name = "EMMC_1V8"; regulator-min-microvolt = <1800000>; @@ -91,7 +91,7 @@ regulator-always-on; }; - dc_in: regulator-dc_in { + dc_in: regulator-dc-in { compatible = "regulator-fixed"; regulator-name = "DC_IN"; regulator-min-microvolt = <5000000>; @@ -99,7 +99,7 @@ regulator-always-on; }; - vddio_c: regulator-vddio_c { + vddio_c: regulator-vddio-c { compatible = "regulator-gpio"; regulator-name = "VDDIO_C"; regulator-min-microvolt = <1800000>; @@ -116,7 +116,7 @@ <3300000 1>; }; - tflash_vdd: regulator-tflash_vdd { + tflash_vdd: regulator-tflash-vdd { compatible = "regulator-fixed"; regulator-name = "TFLASH_VDD"; regulator-min-microvolt = <3300000>; @@ -127,7 +127,7 @@ regulator-always-on; }; - vddao_1v8: regulator-vddao_1v8 { + vddao_1v8: regulator-vddao-1v8 { compatible = "regulator-fixed"; regulator-name = "VDDAO_1V8"; regulator-min-microvolt = <1800000>; @@ -136,7 +136,7 @@ regulator-always-on; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; @@ -165,7 +165,7 @@ }; /* USB Hub Power Enable */ - vl_pwr_en: regulator-vl_pwr_en { + vl_pwr_en: regulator-vl-pwr-en { compatible = "regulator-fixed"; regulator-name = "VL_PWR_EN"; regulator-min-microvolt = <5000000>; diff --git a/src/arm64/amlogic/meson-sm1-odroid-hc4.dts b/src/arm64/amlogic/meson-sm1-odroid-hc4.dts index 846a2d6c20e..0170139b8d3 100644 --- a/src/arm64/amlogic/meson-sm1-odroid-hc4.dts +++ b/src/arm64/amlogic/meson-sm1-odroid-hc4.dts @@ -43,7 +43,7 @@ }; /* Powers the SATA Disk 0 regulator, which is enabled when a disk load is detected */ - p12v_0: regulator-p12v_0 { + p12v_0: regulator-p12v-0 { compatible = "regulator-fixed"; regulator-name = "P12V_0"; regulator-min-microvolt = <12000000>; @@ -56,7 +56,7 @@ }; /* Powers the SATA Disk 1 regulator, which is enabled when a disk load is detected */ - p12v_1: regulator-p12v_1 { + p12v_1: regulator-p12v-1 { compatible = "regulator-fixed"; regulator-name = "P12V_1"; regulator-min-microvolt = <12000000>; diff --git a/src/arm64/amlogic/meson-sm1-odroid.dtsi b/src/arm64/amlogic/meson-sm1-odroid.dtsi index 1db2327bbd1..951eb8e3f0c 100644 --- a/src/arm64/amlogic/meson-sm1-odroid.dtsi +++ b/src/arm64/amlogic/meson-sm1-odroid.dtsi @@ -28,7 +28,7 @@ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; }; - tflash_vdd: regulator-tflash_vdd { + tflash_vdd: regulator-tflash-vdd { compatible = "regulator-fixed"; regulator-name = "TFLASH_VDD"; @@ -40,7 +40,7 @@ regulator-always-on; }; - tf_io: gpio-regulator-tf_io { + tf_io: gpio-regulator-tf-io { compatible = "regulator-gpio"; regulator-name = "TF_IO"; @@ -59,7 +59,7 @@ <1800000 1>; }; - flash_1v8: regulator-flash_1v8 { + flash_1v8: regulator-flash-1v8 { compatible = "regulator-fixed"; regulator-name = "FLASH_1V8"; regulator-min-microvolt = <1800000>; @@ -68,7 +68,7 @@ regulator-always-on; }; - main_12v: regulator-main_12v { + main_12v: regulator-main-12v { compatible = "regulator-fixed"; regulator-name = "12V"; regulator-min-microvolt = <12000000>; @@ -76,7 +76,7 @@ regulator-always-on; }; - vcc_5v: regulator-vcc_5v { + vcc_5v: regulator-vcc-5v { compatible = "regulator-fixed"; regulator-name = "5V"; regulator-min-microvolt = <5000000>; @@ -87,7 +87,7 @@ enable-active-high; }; - vcc_1v8: regulator-vcc_1v8 { + vcc_1v8: regulator-vcc-1v8 { compatible = "regulator-fixed"; regulator-name = "VCC_1V8"; regulator-min-microvolt = <1800000>; @@ -96,7 +96,7 @@ regulator-always-on; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; @@ -125,7 +125,7 @@ regulator-always-on; }; - usb_pwr_en: regulator-usb_pwr_en { + usb_pwr_en: regulator-usb-pwr-en { compatible = "regulator-fixed"; regulator-name = "USB_PWR_EN"; regulator-min-microvolt = <5000000>; @@ -137,7 +137,7 @@ enable-active-high; }; - vddao_1v8: regulator-vddao_1v8 { + vddao_1v8: regulator-vddao-1v8 { compatible = "regulator-fixed"; regulator-name = "VDDAO_1V8"; regulator-min-microvolt = <1800000>; @@ -146,7 +146,7 @@ regulator-always-on; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; diff --git a/src/arm64/amlogic/meson-sm1-sei610.dts b/src/arm64/amlogic/meson-sm1-sei610.dts index 109932068db..3581e14cbf1 100644 --- a/src/arm64/amlogic/meson-sm1-sei610.dts +++ b/src/arm64/amlogic/meson-sm1-sei610.dts @@ -127,7 +127,7 @@ reg = <0x0 0x0 0x0 0x40000000>; }; - ao_5v: regulator-ao_5v { + ao_5v: regulator-ao-5v { compatible = "regulator-fixed"; regulator-name = "AO_5V"; regulator-min-microvolt = <5000000>; @@ -136,7 +136,7 @@ regulator-always-on; }; - dc_in: regulator-dc_in { + dc_in: regulator-dc-in { compatible = "regulator-fixed"; regulator-name = "DC_IN"; regulator-min-microvolt = <5000000>; @@ -144,7 +144,7 @@ regulator-always-on; }; - emmc_1v8: regulator-emmc_1v8 { + emmc_1v8: regulator-emmc-1v8 { compatible = "regulator-fixed"; regulator-name = "EMMC_1V8"; regulator-min-microvolt = <1800000>; @@ -153,7 +153,7 @@ regulator-always-on; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; @@ -163,7 +163,7 @@ }; /* Used by Tuner, RGB Led & IR Emitter LED array */ - vddao_3v3_t: regulator-vddao_3v3_t { + vddao_3v3_t: regulator-vddao-3v3-t { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3_T"; regulator-min-microvolt = <3300000>; @@ -192,7 +192,7 @@ regulator-always-on; }; - vddio_ao1v8: regulator-vddio_ao1v8 { + vddio_ao1v8: regulator-vddio-ao1v8 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO1V8"; regulator-min-microvolt = <1800000>; diff --git a/src/arm64/broadcom/bcmbca/bcm4906-netgear-r8000p.dts b/src/arm64/broadcom/bcmbca/bcm4906-netgear-r8000p.dts index 78204d71ecd..999d9373024 100644 --- a/src/arm64/broadcom/bcmbca/bcm4906-netgear-r8000p.dts +++ b/src/arm64/broadcom/bcmbca/bcm4906-netgear-r8000p.dts @@ -125,6 +125,11 @@ }; }; +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + &nandcs { nand-ecc-strength = <4>; nand-ecc-step-size = <512>; diff --git a/src/arm64/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts b/src/arm64/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts index fcf092c81b5..19fc03ef47a 100644 --- a/src/arm64/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts +++ b/src/arm64/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts @@ -155,6 +155,11 @@ }; }; +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + &nandcs { nand-ecc-strength = <4>; nand-ecc-step-size = <512>; diff --git a/src/arm64/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts b/src/arm64/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts index d94a53d6832..2a0d4ee3bd7 100644 --- a/src/arm64/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts +++ b/src/arm64/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts @@ -166,11 +166,15 @@ }; }; +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + &nandcs { nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-on-flash-bbt; - brcm,nand-has-wp; #address-cells = <1>; #size-cells = <0>; @@ -181,16 +185,17 @@ #size-cells = <1>; partition@0 { - compatible = "nvmem-cells"; label = "cferom"; reg = <0x0 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x100000>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - base_mac_addr: mac@106a0 { - reg = <0x106a0 0x6>; + base_mac_addr: mac@106a0 { + reg = <0x106a0 0x6>; + }; }; }; diff --git a/src/arm64/broadcom/bcmbca/bcm4908.dtsi b/src/arm64/broadcom/bcmbca/bcm4908.dtsi index 2f124b027bb..e01cf4f5407 100644 --- a/src/arm64/broadcom/bcmbca/bcm4908.dtsi +++ b/src/arm64/broadcom/bcmbca/bcm4908.dtsi @@ -227,9 +227,6 @@ brcm,num-gphy = <5>; brcm,num-rgmii-ports = <2>; - #address-cells = <1>; - #size-cells = <0>; - ports: ports { #address-cells = <1>; #size-cells = <0>; @@ -589,7 +586,7 @@ status = "disabled"; }; - nand-controller@1800 { + nand_controller: nand-controller@1800 { #address-cells = <1>; #size-cells = <0>; compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; @@ -597,7 +594,7 @@ reg-names = "nand", "nand-int-base"; interrupts = ; interrupt-names = "nand_ctlrdy"; - status = "okay"; + status = "disabled"; nandcs: nand@0 { compatible = "brcm,nandcs"; diff --git a/src/arm64/broadcom/bcmbca/bcm4912.dtsi b/src/arm64/broadcom/bcmbca/bcm4912.dtsi index d658c81f728..14b2adfb817 100644 --- a/src/arm64/broadcom/bcmbca/bcm4912.dtsi +++ b/src/arm64/broadcom/bcmbca/bcm4912.dtsi @@ -138,6 +138,20 @@ status = "disabled"; }; + nand_controller: nand-controller@1800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x1800 0x600>, <0x2000 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/src/arm64/broadcom/bcmbca/bcm63146.dtsi b/src/arm64/broadcom/bcmbca/bcm63146.dtsi index 4f474d47022..589b8a1efc7 100644 --- a/src/arm64/broadcom/bcmbca/bcm63146.dtsi +++ b/src/arm64/broadcom/bcmbca/bcm63146.dtsi @@ -119,6 +119,20 @@ status = "disabled"; }; + nand_controller: nand-controller@1800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x1800 0x600>, <0x2000 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/src/arm64/broadcom/bcmbca/bcm63158.dtsi b/src/arm64/broadcom/bcmbca/bcm63158.dtsi index 909f254dc47..48d618e7586 100644 --- a/src/arm64/broadcom/bcmbca/bcm63158.dtsi +++ b/src/arm64/broadcom/bcmbca/bcm63158.dtsi @@ -137,6 +137,20 @@ status = "disabled"; }; + nand_controller: nand-controller@1800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x1800 0x600>, <0x2000 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/src/arm64/broadcom/bcmbca/bcm6813.dtsi b/src/arm64/broadcom/bcmbca/bcm6813.dtsi index 685ae32951c..1d1303cf90f 100644 --- a/src/arm64/broadcom/bcmbca/bcm6813.dtsi +++ b/src/arm64/broadcom/bcmbca/bcm6813.dtsi @@ -138,6 +138,20 @@ status = "disabled"; }; + nand_controller: nand-controller@1800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x1800 0x600>, <0x2000 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/src/arm64/broadcom/bcmbca/bcm6856.dtsi b/src/arm64/broadcom/bcmbca/bcm6856.dtsi index 820553ce541..00c62c1e5df 100644 --- a/src/arm64/broadcom/bcmbca/bcm6856.dtsi +++ b/src/arm64/broadcom/bcmbca/bcm6856.dtsi @@ -119,5 +119,19 @@ num-cs = <8>; status = "disabled"; }; + + nand_controller: nand-controller@1800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x1800 0x600>, <0x2000 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; }; }; diff --git a/src/arm64/broadcom/bcmbca/bcm6858.dtsi b/src/arm64/broadcom/bcmbca/bcm6858.dtsi index 0eb93c29829..caeaf428dc1 100644 --- a/src/arm64/broadcom/bcmbca/bcm6858.dtsi +++ b/src/arm64/broadcom/bcmbca/bcm6858.dtsi @@ -156,5 +156,19 @@ num-cs = <8>; status = "disabled"; }; + + nand_controller: nand-controller@1800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x1800 0x600>, <0x2000 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; }; }; diff --git a/src/arm64/broadcom/bcmbca/bcm94908.dts b/src/arm64/broadcom/bcmbca/bcm94908.dts index c4e6e71f631..030ffa5364f 100644 --- a/src/arm64/broadcom/bcmbca/bcm94908.dts +++ b/src/arm64/broadcom/bcmbca/bcm94908.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/src/arm64/broadcom/bcmbca/bcm94912.dts b/src/arm64/broadcom/bcmbca/bcm94912.dts index e69cd683211..4b779e6c22e 100644 --- a/src/arm64/broadcom/bcmbca/bcm94912.dts +++ b/src/arm64/broadcom/bcmbca/bcm94912.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/src/arm64/broadcom/bcmbca/bcm963146.dts b/src/arm64/broadcom/bcmbca/bcm963146.dts index db2c82d6dfd..2851e8e41bf 100644 --- a/src/arm64/broadcom/bcmbca/bcm963146.dts +++ b/src/arm64/broadcom/bcmbca/bcm963146.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/src/arm64/broadcom/bcmbca/bcm963158.dts b/src/arm64/broadcom/bcmbca/bcm963158.dts index 25c12bc6354..17dc594fe83 100644 --- a/src/arm64/broadcom/bcmbca/bcm963158.dts +++ b/src/arm64/broadcom/bcmbca/bcm963158.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/src/arm64/broadcom/bcmbca/bcm96813.dts b/src/arm64/broadcom/bcmbca/bcm96813.dts index faba21f0312..34832a73473 100644 --- a/src/arm64/broadcom/bcmbca/bcm96813.dts +++ b/src/arm64/broadcom/bcmbca/bcm96813.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/src/arm64/broadcom/bcmbca/bcm96856.dts b/src/arm64/broadcom/bcmbca/bcm96856.dts index 9808331eede..e1396b5544b 100644 --- a/src/arm64/broadcom/bcmbca/bcm96856.dts +++ b/src/arm64/broadcom/bcmbca/bcm96856.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/src/arm64/broadcom/bcmbca/bcm96858.dts b/src/arm64/broadcom/bcmbca/bcm96858.dts index 1f561c8e13b..30bbf6f2917 100644 --- a/src/arm64/broadcom/bcmbca/bcm96858.dts +++ b/src/arm64/broadcom/bcmbca/bcm96858.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/src/arm64/exynos/exynos850.dtsi b/src/arm64/exynos/exynos850.dtsi index da3f4a791e6..2ba67c3d068 100644 --- a/src/arm64/exynos/exynos850.dtsi +++ b/src/arm64/exynos/exynos850.dtsi @@ -184,6 +184,16 @@ clock-names = "fin_pll", "mct"; }; + pdma0: dma-controller@120c0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x120c0000 0x1000>; + clocks = <&cmu_core CLK_GOUT_PDMA_CORE_ACLK>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + interrupts = ; + arm,pl330-broken-no-flushp; + }; + gic: interrupt-controller@12a01000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -728,6 +738,24 @@ <&cmu_peri CLK_GOUT_SPI0_IPCLK>; clock-names = "pclk", "ipclk"; status = "disabled"; + + spi_0: spi@13940000 { + compatible = "samsung,exynos850-spi"; + reg = <0x13940000 0x30>; + clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>, + <&cmu_peri CLK_GOUT_SPI0_IPCLK>; + clock-names = "spi", "spi_busclk0"; + dmas = <&pdma0 5>, <&pdma0 4>; + dma-names = "tx", "rx"; + interrupts = ; + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; + num-cs = <1>; + samsung,spi-src-clk = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; usi_cmgp0: usi@11d000c0 { @@ -769,6 +797,24 @@ clock-names = "uart", "clk_uart_baud0"; status = "disabled"; }; + + spi_1: spi@11d00000 { + compatible = "samsung,exynos850-spi"; + reg = <0x11d00000 0x30>; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; + clock-names = "spi", "spi_busclk0"; + dmas = <&pdma0 12>, <&pdma0 13>; + dma-names = "tx", "rx"; + interrupts = ; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + num-cs = <1>; + samsung,spi-src-clk = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; usi_cmgp1: usi@11d200c0 { @@ -810,6 +856,24 @@ clock-names = "uart", "clk_uart_baud0"; status = "disabled"; }; + + spi_2: spi@11d20000 { + compatible = "samsung,exynos850-spi"; + reg = <0x11d20000 0x30>; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; + clock-names = "spi", "spi_busclk0"; + dmas = <&pdma0 14>, <&pdma0 15>; + dma-names = "tx", "rx"; + interrupts = ; + pinctrl-0 = <&spi2_pins>; + pinctrl-names = "default"; + num-cs = <1>; + samsung,spi-src-clk = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; }; }; diff --git a/src/arm64/exynos/google/gs101-oriole.dts b/src/arm64/exynos/google/gs101-oriole.dts index 4a71f752200..6ccade2c8cb 100644 --- a/src/arm64/exynos/google/gs101-oriole.dts +++ b/src/arm64/exynos/google/gs101-oriole.dts @@ -63,6 +63,20 @@ clock-frequency = <200000000>; }; +&hsi2c_8 { + status = "okay"; + + eeprom: eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + }; +}; + +&hsi2c_12 { + status = "okay"; + /* TODO: add the devices once drivers exist */ +}; + &pinctrl_far_alive { key_voldown: key-voldown-pins { samsung,pins = "gpa7-3"; @@ -99,6 +113,16 @@ status = "okay"; }; +&usi8 { + samsung,mode = ; + status = "okay"; +}; + +&usi12 { + samsung,mode = ; + status = "okay"; +}; + &watchdog_cl0 { timeout-sec = <30>; status = "okay"; diff --git a/src/arm64/exynos/google/gs101-pinctrl.dtsi b/src/arm64/exynos/google/gs101-pinctrl.dtsi index e6a9776d4d6..a675f822ace 100644 --- a/src/arm64/exynos/google/gs101-pinctrl.dtsi +++ b/src/arm64/exynos/google/gs101-pinctrl.dtsi @@ -251,7 +251,7 @@ #interrupt-cells = <2>; }; - pcie0_clkreq: pcie0-clkreq-pins{ + pcie0_clkreq: pcie0-clkreq-pins { samsung,pins = "gph0-1"; samsung,pin-function = ; samsung,pin-pud = ; diff --git a/src/arm64/exynos/google/gs101.dtsi b/src/arm64/exynos/google/gs101.dtsi index d838e3a7af6..55e6bcb3689 100644 --- a/src/arm64/exynos/google/gs101.dtsi +++ b/src/arm64/exynos/google/gs101.dtsi @@ -73,7 +73,7 @@ compatible = "arm,cortex-a55"; reg = <0x0000>; enable-method = "psci"; - cpu-idle-states = <&ANANKE_CPU_SLEEP>; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; capacity-dmips-mhz = <250>; dynamic-power-coefficient = <70>; }; @@ -83,7 +83,7 @@ compatible = "arm,cortex-a55"; reg = <0x0100>; enable-method = "psci"; - cpu-idle-states = <&ANANKE_CPU_SLEEP>; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; capacity-dmips-mhz = <250>; dynamic-power-coefficient = <70>; }; @@ -93,7 +93,7 @@ compatible = "arm,cortex-a55"; reg = <0x0200>; enable-method = "psci"; - cpu-idle-states = <&ANANKE_CPU_SLEEP>; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; capacity-dmips-mhz = <250>; dynamic-power-coefficient = <70>; }; @@ -103,7 +103,7 @@ compatible = "arm,cortex-a55"; reg = <0x0300>; enable-method = "psci"; - cpu-idle-states = <&ANANKE_CPU_SLEEP>; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; capacity-dmips-mhz = <250>; dynamic-power-coefficient = <70>; }; @@ -113,7 +113,7 @@ compatible = "arm,cortex-a76"; reg = <0x0400>; enable-method = "psci"; - cpu-idle-states = <&ENYO_CPU_SLEEP>; + cpu-idle-states = <&ENYO_CPU_SLEEP>; capacity-dmips-mhz = <620>; dynamic-power-coefficient = <284>; }; @@ -123,7 +123,7 @@ compatible = "arm,cortex-a76"; reg = <0x0500>; enable-method = "psci"; - cpu-idle-states = <&ENYO_CPU_SLEEP>; + cpu-idle-states = <&ENYO_CPU_SLEEP>; capacity-dmips-mhz = <620>; dynamic-power-coefficient = <284>; }; @@ -133,7 +133,7 @@ compatible = "arm,cortex-x1"; reg = <0x0600>; enable-method = "psci"; - cpu-idle-states = <&HERA_CPU_SLEEP>; + cpu-idle-states = <&HERA_CPU_SLEEP>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <650>; }; @@ -143,7 +143,7 @@ compatible = "arm,cortex-x1"; reg = <0x0700>; enable-method = "psci"; - cpu-idle-states = <&HERA_CPU_SLEEP>; + cpu-idle-states = <&HERA_CPU_SLEEP>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <650>; }; @@ -180,14 +180,6 @@ }; }; - /* TODO replace with CCF clock */ - dummy_clk: clock-3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12345>; - clock-output-names = "pclk"; - }; - /* ect node is required to be present by bootloader */ ect { }; @@ -292,6 +284,26 @@ clock-names = "bus", "sss"; }; + timer@10050000 { + compatible = "google,gs101-mct", + "samsung,exynos4210-mct"; + reg = <0x10050000 0x800>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&ext_24_5m>, <&cmu_misc CLK_GOUT_MISC_MCT_PCLK>; + clock-names = "fin_pll", "mct"; + }; + watchdog_cl0: watchdog@10060000 { compatible = "google,gs101-wdt"; reg = <0x10060000 0x100>; @@ -339,9 +351,20 @@ }; }; + cmu_peric0: clock-controller@10800000 { + compatible = "google,gs101-cmu-peric0"; + reg = <0x10800000 0x4000>; + #clock-cells = <1>; + clocks = <&ext_24_5m>, + <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC0_IP>; + clock-names = "oscclk", "bus", "ip"; + }; + sysreg_peric0: syscon@10820000 { compatible = "google,gs101-peric0-sysreg", "syscon"; reg = <0x10820000 0x10000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK>; }; pinctrl_peric0: pinctrl@10840000 { @@ -350,6 +373,35 @@ interrupts = ; }; + usi8: usi@109700c0 { + compatible = "google,gs101-usi", + "samsung,exynos850-usi"; + reg = <0x109700c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x101c>; + status = "disabled"; + + hsi2c_8: i2c@10970000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10970000 0xc0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c8_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + }; + usi_uart: usi@10a000c0 { compatible = "google,gs101-usi", "samsung,exynos850-usi"; @@ -357,7 +409,8 @@ ranges; #address-cells = <1>; #size-cells = <1>; - clocks = <&dummy_clk>, <&dummy_clk>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric0 0x1020>; samsung,mode = ; @@ -366,19 +419,30 @@ serial_0: serial@10a00000 { compatible = "google,gs101-uart"; reg = <0x10a00000 0xc0>; - reg-io-width = <4>; interrupts = ; - clocks = <&dummy_clk 0>, <&dummy_clk 0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <256>; status = "disabled"; }; }; + cmu_peric1: clock-controller@10c00000 { + compatible = "google,gs101-cmu-peric1"; + reg = <0x10c00000 0x4000>; + #clock-cells = <1>; + clocks = <&ext_24_5m>, + <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC1_IP>; + clock-names = "oscclk", "bus", "ip"; + }; + sysreg_peric1: syscon@10c20000 { compatible = "google,gs101-peric1-sysreg", "syscon"; reg = <0x10c20000 0x10000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK>; }; pinctrl_peric1: pinctrl@10c40000 { @@ -387,6 +451,35 @@ interrupts = ; }; + usi12: usi@10d500c0 { + compatible = "google,gs101-usi", + "samsung,exynos850-usi"; + reg = <0x10d500c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1010>; + status = "disabled"; + + hsi2c_12: i2c@10d50000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10d50000 0xc0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&hsi2c12_bus>; + pinctrl-names = "default"; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + }; + pinctrl_hsi1: pinctrl@11840000 { compatible = "google,gs101-pinctrl"; reg = <0x11840000 0x00001000>; diff --git a/src/arm64/freescale/fsl-ls1012a.dtsi b/src/arm64/freescale/fsl-ls1012a.dtsi index 1e3fe3897b5..fe9093b3c02 100644 --- a/src/arm64/freescale/fsl-ls1012a.dtsi +++ b/src/arm64/freescale/fsl-ls1012a.dtsi @@ -290,7 +290,7 @@ dcfg: dcfg@1ee0000 { compatible = "fsl,ls1012a-dcfg", "syscon"; - reg = <0x0 0x1ee0000 0x0 0x10000>; + reg = <0x0 0x1ee0000 0x0 0x1000>; big-endian; }; @@ -351,24 +351,26 @@ }; i2c0: i2c@2180000 { - compatible = "fsl,vf610-i2c"; + compatible = "fsl,ls1012a-i2c", "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2180000 0x0 0x10000>; interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; + scl-gpios = <&gpio0 2 0>; status = "disabled"; }; i2c1: i2c@2190000 { - compatible = "fsl,vf610-i2c"; + compatible = "fsl,ls1012a-i2c", "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2190000 0x0 0x10000>; interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; + scl-gpios = <&gpio0 13 0>; status = "disabled"; }; @@ -499,6 +501,7 @@ snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; }; sata: sata@3200000 { @@ -550,6 +553,7 @@ <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; + big-endian; status = "disabled"; }; diff --git a/src/arm64/freescale/fsl-ls1046a.dtsi b/src/arm64/freescale/fsl-ls1046a.dtsi index 1515cec2314..754a64be739 100644 --- a/src/arm64/freescale/fsl-ls1046a.dtsi +++ b/src/arm64/freescale/fsl-ls1046a.dtsi @@ -485,7 +485,6 @@ <0x00030005 0x00000042>, <0x00030006 0x0000004c>, <0x00030007 0x00000056>; - big-endian; #thermal-sensor-cells = <1>; }; diff --git a/src/arm64/freescale/fsl-ls1088a.dtsi b/src/arm64/freescale/fsl-ls1088a.dtsi index 8616d5e0c38..604bf88d70b 100644 --- a/src/arm64/freescale/fsl-ls1088a.dtsi +++ b/src/arm64/freescale/fsl-ls1088a.dtsi @@ -591,6 +591,8 @@ reg = <0x00 0x03400000 0x0 0x00100000>, <0x20 0x00000000 0x8 0x00000000>; reg-names = "regs", "addr_space"; + interrupts = ; /* PME interrupt */ + interrupt-names = "pme"; num-ib-windows = <24>; num-ob-windows = <256>; max-functions = /bits/ 8 <2>; @@ -628,6 +630,8 @@ reg = <0x00 0x03500000 0x0 0x00100000>, <0x28 0x00000000 0x8 0x00000000>; reg-names = "regs", "addr_space"; + interrupts = ; /* PME interrupt */ + interrupt-names = "pme"; num-ib-windows = <6>; num-ob-windows = <6>; status = "disabled"; @@ -664,6 +668,8 @@ reg = <0x00 0x03600000 0x0 0x00100000>, <0x30 0x00000000 0x8 0x00000000>; reg-names = "regs", "addr_space"; + interrupts = ; /* PME interrupt */ + interrupt-names = "pme"; num-ib-windows = <6>; num-ob-windows = <6>; status = "disabled"; diff --git a/src/arm64/freescale/fsl-lx2160a.dtsi b/src/arm64/freescale/fsl-lx2160a.dtsi index 6640b49670a..e665c629e1a 100644 --- a/src/arm64/freescale/fsl-lx2160a.dtsi +++ b/src/arm64/freescale/fsl-lx2160a.dtsi @@ -949,34 +949,50 @@ }; uart0: serial@21c0000 { - compatible = "arm,sbsa-uart","arm,pl011"; + compatible = "arm,pl011", "arm,primecell"; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; + clock-names = "uartclk", "apb_pclk"; reg = <0x0 0x21c0000 0x0 0x1000>; interrupts = ; - current-speed = <115200>; status = "disabled"; }; uart1: serial@21d0000 { - compatible = "arm,sbsa-uart","arm,pl011"; + compatible = "arm,pl011", "arm,primecell"; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; + clock-names = "uartclk", "apb_pclk"; reg = <0x0 0x21d0000 0x0 0x1000>; interrupts = ; - current-speed = <115200>; status = "disabled"; }; uart2: serial@21e0000 { - compatible = "arm,sbsa-uart","arm,pl011"; + compatible = "arm,pl011", "arm,primecell"; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; + clock-names = "uartclk", "apb_pclk"; reg = <0x0 0x21e0000 0x0 0x1000>; interrupts = ; - current-speed = <115200>; status = "disabled"; }; uart3: serial@21f0000 { - compatible = "arm,sbsa-uart","arm,pl011"; + compatible = "arm,pl011", "arm,primecell"; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; + clock-names = "uartclk", "apb_pclk"; reg = <0x0 0x21f0000 0x0 0x1000>; interrupts = ; - current-speed = <115200>; status = "disabled"; }; diff --git a/src/arm64/freescale/imx8-apalis-eval-v1.1.dtsi b/src/arm64/freescale/imx8-apalis-eval-v1.1.dtsi new file mode 100644 index 00000000000..0f77f78f4d9 --- /dev/null +++ b/src/arm64/freescale/imx8-apalis-eval-v1.1.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 Toradex + */ + +#include "imx8-apalis-eval.dtsi" + +/* Apalis CAN1 */ +&flexcan1 { + status = "okay"; +}; + +/* Apalis CAN2 */ +&flexcan2 { + status = "okay"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + status = "okay"; +}; + +/* Apalis SD1 */ +&usdhc3 { + status = "okay"; +}; diff --git a/src/arm64/freescale/imx8-apalis-eval-v1.2.dtsi b/src/arm64/freescale/imx8-apalis-eval-v1.2.dtsi new file mode 100644 index 00000000000..f5c6a0164f3 --- /dev/null +++ b/src/arm64/freescale/imx8-apalis-eval-v1.2.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 Toradex + */ + +#include "imx8-apalis-eval.dtsi" + +/ { + reg_3v3_mmc: regulator-3v3-mmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_3v3_mmc>; + enable-active-high; + gpio = <&lsio_gpio5 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <100000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3.3V_MMC"; + startup-delay-us = <10000>; + }; + + reg_3v3_sd: regulator-3v3-sd { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_3v3_sd>; + enable-active-high; + gpio = <&lsio_gpio5 20 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <100000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3.3V_SD"; + startup-delay-us = <10000>; + }; + + reg_can1: regulator-can1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_can1_power>; + enable-active-high; + gpio = <&lsio_gpio5 22 GPIO_ACTIVE_HIGH>; + regulator-name = "5V_SW_CAN1"; + startup-delay-us = <10000>; + }; + + reg_can2: regulator-can2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_can2_power>; + enable-active-high; + gpio = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; + regulator-name = "5V_SW_CAN2"; + startup-delay-us = <10000>; + }; +}; + +/* Apalis CAN1 */ +&flexcan1 { + xceiver-supply = <®_can1>; + status = "okay"; +}; + +/* Apalis CAN2 */ +&flexcan2 { + xceiver-supply = <®_can2>; + status = "okay"; +}; + +/* Apalis I2C1 */ +&i2c2 { + status = "okay"; + + /* Power/Current Measurement Sensor */ + hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + + temperature-sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + }; +}; + +/* Apalis MMC1 */ +&usdhc2 { + pinctrl-0 = <&pinctrl_usdhc2_4bit>, <&pinctrl_mmc1_cd>; + pinctrl-1 = <&pinctrl_usdhc2_4bit_100mhz>, <&pinctrl_mmc1_cd>; + pinctrl-2 = <&pinctrl_usdhc2_4bit_200mhz>, <&pinctrl_mmc1_cd>; + pinctrl-3 = <&pinctrl_usdhc2_4bit_sleep>, <&pinctrl_mmc1_cd_sleep>; + bus-width = <4>; + vmmc-supply = <®_3v3_mmc>; + status = "okay"; +}; + +/* Apalis SD1 */ +&usdhc3 { + vmmc-supply = <®_3v3_sd>; + status = "okay"; +}; + +&iomuxc { + + pinctrl_enable_3v3_mmc: enable3v3mmcgrp { + fsl,pins = ; /* MXM3_148 */ + }; + + pinctrl_enable_3v3_sd: enable3v3sdgrp { + fsl,pins = ; /* MXM3_152 */ + }; + + pinctrl_enable_can1_power: enablecan1powergrp { + fsl,pins = ; /* MXM3_158 */ + }; + + pinctrl_enable_can2_power: enablecan2powergrp { + fsl,pins = ; /* MXM3_156 */ + }; +}; diff --git a/src/arm64/freescale/imx8-apalis-eval.dtsi b/src/arm64/freescale/imx8-apalis-eval.dtsi index 685d4294f4f..deecb96a159 100644 --- a/src/arm64/freescale/imx8-apalis-eval.dtsi +++ b/src/arm64/freescale/imx8-apalis-eval.dtsi @@ -35,18 +35,6 @@ status = "okay"; }; -/* Apalis CAN1 */ -&flexcan1 { - status = "okay"; -}; - -/* Apalis CAN2 */ -&flexcan2 { - status = "okay"; -}; - -/* TODO: GPU */ - /* Apalis I2C1 */ &i2c2 { status = "okay"; @@ -132,13 +120,3 @@ }; /* TODO: Apalis USBH4 SuperSpeed */ - -/* Apalis MMC1 */ -&usdhc2 { - status = "okay"; -}; - -/* Apalis SD1 */ -&usdhc3 { - status = "okay"; -}; diff --git a/src/arm64/freescale/imx8-apalis-v1.1.dtsi b/src/arm64/freescale/imx8-apalis-v1.1.dtsi index f69b0c17560..160153853b6 100644 --- a/src/arm64/freescale/imx8-apalis-v1.1.dtsi +++ b/src/arm64/freescale/imx8-apalis-v1.1.dtsi @@ -261,7 +261,6 @@ reset-assert-us = <2>; reset-deassert-us = <2>; reset-gpios = <&lsio_gpio1 11 GPIO_ACTIVE_LOW>; - reset-names = "phy"; }; }; }; diff --git a/src/arm64/freescale/imx8-ss-audio.dtsi b/src/arm64/freescale/imx8-ss-audio.dtsi index f057c6b21b3..07afeb78ed5 100644 --- a/src/arm64/freescale/imx8-ss-audio.dtsi +++ b/src/arm64/freescale/imx8-ss-audio.dtsi @@ -4,6 +4,7 @@ * Dong Aisheng */ +#include #include #include @@ -14,12 +15,174 @@ audio_ipg_clk: clock-audio-ipg { clock-output-names = "audio_ipg_clk"; }; +clk_ext_aud_mclk0: clock-ext-aud-mclk0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ext_aud_mclk0"; +}; + +clk_ext_aud_mclk1: clock-ext-aud-mclk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ext_aud_mclk1"; +}; + +clk_esai0_rx_clk: clock-esai0-rx { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "esai0_rx_clk"; +}; + +clk_esai0_rx_hf_clk: clock-esai0-rx-hf { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "esai0_rx_hf_clk"; +}; + +clk_esai0_tx_clk: clock-esai0-tx { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "esai0_tx_clk"; +}; + +clk_esai0_tx_hf_clk: clock-esai0-tx-hf { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "esai0_tx_hf_clk"; +}; + +clk_spdif0_rx: clock-spdif0-rx { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "spdif0_rx"; +}; + +clk_sai0_rx_bclk: clock-sai0-rx-bclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai0_rx_bclk"; +}; + +clk_sai0_tx_bclk: clock-sai0-tx-bclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai0_tx_bclk"; +}; + +clk_sai1_rx_bclk: clock-sai1-rx-bclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai1_rx_bclk"; +}; + +clk_sai1_tx_bclk: clock-sai1-tx-bclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai1_tx_bclk"; +}; + +clk_sai2_rx_bclk: clock-sai2-rx-bclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai2_rx_bclk"; +}; + +clk_sai3_rx_bclk: clock-sai3-rx-bclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai3_rx_bclk"; +}; + +clk_sai4_rx_bclk: clock-sai4-rx-bclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai4_rx_bclk"; +}; + audio_subsys: bus@59000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x59000000 0x0 0x59000000 0x1000000>; + sai0: sai@59040000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59040000 0x10000>; + interrupts = ; + clocks = <&sai0_lpcg 1>, + <&clk_dummy>, + <&sai0_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma0 12 0 1>, <&edma0 13 0 0>; + power-domains = <&pd IMX_SC_R_SAI_0>; + status = "disabled"; + }; + + sai1: sai@59050000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59050000 0x10000>; + interrupts = ; + clocks = <&sai1_lpcg 1>, + <&clk_dummy>, + <&sai1_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma0 14 0 1>, <&edma0 15 0 0>; + power-domains = <&pd IMX_SC_R_SAI_1>; + status = "disabled"; + }; + + sai2: sai@59060000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59060000 0x10000>; + interrupts = ; + clocks = <&sai2_lpcg 1>, + <&clk_dummy>, + <&sai2_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx"; + dmas = <&edma0 16 0 1>; + power-domains = <&pd IMX_SC_R_SAI_2>; + status = "disabled"; + }; + + sai3: sai@59070000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59070000 0x10000>; + interrupts = ; + clocks = <&sai3_lpcg 1>, + <&clk_dummy>, + <&sai3_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx"; + dmas = <&edma0 17 0 1>; + power-domains = <&pd IMX_SC_R_SAI_3>; + status = "disabled"; + }; + edma0: dma-controller@591f0000 { compatible = "fsl,imx8qm-edma"; reg = <0x591f0000 0x190000>; @@ -76,6 +239,54 @@ audio_subsys: bus@59000000 { <&pd IMX_SC_R_DMA_0_CH23>; }; + sai0_lpcg: clock-controller@59440000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59440000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI0_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "sai0_lpcg_mclk", + "sai0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_0>; + }; + + sai1_lpcg: clock-controller@59450000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59450000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI1_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "sai1_lpcg_mclk", + "sai1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_1>; + }; + + sai2_lpcg: clock-controller@59460000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59460000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI2_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "sai2_lpcg_mclk", + "sai2_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_2>; + }; + + sai3_lpcg: clock-controller@59470000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59470000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI3_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "sai3_lpcg_mclk", + "sai3_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_3>; + }; + dsp_lpcg: clock-controller@59580000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x59580000 0x10000>; @@ -151,4 +362,123 @@ audio_subsys: bus@59000000 { <&pd IMX_SC_R_DMA_1_CH9>, <&pd IMX_SC_R_DMA_1_CH10>; }; + + aud_rec0_lpcg: clock-controller@59d00000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d00000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; + clock-indices = ; + clock-output-names = "aud_rec_clk0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>; + }; + + aud_rec1_lpcg: clock-controller@59d10000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d10000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>; + clock-indices = ; + clock-output-names = "aud_rec_clk1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>; + }; + + aud_pll_div0_lpcg: clock-controller@59d20000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d20000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>; + clock-indices = ; + clock-output-names = "aud_pll_div_clk0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>; + }; + + aud_pll_div1_lpcg: clock-controller@59d30000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d30000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>; + clock-indices = ; + clock-output-names = "aud_pll_div_clk1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>; + }; + + mclkout0_lpcg: clock-controller@59d50000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d50000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_MCLKOUT0_SEL>; + clock-indices = ; + clock-output-names = "mclkout0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_MCLK_OUT_0>; + }; + + mclkout1_lpcg: clock-controller@59d60000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d60000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_MCLKOUT1_SEL>; + clock-indices = ; + clock-output-names = "mclkout1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_MCLK_OUT_1>; + }; + + acm: acm@59e00000 { + compatible = "fsl,imx8qxp-acm"; + reg = <0x59e00000 0x1d0000>; + #clock-cells = <1>; + power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_MCLK_OUT_0>, + <&pd IMX_SC_R_MCLK_OUT_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_ASRC_0>, + <&pd IMX_SC_R_ASRC_1>, + <&pd IMX_SC_R_ESAI_0>, + <&pd IMX_SC_R_SAI_0>, + <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_SAI_2>, + <&pd IMX_SC_R_SAI_3>, + <&pd IMX_SC_R_SAI_4>, + <&pd IMX_SC_R_SAI_5>, + <&pd IMX_SC_R_SPDIF_0>, + <&pd IMX_SC_R_MQS_0>; + clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>, + <&aud_rec1_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, + <&clk_ext_aud_mclk0>, + <&clk_ext_aud_mclk1>, + <&clk_esai0_rx_clk>, + <&clk_esai0_rx_hf_clk>, + <&clk_esai0_tx_clk>, + <&clk_esai0_tx_hf_clk>, + <&clk_spdif0_rx>, + <&clk_sai0_rx_bclk>, + <&clk_sai0_tx_bclk>, + <&clk_sai1_rx_bclk>, + <&clk_sai1_tx_bclk>, + <&clk_sai2_rx_bclk>, + <&clk_sai3_rx_bclk>, + <&clk_sai4_rx_bclk>; + clock-names = "aud_rec_clk0_lpcg_clk", + "aud_rec_clk1_lpcg_clk", + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "ext_aud_mclk0", + "ext_aud_mclk1", + "esai0_rx_clk", + "esai0_rx_hf_clk", + "esai0_tx_clk", + "esai0_tx_hf_clk", + "spdif0_rx", + "sai0_rx_bclk", + "sai0_tx_bclk", + "sai1_rx_bclk", + "sai1_tx_bclk", + "sai2_rx_bclk", + "sai3_rx_bclk", + "sai4_rx_bclk"; + }; }; diff --git a/src/arm64/freescale/imx8-ss-conn.dtsi b/src/arm64/freescale/imx8-ss-conn.dtsi index 3c42240e78e..4aaf5a0c1ed 100644 --- a/src/arm64/freescale/imx8-ss-conn.dtsi +++ b/src/arm64/freescale/imx8-ss-conn.dtsi @@ -41,7 +41,7 @@ conn_subsys: bus@5b000000 { interrupts = ; fsl,usbphy = <&usbphy1>; fsl,usbmisc = <&usbmisc1 0>; - clocks = <&usb2_lpcg 0>; + clocks = <&usb2_lpcg IMX_LPCG_CLK_6>; ahb-burst-config = <0x0>; tx-burst-size-dword = <0x10>; rx-burst-size-dword = <0x10>; @@ -58,7 +58,7 @@ conn_subsys: bus@5b000000 { usbphy1: usbphy@5b100000 { compatible = "fsl,imx7ulp-usbphy"; reg = <0x5b100000 0x1000>; - clocks = <&usb2_lpcg 1>; + clocks = <&usb2_lpcg IMX_LPCG_CLK_7>; power-domains = <&pd IMX_SC_R_USB_0_PHY>; status = "disabled"; }; @@ -67,8 +67,8 @@ conn_subsys: bus@5b000000 { interrupts = ; reg = <0x5b010000 0x10000>; clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>, - <&sdhc0_lpcg IMX_LPCG_CLK_0>, - <&sdhc0_lpcg IMX_LPCG_CLK_5>; + <&sdhc0_lpcg IMX_LPCG_CLK_5>, + <&sdhc0_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "ahb", "per"; power-domains = <&pd IMX_SC_R_SDHC_0>; status = "disabled"; @@ -78,8 +78,8 @@ conn_subsys: bus@5b000000 { interrupts = ; reg = <0x5b020000 0x10000>; clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>, - <&sdhc1_lpcg IMX_LPCG_CLK_0>, - <&sdhc1_lpcg IMX_LPCG_CLK_5>; + <&sdhc1_lpcg IMX_LPCG_CLK_5>, + <&sdhc1_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "ahb", "per"; power-domains = <&pd IMX_SC_R_SDHC_1>; fsl,tuning-start-tap = <20>; @@ -91,8 +91,8 @@ conn_subsys: bus@5b000000 { interrupts = ; reg = <0x5b030000 0x10000>; clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>, - <&sdhc2_lpcg IMX_LPCG_CLK_0>, - <&sdhc2_lpcg IMX_LPCG_CLK_5>; + <&sdhc2_lpcg IMX_LPCG_CLK_5>, + <&sdhc2_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "ahb", "per"; power-domains = <&pd IMX_SC_R_SDHC_2>; status = "disabled"; diff --git a/src/arm64/freescale/imx8-ss-dma.dtsi b/src/arm64/freescale/imx8-ss-dma.dtsi index b0bb77150ad..f7a91d43a0f 100644 --- a/src/arm64/freescale/imx8-ss-dma.dtsi +++ b/src/arm64/freescale/imx8-ss-dma.dtsi @@ -5,6 +5,7 @@ */ #include +#include #include dma_ipg_clk: clock-dma-ipg { @@ -27,8 +28,8 @@ dma_subsys: bus@5a000000 { #size-cells = <0>; interrupts = ; interrupt-parent = <&gic>; - clocks = <&spi0_lpcg 0>, - <&spi0_lpcg 1>; + clocks = <&spi0_lpcg IMX_LPCG_CLK_0>, + <&spi0_lpcg IMX_LPCG_CLK_4>; clock-names = "per", "ipg"; assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <60000000>; @@ -43,8 +44,8 @@ dma_subsys: bus@5a000000 { #size-cells = <0>; interrupts = ; interrupt-parent = <&gic>; - clocks = <&spi1_lpcg 0>, - <&spi1_lpcg 1>; + clocks = <&spi1_lpcg IMX_LPCG_CLK_0>, + <&spi1_lpcg IMX_LPCG_CLK_4>; clock-names = "per", "ipg"; assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <60000000>; @@ -59,8 +60,8 @@ dma_subsys: bus@5a000000 { #size-cells = <0>; interrupts = ; interrupt-parent = <&gic>; - clocks = <&spi2_lpcg 0>, - <&spi2_lpcg 1>; + clocks = <&spi2_lpcg IMX_LPCG_CLK_0>, + <&spi2_lpcg IMX_LPCG_CLK_4>; clock-names = "per", "ipg"; assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <60000000>; @@ -75,8 +76,8 @@ dma_subsys: bus@5a000000 { #size-cells = <0>; interrupts = ; interrupt-parent = <&gic>; - clocks = <&spi3_lpcg 0>, - <&spi3_lpcg 1>; + clocks = <&spi3_lpcg IMX_LPCG_CLK_0>, + <&spi3_lpcg IMX_LPCG_CLK_4>; clock-names = "per", "ipg"; assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <60000000>; @@ -93,8 +94,8 @@ dma_subsys: bus@5a000000 { assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <80000000>; power-domains = <&pd IMX_SC_R_UART_0>; - dma-names = "tx","rx"; - dmas = <&edma2 9 0 0>, <&edma2 8 0 1>; + dma-names = "rx", "tx"; + dmas = <&edma2 8 0 FSL_EDMA_RX>, <&edma2 9 0 0>; status = "disabled"; }; @@ -107,8 +108,8 @@ dma_subsys: bus@5a000000 { assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <80000000>; power-domains = <&pd IMX_SC_R_UART_1>; - dma-names = "tx","rx"; - dmas = <&edma2 11 0 0>, <&edma2 10 0 1>; + dma-names = "rx", "tx"; + dmas = <&edma2 10 0 FSL_EDMA_RX>, <&edma2 11 0 0>; status = "disabled"; }; @@ -121,8 +122,8 @@ dma_subsys: bus@5a000000 { assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <80000000>; power-domains = <&pd IMX_SC_R_UART_2>; - dma-names = "tx","rx"; - dmas = <&edma2 13 0 0>, <&edma2 12 0 1>; + dma-names = "rx", "tx"; + dmas = <&edma2 12 0 FSL_EDMA_RX>, <&edma2 13 0 0>; status = "disabled"; }; @@ -135,8 +136,8 @@ dma_subsys: bus@5a000000 { assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <80000000>; power-domains = <&pd IMX_SC_R_UART_3>; - dma-names = "tx","rx"; - dmas = <&edma2 15 0 0>, <&edma2 14 0 1>; + dma-names = "rx", "tx"; + dmas = <&edma2 14 0 FSL_EDMA_RX>, <&edma2 15 0 0>; status = "disabled"; }; @@ -144,8 +145,8 @@ dma_subsys: bus@5a000000 { compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; reg = <0x5a190000 0x1000>; interrupts = ; - clocks = <&adma_pwm_lpcg 1>, - <&adma_pwm_lpcg 0>; + clocks = <&adma_pwm_lpcg IMX_LPCG_CLK_4>, + <&adma_pwm_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "per"; assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; @@ -192,29 +193,6 @@ dma_subsys: bus@5a000000 { <&pd IMX_SC_R_DMA_2_CH15>; }; - edma3: dma-controller@5a9f0000 { - compatible = "fsl,imx8qm-edma"; - reg = <0x5a9f0000 0x90000>; - #dma-cells = <3>; - dma-channels = <8>; - interrupts = , - , - , - , - , - , - , - ; - power-domains = <&pd IMX_SC_R_DMA_3_CH0>, - <&pd IMX_SC_R_DMA_3_CH1>, - <&pd IMX_SC_R_DMA_3_CH2>, - <&pd IMX_SC_R_DMA_3_CH3>, - <&pd IMX_SC_R_DMA_3_CH4>, - <&pd IMX_SC_R_DMA_3_CH5>, - <&pd IMX_SC_R_DMA_3_CH6>, - <&pd IMX_SC_R_DMA_3_CH7>; - }; - spi0_lpcg: clock-controller@5a400000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5a400000 0x10000>; @@ -377,8 +355,8 @@ dma_subsys: bus@5a000000 { reg = <0x5a880000 0x10000>; interrupts = ; interrupt-parent = <&gic>; - clocks = <&adc0_lpcg 0>, - <&adc0_lpcg 1>; + clocks = <&adc0_lpcg IMX_LPCG_CLK_0>, + <&adc0_lpcg IMX_LPCG_CLK_4>; clock-names = "per", "ipg"; assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; @@ -392,8 +370,8 @@ dma_subsys: bus@5a000000 { reg = <0x5a890000 0x10000>; interrupts = ; interrupt-parent = <&gic>; - clocks = <&adc1_lpcg 0>, - <&adc1_lpcg 1>; + clocks = <&adc1_lpcg IMX_LPCG_CLK_0>, + <&adc1_lpcg IMX_LPCG_CLK_4>; clock-names = "per", "ipg"; assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; @@ -406,8 +384,8 @@ dma_subsys: bus@5a000000 { reg = <0x5a8d0000 0x10000>; interrupts = ; interrupt-parent = <&gic>; - clocks = <&can0_lpcg 1>, - <&can0_lpcg 0>; + clocks = <&can0_lpcg IMX_LPCG_CLK_4>, + <&can0_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "per"; assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <40000000>; @@ -427,8 +405,8 @@ dma_subsys: bus@5a000000 { * CAN1 shares CAN0's clock and to enable CAN0's clock it * has to be powered on. */ - clocks = <&can0_lpcg 1>, - <&can0_lpcg 0>; + clocks = <&can0_lpcg IMX_LPCG_CLK_4>, + <&can0_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "per"; assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <40000000>; @@ -448,8 +426,8 @@ dma_subsys: bus@5a000000 { * CAN2 shares CAN0's clock and to enable CAN0's clock it * has to be powered on. */ - clocks = <&can0_lpcg 1>, - <&can0_lpcg 0>; + clocks = <&can0_lpcg IMX_LPCG_CLK_4>, + <&can0_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "per"; assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <40000000>; @@ -460,6 +438,29 @@ dma_subsys: bus@5a000000 { status = "disabled"; }; + edma3: dma-controller@5a9f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x5a9f0000 0x90000>; + #dma-cells = <3>; + dma-channels = <8>; + interrupts = , + , + , + , + , + , + , + ; + power-domains = <&pd IMX_SC_R_DMA_3_CH0>, + <&pd IMX_SC_R_DMA_3_CH1>, + <&pd IMX_SC_R_DMA_3_CH2>, + <&pd IMX_SC_R_DMA_3_CH3>, + <&pd IMX_SC_R_DMA_3_CH4>, + <&pd IMX_SC_R_DMA_3_CH5>, + <&pd IMX_SC_R_DMA_3_CH6>, + <&pd IMX_SC_R_DMA_3_CH7>; + }; + i2c0_lpcg: clock-controller@5ac00000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5ac00000 0x10000>; diff --git a/src/arm64/freescale/imx8-ss-gpu0.dtsi b/src/arm64/freescale/imx8-ss-gpu0.dtsi new file mode 100644 index 00000000000..9b8a44aa63d --- /dev/null +++ b/src/arm64/freescale/imx8-ss-gpu0.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng + */ + +#include + +gpu0_subsys: bus@53000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x53000000 0x0 0x53000000 0x1000000>; + + gpu_3d0: gpu@53100000 { + compatible = "vivante,gc"; + reg = <0x53100000 0x40000>; + interrupts = ; + clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>; + clock-names = "core", "shader"; + assigned-clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>; + assigned-clock-rates = <700000000>, <850000000>; + power-domains = <&pd IMX_SC_R_GPU_0_PID0>; + }; +}; diff --git a/src/arm64/freescale/imx8-ss-lsio.dtsi b/src/arm64/freescale/imx8-ss-lsio.dtsi index 7e510b21bba..764c1a08e3b 100644 --- a/src/arm64/freescale/imx8-ss-lsio.dtsi +++ b/src/arm64/freescale/imx8-ss-lsio.dtsi @@ -25,8 +25,8 @@ lsio_subsys: bus@5d000000 { compatible = "fsl,imx27-pwm"; reg = <0x5d000000 0x10000>; clock-names = "ipg", "per"; - clocks = <&pwm0_lpcg 4>, - <&pwm0_lpcg 1>; + clocks = <&pwm0_lpcg IMX_LPCG_CLK_6>, + <&pwm0_lpcg IMX_LPCG_CLK_1>; assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; #pwm-cells = <3>; @@ -38,8 +38,8 @@ lsio_subsys: bus@5d000000 { compatible = "fsl,imx27-pwm"; reg = <0x5d010000 0x10000>; clock-names = "ipg", "per"; - clocks = <&pwm1_lpcg 4>, - <&pwm1_lpcg 1>; + clocks = <&pwm1_lpcg IMX_LPCG_CLK_6>, + <&pwm1_lpcg IMX_LPCG_CLK_1>; assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; #pwm-cells = <3>; @@ -51,8 +51,8 @@ lsio_subsys: bus@5d000000 { compatible = "fsl,imx27-pwm"; reg = <0x5d020000 0x10000>; clock-names = "ipg", "per"; - clocks = <&pwm2_lpcg 4>, - <&pwm2_lpcg 1>; + clocks = <&pwm2_lpcg IMX_LPCG_CLK_6>, + <&pwm2_lpcg IMX_LPCG_CLK_1>; assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; #pwm-cells = <3>; @@ -64,8 +64,8 @@ lsio_subsys: bus@5d000000 { compatible = "fsl,imx27-pwm"; reg = <0x5d030000 0x10000>; clock-names = "ipg", "per"; - clocks = <&pwm3_lpcg 4>, - <&pwm3_lpcg 1>; + clocks = <&pwm3_lpcg IMX_LPCG_CLK_6>, + <&pwm3_lpcg IMX_LPCG_CLK_1>; assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; #pwm-cells = <3>; diff --git a/src/arm64/freescale/imx8dxl-evk.dts b/src/arm64/freescale/imx8dxl-evk.dts index b972658efb1..2123d431e06 100644 --- a/src/arm64/freescale/imx8dxl-evk.dts +++ b/src/arm64/freescale/imx8dxl-evk.dts @@ -81,6 +81,24 @@ status = "disabled"; }; + reg_can0_stby: regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "can0-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416_3 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can1_stby: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "can1-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416_3 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-3 { compatible = "regulator-fixed"; regulator-name = "SD1_SPWR"; @@ -261,12 +279,81 @@ }; }; +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pca6416_3: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&lsio_gpio2>; + interrupts = <5 IRQ_TYPE_EDGE_RISING>; + }; + + pca9548_2: i2c-mux@70 { + compatible = "nxp,pca9548"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + }; +}; + &lpuart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; status = "okay"; }; +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can0_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + &lsio_gpio4 { status = "okay"; }; @@ -436,6 +523,20 @@ >; }; + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX 0x00000021 + IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX 0x00000021 + >; + }; + + pinctrl_flexcan3: flexcan3grp { + fsl,pins = < + IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x00000021 + IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x00000021 + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 diff --git a/src/arm64/freescale/imx8dxl-ss-adma.dtsi b/src/arm64/freescale/imx8dxl-ss-adma.dtsi index 0a477f6318f..5d012c95222 100644 --- a/src/arm64/freescale/imx8dxl-ss-adma.dtsi +++ b/src/arm64/freescale/imx8dxl-ss-adma.dtsi @@ -15,6 +15,63 @@ interrupts = ; }; +&edma0 { + reg = <0x591f0000 0x1a0000>; + #dma-cells = <3>; + dma-channels = <25>; + dma-channel-mask = <0x1c0cc0>; + interrupts = , /* asrc 0 */ + , + , + , + , + , + , + , + , /* spdif0 */ + , + , + , + , /* sai0 */ + , + , /* sai1 */ + , + , /* sai2 */ + , /* sai3 */ + , + , + , + , /* gpt0 */ + , /* gpt1 */ + , /* gpt2 */ + ; /* gpt3 */ + power-domains = <&pd IMX_SC_R_DMA_0_CH0>, + <&pd IMX_SC_R_DMA_0_CH1>, + <&pd IMX_SC_R_DMA_0_CH2>, + <&pd IMX_SC_R_DMA_0_CH3>, + <&pd IMX_SC_R_DMA_0_CH4>, + <&pd IMX_SC_R_DMA_0_CH5>, + <&pd IMX_SC_R_DMA_0_CH6>, + <&pd IMX_SC_R_DMA_0_CH7>, + <&pd IMX_SC_R_DMA_0_CH8>, + <&pd IMX_SC_R_DMA_0_CH9>, + <&pd IMX_SC_R_DMA_0_CH10>, + <&pd IMX_SC_R_DMA_0_CH11>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>, + <&pd IMX_SC_R_DMA_0_CH16>, + <&pd IMX_SC_R_DMA_0_CH17>, + <&pd IMX_SC_R_DMA_0_CH18>, + <&pd IMX_SC_R_DMA_0_CH19>, + <&pd IMX_SC_R_DMA_0_CH20>, + <&pd IMX_SC_R_DMA_0_CH21>, + <&pd IMX_SC_R_DMA_0_CH22>, + <&pd IMX_SC_R_DMA_0_CH23>, + <&pd IMX_SC_R_DMA_0_CH24>; +}; + &edma2 { interrupts = , , @@ -45,24 +102,44 @@ ; }; +&flexcan1 { + interrupts = ; +}; + +&flexcan2 { + interrupts = ; +}; + +&flexcan3 { + interrupts = ; +}; + &i2c0 { compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; interrupts = ; + dma-names = "tx","rx"; + dmas = <&edma3 1 0 0>, <&edma3 0 0 FSL_EDMA_RX>; }; &i2c1 { compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; interrupts = ; + dma-names = "tx","rx"; + dmas = <&edma3 3 0 0>, <&edma3 2 0 FSL_EDMA_RX>; }; &i2c2 { compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; interrupts = ; + dma-names = "tx","rx"; + dmas = <&edma3 5 0 0>, <&edma3 4 0 FSL_EDMA_RX>; }; &i2c3 { compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; interrupts = ; + dma-names = "tx","rx"; + dmas = <&edma3 7 0 0>, <&edma3 6 0 FSL_EDMA_RX>; }; &lpuart0 { diff --git a/src/arm64/freescale/imx8dxl.dtsi b/src/arm64/freescale/imx8dxl.dtsi index f580eb6db9a..a0674c5c557 100644 --- a/src/arm64/freescale/imx8dxl.dtsi +++ b/src/arm64/freescale/imx8dxl.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include diff --git a/src/arm64/freescale/imx8dxp-tqma8xdp-mba8xx.dts b/src/arm64/freescale/imx8dxp-tqma8xdp-mba8xx.dts new file mode 100644 index 00000000000..f35514b7b33 --- /dev/null +++ b/src/arm64/freescale/imx8dxp-tqma8xdp-mba8xx.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR X11) +/* + * Copyright 2018-2023 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/dts-v1/; + +#include "imx8dxp-tqma8xdp.dtsi" +#include "mba8xx.dtsi" + +/ { + model = "TQ-Systems i.MX8DXP TQMa8XDP on MBa8Xx"; + compatible = "tq,imx8dxp-tqma8xdp-mba8xx", "tq,imx8dxp-tqma8xdp", "fsl,imx8dxp"; +}; diff --git a/src/arm64/freescale/imx8dxp-tqma8xdp.dtsi b/src/arm64/freescale/imx8dxp-tqma8xdp.dtsi new file mode 100644 index 00000000000..e2de8517aa0 --- /dev/null +++ b/src/arm64/freescale/imx8dxp-tqma8xdp.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR X11) +/* + * Copyright 2018-2023 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +#include "imx8dxp.dtsi" +#include "tqma8xx.dtsi" + +/ { + model = "TQ-Systems i.MX8DXP TQMa8XDP"; + compatible = "tq,imx8dxp-tqma8xdp", "fsl,imx8dxp"; +}; + +&pmic_thermal { + cooling-maps { + map0 { + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; diff --git a/src/arm64/freescale/imx8dxp.dtsi b/src/arm64/freescale/imx8dxp.dtsi new file mode 100644 index 00000000000..a8f7352332c --- /dev/null +++ b/src/arm64/freescale/imx8dxp.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + */ + +/dts-v1/; + +#include "imx8qxp.dtsi" + +/delete-node/ &A35_2; +/delete-node/ &A35_3; + +&thermal_zones { + cpu0-thermal { + cooling-maps { + map0 { + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/src/arm64/freescale/imx8mm-evk.dtsi b/src/arm64/freescale/imx8mm-evk.dtsi index b53104ed891..bd5b365867f 100644 --- a/src/arm64/freescale/imx8mm-evk.dtsi +++ b/src/arm64/freescale/imx8mm-evk.dtsi @@ -151,6 +151,28 @@ clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; }; }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + + pri-dai-link { + link-name = "micfil hifi"; + format = "i2s"; + + cpu { + sound-dai = <&micfil>; + }; + }; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif1>; + spdif-out; + spdif-in; + }; }; &A53_0 { @@ -434,6 +456,16 @@ status = "okay"; }; +&micfil { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MM_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <196608000>; + status = "okay"; +}; + &mipi_csi { status = "okay"; @@ -509,6 +541,24 @@ status = "okay"; }; +&spdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>, + <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", + "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", + "pll8k", "pll11k"; + status = "okay"; +}; + &uart2 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; @@ -636,6 +686,18 @@ >; }; + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 + MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6 + >; + }; + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 @@ -666,6 +728,13 @@ >; }; + pinctrl_spdif1: spdif1grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 + >; + }; + pinctrl_typec1: typec1grp { fsl,pins = < MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 diff --git a/src/arm64/freescale/imx8mm-kontron-bl-osm-s.dts b/src/arm64/freescale/imx8mm-kontron-bl-osm-s.dts index 8b16bd68576..33f8d7d1970 100644 --- a/src/arm64/freescale/imx8mm-kontron-bl-osm-s.dts +++ b/src/arm64/freescale/imx8mm-kontron-bl-osm-s.dts @@ -25,23 +25,21 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_led>; led1 { label = "led1"; - gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; }; led2 { label = "led2"; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; }; led3 { label = "led3"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; }; }; @@ -52,24 +50,12 @@ reg_rst_eth2: regulator-rst-eth2 { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_eth2>; - gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>; + gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-always-on; regulator-name = "rst-usb-eth2"; }; - reg_usb1_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb1_vbus>; - gpio = <&gpio3 25 GPIO_ACTIVE_LOW>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-name = "usb1-vbus"; - }; - reg_vdd_5v: regulator-5v { compatible = "regulator-fixed"; regulator-always-on; @@ -80,9 +66,6 @@ }; &ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; status = "okay"; can@0 { @@ -91,7 +74,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can>; clocks = <&osc_can>; - interrupts-extended = <&gpio4 28 IRQ_TYPE_LEVEL_LOW>; + interrupts-extended = <&gpio5 1 IRQ_TYPE_LEVEL_LOW>; /* * Limit the SPI clock to 15 MHz to prevent issues * with corrupted data due to chip errata. @@ -103,9 +86,6 @@ }; &ecspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; status = "okay"; eeram@0 { @@ -117,8 +97,8 @@ &fec1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-connection-type = "rgmii-rxid"; + pinctrl-0 = <&pinctrl_enet_rgmii>; + phy-connection-type = "rgmii-id"; phy-handle = <ðphy>; status = "okay"; @@ -127,55 +107,101 @@ #size-cells = <0>; ethphy: ethernet-phy@0 { + compatible = "ethernet-phy-id4f51.e91b"; reg = <0>; - reset-assert-us = <1>; - reset-deassert-us = <15000>; - reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; }; }; }; +/* + * Rename SoM signals according to board usage: + * GPIO_B_0 -> DIO1_OUT + * GPIO_B_1 -> DIO2_OUT + */ &gpio1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio1>; - gpio-line-names = "", "", "", "dio1-out", "", "", "dio1-in", "dio2-out", - "dio2-in", "dio3-out", "dio3-in", "dio4-out", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; + gpio-line-names = "", "GPIO_A_0", "", "GPIO_A_1", + "", "GPIO_A_2", "GPIO_A_3", "GPIO_A_4", + "GPIO_A_5", "GPIO_A_6", "GPIO_A_7", "DIO1_OUT", + "DIO2_OUT", "USB_A_OC#", "CAM_MCK", "USB_B_OC#", + "ETH_MDC", "ETH_MDIO", "ETH_A_(S)(R)(G)MII_TXD3", + "ETH_A_(S)(R)(G)MII_TXD2", "ETH_A_(S)(R)(G)MII_TXD1", + "ETH_A_(S)(R)(G)MII_TXD0", "ETH_A_(R)(G)MII_TX_EN(_ER)", + "ETH_A_(R)(G)MII_TX_CLK", "ETH_A_(R)(G)MII_RX_DV(_ER)", + "ETH_A_(R)(G)MII_RX_CLK", "ETH_A_(S)(R)(G)MII_RXD0", + "ETH_A_(S)(R)(G)MII_RXD1", "ETH_A_(R)(G)MII_RXD2", + "ETH_A_(R)(G)MII_RXD3"; }; -&gpio5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio5>; - gpio-line-names = "", "", "dio4-in", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; +/* + * Rename SoM signals according to board usage: + * GPIO_B_2 -> DIO3_OUT + * GPIO_B_3 -> DIO4_OUT + */ +&gpio3 { + gpio-line-names = "GPIO_C_5", "GPIO_C_4", "SDIO_B_CD#", "SDIO_B_D5", + "SDIO_B_D6", "SDIO_B_D7", "GPIO_C_0", "GPIO_C_1", + "GPIO_C_2", "GPIO_C_3", "SDIO_B_D0", "SDIO_B_D1", + "SDIO_B_D2", "SDIO_B_D3", "", "SDIO_B_D4", + "CARRIER_PWR_EN", "SDIO_B_CLK", "SDIO_B_CMD", "DIO3_OUT", + "USB_B_EN", "DIO4_OUT", "PCIe_CLKREQ#", "PCIe_A_PERST#", + "PCIe_WAKE#", "USB_A_EN"; }; -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; +/* + * Rename SoM signals according to board usage: + * GPIO_B_4 -> DIO1_IN + * GPIO_B_5 -> DIO2_IN + * GPIO_B_6 -> DIO3_IN + * GPIO_B_7 -> DIO4_IN + */ +&gpio4 { + gpio-line-names = "GPIO_C_7", "", "I2S_A_DATA_IN", "I2S_B_DATA_IN", + "DIO1_IN", "BOOT_SEL0#", "BOOT_SEL1#", "", + "", "", "I2S_LRCLK", "I2S_BITCLK", + "I2S_A_DATA_OUT", "I2S_B_DATA_OUT", "DIO2_IN", "DIO3_IN", + "DIO4_IN", "SPI_A_/WP_(IO2)", "SPI_A_/HOLD_(IO3)", "GPIO_C_6", + "I2S_MCLK", "UART_A_TX", "UART_A_RX", "UART_A_CTS", + "UART_A_RTS", "", "", "", + "PCIe_SM_ALERT", "UART_B_RTS", "UART_B_CTS", "UART_B_RX"; +}; + +&i2c3 { status = "okay"; + + usb-hub@2c { + compatible = "microchip,usb2514b"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_hub>; + reg = <0x2c>; + non-removable-ports = <0>, <3>; + reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + }; }; &pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; status = "okay"; }; +®_usb2_vbus { + status = "disabled"; +}; + +®_usdhc2_vcc { + status = "disabled"; +}; + +®_usdhc3_vcc { + status = "disabled"; +}; + &uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; uart-has-rtscts; status = "okay"; }; &uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; linux,rs485-enabled-at-boot-time; uart-has-rtscts; status = "okay"; @@ -183,8 +209,6 @@ &usbotg1 { dr_mode = "otg"; - disable-over-current; - vbus-supply = <®_usb1_vbus>; status = "okay"; }; @@ -195,14 +219,17 @@ #size-cells = <0>; status = "okay"; + /* VBUS is controlled by the hub */ + /delete-property/ vbus-supply; + usb1@1 { - compatible = "usb424,9514"; + compatible = "usb424,2514"; reg = <1>; #address-cells = <1>; #size-cells = <0>; usbnet: ethernet@1 { - compatible = "usb424,ec00"; + compatible = "usbb95,772b"; reg = <1>; local-mac-address = [ 00 00 00 00 00 00 ]; }; @@ -210,167 +237,20 @@ }; &usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; vmmc-supply = <®_vdd_3v3>; - vqmmc-supply = <®_nvcc_sd>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; status = "okay"; }; &iomuxc { pinctrl_can: cangrp { fsl,pins = < - MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 /* SDIO_B_PWR_EN */ >; }; - pinctrl_ecspi2: ecspi2grp { + pinctrl_usb_hub: usbhubgrp { fsl,pins = < - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 - MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 - MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 - MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 /* PHY RST */ - MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* ETH IRQ */ - >; - }; - - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 - MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19 - >; - }; - - pinctrl_gpio1: gpio1grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 - >; - }; - - pinctrl_gpio5: gpio5grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 - >; - }; - - pinctrl_reg_usb1_vbus: regusb1vbusgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140 - MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 - MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 - >; - }; - - pinctrl_usb_eth2: usbeth2grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 /* SDIO_B_WP */ >; }; }; diff --git a/src/arm64/freescale/imx8mm-kontron-bl.dts b/src/arm64/freescale/imx8mm-kontron-bl.dts index dcec57c2039..aab8e242165 100644 --- a/src/arm64/freescale/imx8mm-kontron-bl.dts +++ b/src/arm64/freescale/imx8mm-kontron-bl.dts @@ -279,8 +279,8 @@ pinctrl_i2c4: i2c4grp { fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000083 >; }; @@ -292,19 +292,19 @@ pinctrl_uart1: uart1grp { fsl,pins = < - MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140 - MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0 + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x0 + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x0 + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x0 >; }; pinctrl_uart2: uart2grp { fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 - MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0 + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0 + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0 + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0 >; }; @@ -316,40 +316,40 @@ pinctrl_usdhc2: usdhc2grp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 >; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 >; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 >; }; }; diff --git a/src/arm64/freescale/imx8mm-kontron-osm-s.dtsi b/src/arm64/freescale/imx8mm-kontron-osm-s.dtsi index 6e75ab879bf..663ae52b485 100644 --- a/src/arm64/freescale/imx8mm-kontron-osm-s.dtsi +++ b/src/arm64/freescale/imx8mm-kontron-osm-s.dtsi @@ -3,6 +3,7 @@ * Copyright (C) 2022 Kontron Electronics GmbH */ +#include #include #include "imx8mm.dtsi" @@ -28,6 +29,73 @@ chosen { stdout-path = &uart3; }; + + reg_vdd_carrier: regulator-vdd-carrier { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_vdd_carrier>; + gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + regulator-name = "VDD_CARRIER"; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + + regulator-state-disk { + regulator-off-in-suspend; + }; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb1_vbus>; + enable-active-high; + gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "VBUS_USB1"; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2_vbus>; + enable-active-high; + gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "VBUS_USB2"; + }; + + reg_usdhc2_vcc: regulator-usdhc2-vcc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vcc>; + enable-active-high; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "VCC_SDIO_A"; + }; + + reg_usdhc3_vcc: regulator-usdhc3-vcc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc3_vcc>; + enable-active-high; + gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "VCC_SDIO_B"; + }; }; &A53_0 { @@ -96,6 +164,79 @@ }; }; +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>, <&pinctrl_ecspi2_gpio>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>; + gpio-line-names = "", "GPIO_A_0", "", "GPIO_A_1", + "", "GPIO_A_2", "GPIO_A_3", "GPIO_A_4", + "GPIO_A_5", "GPIO_A_6", "GPIO_A_7", "GPIO_B_0", + "GPIO_B_1", "USB_A_OC#", "CAM_MCK", "USB_B_OC#", + "ETH_MDC", "ETH_MDIO", "ETH_A_(S)(R)(G)MII_TXD3", + "ETH_A_(S)(R)(G)MII_TXD2", "ETH_A_(S)(R)(G)MII_TXD1", + "ETH_A_(S)(R)(G)MII_TXD0", "ETH_A_(R)(G)MII_TX_EN(_ER)", + "ETH_A_(R)(G)MII_TX_CLK", "ETH_A_(R)(G)MII_RX_DV(_ER)", + "ETH_A_(R)(G)MII_RX_CLK", "ETH_A_(S)(R)(G)MII_RXD0", + "ETH_A_(S)(R)(G)MII_RXD1", "ETH_A_(R)(G)MII_RXD2", + "ETH_A_(R)(G)MII_RXD3"; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "SDIO_A_CD#", "SDIO_A_CLK", "SDIO_A_CMD", "SDIO_A_D0", + "SDIO_A_D1", "SDIO_A_D2", "SDIO_A_D3", "SDIO_A_PWR_EN", + "SDIO_A_WP"; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio3>; + gpio-line-names = "GPIO_C_5", "GPIO_C_4", "SDIO_B_CD#", "SDIO_B_D5", + "SDIO_B_D6", "SDIO_B_D7", "GPIO_C_0", "GPIO_C_1", + "GPIO_C_2", "GPIO_C_3", "SDIO_B_D0", "SDIO_B_D1", + "SDIO_B_D2", "SDIO_B_D3", "", "SDIO_B_D4", + "CARRIER_PWR_EN", "SDIO_B_CLK", "SDIO_B_CMD", "GPIO_B_2", + "USB_B_EN", "GPIO_B_3", "PCIe_CLKREQ#", "PCIe_A_PERST#", + "PCIe_WAKE#", "USB_A_EN"; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4>; + gpio-line-names = "GPIO_C_7", "", "I2S_A_DATA_IN", "I2S_B_DATA_IN", + "GPIO_B_4", "BOOT_SEL0#", "BOOT_SEL1#", "", + "", "", "I2S_LRCLK", "I2S_BITCLK", + "I2S_A_DATA_OUT", "I2S_B_DATA_OUT", "GPIO_B_5", "GPIO_B_6", + "GPIO_B_7", "SPI_A_/WP_(IO2)", "SPI_A_/HOLD_(IO3)", "GPIO_C_6", + "I2S_MCLK", "UART_A_TX", "UART_A_RX", "UART_A_CTS", + "UART_A_RTS", "", "", "", + "PCIe_SM_ALERT", "UART_B_RTS", "UART_B_CTS", "UART_B_RX"; +}; + +&gpio5 { + gpio-line-names = "UART_B_TX", "SDIO_B_PWR_EN", "SDIO_B_WP", "PWM_2", + "PWM_1", "PWM_0", "", "", + "", "", "SPI_A_SCK", "SPI_A_SDO_(IO1)", + "SPI_A_SCK", "SPI_A_CS0#", "", "", + "I2C_A_SCL", "I2C_A_SDA", "I2C_B_SCL", "I2C_B_SDA", + "PCIe_SMCLK", "PCIe_SMDAT", "SPI_B_SCK", "SPI_B_SDO", + "SPI_B_SDI", "SPI_B_CS0#", "UART_CON_RX", "UART_CON_TX", + "UART_C_RX", "UART_C_TX"; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -205,22 +346,86 @@ }; }; + eeprom: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + address-width = <16>; + pagesize = <32>; + size = <8192>; + }; + rv3028: rtc@52 { compatible = "microcrystal,rv3028"; reg = <0x52>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rtc>; - interrupts-extended = <&gpio4 1 IRQ_TYPE_LEVEL_HIGH>; - trickle-diode-disable; + interrupts-extended = <&gpio4 1 IRQ_TYPE_LEVEL_LOW>; }; }; +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + &uart3 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; status = "okay"; }; +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + vbus-supply = <®_usb1_vbus>; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + vbus-supply = <®_usb2_vbus>; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -233,6 +438,26 @@ status = "okay"; }; +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + vmmc-supply = <®_usdhc2_vcc>; + vqmmc-supply = <®_nvcc_sd>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>; + vmmc-supply = <®_usdhc3_vcc>; + vqmmc-supply = <®_nvcc_sd>; + cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; +}; + &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; @@ -241,6 +466,12 @@ }; &iomuxc { + pinctrl_csi_mck: csimckgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 /* CAM_MCK */ + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 @@ -250,10 +481,140 @@ >; }; + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 /* SPI_A_SDI_(IO0) */ + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 /* SPI_A_SDO_(IO1) */ + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 /* SPI_A_SCK */ + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 /* SPI_A_CS0# */ + >; + }; + + pinctrl_ecspi2_gpio: ecspi2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 /* SPI_A_/WP_(IO2) */ + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* SPI_A_/HOLD_(IO3) */ + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 /* SPI_B_SDI */ + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 /* SPI_B_SDO */ + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 /* SPI_B_SCK */ + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 /* SPI_B_CS0# */ + >; + }; + + pinctrl_enet_rgmii: enetrgmiigrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03 /* ETH_MDC */ + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03 /* ETH_MDIO */ + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f /* ETH_A_(S)(R)(G)MII_TXD3 */ + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f /* ETH_A_(S)(R)(G)MII_TXD2 */ + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f /* ETH_A_(S)(R)(G)MII_TXD1 */ + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f /* ETH_A_(S)(R)(G)MII_TXD0 */ + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 /* ETH_A_(R)(G)MII_RXD3 */ + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 /* ETH_A_(R)(G)MII_RXD2 */ + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 /* ETH_A_(S)(R)(G)MII_RXD1 */ + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 /* ETH_A_(S)(R)(G)MII_RXD0 */ + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f /* ETH_A_(R)(G)MII_TX_CLK */ + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 /* ETH_A_(R)(G)MII_RX_CLK */ + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 /* ETH_A_(R)(G)MII_RX_DV(_ER) */ + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f /* ETH_A_(R)(G)MII_TX_EN(_ER) */ + >; + }; + + pinctrl_enet_rmii: enetrmiigrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03 /* ETH_MDC */ + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03 /* ETH_MDIO */ + MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f /* ETH_A_(S)(R)(G)MII_TXD2 */ + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56 /* ETH_A_(S)(R)(G)MII_TXD1 */ + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56 /* ETH_A_(S)(R)(G)MII_TXD0 */ + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56 /* ETH_A_(S)(R)(G)MII_RXD1 */ + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56 /* ETH_A_(S)(R)(G)MII_RXD0 */ + MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56 /* ETH_A_(R)(G)MII_RX_CLK */ + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56 /* ETH_A_(R)(G)MII_RX_DV(_ER) */ + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56 /* ETH_A_(R)(G)MII_TX_EN(_ER) */ + >; + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 /* GPIO_A_0 */ + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* GPIO_A_1 */ + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* GPIO_A_2 */ + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 /* GPIO_A_3 */ + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 /* GPIO_A_4 */ + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 /* GPIO_A_5 */ + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 /* GPIO_A_6 */ + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* GPIO_A_7 */ + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* GPIO_B_0 */ + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 /* GPIO_B_1 */ + >; + }; + + pinctrl_gpio3: gpio3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* GPIO_C_5 */ + MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x19 /* GPIO_C_4 */ + MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* GPIO_C_0 */ + MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* GPIO_C_1 */ + MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* GPIO_C_2 */ + MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* GPIO_C_3 */ + MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 /* GPIO_B_2 */ + MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 /* GPIO_B_3 */ + >; + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* GPIO_C_7 */ + MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* GPIO_B_4 */ + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* BOOT_SEL0# */ + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* BOOT_SEL1# */ + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 /* GPIO_B_5 */ + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* GPIO_B_6 */ + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* GPIO_B_7 */ + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* GPIO_C_6 */ + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000083 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000083 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000083 /* I2C_A_SCL */ + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000083 /* I2C_A_SDA */ + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000083 /* I2C_B_SCL */ + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000083 /* I2C_B_SDA */ + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083 /* PCIe_SMCLK and I2C_CAM_SCL/CSI_TX_P */ + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000083 /* PCIe_SMDAT and I2C_CAM_SDA/CSI_TX_N */ + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 /* PCIe_CLKREQ# */ + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 /* PCIe_A_PERST# */ + MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x19 /* PCIe_WAKE# */ + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* PCIe_SM_ALERT */ >; }; @@ -263,16 +624,113 @@ >; }; + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x19 /* PWM_0 */ + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 /* PWM_1 */ + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x19 /* PWM_2 */ + >; + }; + + pinctrl_reg_usb1_vbus: regusb1vbusgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 /* USB_A_EN */ + >; + }; + + pinctrl_reg_usb2_vbus: regusb2vbusgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 /* USB_B_EN */ + >; + }; + + pinctrl_reg_usdhc2_vcc: regusdhc2vccgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x19 /* SDIO_A_PWR_EN */ + >; + }; + + pinctrl_reg_usdhc3_vcc: regusdhc3vccgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 /* SDIO_B_PWR_EN */ + >; + }; + + pinctrl_reg_vdd_carrier: regvddcarriergrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* CARRIER_PWR_EN */ + >; + }; + pinctrl_rtc: rtcgrp { fsl,pins = < MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 >; }; + pinctrl_sai1: sai1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6 /* I2S_A_DATA_IN */ + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 /* I2S_A_DATA_OUT */ + MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0xd6 /* I2S_B_DATA_IN */ + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 /* I2S_B_DATA_OUT */ + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 /* I2S_MCLK */ + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 /* I2S_LRCLK */ + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 /* I2S_BITCLK */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0 /* UART_A_RX */ + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x0 /* UART_A_TX */ + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x0 /* UART_A_CTS */ + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x0 /* UART_A_RTS */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0 /* UART_B_RX */ + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0 /* UART_B_TX */ + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0 /* UART_B_CTS */ + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0 /* UART_B_RTS */ + >; + }; + pinctrl_uart3: uart3grp { fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 /* UART_CON_RX */ + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 /* UART_CON_TX */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x0 /* UART_C_RX */ + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x0 /* UART_C_TX */ + >; + }; + + pinctrl_usb1: usb1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x19 /* USB_A_OC# */ + >; + }; + + pinctrl_usb2: usb2grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x19 /* USB_B_OC# */ >; }; @@ -327,6 +785,103 @@ >; }; + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90 /* SDIO_A_CLK */ + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 /* SDIO_A_CMD */ + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 /* SDIO_A_D0 */ + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 /* SDIO_A_D1 */ + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 /* SDIO_A_D2 */ + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 /* SDIO_A_D3 */ + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94 /* SDIO_A_CLK */ + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 /* SDIO_A_CMD */ + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 /* SDIO_A_D0 */ + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 /* SDIO_A_D1 */ + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 /* SDIO_A_D2 */ + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 /* SDIO_A_D3 */ + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96 /* SDIO_A_CLK */ + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 /* SDIO_A_CMD */ + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 /* SDIO_A_D0 */ + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 /* SDIO_A_D1 */ + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 /* SDIO_A_D2 */ + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 /* SDIO_A_D3 */ + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 /* SDIO_A_CD# */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x90 /* SDIO_B_CLK */ + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x90 /* SDIO_B_CMD */ + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x90 /* SDIO_B_D0 */ + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x90 /* SDIO_B_D1 */ + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x90 /* SDIO_B_D2 */ + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x90 /* SDIO_B_D3 */ + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x90 /* SDIO_B_D4 */ + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x90 /* SDIO_B_D5 */ + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x90 /* SDIO_B_D6 */ + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x90 /* SDIO_B_D7 */ + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x94 /* SDIO_B_CLK */ + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x94 /* SDIO_B_CMD */ + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x94 /* SDIO_B_D0 */ + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x94 /* SDIO_B_D1 */ + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x94 /* SDIO_B_D2 */ + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x94 /* SDIO_B_D3 */ + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x94 /* SDIO_B_D4 */ + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x94 /* SDIO_B_D5 */ + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x94 /* SDIO_B_D6 */ + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x94 /* SDIO_B_D7 */ + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x96 /* SDIO_B_CLK */ + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x96 /* SDIO_B_CMD */ + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x96 /* SDIO_B_D0 */ + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x96 /* SDIO_B_D1 */ + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x96 /* SDIO_B_D2 */ + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x96 /* SDIO_B_D3 */ + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x96 /* SDIO_B_D4 */ + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x96 /* SDIO_B_D5 */ + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x96 /* SDIO_B_D6 */ + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x96 /* SDIO_B_D7 */ + >; + }; + + pinctrl_usdhc3_gpio: usdhc3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 /* SDIO_B_CD# */ + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 /* SDIO_B_WP */ + >; + }; + pinctrl_wdog: wdoggrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 diff --git a/src/arm64/freescale/imx8mm-kontron-sl.dtsi b/src/arm64/freescale/imx8mm-kontron-sl.dtsi index 1f8326613ee..2076148e086 100644 --- a/src/arm64/freescale/imx8mm-kontron-sl.dtsi +++ b/src/arm64/freescale/imx8mm-kontron-sl.dtsi @@ -237,8 +237,8 @@ pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000083 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000083 >; }; diff --git a/src/arm64/freescale/imx8mm-tqma8mqml-mba8mx.dts b/src/arm64/freescale/imx8mm-tqma8mqml-mba8mx.dts index ea6e8b85169..01b632b220d 100644 --- a/src/arm64/freescale/imx8mm-tqma8mqml-mba8mx.dts +++ b/src/arm64/freescale/imx8mm-tqma8mqml-mba8mx.dts @@ -5,6 +5,8 @@ /dts-v1/; +#include + #include "imx8mm-tqma8mqml.dtsi" #include "mba8mx.dtsi" @@ -74,19 +76,23 @@ }; &pcie_phy { - clocks = <&pcie0_refclk>; + fsl,refclk-pad-mode = ; + fsl,clkreq-unsupported; + clocks = <&pcieclk 2>; + clock-names = "ref"; status = "okay"; }; +/* PCIe slot on X36 */ &pcie0 { reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcieclk 3>, <&clk IMX8MM_CLK_PCIE1_AUX>; assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; + <&clk IMX8MM_CLK_PCIE1_CTRL>; assigned-clock-rates = <10000000>, <250000000>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_250M>; + <&clk IMX8MM_SYS_PLL2_250M>; status = "okay"; }; diff --git a/src/arm64/freescale/imx8mm-venice-gw71xx.dtsi b/src/arm64/freescale/imx8mm-venice-gw71xx.dtsi index 6425773f68e..41c966147b9 100644 --- a/src/arm64/freescale/imx8mm-venice-gw71xx.dtsi +++ b/src/arm64/freescale/imx8mm-venice-gw71xx.dtsi @@ -47,25 +47,20 @@ gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; status = "okay"; }; - - reg_usb_otg1_vbus: regulator-usb-otg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb1_en>; - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; }; -/* off-board header */ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, + <&gpio1 10 GPIO_ACTIVE_LOW>; status = "okay"; + + tpm@1 { + compatible = "tcg,tpm_tis-spi"; + reg = <0x1>; + spi-max-frequency = <36000000>; + }; }; &gpio1 { @@ -144,9 +139,10 @@ }; &usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; dr_mode = "otg"; over-current-active-low; - vbus-supply = <®_usb_otg1_vbus>; status = "okay"; }; @@ -204,20 +200,13 @@ >; }; - pinctrl_reg_usb1_en: regusb1grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x141 - MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41 - >; - }; - pinctrl_spi2: spi2grp { fsl,pins = < MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6 >; }; @@ -234,4 +223,11 @@ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 >; }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x141 + MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41 + >; + }; }; diff --git a/src/arm64/freescale/imx8mm-venice-gw7901.dts b/src/arm64/freescale/imx8mm-venice-gw7901.dts index 87b80e2412c..5e2cbaf27e0 100644 --- a/src/arm64/freescale/imx8mm-venice-gw7901.dts +++ b/src/arm64/freescale/imx8mm-venice-gw7901.dts @@ -285,7 +285,8 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, + <&gpio4 24 GPIO_ACTIVE_LOW>; status = "okay"; flash@0 { @@ -294,6 +295,12 @@ spi-max-frequency = <40000000>; status = "okay"; }; + + tpm@1 { + compatible = "tcg,tpm_tis-spi"; + reg = <0x1>; + spi-max-frequency = <36000000>; + }; }; &fec1 { @@ -319,7 +326,7 @@ &gpio4 { gpio-line-names = "", "", "", "", - "", "", "uart3_rs232#", "uart3_rs422#", + "dig1_ctl", "dig2_ctl", "uart3_rs232#", "uart3_rs422#", "uart3_rs485#", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", ""; @@ -842,6 +849,8 @@ pinctrl_hog: hoggrp { fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIG1_CTL */ + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x40000041 /* DIG2_CTL */ MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */ @@ -987,6 +996,7 @@ MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140 + MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140 >; }; diff --git a/src/arm64/freescale/imx8mn-beacon-kit.dts b/src/arm64/freescale/imx8mn-beacon-kit.dts index 35b8d2060cd..bbd80896db9 100644 --- a/src/arm64/freescale/imx8mn-beacon-kit.dts +++ b/src/arm64/freescale/imx8mn-beacon-kit.dts @@ -99,8 +99,6 @@ }; &lcdif { - assigned-clocks = <&clk IMX8MN_VIDEO_PLL1>; - assigned-clock-rates = <594000000>; status = "okay"; }; diff --git a/src/arm64/freescale/imx8mn-evk.dtsi b/src/arm64/freescale/imx8mn-evk.dtsi index a0e13d3324e..269e70f66a1 100644 --- a/src/arm64/freescale/imx8mn-evk.dtsi +++ b/src/arm64/freescale/imx8mn-evk.dtsi @@ -110,6 +110,20 @@ spdif-out; spdif-in; }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + + pri-dai-link { + link-name = "micfil hifi"; + format = "i2s"; + + cpu { + sound-dai = <&micfil>; + }; + }; + }; }; &easrc { @@ -285,6 +299,16 @@ status = "okay"; }; +&micfil { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MN_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <196608000>; + status = "okay"; +}; + &mipi_csi { status = "okay"; @@ -522,6 +546,18 @@ >; }; + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 + MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0xd6 + MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0xd6 + MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0xd6 + MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0xd6 + >; + }; + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 diff --git a/src/arm64/freescale/imx8mn-rve-gateway.dts b/src/arm64/freescale/imx8mn-rve-gateway.dts index 1b633bd1ebb..ea1855171fb 100644 --- a/src/arm64/freescale/imx8mn-rve-gateway.dts +++ b/src/arm64/freescale/imx8mn-rve-gateway.dts @@ -10,7 +10,7 @@ / { model = "RVE gateway"; - compatible = "rve,rve-gateway", "variscite,var-som-mx8mn", "fsl,imx8mn"; + compatible = "rve,gateway", "variscite,var-som-mx8mn", "fsl,imx8mn"; crystal_duart_24m: crystal-duart-24m { compatible = "fixed-clock"; diff --git a/src/arm64/freescale/imx8mn-tqma8mqnl-mba8mx-usbotg.dtso b/src/arm64/freescale/imx8mn-tqma8mqnl-mba8mx-usbotg.dtso new file mode 100644 index 00000000000..96db07fc9be --- /dev/null +++ b/src/arm64/freescale/imx8mn-tqma8mqnl-mba8mx-usbotg.dtso @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2022-2024 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/dts-v1/; +/plugin/; + +#include + +#include "imx8mn-pinfunc.h" + +&{/} { + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + type = "micro"; + label = "X19"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_connector>; + id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; +}; + +&rst_usb_hub_hog { + output-low; +}; + +&sel_usb_hub_hog { + output-low; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + /delete-property/ disable-over-current; + over-current-active-low; + usb-role-switch; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; + }; +}; + +&iomuxc { + pinctrl_usb1_connector: usb1-connectorgrp { + fsl,pins = ; + }; +}; diff --git a/src/arm64/freescale/imx8mn-tqma8mqnl-mba8mx.dts b/src/arm64/freescale/imx8mn-tqma8mqnl-mba8mx.dts index c07d59147ab..433d8bba442 100644 --- a/src/arm64/freescale/imx8mn-tqma8mqnl-mba8mx.dts +++ b/src/arm64/freescale/imx8mn-tqma8mqnl-mba8mx.dts @@ -41,7 +41,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0hub_sel>; - sel-usb-hub-hog { + sel_usb_hub_hog: sel-usb-hub-hog { gpio-hog; gpios = <1 GPIO_ACTIVE_HIGH>; output-high; @@ -198,8 +198,7 @@ pinctrl_usbotg: usbotggrp { fsl,pins = , - , - ; + ; }; pinctrl_usdhc2: usdhc2grp { diff --git a/src/arm64/freescale/imx8mn.dtsi b/src/arm64/freescale/imx8mn.dtsi index 136e75c5125..932c8b05c75 100644 --- a/src/arm64/freescale/imx8mn.dtsi +++ b/src/arm64/freescale/imx8mn.dtsi @@ -1168,7 +1168,7 @@ <&clk IMX8MN_SYS_PLL1_800M>; assigned-clock-rates = <266000000>, <24000000>, - <594000000>, + <24000000>, <500000000>, <200000000>; #power-domain-cells = <1>; diff --git a/src/arm64/freescale/imx8mp-beacon-som.dtsi b/src/arm64/freescale/imx8mp-beacon-som.dtsi index e5da9080478..8be251b6937 100644 --- a/src/arm64/freescale/imx8mp-beacon-som.dtsi +++ b/src/arm64/freescale/imx8mp-beacon-som.dtsi @@ -50,6 +50,8 @@ phy-mode = "rgmii-id"; phy-handle = <ðphy0>; snps,force_thresh_dma_mode; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; status = "okay"; mdio { @@ -66,6 +68,71 @@ interrupts = <10 IRQ_TYPE_LEVEL_LOW>; }; }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <5>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + snps,map-to-dma-channel = <4>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + }; + }; }; &flexspi { @@ -206,6 +273,10 @@ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; uart-has-rtscts; status = "okay"; + + bluetooth { + compatible = "nxp,88w8997-bt"; + }; }; &usdhc1 { diff --git a/src/arm64/freescale/imx8mp-data-modul-edm-sbc.dts b/src/arm64/freescale/imx8mp-data-modul-edm-sbc.dts index 5828c9d7821..7e1b58dbe23 100644 --- a/src/arm64/freescale/imx8mp-data-modul-edm-sbc.dts +++ b/src/arm64/freescale/imx8mp-data-modul-edm-sbc.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include "imx8mp.dtsi" / { @@ -45,6 +46,19 @@ clock-frequency = <25000000>; }; + clk_pwm4: clock-pwm4 { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + clock-output-names = "codec-pwm4"; + /* + * 1 / 83 ns ~= 12 MHz , but since the PWM input clock is 24 MHz + * and the calculated PWM period is 1 and duty cycle is 50%, the + * result is exactly 12 MHz, which is fine for SGTL5000 MCLK. + */ + pwms = <&pwm4 0 83 0>; + }; + panel: panel { /* Compatible string is filled in by panel board DT Overlay. */ backlight = <&backlight>; @@ -82,6 +96,24 @@ vin-supply = <&buck4>; }; + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SGTL5000-Card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,widgets = "Headphone", "Headphone Jack"; + simple-audio-card,routing = "Headphone Jack", "HP_OUT"; + + cpu_dai: simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + }; + watchdog { /* TPS3813 */ compatible = "linux,wdt-gpio"; pinctrl-names = "default"; @@ -121,7 +153,7 @@ flash@0 { /* W25Q128JVEI */ compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <100000000>; /* Up to 133 MHz */ + spi-max-frequency = <40000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; }; @@ -288,6 +320,15 @@ sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + clocks = <&clk_pwm4>; + VDDA-supply = <&buck4>; + VDDIO-supply = <&buck4>; + }; + usb-hub@2c { compatible = "microchip,usb2514bi"; reg = <0x2c>; @@ -429,6 +470,21 @@ status = "okay"; }; +&pcie_phy { + clocks = <&pcieclk 0>; + clock-names = "ref"; + fsl,refclk-pad-mode = ; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + fsl,max-link-speed = <3>; + reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_panel_pwm>; @@ -436,6 +492,23 @@ status = "disabled"; }; +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&sai3 { + #clock-cells = <0>; + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + status = "okay"; +}; + /* SD slot */ &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; @@ -785,6 +858,12 @@ >; }; + pinctrl_pwm4: pwm4-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0xd6 + >; + }; + pinctrl_rtc: rtc-grp { fsl,pins = < /* RTC_IRQ# */ @@ -816,7 +895,6 @@ MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 - MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 >; }; diff --git a/src/arm64/freescale/imx8mp-evk.dts b/src/arm64/freescale/imx8mp-evk.dts index f87fa5a948c..9beba8d6a0d 100644 --- a/src/arm64/freescale/imx8mp-evk.dts +++ b/src/arm64/freescale/imx8mp-evk.dts @@ -23,7 +23,7 @@ port { hdmi_connector_in: endpoint { - remote-endpoint = <&adv7533_out>; + remote-endpoint = <&adv7535_out>; }; }; }; @@ -107,6 +107,13 @@ enable-active-high; }; + reg_vext_3v3: regulator-vext-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VEXT_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + sound { compatible = "simple-audio-card"; simple-audio-card,name = "wm8960-audio"; @@ -364,7 +371,7 @@ regulator-always-on; }; - BUCK5 { + reg_buck5: BUCK5 { regulator-name = "BUCK5"; regulator-min-microvolt = <1650000>; regulator-max-microvolt = <1950000>; @@ -415,14 +422,16 @@ hdmi@3d { compatible = "adi,adv7535"; - reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>; - reg-names = "main", "cec", "edid", "packet"; + reg = <0x3d>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; adi,dsi-lanes = <4>; - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; + avdd-supply = <®_buck5>; + dvdd-supply = <®_buck5>; + pvdd-supply = <®_buck5>; + a2vdd-supply = <®_buck5>; + v3p3-supply = <®_vext_3v3>; + v1p2-supply = <®_buck5>; ports { #address-cells = <1>; @@ -431,7 +440,7 @@ port@0 { reg = <0>; - adv7533_in: endpoint { + adv7535_in: endpoint { remote-endpoint = <&dsi_out>; }; }; @@ -439,7 +448,7 @@ port@1 { reg = <1>; - adv7533_out: endpoint { + adv7535_out: endpoint { remote-endpoint = <&hdmi_connector_in>; }; }; @@ -524,7 +533,7 @@ reg = <1>; dsi_out: endpoint { - remote-endpoint = <&adv7533_in>; + remote-endpoint = <&adv7535_in>; data-lanes = <1 2 3 4>; }; }; diff --git a/src/arm64/freescale/imx8mp-phyboard-pollux-rdk.dts b/src/arm64/freescale/imx8mp-phyboard-pollux-rdk.dts index c8640cac3ed..00a240484c2 100644 --- a/src/arm64/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/src/arm64/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -19,6 +19,30 @@ stdout-path = &uart1; }; + backlight_lvds: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <11>; + enable-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; + num-interpolated-steps = <2>; + power-supply = <®_lvds1_reg_en>; + pwms = <&pwm3 0 50000 0>; + }; + + panel1_lvds: panel-lvds { + compatible = "edt,etml1010g3dra"; + backlight = <&backlight_lvds>; + power-supply = <®_vcc_3v3_sw>; + + port { + panel1_in: endpoint { + remote-endpoint = <&ldb_lvds_ch1>; + }; + }; + }; + reg_can1_stby: regulator-can1-stby { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -39,6 +63,15 @@ regulator-name = "can2-stby"; }; + reg_lvds1_reg_en: regulator-lvds1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + regulator-name = "lvds1_reg_en"; + }; + reg_usb1_vbus: regulator-usb1-vbus { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -61,6 +94,13 @@ startup-delay-us = <100>; off-on-delay-us = <12000>; }; + + reg_vcc_3v3_sw: regulator-vcc-3v3-sw { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3_SW"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; &eqos { @@ -135,10 +175,41 @@ }; }; +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + status = "okay"; + + ports { + port@2 { + ldb_lvds_ch1: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; + }; +}; + &snvs_pwrkey { status = "okay"; }; +&pwm3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; +}; + +&rv3028 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio4>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + trickle-resistor-ohms = <3000>; +}; + /* debug console */ &uart1 { pinctrl-names = "default"; @@ -239,12 +310,12 @@ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x12 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10 >; }; @@ -289,16 +360,34 @@ >; }; + pinctrl_lvds1: lvds1grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x12 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x12 + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 >; }; + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1C0 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < - MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40 - MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40 + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 >; }; @@ -319,7 +408,7 @@ pinctrl_usdhc2_pins: usdhc2-gpiogrp { fsl,pins = < - MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40 >; }; diff --git a/src/arm64/freescale/imx8mp-phycore-som.dtsi b/src/arm64/freescale/imx8mp-phycore-som.dtsi index c976c3b6cbc..e6ffa6a6b68 100644 --- a/src/arm64/freescale/imx8mp-phycore-som.dtsi +++ b/src/arm64/freescale/imx8mp-phycore-som.dtsi @@ -175,7 +175,6 @@ rv3028: rtc@52 { compatible = "microcrystal,rv3028"; reg = <0x52>; - trickle-resistor-ohms = <3000>; }; }; diff --git a/src/arm64/freescale/imx8mp-venice-gw71xx.dtsi b/src/arm64/freescale/imx8mp-venice-gw71xx.dtsi index 0e8d0f3c7ea..e7bf032265e 100644 --- a/src/arm64/freescale/imx8mp-venice-gw71xx.dtsi +++ b/src/arm64/freescale/imx8mp-venice-gw71xx.dtsi @@ -63,8 +63,15 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, + <&gpio1 10 GPIO_ACTIVE_LOW>; status = "okay"; + + tpm@1 { + compatible = "tcg,tpm_tis-spi"; + reg = <0x1>; + spi-max-frequency = <36000000>; + }; }; &gpio4 { @@ -228,6 +235,7 @@ MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 >; }; diff --git a/src/arm64/freescale/imx8mp-venice-gw72xx.dtsi b/src/arm64/freescale/imx8mp-venice-gw72xx.dtsi index 41c79d2ebdd..f24b1474479 100644 --- a/src/arm64/freescale/imx8mp-venice-gw72xx.dtsi +++ b/src/arm64/freescale/imx8mp-venice-gw72xx.dtsi @@ -14,6 +14,7 @@ pinctrl-0 = <&pinctrl_usbcon1>; type = "micro"; label = "otg"; + vbus-supply = <®_usb1_vbus>; id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; port { @@ -183,7 +184,6 @@ }; &usb3_phy0 { - vbus-supply = <®_usb1_vbus>; status = "okay"; }; diff --git a/src/arm64/freescale/imx8mp-venice-gw73xx.dtsi b/src/arm64/freescale/imx8mp-venice-gw73xx.dtsi index d5c400b355a..f5491a608b2 100644 --- a/src/arm64/freescale/imx8mp-venice-gw73xx.dtsi +++ b/src/arm64/freescale/imx8mp-venice-gw73xx.dtsi @@ -14,6 +14,7 @@ pinctrl-0 = <&pinctrl_usbcon1>; type = "micro"; label = "otg"; + vbus-supply = <®_usb1_vbus>; id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; port { @@ -202,7 +203,6 @@ }; &usb3_phy0 { - vbus-supply = <®_usb1_vbus>; status = "okay"; }; diff --git a/src/arm64/freescale/imx8mp-verdin.dtsi b/src/arm64/freescale/imx8mp-verdin.dtsi index c3305f0d400..faa17cbbe2f 100644 --- a/src/arm64/freescale/imx8mp-verdin.dtsi +++ b/src/arm64/freescale/imx8mp-verdin.dtsi @@ -552,7 +552,7 @@ regulator-name = "On-module +V3.3_ADC (LDO4)"; }; - LDO5 { + reg_vdd_sdio: LDO5 { regulator-max-microvolt = <3300000>; regulator-min-microvolt = <1800000>; regulator-name = "On-module +V3.3_1.8_SD (LDO5)"; @@ -885,6 +885,7 @@ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_vdd_sdio>; }; /* On-module eMMC */ diff --git a/src/arm64/freescale/imx8mp.dtsi b/src/arm64/freescale/imx8mp.dtsi index 39a550c1cd2..8141926e4ef 100644 --- a/src/arm64/freescale/imx8mp.dtsi +++ b/src/arm64/freescale/imx8mp.dtsi @@ -1636,8 +1636,10 @@ <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; clock-names = "pclk", "wrap", "phy", "axi"; - assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_CLK_24M>; assigned-clock-rates = <500000000>; power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; status = "disabled"; @@ -1670,8 +1672,10 @@ <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; clock-names = "pclk", "wrap", "phy", "axi"; - assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_CLK_24M>; assigned-clock-rates = <266000000>; power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>; status = "disabled"; diff --git a/src/arm64/freescale/imx8mq-tqma8mq-mba8mx.dts b/src/arm64/freescale/imx8mq-tqma8mq-mba8mx.dts index b302daca4ce..0165f3a2598 100644 --- a/src/arm64/freescale/imx8mq-tqma8mq-mba8mx.dts +++ b/src/arm64/freescale/imx8mq-tqma8mq-mba8mx.dts @@ -28,18 +28,6 @@ id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; }; - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pcie1_refclk: pcie1-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - reg_otg_vbus: regulator-otg-vbus { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -103,23 +91,24 @@ gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; }; +/* PCIe slot on X36 */ &pcie0 { reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, - <&pcie0_refclk>, - <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&pcieclk 3>, + <&pcieclk 2>, <&clk IMX8MQ_CLK_PCIE1_AUX>; status = "okay"; }; /* - * miniPCIe, also usable for cards with USB. Therefore configure the reset as + * miniPCIe on X28, also usable for cards with USB. Therefore configure the reset as * static gpio hog. */ &pcie1 { clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, - <&pcie1_refclk>, - <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&pcieclk 1>, + <&pcieclk 0>, <&clk IMX8MQ_CLK_PCIE2_AUX>; status = "okay"; }; @@ -171,6 +160,7 @@ }; &usb3_phy1 { + vbus-supply = <®_hub_vbus>; status = "okay"; }; diff --git a/src/arm64/freescale/imx8qm-apalis-eval-v1.2.dts b/src/arm64/freescale/imx8qm-apalis-eval-v1.2.dts new file mode 100644 index 00000000000..8466a8204ed --- /dev/null +++ b/src/arm64/freescale/imx8qm-apalis-eval-v1.2.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 Toradex + */ + +/dts-v1/; + +#include "imx8qm-apalis.dtsi" +#include "imx8-apalis-eval-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX8QM/QP on Apalis Evaluation Board V1.2"; + compatible = "toradex,apalis-imx8-eval-v1.2", + "toradex,apalis-imx8", + "fsl,imx8qm"; +}; diff --git a/src/arm64/freescale/imx8qm-apalis-eval.dts b/src/arm64/freescale/imx8qm-apalis-eval.dts index 5ab0921eb59..b0ebf6d0545 100644 --- a/src/arm64/freescale/imx8qm-apalis-eval.dts +++ b/src/arm64/freescale/imx8qm-apalis-eval.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "imx8qm-apalis.dtsi" -#include "imx8-apalis-eval.dtsi" +#include "imx8-apalis-eval-v1.1.dtsi" / { model = "Toradex Apalis iMX8QM/QP on Apalis Evaluation Board"; diff --git a/src/arm64/freescale/imx8qm-apalis-v1.1-eval-v1.2.dts b/src/arm64/freescale/imx8qm-apalis-v1.1-eval-v1.2.dts new file mode 100644 index 00000000000..92c0ae0c033 --- /dev/null +++ b/src/arm64/freescale/imx8qm-apalis-v1.1-eval-v1.2.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 Toradex + */ + +/dts-v1/; + +#include "imx8qm-apalis-v1.1.dtsi" +#include "imx8-apalis-eval-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX8QM V1.1 on Apalis Evaluation Board V1.2"; + compatible = "toradex,apalis-imx8-v1.1-eval-v1.2", + "toradex,apalis-imx8-v1.1", + "fsl,imx8qm"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + /delete-property/ no-1-8-v; +}; + +/* Apalis SD1 */ +&usdhc3 { + /delete-property/ no-1-8-v; +}; diff --git a/src/arm64/freescale/imx8qm-apalis-v1.1-eval.dts b/src/arm64/freescale/imx8qm-apalis-v1.1-eval.dts index c8ff7583155..c998e542f93 100644 --- a/src/arm64/freescale/imx8qm-apalis-v1.1-eval.dts +++ b/src/arm64/freescale/imx8qm-apalis-v1.1-eval.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "imx8qm-apalis-v1.1.dtsi" -#include "imx8-apalis-eval.dtsi" +#include "imx8-apalis-eval-v1.1.dtsi" / { model = "Toradex Apalis iMX8QM V1.1 on Apalis Evaluation Board"; diff --git a/src/arm64/freescale/imx8qm-mek.dts b/src/arm64/freescale/imx8qm-mek.dts index 6d50838ad17..77ac0efdfaa 100644 --- a/src/arm64/freescale/imx8qm-mek.dts +++ b/src/arm64/freescale/imx8qm-mek.dts @@ -41,6 +41,18 @@ }; }; +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + &lpuart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; @@ -104,6 +116,20 @@ }; &iomuxc { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c + IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c + >; + }; + + pinctrl_i2c1_gpio: i2c1gpio-grp { + fsl,pins = < + IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0xc600004c + IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 0xc600004c + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 diff --git a/src/arm64/freescale/imx8qm-ss-conn.dtsi b/src/arm64/freescale/imx8qm-ss-conn.dtsi index ec1639174e2..545e175c88b 100644 --- a/src/arm64/freescale/imx8qm-ss-conn.dtsi +++ b/src/arm64/freescale/imx8qm-ss-conn.dtsi @@ -6,20 +6,25 @@ &fec1 { compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec"; + iommus = <&smmu 0x12 0x7f80>; }; &fec2 { compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec"; + iommus = <&smmu 0x12 0x7f80>; }; &usdhc1 { compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; + iommus = <&smmu 0x11 0x7f80>; }; &usdhc2 { compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; + iommus = <&smmu 0x11 0x7f80>; }; &usdhc3 { compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; + iommus = <&smmu 0x11 0x7f80>; }; diff --git a/src/arm64/freescale/imx8qm-ss-dma.dtsi b/src/arm64/freescale/imx8qm-ss-dma.dtsi index 69cb8676732..aa9f28c4431 100644 --- a/src/arm64/freescale/imx8qm-ss-dma.dtsi +++ b/src/arm64/freescale/imx8qm-ss-dma.dtsi @@ -17,6 +17,32 @@ power-domains = <&pd IMX_SC_R_UART_4>; }; + i2c4: i2c@5a840000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x5a840000 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&i2c4_lpcg 0>, + <&i2c4_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_4>; + status = "disabled"; + }; + + i2c4_lpcg: clock-controller@5ac40000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ac40000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + clock-indices = , ; + clock-output-names = "i2c4_lpcg_clk", + "i2c4_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_I2C_4>; + }; + can1_lpcg: clock-controller@5ace0000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5ace0000 0x10000>; @@ -96,15 +122,30 @@ status = "okay"; }; +/* It is eDMA1 in 8QM RM, but 8QXP it is eDMA3 */ &edma3 { + reg = <0x5a9f0000 0x210000>; + dma-channels = <10>; + interrupts = , + , + , + , + , + , + , + , + , + ; power-domains = <&pd IMX_SC_R_DMA_1_CH0>, - <&pd IMX_SC_R_DMA_1_CH1>, - <&pd IMX_SC_R_DMA_1_CH2>, - <&pd IMX_SC_R_DMA_1_CH3>, - <&pd IMX_SC_R_DMA_1_CH4>, - <&pd IMX_SC_R_DMA_1_CH5>, - <&pd IMX_SC_R_DMA_1_CH6>, - <&pd IMX_SC_R_DMA_1_CH7>; + <&pd IMX_SC_R_DMA_1_CH1>, + <&pd IMX_SC_R_DMA_1_CH2>, + <&pd IMX_SC_R_DMA_1_CH3>, + <&pd IMX_SC_R_DMA_1_CH4>, + <&pd IMX_SC_R_DMA_1_CH5>, + <&pd IMX_SC_R_DMA_1_CH6>, + <&pd IMX_SC_R_DMA_1_CH7>, + <&pd IMX_SC_R_DMA_1_CH8>, + <&pd IMX_SC_R_DMA_1_CH9>; }; &flexcan1 { @@ -112,15 +153,15 @@ }; &flexcan2 { - clocks = <&can1_lpcg 1>, - <&can1_lpcg 0>; + clocks = <&can1_lpcg IMX_LPCG_CLK_4>, + <&can1_lpcg IMX_LPCG_CLK_0>; assigned-clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>; fsl,clk-source = /bits/ 8 <1>; }; &flexcan3 { - clocks = <&can2_lpcg 1>, - <&can2_lpcg 0>; + clocks = <&can2_lpcg IMX_LPCG_CLK_4>, + <&can2_lpcg IMX_LPCG_CLK_0>; assigned-clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>; fsl,clk-source = /bits/ 8 <1>; }; diff --git a/src/arm64/freescale/imx8qm.dtsi b/src/arm64/freescale/imx8qm.dtsi index 31744fc1ab0..b3d01677b70 100644 --- a/src/arm64/freescale/imx8qm.dtsi +++ b/src/arm64/freescale/imx8qm.dtsi @@ -265,6 +265,47 @@ ; /* Hypervisor */ }; + smmu: iommu@51400000 { + compatible = "arm,mmu-500"; + interrupt-parent = <&gic>; + reg = <0 0x51400000 0 0x40000>; + #global-interrupts = <1>; + #iommu-cells = <2>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + system-controller { compatible = "fsl,imx-scu"; mbox-names = "tx0", diff --git a/src/arm64/freescale/imx8qxp-tqma8xqp-mba8xx.dts b/src/arm64/freescale/imx8qxp-tqma8xqp-mba8xx.dts new file mode 100644 index 00000000000..7d2e98bf8bc --- /dev/null +++ b/src/arm64/freescale/imx8qxp-tqma8xqp-mba8xx.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR X11) +/* + * Copyright 2018-2023 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/dts-v1/; + +#include "imx8qxp-tqma8xqp.dtsi" +#include "mba8xx.dtsi" + +/ { + model = "TQ-Systems i.MX8QXP TQMa8XQP on MBa8Xx"; + compatible = "tq,imx8qxp-tqma8xqp-mba8xx", "tq,imx8qxp-tqma8xqp", "fsl,imx8qxp"; +}; diff --git a/src/arm64/freescale/imx8qxp-tqma8xqp.dtsi b/src/arm64/freescale/imx8qxp-tqma8xqp.dtsi new file mode 100644 index 00000000000..b14040bf4dd --- /dev/null +++ b/src/arm64/freescale/imx8qxp-tqma8xqp.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR X11) +/* + * Copyright 2018-2023 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +#include "imx8qxp.dtsi" +#include "tqma8xx.dtsi" + +/ { + model = "TQ-Systems i.MX8QXP TQMa8XQP"; + compatible = "tq,imx8qxp-tqma8xqp", "fsl,imx8qxp"; +}; diff --git a/src/arm64/freescale/imx8qxp.dtsi b/src/arm64/freescale/imx8qxp.dtsi index 958267b3334..10e16d84c0c 100644 --- a/src/arm64/freescale/imx8qxp.dtsi +++ b/src/arm64/freescale/imx8qxp.dtsi @@ -260,6 +260,13 @@ ; /* Hypervisor */ }; + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + xtal32k: clock-xtal32k { compatible = "fixed-clock"; #clock-cells = <0>; @@ -310,6 +317,7 @@ /* sorted in register address */ #include "imx8-ss-img.dtsi" #include "imx8-ss-vpu.dtsi" + #include "imx8-ss-gpu0.dtsi" #include "imx8-ss-adma.dtsi" #include "imx8-ss-conn.dtsi" #include "imx8-ss-ddr.dtsi" diff --git a/src/arm64/freescale/imx8ulp-evk.dts b/src/arm64/freescale/imx8ulp-evk.dts index 69dd8e31027..24bb253b938 100644 --- a/src/arm64/freescale/imx8ulp-evk.dts +++ b/src/arm64/freescale/imx8ulp-evk.dts @@ -37,7 +37,7 @@ no-map; }; - rsc_table: rsc-table@1fff8000{ + rsc_table: rsc-table@1fff8000 { reg = <0 0x1fff8000 0 0x1000>; no-map; }; diff --git a/src/arm64/freescale/imx93-phyboard-segin.dts b/src/arm64/freescale/imx93-phyboard-segin.dts new file mode 100644 index 00000000000..85fb188b057 --- /dev/null +++ b/src/arm64/freescale/imx93-phyboard-segin.dts @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov , Christoph Stoidner + * Copyright (C) 2024 Mathieu Othacehe + * + * Product homepage: + * phyBOARD-Segin carrier board is reused for the i.MX93 design. + * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/ + */ +/dts-v1/; + +#include "imx93-phycore-som.dtsi" + +/{ + model = "PHYTEC phyBOARD-Segin-i.MX93"; + compatible = "phytec,imx93-phyboard-segin", "phytec,imx93-phycore-som", + "fsl,imx93"; + + chosen { + stdout-path = &lpuart1; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "VCC_SD"; + }; +}; + +/* Console */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* eMMC */ +&usdhc1 { + no-1-8-v; +}; + +/* SD-Card */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; + bus-width = <4>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x30e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_usdhc2_cd: usdhc2cdgrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + pinctrl_usdhc2_default: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x178e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; +}; diff --git a/src/arm64/freescale/imx93-phycore-som.dtsi b/src/arm64/freescale/imx93-phycore-som.dtsi new file mode 100644 index 00000000000..88c2657b50e --- /dev/null +++ b/src/arm64/freescale/imx93-phycore-som.dtsi @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov , Christoph Stoidner + * Copyright (C) 2024 Mathieu Othacehe + * + * Product homepage: + * https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ + */ + +#include + +#include "imx93.dtsi" + +/{ + model = "PHYTEC phyCORE-i.MX93"; + compatible = "phytec,imx93-phycore-som", "fsl,imx93"; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0 0x80000000 0 0x40000000>; + size = <0 0x10000000>; + linux,cma-default; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +/* Ethernet */ +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + fsl,magic-packet; + assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, + <&clk IMX93_CLK_ENET_REF>, + <&clk IMX93_CLK_ENET_REF_PHY>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <100000000>, <50000000>, <50000000>; + status = "okay"; + + mdio: mdio { + clock-frequency = <5000000>; + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +/* Watchdog */ +&wdog3 { + status = "okay"; +}; + +&iomuxc { + pinctrl_fec: fecgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__ENET1_MDC 0x50e + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x502 + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x5fe + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x50e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x50e + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x50e + MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x4000050e + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e + MX93_PAD_SD1_CMD__USDHC1_CMD 0x1386 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x1386 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x1386 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x1386 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x1386 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x1386 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x1386 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e + >; + }; +}; diff --git a/src/arm64/freescale/imx93-tqma9352.dtsi b/src/arm64/freescale/imx93-tqma9352.dtsi index f6e422dc266..9d2328c185c 100644 --- a/src/arm64/freescale/imx93-tqma9352.dtsi +++ b/src/arm64/freescale/imx93-tqma9352.dtsi @@ -122,10 +122,8 @@ /* protectable identification memory (part of M24C64-D @57) */ eeprom@5f { - compatible = "st,24c64", "atmel,24c64"; + compatible = "atmel,24c64d-wl"; reg = <0x5f>; - size = <32>; - pagesize = <32>; vcc-supply = <®_v3v3>; }; diff --git a/src/arm64/freescale/imx93-var-som-symphony.dts b/src/arm64/freescale/imx93-var-som-symphony.dts new file mode 100644 index 00000000000..576d6982a4a --- /dev/null +++ b/src/arm64/freescale/imx93-var-som-symphony.dts @@ -0,0 +1,351 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + * Copyright 2023 Variscite Ltd. + */ + +/dts-v1/; + +#include +#include "imx93-var-som.dtsi" + +/{ + model = "Variscite VAR-SOM-MX93 on Symphony evaluation board"; + compatible = "variscite,var-som-mx93-symphony", + "variscite,var-som-mx93", "fsl,imx93"; + + aliases { + ethernet0 = &eqos; + ethernet1 = &fec; + }; + + chosen { + stdout-path = &lpuart1; + }; + + /* + * Needed only for Symphony <= v1.5 + */ + reg_fec_phy: regulator-fec-phy { + compatible = "regulator-fixed"; + regulator-name = "fec-phy"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <20000>; + gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + enable-active-high; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ethosu_mem: ethosu-region@88000000 { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 0x88000000 0x0 0x8000000>; + }; + + vdev0vring0: vdev0vring0@87ee0000 { + reg = <0 0x87ee0000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@87ee8000 { + reg = <0 0x87ee8000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@87ef0000 { + reg = <0 0x87ef0000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@87ef8000 { + reg = <0 0x87ef8000 0 0x8000>; + no-map; + }; + + rsc_table: rsc-table@2021f000 { + reg = <0 0x2021f000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@87f00000 { + compatible = "shared-dma-pool"; + reg = <0 0x87f00000 0 0x100000>; + no-map; + }; + + ele_reserved: ele-reserved@87de0000 { + compatible = "shared-dma-pool"; + reg = <0 0x87de0000 0 0x100000>; + no-map; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-back { + label = "Back"; + gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-home { + label = "Home"; + gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-menu { + label = "Menu"; + gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +/* Use external instead of internal RTC*/ +&bbnsm_rtc { + status = "disabled"; +}; + +&eqos { + mdio { + ethphy1: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + qca,disable-smarteee; + eee-broken-1000t; + reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + vddio-supply = <&vddio1>; + + vddio1: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + phy-supply = <®_fec_phy>; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1_gpio>; + pinctrl-2 = <&pinctrl_lpi2c1_gpio>; + scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + + /* DS1337 RTC module */ + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; +}; + +&lpi2c5 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c5>; + pinctrl-1 = <&pinctrl_lpi2c5_gpio>; + pinctrl-2 = <&pinctrl_lpi2c5_gpio>; + scl-gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pca9534: gpio@20 { + compatible = "nxp,pca9534"; + reg = <0x20>; + gpio-controller; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9534>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + #gpio-cells = <2>; + wakeup-source; + }; +}; + +/* Console */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* J18.7, J18.9 */ +&lpuart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + status = "okay"; +}; + +/* SD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; + no-sdio; + no-mmc; +}; + +/* Watchdog */ +&wdog3 { + status = "okay"; +}; + +&iomuxc { + pinctrl_fec: fecgrp { + fsl,pins = < + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX93_PAD_PDM_CLK__CAN1_TX 0x139e + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c1_gpio: lpi2c1gpiogrp { + fsl,pins = < + MX93_PAD_I2C1_SCL__GPIO1_IO00 0x31e + MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e + >; + }; + + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins = < + MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e + MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c5_gpio: lpi2c5gpiogrp { + fsl,pins = < + MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e + MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e + >; + }; + + pinctrl_pca9534: pca9534grp { + fsl,pins = < + MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX93_PAD_GPIO_IO05__LPUART6_RX 0x31e + MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_GPIO_IO18__GPIO2_IO18 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; +}; diff --git a/src/arm64/freescale/imx93-var-som.dtsi b/src/arm64/freescale/imx93-var-som.dtsi new file mode 100644 index 00000000000..783938245e4 --- /dev/null +++ b/src/arm64/freescale/imx93-var-som.dtsi @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + * Copyright 2023 Variscite Ltd. + */ + +/dts-v1/; + +#include "imx93.dtsi" + +/{ + model = "Variscite VAR-SOM-MX93 module"; + compatible = "variscite,var-som-mx93", "fsl,imx93"; + + mmc_pwrseq: mmc-pwrseq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <10000>; + reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ + <&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ + }; + + reg_eqos_phy: regulator-eqos-phy { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_eqos_phy>; + regulator-name = "eth_phy_pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100000>; + regulator-always-on; + }; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <1000000>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + eee-broken-1000t; + }; + }; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_reg_eqos_phy: regeqosgrp { + fsl,pins = < + MX93_PAD_UART2_TXD__GPIO1_IO07 0x51e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; +}; diff --git a/src/arm64/freescale/imx93.dtsi b/src/arm64/freescale/imx93.dtsi index 8f2e7c42ad6..601c94e1fac 100644 --- a/src/arm64/freescale/imx93.dtsi +++ b/src/arm64/freescale/imx93.dtsi @@ -294,7 +294,7 @@ status = "disabled"; }; - i3c1: i3c-master@44330000 { + i3c1: i3c@44330000 { compatible = "silvaco,i3c-master-v1"; reg = <0x44330000 0x10000>; interrupts = ; @@ -671,7 +671,7 @@ status = "disabled"; }; - i3c2: i3c-master@42520000 { + i3c2: i3c@42520000 { compatible = "silvaco,i3c-master-v1"; reg = <0x42520000 0x10000>; interrupts = ; diff --git a/src/arm64/freescale/mba8mx.dtsi b/src/arm64/freescale/mba8mx.dtsi index e2bc53b8d39..427467df42b 100644 --- a/src/arm64/freescale/mba8mx.dtsi +++ b/src/arm64/freescale/mba8mx.dtsi @@ -29,6 +29,12 @@ stdout-path = &uart3; }; + clk_xtal25: clk-xtal25 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -100,12 +106,6 @@ }; }; - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - reg_12v: regulator-12v { compatible = "regulator-fixed"; regulator-name = "MBA8MX_12V"; @@ -219,7 +219,7 @@ line-name = "BOOT_CFG_OE#"; }; - rst-usb-hub-hog { + rst_usb_hub_hog: rst-usb-hub-hog { gpio-hog; gpios = <13 0>; output-high; @@ -264,6 +264,13 @@ pagesize = <16>; vcc-supply = <®_vcc_3v3>; }; + + pcieclk: clk@68 { + compatible = "renesas,9fgv0441"; + reg = <0x68>; + clocks = <&clk_xtal25>; + #clock-cells = <1>; + }; }; &i2c3 { diff --git a/src/arm64/freescale/mba8xx.dtsi b/src/arm64/freescale/mba8xx.dtsi new file mode 100644 index 00000000000..276d1683b03 --- /dev/null +++ b/src/arm64/freescale/mba8xx.dtsi @@ -0,0 +1,554 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR X11) +/* + * Copyright 2018-2023 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +#include +#include +#include + +/ { + adc { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>; + }; + + aliases { + rtc0 = &pcf85063; + rtc1 = &rtc; + }; + + backlight_lvds: backlight-lvds { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bl_lvds>; + pwms = <&adma_pwm 0 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_12v0>; + enable-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + chosen { + stdout-path = &lpuart1; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiobuttons>; + autorepeat; + + switch-a { + label = "switcha"; + linux,code = ; + gpios = <&lsio_gpio1 13 GPIO_ACTIVE_LOW>; + }; + + switch-b { + label = "switchb"; + linux,code = ; + gpios = <&lsio_gpio1 14 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led1 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&expander 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led2 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&expander 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + /* TODO LVDS panels */ + + reg_12v0: regulator-12v0 { + compatible = "regulator-fixed"; + regulator-name = "V_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&expander 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_pcie_1v5: regulator-pcie-1v5 { + compatible = "regulator-fixed"; + regulator-name = "MBA8XX_PCIE_1V5"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_pcie_1v5>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&lsio_gpio0 30 GPIO_ACTIVE_HIGH>; + startup-delay-us = <1000>; + enable-active-high; + }; + + reg_pcie_3v3: regulator-pcie-3v3 { + compatible = "regulator-fixed"; + regulator-name = "MBA8XX_PCIE_3V3"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_pcie_3v3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; + startup-delay-us = <1000>; + enable-active-high; + regulator-always-on; + }; + + reg_3v3_mb: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_MB"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "tqm-tlv320aic32"; + audio-codec = <&tlv320aic3x04>; + ssi-controller = <&sai1>; + }; +}; + +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; + vref-supply = <®_1v8>; + #io-channel-cells = <1>; + status = "okay"; +}; + +&adma_pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_admapwm>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ethphy0>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + reset-gpios = <&lsio_gpio3 2 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + enet-phy-lane-no-swap; + interrupt-parent = <&lsio_gpio3>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + }; + + ethphy3: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ethphy3>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + reset-gpios = <&lsio_gpio3 3 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + enet-phy-lane-no-swap; + interrupt-parent = <&lsio_gpio3>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy3>; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0>; + xceiver-supply = <®_3v3>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_3v3>; + status = "okay"; +}; + +&i2c1 { + tlv320aic3x04: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + iov-supply = <®_1v8>; + ldoin-supply = <®_3v3>; + }; + + se97b_1c: temperature-sensor@1c { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x1c>; + }; + + at24c02_54: eeprom@54 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x54>; + pagesize = <16>; + vcc-supply = <®_3v3>; + }; + + expander: gpio@70 { + compatible = "nxp,pca9538"; + reg = <0x70>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9538>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&lsio_gpio4>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + vcc-supply = <®_1v8>; + + gpio-line-names = "", "LED_A", + "LED_B", "", + "DSI_EN", "USB_RESET#", + "V_12V_EN", "PCIE_DIS#"; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2gpio>; + scl-gpios = <&lsio_gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&lsio_gpio2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +/* TODO LDB */ + +&lpspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + cs-gpios = <&lsio_gpio0 27 GPIO_ACTIVE_LOW>, <&lsio_gpio0 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&lpspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&lpspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi3>; + num-cs = <2>; + cs-gpios = <&lsio_gpio0 16 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "okay"; +}; + +&lsio_gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lsgpio3>; + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "X4_15", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +/* TODO: Mini-PCIe */ + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + over-current-active-low; + dr_mode = "otg"; + status = "okay"; +}; + +&usbotg3 { + status = "okay"; +}; + +&usbotg3_cdns3 { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_3v3_mb>; + no-1-8-v; + no-sdio; + no-mmc; + status = "okay"; +}; + +&iomuxc { + pinctrl_adc0: adc0grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_admapwm: admapwmgrp { + fsl,pins = ; + }; + + pinctrl_bl_lvds: bllvdsgrp { + fsl,pins = ; + }; + + pinctrl_can0: can0grp { + fsl,pins = , + ; + }; + + pinctrl_can1: can1grp { + fsl,pins = , + ; + }; + + pinctrl_ethphy0: ethphy0grp { + fsl,pins = , + ; + }; + + pinctrl_ethphy3: ethphy3grp { + fsl,pins = , + ; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_gpiobuttons: gpiobuttonsgrp { + fsl,pins = , + ; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = , + ; + }; + + pinctrl_lpi2c2gpio: lpi2c2gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = , + ; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = , + ; + }; + + pinctrl_lsgpio3: lsgpio3grp { + fsl,pins = ; + }; + + pinctrl_pca9538: pca9538grp { + fsl,pins = ; + }; + + pinctrl_pcieb: pcieagrp { + fsl,pins = , + , + ; + }; + + pinctrl_reg_pcie_1v5: regpcie1v5grp { + fsl,pins = ; + }; + + pinctrl_reg_pcie_3v3: regpcie3v3grp { + fsl,pins = ; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = , + , + , + , + ; + }; + + pinctrl_spi1: spi1grp { + fsl,pins = , + , + , + , + ; + }; + + pinctrl_spi2: spi2grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_spi3: spi3grp { + fsl,pins = , + , + , + , + ; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = , + ; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = , + , + , + , + , + , + ; + }; +}; diff --git a/src/arm64/freescale/tqma8xx.dtsi b/src/arm64/freescale/tqma8xx.dtsi new file mode 100644 index 00000000000..d98469a7c47 --- /dev/null +++ b/src/arm64/freescale/tqma8xx.dtsi @@ -0,0 +1,265 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR X11) +/* + * Copyright 2018-2023 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "V_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * global autoconfigured region for contiguous allocations + * must not exceed memory size and region + */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x20000000>; + alloc-ranges = <0 0x96000000 0 0x30000000>; + linux,cma-default; + }; + }; +}; + +/* TQMa8Xx only uses industrial grade, reduce trip points accordingly */ +&cpu_alert0 { + temperature = <95000>; +}; + +&cpu_crit0 { + temperature = <100000>; +}; +/* end of temperature grade adjustments */ + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <66000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + }; +}; + +/* TODO GPU */ + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1gpio>; + scl-gpios = <&lsio_gpio1 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&lsio_gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + se97: temperature-sensor@1b { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x1b>; + }; + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <7000>; + }; + + at24c02: eeprom@53 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + read-only; + vcc-supply = <®_3v3>; + }; + + m24c64: eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + vcc-supply = <®_3v3>; + }; +}; + +&mu_m0 { + status = "okay"; +}; + +&mu1_m0 { + status = "okay"; +}; + +&thermal_zones { + pmic_thermal: pmic-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; + + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + vqmmc-supply = <®_1v8>; + vmmc-supply = <®_3v3>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&vpu { + compatible = "nxp,imx8qxp-vpu"; + status = "okay"; +}; + +&vpu_core0 { + memory-region = <&decoder_boot>, <&decoder_rpc>; + status = "okay"; +}; + +&vpu_core1 { + memory-region = <&encoder_boot>, <&encoder_rpc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004d + IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004d + IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004d + IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004d + IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004d + IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004d + IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004d + IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004d + IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004d + IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004d + IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004d + IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004d + IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004d + IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004d + IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004d + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021 + IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021 + >; + }; + + pinctrl_lpi2c1gpio: lpi2c1gpiogrp { + fsl,pins = < + IMX8QXP_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27 0x06000021 + IMX8QXP_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 0x06000021 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + >; + }; +}; diff --git a/src/arm64/intel/socfpga_agilex5.dtsi b/src/arm64/intel/socfpga_agilex5.dtsi index d66d425e45b..1162978329c 100644 --- a/src/arm64/intel/socfpga_agilex5.dtsi +++ b/src/arm64/intel/socfpga_agilex5.dtsi @@ -202,7 +202,7 @@ status = "disabled"; }; - i3c0: i3c-master@10da0000 { + i3c0: i3c@10da0000 { compatible = "snps,dw-i3c-master-1.00a"; reg = <0x10da0000 0x1000>; #address-cells = <3>; @@ -212,7 +212,7 @@ status = "disabled"; }; - i3c1: i3c-master@10da1000 { + i3c1: i3c@10da1000 { compatible = "snps,dw-i3c-master-1.00a"; reg = <0x10da1000 0x1000>; #address-cells = <3>; diff --git a/src/arm64/marvell/ac5-98dx25xx.dtsi b/src/arm64/marvell/ac5-98dx25xx.dtsi index b5e042b8e92..5591939e057 100644 --- a/src/arm64/marvell/ac5-98dx25xx.dtsi +++ b/src/arm64/marvell/ac5-98dx25xx.dtsi @@ -77,7 +77,6 @@ #address-cells = <2>; #size-cells = <2>; ranges; - dma-ranges; internal-regs@7f000000 { #address-cells = <1>; @@ -204,6 +203,30 @@ }; }; + mmc_dma: bus@80500000 { + compatible = "simple-bus"; + ranges; + #address-cells = <0x2>; + #size-cells = <0x2>; + reg = <0x0 0x80500000 0x0 0x100000>; + dma-ranges = <0x0 0x0 0x2 0x0 0x0 0x80000000>; + dma-coherent; + + sdhci: mmc@805c0000 { + compatible = "marvell,ac5-sdhci", + "marvell,armada-ap806-sdhci"; + reg = <0x0 0x805c0000 0x0 0x1000>; + interrupts = ; + clocks = <&emmc_clock>, <&cnm_clock>; + clock-names = "core", "axi"; + bus-width = <8>; + non-removable; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + }; + }; + /* * Dedicated section for devices behind 32bit controllers so we * can configure specific DMA mapping for them @@ -335,5 +358,11 @@ #clock-cells = <0>; clock-frequency = <400000000>; }; + + emmc_clock: emmc-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; }; }; diff --git a/src/arm64/marvell/ac5-98dx35xx-rd.dts b/src/arm64/marvell/ac5-98dx35xx-rd.dts index f0ebdb84eec..0c973d7a215 100644 --- a/src/arm64/marvell/ac5-98dx35xx-rd.dts +++ b/src/arm64/marvell/ac5-98dx35xx-rd.dts @@ -99,3 +99,7 @@ }; }; }; + +&sdhci { + status = "okay"; +}; diff --git a/src/arm64/marvell/armada-37xx.dtsi b/src/arm64/marvell/armada-37xx.dtsi index e300145ad1a..1cc3fa1c354 100644 --- a/src/arm64/marvell/armada-37xx.dtsi +++ b/src/arm64/marvell/armada-37xx.dtsi @@ -431,14 +431,14 @@ crypto: crypto@90000 { compatible = "inside-secure,safexcel-eip97ies"; reg = <0x90000 0x20000>; - interrupts = , - , + interrupts = , , , , - ; - interrupt-names = "mem", "ring0", "ring1", - "ring2", "ring3", "eip"; + , + ; + interrupt-names = "ring0", "ring1", "ring2", + "ring3", "eip", "mem"; clocks = <&nb_periph_clk 15>; }; diff --git a/src/arm64/marvell/armada-ap807.dtsi b/src/arm64/marvell/armada-ap807.dtsi index 4a23f65d475..a3328d05fc9 100644 --- a/src/arm64/marvell/armada-ap807.dtsi +++ b/src/arm64/marvell/armada-ap807.dtsi @@ -33,3 +33,6 @@ "marvell,armada-ap806-sdhci"; /* Backward compatibility */ }; +&ap_thermal { + compatible = "marvell,armada-ap807-thermal"; +}; diff --git a/src/arm64/marvell/armada-cp11x.dtsi b/src/arm64/marvell/armada-cp11x.dtsi index 4ec1aae0a3a..7e595ac8004 100644 --- a/src/arm64/marvell/armada-cp11x.dtsi +++ b/src/arm64/marvell/armada-cp11x.dtsi @@ -511,14 +511,14 @@ CP11X_LABEL(crypto): crypto@800000 { compatible = "inside-secure,safexcel-eip197b"; reg = <0x800000 0x200000>; - interrupts = <87 IRQ_TYPE_LEVEL_HIGH>, - <88 IRQ_TYPE_LEVEL_HIGH>, + interrupts = <88 IRQ_TYPE_LEVEL_HIGH>, <89 IRQ_TYPE_LEVEL_HIGH>, <90 IRQ_TYPE_LEVEL_HIGH>, <91 IRQ_TYPE_LEVEL_HIGH>, - <92 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mem", "ring0", "ring1", - "ring2", "ring3", "eip"; + <92 IRQ_TYPE_LEVEL_HIGH>, + <87 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ring0", "ring1", "ring2", "ring3", + "eip", "mem"; clock-names = "core", "reg"; clocks = <&CP11X_LABEL(clk) 1 26>, <&CP11X_LABEL(clk) 1 17>; diff --git a/src/arm64/mediatek/mt2712-evb.dts b/src/arm64/mediatek/mt2712-evb.dts index fffdb7bbf88..234e3b23d7a 100644 --- a/src/arm64/mediatek/mt2712-evb.dts +++ b/src/arm64/mediatek/mt2712-evb.dts @@ -43,12 +43,12 @@ extcon_usb: extcon_iddig { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pio 12 GPIO_ACTIVE_HIGH>; + id-gpios = <&pio 12 GPIO_ACTIVE_HIGH>; }; extcon_usb1: extcon_iddig1 { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pio 14 GPIO_ACTIVE_HIGH>; + id-gpios = <&pio 14 GPIO_ACTIVE_HIGH>; }; usb_p0_vbus: regulator-usb-p0-vbus { @@ -129,7 +129,7 @@ }; &pio { - eth_default: eth_default { + eth_default: eth-default-pins { tx_pins { pinmux = , , @@ -156,7 +156,7 @@ }; }; - eth_sleep: eth_sleep { + eth_sleep: eth-sleep-pins { tx_pins { pinmux = , , @@ -182,14 +182,14 @@ }; }; - usb0_id_pins_float: usb0_iddig { + usb0_id_pins_float: usb0-iddig-pins { pins_iddig { pinmux = ; bias-pull-up; }; }; - usb1_id_pins_float: usb1_iddig { + usb1_id_pins_float: usb1-iddig-pins { pins_iddig { pinmux = ; bias-pull-up; diff --git a/src/arm64/mediatek/mt2712e.dtsi b/src/arm64/mediatek/mt2712e.dtsi index ed1a9d31941..082672efba0 100644 --- a/src/arm64/mediatek/mt2712e.dtsi +++ b/src/arm64/mediatek/mt2712e.dtsi @@ -249,10 +249,11 @@ #clock-cells = <1>; }; - infracfg: syscon@10001000 { + infracfg: clock-controller@10001000 { compatible = "mediatek,mt2712-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; pericfg: syscon@10003000 { @@ -261,7 +262,7 @@ #clock-cells = <1>; }; - syscfg_pctl_a: syscfg_pctl_a@10005000 { + syscfg_pctl_a: syscon@10005000 { compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon"; reg = <0 0x10005000 0 0x1000>; }; diff --git a/src/arm64/mediatek/mt6797.dtsi b/src/arm64/mediatek/mt6797.dtsi index c3677d77e0a..0e9d11b4585 100644 --- a/src/arm64/mediatek/mt6797.dtsi +++ b/src/arm64/mediatek/mt6797.dtsi @@ -117,7 +117,7 @@ #clock-cells = <1>; }; - infrasys: infracfg_ao@10001000 { + infrasys: syscon@10001000 { compatible = "mediatek,mt6797-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; @@ -452,19 +452,19 @@ #clock-cells = <1>; }; - imgsys: imgsys_config@15000000 { + imgsys: syscon@15000000 { compatible = "mediatek,mt6797-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; }; - vdecsys: vdec_gcon@16000000 { + vdecsys: syscon@16000000 { compatible = "mediatek,mt6797-vdecsys", "syscon"; reg = <0 0x16000000 0 0x10000>; #clock-cells = <1>; }; - vencsys: venc_gcon@17000000 { + vencsys: syscon@17000000 { compatible = "mediatek,mt6797-vencsys", "syscon"; reg = <0 0x17000000 0 0x1000>; #clock-cells = <1>; diff --git a/src/arm64/mediatek/mt7622-bananapi-bpi-r64.dts b/src/arm64/mediatek/mt7622-bananapi-bpi-r64.dts index a1f42048dcc..224bb289660 100644 --- a/src/arm64/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/src/arm64/mediatek/mt7622-bananapi-bpi-r64.dts @@ -75,6 +75,7 @@ memory@40000000 { reg = <0 0x40000000 0 0x40000000>; + device_type = "memory"; }; reg_1p8v: regulator-1p8v { @@ -185,6 +186,18 @@ label = "lan3"; }; + port@5 { + reg = <5>; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + port@6 { reg = <6>; label = "cpu"; diff --git a/src/arm64/mediatek/mt7622-rfb1.dts b/src/arm64/mediatek/mt7622-rfb1.dts index 2dc1bdc74e2..41629769bdc 100644 --- a/src/arm64/mediatek/mt7622-rfb1.dts +++ b/src/arm64/mediatek/mt7622-rfb1.dts @@ -57,6 +57,7 @@ memory@40000000 { reg = <0 0x40000000 0 0x20000000>; + device_type = "memory"; }; reg_1p8v: regulator-1p8v { @@ -117,6 +118,18 @@ }; }; + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + mdio-bus { #address-cells = <1>; #size-cells = <0>; @@ -155,6 +168,18 @@ label = "wan"; }; + port@5 { + reg = <5>; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + port@6 { reg = <6>; label = "cpu"; diff --git a/src/arm64/mediatek/mt7622.dtsi b/src/arm64/mediatek/mt7622.dtsi index 3ee9266fa8e..917fa39a74f 100644 --- a/src/arm64/mediatek/mt7622.dtsi +++ b/src/arm64/mediatek/mt7622.dtsi @@ -252,7 +252,7 @@ clock-names = "hif_sel"; }; - cir: cir@10009000 { + cir: ir-receiver@10009000 { compatible = "mediatek,mt7622-cir"; reg = <0 0x10009000 0 0x1000>; interrupts = ; @@ -283,16 +283,14 @@ }; }; - apmixedsys: apmixedsys@10209000 { - compatible = "mediatek,mt7622-apmixedsys", - "syscon"; + apmixedsys: clock-controller@10209000 { + compatible = "mediatek,mt7622-apmixedsys"; reg = <0 0x10209000 0 0x1000>; #clock-cells = <1>; }; - topckgen: topckgen@10210000 { - compatible = "mediatek,mt7622-topckgen", - "syscon"; + topckgen: clock-controller@10210000 { + compatible = "mediatek,mt7622-topckgen"; reg = <0 0x10210000 0 0x1000>; #clock-cells = <1>; }; @@ -515,7 +513,6 @@ <&pericfg CLK_PERI_AUXADC_PD>; clock-names = "therm", "auxadc"; resets = <&pericfg MT7622_PERI_THERM_SW_RST>; - reset-names = "therm"; mediatek,auxadc = <&auxadc>; mediatek,apmixedsys = <&apmixedsys>; nvmem-cells = <&thermal_calibration>; @@ -734,9 +731,8 @@ power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>; }; - ssusbsys: ssusbsys@1a000000 { - compatible = "mediatek,mt7622-ssusbsys", - "syscon"; + ssusbsys: clock-controller@1a000000 { + compatible = "mediatek,mt7622-ssusbsys"; reg = <0 0x1a000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; @@ -793,9 +789,8 @@ }; }; - pciesys: pciesys@1a100800 { - compatible = "mediatek,mt7622-pciesys", - "syscon"; + pciesys: clock-controller@1a100800 { + compatible = "mediatek,mt7622-pciesys"; reg = <0 0x1a100800 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; @@ -921,12 +916,13 @@ }; }; - hifsys: syscon@1af00000 { - compatible = "mediatek,mt7622-hifsys", "syscon"; + hifsys: clock-controller@1af00000 { + compatible = "mediatek,mt7622-hifsys"; reg = <0 0x1af00000 0 0x70>; + #clock-cells = <1>; }; - ethsys: syscon@1b000000 { + ethsys: clock-controller@1b000000 { compatible = "mediatek,mt7622-ethsys", "syscon"; reg = <0 0x1b000000 0 0x1000>; @@ -966,9 +962,7 @@ }; eth: ethernet@1b100000 { - compatible = "mediatek,mt7622-eth", - "mediatek,mt2701-eth", - "syscon"; + compatible = "mediatek,mt7622-eth"; reg = <0 0x1b100000 0 0x20000>; interrupts = , , diff --git a/src/arm64/mediatek/mt7981b-xiaomi-ax3000t.dts b/src/arm64/mediatek/mt7981b-xiaomi-ax3000t.dts new file mode 100644 index 00000000000..a314c3e05e5 --- /dev/null +++ b/src/arm64/mediatek/mt7981b-xiaomi-ax3000t.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +/dts-v1/; + +#include "mt7981b.dtsi" + +/ { + compatible = "xiaomi,ax3000t", "mediatek,mt7981b"; + model = "Xiaomi AX3000T"; + + memory@40000000 { + reg = <0 0x40000000 0 0x10000000>; + device_type = "memory"; + }; +}; diff --git a/src/arm64/mediatek/mt7981b.dtsi b/src/arm64/mediatek/mt7981b.dtsi new file mode 100644 index 00000000000..4feff3d1c5f --- /dev/null +++ b/src/arm64/mediatek/mt7981b.dtsi @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +#include +#include + +/ { + compatible = "mediatek,mt7981b"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x0>; + device_type = "cpu"; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x1>; + device_type = "cpu"; + enable-method = "psci"; + }; + }; + + oscillator-40m { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + clock-output-names = "clkxtal"; + #clock-cells = <0>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc { + compatible = "simple-bus"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + reg = <0 0x0c000000 0 0x40000>, /* GICD */ + <0 0x0c080000 0 0x200000>; /* GICR */ + interrupt-parent = <&gic>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + + infracfg: clock-controller@10001000 { + compatible = "mediatek,mt7981-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + clock-controller@1001b000 { + compatible = "mediatek,mt7981-topckgen", "syscon"; + reg = <0 0x1001b000 0 0x1000>; + #clock-cells = <1>; + }; + + clock-controller@1001e000 { + compatible = "mediatek,mt7981-apmixedsys"; + reg = <0 0x1001e000 0 0x1000>; + #clock-cells = <1>; + }; + + pwm@10048000 { + compatible = "mediatek,mt7981-pwm"; + reg = <0 0x10048000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_PWM_STA>, + <&infracfg CLK_INFRA_PWM_HCK>, + <&infracfg CLK_INFRA_PWM1_CK>, + <&infracfg CLK_INFRA_PWM2_CK>, + <&infracfg CLK_INFRA_PWM3_CK>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; + #pwm-cells = <2>; + }; + + clock-controller@15000000 { + compatible = "mediatek,mt7981-ethsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; +}; diff --git a/src/arm64/mediatek/mt7986a-acelink-ew-7886cax.dts b/src/arm64/mediatek/mt7986a-acelink-ew-7886cax.dts new file mode 100644 index 00000000000..08b3b082743 --- /dev/null +++ b/src/arm64/mediatek/mt7986a-acelink-ew-7886cax.dts @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +/dts-v1/; +#include +#include +#include + +#include "mt7986a.dtsi" + +/ { + compatible = "acelink,ew-7886cax", "mediatek,mt7986a"; + model = "Acelink EW-7886CAX"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + reg = <0 0x40000000 0 0x20000000>; + device_type = "memory"; + }; + + keys { + compatible = "gpio-keys"; + + key-restart { + label = "Reset"; + gpios = <&pio 7 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 18 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 19 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 20 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&crypto { + status = "okay"; +}; + +ð { + status = "okay"; + + mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; + phy-handle = <&phy6>; + nvmem-cells = <&macaddr>; + nvmem-cell-names = "mac-address"; + }; + + mdio-bus { + reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>; + reset-delay-us = <50000>; + reset-post-delay-us = <20000>; + + #address-cells = <1>; + #size-cells = <0>; + + phy6: phy@6 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <6>; + }; + }; +}; + +&pcie_phy { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x100000>; + label = "bootloader"; + read-only; + }; + + partition@100000 { + reg = <0x100000 0x80000>; + label = "u-boot-env"; + }; + + partition@180000 { + compatible = "nvmem-cells"; + reg = <0x180000 0x200000>; + label = "factory"; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom: eeprom@0 { + reg = <0x0 0x1000>; + }; + + macaddr: macaddr@4 { + reg = <0x4 0x6>; + }; + }; + }; + + partition@380000 { + reg = <0x380000 0x200000>; + label = "fip"; + }; + + partition@580000 { + reg = <0x580000 0x4000000>; + label = "ubi"; + }; + }; + }; +}; + +&trng { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + nvmem-cells = <&eeprom>; + nvmem-cell-names = "eeprom"; + status = "okay"; +}; diff --git a/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso b/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso index 543c13385d6..7b97c5c91bd 100644 --- a/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso +++ b/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso @@ -15,7 +15,7 @@ __overlay__ { #address-cells = <1>; #size-cells = <0>; - spi_nand: spi_nand@0 { + spi_nand: flash@0 { compatible = "spi-nand"; reg = <0>; spi-max-frequency = <10000000>; diff --git a/src/arm64/mediatek/mt7986a-bananapi-bpi-r3.dts b/src/arm64/mediatek/mt7986a-bananapi-bpi-r3.dts index d06d4af43cb..ed79ad1ae87 100644 --- a/src/arm64/mediatek/mt7986a-bananapi-bpi-r3.dts +++ b/src/arm64/mediatek/mt7986a-bananapi-bpi-r3.dts @@ -43,7 +43,7 @@ #cooling-cells = <2>; /* cooling level (0, 1, 2) - pwm inverted */ cooling-levels = <255 96 0>; - pwms = <&pwm 0 10000 0>; + pwms = <&pwm 0 10000>; status = "okay"; }; @@ -146,19 +146,19 @@ &cpu_thermal { cooling-maps { - cpu-active-high { + map-cpu-active-high { /* active: set fan to cooling level 2 */ cooling-device = <&fan 2 2>; trip = <&cpu_trip_active_high>; }; - cpu-active-med { + map-cpu-active-med { /* active: set fan to cooling level 1 */ cooling-device = <&fan 1 1>; trip = <&cpu_trip_active_med>; }; - cpu-active-low { + map-cpu-active-low { /* active: set fan to cooling level 0 */ cooling-device = <&fan 0 0>; trip = <&cpu_trip_active_low>; diff --git a/src/arm64/mediatek/mt7986a-rfb.dts b/src/arm64/mediatek/mt7986a-rfb.dts index 3ef371ca254..5d8e3d3f6c2 100644 --- a/src/arm64/mediatek/mt7986a-rfb.dts +++ b/src/arm64/mediatek/mt7986a-rfb.dts @@ -65,6 +65,18 @@ }; }; + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + mdio: mdio-bus { #address-cells = <1>; #size-cells = <0>; @@ -237,12 +249,13 @@ pinctrl-0 = <&spi_flash_pins>; cs-gpios = <0>, <0>; status = "okay"; - spi_nand: spi_nand@0 { + + spi_nand: flash@0 { compatible = "spi-nand"; reg = <0>; spi-max-frequency = <10000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; }; }; @@ -287,6 +300,18 @@ label = "lan4"; }; + port@5 { + reg = <5>; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + port@6 { reg = <6>; label = "cpu"; diff --git a/src/arm64/mediatek/mt7986a.dtsi b/src/arm64/mediatek/mt7986a.dtsi index fc751e04995..559990dcd1d 100644 --- a/src/arm64/mediatek/mt7986a.dtsi +++ b/src/arm64/mediatek/mt7986a.dtsi @@ -16,6 +16,42 @@ #address-cells = <2>; #size-cells = <2>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x0>; + device_type = "cpu"; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x1>; + device_type = "cpu"; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + reg = <0x2>; + device_type = "cpu"; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + reg = <0x3>; + device_type = "cpu"; + enable-method = "psci"; + #cooling-cells = <2>; + }; + }; + clk40m: oscillator-40m { compatible = "fixed-clock"; clock-frequency = <40000000>; @@ -23,42 +59,6 @@ clock-output-names = "clkxtal"; }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x0>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x1>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x2>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - enable-method = "psci"; - compatible = "arm,cortex-a53"; - reg = <0x3>; - #cooling-cells = <2>; - }; - }; - psci { compatible = "arm,psci-0.2"; method = "smc"; @@ -121,38 +121,30 @@ }; - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - soc { - #address-cells = <2>; - #size-cells = <2>; compatible = "simple-bus"; ranges; + #address-cells = <2>; + #size-cells = <2>; gic: interrupt-controller@c000000 { compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - interrupt-controller; reg = <0 0x0c000000 0 0x10000>, /* GICD */ <0 0x0c080000 0 0x80000>, /* GICR */ <0 0x0c400000 0 0x2000>, /* GICC */ <0 0x0c410000 0 0x1000>, /* GICH */ <0 0x0c420000 0 0x2000>; /* GICV */ + interrupt-parent = <&gic>; interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; }; infracfg: infracfg@10001000 { compatible = "mediatek,mt7986-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; wed_pcie: wed-pcie@10003000 { @@ -202,6 +194,19 @@ #interrupt-cells = <2>; }; + pwm: pwm@10048000 { + compatible = "mediatek,mt7986-pwm"; + reg = <0 0x10048000 0 0x1000>; + #pwm-cells = <2>; + interrupts = ; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&infracfg CLK_INFRA_PWM_STA>, + <&infracfg CLK_INFRA_PWM1_CK>, + <&infracfg CLK_INFRA_PWM2_CK>; + clock-names = "top", "main", "pwm1", "pwm2"; + status = "disabled"; + }; + sgmiisys0: syscon@10060000 { compatible = "mediatek,mt7986-sgmiisys_0", "syscon"; @@ -234,26 +239,11 @@ ; interrupt-names = "ring0", "ring1", "ring2", "ring3"; clocks = <&infracfg CLK_INFRA_EIP97_CK>; - clock-names = "infra_eip97_ck"; assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>; assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>; status = "disabled"; }; - pwm: pwm@10048000 { - compatible = "mediatek,mt7986-pwm"; - reg = <0 0x10048000 0 0x1000>; - #clock-cells = <1>; - #pwm-cells = <2>; - interrupts = ; - clocks = <&topckgen CLK_TOP_PWM_SEL>, - <&infracfg CLK_INFRA_PWM_STA>, - <&infracfg CLK_INFRA_PWM1_CK>, - <&infracfg CLK_INFRA_PWM2_CK>; - clock-names = "top", "main", "pwm1", "pwm2"; - status = "disabled"; - }; - uart0: serial@11002000 { compatible = "mediatek,mt7986-uart", "mediatek,mt6577-uart"; @@ -311,9 +301,9 @@ spi0: spi@1100a000 { compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; + reg = <0 0x1100a000 0 0x100>; #address-cells = <1>; #size-cells = <0>; - reg = <0 0x1100a000 0 0x100>; interrupts = ; clocks = <&topckgen CLK_TOP_MPLL_D2>, <&topckgen CLK_TOP_SPI_SEL>, @@ -325,9 +315,9 @@ spi1: spi@1100b000 { compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; + reg = <0 0x1100b000 0 0x100>; #address-cells = <1>; #size-cells = <0>; - reg = <0 0x1100b000 0 0x100>; interrupts = ; clocks = <&topckgen CLK_TOP_MPLL_D2>, <&topckgen CLK_TOP_SPIM_MST_SEL>, @@ -337,6 +327,20 @@ status = "disabled"; }; + thermal: thermal@1100c800 { + compatible = "mediatek,mt7986-thermal"; + reg = <0 0x1100c800 0 0x800>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM_CK>, + <&infracfg CLK_INFRA_ADC_26M_CK>; + clock-names = "therm", "auxadc"; + nvmem-cells = <&thermal_calibration>; + nvmem-cell-names = "calibration-data"; + #thermal-sensor-cells = <1>; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + }; + auxadc: adc@1100d000 { compatible = "mediatek,mt7986-auxadc"; reg = <0 0x1100d000 0 0x1000>; @@ -388,39 +392,23 @@ status = "disabled"; }; - thermal: thermal@1100c800 { - #thermal-sensor-cells = <1>; - compatible = "mediatek,mt7986-thermal"; - reg = <0 0x1100c800 0 0x800>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_THERM_CK>, - <&infracfg CLK_INFRA_ADC_26M_CK>, - <&infracfg CLK_INFRA_ADC_FRC_CK>; - clock-names = "therm", "auxadc", "adc_32k"; - mediatek,auxadc = <&auxadc>; - mediatek,apmixedsys = <&apmixedsys>; - nvmem-cells = <&thermal_calibration>; - nvmem-cell-names = "calibration-data"; - }; - pcie: pcie@11280000 { compatible = "mediatek,mt7986-pcie", "mediatek,mt8192-pcie"; + reg = <0x00 0x11280000 0x00 0x4000>; + reg-names = "pcie-mac"; + ranges = <0x82000000 0x00 0x20000000 0x00 + 0x20000000 0x00 0x10000000>; device_type = "pci"; #address-cells = <3>; #size-cells = <2>; - reg = <0x00 0x11280000 0x00 0x4000>; - reg-names = "pcie-mac"; interrupts = ; bus-range = <0x00 0xff>; - ranges = <0x82000000 0x00 0x20000000 0x00 - 0x20000000 0x00 0x10000000>; clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, <&infracfg CLK_INFRA_IPCIE_CK>, <&infracfg CLK_INFRA_IPCIER_CK>, <&infracfg CLK_INFRA_IPCIEB_CK>; clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; - status = "disabled"; phys = <&pcie_port PHY_TYPE_PCIE>; phy-names = "pcie-phy"; @@ -431,6 +419,8 @@ <0 0 0 2 &pcie_intc 1>, <0 0 0 3 &pcie_intc 2>, <0 0 0 4 &pcie_intc 3>; + status = "disabled"; + pcie_intc: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; @@ -441,9 +431,9 @@ pcie_phy: t-phy { compatible = "mediatek,mt7986-tphy", "mediatek,generic-tphy-v2"; + ranges; #address-cells = <2>; #size-cells = <2>; - ranges; status = "disabled"; pcie_port: pcie-phy@11c00000 { @@ -468,9 +458,9 @@ usb_phy: t-phy@11e10000 { compatible = "mediatek,mt7986-tphy", "mediatek,generic-tphy-v2"; + ranges = <0 0 0x11e10000 0x1700>; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0 0x11e10000 0x1700>; status = "disabled"; u2port0: usb-phy@0 { @@ -498,8 +488,6 @@ }; ethsys: syscon@15000000 { - #address-cells = <1>; - #size-cells = <1>; compatible = "mediatek,mt7986-ethsys", "syscon"; reg = <0 0x15000000 0 0x1000>; @@ -533,20 +521,6 @@ mediatek,wo-ccif = <&wo_ccif1>; }; - wo_ccif0: syscon@151a5000 { - compatible = "mediatek,mt7986-wo-ccif", "syscon"; - reg = <0 0x151a5000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - }; - - wo_ccif1: syscon@151ad000 { - compatible = "mediatek,mt7986-wo-ccif", "syscon"; - reg = <0 0x151ad000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - }; - eth: ethernet@15100000 { compatible = "mediatek,mt7986-eth"; reg = <0 0x15100000 0 0x80000>; @@ -579,26 +553,39 @@ <&topckgen CLK_TOP_SGM_325M_SEL>; assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, <&apmixedsys CLK_APMIXED_SGMPLL>; + #address-cells = <1>; + #size-cells = <0>; mediatek,ethsys = <ðsys>; mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; mediatek,wed-pcie = <&wed_pcie>; mediatek,wed = <&wed0>, <&wed1>; - #reset-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; + wo_ccif0: syscon@151a5000 { + compatible = "mediatek,mt7986-wo-ccif", "syscon"; + reg = <0 0x151a5000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + wo_ccif1: syscon@151ad000 { + compatible = "mediatek,mt7986-wo-ccif", "syscon"; + reg = <0 0x151ad000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + }; + wifi: wifi@18000000 { compatible = "mediatek,mt7986-wmac"; + reg = <0 0x18000000 0 0x1000000>, + <0 0x10003000 0 0x1000>, + <0 0x11d10000 0 0x1000>; resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; reset-names = "consys"; clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>, <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; clock-names = "mcu", "ap2conn"; - reg = <0 0x18000000 0 0x1000000>, - <0 0x10003000 0 0x1000>, - <0 0x11d10000 0 0x1000>; interrupts = , , , @@ -646,4 +633,13 @@ }; }; }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; }; diff --git a/src/arm64/mediatek/mt7986b-rfb.dts b/src/arm64/mediatek/mt7986b-rfb.dts index dde190442e3..58f77d93242 100644 --- a/src/arm64/mediatek/mt7986b-rfb.dts +++ b/src/arm64/mediatek/mt7986b-rfb.dts @@ -45,6 +45,18 @@ }; }; + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + mdio: mdio-bus { #address-cells = <1>; #size-cells = <0>; @@ -83,6 +95,18 @@ label = "lan4"; }; + port@5 { + reg = <5>; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + port@6 { reg = <6>; label = "cpu"; @@ -152,12 +176,13 @@ pinctrl-0 = <&spi_flash_pins>; cs-gpios = <0>, <0>; status = "okay"; - spi_nand: spi_nand@0 { + + spi_nand: flash@0 { compatible = "spi-nand"; reg = <0>; spi-max-frequency = <10000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; }; }; diff --git a/src/arm64/mediatek/mt7988a-bananapi-bpi-r4.dts b/src/arm64/mediatek/mt7988a-bananapi-bpi-r4.dts new file mode 100644 index 00000000000..efc4ad0b08b --- /dev/null +++ b/src/arm64/mediatek/mt7988a-bananapi-bpi-r4.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +/dts-v1/; + +#include "mt7988a.dtsi" + +/ { + compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; + model = "Banana Pi BPI-R4"; + chassis-type = "embedded"; +}; diff --git a/src/arm64/mediatek/mt7988a.dtsi b/src/arm64/mediatek/mt7988a.dtsi new file mode 100644 index 00000000000..bba97de4fb4 --- /dev/null +++ b/src/arm64/mediatek/mt7988a.dtsi @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +#include + +/ { + compatible = "mediatek,mt7988a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a73"; + reg = <0x0>; + device_type = "cpu"; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "arm,cortex-a73"; + reg = <0x1>; + device_type = "cpu"; + enable-method = "psci"; + }; + + cpu@2 { + compatible = "arm,cortex-a73"; + reg = <0x2>; + device_type = "cpu"; + enable-method = "psci"; + }; + + cpu@3 { + compatible = "arm,cortex-a73"; + reg = <0x3>; + device_type = "cpu"; + enable-method = "psci"; + }; + }; + + oscillator-40m { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + clock-output-names = "clkxtal"; + }; + + pmu { + compatible = "arm,cortex-a73-pmu"; + interrupt-parent = <&gic>; + interrupts = ; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + soc { + compatible = "simple-bus"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + reg = <0 0x0c000000 0 0x40000>, /* GICD */ + <0 0x0c080000 0 0x200000>, /* GICR */ + <0 0x0c400000 0 0x2000>, /* GICC */ + <0 0x0c410000 0 0x1000>, /* GICH */ + <0 0x0c420000 0 0x2000>; /* GICV */ + interrupt-parent = <&gic>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + + clock-controller@10001000 { + compatible = "mediatek,mt7988-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + clock-controller@1001b000 { + compatible = "mediatek,mt7988-topckgen", "syscon"; + reg = <0 0x1001b000 0 0x1000>; + #clock-cells = <1>; + }; + + watchdog: watchdog@1001c000 { + compatible = "mediatek,mt7988-wdt"; + reg = <0 0x1001c000 0 0x1000>; + interrupts = ; + #reset-cells = <1>; + }; + + clock-controller@1001e000 { + compatible = "mediatek,mt7988-apmixedsys"; + reg = <0 0x1001e000 0 0x1000>; + #clock-cells = <1>; + }; + + clock-controller@11f40000 { + compatible = "mediatek,mt7988-xfi-pll"; + reg = <0 0x11f40000 0 0x1000>; + resets = <&watchdog 16>; + #clock-cells = <1>; + }; + + clock-controller@15000000 { + compatible = "mediatek,mt7988-ethsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock-controller@15031000 { + compatible = "mediatek,mt7988-ethwarp"; + reg = <0 0x15031000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; +}; diff --git a/src/arm64/mediatek/mt8173-elm-hana-rev7.dts b/src/arm64/mediatek/mt8173-elm-hana-rev7.dts index 256f245ac01..1c9fc791bdf 100644 --- a/src/arm64/mediatek/mt8173-elm-hana-rev7.dts +++ b/src/arm64/mediatek/mt8173-elm-hana-rev7.dts @@ -14,7 +14,7 @@ &cpu_thermal { trips { - cpu_crit: cpu_crit0 { + cpu_crit: cpu-crit0 { temperature = <100000>; type = "critical"; }; diff --git a/src/arm64/mediatek/mt8173-elm.dtsi b/src/arm64/mediatek/mt8173-elm.dtsi index 8d614ac2c58..6d962d437e0 100644 --- a/src/arm64/mediatek/mt8173-elm.dtsi +++ b/src/arm64/mediatek/mt8173-elm.dtsi @@ -1135,7 +1135,7 @@ compatible = "mediatek,mt6397-rtc"; }; - syscfg_pctl_pmic: syscfg_pctl_pmic@c000 { + syscfg_pctl_pmic: syscon@c000 { compatible = "mediatek,mt6397-pctl-pmic-syscfg", "syscon"; reg = <0 0x0000c000 0 0x0108>; @@ -1155,6 +1155,7 @@ spi-max-frequency = <12000000>; interrupts-extended = <&pio 0 IRQ_TYPE_LEVEL_LOW>; google,cros-ec-spi-msg-delay = <500>; + wakeup-source; i2c_tunnel: i2c-tunnel0 { compatible = "google,cros-ec-i2c-tunnel"; diff --git a/src/arm64/mediatek/mt8173-evb.dts b/src/arm64/mediatek/mt8173-evb.dts index 0e5c628d1ec..3fab21f59d1 100644 --- a/src/arm64/mediatek/mt8173-evb.dts +++ b/src/arm64/mediatek/mt8173-evb.dts @@ -41,7 +41,7 @@ extcon_usb: extcon_iddig { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pio 16 GPIO_ACTIVE_HIGH>; + id-gpios = <&pio 16 GPIO_ACTIVE_HIGH>; }; usb_p1_vbus: regulator-usb-p1 { diff --git a/src/arm64/mediatek/mt8173.dtsi b/src/arm64/mediatek/mt8173.dtsi index cac4cd0a032..3458be7f7f6 100644 --- a/src/arm64/mediatek/mt8173.dtsi +++ b/src/arm64/mediatek/mt8173.dtsi @@ -222,14 +222,14 @@ }; }; - pmu_a53 { + pmu-a53 { compatible = "arm,cortex-a53-pmu"; interrupts = , ; interrupt-affinity = <&cpu0>, <&cpu1>; }; - pmu_a72 { + pmu-a72 { compatible = "arm,cortex-a72-pmu"; interrupts = , ; @@ -286,7 +286,7 @@ type = "passive"; }; - cpu_crit: cpu_crit0 { + cpu_crit: cpu-crit0 { temperature = <115000>; hysteresis = <2000>; type = "critical"; @@ -318,7 +318,7 @@ #address-cells = <2>; #size-cells = <2>; ranges; - vpu_dma_reserved: vpu_dma_mem_region@b7000000 { + vpu_dma_reserved: vpu-dma-mem@b7000000 { compatible = "shared-dma-pool"; reg = <0 0xb7000000 0 0x500000>; alignment = <0x1000>; @@ -366,7 +366,7 @@ #reset-cells = <1>; }; - syscfg_pctl_a: syscfg_pctl_a@10005000 { + syscfg_pctl_a: syscon@10005000 { compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; reg = <0 0x10005000 0 0x1000>; }; @@ -590,6 +590,15 @@ reg = <0 0x10206000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; + + socinfo-data1@40 { + reg = <0x040 0x4>; + }; + + socinfo-data2@44 { + reg = <0x044 0x4>; + }; + thermal_calibration: calib@528 { reg = <0x528 0xc>; }; diff --git a/src/arm64/mediatek/mt8183-kukui-jacuzzi-pico6.dts b/src/arm64/mediatek/mt8183-kukui-jacuzzi-pico6.dts index a2e74b82932..6a7ae616512 100644 --- a/src/arm64/mediatek/mt8183-kukui-jacuzzi-pico6.dts +++ b/src/arm64/mediatek/mt8183-kukui-jacuzzi-pico6.dts @@ -82,7 +82,8 @@ }; &mmc1 { - bt_reset: bt-reset { + bluetooth@2 { + reg = <2>; compatible = "mediatek,mt7921s-bluetooth"; pinctrl-names = "default"; pinctrl-0 = <&bt_pins_reset>; diff --git a/src/arm64/mediatek/mt8183-kukui-kakadu.dtsi b/src/arm64/mediatek/mt8183-kukui-kakadu.dtsi index b6a9830af26..bfb9e42c8ac 100644 --- a/src/arm64/mediatek/mt8183-kukui-kakadu.dtsi +++ b/src/arm64/mediatek/mt8183-kukui-kakadu.dtsi @@ -360,6 +360,10 @@ }; &cros_ec { + cbas { + compatible = "google,cros-cbas"; + }; + keyboard-controller { compatible = "google,cros-ec-keyb-switches"; }; diff --git a/src/arm64/mediatek/mt8183-kukui-kodama.dtsi b/src/arm64/mediatek/mt8183-kukui-kodama.dtsi index 306c95166f3..5c1bf6a1e47 100644 --- a/src/arm64/mediatek/mt8183-kukui-kodama.dtsi +++ b/src/arm64/mediatek/mt8183-kukui-kodama.dtsi @@ -339,6 +339,10 @@ }; &cros_ec { + cbas { + compatible = "google,cros-cbas"; + }; + keyboard-controller { compatible = "google,cros-ec-keyb-switches"; }; diff --git a/src/arm64/mediatek/mt8183-kukui-krane.dtsi b/src/arm64/mediatek/mt8183-kukui-krane.dtsi index 382e4c6d719..0f5fa893a77 100644 --- a/src/arm64/mediatek/mt8183-kukui-krane.dtsi +++ b/src/arm64/mediatek/mt8183-kukui-krane.dtsi @@ -343,6 +343,10 @@ }; &cros_ec { + cbas { + compatible = "google,cros-cbas"; + }; + keyboard-controller { compatible = "google,cros-ec-keyb-switches"; }; diff --git a/src/arm64/mediatek/mt8183-kukui.dtsi b/src/arm64/mediatek/mt8183-kukui.dtsi index 1b3396b1cee..100191c6453 100644 --- a/src/arm64/mediatek/mt8183-kukui.dtsi +++ b/src/arm64/mediatek/mt8183-kukui.dtsi @@ -433,7 +433,6 @@ }; &mt6358_vgpu_reg { - regulator-min-microvolt = <625000>; regulator-max-microvolt = <900000>; regulator-coupled-with = <&mt6358_vsram_gpu_reg>; @@ -924,6 +923,7 @@ interrupts-extended = <&pio 151 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&ec_ap_int_odl>; + wakeup-source; i2c_tunnel: i2c-tunnel { compatible = "google,cros-ec-i2c-tunnel"; @@ -937,10 +937,6 @@ google,usb-port-id = <0>; }; - cbas { - compatible = "google,cros-cbas"; - }; - typec { compatible = "google,cros-ec-typec"; #address-cells = <1>; diff --git a/src/arm64/mediatek/mt8183-pumpkin.dts b/src/arm64/mediatek/mt8183-pumpkin.dts index 76449b4cf23..333c516af49 100644 --- a/src/arm64/mediatek/mt8183-pumpkin.dts +++ b/src/arm64/mediatek/mt8183-pumpkin.dts @@ -33,7 +33,7 @@ #size-cells = <2>; ranges; - scp_mem_reserved: scp_mem_region@50000000 { + scp_mem_reserved: scp-mem@50000000 { compatible = "shared-dma-pool"; reg = <0 0x50000000 0 0x2900000>; no-map; diff --git a/src/arm64/mediatek/mt8183.dtsi b/src/arm64/mediatek/mt8183.dtsi index 920ee415ef5..774ae5d9143 100644 --- a/src/arm64/mediatek/mt8183.dtsi +++ b/src/arm64/mediatek/mt8183.dtsi @@ -1585,6 +1585,15 @@ reg = <0 0x11f10000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; + + socinfo-data1@4c { + reg = <0x04c 0x4>; + }; + + socinfo-data2@60 { + reg = <0x060 0x4>; + }; + thermal_calibration: calib@180 { reg = <0x180 0xc>; }; @@ -1628,6 +1637,7 @@ compatible = "mediatek,mt8183-mfgcfg", "syscon"; reg = <0 0x13000000 0 0x1000>; #clock-cells = <1>; + power-domains = <&spm MT8183_POWER_DOMAIN_MFG_ASYNC>; }; gpu: gpu@13040000 { @@ -1955,7 +1965,7 @@ power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; }; - venc_jpg: venc_jpg@17030000 { + venc_jpg: jpeg-encoder@17030000 { compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc"; reg = <0 0x17030000 0 0x1000>; interrupts = ; diff --git a/src/arm64/mediatek/mt8186-corsola-krabby.dtsi b/src/arm64/mediatek/mt8186-corsola-krabby.dtsi new file mode 100644 index 00000000000..7c971198fa9 --- /dev/null +++ b/src/arm64/mediatek/mt8186-corsola-krabby.dtsi @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola.dtsi" +#include + +/ { + aliases { + i2c4 = &i2c4; + }; +}; + +&dsi_out { + remote-endpoint = <&ps8640_in>; +}; + +&i2c0 { + clock-frequency = <400000>; + + edp-bridge@8 { + compatible = "parade,ps8640"; + reg = <0x8>; + pinctrl-names = "default"; + pinctrl-0 = <&ps8640_pins>; + powerdown-gpios = <&pio 96 GPIO_ACTIVE_LOW>; + reset-gpios = <&pio 98 GPIO_ACTIVE_LOW>; + vdd12-supply = <&mt6366_vrf12_reg>; + vdd33-supply = <&mt6366_vcn33_reg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ps8640_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + ps8640_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + aux-bus { + panel { + compatible = "edp-panel"; + power-supply = <&pp3300_disp_x>; + backlight = <&backlight_lcd0>; + + port { + panel_in: endpoint { + remote-endpoint = <&ps8640_out>; + }; + }; + }; + }; + }; +}; + +&i2c1 { + i2c-scl-internal-delay-ns = <10000>; + + touchscreen: touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + post-power-on-delay-ms = <10>; + hid-descr-addr = <0x0001>; + vdd-supply = <&pp3300_s3>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + clock-frequency = <400000>; + status = "okay"; + + proximity@28 { + compatible = "semtech,sx9324"; + reg = <0x28>; + #io-channel-cells = <1>; + interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sar_sensor_pins>; + vdd-supply = <&mt6366_vio18_reg>; + svdd-supply = <&mt6366_vio18_reg>; + }; +}; + +&pio { + i2c4_pins: i2c4-pins { + pins-bus { + pinmux = , + ; + bias-disable; + drive-strength = <4>; + input-enable; + }; + }; + + ps8640_pins: ps8640-pins { + pins-pwrdn-rst { + pinmux = , + ; + output-low; + }; + }; + + sar_sensor_pins: sar-sensor-pins { + pins-irq { + pinmux = ; + input-enable; + bias-pull-up; + }; + }; +}; diff --git a/src/arm64/mediatek/mt8186-corsola-magneton-sku393216.dts b/src/arm64/mediatek/mt8186-corsola-magneton-sku393216.dts new file mode 100644 index 00000000000..c9673381ad3 --- /dev/null +++ b/src/arm64/mediatek/mt8186-corsola-magneton-sku393216.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-steelix.dtsi" + +/ { + model = "Google Magneton board"; + compatible = "google,steelix-sku393219", "google,steelix-sku393216", + "google,steelix", "mediatek,mt8186"; + chassis-type = "laptop"; +}; + +&gpio_keys { + status = "disabled"; +}; + +&i2c1 { + touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + vdd-supply = <&pp3300_s3>; + post-power-on-delay-ms = <350>; + hid-descr-addr = <0x0001>; + }; +}; + +&touchscreen { + status = "disabled"; +}; + +&usb_c1 { + status = "disabled"; +}; diff --git a/src/arm64/mediatek/mt8186-corsola-magneton-sku393217.dts b/src/arm64/mediatek/mt8186-corsola-magneton-sku393217.dts new file mode 100644 index 00000000000..28e3bbe5642 --- /dev/null +++ b/src/arm64/mediatek/mt8186-corsola-magneton-sku393217.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-steelix.dtsi" + +/ { + model = "Google Magneton board"; + compatible = "google,steelix-sku393220", "google,steelix-sku393217", + "google,steelix", "mediatek,mt8186"; + chassis-type = "laptop"; +}; + +&gpio_keys { + status = "disabled"; +}; + +&i2c1 { + touchscreen@40 { + compatible = "hid-over-i2c"; + reg = <0x40>; + interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + vdd-supply = <&pp3300_s3>; + post-power-on-delay-ms = <450>; + hid-descr-addr = <0x0001>; + }; +}; + +&touchscreen { + status = "disabled"; +}; + +&usb_c1 { + status = "disabled"; +}; diff --git a/src/arm64/mediatek/mt8186-corsola-magneton-sku393218.dts b/src/arm64/mediatek/mt8186-corsola-magneton-sku393218.dts new file mode 100644 index 00000000000..332894218f0 --- /dev/null +++ b/src/arm64/mediatek/mt8186-corsola-magneton-sku393218.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-steelix.dtsi" + +/ { + model = "Google Magneton board"; + compatible = "google,steelix-sku393221", "google,steelix-sku393218", + "google,steelix", "mediatek,mt8186"; + chassis-type = "laptop"; +}; + +&gpio_keys { + status = "disabled"; +}; + +&touchscreen { + status = "disabled"; +}; + +&usb_c1 { + status = "disabled"; +}; diff --git a/src/arm64/mediatek/mt8186-corsola-rusty-sku196608.dts b/src/arm64/mediatek/mt8186-corsola-rusty-sku196608.dts new file mode 100644 index 00000000000..731b0d60228 --- /dev/null +++ b/src/arm64/mediatek/mt8186-corsola-rusty-sku196608.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-steelix.dtsi" + +/ { + model = "Google Rusty board"; + compatible = "google,steelix-sku196609", "google,steelix-sku196608", + "google,steelix", "mediatek,mt8186"; + chassis-type = "laptop"; +}; + +&gpio_keys { + status = "disabled"; +}; + +&i2c1 { + status = "disabled"; +}; + +&touchscreen { + status = "disabled"; +}; diff --git a/src/arm64/mediatek/mt8186-corsola-steelix-sku131072.dts b/src/arm64/mediatek/mt8186-corsola-steelix-sku131072.dts new file mode 100644 index 00000000000..eae17bca858 --- /dev/null +++ b/src/arm64/mediatek/mt8186-corsola-steelix-sku131072.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-steelix.dtsi" + +/ { + model = "Google Steelix board"; + compatible = "google,steelix-sku131072", "google,steelix", + "mediatek,mt8186"; + chassis-type = "convertible"; +}; + +&mt6366codec { + mediatek,dmic-mode = <0>; /* two-wire */ +}; diff --git a/src/arm64/mediatek/mt8186-corsola-steelix-sku131073.dts b/src/arm64/mediatek/mt8186-corsola-steelix-sku131073.dts new file mode 100644 index 00000000000..a55375b95d0 --- /dev/null +++ b/src/arm64/mediatek/mt8186-corsola-steelix-sku131073.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-steelix.dtsi" + +/ { + model = "Google Steelix board"; + compatible = "google,steelix-sku131073", "google,steelix", + "mediatek,mt8186"; + chassis-type = "convertible"; +}; + +&mt6366codec { + mediatek,dmic-mode = <1>; /* one-wire */ +}; diff --git a/src/arm64/mediatek/mt8186-corsola-steelix.dtsi b/src/arm64/mediatek/mt8186-corsola-steelix.dtsi new file mode 100644 index 00000000000..e74e886a00c --- /dev/null +++ b/src/arm64/mediatek/mt8186-corsola-steelix.dtsi @@ -0,0 +1,199 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola.dtsi" +#include +#include + +/{ + pp1000_edpbrdg: regulator-pp1000-edpbrdg { + compatible = "regulator-fixed"; + regulator-name = "pp1000_edpbrdg"; + pinctrl-names = "default"; + pinctrl-0 = <&en_pp1000_edpbrdg>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 29 GPIO_ACTIVE_HIGH>; + vin-supply = <&pp3300_z2>; + }; + + pp1800_edpbrdg_dx: regulator-pp1800-edpbrdg-dx { + compatible = "regulator-fixed"; + regulator-name = "pp1800_edpbrdg_dx"; + pinctrl-names = "default"; + pinctrl-0 = <&en_pp1800_edpbrdg>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 30 GPIO_ACTIVE_HIGH>; + vin-supply = <&mt6366_vio18_reg>; + }; + + pp3300_edp_dx: regulator-pp3300-edp-dx { + compatible = "regulator-fixed"; + regulator-name = "pp3300_edp_dx"; + pinctrl-names = "default"; + pinctrl-0 = <&en_pp3300_edpbrdg>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 31 GPIO_ACTIVE_HIGH>; + vin-supply = <&pp3300_z2>; + }; +}; + +&dsi_out { + remote-endpoint = <&anx7625_in>; +}; + +&i2c0 { + clock-frequency = <400000>; + + anx_bridge: anx7625@58 { + compatible = "analogix,anx7625"; + reg = <0x58>; + pinctrl-names = "default"; + pinctrl-0 = <&anx7625_pins>; + enable-gpios = <&pio 96 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 98 GPIO_ACTIVE_HIGH>; + vdd10-supply = <&pp1000_edpbrdg>; + vdd18-supply = <&pp1800_edpbrdg_dx>; + vdd33-supply = <&pp3300_edp_dx>; + analogix,lane0-swing = /bits/ 8 <0x70 0x30>; + analogix,lane1-swing = /bits/ 8 <0x70 0x30>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + anx7625_in: endpoint { + remote-endpoint = <&dsi_out>; + data-lanes = <0 1 2 3>; + }; + }; + + port@1 { + reg = <1>; + + anx7625_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + aux-bus { + panel: panel { + compatible = "edp-panel"; + power-supply = <&pp3300_disp_x>; + backlight = <&backlight_lcd0>; + + port { + panel_in: endpoint { + remote-endpoint = <&anx7625_out>; + }; + }; + }; + }; + }; +}; + +&i2c1 { + touchscreen: touchscreen@5d { + compatible = "goodix,gt7375p"; + reg = <0x5d>; + interrupts-extended = <&pio 12 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + reset-gpios = <&pio 60 GPIO_ACTIVE_LOW>; + vdd-supply = <&pp3300_s3>; + goodix,no-reset-during-suspend; + }; +}; + +&i2c2 { + i2c-scl-internal-delay-ns = <22000>; + + /* second source component */ + trackpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + hid-descr-addr = <0x20>; + interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&pp3300_s3>; + wakeup-source; + }; +}; + +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x01, 0x04, KEY_MICMUTE) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + CROS_STD_MAIN_KEYMAP + >; +}; + +&pio { + anx7625_pins: anx7625-pins { + pins-int { + pinmux = ; + input-enable; + bias-disable; + }; + + pins-reset { + pinmux = ; + output-low; + }; + + pins-power-en { + pinmux = ; + output-low; + }; + }; + + en_pp1000_edpbrdg: pp1000-edpbrdg-en-pins { + pins-vreg-en { + pinmux = ; + output-low; + }; + }; + + en_pp1800_edpbrdg: pp1800-edpbrdg-en-pins { + pins-vreg-en { + pinmux = ; + output-low; + }; + }; + + en_pp3300_edpbrdg: pp3300-edpbrdg-en-pins { + pins-vreg-en { + pinmux = ; + output-low; + }; + }; +}; diff --git a/src/arm64/mediatek/mt8186-corsola-tentacool-sku327681.dts b/src/arm64/mediatek/mt8186-corsola-tentacool-sku327681.dts new file mode 100644 index 00000000000..9bb64353ca6 --- /dev/null +++ b/src/arm64/mediatek/mt8186-corsola-tentacool-sku327681.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-krabby.dtsi" + +/ { + model = "Google Tentacool board"; + compatible = "google,tentacruel-sku327681", "google,tentacruel", "mediatek,mt8186"; + chassis-type = "laptop"; +}; + +/* Tentacool omits the pen. */ +&gpio_keys { + status = "disabled"; +}; + +/* Tentacool omits the touchscreen; nothing else is on i2c1. */ +&i2c1 { + status = "disabled"; +}; + +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + CROS_STD_MAIN_KEYMAP + >; +}; + +/* Tentacool omits the touchscreen. */ +&touchscreen { + status = "disabled"; +}; diff --git a/src/arm64/mediatek/mt8186-corsola-tentacool-sku327683.dts b/src/arm64/mediatek/mt8186-corsola-tentacool-sku327683.dts new file mode 100644 index 00000000000..c3ae6f9616c --- /dev/null +++ b/src/arm64/mediatek/mt8186-corsola-tentacool-sku327683.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2023 Google LLC + */ + +#include "mt8186-corsola-tentacool-sku327681.dts" + +/ { + compatible = "google,tentacruel-sku327683", "google,tentacruel", "mediatek,mt8186"; +}; + +/* This variant replaces only the trackpad controller. */ +&i2c2 { + /delete-node/ trackpad@15; + + trackpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_LOW>; + hid-descr-addr = <0x0001>; + vdd-supply = <&pp3300_s3>; + wakeup-source; + }; +}; diff --git a/src/arm64/mediatek/mt8186-corsola-tentacruel-sku262144.dts b/src/arm64/mediatek/mt8186-corsola-tentacruel-sku262144.dts new file mode 100644 index 00000000000..26d3451a5e4 --- /dev/null +++ b/src/arm64/mediatek/mt8186-corsola-tentacruel-sku262144.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-krabby.dtsi" + +/ { + model = "Google Tentacruel board"; + compatible = "google,tentacruel-sku262147", "google,tentacruel-sku262146", + "google,tentacruel-sku262145", "google,tentacruel-sku262144", + "google,tentacruel", "mediatek,mt8186"; + chassis-type = "convertible"; +}; + +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + CROS_STD_MAIN_KEYMAP + >; +}; diff --git a/src/arm64/mediatek/mt8186-corsola-tentacruel-sku262148.dts b/src/arm64/mediatek/mt8186-corsola-tentacruel-sku262148.dts new file mode 100644 index 00000000000..447b57b12b4 --- /dev/null +++ b/src/arm64/mediatek/mt8186-corsola-tentacruel-sku262148.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2023 Google LLC + */ + +#include "mt8186-corsola-tentacruel-sku262144.dts" + +/ { + compatible = "google,tentacruel-sku262151", "google,tentacruel-sku262150", + "google,tentacruel-sku262149", "google,tentacruel-sku262148", + "google,tentacruel", "mediatek,mt8186"; +}; + +/* This variant replaces only the trackpad controller. */ +&i2c2 { + /delete-node/ trackpad@15; + + trackpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_LOW>; + hid-descr-addr = <0x0001>; + vdd-supply = <&pp3300_s3>; + wakeup-source; + }; +}; diff --git a/src/arm64/mediatek/mt8186-corsola.dtsi b/src/arm64/mediatek/mt8186-corsola.dtsi new file mode 100644 index 00000000000..1807e9d6cb0 --- /dev/null +++ b/src/arm64/mediatek/mt8186-corsola.dtsi @@ -0,0 +1,1681 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + */ +/dts-v1/; +#include "mt8186.dtsi" +#include +#include +#include +#include +#include + +/ { + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c5 = &i2c5; + mmc0 = &mmc0; + mmc1 = &mmc1; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + /* The size should be filled in by the bootloader. */ + reg = <0 0x40000000 0 0>; + }; + + backlight_lcd0: backlight-lcd0 { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 500000>; + power-supply = <&ppvar_sys>; + enable-gpios = <&pio 152 0>; + brightness-levels = <0 1023>; + num-interpolated-steps = <1023>; + default-brightness-level = <576>; + }; + + bt-sco-codec { + compatible = "linux,bt-sco"; + #sound-dai-cells = <0>; + }; + + dmic-codec { + compatible = "dmic-codec"; + #sound-dai-cells = <0>; + num-channels = <2>; + wakeup-delay-ms = <50>; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pen_eject>; + + pen_insert: pen-insert-switch { + label = "Pen Insert"; + /* Insert = low, eject = high */ + gpios = <&pio 18 GPIO_ACTIVE_LOW>; + wakeup-event-action = ; + wakeup-source; + linux,code = ; + linux,input-type = ; + }; + }; + + pp1800_dpbrdg_dx: regulator-pp1800-dpbrdg-dx { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&en_pp1800_dpbrdg>; + gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + regulator-name = "pp1800_dpbrdg_dx"; + enable-active-high; + vin-supply = <&mt6366_vio18_reg>; + }; + + pp3300_disp_x: regulator-pp3300-disp-x { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&edp_panel_fixed_pins>; + gpios = <&pio 153 GPIO_ACTIVE_HIGH>; + regulator-name = "pp3300_disp_x"; + enable-active-high; + regulator-boot-on; + vin-supply = <&pp3300_z2>; + }; + + /* system wide LDO 3.3V power rail */ + pp3300_z5: regulator-pp3300-ldo-z5 { + compatible = "regulator-fixed"; + regulator-name = "pp3300_ldo_z5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&ppvar_sys>; + }; + + /* separately switched 3.3V power rail */ + pp3300_s3: regulator-pp3300-s3 { + compatible = "regulator-fixed"; + regulator-name = "pp3300_s3"; + /* automatically sequenced by PMIC EXT_PMIC_EN2 */ + regulator-always-on; + regulator-boot-on; + vin-supply = <&pp3300_z2>; + }; + + /* system wide 3.3V power rail */ + pp3300_z2: regulator-pp3300-z2 { + compatible = "regulator-fixed"; + regulator-name = "pp3300_z2"; + /* EN pin tied to pp4200_z2, which is controlled by EC */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&ppvar_sys>; + }; + + /* system wide 4.2V power rail */ + pp4200_z2: regulator-pp4200-z2 { + compatible = "regulator-fixed"; + regulator-name = "pp4200_z2"; + /* controlled by EC */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + vin-supply = <&ppvar_sys>; + }; + + /* system wide switching 5.0V power rail */ + pp5000_z2: regulator-pp5000-z2 { + compatible = "regulator-fixed"; + regulator-name = "pp5000_z2"; + /* controlled by EC */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&ppvar_sys>; + }; + + /* system wide semi-regulated power rail from battery or USB */ + ppvar_sys: regulator-ppvar-sys { + compatible = "regulator-fixed"; + regulator-name = "ppvar_sys"; + regulator-always-on; + regulator-boot-on; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + adsp_dma_mem: memory@61000000 { + compatible = "shared-dma-pool"; + reg = <0 0x61000000 0 0x100000>; + no-map; + }; + + adsp_mem: memory@60000000 { + compatible = "shared-dma-pool"; + reg = <0 0x60000000 0 0xA00000>; + no-map; + }; + + scp_mem: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x10a0000>; + no-map; + }; + }; + + sound: sound { + compatible = "mediatek,mt8186-mt6366-rt1019-rt5682s-sound"; + pinctrl-names = "aud_clk_mosi_off", + "aud_clk_mosi_on", + "aud_clk_miso_off", + "aud_clk_miso_on", + "aud_dat_miso_off", + "aud_dat_miso_on", + "aud_dat_mosi_off", + "aud_dat_mosi_on", + "aud_gpio_i2s0_off", + "aud_gpio_i2s0_on", + "aud_gpio_i2s1_off", + "aud_gpio_i2s1_on", + "aud_gpio_i2s2_off", + "aud_gpio_i2s2_on", + "aud_gpio_i2s3_off", + "aud_gpio_i2s3_on", + "aud_gpio_pcm_off", + "aud_gpio_pcm_on", + "aud_gpio_dmic_sec"; + pinctrl-0 = <&aud_clk_mosi_off>; + pinctrl-1 = <&aud_clk_mosi_on>; + pinctrl-2 = <&aud_clk_miso_off>; + pinctrl-3 = <&aud_clk_miso_on>; + pinctrl-4 = <&aud_dat_miso_off>; + pinctrl-5 = <&aud_dat_miso_on>; + pinctrl-6 = <&aud_dat_mosi_off>; + pinctrl-7 = <&aud_dat_mosi_on>; + pinctrl-8 = <&aud_gpio_i2s0_off>; + pinctrl-9 = <&aud_gpio_i2s0_on>; + pinctrl-10 = <&aud_gpio_i2s1_off>; + pinctrl-11 = <&aud_gpio_i2s1_on>; + pinctrl-12 = <&aud_gpio_i2s2_off>; + pinctrl-13 = <&aud_gpio_i2s2_on>; + pinctrl-14 = <&aud_gpio_i2s3_off>; + pinctrl-15 = <&aud_gpio_i2s3_on>; + pinctrl-16 = <&aud_gpio_pcm_off>; + pinctrl-17 = <&aud_gpio_pcm_on>; + pinctrl-18 = <&aud_gpio_dmic_sec>; + mediatek,adsp = <&adsp>; + mediatek,platform = <&afe>; + + playback-codecs { + sound-dai = <&it6505dptx>, <&rt1019p>; + }; + + headset-codec { + sound-dai = <&rt5682s 0>; + }; + }; + + rt1019p: speaker-codec { + compatible = "realtek,rt1019p"; + pinctrl-names = "default"; + pinctrl-0 = <&rt1019p_pins_default>; + #sound-dai-cells = <0>; + sdb-gpios = <&pio 150 GPIO_ACTIVE_HIGH>; + }; + + usb_p1_vbus: regulator-usb-p1-vbus { + compatible = "regulator-fixed"; + gpio = <&pio 148 GPIO_ACTIVE_HIGH>; + regulator-name = "vbus1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + vin-supply = <&pp5000_z2>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_pin>; + post-power-on-delay-ms = <50>; + reset-gpios = <&pio 54 GPIO_ACTIVE_LOW>; + }; + + wifi_wakeup: wifi-wakeup { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_wakeup_pin>; + + wowlan-event { + label = "Wake on WiFi"; + gpios = <&pio 7 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; +}; + +&adsp { + memory-region = <&adsp_dma_mem>, <&adsp_mem>; + status = "okay"; +}; + +&afe { + status = "okay"; +}; + +&cci { + proc-supply = <&mt6366_vproc12_reg>; +}; + +&cpu0 { + proc-supply = <&mt6366_vproc12_reg>; +}; + +&cpu1 { + proc-supply = <&mt6366_vproc12_reg>; +}; + +&cpu2 { + proc-supply = <&mt6366_vproc12_reg>; +}; + +&cpu3 { + proc-supply = <&mt6366_vproc12_reg>; +}; + +&cpu4 { + proc-supply = <&mt6366_vproc12_reg>; +}; + +&cpu5 { + proc-supply = <&mt6366_vproc12_reg>; +}; + +&cpu6 { + proc-supply = <&mt6366_vproc11_reg>; +}; + +&cpu7 { + proc-supply = <&mt6366_vproc11_reg>; +}; + +&dpi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dpi_pins_default>; + pinctrl-1 = <&dpi_pins_sleep>; + status = "okay"; +}; + +&dpi_out { + remote-endpoint = <&it6505_in>; +}; + +&dsi0 { + status = "okay"; +}; + +&gic { + mediatek,broken-save-restore-fw; +}; + +&gpu { + mali-supply = <&mt6366_vgpu_reg>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + i2c-scl-internal-delay-ns = <8000>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + /* + * Trackpad pin put here to work around second source components + * sharing the pinmux in steelix designs. + */ + pinctrl-0 = <&i2c2_pins>, <&trackpad_pin>; + clock-frequency = <400000>; + i2c-scl-internal-delay-ns = <10000>; + status = "okay"; + + trackpad@15 { + compatible = "elan,ekth3000"; + reg = <0x15>; + interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <&pp3300_s3>; + wakeup-source; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <100000>; + status = "okay"; + + it6505dptx: dp-bridge@5c { + compatible = "ite,it6505"; + reg = <0x5c>; + interrupts-extended = <&pio 8 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&it6505_pins>; + #sound-dai-cells = <0>; + ovdd-supply = <&mt6366_vsim2_reg>; + pwr18-supply = <&pp1800_dpbrdg_dx>; + reset-gpios = <&pio 177 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + it6505_in: endpoint { + link-frequencies = /bits/ 64 <150000000>; + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; + status = "okay"; + + rt5682s: codec@1a { + compatible = "realtek,rt5682s"; + reg = <0x1a>; + interrupts-extended = <&pio 17 IRQ_TYPE_EDGE_BOTH>; + #sound-dai-cells = <1>; + AVDD-supply = <&mt6366_vio18_reg>; + DBVDD-supply = <&mt6366_vio18_reg>; + LDO1-IN-supply = <&mt6366_vio18_reg>; + MICVDD-supply = <&pp3300_z2>; + realtek,jd-src = <1>; + }; +}; + +&mfg0 { + domain-supply = <&mt6366_vsram_gpu_reg>; +}; + +&mfg1 { + domain-supply = <&mt6366_vgpu_reg>; +}; + +&mipi_tx0 { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + supports-cqe; + no-sd; + no-sdio; + cap-mmc-hw-reset; + hs400-ds-delay = <0x11814>; + mediatek,hs400-ds-dly3 = <0x14>; + vmmc-supply = <&mt6366_vemc_reg>; + vqmmc-supply = <&mt6366_vio18_reg>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default", "state_uhs", "state_eint"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_uhs>; + pinctrl-2 = <&mmc1_pins_eint>; + /delete-property/ interrupts; + interrupt-names = "msdc", "sdio_wakeup"; + interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>, + <&pio 87 IRQ_TYPE_LEVEL_LOW>; + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr104; + sd-uhs-sdr50; + keep-power-in-suspend; + wakeup-source; + cap-sdio-irq; + no-mmc; + no-sd; + non-removable; + vmmc-supply = <&pp3300_s3>; + vqmmc-supply = <&mt6366_vio18_reg>; + mmc-pwrseq = <&wifi_pwrseq>; + status = "okay"; + + bluetooth@2 { + compatible = "mediatek,mt7921s-bluetooth"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_pins_reset>; + reset-gpios = <&pio 155 GPIO_ACTIVE_LOW>; + }; +}; + +&nor_flash { + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D7_D4>; + pinctrl-names = "default"; + pinctrl-0 = <&nor_pins_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <39000000>; + }; +}; + +&pio { + /* 185 lines */ + gpio-line-names = "TP", + "TP", + "TP", + "I2S0_HP_DI", + "I2S3_DP_SPKR_DO", + "SAR_INT_ODL", + "BT_WAKE_AP_ODL", + "WIFI_INT_ODL", + "DPBRDG_INT_ODL", + "EDPBRDG_INT_ODL", + "EC_AP_HPD_OD", + "TCHPAD_INT_ODL", + "TCHSCR_INT_1V8_ODL", + "EC_AP_INT_ODL", + "EC_IN_RW_ODL", + "GSC_AP_INT_ODL", + /* AP_FLASH_WP_L is crossystem ABI. Rev1 schematics call it AP_WP_ODL. */ + "AP_FLASH_WP_L", + "HP_INT_ODL", + "PEN_EJECT_OD", + "WCAM_PWDN_L", + "WCAM_RST_L", + "UCAM_SEN_EN", + "UCAM_RST_L", + "LTE_RESET_L", + "LTE_SAR_DETECT_L", + "I2S2_DP_SPK_MCK", + "I2S2_DP_SPKR_BCK", + "I2S2_DP_SPKR_LRCK", + "I2S2_DP_SPKR_DI (TP)", + "EN_PP1000_EDPBRDG", + "EN_PP1800_EDPBRDG", + "EN_PP3300_EDPBRDG", + "UART_GSC_TX_AP_RX", + "UART_AP_TX_GSC_RX", + "UART_DBGCON_TX_ADSP_RX", + "UART_ADSP_TX_DBGCON_RX", + "EN_PP1000_DPBRDG", + "TCHSCR_REPORT_DISABLE", + "EN_PP3300_DPBRDG", + "EN_PP1800_DPBRDG", + "SPI_AP_CLK_EC", + "SPI_AP_CS_EC_L", + "SPI_AP_DO_EC_DI", + "SPI_AP_DI_EC_DO", + "SPI_AP_CLK_GSC", + "SPI_AP_CS_GSC_L", + "SPI_AP_DO_GSC_DI", + "SPI_AP_DI_GSC_DO", + "UART_DBGCON_TX_SCP_RX", + "UART_SCP_TX_DBGCON_RX", + "EN_PP1200_CAM_X", + "EN_PP2800A_VCM_X", + "EN_PP2800A_UCAM_X", + "EN_PP2800A_WCAM_X", + "WLAN_MODULE_RST_L", + "EN_PP1200_UCAM_X", + "I2S1_HP_DO", + "I2S1_HP_BCK", + "I2S1_HP_LRCK", + "I2S1_HP_MCK", + "TCHSCR_RST_1V8_L", + "SPI_AP_CLK_ROM", + "SPI_AP_CS_ROM_L", + "SPI_AP_DO_ROM_DI", + "SPI_AP_DI_ROM_DO", + "NC", + "NC", + "EMMC_STRB", + "EMMC_CLK", + "EMMC_CMD", + "EMMC_RST_L", + "EMMC_DATA0", + "EMMC_DATA1", + "EMMC_DATA2", + "EMMC_DATA3", + "EMMC_DATA4", + "EMMC_DATA5", + "EMMC_DATA6", + "EMMC_DATA7", + "AP_KPCOL0", + "NC", + "NC", + "NC", + "TP", + "SDIO_CLK", + "SDIO_CMD", + "SDIO_DATA0", + "SDIO_DATA1", + "SDIO_DATA2", + "SDIO_DATA3", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "EDPBRDG_PWREN", + "BL_PWM_1V8", + "EDPBRDG_RST_L", + "MIPI_DPI_CLK", + "MIPI_DPI_VSYNC", + "MIPI_DPI_HSYNC", + "MIPI_DPI_DE", + "MIPI_DPI_D0", + "MIPI_DPI_D1", + "MIPI_DPI_D2", + "MIPI_DPI_D3", + "MIPI_DPI_D4", + "MIPI_DPI_D5", + "MIPI_DPI_D6", + "MIPI_DPI_DA7", + "MIPI_DPI_D8", + "MIPI_DPI_D9", + "MIPI_DPI_D10", + "MIPI_DPI_D11", + "PCM_BT_CLK", + "PCM_BT_SYNC", + "PCM_BT_DI", + "PCM_BT_DO", + "JTAG_TMS_TP", + "JTAG_TCK_TP", + "JTAG_TDI_TP", + "JTAG_TDO_TP", + "JTAG_TRSTN_TP", + "CLK_24M_WCAM", + "CLK_24M_UCAM", + "UCAM_DET_ODL", + "AP_I2C_EDPBRDG_SCL_1V8", + "AP_I2C_EDPBRDG_SDA_1V8", + "AP_I2C_TCHSCR_SCL_1V8", + "AP_I2C_TCHSCR_SDA_1V8", + "AP_I2C_TCHPAD_SCL_1V8", + "AP_I2C_TCHPAD_SDA_1V8", + "AP_I2C_DPBRDG_SCL_1V8", + "AP_I2C_DPBRDG_SDA_1V8", + "AP_I2C_WLAN_SCL_1V8", + "AP_I2C_WLAN_SDA_1V8", + "AP_I2C_AUD_SCL_1V8", + "AP_I2C_AUD_SDA_1V8", + "AP_I2C_TPM_SCL_1V8", + "AP_I2C_UCAM_SDA_1V8", + "AP_I2C_UCAM_SCL_1V8", + "AP_I2C_UCAM_SDA_1V8", + "AP_I2C_WCAM_SCL_1V8", + "AP_I2C_WCAM_SDA_1V8", + "SCP_I2C_SENSOR_SCL_1V8", + "SCP_I2C_SENSOR_SDA_1V8", + "AP_EC_WARM_RST_REQ", + "AP_XHCI_INIT_DONE", + "USB3_HUB_RST_L", + "EN_SPKR", + "BEEP_ON", + "AP_EDP_BKLTEN", + "EN_PP3300_DISP_X", + "EN_PP3300_SDBRDG_X", + "BT_KILL_1V8_L", + "WIFI_KILL_1V8_L", + "PWRAP_SPI0_CSN", + "PWRAP_SPI0_CK", + "PWRAP_SPI0_MO", + "PWRAP_SPI0_MI", + "SRCLKENA0", + "SRCLKENA1", + "SCP_VREQ_VAO", + "AP_RTC_CLK32K", + "AP_PMIC_WDTRST_L", + "AUD_CLK_MOSI", + "AUD_SYNC_MOSI", + "AUD_DAT_MOSI0", + "AUD_DAT_MOSI1", + "AUD_CLK_MISO", + "AUD_SYNC_MISO", + "AUD_DAT_MISO0", + "AUD_DAT_MISO1", + "NC", + "NC", + "DPBRDG_PWREN", + "DPBRDG_RST_L", + "LTE_W_DISABLE_L", + "LTE_SAR_DETECT_L", + "EN_PP3300_LTE_X", + "LTE_PWR_OFF_L", + "LTE_RESET_L", + "TP", + "TP"; + + aud_clk_mosi_off: aud-clk-mosi-off-pins { + pins-clk-sync { + pinmux = , + ; + input-enable; + bias-pull-down; + }; + }; + + aud_clk_mosi_on: aud-clk-mosi-on-pins { + pins-clk-sync { + pinmux = , + ; + }; + }; + + aud_clk_miso_off: aud-clk-miso-off-pins { + pins-clk-sync { + pinmux = , + ; + input-enable; + bias-pull-down; + }; + }; + + aud_clk_miso_on: aud-clk-miso-on-pins { + pins-clk-sync { + pinmux = , + ; + }; + }; + + aud_dat_mosi_off: aud-dat-mosi-off-pins { + pins-dat { + pinmux = , + ; + input-enable; + bias-pull-down; + }; + }; + + aud_dat_mosi_on: aud-dat-mosi-on-pins { + pins-dat { + pinmux = , + ; + }; + }; + + aud_dat_miso_off: aud-dat-miso-off-pins { + pins-dat { + pinmux = , + ; + input-enable; + bias-pull-down; + }; + }; + + aud_dat_miso_on: aud-dat-miso-on-pins { + pins-dat { + pinmux = , + ; + input-schmitt-enable; + bias-disable; + }; + }; + + aud_gpio_i2s0_off: aud-gpio-i2s0-off-pins { + pins-sdata { + pinmux = ; + }; + }; + + aud_gpio_i2s0_on: aud-gpio-i2s0-on-pins { + pins-sdata { + pinmux = ; + }; + }; + + aud_gpio_i2s1_off: aud-gpio-i2s-off-pins { + pins-clk-sdata { + pinmux = , + , + , + ; + output-low; + }; + }; + + aud_gpio_i2s1_on: aud-gpio-i2s1-on-pins { + pins-clk-sdata { + pinmux = , + , + , + ; + }; + }; + + aud_gpio_i2s2_off: aud-gpio-i2s2-off-pins { + pins-cmd-dat { + pinmux = , + ; + output-low; + }; + }; + + aud_gpio_i2s2_on: aud-gpio-i2s2-on-pins { + pins-clk { + pinmux = , + ; + drive-strength = <4>; + }; + }; + + aud_gpio_i2s3_off: aud-gpio-i2s3-off-pins { + pins-sdata { + pinmux = ; + output-low; + }; + }; + + aud_gpio_i2s3_on: aud-gpio-i2s3-on-pins { + pins-sdata { + pinmux = ; + drive-strength = <4>; + }; + }; + + aud_gpio_pcm_off: aud-gpio-pcm-off-pins { + pins-clk-sdata { + pinmux = , + , + , + ; + output-low; + }; + }; + + aud_gpio_pcm_on: aud-gpio-pcm-on-pins { + pins-clk-sdata { + pinmux = , + , + , + ; + }; + }; + + aud_gpio_dmic_sec: aud-gpio-dmic-sec-pins { + pins { + pinmux = ; + output-low; + }; + }; + + bt_pins_reset: bt-reset-pins { + pins-bt-reset { + pinmux = ; + output-high; + }; + }; + + dpi_pins_sleep: dpi-sleep-pins { + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + drive-strength = <10>; + output-low; + }; + }; + + dpi_pins_default: dpi-default-pins { + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + drive-strength = <10>; + }; + }; + + ec_ap_int: cros-ec-int-pins { + pins-ec-ap-int-odl { + pinmux = ; + input-enable; + }; + }; + + edp_panel_fixed_pins: edp-panel-fixed-pins { + pins-vreg-en { + pinmux = ; + output-high; + }; + }; + + en_pp1800_dpbrdg: en-pp1800-dpbrdg-pins { + pins-vreg-en { + pinmux = ; + output-low; + }; + }; + + gsc_int: gsc-int-pins { + pins-gsc-ap-int-odl { + pinmux = ; + input-enable; + }; + }; + + i2c0_pins: i2c0-pins { + pins-bus { + pinmux = , + ; + bias-disable; + drive-strength = <4>; + input-enable; + }; + }; + + i2c1_pins: i2c1-pins { + pins-bus { + pinmux = , + ; + bias-disable; + drive-strength = <4>; + input-enable; + }; + }; + + i2c2_pins: i2c2-pins { + pins-bus { + pinmux = , + ; + bias-disable; + drive-strength = <4>; + input-enable; + }; + }; + + i2c3_pins: i2c3-pins { + pins-bus { + pinmux = , + ; + bias-disable; + drive-strength = <4>; + input-enable; + }; + }; + + i2c5_pins: i2c5-pins { + pins-bus { + pinmux = , + ; + bias-disable; + drive-strength = <4>; + input-enable; + }; + }; + + it6505_pins: it6505-pins { + pins-hpd { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-int { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-reset { + pinmux = ; + output-low; + bias-pull-up; + }; + }; + + mmc0_pins_default: mmc0-default-pins { + pins-clk { + pinmux = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + bias-pull-up = ; + }; + + pins-rst { + pinmux = ; + bias-pull-up = ; + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = <6>; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = <6>; + bias-pull-up = ; + }; + + pins-ds { + pinmux = ; + drive-strength = <6>; + bias-pull-down = ; + }; + + pins-rst { + pinmux = ; + bias-pull-up = ; + }; + }; + + mmc1_pins_default: mmc1-default-pins { + pins-clk { + pinmux = ; + drive-strength = <6>; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = <6>; + bias-pull-up = ; + }; + }; + + mmc1_pins_uhs: mmc1-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = <6>; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = <8>; + bias-pull-up = ; + }; + }; + + mmc1_pins_eint: mmc1-eint-pins { + pins-dat1 { + pinmux = ; + input-enable; + bias-pull-up = ; + }; + }; + + nor_pins_default: nor-default-pins { + pins-clk-dat { + pinmux = , + , + ; + drive-strength = <6>; + bias-pull-down; + }; + + pins-cs-dat { + pinmux = , + , + ; + drive-strength = <6>; + bias-pull-up; + }; + }; + + pen_eject: pen-eject-pins { + pins { + pinmux = ; + input-enable; + /* External pull-up. */ + bias-disable; + }; + }; + + pwm0_pin: disp-pwm-pins { + pins { + pinmux = ; + output-high; + }; + }; + + rt1019p_pins_default: rt1019p-default-pins { + pins-sdb { + pinmux = ; + output-low; + }; + }; + + scp_pins: scp-default-pins { + pins-scp-uart { + pinmux = , + ; + }; + }; + + spi1_pins: spi1-pins { + pins-bus { + pinmux = , + , + , + ; + bias-disable; + input-enable; + }; + }; + + spi2_pins: spi2-pins { + pins-bus { + pinmux = , + , + , + ; + bias-disable; + input-enable; + }; + }; + + spmi_pins: spmi-pins { + pins-bus { + pinmux = , + ; + }; + }; + + touchscreen_pins: touchscreen-pins { + pins-irq { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-reset { + pinmux = ; + output-high; + }; + + pins-report-sw { + pinmux = ; + output-low; + }; + }; + + trackpad_pin: trackpad-default-pins { + pins-int-n { + pinmux = ; + input-enable; + bias-disable; /* pulled externally */ + }; + }; + + wifi_enable_pin: wifi-enable-pins { + pins-wifi-enable { + pinmux = ; + }; + }; + + wifi_wakeup_pin: wifi-wakeup-pins { + pins-wifi-wakeup { + pinmux = ; + input-enable; + }; + }; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + status = "okay"; +}; + +&pwrap { + pmic { + compatible = "mediatek,mt6366", "mediatek,mt6358"; + interrupt-controller; + interrupts-extended = <&pio 201 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + + mt6366codec: codec { + compatible = "mediatek,mt6366-sound", "mediatek,mt6358-sound"; + Avdd-supply = <&mt6366_vaud28_reg>; + mediatek,dmic-mode = <1>; /* one-wire */ + }; + + mt6366_regulators: regulators { + compatible = "mediatek,mt6366-regulator", "mediatek,mt6358-regulator"; + vsys-ldo1-supply = <&pp4200_z2>; + vsys-ldo2-supply = <&pp4200_z2>; + vsys-ldo3-supply = <&pp4200_z2>; + vsys-vcore-supply = <&pp4200_z2>; + vsys-vdram1-supply = <&pp4200_z2>; + vsys-vgpu-supply = <&pp4200_z2>; + vsys-vmodem-supply = <&pp4200_z2>; + vsys-vpa-supply = <&pp4200_z2>; + vsys-vproc11-supply = <&pp4200_z2>; + vsys-vproc12-supply = <&pp4200_z2>; + vsys-vs1-supply = <&pp4200_z2>; + vsys-vs2-supply = <&pp4200_z2>; + vs1-ldo1-supply = <&mt6366_vs1_reg>; + vs2-ldo1-supply = <&mt6366_vdram1_reg>; + vs2-ldo2-supply = <&mt6366_vs2_reg>; + vs2-ldo3-supply = <&mt6366_vs2_reg>; + + vcore { + regulator-name = "pp0750_dvdd_core"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <800000>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <200>; + regulator-allowed-modes = ; + regulator-always-on; + }; + + mt6366_vdram1_reg: vdram1 { + regulator-name = "pp1125_emi_vdd2"; + regulator-min-microvolt = <1125000>; + regulator-max-microvolt = <1125000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <0>; + regulator-allowed-modes = ; + regulator-always-on; + }; + + mt6366_vgpu_reg: vgpu { + /* + * Called "ppvar_dvdd_gpu" in the schematic. + * Called "ppvar_dvdd_vgpu" here to match + * regulator coupling requirements. + */ + regulator-name = "ppvar_dvdd_vgpu"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <200>; + regulator-allowed-modes = ; + regulator-coupled-with = <&mt6366_vsram_gpu_reg>; + regulator-coupled-max-spread = <10000>; + }; + + mt6366_vproc11_reg: vproc11 { + regulator-name = "ppvar_dvdd_proc_bc_mt6366"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <200>; + regulator-allowed-modes = ; + regulator-always-on; + }; + + mt6366_vproc12_reg: vproc12 { + regulator-name = "ppvar_dvdd_proc_lc"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <200>; + regulator-allowed-modes = ; + regulator-always-on; + }; + + mt6366_vs1_reg: vs1 { + regulator-name = "pp2000_vs1"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <0>; + regulator-always-on; + }; + + mt6366_vs2_reg: vs2 { + regulator-name = "pp1350_vs2"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <0>; + regulator-always-on; + }; + + va12 { + regulator-name = "pp1200_va12"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <270>; + regulator-always-on; + }; + + mt6366_vaud28_reg: vaud28 { + regulator-name = "pp2800_vaud28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6366_vaux18_reg: vaux18 { + regulator-name = "pp1840_vaux18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1840000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6366_vbif28_reg: vbif28 { + regulator-name = "pp2800_vbif28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6366_vcn18_reg: vcn18 { + regulator-name = "pp1800_vcn18_x"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6366_vcn28_reg: vcn28 { + regulator-name = "pp2800_vcn28_x"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6366_vefuse_reg: vefuse { + regulator-name = "pp1800_vefuse"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6366_vfe28_reg: vfe28 { + regulator-name = "pp2800_vfe28_x"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6366_vemc_reg: vemc { + regulator-name = "pp3000_vemc"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <60>; + }; + + mt6366_vibr_reg: vibr { + regulator-name = "pp2800_vibr_x"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <60>; + }; + + mt6366_vio18_reg: vio18 { + regulator-name = "pp1800_vio18_s3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <2700>; + regulator-always-on; + }; + + mt6366_vio28_reg: vio28 { + regulator-name = "pp2800_vio28_x"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6366_vm18_reg: vm18 { + regulator-name = "pp1800_emi_vdd1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1840000>; + regulator-enable-ramp-delay = <325>; + regulator-always-on; + }; + + mt6366_vmc_reg: vmc { + regulator-name = "pp3000_vmc"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <60>; + }; + + mt6366_vmddr_reg: vmddr { + regulator-name = "pm0750_emi_vmddr"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <750000>; + regulator-enable-ramp-delay = <325>; + regulator-always-on; + }; + + mt6366_vmch_reg: vmch { + regulator-name = "pp3000_vmch"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <60>; + }; + + mt6366_vcn33_reg: vcn33 { + regulator-name = "pp3300_vcn33_x"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <270>; + }; + + vdram2 { + regulator-name = "pp0600_emi_vddq"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + regulator-enable-ramp-delay = <3300>; + regulator-always-on; + }; + + mt6366_vrf12_reg: vrf12 { + regulator-name = "pp1200_vrf12_x"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <120>; + }; + + mt6366_vrf18_reg: vrf18 { + regulator-name = "pp1800_vrf18_x"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <120>; + }; + + vsim1 { + regulator-name = "pp1860_vsim1_x"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1860000>; + regulator-enable-ramp-delay = <540>; + }; + + mt6366_vsim2_reg: vsim2 { + regulator-name = "pp2760_vsim2_x"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2760000>; + regulator-enable-ramp-delay = <540>; + }; + + mt6366_vsram_gpu_reg: vsram-gpu { + regulator-name = "pp0900_dvdd_sram_gpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <240>; + regulator-coupled-with = <&mt6366_vgpu_reg>; + regulator-coupled-max-spread = <10000>; + }; + + mt6366_vsram_others_reg: vsram-others { + regulator-name = "pp0900_dvdd_sram_core"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <240>; + regulator-always-on; + }; + + mt6366_vsram_proc11_reg: vsram-proc11 { + regulator-name = "pp0900_dvdd_sram_bc"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1120000>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <240>; + regulator-always-on; + }; + + mt6366_vsram_proc12_reg: vsram-proc12 { + regulator-name = "pp0900_dvdd_sram_lc"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1120000>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <240>; + regulator-always-on; + }; + + vusb { + regulator-name = "pp3070_vusb"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3070000>; + regulator-enable-ramp-delay = <270>; + regulator-always-on; + }; + + vxo22 { + regulator-name = "pp2240_vxo22"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2240000>; + regulator-enable-ramp-delay = <120>; + /* Feeds DCXO internally */ + regulator-always-on; + }; + }; + + rtc { + compatible = "mediatek,mt6366-rtc", "mediatek,mt6358-rtc"; + }; + }; +}; + +&scp { + pinctrl-names = "default"; + pinctrl-0 = <&scp_pins>; + firmware-name = "mediatek/mt8186/scp.img"; + memory-region = <&scp_mem>; + status = "okay"; + + cros-ec-rpmsg { + compatible = "google,cros-ec-rpmsg"; + mediatek,rpmsg-name = "cros-ec-rpmsg"; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + mediatek,pad-select = <0>; + status = "okay"; + + cros_ec: ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0>; + interrupts-extended = <&pio 13 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ec_ap_int>; + spi-max-frequency = <1000000>; + + i2c_tunnel: i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + google,remote-bus = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + typec { + compatible = "google,cros-ec-typec"; + #address-cells = <1>; + #size-cells = <0>; + + usb_c0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + label = "left"; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + + usb_c1: connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + label = "right"; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + }; + }; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins>; + cs-gpios = <&pio 45 GPIO_ACTIVE_LOW>; + mediatek,pad-select = <0>; + status = "okay"; + + tpm@0 { + compatible = "google,cr50"; + reg = <0>; + interrupts-extended = <&pio 15 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&gsc_int>; + spi-max-frequency = <1000000>; + }; +}; + +&ssusb0 { + status = "okay"; +}; + +&ssusb1 { + status = "okay"; +}; + +&u3phy0 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usb_host0 { + vbus-supply = <&pp3300_s3>; + status = "okay"; +}; + +&usb_host1 { + vbus-supply = <&usb_p1_vbus>; + status = "okay"; +}; + +&watchdog { + mediatek,reset-by-toprgu; +}; + +#include +#include diff --git a/src/arm64/mediatek/mt8186.dtsi b/src/arm64/mediatek/mt8186.dtsi index 2fec6fd1c1a..4763ed5dc86 100644 --- a/src/arm64/mediatek/mt8186.dtsi +++ b/src/arm64/mediatek/mt8186.dtsi @@ -931,11 +931,17 @@ power-domain@MT8186_POWER_DOMAIN_SSUSB { reg = ; + clocks = <&topckgen CLK_TOP_USB_TOP>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>; + clock-names = "sys_ck", "ref_ck"; #power-domain-cells = <0>; }; power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 { reg = ; + clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>; + clock-names = "sys_ck", "ref_ck"; #power-domain-cells = <0>; }; @@ -1061,7 +1067,7 @@ reg = ; clocks = <&topckgen CLK_TOP_VENC>, <&vencsys CLK_VENC_CKE1_VENC>; - clock-names = "venc0", "larb"; + clock-names = "venc0", "subsys-larb"; mediatek,infracfg = <&infracfg_ao>; #power-domain-cells = <0>; }; @@ -1530,8 +1536,9 @@ clocks = <&topckgen CLK_TOP_USB_TOP>, <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, - <&infracfg_ao CLK_INFRA_AO_ICUSB>; - clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + <&infracfg_ao CLK_INFRA_AO_ICUSB>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; interrupts = ; phys = <&u2port0 PHY_TYPE_USB2>; power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>; @@ -1595,8 +1602,9 @@ clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, - <&clk26m>; - clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; interrupts = ; phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>; @@ -1672,6 +1680,10 @@ reg = <0x59c 0x4>; bits = <0 3>; }; + + socinfo-data1@7a0 { + reg = <0x7a0 0x4>; + }; }; mipi_tx0: dsi-phy@11cc0000 { @@ -1959,6 +1971,43 @@ power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>; }; + video_decoder: video-decoder@16000000 { + compatible = "mediatek,mt8186-vcodec-dec"; + reg = <0 0x16000000 0 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + iommus = <&iommu_mm IOMMU_PORT_L4_HW_VDEC_MC_EXT>; + mediatek,scp = <&scp>; + + vcodec_core: video-codec@16025000 { + compatible = "mediatek,mtk-vcodec-core"; + reg = <0 0x16025000 0 0x1000>; + interrupts = ; + iommus = <&iommu_mm IOMMU_PORT_L4_HW_VDEC_MC_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_UFO_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PP_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PRED_RD_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PRED_WR_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PPWRAP_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_TILE_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_VLD_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_VLD2_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_AVC_MV_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_UFO_ENC_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT>; + clocks = <&topckgen CLK_TOP_VDEC>, + <&vdecsys CLK_VDEC_CKEN>, + <&vdecsys CLK_VDEC_LARB1_CKEN>, + <&topckgen CLK_TOP_UNIVPLL_D3>; + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec", "vdec-top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>; + power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>; + }; + }; + larb4: smi@1602e000 { compatible = "mediatek,mt8186-smi-larb"; reg = <0 0x1602e000 0 0x1000>; @@ -1993,6 +2042,40 @@ power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; }; + venc: video-encoder@17020000 { + compatible = "mediatek,mt8186-vcodec-enc", "mediatek,mt8183-vcodec-enc"; + reg = <0 0x17020000 0 0x2000>; + interrupts = ; + iommus = <&iommu_mm IOMMU_PORT_L7_VENC_RCPU>, + <&iommu_mm IOMMU_PORT_L7_VENC_REC>, + <&iommu_mm IOMMU_PORT_L7_VENC_BSDMA>, + <&iommu_mm IOMMU_PORT_L7_VENC_SV_COMV>, + <&iommu_mm IOMMU_PORT_L7_VENC_RD_COMV>, + <&iommu_mm IOMMU_PORT_L7_VENC_CUR_LUMA>, + <&iommu_mm IOMMU_PORT_L7_VENC_CUR_CHROMA>, + <&iommu_mm IOMMU_PORT_L7_VENC_REF_LUMA>, + <&iommu_mm IOMMU_PORT_L7_VENC_REF_CHROMA>; + clocks = <&vencsys CLK_VENC_CKE1_VENC>; + clock-names = "venc_sel"; + assigned-clocks = <&topckgen CLK_TOP_VENC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>; + power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; + mediatek,scp = <&scp>; + }; + + jpgenc: jpeg-encoder@17030000 { + compatible = "mediatek,mt8186-jpgenc", "mediatek,mtk-jpgenc"; + reg = <0 0x17030000 0 0x10000>; + interrupts = ; + clocks = <&vencsys CLK_VENC_CKE2_JPGENC>; + clock-names = "jpgenc"; + iommus = <&iommu_mm IOMMU_PORT_L7_JPGENC_Y_RDMA>, + <&iommu_mm IOMMU_PORT_L7_JPGENC_C_RDMA>, + <&iommu_mm IOMMU_PORT_L7_JPGENC_Q_TABLE>, + <&iommu_mm IOMMU_PORT_L7_JPGENC_BSDMA>; + power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; + }; + camsys: clock-controller@1a000000 { compatible = "mediatek,mt8186-camsys"; reg = <0 0x1a000000 0 0x1000>; diff --git a/src/arm64/mediatek/mt8192-asurada.dtsi b/src/arm64/mediatek/mt8192-asurada.dtsi index d87aab8d7a7..7a704246678 100644 --- a/src/arm64/mediatek/mt8192-asurada.dtsi +++ b/src/arm64/mediatek/mt8192-asurada.dtsi @@ -1332,14 +1332,11 @@ spi-max-frequency = <3000000>; pinctrl-names = "default"; pinctrl-0 = <&cros_ec_int>; + wakeup-source; #address-cells = <1>; #size-cells = <0>; - base_detection: cbas { - compatible = "google,cros-cbas"; - }; - cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; @@ -1424,7 +1421,7 @@ mt6315_6_vbuck1: vbuck1 { regulator-compatible = "vbuck1"; regulator-name = "Vbcpu"; - regulator-min-microvolt = <300000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1193750>; regulator-enable-ramp-delay = <256>; regulator-allowed-modes = <0 1 2>; @@ -1434,7 +1431,7 @@ mt6315_6_vbuck3: vbuck3 { regulator-compatible = "vbuck3"; regulator-name = "Vlcpu"; - regulator-min-microvolt = <300000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1193750>; regulator-enable-ramp-delay = <256>; regulator-allowed-modes = <0 1 2>; @@ -1451,7 +1448,7 @@ mt6315_7_vbuck1: vbuck1 { regulator-compatible = "vbuck1"; regulator-name = "Vgpu"; - regulator-min-microvolt = <606250>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <800000>; regulator-enable-ramp-delay = <256>; regulator-allowed-modes = <0 1 2>; diff --git a/src/arm64/mediatek/mt8192.dtsi b/src/arm64/mediatek/mt8192.dtsi index 6dd32dbfb83..84cbdf6e9eb 100644 --- a/src/arm64/mediatek/mt8192.dtsi +++ b/src/arm64/mediatek/mt8192.dtsi @@ -1164,6 +1164,14 @@ #address-cells = <1>; #size-cells = <1>; + socinfo-data1@44 { + reg = <0x044 0x4>; + }; + + socinfo-data2@50 { + reg = <0x050 0x4>; + }; + lvts_e_data1: data1@1c0 { reg = <0x1c0 0x58>; }; @@ -1456,6 +1464,7 @@ reg = <0 0x14001000 0 0x1000>; interrupts = ; clocks = <&mmsys CLK_MM_DISP_MUTEX0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; mediatek,gce-events = , ; power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; @@ -1814,7 +1823,7 @@ mediatek,scp = <&scp>; power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; clocks = <&vencsys CLK_VENC_SET1_VENC>; - clock-names = "venc-set1"; + clock-names = "venc_sel"; assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; }; diff --git a/src/arm64/mediatek/mt8195-cherry-tomato-r1.dts b/src/arm64/mediatek/mt8195-cherry-tomato-r1.dts index 2d5e8f371b6..a82d716f10d 100644 --- a/src/arm64/mediatek/mt8195-cherry-tomato-r1.dts +++ b/src/arm64/mediatek/mt8195-cherry-tomato-r1.dts @@ -23,3 +23,7 @@ &ts_10 { status = "okay"; }; + +&watchdog { + /delete-property/ mediatek,disable-extrst; +}; diff --git a/src/arm64/mediatek/mt8195-cherry-tomato-r2.dts b/src/arm64/mediatek/mt8195-cherry-tomato-r2.dts index 2586c32ce6e..2fe20e0dad8 100644 --- a/src/arm64/mediatek/mt8195-cherry-tomato-r2.dts +++ b/src/arm64/mediatek/mt8195-cherry-tomato-r2.dts @@ -43,3 +43,7 @@ &ts_10 { status = "okay"; }; + +&watchdog { + /delete-property/ mediatek,disable-extrst; +}; diff --git a/src/arm64/mediatek/mt8195-cherry-tomato-r3.dts b/src/arm64/mediatek/mt8195-cherry-tomato-r3.dts index f54f9477b99..dd294ca9819 100644 --- a/src/arm64/mediatek/mt8195-cherry-tomato-r3.dts +++ b/src/arm64/mediatek/mt8195-cherry-tomato-r3.dts @@ -44,3 +44,7 @@ &ts_10 { status = "okay"; }; + +&watchdog { + /delete-property/ mediatek,disable-extrst; +}; diff --git a/src/arm64/mediatek/mt8195-cherry.dtsi b/src/arm64/mediatek/mt8195-cherry.dtsi index 3c6079edda1..4a11918da37 100644 --- a/src/arm64/mediatek/mt8195-cherry.dtsi +++ b/src/arm64/mediatek/mt8195-cherry.dtsi @@ -264,6 +264,38 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu1 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu2 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu3 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu4 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&cpu5 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&cpu6 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&cpu7 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + &dp_intf0 { status = "okay"; @@ -1149,6 +1181,7 @@ pinctrl-names = "default"; pinctrl-0 = <&cros_ec_int>; spi-max-frequency = <3000000>; + wakeup-source; keyboard-backlight { compatible = "google,cros-kbd-led-backlight"; @@ -1213,7 +1246,7 @@ mt6315_6_vbuck1: vbuck1 { regulator-compatible = "vbuck1"; regulator-name = "Vbcpu"; - regulator-min-microvolt = <300000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1193750>; regulator-enable-ramp-delay = <256>; regulator-ramp-delay = <6250>; @@ -1231,7 +1264,7 @@ mt6315_7_vbuck1: vbuck1 { regulator-compatible = "vbuck1"; regulator-name = "Vgpu"; - regulator-min-microvolt = <625000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1193750>; regulator-enable-ramp-delay = <256>; regulator-ramp-delay = <6250>; @@ -1291,11 +1324,32 @@ status = "okay"; }; +/* + * For the USB Type-C ports the role and alternate modes switching is + * done by the EC so we set dr_mode to host to avoid interfering. + */ +&ssusb0 { + dr_mode = "host"; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&ssusb2 { + dr_mode = "host"; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&ssusb3 { + dr_mode = "host"; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + &xhci0 { status = "okay"; rx-fifo-depth = <3072>; - vusb33-supply = <&mt6359_vusb_ldo_reg>; vbus-supply = <&usb_vbus>; }; @@ -1309,8 +1363,6 @@ &xhci2 { status = "okay"; - - vusb33-supply = <&mt6359_vusb_ldo_reg>; vbus-supply = <&usb_vbus>; }; @@ -1319,7 +1371,6 @@ /* MT7921's USB Bluetooth has issues with USB2 LPM */ usb2-lpm-disable; - vusb33-supply = <&mt6359_vusb_ldo_reg>; vbus-supply = <&usb_vbus>; }; diff --git a/src/arm64/mediatek/mt8195-demo.dts b/src/arm64/mediatek/mt8195-demo.dts index 4127cb84eba..b82f7176b4a 100644 --- a/src/arm64/mediatek/mt8195-demo.dts +++ b/src/arm64/mediatek/mt8195-demo.dts @@ -529,8 +529,22 @@ status = "okay"; }; -&xhci0 { +&ssusb0 { vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&ssusb2 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&ssusb3 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&xhci0 { vbus-supply = <&otg_vbus_regulator>; status = "okay"; }; @@ -541,11 +555,9 @@ }; &xhci2 { - vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; }; &xhci3 { - vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; }; diff --git a/src/arm64/mediatek/mt8195-evb.dts b/src/arm64/mediatek/mt8195-evb.dts index 690dc7717f2..341b6e07413 100644 --- a/src/arm64/mediatek/mt8195-evb.dts +++ b/src/arm64/mediatek/mt8195-evb.dts @@ -160,6 +160,18 @@ status = "okay"; }; +&ssusb0 { + status = "okay"; +}; + +&ssusb2 { + status = "okay"; +}; + +&ssusb3 { + status = "okay"; +}; + &xhci0 { status = "okay"; }; diff --git a/src/arm64/mediatek/mt8195.dtsi b/src/arm64/mediatek/mt8195.dtsi index b9101662ce4..5d8b68f86ce 100644 --- a/src/arm64/mediatek/mt8195.dtsi +++ b/src/arm64/mediatek/mt8195.dtsi @@ -1347,29 +1347,40 @@ }; }; - xhci0: usb@11200000 { - compatible = "mediatek,mt8195-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x11200000 0 0x1000>, - <0 0x11203e00 0 0x0100>; + ssusb0: usb@11201000 { + compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3"; + reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; reg-names = "mac", "ippc"; - interrupts = ; - phys = <&u2port0 PHY_TYPE_USB2>, - <&u3port0 PHY_TYPE_USB3>; - assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, - <&topckgen CLK_TOP_SSUSB_XHCI>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, - <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + ranges = <0 0 0 0x11200000 0 0x3f00>; + #address-cells = <2>; + #size-cells = <2>; + interrupts = ; clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, <&topckgen CLK_TOP_SSUSB_REF>, - <&apmixedsys CLK_APMIXED_USB1PLL>, - <&clk26m>, <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; - clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", - "xhci_ck"; - mediatek,syscon-wakeup = <&pericfg 0x400 103>; + clock-names = "sys_ck", "ref_ck", "mcu_ck"; + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; wakeup-source; + mediatek,syscon-wakeup = <&pericfg 0x400 103>; status = "disabled"; + + xhci0: usb@0 { + compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci"; + reg = <0 0 0 0x1000>; + reg-names = "mac"; + interrupts = ; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, + <&topckgen CLK_TOP_SSUSB_XHCI>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, + <&topckgen CLK_TOP_SSUSB_REF>, + <&apmixedsys CLK_APMIXED_USB1PLL>, + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; + status = "disabled"; + }; }; mmc0: mmc@11230000 { @@ -1450,52 +1461,68 @@ status = "disabled"; }; - xhci2: usb@112a0000 { - compatible = "mediatek,mt8195-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x112a0000 0 0x1000>, - <0 0x112a3e00 0 0x0100>; + ssusb2: usb@112a1000 { + compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3"; + reg = <0 0x112a1000 0 0x2dff>, <0 0x112a3e00 0 0x0100>; reg-names = "mac", "ippc"; - interrupts = ; - phys = <&u2port2 PHY_TYPE_USB2>; - assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>, - <&topckgen CLK_TOP_SSUSB_XHCI_2P>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, - <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + ranges = <0 0 0 0x112a0000 0 0x3f00>; + #address-cells = <2>; + #size-cells = <2>; + interrupts = ; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, <&topckgen CLK_TOP_SSUSB_P2_REF>, - <&clk26m>, - <&clk26m>, <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; - clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", - "xhci_ck"; - mediatek,syscon-wakeup = <&pericfg 0x400 105>; + clock-names = "sys_ck", "ref_ck", "mcu_ck"; + phys = <&u2port2 PHY_TYPE_USB2>; wakeup-source; + mediatek,syscon-wakeup = <&pericfg 0x400 105>; status = "disabled"; + + xhci2: usb@0 { + compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci"; + reg = <0 0 0 0x1000>; + reg-names = "mac"; + interrupts = ; + assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; + clock-names = "sys_ck"; + status = "disabled"; + }; }; - xhci3: usb@112b0000 { - compatible = "mediatek,mt8195-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x112b0000 0 0x1000>, - <0 0x112b3e00 0 0x0100>; + ssusb3: usb@112b1000 { + compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3"; + reg = <0 0x112b1000 0 0x2dff>, <0 0x112b3e00 0 0x0100>; reg-names = "mac", "ippc"; - interrupts = ; - phys = <&u2port3 PHY_TYPE_USB2>; - assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>, - <&topckgen CLK_TOP_SSUSB_XHCI_3P>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, - <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + ranges = <0 0 0 0x112b0000 0 0x3f00>; + #address-cells = <2>; + #size-cells = <2>; + interrupts = ; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, <&topckgen CLK_TOP_SSUSB_P3_REF>, - <&clk26m>, - <&clk26m>, <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; - clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", - "xhci_ck"; - mediatek,syscon-wakeup = <&pericfg 0x400 106>; + clock-names = "sys_ck", "ref_ck", "mcu_ck"; + phys = <&u2port3 PHY_TYPE_USB2>; wakeup-source; + mediatek,syscon-wakeup = <&pericfg 0x400 106>; status = "disabled"; + + xhci3: usb@0 { + compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci"; + reg = <0 0 0 0x1000>; + reg-names = "mac"; + interrupts = ; + assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; + clock-names = "sys_ck"; + status = "disabled"; + }; }; pcie0: pcie@112f0000 { @@ -1701,6 +1728,9 @@ svs_calib_data: svs-calib@580 { reg = <0x580 0x64>; }; + socinfo-data1@7a0 { + reg = <0x7a0 0x4>; + }; }; u3phy2: t-phy@11c40000 { @@ -1998,6 +2028,7 @@ compatible = "mediatek,mt8195-vppsys0", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>; }; dma-controller@14001000 { @@ -2221,6 +2252,7 @@ compatible = "mediatek,mt8195-vppsys1", "syscon"; reg = <0 0x14f00000 0 0x1000>; #clock-cells = <1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>; }; mutex@14f01000 { @@ -3050,6 +3082,7 @@ reg = <0 0x1c01a000 0 0x1000>; mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; #clock-cells = <1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>; }; @@ -3231,6 +3264,7 @@ interrupts = ; power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>; mediatek,gce-events = ; }; @@ -3301,6 +3335,7 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>; clock-names = "vdo1_mutex"; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>; mediatek,gce-events = ; }; diff --git a/src/arm64/mediatek/mt8395-genio-1200-evk.dts b/src/arm64/mediatek/mt8395-genio-1200-evk.dts index 7fc515a07c6..1558649f633 100644 --- a/src/arm64/mediatek/mt8395-genio-1200-evk.dts +++ b/src/arm64/mediatek/mt8395-genio-1200-evk.dts @@ -880,6 +880,21 @@ status = "disabled"; }; +&ssusb0 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&ssusb2 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&ssusb3 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + &xhci0 { status = "okay"; }; @@ -890,11 +905,9 @@ }; &xhci2 { - vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; }; &xhci3 { - vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; }; diff --git a/src/arm64/mediatek/mt8395-radxa-nio-12l.dts b/src/arm64/mediatek/mt8395-radxa-nio-12l.dts new file mode 100644 index 00000000000..e5d9b671a40 --- /dev/null +++ b/src/arm64/mediatek/mt8395-radxa-nio-12l.dts @@ -0,0 +1,825 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Radxa Limited + * Copyright (C) 2024 Collabora Ltd. + * AngeloGioacchino Del Regno + */ + +#include "mt8195.dtsi" +#include "mt6359.dtsi" +#include +#include +#include +#include +#include +#include + +/ { + model = "Radxa NIO 12L"; + chassis-type = "embedded"; + compatible = "radxa,nio-12l", "mediatek,mt8395", "mediatek,mt8195"; + + aliases { + i2c0 = &i2c2; + i2c1 = &i2c3; + i2c2 = &i2c4; + i2c3 = &i2c0; + i2c4 = &i2c1; + ethernet0 = ð + serial0 = &uart0; + serial1 = &uart1; + spi0 = &spi1; + spi1 = &spi2; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0x1 0x0>; + }; + + wifi_vreg: regulator-wifi-3v3-en { + compatible = "regulator-fixed"; + regulator-name = "wifi_3v3_en"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pio 67 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_vreg_pins>; + vin-supply = <&vsys>; + }; + + /* system wide switching 5.0V power rail */ + vsys: regulator-vsys { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_vsys>; + }; + + vsys_buck: regulator-vsys-buck { + compatible = "regulator-fixed"; + regulator-name = "vsys_buck"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_vsys>; + }; + + /* Rail from power-only "TYPE C DC" port */ + vcc5v0_vsys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + reg = <0 0x43200000 0 0xc00000>; + no-map; + }; + + scp_mem: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + + vpu_mem: memory@53000000 { + compatible = "shared-dma-pool"; + reg = <0 0x53000000 0 0x1400000>; /* 20 MB */ + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_mem: memory@54600000 { + reg = <0 0x54600000 0x0 0x200000>; + no-map; + }; + + afe_mem: memory@60000000 { + compatible = "shared-dma-pool"; + reg = <0 0x60000000 0 0x1100000>; + no-map; + }; + + apu_mem: memory@62000000 { + compatible = "shared-dma-pool"; + reg = <0 0x62000000 0 0x1400000>; /* 20 MB */ + }; + }; +}; + +ð { + phy-mode = "rgmii-rxid"; + phy-handle = <&rgmii_phy>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð_default_pins>; + pinctrl-1 = <ð_sleep_pins>; + mediatek,tx-delay-ps = <2030>; + mediatek,mac-wol; + snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>; + snps,reset-delays-us = <0 20000 100000>; + status = "okay"; + + mdio { + rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + }; + }; +}; + +&gpu { + mali-supply = <&mt6315_7_vbuck1>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + status = "okay"; + + typec-mux@48 { + compatible = "ite,it5205"; + reg = <0x48>; + + mode-switch; + orientation-switch; + + vcc-supply = <&mt6359_vibr_ldo_reg>; + + port { + it5205_sbu_mux: endpoint { + remote-endpoint = <&typec_con_mux>; + }; + }; + }; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* I2C4 exposed at 39-pins MIPI-LCD connector */ +}; + +&i2c6 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c6_pins>; + pinctrl-names = "default"; + status = "okay"; + + mt6360: pmic@34 { + compatible = "mediatek,mt6360"; + reg = <0x34>; + interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "IRQB"; + interrupt-controller; + #interrupt-cells = <1>; + pinctrl-0 = <&mt6360_pins>; + + charger { + compatible = "mediatek,mt6360-chg"; + richtek,vinovp-microvolt = <14500000>; + + otg_vbus_regulator: usb-otg-vbus-regulator { + regulator-name = "usb-otg-vbus"; + regulator-min-microvolt = <4425000>; + regulator-max-microvolt = <5825000>; + }; + }; + + regulator { + compatible = "mediatek,mt6360-regulator"; + LDO_VIN1-supply = <&vsys_buck>; + LDO_VIN3-supply = <&mt6360_buck2>; + + mt6360_buck1: buck1 { + regulator-name = "emi_vdd2"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1300000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + + mt6360_buck2: buck2 { + regulator-name = "emi_vddq"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1300000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + + mt6360_ldo1: ldo1 { + regulator-name = "ext_lcd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + + mt6360_ldo2: ldo2 { + regulator-name = "panel1_p1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo3: ldo3 { + regulator-name = "vmc_pmu"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo5: ldo5 { + regulator-name = "vmch_pmu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + + mt6360_ldo6: ldo6 { + regulator-name = "mt6360_ldo6"; /* Test point */ + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2100000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo7: ldo7 { + regulator-name = "emi_vmddr_en"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2100000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + }; + + typec { + compatible = "mediatek,mt6360-tcpc"; + interrupts-extended = <&pio 100 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "PD_IRQB"; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + op-sink-microwatt = <10000000>; + power-role = "dual"; + try-power-role = "sink"; + + source-pdos = ; + sink-pdos = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + typec_con_hs: endpoint { + remote-endpoint = <&mtu3_hs0_role_sw>; + }; + }; + + port@2 { + reg = <2>; + typec_con_mux: endpoint { + remote-endpoint = <&it5205_sbu_mux>; + }; + }; + }; + }; + }; + }; +}; + +/* MMC0 Controller: eMMC (HS400). Power lines are shared with UFS! */ +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + bus-width = <8>; + max-frequency = <200000000>; + hs400-ds-delay = <0x14c11>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + no-sdio; + no-sd; + non-removable; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; + status = "okay"; +}; + +/* MMC1 Controller: MicroSD card slot */ +&mmc1 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_default_pins>, <&mmc1_pins_detect>; + pinctrl-1 = <&mmc1_default_pins>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&mt6360_ldo5>; + vqmmc-supply = <&mt6360_ldo3>; + status = "okay"; +}; + +&mt6359_vaud18_ldo_reg { + regulator-always-on; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +/* For USB Hub */ +&mt6359_vcamio_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcn33_2_bt_ldo_reg { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +&mt6359_vcore_buck_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-always-on; +}; + +&mt6359_vproc1_buck_reg { + regulator-always-on; +}; + +&mt6359_vproc2_buck_reg { + regulator-always-on; +}; + +&mt6359_vpu_buck_reg { + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-always-on; +}; + +&mt6359_vsram_md_ldo_reg { + regulator-always-on; +}; + +/* for GPU SRAM */ +&mt6359_vsram_others_ldo_reg { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; +}; + +&pio { + eth_default_pins: eth-default-pins { + pins-cc { + pinmux = , + , + , + ; + drive-strength = <8>; + }; + + pins-mdio { + pinmux = , + ; + input-enable; + }; + + pins-power { + pinmux = , + ; + output-high; + }; + + pins-rst { + pinmux = ; + }; + + pins-rxd { + pinmux = , + , + , + ; + }; + + pins-txd { + pinmux = , + , + , + ; + drive-strength = <8>; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-cc { + pinmux = , + , + , + ; + }; + + pins-mdio { + pinmux = , + ; + bias-disable; + input-disable; + }; + + pins-rxd { + pinmux = , + , + , + ; + }; + + pins-txd { + pinmux = , + , + , + ; + }; + }; + + i2c2_pins: i2c2-pins { + pins-bus { + pinmux = , + ; + bias-pull-up = ; + drive-strength = <6>; + drive-strength-microamp = <1000>; + }; + }; + + i2c4_pins: i2c4-pins { + pins-bus { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c6_pins: i2c6-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-clk { + pinmux = ; + bias-pull-down = ; + drive-strength = <6>; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + bias-pull-up = ; + drive-strength = <6>; + input-enable; + }; + + pins-rst { + pinmux = ; + bias-pull-up = ; + drive-strength = <6>; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-clk { + pinmux = ; + bias-pull-down = ; + drive-strength = <8>; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + bias-pull-up = ; + drive-strength = <8>; + input-enable; + }; + + pins-ds { + pinmux = ; + bias-pull-down = ; + drive-strength = <8>; + }; + + pins-rst { + pinmux = ; + bias-pull-up = ; + drive-strength = <8>; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-clk { + pinmux = ; + bias-pull-down = ; + drive-strength = <8>; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + bias-pull-up = ; + drive-strength = <8>; + input-enable; + }; + }; + + mmc1_pins_detect: mmc1-detect-pins { + pins-insert { + pinmux = ; + bias-pull-up; + }; + }; + + mt6360_pins: mt6360-pins { + pins-irq { + pinmux = , + ; + input-enable; + bias-pull-up; + }; + }; + + pcie0_default_pins: pcie0-default-pins { + pins-bus { + pinmux = , + , + ; + bias-pull-up; + }; + }; + + pcie1_default_pins: pcie1-default-pins { + pins-bus { + pinmux = , + , + ; + bias-disable; + }; + }; + + spi1_pins: spi1-default-pins { + pins-bus { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + spi2_pins: spi2-default-pins { + pins-bus { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + uart0_pins: uart0-pins { + pins-bus { + pinmux = , + ; + }; + }; + + uart1_pins: uart1-pins { + pins-bus { + pinmux = , + ; + }; + }; + + wifi_vreg_pins: wifi-vreg-pins { + pins-wifi-pmu-en { + pinmux = ; + output-high; + }; + + pins-wifi-vreg-en { + pinmux = ; + }; + }; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_pins>; + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_pins>; + status = "okay"; +}; + +&pmic { + interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; +}; + +&scp { + memory-region = <&scp_mem>; + status = "okay"; +}; + +&spi1 { + /* Exposed at 40 pin connector */ + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + mediatek,pad-select = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + +&spi2 { + /* Exposed at 40 pin connector */ + pinctrl-0 = <&spi2_pins>; + pinctrl-names = "default"; + mediatek,pad-select = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + +&spmi { + #address-cells = <2>; + #size-cells = <0>; + + mt6315_6: pmic@6 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x6 SPMI_USID>; + + regulators { + mt6315_6_vbuck1: vbuck1 { + regulator-compatible = "vbuck1"; + regulator-name = "Vbcpu"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + }; + }; + + mt6315_7: pmic@7 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x7 SPMI_USID>; + + regulators { + mt6315_7_vbuck1: vbuck1 { + regulator-compatible = "vbuck1"; + regulator-name = "Vgpu"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + }; + }; + }; +}; + +&uart0 { + /* Exposed at 40 pin connector */ + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + /* Exposed at 40 pin connector */ + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&ssusb0 { + role-switch-default-mode = "host"; + usb-role-switch; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; + + port { + mtu3_hs0_role_sw: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&ssusb2 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&xhci0 { + vbus-supply = <&otg_vbus_regulator>; + status = "okay"; +}; + +&xhci1 { + /* MT7921's USB Bluetooth has issues with USB2 LPM */ + usb2-lpm-disable; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&vsys>; + status = "okay"; +}; + +&xhci2 { + vbus-supply = <&vsys>; + status = "okay"; +}; diff --git a/src/arm64/nvidia/tegra132-norrin.dts b/src/arm64/nvidia/tegra132-norrin.dts index bbc2e9bef08..14d58859bb5 100644 --- a/src/arm64/nvidia/tegra132-norrin.dts +++ b/src/arm64/nvidia/tegra132-norrin.dts @@ -762,6 +762,7 @@ interrupt-parent = <&gpio>; interrupts = ; reg = <0>; + wakeup-source; google,cros-ec-spi-msg-delay = <2000>; diff --git a/src/arm64/nvidia/tegra194-p2888.dtsi b/src/arm64/nvidia/tegra194-p2888.dtsi index 5b59c1986e9..e8b296d9e0d 100644 --- a/src/arm64/nvidia/tegra194-p2888.dtsi +++ b/src/arm64/nvidia/tegra194-p2888.dtsi @@ -53,6 +53,56 @@ status = "okay"; }; + i2c@c240000 { + status = "okay"; + + power-sensor@40 { + compatible = "ti,ina3221"; + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + + input@0 { + reg = <0x0>; + label = "GPU"; + shunt-resistor-micro-ohms = <5000>; + }; + input@1 { + reg = <0x1>; + label = "CPU"; + shunt-resistor-micro-ohms = <5000>; + }; + input@2 { + reg = <0x2>; + label = "SOC"; + shunt-resistor-micro-ohms = <5000>; + }; + }; + + power-sensor@41 { + compatible = "ti,ina3221"; + reg = <0x41>; + #address-cells = <1>; + #size-cells = <0>; + + input@0 { + reg = <0x0>; + label = "CV"; + shunt-resistor-micro-ohms = <5000>; + }; + input@1 { + reg = <0x1>; + label = "VDDRQ"; + shunt-resistor-micro-ohms = <5000>; + }; + input@2 { + reg = <0x2>; + label = "SYS5V"; + shunt-resistor-micro-ohms = <5000>; + }; + }; + }; + serial@3110000 { status = "okay"; }; diff --git a/src/arm64/nvidia/tegra194-p2972-0000.dts b/src/arm64/nvidia/tegra194-p2972-0000.dts index 64a3398fe7a..c32876699a4 100644 --- a/src/arm64/nvidia/tegra194-p2972-0000.dts +++ b/src/arm64/nvidia/tegra194-p2972-0000.dts @@ -2062,8 +2062,15 @@ ports { usb2-0 { - mode = "host"; + mode = "otg"; + usb-role-switch; status = "okay"; + + port { + hs_typec_p0: endpoint { + remote-endpoint = <&hs_ucsi_ccg_p0>; + }; + }; }; usb2-1 { @@ -2094,6 +2101,14 @@ }; }; + usb@3550000 { + status = "okay"; + + phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>; + phy-names = "usb2-0", "usb3-0"; + }; + usb@3610000 { status = "okay"; @@ -2106,6 +2121,40 @@ phy-names = "usb2-0", "usb2-1", "usb2-3", "usb3-0", "usb3-2", "usb3-3"; }; + i2c@c240000 { + typec@8 { + compatible = "cypress,cypd4226"; + reg = <0x08>; + interrupt-parent = <&gpio_aon>; + interrupts = ; + firmware-name = "nvidia,jetson-agx-xavier"; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + ccg_typec_con0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + label = "USB-C"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hs_ucsi_ccg_p0: endpoint { + remote-endpoint = <&hs_typec_p0>; + }; + }; + }; + }; + }; + }; + i2c@c250000 { status = "okay"; diff --git a/src/arm64/nvidia/tegra194-p3668.dtsi b/src/arm64/nvidia/tegra194-p3668.dtsi index 58f190b0f86..59860d19f0f 100644 --- a/src/arm64/nvidia/tegra194-p3668.dtsi +++ b/src/arm64/nvidia/tegra194-p3668.dtsi @@ -50,6 +50,33 @@ status = "okay"; }; + i2c@c250000 { + status = "okay"; + + power-sensor@40 { + compatible = "ti,ina3221"; + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + + input@0 { + reg = <0x0>; + label = "VDD_IN"; + shunt-resistor-micro-ohms = <5000>; + }; + input@1 { + reg = <0x1>; + label = "VDD_CPU_GPU_CV"; + shunt-resistor-micro-ohms = <5000>; + }; + input@2 { + reg = <0x2>; + label = "VDD_SOC"; + shunt-resistor-micro-ohms = <5000>; + }; + }; + }; + serial@3100000 { status = "okay"; }; diff --git a/src/arm64/nvidia/tegra234-p3701.dtsi b/src/arm64/nvidia/tegra234-p3701.dtsi index db6ef711674..320c8e9b06b 100644 --- a/src/arm64/nvidia/tegra234-p3701.dtsi +++ b/src/arm64/nvidia/tegra234-p3701.dtsi @@ -3,6 +3,11 @@ / { compatible = "nvidia,p3701", "nvidia,tegra234"; + aliases { + mmc0 = "/bus@0/mmc@3460000"; + mmc1 = "/bus@0/mmc@3400000"; + }; + bus@0 { aconnect@2900000 { status = "okay"; @@ -12,1970 +17,22 @@ i2s@2901000 { status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s1_cif: endpoint { - remote-endpoint = <&xbar_i2s1>; - }; - }; - - i2s1_port: port@1 { - reg = <1>; - - i2s1_dap: endpoint { - dai-format = "i2s"; - /* placeholder for external codec */ - }; - }; - }; }; i2s@2901100 { status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s2_cif: endpoint { - remote-endpoint = <&xbar_i2s2>; - }; - }; - - i2s2_port: port@1 { - reg = <1>; - - i2s2_dap: endpoint { - dai-format = "i2s"; - /* placeholder for external codec */ - }; - }; - }; }; i2s@2901300 { status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s4_cif: endpoint { - remote-endpoint = <&xbar_i2s4>; - }; - }; - - i2s4_port: port@1 { - reg = <1>; - - i2s4_dap: endpoint { - dai-format = "i2s"; - /* placeholder for external codec */ - }; - }; - }; }; i2s@2901500 { status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s6_cif: endpoint { - remote-endpoint = <&xbar_i2s6>; - }; - }; - - i2s6_port: port@1 { - reg = <1>; - - i2s6_dap: endpoint { - dai-format = "i2s"; - /* placeholder for external codec */ - }; - }; - }; - }; - - sfc@2902000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc1_cif_in: endpoint { - remote-endpoint = <&xbar_sfc1_in>; - }; - }; - - sfc1_out_port: port@1 { - reg = <1>; - - sfc1_cif_out: endpoint { - remote-endpoint = <&xbar_sfc1_out>; - }; - }; - }; - }; - - sfc@2902200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc2_cif_in: endpoint { - remote-endpoint = <&xbar_sfc2_in>; - }; - }; - - sfc2_out_port: port@1 { - reg = <1>; - - sfc2_cif_out: endpoint { - remote-endpoint = <&xbar_sfc2_out>; - }; - }; - }; - }; - - sfc@2902400 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc3_cif_in: endpoint { - remote-endpoint = <&xbar_sfc3_in>; - }; - }; - - sfc3_out_port: port@1 { - reg = <1>; - - sfc3_cif_out: endpoint { - remote-endpoint = <&xbar_sfc3_out>; - }; - }; - }; - }; - - sfc@2902600 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc4_cif_in: endpoint { - remote-endpoint = <&xbar_sfc4_in>; - }; - }; - - sfc4_out_port: port@1 { - reg = <1>; - - sfc4_cif_out: endpoint { - remote-endpoint = <&xbar_sfc4_out>; - }; - }; - }; - }; - - amx@2903000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx1_in1: endpoint { - remote-endpoint = <&xbar_amx1_in1>; - }; - }; - - port@1 { - reg = <1>; - - amx1_in2: endpoint { - remote-endpoint = <&xbar_amx1_in2>; - }; - }; - - port@2 { - reg = <2>; - - amx1_in3: endpoint { - remote-endpoint = <&xbar_amx1_in3>; - }; - }; - - port@3 { - reg = <3>; - - amx1_in4: endpoint { - remote-endpoint = <&xbar_amx1_in4>; - }; - }; - - amx1_out_port: port@4 { - reg = <4>; - - amx1_out: endpoint { - remote-endpoint = <&xbar_amx1_out>; - }; - }; - }; - }; - - amx@2903100 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx2_in1: endpoint { - remote-endpoint = <&xbar_amx2_in1>; - }; - }; - - port@1 { - reg = <1>; - - amx2_in2: endpoint { - remote-endpoint = <&xbar_amx2_in2>; - }; - }; - - port@2 { - reg = <2>; - - amx2_in3: endpoint { - remote-endpoint = <&xbar_amx2_in3>; - }; - }; - - port@3 { - reg = <3>; - - amx2_in4: endpoint { - remote-endpoint = <&xbar_amx2_in4>; - }; - }; - - amx2_out_port: port@4 { - reg = <4>; - - amx2_out: endpoint { - remote-endpoint = <&xbar_amx2_out>; - }; - }; - }; - }; - - amx@2903200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx3_in1: endpoint { - remote-endpoint = <&xbar_amx3_in1>; - }; - }; - - port@1 { - reg = <1>; - - amx3_in2: endpoint { - remote-endpoint = <&xbar_amx3_in2>; - }; - }; - - port@2 { - reg = <2>; - - amx3_in3: endpoint { - remote-endpoint = <&xbar_amx3_in3>; - }; - }; - - port@3 { - reg = <3>; - - amx3_in4: endpoint { - remote-endpoint = <&xbar_amx3_in4>; - }; - }; - - amx3_out_port: port@4 { - reg = <4>; - - amx3_out: endpoint { - remote-endpoint = <&xbar_amx3_out>; - }; - }; - }; - }; - - amx@2903300 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx4_in1: endpoint { - remote-endpoint = <&xbar_amx4_in1>; - }; - }; - - port@1 { - reg = <1>; - - amx4_in2: endpoint { - remote-endpoint = <&xbar_amx4_in2>; - }; - }; - - port@2 { - reg = <2>; - - amx4_in3: endpoint { - remote-endpoint = <&xbar_amx4_in3>; - }; - }; - - port@3 { - reg = <3>; - - amx4_in4: endpoint { - remote-endpoint = <&xbar_amx4_in4>; - }; - }; - - amx4_out_port: port@4 { - reg = <4>; - - amx4_out: endpoint { - remote-endpoint = <&xbar_amx4_out>; - }; - }; - }; - }; - - adx@2903800 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx1_in: endpoint { - remote-endpoint = <&xbar_adx1_in>; - }; - }; - - adx1_out1_port: port@1 { - reg = <1>; - - adx1_out1: endpoint { - remote-endpoint = <&xbar_adx1_out1>; - }; - }; - - adx1_out2_port: port@2 { - reg = <2>; - - adx1_out2: endpoint { - remote-endpoint = <&xbar_adx1_out2>; - }; - }; - - adx1_out3_port: port@3 { - reg = <3>; - - adx1_out3: endpoint { - remote-endpoint = <&xbar_adx1_out3>; - }; - }; - - adx1_out4_port: port@4 { - reg = <4>; - - adx1_out4: endpoint { - remote-endpoint = <&xbar_adx1_out4>; - }; - }; - }; - }; - - adx@2903900 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx2_in: endpoint { - remote-endpoint = <&xbar_adx2_in>; - }; - }; - - adx2_out1_port: port@1 { - reg = <1>; - - adx2_out1: endpoint { - remote-endpoint = <&xbar_adx2_out1>; - }; - }; - - adx2_out2_port: port@2 { - reg = <2>; - - adx2_out2: endpoint { - remote-endpoint = <&xbar_adx2_out2>; - }; - }; - - adx2_out3_port: port@3 { - reg = <3>; - - adx2_out3: endpoint { - remote-endpoint = <&xbar_adx2_out3>; - }; - }; - - adx2_out4_port: port@4 { - reg = <4>; - - adx2_out4: endpoint { - remote-endpoint = <&xbar_adx2_out4>; - }; - }; - }; - }; - - adx@2903a00 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx3_in: endpoint { - remote-endpoint = <&xbar_adx3_in>; - }; - }; - - adx3_out1_port: port@1 { - reg = <1>; - - adx3_out1: endpoint { - remote-endpoint = <&xbar_adx3_out1>; - }; - }; - - adx3_out2_port: port@2 { - reg = <2>; - - adx3_out2: endpoint { - remote-endpoint = <&xbar_adx3_out2>; - }; - }; - - adx3_out3_port: port@3 { - reg = <3>; - - adx3_out3: endpoint { - remote-endpoint = <&xbar_adx3_out3>; - }; - }; - - adx3_out4_port: port@4 { - reg = <4>; - - adx3_out4: endpoint { - remote-endpoint = <&xbar_adx3_out4>; - }; - }; - }; - }; - - adx@2903b00 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx4_in: endpoint { - remote-endpoint = <&xbar_adx4_in>; - }; - }; - - adx4_out1_port: port@1 { - reg = <1>; - - adx4_out1: endpoint { - remote-endpoint = <&xbar_adx4_out1>; - }; - }; - - adx4_out2_port: port@2 { - reg = <2>; - - adx4_out2: endpoint { - remote-endpoint = <&xbar_adx4_out2>; - }; - }; - - adx4_out3_port: port@3 { - reg = <3>; - - adx4_out3: endpoint { - remote-endpoint = <&xbar_adx4_out3>; - }; - }; - - adx4_out4_port: port@4 { - reg = <4>; - - adx4_out4: endpoint { - remote-endpoint = <&xbar_adx4_out4>; - }; - }; - }; }; dmic@2904200 { status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic3_cif: endpoint { - remote-endpoint = <&xbar_dmic3>; - }; - }; - - dmic3_port: port@1 { - reg = <1>; - - dmic3_dap: endpoint { - /* placeholder for external codec */ - }; - }; - }; - }; - - processing-engine@2908000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - ope1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_ope1_in_ep>; - }; - }; - - ope1_out_port: port@1 { - reg = <0x1>; - - ope1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_ope1_out_ep>; - }; - }; - }; - }; - - mvc@290a000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mvc1_cif_in: endpoint { - remote-endpoint = <&xbar_mvc1_in>; - }; - }; - - mvc1_out_port: port@1 { - reg = <1>; - - mvc1_cif_out: endpoint { - remote-endpoint = <&xbar_mvc1_out>; - }; - }; - }; - }; - - mvc@290a200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mvc2_cif_in: endpoint { - remote-endpoint = <&xbar_mvc2_in>; - }; - }; - - mvc2_out_port: port@1 { - reg = <1>; - - mvc2_cif_out: endpoint { - remote-endpoint = <&xbar_mvc2_out>; - }; - }; - }; - }; - - amixer@290bb00 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - mix_in1: endpoint { - remote-endpoint = <&xbar_mix_in1>; - }; - }; - - port@1 { - reg = <0x1>; - - mix_in2: endpoint { - remote-endpoint = <&xbar_mix_in2>; - }; - }; - - port@2 { - reg = <0x2>; - - mix_in3: endpoint { - remote-endpoint = <&xbar_mix_in3>; - }; - }; - - port@3 { - reg = <0x3>; - - mix_in4: endpoint { - remote-endpoint = <&xbar_mix_in4>; - }; - }; - - port@4 { - reg = <0x4>; - - mix_in5: endpoint { - remote-endpoint = <&xbar_mix_in5>; - }; - }; - - port@5 { - reg = <0x5>; - - mix_in6: endpoint { - remote-endpoint = <&xbar_mix_in6>; - }; - }; - - port@6 { - reg = <0x6>; - - mix_in7: endpoint { - remote-endpoint = <&xbar_mix_in7>; - }; - }; - - port@7 { - reg = <0x7>; - - mix_in8: endpoint { - remote-endpoint = <&xbar_mix_in8>; - }; - }; - - port@8 { - reg = <0x8>; - - mix_in9: endpoint { - remote-endpoint = <&xbar_mix_in9>; - }; - }; - - port@9 { - reg = <0x9>; - - mix_in10: endpoint { - remote-endpoint = <&xbar_mix_in10>; - }; - }; - - mix_out1_port: port@a { - reg = <0xa>; - - mix_out1: endpoint { - remote-endpoint = <&xbar_mix_out1>; - }; - }; - - mix_out2_port: port@b { - reg = <0xb>; - - mix_out2: endpoint { - remote-endpoint = <&xbar_mix_out2>; - }; - }; - - mix_out3_port: port@c { - reg = <0xc>; - - mix_out3: endpoint { - remote-endpoint = <&xbar_mix_out3>; - }; - }; - - mix_out4_port: port@d { - reg = <0xd>; - - mix_out4: endpoint { - remote-endpoint = <&xbar_mix_out4>; - }; - }; - - mix_out5_port: port@e { - reg = <0xe>; - - mix_out5: endpoint { - remote-endpoint = <&xbar_mix_out5>; - }; - }; - }; - }; - - admaif@290f000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - admaif0_port: port@0 { - reg = <0x0>; - - admaif0: endpoint { - remote-endpoint = <&xbar_admaif0>; - }; - }; - - admaif1_port: port@1 { - reg = <0x1>; - - admaif1: endpoint { - remote-endpoint = <&xbar_admaif1>; - }; - }; - - admaif2_port: port@2 { - reg = <0x2>; - - admaif2: endpoint { - remote-endpoint = <&xbar_admaif2>; - }; - }; - - admaif3_port: port@3 { - reg = <0x3>; - - admaif3: endpoint { - remote-endpoint = <&xbar_admaif3>; - }; - }; - - admaif4_port: port@4 { - reg = <0x4>; - - admaif4: endpoint { - remote-endpoint = <&xbar_admaif4>; - }; - }; - - admaif5_port: port@5 { - reg = <0x5>; - - admaif5: endpoint { - remote-endpoint = <&xbar_admaif5>; - }; - }; - - admaif6_port: port@6 { - reg = <0x6>; - - admaif6: endpoint { - remote-endpoint = <&xbar_admaif6>; - }; - }; - - admaif7_port: port@7 { - reg = <0x7>; - - admaif7: endpoint { - remote-endpoint = <&xbar_admaif7>; - }; - }; - - admaif8_port: port@8 { - reg = <0x8>; - - admaif8: endpoint { - remote-endpoint = <&xbar_admaif8>; - }; - }; - - admaif9_port: port@9 { - reg = <0x9>; - - admaif9: endpoint { - remote-endpoint = <&xbar_admaif9>; - }; - }; - - admaif10_port: port@a { - reg = <0xa>; - - admaif10: endpoint { - remote-endpoint = <&xbar_admaif10>; - }; - }; - - admaif11_port: port@b { - reg = <0xb>; - - admaif11: endpoint { - remote-endpoint = <&xbar_admaif11>; - }; - }; - - admaif12_port: port@c { - reg = <0xc>; - - admaif12: endpoint { - remote-endpoint = <&xbar_admaif12>; - }; - }; - - admaif13_port: port@d { - reg = <0xd>; - - admaif13: endpoint { - remote-endpoint = <&xbar_admaif13>; - }; - }; - - admaif14_port: port@e { - reg = <0xe>; - - admaif14: endpoint { - remote-endpoint = <&xbar_admaif14>; - }; - }; - - admaif15_port: port@f { - reg = <0xf>; - - admaif15: endpoint { - remote-endpoint = <&xbar_admaif15>; - }; - }; - - admaif16_port: port@10 { - reg = <0x10>; - - admaif16: endpoint { - remote-endpoint = <&xbar_admaif16>; - }; - }; - - admaif17_port: port@11 { - reg = <0x11>; - - admaif17: endpoint { - remote-endpoint = <&xbar_admaif17>; - }; - }; - - admaif18_port: port@12 { - reg = <0x12>; - - admaif18: endpoint { - remote-endpoint = <&xbar_admaif18>; - }; - }; - - admaif19_port: port@13 { - reg = <0x13>; - - admaif19: endpoint { - remote-endpoint = <&xbar_admaif19>; - }; - }; - }; - }; - - asrc@2910000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - asrc_in1_ep: endpoint { - remote-endpoint = <&xbar_asrc_in1_ep>; - }; - }; - - port@1 { - reg = <0x1>; - - asrc_in2_ep: endpoint { - remote-endpoint = <&xbar_asrc_in2_ep>; - }; - }; - - port@2 { - reg = <0x2>; - - asrc_in3_ep: endpoint { - remote-endpoint = <&xbar_asrc_in3_ep>; - }; - }; - - port@3 { - reg = <0x3>; - - asrc_in4_ep: endpoint { - remote-endpoint = <&xbar_asrc_in4_ep>; - }; - }; - - port@4 { - reg = <0x4>; - - asrc_in5_ep: endpoint { - remote-endpoint = <&xbar_asrc_in5_ep>; - }; - }; - - port@5 { - reg = <0x5>; - - asrc_in6_ep: endpoint { - remote-endpoint = <&xbar_asrc_in6_ep>; - }; - }; - - port@6 { - reg = <0x6>; - - asrc_in7_ep: endpoint { - remote-endpoint = <&xbar_asrc_in7_ep>; - }; - }; - - asrc_out1_port: port@7 { - reg = <0x7>; - - asrc_out1_ep: endpoint { - remote-endpoint = <&xbar_asrc_out1_ep>; - }; - }; - - asrc_out2_port: port@8 { - reg = <0x8>; - - asrc_out2_ep: endpoint { - remote-endpoint = <&xbar_asrc_out2_ep>; - }; - }; - - asrc_out3_port: port@9 { - reg = <0x9>; - - asrc_out3_ep: endpoint { - remote-endpoint = <&xbar_asrc_out3_ep>; - }; - }; - - asrc_out4_port: port@a { - reg = <0xa>; - - asrc_out4_ep: endpoint { - remote-endpoint = <&xbar_asrc_out4_ep>; - }; - }; - - asrc_out5_port: port@b { - reg = <0xb>; - - asrc_out5_ep: endpoint { - remote-endpoint = <&xbar_asrc_out5_ep>; - }; - }; - - asrc_out6_port: port@c { - reg = <0xc>; - - asrc_out6_ep: endpoint { - remote-endpoint = <&xbar_asrc_out6_ep>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - xbar_admaif0: endpoint { - remote-endpoint = <&admaif0>; - }; - }; - - port@1 { - reg = <0x1>; - - xbar_admaif1: endpoint { - remote-endpoint = <&admaif1>; - }; - }; - - port@2 { - reg = <0x2>; - - xbar_admaif2: endpoint { - remote-endpoint = <&admaif2>; - }; - }; - - port@3 { - reg = <0x3>; - - xbar_admaif3: endpoint { - remote-endpoint = <&admaif3>; - }; - }; - - port@4 { - reg = <0x4>; - - xbar_admaif4: endpoint { - remote-endpoint = <&admaif4>; - }; - }; - - port@5 { - reg = <0x5>; - - xbar_admaif5: endpoint { - remote-endpoint = <&admaif5>; - }; - }; - - port@6 { - reg = <0x6>; - - xbar_admaif6: endpoint { - remote-endpoint = <&admaif6>; - }; - }; - - port@7 { - reg = <0x7>; - - xbar_admaif7: endpoint { - remote-endpoint = <&admaif7>; - }; - }; - - port@8 { - reg = <0x8>; - - xbar_admaif8: endpoint { - remote-endpoint = <&admaif8>; - }; - }; - - port@9 { - reg = <0x9>; - - xbar_admaif9: endpoint { - remote-endpoint = <&admaif9>; - }; - }; - - port@a { - reg = <0xa>; - - xbar_admaif10: endpoint { - remote-endpoint = <&admaif10>; - }; - }; - - port@b { - reg = <0xb>; - - xbar_admaif11: endpoint { - remote-endpoint = <&admaif11>; - }; - }; - - port@c { - reg = <0xc>; - - xbar_admaif12: endpoint { - remote-endpoint = <&admaif12>; - }; - }; - - port@d { - reg = <0xd>; - - xbar_admaif13: endpoint { - remote-endpoint = <&admaif13>; - }; - }; - - port@e { - reg = <0xe>; - - xbar_admaif14: endpoint { - remote-endpoint = <&admaif14>; - }; - }; - - port@f { - reg = <0xf>; - - xbar_admaif15: endpoint { - remote-endpoint = <&admaif15>; - }; - }; - - port@10 { - reg = <0x10>; - - xbar_admaif16: endpoint { - remote-endpoint = <&admaif16>; - }; - }; - - port@11 { - reg = <0x11>; - - xbar_admaif17: endpoint { - remote-endpoint = <&admaif17>; - }; - }; - - port@12 { - reg = <0x12>; - - xbar_admaif18: endpoint { - remote-endpoint = <&admaif18>; - }; - }; - - port@13 { - reg = <0x13>; - - xbar_admaif19: endpoint { - remote-endpoint = <&admaif19>; - }; - }; - - xbar_i2s1_port: port@14 { - reg = <0x14>; - - xbar_i2s1: endpoint { - remote-endpoint = <&i2s1_cif>; - }; - }; - - xbar_i2s2_port: port@15 { - reg = <0x15>; - - xbar_i2s2: endpoint { - remote-endpoint = <&i2s2_cif>; - }; - }; - - xbar_i2s4_port: port@17 { - reg = <0x17>; - - xbar_i2s4: endpoint { - remote-endpoint = <&i2s4_cif>; - }; - }; - - xbar_i2s6_port: port@19 { - reg = <0x19>; - - xbar_i2s6: endpoint { - remote-endpoint = <&i2s6_cif>; - }; - }; - - xbar_dmic3_port: port@1c { - reg = <0x1c>; - - xbar_dmic3: endpoint { - remote-endpoint = <&dmic3_cif>; - }; - }; - - xbar_sfc1_in_port: port@20 { - reg = <0x20>; - - xbar_sfc1_in: endpoint { - remote-endpoint = <&sfc1_cif_in>; - }; - }; - - port@21 { - reg = <0x21>; - - xbar_sfc1_out: endpoint { - remote-endpoint = <&sfc1_cif_out>; - }; - }; - - xbar_sfc2_in_port: port@22 { - reg = <0x22>; - - xbar_sfc2_in: endpoint { - remote-endpoint = <&sfc2_cif_in>; - }; - }; - - port@23 { - reg = <0x23>; - - xbar_sfc2_out: endpoint { - remote-endpoint = <&sfc2_cif_out>; - }; - }; - - xbar_sfc3_in_port: port@24 { - reg = <0x24>; - - xbar_sfc3_in: endpoint { - remote-endpoint = <&sfc3_cif_in>; - }; - }; - - port@25 { - reg = <0x25>; - - xbar_sfc3_out: endpoint { - remote-endpoint = <&sfc3_cif_out>; - }; - }; - - xbar_sfc4_in_port: port@26 { - reg = <0x26>; - - xbar_sfc4_in: endpoint { - remote-endpoint = <&sfc4_cif_in>; - }; - }; - - port@27 { - reg = <0x27>; - - xbar_sfc4_out: endpoint { - remote-endpoint = <&sfc4_cif_out>; - }; - }; - - xbar_mvc1_in_port: port@28 { - reg = <0x28>; - - xbar_mvc1_in: endpoint { - remote-endpoint = <&mvc1_cif_in>; - }; - }; - - port@29 { - reg = <0x29>; - - xbar_mvc1_out: endpoint { - remote-endpoint = <&mvc1_cif_out>; - }; - }; - - xbar_mvc2_in_port: port@2a { - reg = <0x2a>; - - xbar_mvc2_in: endpoint { - remote-endpoint = <&mvc2_cif_in>; - }; - }; - - port@2b { - reg = <0x2b>; - - xbar_mvc2_out: endpoint { - remote-endpoint = <&mvc2_cif_out>; - }; - }; - - xbar_amx1_in1_port: port@2c { - reg = <0x2c>; - - xbar_amx1_in1: endpoint { - remote-endpoint = <&amx1_in1>; - }; - }; - - xbar_amx1_in2_port: port@2d { - reg = <0x2d>; - - xbar_amx1_in2: endpoint { - remote-endpoint = <&amx1_in2>; - }; - }; - - xbar_amx1_in3_port: port@2e { - reg = <0x2e>; - - xbar_amx1_in3: endpoint { - remote-endpoint = <&amx1_in3>; - }; - }; - - xbar_amx1_in4_port: port@2f { - reg = <0x2f>; - - xbar_amx1_in4: endpoint { - remote-endpoint = <&amx1_in4>; - }; - }; - - port@30 { - reg = <0x30>; - - xbar_amx1_out: endpoint { - remote-endpoint = <&amx1_out>; - }; - }; - - xbar_amx2_in1_port: port@31 { - reg = <0x31>; - - xbar_amx2_in1: endpoint { - remote-endpoint = <&amx2_in1>; - }; - }; - - xbar_amx2_in2_port: port@32 { - reg = <0x32>; - - xbar_amx2_in2: endpoint { - remote-endpoint = <&amx2_in2>; - }; - }; - - xbar_amx2_in3_port: port@33 { - reg = <0x33>; - - xbar_amx2_in3: endpoint { - remote-endpoint = <&amx2_in3>; - }; - }; - - xbar_amx2_in4_port: port@34 { - reg = <0x34>; - - xbar_amx2_in4: endpoint { - remote-endpoint = <&amx2_in4>; - }; - }; - - port@35 { - reg = <0x35>; - - xbar_amx2_out: endpoint { - remote-endpoint = <&amx2_out>; - }; - }; - - xbar_amx3_in1_port: port@36 { - reg = <0x36>; - - xbar_amx3_in1: endpoint { - remote-endpoint = <&amx3_in1>; - }; - }; - - xbar_amx3_in2_port: port@37 { - reg = <0x37>; - - xbar_amx3_in2: endpoint { - remote-endpoint = <&amx3_in2>; - }; - }; - - xbar_amx3_in3_port: port@38 { - reg = <0x38>; - - xbar_amx3_in3: endpoint { - remote-endpoint = <&amx3_in3>; - }; - }; - - xbar_amx3_in4_port: port@39 { - reg = <0x39>; - - xbar_amx3_in4: endpoint { - remote-endpoint = <&amx3_in4>; - }; - }; - - port@3a { - reg = <0x3a>; - - xbar_amx3_out: endpoint { - remote-endpoint = <&amx3_out>; - }; - }; - - xbar_amx4_in1_port: port@3b { - reg = <0x3b>; - - xbar_amx4_in1: endpoint { - remote-endpoint = <&amx4_in1>; - }; - }; - - xbar_amx4_in2_port: port@3c { - reg = <0x3c>; - - xbar_amx4_in2: endpoint { - remote-endpoint = <&amx4_in2>; - }; - }; - - xbar_amx4_in3_port: port@3d { - reg = <0x3d>; - - xbar_amx4_in3: endpoint { - remote-endpoint = <&amx4_in3>; - }; - }; - - xbar_amx4_in4_port: port@3e { - reg = <0x3e>; - - xbar_amx4_in4: endpoint { - remote-endpoint = <&amx4_in4>; - }; - }; - - port@3f { - reg = <0x3f>; - - xbar_amx4_out: endpoint { - remote-endpoint = <&amx4_out>; - }; - }; - - xbar_adx1_in_port: port@40 { - reg = <0x40>; - - xbar_adx1_in: endpoint { - remote-endpoint = <&adx1_in>; - }; - }; - - port@41 { - reg = <0x41>; - - xbar_adx1_out1: endpoint { - remote-endpoint = <&adx1_out1>; - }; - }; - - port@42 { - reg = <0x42>; - - xbar_adx1_out2: endpoint { - remote-endpoint = <&adx1_out2>; - }; - }; - - port@43 { - reg = <0x43>; - - xbar_adx1_out3: endpoint { - remote-endpoint = <&adx1_out3>; - }; - }; - - port@44 { - reg = <0x44>; - - xbar_adx1_out4: endpoint { - remote-endpoint = <&adx1_out4>; - }; - }; - - xbar_adx2_in_port: port@45 { - reg = <0x45>; - - xbar_adx2_in: endpoint { - remote-endpoint = <&adx2_in>; - }; - }; - - port@46 { - reg = <0x46>; - - xbar_adx2_out1: endpoint { - remote-endpoint = <&adx2_out1>; - }; - }; - - port@47 { - reg = <0x47>; - - xbar_adx2_out2: endpoint { - remote-endpoint = <&adx2_out2>; - }; - }; - - port@48 { - reg = <0x48>; - - xbar_adx2_out3: endpoint { - remote-endpoint = <&adx2_out3>; - }; - }; - - port@49 { - reg = <0x49>; - - xbar_adx2_out4: endpoint { - remote-endpoint = <&adx2_out4>; - }; - }; - - xbar_adx3_in_port: port@4a { - reg = <0x4a>; - - xbar_adx3_in: endpoint { - remote-endpoint = <&adx3_in>; - }; - }; - - port@4b { - reg = <0x4b>; - - xbar_adx3_out1: endpoint { - remote-endpoint = <&adx3_out1>; - }; - }; - - port@4c { - reg = <0x4c>; - - xbar_adx3_out2: endpoint { - remote-endpoint = <&adx3_out2>; - }; - }; - - port@4d { - reg = <0x4d>; - - xbar_adx3_out3: endpoint { - remote-endpoint = <&adx3_out3>; - }; - }; - - port@4e { - reg = <0x4e>; - - xbar_adx3_out4: endpoint { - remote-endpoint = <&adx3_out4>; - }; - }; - - xbar_adx4_in_port: port@4f { - reg = <0x4f>; - - xbar_adx4_in: endpoint { - remote-endpoint = <&adx4_in>; - }; - }; - - port@50 { - reg = <0x50>; - - xbar_adx4_out1: endpoint { - remote-endpoint = <&adx4_out1>; - }; - }; - - port@51 { - reg = <0x51>; - - xbar_adx4_out2: endpoint { - remote-endpoint = <&adx4_out2>; - }; - }; - - port@52 { - reg = <0x52>; - - xbar_adx4_out3: endpoint { - remote-endpoint = <&adx4_out3>; - }; - }; - - port@53 { - reg = <0x53>; - - xbar_adx4_out4: endpoint { - remote-endpoint = <&adx4_out4>; - }; - }; - - xbar_mix_in1_port: port@54 { - reg = <0x54>; - - xbar_mix_in1: endpoint { - remote-endpoint = <&mix_in1>; - }; - }; - - xbar_mix_in2_port: port@55 { - reg = <0x55>; - - xbar_mix_in2: endpoint { - remote-endpoint = <&mix_in2>; - }; - }; - - xbar_mix_in3_port: port@56 { - reg = <0x56>; - - xbar_mix_in3: endpoint { - remote-endpoint = <&mix_in3>; - }; - }; - - xbar_mix_in4_port: port@57 { - reg = <0x57>; - - xbar_mix_in4: endpoint { - remote-endpoint = <&mix_in4>; - }; - }; - - xbar_mix_in5_port: port@58 { - reg = <0x58>; - - xbar_mix_in5: endpoint { - remote-endpoint = <&mix_in5>; - }; - }; - - xbar_mix_in6_port: port@59 { - reg = <0x59>; - - xbar_mix_in6: endpoint { - remote-endpoint = <&mix_in6>; - }; - }; - - xbar_mix_in7_port: port@5a { - reg = <0x5a>; - - xbar_mix_in7: endpoint { - remote-endpoint = <&mix_in7>; - }; - }; - - xbar_mix_in8_port: port@5b { - reg = <0x5b>; - - xbar_mix_in8: endpoint { - remote-endpoint = <&mix_in8>; - }; - }; - - xbar_mix_in9_port: port@5c { - reg = <0x5c>; - - xbar_mix_in9: endpoint { - remote-endpoint = <&mix_in9>; - }; - }; - - xbar_mix_in10_port: port@5d { - reg = <0x5d>; - - xbar_mix_in10: endpoint { - remote-endpoint = <&mix_in10>; - }; - }; - - port@5e { - reg = <0x5e>; - - xbar_mix_out1: endpoint { - remote-endpoint = <&mix_out1>; - }; - }; - - port@5f { - reg = <0x5f>; - - xbar_mix_out2: endpoint { - remote-endpoint = <&mix_out2>; - }; - }; - - port@60 { - reg = <0x60>; - - xbar_mix_out3: endpoint { - remote-endpoint = <&mix_out3>; - }; - }; - - port@61 { - reg = <0x61>; - - xbar_mix_out4: endpoint { - remote-endpoint = <&mix_out4>; - }; - }; - - port@62 { - reg = <0x62>; - - xbar_mix_out5: endpoint { - remote-endpoint = <&mix_out5>; - }; - }; - - xbar_asrc_in1_port: port@63 { - reg = <0x63>; - - xbar_asrc_in1_ep: endpoint { - remote-endpoint = <&asrc_in1_ep>; - }; - }; - - port@64 { - reg = <0x64>; - - xbar_asrc_out1_ep: endpoint { - remote-endpoint = <&asrc_out1_ep>; - }; - }; - - xbar_asrc_in2_port: port@65 { - reg = <0x65>; - - xbar_asrc_in2_ep: endpoint { - remote-endpoint = <&asrc_in2_ep>; - }; - }; - - port@66 { - reg = <0x66>; - - xbar_asrc_out2_ep: endpoint { - remote-endpoint = <&asrc_out2_ep>; - }; - }; - - xbar_asrc_in3_port: port@67 { - reg = <0x67>; - - xbar_asrc_in3_ep: endpoint { - remote-endpoint = <&asrc_in3_ep>; - }; - }; - - port@68 { - reg = <0x68>; - - xbar_asrc_out3_ep: endpoint { - remote-endpoint = <&asrc_out3_ep>; - }; - }; - - xbar_asrc_in4_port: port@69 { - reg = <0x69>; - - xbar_asrc_in4_ep: endpoint { - remote-endpoint = <&asrc_in4_ep>; - }; - }; - - port@6a { - reg = <0x6a>; - - xbar_asrc_out4_ep: endpoint { - remote-endpoint = <&asrc_out4_ep>; - }; - }; - - xbar_asrc_in5_port: port@6b { - reg = <0x6b>; - - xbar_asrc_in5_ep: endpoint { - remote-endpoint = <&asrc_in5_ep>; - }; - }; - - port@6c { - reg = <0x6c>; - - xbar_asrc_out5_ep: endpoint { - remote-endpoint = <&asrc_out5_ep>; - }; - }; - - xbar_asrc_in6_port: port@6d { - reg = <0x6d>; - - xbar_asrc_in6_ep: endpoint { - remote-endpoint = <&asrc_in6_ep>; - }; - }; - - port@6e { - reg = <0x6e>; - - xbar_asrc_out6_ep: endpoint { - remote-endpoint = <&asrc_out6_ep>; - }; - }; - - xbar_asrc_in7_port: port@6f { - reg = <0x6f>; - - xbar_asrc_in7_ep: endpoint { - remote-endpoint = <&asrc_in7_ep>; - }; - }; - - xbar_ope1_in_port: port@70 { - reg = <0x70>; - - xbar_ope1_in_ep: endpoint { - remote-endpoint = <&ope1_cif_in_ep>; - }; - }; - - port@71 { - reg = <0x71>; - - xbar_ope1_out_ep: endpoint { - remote-endpoint = <&ope1_cif_out_ep>; - }; - }; }; }; diff --git a/src/arm64/nvidia/tegra234-p3737-0000+p3701-0000.dts b/src/arm64/nvidia/tegra234-p3737-0000+p3701-0000.dts index 81a82933e35..69db584253d 100644 --- a/src/arm64/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/src/arm64/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -12,7 +12,6 @@ compatible = "nvidia,p3737-0000+p3701-0000", "nvidia,p3701-0000", "nvidia,tegra234"; aliases { - mmc3 = "/bus@0/mmc@3460000"; serial0 = &tcu; serial1 = &uarta; }; diff --git a/src/arm64/nvidia/tegra234-p3767-0000.dtsi b/src/arm64/nvidia/tegra234-p3767-0000.dtsi deleted file mode 100644 index baf4f69e410..00000000000 --- a/src/arm64/nvidia/tegra234-p3767-0000.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include "tegra234-p3767.dtsi" - -/ { - compatible = "nvidia,p3767-0000", "nvidia,tegra234"; - model = "NVIDIA Jetson Orin NX"; - - bus@0 { - hda@3510000 { - nvidia,model = "NVIDIA Jetson Orin NX HDA"; - }; - }; -}; diff --git a/src/arm64/nvidia/tegra234-p3767-0005.dtsi b/src/arm64/nvidia/tegra234-p3767-0005.dtsi deleted file mode 100644 index 232fa95ef4a..00000000000 --- a/src/arm64/nvidia/tegra234-p3767-0005.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include "tegra234-p3767.dtsi" - -/ { - compatible = "nvidia,p3767-0005", "nvidia,tegra234"; - model = "NVIDIA Jetson Orin Nano"; - - bus@0 { - hda@3510000 { - nvidia,model = "NVIDIA Jetson Orin Nano HDA"; - }; - }; -}; diff --git a/src/arm64/nvidia/tegra234-p3767.dtsi b/src/arm64/nvidia/tegra234-p3767.dtsi index 59c14ded5e9..84db7132e8f 100644 --- a/src/arm64/nvidia/tegra234-p3767.dtsi +++ b/src/arm64/nvidia/tegra234-p3767.dtsi @@ -5,7 +5,35 @@ / { compatible = "nvidia,p3767", "nvidia,tegra234"; + aliases { + mmc0 = "/bus@0/mmc@3400000"; + }; + bus@0 { + aconnect@2900000 { + status = "okay"; + + ahub@2900800 { + status = "okay"; + + i2s@2901100 { + status = "okay"; + }; + + i2s@2901300 { + status = "okay"; + }; + }; + + dma-controller@2930000 { + status = "okay"; + }; + + interrupt-controller@2a40000 { + status = "okay"; + }; + }; + i2c@3160000 { status = "okay"; @@ -127,6 +155,64 @@ vin-supply = <&vdd_5v0_sys>; }; + sound { + compatible = "nvidia,tegra186-audio-graph-card"; + status = "okay"; + + dais = /* ADMAIF (FE) Ports */ + <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, + <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>, + <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>, + <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>, + <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>, + /* XBAR Ports */ + <&xbar_i2s2_port>, <&xbar_i2s4_port>, + <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>, + <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>, + <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>, + <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>, + <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>, + <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>, + <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>, + <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>, + <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>, + <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>, + <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>, + <&xbar_adx1_in_port>, <&xbar_adx2_in_port>, + <&xbar_adx3_in_port>, <&xbar_adx4_in_port>, + <&xbar_mix_in1_port>, <&xbar_mix_in2_port>, + <&xbar_mix_in3_port>, <&xbar_mix_in4_port>, + <&xbar_mix_in5_port>, <&xbar_mix_in6_port>, + <&xbar_mix_in7_port>, <&xbar_mix_in8_port>, + <&xbar_mix_in9_port>, <&xbar_mix_in10_port>, + <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>, + <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>, + <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>, + <&xbar_asrc_in7_port>, + <&xbar_ope1_in_port>, + /* HW accelerators */ + <&sfc1_out_port>, <&sfc2_out_port>, + <&sfc3_out_port>, <&sfc4_out_port>, + <&mvc1_out_port>, <&mvc2_out_port>, + <&amx1_out_port>, <&amx2_out_port>, + <&amx3_out_port>, <&amx4_out_port>, + <&adx1_out1_port>, <&adx1_out2_port>, + <&adx1_out3_port>, <&adx1_out4_port>, + <&adx2_out1_port>, <&adx2_out2_port>, + <&adx2_out3_port>, <&adx2_out4_port>, + <&adx3_out1_port>, <&adx3_out2_port>, + <&adx3_out3_port>, <&adx3_out4_port>, + <&adx4_out1_port>, <&adx4_out2_port>, + <&adx4_out3_port>, <&adx4_out4_port>, + <&mix_out1_port>, <&mix_out2_port>, <&mix_out3_port>, + <&mix_out4_port>, <&mix_out5_port>, + <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>, + <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>, + <&ope1_out_port>, + /* BE I/O Ports */ + <&i2s2_port>, <&i2s4_port>; + }; + thermal-zones { tj-thermal { polling-delay = <1000>; diff --git a/src/arm64/nvidia/tegra234-p3768-0000+p3767-0000.dts b/src/arm64/nvidia/tegra234-p3768-0000+p3767-0000.dts index 61b0e69d3d2..1607ee14216 100644 --- a/src/arm64/nvidia/tegra234-p3768-0000+p3767-0000.dts +++ b/src/arm64/nvidia/tegra234-p3768-0000+p3767-0000.dts @@ -4,7 +4,7 @@ #include #include -#include "tegra234-p3767-0000.dtsi" +#include "tegra234-p3767.dtsi" #include "tegra234-p3768-0000.dtsi" / { @@ -37,7 +37,6 @@ hda@3510000 { nvidia,model = "NVIDIA Jetson Orin NX HDA"; - status = "okay"; }; padctl@3520000 { @@ -85,6 +84,10 @@ enable-active-high; }; + sound { + label = "NVIDIA Jetson Orin NX APE"; + }; + thermal-zones { tj-thermal { cooling-maps { diff --git a/src/arm64/nvidia/tegra234-p3768-0000+p3767-0005.dts b/src/arm64/nvidia/tegra234-p3768-0000+p3767-0005.dts index 9e9bb9ca8be..dc2d4bef1e8 100644 --- a/src/arm64/nvidia/tegra234-p3768-0000+p3767-0005.dts +++ b/src/arm64/nvidia/tegra234-p3768-0000+p3767-0005.dts @@ -4,17 +4,27 @@ #include #include -#include "tegra234-p3767-0005.dtsi" +#include "tegra234-p3767.dtsi" #include "tegra234-p3768-0000.dtsi" / { compatible = "nvidia,p3768-0000+p3767-0005", "nvidia,p3767-0005", "nvidia,tegra234"; model = "NVIDIA Jetson Orin Nano Developer Kit"; + bus@0 { + hda@3510000 { + nvidia,model = "NVIDIA Jetson Orin Nano HDA"; + }; + }; + pwm-fan { cooling-levels = <0 88 187 255>; }; + sound { + label = "NVIDIA Jetson Orin Nano APE"; + }; + thermal-zones { tj-thermal { cooling-maps { diff --git a/src/arm64/nvidia/tegra234-sim-vdk.dts b/src/arm64/nvidia/tegra234-sim-vdk.dts index 9f3e9f30c3f..292e28376ee 100644 --- a/src/arm64/nvidia/tegra234-sim-vdk.dts +++ b/src/arm64/nvidia/tegra234-sim-vdk.dts @@ -8,7 +8,6 @@ compatible = "nvidia,tegra234-vdk", "nvidia,tegra234"; aliases { - mmc3 = "/bus@0/mmc@3460000"; serial0 = &uarta; }; diff --git a/src/arm64/nvidia/tegra234.dtsi b/src/arm64/nvidia/tegra234.dtsi index d1bd328892a..78cbfdd98dd 100644 --- a/src/arm64/nvidia/tegra234.dtsi +++ b/src/arm64/nvidia/tegra234.dtsi @@ -200,6 +200,28 @@ assigned-clock-rates = <1536000>; sound-name-prefix = "I2S1"; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s1_cif: endpoint { + remote-endpoint = <&xbar_i2s1>; + }; + }; + + i2s1_port: port@1 { + reg = <1>; + + i2s1_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; }; tegra_i2s2: i2s@2901100 { @@ -214,6 +236,28 @@ assigned-clock-rates = <1536000>; sound-name-prefix = "I2S2"; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s2_cif: endpoint { + remote-endpoint = <&xbar_i2s2>; + }; + }; + + i2s2_port: port@1 { + reg = <1>; + + i2s2_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; }; tegra_i2s3: i2s@2901200 { @@ -228,6 +272,28 @@ assigned-clock-rates = <1536000>; sound-name-prefix = "I2S3"; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s3_cif: endpoint { + remote-endpoint = <&xbar_i2s3>; + }; + }; + + i2s3_port: port@1 { + reg = <1>; + + i2s3_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; }; tegra_i2s4: i2s@2901300 { @@ -242,6 +308,28 @@ assigned-clock-rates = <1536000>; sound-name-prefix = "I2S4"; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s4_cif: endpoint { + remote-endpoint = <&xbar_i2s4>; + }; + }; + + i2s4_port: port@1 { + reg = <1>; + + i2s4_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; }; tegra_i2s5: i2s@2901400 { @@ -256,6 +344,28 @@ assigned-clock-rates = <1536000>; sound-name-prefix = "I2S5"; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s5_cif: endpoint { + remote-endpoint = <&xbar_i2s5>; + }; + }; + + i2s5_port: port@1 { + reg = <1>; + + i2s5_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; }; tegra_i2s6: i2s@2901500 { @@ -270,6 +380,28 @@ assigned-clock-rates = <1536000>; sound-name-prefix = "I2S6"; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s6_cif: endpoint { + remote-endpoint = <&xbar_i2s6>; + }; + }; + + i2s6_port: port@1 { + reg = <1>; + + i2s6_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; }; tegra_sfc1: sfc@2902000 { @@ -277,7 +409,27 @@ "nvidia,tegra210-sfc"; reg = <0x0 0x2902000 0x0 0x200>; sound-name-prefix = "SFC1"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc1_cif_in: endpoint { + remote-endpoint = <&xbar_sfc1_in>; + }; + }; + + sfc1_out_port: port@1 { + reg = <1>; + + sfc1_cif_out: endpoint { + remote-endpoint = <&xbar_sfc1_out>; + }; + }; + }; }; tegra_sfc2: sfc@2902200 { @@ -285,7 +437,27 @@ "nvidia,tegra210-sfc"; reg = <0x0 0x2902200 0x0 0x200>; sound-name-prefix = "SFC2"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc2_cif_in: endpoint { + remote-endpoint = <&xbar_sfc2_in>; + }; + }; + + sfc2_out_port: port@1 { + reg = <1>; + + sfc2_cif_out: endpoint { + remote-endpoint = <&xbar_sfc2_out>; + }; + }; + }; }; tegra_sfc3: sfc@2902400 { @@ -293,7 +465,27 @@ "nvidia,tegra210-sfc"; reg = <0x0 0x2902400 0x0 0x200>; sound-name-prefix = "SFC3"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc3_cif_in: endpoint { + remote-endpoint = <&xbar_sfc3_in>; + }; + }; + + sfc3_out_port: port@1 { + reg = <1>; + + sfc3_cif_out: endpoint { + remote-endpoint = <&xbar_sfc3_out>; + }; + }; + }; }; tegra_sfc4: sfc@2902600 { @@ -301,7 +493,27 @@ "nvidia,tegra210-sfc"; reg = <0x0 0x2902600 0x0 0x200>; sound-name-prefix = "SFC4"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc4_cif_in: endpoint { + remote-endpoint = <&xbar_sfc4_in>; + }; + }; + + sfc4_out_port: port@1 { + reg = <1>; + + sfc4_cif_out: endpoint { + remote-endpoint = <&xbar_sfc4_out>; + }; + }; + }; }; tegra_amx1: amx@2903000 { @@ -309,7 +521,51 @@ "nvidia,tegra194-amx"; reg = <0x0 0x2903000 0x0 0x100>; sound-name-prefix = "AMX1"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx1_in1: endpoint { + remote-endpoint = <&xbar_amx1_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx1_in2: endpoint { + remote-endpoint = <&xbar_amx1_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx1_in3: endpoint { + remote-endpoint = <&xbar_amx1_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx1_in4: endpoint { + remote-endpoint = <&xbar_amx1_in4>; + }; + }; + + amx1_out_port: port@4 { + reg = <4>; + + amx1_out: endpoint { + remote-endpoint = <&xbar_amx1_out>; + }; + }; + }; }; tegra_amx2: amx@2903100 { @@ -317,7 +573,51 @@ "nvidia,tegra194-amx"; reg = <0x0 0x2903100 0x0 0x100>; sound-name-prefix = "AMX2"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx2_in1: endpoint { + remote-endpoint = <&xbar_amx2_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx2_in2: endpoint { + remote-endpoint = <&xbar_amx2_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx2_in3: endpoint { + remote-endpoint = <&xbar_amx2_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx2_in4: endpoint { + remote-endpoint = <&xbar_amx2_in4>; + }; + }; + + amx2_out_port: port@4 { + reg = <4>; + + amx2_out: endpoint { + remote-endpoint = <&xbar_amx2_out>; + }; + }; + }; }; tegra_amx3: amx@2903200 { @@ -325,7 +625,51 @@ "nvidia,tegra194-amx"; reg = <0x0 0x2903200 0x0 0x100>; sound-name-prefix = "AMX3"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx3_in1: endpoint { + remote-endpoint = <&xbar_amx3_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx3_in2: endpoint { + remote-endpoint = <&xbar_amx3_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx3_in3: endpoint { + remote-endpoint = <&xbar_amx3_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx3_in4: endpoint { + remote-endpoint = <&xbar_amx3_in4>; + }; + }; + + amx3_out_port: port@4 { + reg = <4>; + + amx3_out: endpoint { + remote-endpoint = <&xbar_amx3_out>; + }; + }; + }; }; tegra_amx4: amx@2903300 { @@ -333,7 +677,51 @@ "nvidia,tegra194-amx"; reg = <0x0 0x2903300 0x0 0x100>; sound-name-prefix = "AMX4"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx4_in1: endpoint { + remote-endpoint = <&xbar_amx4_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx4_in2: endpoint { + remote-endpoint = <&xbar_amx4_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx4_in3: endpoint { + remote-endpoint = <&xbar_amx4_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx4_in4: endpoint { + remote-endpoint = <&xbar_amx4_in4>; + }; + }; + + amx4_out_port: port@4 { + reg = <4>; + + amx4_out: endpoint { + remote-endpoint = <&xbar_amx4_out>; + }; + }; + }; }; tegra_adx1: adx@2903800 { @@ -341,7 +729,51 @@ "nvidia,tegra210-adx"; reg = <0x0 0x2903800 0x0 0x100>; sound-name-prefix = "ADX1"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx1_in: endpoint { + remote-endpoint = <&xbar_adx1_in>; + }; + }; + + adx1_out1_port: port@1 { + reg = <1>; + + adx1_out1: endpoint { + remote-endpoint = <&xbar_adx1_out1>; + }; + }; + + adx1_out2_port: port@2 { + reg = <2>; + + adx1_out2: endpoint { + remote-endpoint = <&xbar_adx1_out2>; + }; + }; + + adx1_out3_port: port@3 { + reg = <3>; + + adx1_out3: endpoint { + remote-endpoint = <&xbar_adx1_out3>; + }; + }; + + adx1_out4_port: port@4 { + reg = <4>; + + adx1_out4: endpoint { + remote-endpoint = <&xbar_adx1_out4>; + }; + }; + }; }; tegra_adx2: adx@2903900 { @@ -349,7 +781,51 @@ "nvidia,tegra210-adx"; reg = <0x0 0x2903900 0x0 0x100>; sound-name-prefix = "ADX2"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx2_in: endpoint { + remote-endpoint = <&xbar_adx2_in>; + }; + }; + + adx2_out1_port: port@1 { + reg = <1>; + + adx2_out1: endpoint { + remote-endpoint = <&xbar_adx2_out1>; + }; + }; + + adx2_out2_port: port@2 { + reg = <2>; + + adx2_out2: endpoint { + remote-endpoint = <&xbar_adx2_out2>; + }; + }; + + adx2_out3_port: port@3 { + reg = <3>; + + adx2_out3: endpoint { + remote-endpoint = <&xbar_adx2_out3>; + }; + }; + + adx2_out4_port: port@4 { + reg = <4>; + + adx2_out4: endpoint { + remote-endpoint = <&xbar_adx2_out4>; + }; + }; + }; }; tegra_adx3: adx@2903a00 { @@ -357,7 +833,51 @@ "nvidia,tegra210-adx"; reg = <0x0 0x2903a00 0x0 0x100>; sound-name-prefix = "ADX3"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx3_in: endpoint { + remote-endpoint = <&xbar_adx3_in>; + }; + }; + + adx3_out1_port: port@1 { + reg = <1>; + + adx3_out1: endpoint { + remote-endpoint = <&xbar_adx3_out1>; + }; + }; + + adx3_out2_port: port@2 { + reg = <2>; + + adx3_out2: endpoint { + remote-endpoint = <&xbar_adx3_out2>; + }; + }; + + adx3_out3_port: port@3 { + reg = <3>; + + adx3_out3: endpoint { + remote-endpoint = <&xbar_adx3_out3>; + }; + }; + + adx3_out4_port: port@4 { + reg = <4>; + + adx3_out4: endpoint { + remote-endpoint = <&xbar_adx3_out4>; + }; + }; + }; }; tegra_adx4: adx@2903b00 { @@ -365,7 +885,51 @@ "nvidia,tegra210-adx"; reg = <0x0 0x2903b00 0x0 0x100>; sound-name-prefix = "ADX4"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx4_in: endpoint { + remote-endpoint = <&xbar_adx4_in>; + }; + }; + + adx4_out1_port: port@1 { + reg = <1>; + + adx4_out1: endpoint { + remote-endpoint = <&xbar_adx4_out1>; + }; + }; + + adx4_out2_port: port@2 { + reg = <2>; + + adx4_out2: endpoint { + remote-endpoint = <&xbar_adx4_out2>; + }; + }; + + adx4_out3_port: port@3 { + reg = <3>; + + adx4_out3: endpoint { + remote-endpoint = <&xbar_adx4_out3>; + }; + }; + + adx4_out4_port: port@4 { + reg = <4>; + + adx4_out4: endpoint { + remote-endpoint = <&xbar_adx4_out4>; + }; + }; + }; }; @@ -380,6 +944,27 @@ assigned-clock-rates = <3072000>; sound-name-prefix = "DMIC1"; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic1_cif: endpoint { + remote-endpoint = <&xbar_dmic1>; + }; + }; + + dmic1_port: port@1 { + reg = <1>; + + dmic1_dap: endpoint { + /* placeholder for external codec */ + }; + }; + }; }; tegra_dmic2: dmic@2904100 { @@ -393,6 +978,27 @@ assigned-clock-rates = <3072000>; sound-name-prefix = "DMIC2"; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic2_cif: endpoint { + remote-endpoint = <&xbar_dmic2>; + }; + }; + + dmic2_port: port@1 { + reg = <1>; + + dmic2_dap: endpoint { + /* placeholder for external codec */ + }; + }; + }; }; tegra_dmic3: dmic@2904200 { @@ -406,6 +1012,27 @@ assigned-clock-rates = <3072000>; sound-name-prefix = "DMIC3"; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic3_cif: endpoint { + remote-endpoint = <&xbar_dmic3>; + }; + }; + + dmic3_port: port@1 { + reg = <1>; + + dmic3_dap: endpoint { + /* placeholder for external codec */ + }; + }; + }; }; tegra_dmic4: dmic@2904300 { @@ -419,6 +1046,27 @@ assigned-clock-rates = <3072000>; sound-name-prefix = "DMIC4"; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic4_cif: endpoint { + remote-endpoint = <&xbar_dmic4>; + }; + }; + + dmic4_port: port@1 { + reg = <1>; + + dmic4_dap: endpoint { + /* placeholder for external codec */ + }; + }; + }; }; tegra_dspk1: dspk@2905000 { @@ -432,6 +1080,27 @@ assigned-clock-rates = <12288000>; sound-name-prefix = "DSPK1"; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dspk1_cif: endpoint { + remote-endpoint = <&xbar_dspk1>; + }; + }; + + dspk1_port: port@1 { + reg = <1>; + + dspk1_dap: endpoint { + /* placeholder for external codec */ + }; + }; + }; }; tegra_dspk2: dspk@2905100 { @@ -445,6 +1114,27 @@ assigned-clock-rates = <12288000>; sound-name-prefix = "DSPK2"; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dspk2_cif: endpoint { + remote-endpoint = <&xbar_dspk2>; + }; + }; + + dspk2_port: port@1 { + reg = <1>; + + dspk2_dap: endpoint { + /* placeholder for external codec */ + }; + }; + }; }; tegra_ope1: processing-engine@2908000 { @@ -452,7 +1142,6 @@ "nvidia,tegra210-ope"; reg = <0x0 0x2908000 0x0 0x100>; sound-name-prefix = "OPE1"; - status = "disabled"; #address-cells = <2>; #size-cells = <2>; @@ -469,6 +1158,29 @@ "nvidia,tegra210-mbdrc"; reg = <0x0 0x2908200 0x0 0x200>; }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + ope1_cif_in_ep: endpoint { + remote-endpoint = + <&xbar_ope1_in_ep>; + }; + }; + + ope1_out_port: port@1 { + reg = <0x1>; + + ope1_cif_out_ep: endpoint { + remote-endpoint = + <&xbar_ope1_out_ep>; + }; + }; + }; }; tegra_mvc1: mvc@290a000 { @@ -476,7 +1188,27 @@ "nvidia,tegra210-mvc"; reg = <0x0 0x290a000 0x0 0x200>; sound-name-prefix = "MVC1"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc1_cif_in: endpoint { + remote-endpoint = <&xbar_mvc1_in>; + }; + }; + + mvc1_out_port: port@1 { + reg = <1>; + + mvc1_cif_out: endpoint { + remote-endpoint = <&xbar_mvc1_out>; + }; + }; + }; }; tegra_mvc2: mvc@290a200 { @@ -484,7 +1216,27 @@ "nvidia,tegra210-mvc"; reg = <0x0 0x290a200 0x0 0x200>; sound-name-prefix = "MVC2"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc2_cif_in: endpoint { + remote-endpoint = <&xbar_mvc2_in>; + }; + }; + + mvc2_out_port: port@1 { + reg = <1>; + + mvc2_cif_out: endpoint { + remote-endpoint = <&xbar_mvc2_out>; + }; + }; + }; }; tegra_amixer: amixer@290bb00 { @@ -492,7 +1244,131 @@ "nvidia,tegra210-amixer"; reg = <0x0 0x290bb00 0x0 0x800>; sound-name-prefix = "MIXER1"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + mix_in1: endpoint { + remote-endpoint = <&xbar_mix_in1>; + }; + }; + + port@1 { + reg = <0x1>; + + mix_in2: endpoint { + remote-endpoint = <&xbar_mix_in2>; + }; + }; + + port@2 { + reg = <0x2>; + + mix_in3: endpoint { + remote-endpoint = <&xbar_mix_in3>; + }; + }; + + port@3 { + reg = <0x3>; + + mix_in4: endpoint { + remote-endpoint = <&xbar_mix_in4>; + }; + }; + + port@4 { + reg = <0x4>; + + mix_in5: endpoint { + remote-endpoint = <&xbar_mix_in5>; + }; + }; + + port@5 { + reg = <0x5>; + + mix_in6: endpoint { + remote-endpoint = <&xbar_mix_in6>; + }; + }; + + port@6 { + reg = <0x6>; + + mix_in7: endpoint { + remote-endpoint = <&xbar_mix_in7>; + }; + }; + + port@7 { + reg = <0x7>; + + mix_in8: endpoint { + remote-endpoint = <&xbar_mix_in8>; + }; + }; + + port@8 { + reg = <0x8>; + + mix_in9: endpoint { + remote-endpoint = <&xbar_mix_in9>; + }; + }; + + port@9 { + reg = <0x9>; + + mix_in10: endpoint { + remote-endpoint = <&xbar_mix_in10>; + }; + }; + + mix_out1_port: port@a { + reg = <0xa>; + + mix_out1: endpoint { + remote-endpoint = <&xbar_mix_out1>; + }; + }; + + mix_out2_port: port@b { + reg = <0xb>; + + mix_out2: endpoint { + remote-endpoint = <&xbar_mix_out2>; + }; + }; + + mix_out3_port: port@c { + reg = <0xc>; + + mix_out3: endpoint { + remote-endpoint = <&xbar_mix_out3>; + }; + }; + + mix_out4_port: port@d { + reg = <0xd>; + + mix_out4: endpoint { + remote-endpoint = <&xbar_mix_out4>; + }; + }; + + mix_out5_port: port@e { + reg = <0xe>; + + mix_out5: endpoint { + remote-endpoint = <&xbar_mix_out5>; + }; + }; + }; }; tegra_admaif: admaif@290f000 { @@ -543,7 +1419,171 @@ <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; interconnect-names = "dma-mem", "write"; iommus = <&smmu_niso0 TEGRA234_SID_APE>; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + admaif0_port: port@0 { + reg = <0x0>; + + admaif0: endpoint { + remote-endpoint = <&xbar_admaif0>; + }; + }; + + admaif1_port: port@1 { + reg = <0x1>; + + admaif1: endpoint { + remote-endpoint = <&xbar_admaif1>; + }; + }; + + admaif2_port: port@2 { + reg = <0x2>; + + admaif2: endpoint { + remote-endpoint = <&xbar_admaif2>; + }; + }; + + admaif3_port: port@3 { + reg = <0x3>; + + admaif3: endpoint { + remote-endpoint = <&xbar_admaif3>; + }; + }; + + admaif4_port: port@4 { + reg = <0x4>; + + admaif4: endpoint { + remote-endpoint = <&xbar_admaif4>; + }; + }; + + admaif5_port: port@5 { + reg = <0x5>; + + admaif5: endpoint { + remote-endpoint = <&xbar_admaif5>; + }; + }; + + admaif6_port: port@6 { + reg = <0x6>; + + admaif6: endpoint { + remote-endpoint = <&xbar_admaif6>; + }; + }; + + admaif7_port: port@7 { + reg = <0x7>; + + admaif7: endpoint { + remote-endpoint = <&xbar_admaif7>; + }; + }; + + admaif8_port: port@8 { + reg = <0x8>; + + admaif8: endpoint { + remote-endpoint = <&xbar_admaif8>; + }; + }; + + admaif9_port: port@9 { + reg = <0x9>; + + admaif9: endpoint { + remote-endpoint = <&xbar_admaif9>; + }; + }; + + admaif10_port: port@a { + reg = <0xa>; + + admaif10: endpoint { + remote-endpoint = <&xbar_admaif10>; + }; + }; + + admaif11_port: port@b { + reg = <0xb>; + + admaif11: endpoint { + remote-endpoint = <&xbar_admaif11>; + }; + }; + + admaif12_port: port@c { + reg = <0xc>; + + admaif12: endpoint { + remote-endpoint = <&xbar_admaif12>; + }; + }; + + admaif13_port: port@d { + reg = <0xd>; + + admaif13: endpoint { + remote-endpoint = <&xbar_admaif13>; + }; + }; + + admaif14_port: port@e { + reg = <0xe>; + + admaif14: endpoint { + remote-endpoint = <&xbar_admaif14>; + }; + }; + + admaif15_port: port@f { + reg = <0xf>; + + admaif15: endpoint { + remote-endpoint = <&xbar_admaif15>; + }; + }; + + admaif16_port: port@10 { + reg = <0x10>; + + admaif16: endpoint { + remote-endpoint = <&xbar_admaif16>; + }; + }; + + admaif17_port: port@11 { + reg = <0x11>; + + admaif17: endpoint { + remote-endpoint = <&xbar_admaif17>; + }; + }; + + admaif18_port: port@12 { + reg = <0x12>; + + admaif18: endpoint { + remote-endpoint = <&xbar_admaif18>; + }; + }; + + admaif19_port: port@13 { + reg = <0x13>; + + admaif19: endpoint { + remote-endpoint = <&xbar_admaif19>; + }; + }; + }; }; tegra_asrc: asrc@2910000 { @@ -551,7 +1591,1045 @@ "nvidia,tegra186-asrc"; reg = <0x0 0x2910000 0x0 0x2000>; sound-name-prefix = "ASRC1"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + asrc_in1_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in1_ep>; + }; + }; + + port@1 { + reg = <0x1>; + + asrc_in2_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in2_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + asrc_in3_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in3_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + asrc_in4_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in4_ep>; + }; + }; + + port@4 { + reg = <0x4>; + + asrc_in5_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in5_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + asrc_in6_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in6_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + asrc_in7_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in7_ep>; + }; + }; + + asrc_out1_port: port@7 { + reg = <0x7>; + + asrc_out1_ep: endpoint { + remote-endpoint = + <&xbar_asrc_out1_ep>; + }; + }; + + asrc_out2_port: port@8 { + reg = <0x8>; + + asrc_out2_ep: endpoint { + remote-endpoint = + <&xbar_asrc_out2_ep>; + }; + }; + + asrc_out3_port: port@9 { + reg = <0x9>; + + asrc_out3_ep: endpoint { + remote-endpoint = + <&xbar_asrc_out3_ep>; + }; + }; + + asrc_out4_port: port@a { + reg = <0xa>; + + asrc_out4_ep: endpoint { + remote-endpoint = + <&xbar_asrc_out4_ep>; + }; + }; + + asrc_out5_port: port@b { + reg = <0xb>; + + asrc_out5_ep: endpoint { + remote-endpoint = + <&xbar_asrc_out5_ep>; + }; + }; + + asrc_out6_port: port@c { + reg = <0xc>; + + asrc_out6_ep: endpoint { + remote-endpoint = + <&xbar_asrc_out6_ep>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + xbar_admaif0: endpoint { + remote-endpoint = <&admaif0>; + }; + }; + + port@1 { + reg = <0x1>; + + xbar_admaif1: endpoint { + remote-endpoint = <&admaif1>; + }; + }; + + port@2 { + reg = <0x2>; + + xbar_admaif2: endpoint { + remote-endpoint = <&admaif2>; + }; + }; + + port@3 { + reg = <0x3>; + + xbar_admaif3: endpoint { + remote-endpoint = <&admaif3>; + }; + }; + + port@4 { + reg = <0x4>; + + xbar_admaif4: endpoint { + remote-endpoint = <&admaif4>; + }; + }; + + port@5 { + reg = <0x5>; + + xbar_admaif5: endpoint { + remote-endpoint = <&admaif5>; + }; + }; + + port@6 { + reg = <0x6>; + + xbar_admaif6: endpoint { + remote-endpoint = <&admaif6>; + }; + }; + + port@7 { + reg = <0x7>; + + xbar_admaif7: endpoint { + remote-endpoint = <&admaif7>; + }; + }; + + port@8 { + reg = <0x8>; + + xbar_admaif8: endpoint { + remote-endpoint = <&admaif8>; + }; + }; + + port@9 { + reg = <0x9>; + + xbar_admaif9: endpoint { + remote-endpoint = <&admaif9>; + }; + }; + + port@a { + reg = <0xa>; + + xbar_admaif10: endpoint { + remote-endpoint = <&admaif10>; + }; + }; + + port@b { + reg = <0xb>; + + xbar_admaif11: endpoint { + remote-endpoint = <&admaif11>; + }; + }; + + port@c { + reg = <0xc>; + + xbar_admaif12: endpoint { + remote-endpoint = <&admaif12>; + }; + }; + + port@d { + reg = <0xd>; + + xbar_admaif13: endpoint { + remote-endpoint = <&admaif13>; + }; + }; + + port@e { + reg = <0xe>; + + xbar_admaif14: endpoint { + remote-endpoint = <&admaif14>; + }; + }; + + port@f { + reg = <0xf>; + + xbar_admaif15: endpoint { + remote-endpoint = <&admaif15>; + }; + }; + + port@10 { + reg = <0x10>; + + xbar_admaif16: endpoint { + remote-endpoint = <&admaif16>; + }; + }; + + port@11 { + reg = <0x11>; + + xbar_admaif17: endpoint { + remote-endpoint = <&admaif17>; + }; + }; + + port@12 { + reg = <0x12>; + + xbar_admaif18: endpoint { + remote-endpoint = <&admaif18>; + }; + }; + + port@13 { + reg = <0x13>; + + xbar_admaif19: endpoint { + remote-endpoint = <&admaif19>; + }; + }; + + xbar_i2s1_port: port@14 { + reg = <0x14>; + + xbar_i2s1: endpoint { + remote-endpoint = <&i2s1_cif>; + }; + }; + + xbar_i2s2_port: port@15 { + reg = <0x15>; + + xbar_i2s2: endpoint { + remote-endpoint = <&i2s2_cif>; + }; + }; + + xbar_i2s3_port: port@16 { + reg = <0x16>; + + xbar_i2s3: endpoint { + remote-endpoint = <&i2s3_cif>; + }; + }; + + xbar_i2s4_port: port@17 { + reg = <0x17>; + + xbar_i2s4: endpoint { + remote-endpoint = <&i2s4_cif>; + }; + }; + + xbar_i2s5_port: port@18 { + reg = <0x18>; + + xbar_i2s5: endpoint { + remote-endpoint = <&i2s5_cif>; + }; + }; + + xbar_i2s6_port: port@19 { + reg = <0x19>; + + xbar_i2s6: endpoint { + remote-endpoint = <&i2s6_cif>; + }; + }; + + xbar_dmic1_port: port@1a { + reg = <0x1a>; + + xbar_dmic1: endpoint { + remote-endpoint = <&dmic1_cif>; + }; + }; + + xbar_dmic2_port: port@1b { + reg = <0x1b>; + + xbar_dmic2: endpoint { + remote-endpoint = <&dmic2_cif>; + }; + }; + + xbar_dmic3_port: port@1c { + reg = <0x1c>; + + xbar_dmic3: endpoint { + remote-endpoint = <&dmic3_cif>; + }; + }; + + xbar_dmic4_port: port@1d { + reg = <0x1d>; + + xbar_dmic4: endpoint { + remote-endpoint = <&dmic4_cif>; + }; + }; + + xbar_dspk1_port: port@1e { + reg = <0x1e>; + + xbar_dspk1: endpoint { + remote-endpoint = <&dspk1_cif>; + }; + }; + + xbar_dspk2_port: port@1f { + reg = <0x1f>; + + xbar_dspk2: endpoint { + remote-endpoint = <&dspk2_cif>; + }; + }; + + xbar_sfc1_in_port: port@20 { + reg = <0x20>; + + xbar_sfc1_in: endpoint { + remote-endpoint = <&sfc1_cif_in>; + }; + }; + + port@21 { + reg = <0x21>; + + xbar_sfc1_out: endpoint { + remote-endpoint = <&sfc1_cif_out>; + }; + }; + + xbar_sfc2_in_port: port@22 { + reg = <0x22>; + + xbar_sfc2_in: endpoint { + remote-endpoint = <&sfc2_cif_in>; + }; + }; + + port@23 { + reg = <0x23>; + + xbar_sfc2_out: endpoint { + remote-endpoint = <&sfc2_cif_out>; + }; + }; + + xbar_sfc3_in_port: port@24 { + reg = <0x24>; + + xbar_sfc3_in: endpoint { + remote-endpoint = <&sfc3_cif_in>; + }; + }; + + port@25 { + reg = <0x25>; + + xbar_sfc3_out: endpoint { + remote-endpoint = <&sfc3_cif_out>; + }; + }; + + xbar_sfc4_in_port: port@26 { + reg = <0x26>; + + xbar_sfc4_in: endpoint { + remote-endpoint = <&sfc4_cif_in>; + }; + }; + + port@27 { + reg = <0x27>; + + xbar_sfc4_out: endpoint { + remote-endpoint = <&sfc4_cif_out>; + }; + }; + + xbar_mvc1_in_port: port@28 { + reg = <0x28>; + + xbar_mvc1_in: endpoint { + remote-endpoint = <&mvc1_cif_in>; + }; + }; + + port@29 { + reg = <0x29>; + + xbar_mvc1_out: endpoint { + remote-endpoint = <&mvc1_cif_out>; + }; + }; + + xbar_mvc2_in_port: port@2a { + reg = <0x2a>; + + xbar_mvc2_in: endpoint { + remote-endpoint = <&mvc2_cif_in>; + }; + }; + + port@2b { + reg = <0x2b>; + + xbar_mvc2_out: endpoint { + remote-endpoint = <&mvc2_cif_out>; + }; + }; + + xbar_amx1_in1_port: port@2c { + reg = <0x2c>; + + xbar_amx1_in1: endpoint { + remote-endpoint = <&amx1_in1>; + }; + }; + + xbar_amx1_in2_port: port@2d { + reg = <0x2d>; + + xbar_amx1_in2: endpoint { + remote-endpoint = <&amx1_in2>; + }; + }; + + xbar_amx1_in3_port: port@2e { + reg = <0x2e>; + + xbar_amx1_in3: endpoint { + remote-endpoint = <&amx1_in3>; + }; + }; + + xbar_amx1_in4_port: port@2f { + reg = <0x2f>; + + xbar_amx1_in4: endpoint { + remote-endpoint = <&amx1_in4>; + }; + }; + + port@30 { + reg = <0x30>; + + xbar_amx1_out: endpoint { + remote-endpoint = <&amx1_out>; + }; + }; + + xbar_amx2_in1_port: port@31 { + reg = <0x31>; + + xbar_amx2_in1: endpoint { + remote-endpoint = <&amx2_in1>; + }; + }; + + xbar_amx2_in2_port: port@32 { + reg = <0x32>; + + xbar_amx2_in2: endpoint { + remote-endpoint = <&amx2_in2>; + }; + }; + + xbar_amx2_in3_port: port@33 { + reg = <0x33>; + + xbar_amx2_in3: endpoint { + remote-endpoint = <&amx2_in3>; + }; + }; + + xbar_amx2_in4_port: port@34 { + reg = <0x34>; + + xbar_amx2_in4: endpoint { + remote-endpoint = <&amx2_in4>; + }; + }; + + port@35 { + reg = <0x35>; + + xbar_amx2_out: endpoint { + remote-endpoint = <&amx2_out>; + }; + }; + + xbar_amx3_in1_port: port@36 { + reg = <0x36>; + + xbar_amx3_in1: endpoint { + remote-endpoint = <&amx3_in1>; + }; + }; + + xbar_amx3_in2_port: port@37 { + reg = <0x37>; + + xbar_amx3_in2: endpoint { + remote-endpoint = <&amx3_in2>; + }; + }; + + xbar_amx3_in3_port: port@38 { + reg = <0x38>; + + xbar_amx3_in3: endpoint { + remote-endpoint = <&amx3_in3>; + }; + }; + + xbar_amx3_in4_port: port@39 { + reg = <0x39>; + + xbar_amx3_in4: endpoint { + remote-endpoint = <&amx3_in4>; + }; + }; + + port@3a { + reg = <0x3a>; + + xbar_amx3_out: endpoint { + remote-endpoint = <&amx3_out>; + }; + }; + + xbar_amx4_in1_port: port@3b { + reg = <0x3b>; + + xbar_amx4_in1: endpoint { + remote-endpoint = <&amx4_in1>; + }; + }; + + xbar_amx4_in2_port: port@3c { + reg = <0x3c>; + + xbar_amx4_in2: endpoint { + remote-endpoint = <&amx4_in2>; + }; + }; + + xbar_amx4_in3_port: port@3d { + reg = <0x3d>; + + xbar_amx4_in3: endpoint { + remote-endpoint = <&amx4_in3>; + }; + }; + + xbar_amx4_in4_port: port@3e { + reg = <0x3e>; + + xbar_amx4_in4: endpoint { + remote-endpoint = <&amx4_in4>; + }; + }; + + port@3f { + reg = <0x3f>; + + xbar_amx4_out: endpoint { + remote-endpoint = <&amx4_out>; + }; + }; + + xbar_adx1_in_port: port@40 { + reg = <0x40>; + + xbar_adx1_in: endpoint { + remote-endpoint = <&adx1_in>; + }; + }; + + port@41 { + reg = <0x41>; + + xbar_adx1_out1: endpoint { + remote-endpoint = <&adx1_out1>; + }; + }; + + port@42 { + reg = <0x42>; + + xbar_adx1_out2: endpoint { + remote-endpoint = <&adx1_out2>; + }; + }; + + port@43 { + reg = <0x43>; + + xbar_adx1_out3: endpoint { + remote-endpoint = <&adx1_out3>; + }; + }; + + port@44 { + reg = <0x44>; + + xbar_adx1_out4: endpoint { + remote-endpoint = <&adx1_out4>; + }; + }; + + xbar_adx2_in_port: port@45 { + reg = <0x45>; + + xbar_adx2_in: endpoint { + remote-endpoint = <&adx2_in>; + }; + }; + + port@46 { + reg = <0x46>; + + xbar_adx2_out1: endpoint { + remote-endpoint = <&adx2_out1>; + }; + }; + + port@47 { + reg = <0x47>; + + xbar_adx2_out2: endpoint { + remote-endpoint = <&adx2_out2>; + }; + }; + + port@48 { + reg = <0x48>; + + xbar_adx2_out3: endpoint { + remote-endpoint = <&adx2_out3>; + }; + }; + + port@49 { + reg = <0x49>; + + xbar_adx2_out4: endpoint { + remote-endpoint = <&adx2_out4>; + }; + }; + + xbar_adx3_in_port: port@4a { + reg = <0x4a>; + + xbar_adx3_in: endpoint { + remote-endpoint = <&adx3_in>; + }; + }; + + port@4b { + reg = <0x4b>; + + xbar_adx3_out1: endpoint { + remote-endpoint = <&adx3_out1>; + }; + }; + + port@4c { + reg = <0x4c>; + + xbar_adx3_out2: endpoint { + remote-endpoint = <&adx3_out2>; + }; + }; + + port@4d { + reg = <0x4d>; + + xbar_adx3_out3: endpoint { + remote-endpoint = <&adx3_out3>; + }; + }; + + port@4e { + reg = <0x4e>; + + xbar_adx3_out4: endpoint { + remote-endpoint = <&adx3_out4>; + }; + }; + + xbar_adx4_in_port: port@4f { + reg = <0x4f>; + + xbar_adx4_in: endpoint { + remote-endpoint = <&adx4_in>; + }; + }; + + port@50 { + reg = <0x50>; + + xbar_adx4_out1: endpoint { + remote-endpoint = <&adx4_out1>; + }; + }; + + port@51 { + reg = <0x51>; + + xbar_adx4_out2: endpoint { + remote-endpoint = <&adx4_out2>; + }; + }; + + port@52 { + reg = <0x52>; + + xbar_adx4_out3: endpoint { + remote-endpoint = <&adx4_out3>; + }; + }; + + port@53 { + reg = <0x53>; + + xbar_adx4_out4: endpoint { + remote-endpoint = <&adx4_out4>; + }; + }; + + xbar_mix_in1_port: port@54 { + reg = <0x54>; + + xbar_mix_in1: endpoint { + remote-endpoint = <&mix_in1>; + }; + }; + + xbar_mix_in2_port: port@55 { + reg = <0x55>; + + xbar_mix_in2: endpoint { + remote-endpoint = <&mix_in2>; + }; + }; + + xbar_mix_in3_port: port@56 { + reg = <0x56>; + + xbar_mix_in3: endpoint { + remote-endpoint = <&mix_in3>; + }; + }; + + xbar_mix_in4_port: port@57 { + reg = <0x57>; + + xbar_mix_in4: endpoint { + remote-endpoint = <&mix_in4>; + }; + }; + + xbar_mix_in5_port: port@58 { + reg = <0x58>; + + xbar_mix_in5: endpoint { + remote-endpoint = <&mix_in5>; + }; + }; + + xbar_mix_in6_port: port@59 { + reg = <0x59>; + + xbar_mix_in6: endpoint { + remote-endpoint = <&mix_in6>; + }; + }; + + xbar_mix_in7_port: port@5a { + reg = <0x5a>; + + xbar_mix_in7: endpoint { + remote-endpoint = <&mix_in7>; + }; + }; + + xbar_mix_in8_port: port@5b { + reg = <0x5b>; + + xbar_mix_in8: endpoint { + remote-endpoint = <&mix_in8>; + }; + }; + + xbar_mix_in9_port: port@5c { + reg = <0x5c>; + + xbar_mix_in9: endpoint { + remote-endpoint = <&mix_in9>; + }; + }; + + xbar_mix_in10_port: port@5d { + reg = <0x5d>; + + xbar_mix_in10: endpoint { + remote-endpoint = <&mix_in10>; + }; + }; + + port@5e { + reg = <0x5e>; + + xbar_mix_out1: endpoint { + remote-endpoint = <&mix_out1>; + }; + }; + + port@5f { + reg = <0x5f>; + + xbar_mix_out2: endpoint { + remote-endpoint = <&mix_out2>; + }; + }; + + port@60 { + reg = <0x60>; + + xbar_mix_out3: endpoint { + remote-endpoint = <&mix_out3>; + }; + }; + + port@61 { + reg = <0x61>; + + xbar_mix_out4: endpoint { + remote-endpoint = <&mix_out4>; + }; + }; + + port@62 { + reg = <0x62>; + + xbar_mix_out5: endpoint { + remote-endpoint = <&mix_out5>; + }; + }; + + xbar_asrc_in1_port: port@63 { + reg = <0x63>; + + xbar_asrc_in1_ep: endpoint { + remote-endpoint = <&asrc_in1_ep>; + }; + }; + + port@64 { + reg = <0x64>; + + xbar_asrc_out1_ep: endpoint { + remote-endpoint = <&asrc_out1_ep>; + }; + }; + + xbar_asrc_in2_port: port@65 { + reg = <0x65>; + + xbar_asrc_in2_ep: endpoint { + remote-endpoint = <&asrc_in2_ep>; + }; + }; + + port@66 { + reg = <0x66>; + + xbar_asrc_out2_ep: endpoint { + remote-endpoint = <&asrc_out2_ep>; + }; + }; + + xbar_asrc_in3_port: port@67 { + reg = <0x67>; + + xbar_asrc_in3_ep: endpoint { + remote-endpoint = <&asrc_in3_ep>; + }; + }; + + port@68 { + reg = <0x68>; + + xbar_asrc_out3_ep: endpoint { + remote-endpoint = <&asrc_out3_ep>; + }; + }; + + xbar_asrc_in4_port: port@69 { + reg = <0x69>; + + xbar_asrc_in4_ep: endpoint { + remote-endpoint = <&asrc_in4_ep>; + }; + }; + + port@6a { + reg = <0x6a>; + + xbar_asrc_out4_ep: endpoint { + remote-endpoint = <&asrc_out4_ep>; + }; + }; + + xbar_asrc_in5_port: port@6b { + reg = <0x6b>; + + xbar_asrc_in5_ep: endpoint { + remote-endpoint = <&asrc_in5_ep>; + }; + }; + + port@6c { + reg = <0x6c>; + + xbar_asrc_out5_ep: endpoint { + remote-endpoint = <&asrc_out5_ep>; + }; + }; + + xbar_asrc_in6_port: port@6d { + reg = <0x6d>; + + xbar_asrc_in6_ep: endpoint { + remote-endpoint = <&asrc_in6_ep>; + }; + }; + + port@6e { + reg = <0x6e>; + + xbar_asrc_out6_ep: endpoint { + remote-endpoint = <&asrc_out6_ep>; + }; + }; + + xbar_asrc_in7_port: port@6f { + reg = <0x6f>; + + xbar_asrc_in7_ep: endpoint { + remote-endpoint = <&asrc_in7_ep>; + }; + }; + + xbar_ope1_in_port: port@70 { + reg = <0x70>; + + xbar_ope1_in_ep: endpoint { + remote-endpoint = <&ope1_cif_in_ep>; + }; + }; + + port@71 { + reg = <0x71>; + + xbar_ope1_out_ep: endpoint { + remote-endpoint = <&ope1_cif_out_ep>; + }; + }; }; }; @@ -1461,6 +3539,14 @@ iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; status = "disabled"; + + snps,axi-config = <&mgbe0_axi_setup>; + + mgbe0_axi_setup: stmmac-axi-config { + snps,blen = <256 128 64 32>; + snps,rd_osr_lmt = <63>; + snps,wr_osr_lmt = <63>; + }; }; ethernet@6900000 { @@ -1495,6 +3581,14 @@ iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>; power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>; status = "disabled"; + + snps,axi-config = <&mgbe1_axi_setup>; + + mgbe1_axi_setup: stmmac-axi-config { + snps,blen = <256 128 64 32>; + snps,rd_osr_lmt = <63>; + snps,wr_osr_lmt = <63>; + }; }; ethernet@6a00000 { @@ -1529,6 +3623,14 @@ iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>; power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; status = "disabled"; + + snps,axi-config = <&mgbe2_axi_setup>; + + mgbe2_axi_setup: stmmac-axi-config { + snps,blen = <256 128 64 32>; + snps,rd_osr_lmt = <63>; + snps,wr_osr_lmt = <63>; + }; }; ethernet@6b00000 { diff --git a/src/arm64/qcom/apq8016-sbc-d3-camera-mezzanine.dts b/src/arm64/qcom/apq8016-sbc-d3-camera-mezzanine.dts index c08b4be5cc7..f9cbf8c1d68 100644 --- a/src/arm64/qcom/apq8016-sbc-d3-camera-mezzanine.dts +++ b/src/arm64/qcom/apq8016-sbc-d3-camera-mezzanine.dts @@ -9,7 +9,7 @@ #include "apq8016-sbc.dts" / { - camera_vdddo_1v8: camera-vdddo-1v8 { + camera_vdddo_1v8: regulator-camera-vdddo { compatible = "regulator-fixed"; regulator-name = "camera_vdddo"; regulator-min-microvolt = <1800000>; @@ -17,7 +17,7 @@ regulator-always-on; }; - camera_vdda_2v8: camera-vdda-2v8 { + camera_vdda_2v8: regulator-camera-vdda { compatible = "regulator-fixed"; regulator-name = "camera_vdda"; regulator-min-microvolt = <2800000>; @@ -25,7 +25,7 @@ regulator-always-on; }; - camera_vddd_1v5: camera-vddd-1v5 { + camera_vddd_1v5: regulator-camera-vddd { compatible = "regulator-fixed"; regulator-name = "camera_vddd"; regulator-min-microvolt = <1500000>; @@ -53,7 +53,7 @@ }; &cci_i2c0 { - camera_rear@3b { + camera@3b { compatible = "ovti,ov5640"; reg = <0x3b>; diff --git a/src/arm64/qcom/ipq5332.dtsi b/src/arm64/qcom/ipq5332.dtsi index 42e2e48b2bc..770d9c2fb45 100644 --- a/src/arm64/qcom/ipq5332.dtsi +++ b/src/arm64/qcom/ipq5332.dtsi @@ -320,8 +320,12 @@ compatible = "qcom,ipq5332-dwc3", "qcom,dwc3"; reg = <0x08af8800 0x400>; - interrupts = ; - interrupt-names = "hs_phy_irq"; + interrupts = , + , + ; + interrupt-names = "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq"; clocks = <&gcc GCC_USB0_MASTER_CLK>, <&gcc GCC_SNOC_USB_CLK>, diff --git a/src/arm64/qcom/ipq6018.dtsi b/src/arm64/qcom/ipq6018.dtsi index 61c8fd49c96..4e29adea570 100644 --- a/src/arm64/qcom/ipq6018.dtsi +++ b/src/arm64/qcom/ipq6018.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include / { #address-cells = <2>; @@ -43,6 +44,7 @@ clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; cpu-supply = <&ipq6018_s2>; + #cooling-cells = <2>; }; CPU1: cpu@1 { @@ -55,6 +57,7 @@ clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; cpu-supply = <&ipq6018_s2>; + #cooling-cells = <2>; }; CPU2: cpu@2 { @@ -67,6 +70,7 @@ clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; cpu-supply = <&ipq6018_s2>; + #cooling-cells = <2>; }; CPU3: cpu@3 { @@ -79,6 +83,7 @@ clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; cpu-supply = <&ipq6018_s2>; + #cooling-cells = <2>; }; L2_0: l2-cache { @@ -330,6 +335,16 @@ clock-names = "core"; }; + tsens: thermal-sensor@4a9000 { + compatible = "qcom,ipq6018-tsens", "qcom,ipq8074-tsens"; + reg = <0x0 0x004a9000 0x0 0x1000>, + <0x0 0x004a8000 0x0 0x1000>; + interrupts = ; + interrupt-names = "combined"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + cryptobam: dma-controller@704000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0 0x00704000 0x0 0x20000>; @@ -418,6 +433,12 @@ <&gcc GCC_USB1_MOCK_UTMI_CLK>; assigned-clock-rates = <133330000>, <24000000>; + + interrupts = , + ; + interrupt-names = "pwr_event", + "qusb2_phy"; + resets = <&gcc GCC_USB1_BCR>; status = "disabled"; @@ -578,6 +599,21 @@ status = "disabled"; }; + blsp1_i2c6: i2c@78ba000 { + compatible = "qcom,i2c-qup-v2.2.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x078ba000 0x0 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + dmas = <&blsp_dma 22>, <&blsp_dma 23>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + qpic_bam: dma-controller@7984000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0 0x07984000 0x0 0x1a000>; @@ -630,6 +666,13 @@ <133330000>, <24000000>; + interrupts = , + , + ; + interrupt-names = "pwr_event", + "qusb2_phy", + "ss_phy_irq"; + resets = <&gcc GCC_USB0_BCR>; status = "disabled"; @@ -867,6 +910,122 @@ }; }; + thermal-zones { + nss-top-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 4>; + + trips { + nss-top-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nss-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 5>; + + trips { + nss-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + wcss-phya0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 7>; + + trips { + wcss-phya0-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + wcss-phya1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 8>; + + trips { + wcss-phya1-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 13>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + + cpu_alert: cpu-passive { + temperature = <110000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + lpass-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 14>; + + trips { + lpass-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ddrss-top-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 15>; + + trips { + ddrss-top-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , diff --git a/src/arm64/qcom/ipq8074.dtsi b/src/arm64/qcom/ipq8074.dtsi index 26441447c86..e5b89753aa5 100644 --- a/src/arm64/qcom/ipq8074.dtsi +++ b/src/arm64/qcom/ipq8074.dtsi @@ -252,6 +252,8 @@ clocks = <&gcc GCC_MDIO_AHB_CLK>; clock-names = "gcc_mdio_ahb_clk"; + clock-frequency = <6250000>; + status = "disabled"; }; @@ -627,6 +629,13 @@ <133330000>, <19200000>; + interrupts = , + , + ; + interrupt-names = "pwr_event", + "qusb2_phy", + "ss_phy_irq"; + power-domains = <&gcc USB0_GDSC>; resets = <&gcc GCC_USB0_BCR>; @@ -669,6 +678,13 @@ <133330000>, <19200000>; + interrupts = , + , + ; + interrupt-names = "pwr_event", + "qusb2_phy", + "ss_phy_irq"; + power-domains = <&gcc USB1_GDSC>; resets = <&gcc GCC_USB1_BCR>; diff --git a/src/arm64/qcom/ipq9574.dtsi b/src/arm64/qcom/ipq9574.dtsi index 5f83ee42a71..7f2e5cbf3bb 100644 --- a/src/arm64/qcom/ipq9574.dtsi +++ b/src/arm64/qcom/ipq9574.dtsi @@ -321,8 +321,10 @@ sdhc_1: mmc@7804000 { compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; - reg = <0x07804000 0x1000>, <0x07805000 0x1000>; - reg-names = "hc", "cqhci"; + reg = <0x07804000 0x1000>, + <0x07805000 0x1000>, + <0x07808000 0x2000>; + reg-names = "hc", "cqhci", "ice"; interrupts = , ; @@ -330,9 +332,11 @@ clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, - <&xo_board_clk>; - clock-names = "iface", "core", "xo"; + <&xo_board_clk>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface", "core", "xo", "ice"; non-removable; + supports-cqe; status = "disabled"; }; diff --git a/src/arm64/qcom/msm8216-samsung-fortuna3g.dts b/src/arm64/qcom/msm8216-samsung-fortuna3g.dts new file mode 100644 index 00000000000..366914be7d5 --- /dev/null +++ b/src/arm64/qcom/msm8216-samsung-fortuna3g.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-samsung-fortuna-common.dtsi" + +/ { + model = "Samsung Galaxy Grand Prime (SM-G530H)"; + compatible = "samsung,fortuna3g", "qcom,msm8916"; + chassis-type = "handset"; +}; diff --git a/src/arm64/qcom/msm8916-samsung-fortuna-common.dtsi b/src/arm64/qcom/msm8916-samsung-fortuna-common.dtsi new file mode 100644 index 00000000000..c2800ad2dd5 --- /dev/null +++ b/src/arm64/qcom/msm8916-samsung-fortuna-common.dtsi @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "msm8916-pm8916.dtsi" +#include "msm8916-modem-qdsp6.dtsi" + +#include +#include +#include + +/ { + aliases { + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ + serial0 = &blsp_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + reserved-memory { + /* Additional memory used by Samsung firmware modifications */ + tz-apps@85a00000 { + reg = <0x0 0x85a00000 0x0 0x600000>; + no-map; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + label = "GPIO Buttons"; + + button-volume-up { + label = "Volume Up"; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + button-home { + label = "Home"; + gpios = <&tlmm 109 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + haptic { + compatible = "regulator-haptic"; + haptic-supply = <®_motor_vdd>; + min-microvolt = <3300000>; + max-microvolt = <3300000>; + }; + + reg_motor_vdd: regulator-motor-vdd { + compatible = "regulator-fixed"; + regulator-name = "motor_vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 72 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&motor_en_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_i2c1 { + status = "okay"; + + muic: extcon@25 { + compatible = "siliconmitus,sm5502-muic"; + reg = <0x25>; + interrupts-extended = <&tlmm 12 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&muic_int_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_i2c4 { + status = "okay"; + + fuel-gauge@35 { + compatible = "richtek,rt5033-battery"; + reg = <0x35>; + + interrupts-extended = <&tlmm 121 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&fg_alert_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_uart2 { + status = "okay"; +}; + +&mpss_mem { + reg = <0x0 0x86800000 0x0 0x5000000>; +}; + +&pm8916_resin { + linux,code = ; + status = "okay"; +}; + +&pm8916_rpm_regulators { + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + +&sdhc_1 { + status = "okay"; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; + pinctrl-names = "default", "sleep"; + + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&sound { + model = "msm8916-1mic"; + audio-routing = + "AMIC1", "MIC BIAS External1", + "AMIC2", "MIC BIAS Internal2", + "AMIC3", "MIC BIAS External1"; +}; + +&usb { + extcon = <&muic>, <&muic>; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&muic>; +}; + +&venus { + status = "okay"; +}; + +&venus_mem { + status = "okay"; +}; + +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + +&wcnss_mem { + status = "okay"; +}; + +&tlmm { + fg_alert_default: fg-alert-default-state { + pins = "gpio121"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + gpio_keys_default: gpio-keys-default-state { + pins = "gpio107", "gpio109"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + motor_en_default: motor-en-default-state { + pins = "gpio72"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + muic_int_default: muic-int-default-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; diff --git a/src/arm64/qcom/msm8916-samsung-gprimeltecan.dts b/src/arm64/qcom/msm8916-samsung-gprimeltecan.dts new file mode 100644 index 00000000000..9d65fa58ba9 --- /dev/null +++ b/src/arm64/qcom/msm8916-samsung-gprimeltecan.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-samsung-fortuna-common.dtsi" + +/ { + model = "Samsung Galaxy Grand Prime (SM-G530W)"; + compatible = "samsung,gprimeltecan", "qcom,msm8916"; + chassis-type = "handset"; + + reserved-memory { + /* Firmware for gprimeltecan needs more space */ + /delete-node/ tz-apps@85a00000; + + /* Additional memory used by Samsung firmware modifications */ + tz-apps@85500000 { + reg = <0x0 0x85500000 0x0 0xb00000>; + no-map; + }; + }; +}; + +&mpss_mem { + /* Firmware for gprimeltecan needs more space */ + reg = <0x0 0x86800000 0x0 0x5400000>; +}; diff --git a/src/arm64/qcom/msm8916-samsung-grandprimelte.dts b/src/arm64/qcom/msm8916-samsung-grandprimelte.dts new file mode 100644 index 00000000000..a66ce4b1354 --- /dev/null +++ b/src/arm64/qcom/msm8916-samsung-grandprimelte.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-samsung-fortuna-common.dtsi" + +/ { + model = "Samsung Galaxy Grand Prime (SM-G530FZ)"; + compatible = "samsung,grandprimelte", "qcom,msm8916"; + chassis-type = "handset"; +}; + +&mpss_mem { + /* Firmware for grandprimelte needs more space */ + reg = <0x0 0x86800000 0x0 0x5400000>; +}; diff --git a/src/arm64/qcom/msm8916-samsung-rossa-common.dtsi b/src/arm64/qcom/msm8916-samsung-rossa-common.dtsi new file mode 100644 index 00000000000..42843771ae2 --- /dev/null +++ b/src/arm64/qcom/msm8916-samsung-rossa-common.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "msm8916-samsung-fortuna-common.dtsi" + +/* SM5504 MUIC instead of SM5502 */ +/delete-node/ &muic; + +&blsp_i2c1 { + muic: extcon@14 { + compatible = "siliconmitus,sm5504-muic"; + reg = <0x14>; + interrupts-extended = <&tlmm 12 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&muic_int_default>; + pinctrl-names = "default"; + }; +}; diff --git a/src/arm64/qcom/msm8916-samsung-rossa.dts b/src/arm64/qcom/msm8916-samsung-rossa.dts new file mode 100644 index 00000000000..ebaa13c6b01 --- /dev/null +++ b/src/arm64/qcom/msm8916-samsung-rossa.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-samsung-rossa-common.dtsi" + +/ { + model = "Samsung Galaxy Core Prime LTE"; + compatible = "samsung,rossa", "qcom,msm8916"; + chassis-type = "handset"; +}; + +&mpss_mem { + /* Firmware for rossa needs more space */ + reg = <0x0 0x86800000 0x0 0x5800000>; +}; diff --git a/src/arm64/qcom/msm8916.dtsi b/src/arm64/qcom/msm8916.dtsi index e423c57ddd4..cedff4166bf 100644 --- a/src/arm64/qcom/msm8916.dtsi +++ b/src/arm64/qcom/msm8916.dtsi @@ -1785,6 +1785,8 @@ power-domains = <&gcc OXILI_GDSC>; operating-points-v2 = <&gpu_opp_table>; iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; + #cooling-cells = <2>; + status = "disabled"; gpu_opp_table: opp-table { @@ -2688,6 +2690,13 @@ thermal-sensors = <&tsens 2>; + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { gpu_alert0: trip-point0 { temperature = <75000>; diff --git a/src/arm64/qcom/msm8939.dtsi b/src/arm64/qcom/msm8939.dtsi index 82d85ff6104..dd45975682b 100644 --- a/src/arm64/qcom/msm8939.dtsi +++ b/src/arm64/qcom/msm8939.dtsi @@ -1427,6 +1427,8 @@ power-domains = <&gcc OXILI_GDSC>; operating-points-v2 = <&opp_table>; iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; + #cooling-cells = <2>; + status = "disabled"; opp_table: opp-table { @@ -2456,6 +2458,13 @@ thermal-sensors = <&tsens 3>; + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { gpu_alert0: trip-point0 { temperature = <75000>; @@ -2463,7 +2472,7 @@ type = "passive"; }; - gpu_crit: gpu_crit { + gpu_crit: gpu-crit { temperature = <95000>; hysteresis = <2000>; type = "critical"; diff --git a/src/arm64/qcom/msm8953.dtsi b/src/arm64/qcom/msm8953.dtsi index ad2f8cf9c96..f1011bb641c 100644 --- a/src/arm64/qcom/msm8953.dtsi +++ b/src/arm64/qcom/msm8953.dtsi @@ -859,6 +859,8 @@ "vsync", "core"; + resets = <&gcc GCC_MDSS_BCR>; + #address-cells = <1>; #size-cells = <1>; ranges; @@ -1044,6 +1046,125 @@ }; }; + gpu: gpu@1c00000 { + compatible = "qcom,adreno-506.0", "qcom,adreno"; + reg = <0x01c00000 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = ; + + clocks = <&gcc GCC_OXILI_GFX3D_CLK>, + <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_BIMC_GPU_CLK>, + <&gcc GCC_OXILI_TIMER_CLK>, + <&gcc GCC_OXILI_AON_CLK>; + clock-names = "core", + "iface", + "mem_iface", + "alt_mem_iface", + "rbbmtimer", + "alwayson"; + power-domains = <&gcc OXILI_GX_GDSC>; + + iommus = <&gpu_iommu 0>; + operating-points-v2 = <&gpu_opp_table>; + + #cooling-cells = <2>; + + status = "disabled"; + + zap-shader { + memory-region = <&zap_shader_region>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_min_svs>; + }; + + opp-133300000 { + opp-hz = /bits/ 64 <133300000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_min_svs>; + }; + + opp-216000000 { + opp-hz = /bits/ 64 <216000000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-510000000 { + opp-hz = /bits/ 64 <510000000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_nom>; + }; + + opp-560000000 { + opp-hz = /bits/ 64 <560000000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_nom_plus>; + }; + + /* + * This opp is only available on msm8953 and + * sdm632, the max for sdm450 is 600MHz. + */ + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_turbo>; + }; + }; + }; + + gpu_iommu: iommu@1c48000 { + compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v2"; + ranges = <0 0x01c48000 0x8000>; + + clocks = <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_BIMC_GFX_CLK>; + clock-names = "iface", "bus"; + + power-domains = <&gcc OXILI_CX_GDSC>; + + qcom,iommu-secure-id = <18>; + + #address-cells = <1>; + #iommu-cells = <1>; + #size-cells = <1>; + + /* gfx3d_user */ + iommu-ctx@0 { + compatible = "qcom,msm-iommu-v2-ns"; + reg = <0x0000 0x1000>; + interrupts = ; + }; + + /* gfx3d_secure */ + iommu-ctx@2000 { + compatible = "qcom,msm-iommu-v2-sec"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + }; + apps_iommu: iommu@1e20000 { compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1"; ranges = <0 0x01e20000 0x20000>; @@ -1160,9 +1281,12 @@ #size-cells = <1>; ranges; - interrupts = , + interrupts = , + , ; - interrupt-names = "hs_phy_irq", "ss_phy_irq"; + interrupt-names = "pwr_event", + "qusb2_phy", + "ss_phy_irq"; clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, <&gcc GCC_USB30_MASTER_CLK>, @@ -2012,6 +2136,33 @@ }; }; }; + + gpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens0 15>; + + trips { + gpu_alert: trip-point0 { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_crit: crit { + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_alert>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; }; timer { diff --git a/src/arm64/qcom/msm8994-msft-lumia-octagon.dtsi b/src/arm64/qcom/msm8994-msft-lumia-octagon.dtsi index cbc84459a5a..10cd244dea4 100644 --- a/src/arm64/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/src/arm64/qcom/msm8994-msft-lumia-octagon.dtsi @@ -377,7 +377,7 @@ &blsp2_i2c1 { status = "okay"; - sideinteraction: ad7147_captouch@2c { + sideinteraction: touch@2c { compatible = "ad,ad7147_captouch"; reg = <0x2c>; diff --git a/src/arm64/qcom/msm8994-sony-xperia-kitakami.dtsi b/src/arm64/qcom/msm8994-sony-xperia-kitakami.dtsi index 9dbde79f26a..0163d41f95f 100644 --- a/src/arm64/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/src/arm64/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -79,7 +79,7 @@ pmsg-size = <0x80000>; }; - fb_region: fb_region@40000000 { + fb_region: fb@40000000 { reg = <0 0x40000000 0 0x1000000>; no-map; }; diff --git a/src/arm64/qcom/msm8994.dtsi b/src/arm64/qcom/msm8994.dtsi index 8295bf1b219..695e541832a 100644 --- a/src/arm64/qcom/msm8994.dtsi +++ b/src/arm64/qcom/msm8994.dtsi @@ -233,7 +233,7 @@ #size-cells = <2>; ranges; - dfps_data_mem: dfps_data_mem@3400000 { + dfps_data_mem: dfps-data@3400000 { reg = <0 0x03400000 0 0x1000>; no-map; }; @@ -243,7 +243,7 @@ no-map; }; - smem_mem: smem_region@6a00000 { + smem_mem: smem@6a00000 { reg = <0 0x06a00000 0 0x200000>; no-map; }; diff --git a/src/arm64/qcom/msm8996.dtsi b/src/arm64/qcom/msm8996.dtsi index ee6f87c828a..1601e46549e 100644 --- a/src/arm64/qcom/msm8996.dtsi +++ b/src/arm64/qcom/msm8996.dtsi @@ -756,12 +756,12 @@ #address-cells = <1>; #size-cells = <1>; - qusb2p_hstx_trim: hstx_trim@24e { + qusb2p_hstx_trim: hstx-trim@24e { reg = <0x24e 0x2>; bits = <5 4>; }; - qusb2s_hstx_trim: hstx_trim@24f { + qusb2s_hstx_trim: hstx-trim@24f { reg = <0x24f 0x1>; bits = <1 4>; }; @@ -2077,7 +2077,7 @@ <0 0>, <0 0>, <150000000 300000000>, - <0 0>, + <75000000 150000000>, <0 0>, <0 0>, <0 0>, @@ -2096,8 +2096,8 @@ compatible = "qcom,msm8996-qmp-ufs-phy"; reg = <0x00627000 0x1000>; - clocks = <&gcc GCC_UFS_CLKREF_CLK>; - clock-names = "ref"; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, <&gcc GCC_UFS_CLKREF_CLK>; + clock-names = "ref", "qref"; resets = <&ufshc 0>; reset-names = "ufsphy"; @@ -3381,8 +3381,12 @@ #size-cells = <1>; ranges; - interrupts = ; - interrupt-names = "hs_phy_irq"; + interrupts = , + , + ; + interrupt-names = "pwr_event", + "qusb2_phy", + "hs_phy_irq"; clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, <&gcc GCC_USB20_MASTER_CLK>, diff --git a/src/arm64/qcom/msm8998.dtsi b/src/arm64/qcom/msm8998.dtsi index 2793cc22d38..4dfe2d09ac2 100644 --- a/src/arm64/qcom/msm8998.dtsi +++ b/src/arm64/qcom/msm8998.dtsi @@ -1047,12 +1047,12 @@ compatible = "qcom,msm8998-qmp-ufs-phy"; reg = <0x01da7000 0x1000>; - clock-names = - "ref", - "ref_aux"; - clocks = - <&gcc GCC_UFS_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_AUX_CLK>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK1>, + <&gcc GCC_UFS_PHY_AUX_CLK>, + <&gcc GCC_UFS_CLKREF_CLK>; + clock-names = "ref", + "ref_aux", + "qref"; reset-names = "ufsphy"; resets = <&ufshc 0>; @@ -1072,6 +1072,11 @@ reg = <0x01f60000 0x20000>; }; + tcsr_regs_2: syscon@1fc0000 { + compatible = "qcom,msm8998-tcsr", "syscon"; + reg = <0x01fc0000 0x26000>; + }; + tlmm: pinctrl@3400000 { compatible = "qcom,msm8998-pinctrl"; reg = <0x03400000 0xc00000>; @@ -2132,9 +2137,12 @@ <&gcc GCC_USB30_MASTER_CLK>; assigned-clock-rates = <19200000>, <120000000>; - interrupts = , + interrupts = , + , ; - interrupt-names = "hs_phy_irq", "ss_phy_irq"; + interrupt-names = "pwr_event", + "qusb2_phy", + "ss_phy_irq"; power-domains = <&gcc USB_30_GDSC>; @@ -2174,6 +2182,8 @@ reset-names = "phy", "phy_phy"; + qcom,tcsr-reg = <&tcsr_regs_2 0xb244>; + status = "disabled"; }; diff --git a/src/arm64/qcom/pm2250.dtsi b/src/arm64/qcom/pm4125.dtsi similarity index 56% rename from src/arm64/qcom/pm2250.dtsi rename to src/arm64/qcom/pm4125.dtsi index 5f1d15db5c9..cf8c822e80c 100644 --- a/src/arm64/qcom/pm2250.dtsi +++ b/src/arm64/qcom/pm4125.dtsi @@ -19,7 +19,7 @@ compatible = "qcom,pm8916-pon"; reg = <0x800>; - pm2250_pwrkey: pwrkey { + pm4125_pwrkey: pwrkey { compatible = "qcom,pm8941-pwrkey"; interrupts-extended = <&spmi_bus 0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; linux,code = ; @@ -27,7 +27,7 @@ bias-pull-up; }; - pm2250_resin: resin { + pm4125_resin: resin { compatible = "qcom,pm8941-resin"; interrupts-extended = <&spmi_bus 0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; debounce = <15625>; @@ -36,6 +36,36 @@ }; }; + pm4125_vbus: usb-vbus-regulator@1100 { + compatible = "qcom,pm4125-vbus-reg", "qcom,pm8150b-vbus-reg"; + reg = <0x1100>; + status = "disabled"; + }; + + pm4125_typec: typec@1500 { + compatible = "qcom,pm4125-typec", "qcom,pmi632-typec"; + reg = <0x1500>; + interrupts = <0x0 0x15 0x00 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x01 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x02 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x03 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x04 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x05 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x06 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x07 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "or-rid-detect-change", + "vpd-detect", + "cc-state-change", + "vconn-oc", + "vbus-change", + "attach-detach", + "legacy-cable-detect", + "try-snk-src-detect"; + vdd-vbus-supply = <&pm4125_vbus>; + + status = "disabled"; + }; + rtc@6000 { compatible = "qcom,pm8941-rtc"; reg = <0x6000>, <0x6100>; @@ -43,11 +73,11 @@ interrupts-extended = <&spmi_bus 0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; }; - pm2250_gpios: gpio@c000 { + pm4125_gpios: gpio@c000 { compatible = "qcom,pm2250-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; - gpio-ranges = <&pm2250_gpios 0 0 10>; + gpio-ranges = <&pm4125_gpios 0 0 10>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/src/arm64/qcom/pm6150.dtsi b/src/arm64/qcom/pm6150.dtsi index ddbaf7280b0..11158c2bd52 100644 --- a/src/arm64/qcom/pm6150.dtsi +++ b/src/arm64/qcom/pm6150.dtsi @@ -63,6 +63,52 @@ }; }; + pm6150_vbus: usb-vbus-regulator@1100 { + compatible = "qcom,pm6150-vbus-reg, + qcom,pm8150b-vbus-reg"; + reg = <0x1100>; + status = "disabled"; + }; + + pm6150_typec: typec@1500 { + compatible = "qcom,pm6150-typec, + qcom,pm8150b-typec"; + reg = <0x1500>, <0x1700>; + interrupts = <0x0 0x15 0x00 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x01 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x02 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x03 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x04 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x05 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x06 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x07 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x00 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x01 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x02 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x03 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x04 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x05 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x06 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x07 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "or-rid-detect-change", + "vpd-detect", + "cc-state-change", + "vconn-oc", + "vbus-change", + "attach-detach", + "legacy-cable-detect", + "try-snk-src-detect", + "sig-tx", + "sig-rx", + "msg-tx", + "msg-rx", + "msg-tx-failed", + "msg-tx-discarded", + "msg-rx-discarded", + "fr-swap"; + status = "disabled"; + }; + pm6150_temp: temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; reg = <0x2400>; diff --git a/src/arm64/qcom/pmi632.dtsi b/src/arm64/qcom/pmi632.dtsi index 4eb79e0ce40..94d53b1cf6c 100644 --- a/src/arm64/qcom/pmi632.dtsi +++ b/src/arm64/qcom/pmi632.dtsi @@ -45,6 +45,36 @@ #address-cells = <1>; #size-cells = <0>; + pmi632_vbus: usb-vbus-regulator@1100 { + compatible = "qcom,pmi632-vbus-reg", "qcom,pm8150b-vbus-reg"; + reg = <0x1100>; + status = "disabled"; + }; + + pmi632_typec: typec@1500 { + compatible = "qcom,pmi632-typec"; + reg = <0x1500>; + interrupts = <0x2 0x15 0x00 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x01 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x15 0x02 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x03 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x15 0x04 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x05 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x06 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x15 0x07 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "or-rid-detect-change", + "vpd-detect", + "cc-state-change", + "vconn-oc", + "vbus-change", + "attach-detach", + "legacy-cable-detect", + "try-snk-src-detect"; + vdd-vbus-supply = <&pmi632_vbus>; + + status = "disabled"; + }; + pmi632_temp: temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; reg = <0x2400>; @@ -127,6 +157,11 @@ status = "disabled"; }; + pmi632_pbs_client3: pbs@7400 { + compatible = "qcom,pmi632-pbs", "qcom,pbs"; + reg = <0x7400>; + }; + pmi632_sdam_7: nvram@b600 { compatible = "qcom,spmi-sdam"; reg = <0xb600>; @@ -155,6 +190,10 @@ pmi632_lpg: pwm { compatible = "qcom,pmi632-lpg"; + nvmem = <&pmi632_sdam_7>; + nvmem-names = "lpg_chan_sdam"; + qcom,pbs = <&pmi632_pbs_client3>; + #address-cells = <1>; #size-cells = <0>; #pwm-cells = <2>; diff --git a/src/arm64/qcom/qcm2290.dtsi b/src/arm64/qcom/qcm2290.dtsi index 0911fb08ed6..89beac833d4 100644 --- a/src/arm64/qcom/qcm2290.dtsi +++ b/src/arm64/qcom/qcm2290.dtsi @@ -442,6 +442,11 @@ #hwlock-cells = <1>; }; + tcsr_regs: syscon@3c0000 { + compatible = "qcom,qcm2290-tcsr", "syscon"; + reg = <0x0 0x003c0000 0x0 0x40000>; + }; + tlmm: pinctrl@500000 { compatible = "qcom,qcm2290-tlmm"; reg = <0x0 0x00500000 0x0 0x300000>; @@ -690,6 +695,8 @@ #phy-cells = <0>; + qcom,tcsr-reg = <&tcsr_regs 0xb244>; + status = "disabled"; }; diff --git a/src/arm64/qcom/qcm6490-fairphone-fp5.dts b/src/arm64/qcom/qcm6490-fairphone-fp5.dts index 176898c9dbb..4ff9fc24e50 100644 --- a/src/arm64/qcom/qcm6490-fairphone-fp5.dts +++ b/src/arm64/qcom/qcm6490-fairphone-fp5.dts @@ -71,6 +71,41 @@ }; }; + pmic-glink { + compatible = "qcom,qcm6490-pmic-glink", "qcom,pmic-glink"; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + }; + }; + }; + reserved-memory { cont_splash_mem: cont-splash@e1000000 { reg = <0x0 0xe1000000 0x0 0x2300000>; @@ -82,6 +117,11 @@ no-map; }; + removed_mem: removed@c0000000 { + reg = <0x0 0xc0000000 0x0 0x5100000>; + no-map; + }; + rmtfs_mem: memory@f8500000 { compatible = "qcom,rmtfs-mem"; reg = <0x0 0xf8500000 0x0 0x600000>; @@ -886,7 +926,16 @@ }; &usb_1_dwc3 { - dr_mode = "peripheral"; + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_dwc3_ss { + remote-endpoint = <&pmic_glink_ss_in>; }; &usb_1_hsphy { @@ -915,6 +964,11 @@ status = "okay"; }; +&venus { + firmware-name = "qcom/qcm6490/fairphone5/venus.mbn"; + status = "okay"; +}; + &wifi { qcom,ath11k-calibration-variant = "Fairphone_5"; status = "okay"; diff --git a/src/arm64/qcom/qcm6490-idp.dts b/src/arm64/qcom/qcm6490-idp.dts index 03e97e27d16..e4bfad50a66 100644 --- a/src/arm64/qcom/qcm6490-idp.dts +++ b/src/arm64/qcom/qcm6490-idp.dts @@ -5,8 +5,14 @@ /dts-v1/; +/* PM7250B is configured to use SID8/9 */ +#define PM7250B_SID 8 +#define PM7250B_SID1 9 + +#include #include #include "sc7280.dtsi" +#include "pm7250b.dtsi" #include "pm7325.dtsi" #include "pm8350c.dtsi" #include "pmk8350.dtsi" @@ -109,7 +115,7 @@ no-map; }; - trusted_apps_mem: trusted_apps@c1800000 { + trusted_apps_mem: trusted-apps@c1800000 { reg = <0x0 0xc1800000 0x0 0x1c00000>; no-map; }; @@ -123,8 +129,8 @@ vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <4350000>; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; }; }; @@ -415,6 +421,33 @@ }; }; +&pm8350c_pwm { + status = "okay"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + + led@3 { + reg = <3>; + color = ; + }; + }; +}; + &qupv3_id_0 { status = "okay"; }; diff --git a/src/arm64/qcom/qcs404.dtsi b/src/arm64/qcom/qcs404.dtsi index 2f2eeaf2e94..a05d0234f7f 100644 --- a/src/arm64/qcom/qcs404.dtsi +++ b/src/arm64/qcom/qcs404.dtsi @@ -675,6 +675,14 @@ assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, <&gcc GCC_USB30_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; + + interrupts = , + , + ; + interrupt-names = "pwr_event", + "hs_phy_irq", + "qusb2_phy"; + status = "disabled"; usb3_dwc3: usb@7580000 { @@ -704,6 +712,14 @@ assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>; assigned-clock-rates = <19200000>, <133333333>; + + interrupts = , + , + ; + interrupt-names = "pwr_event", + "hs_phy_irq", + "qusb2_phy"; + status = "disabled"; usb@78c0000 { diff --git a/src/arm64/qcom/qcs6490-rb3gen2.dts b/src/arm64/qcom/qcs6490-rb3gen2.dts index 8bb7d13d85f..97824c769ba 100644 --- a/src/arm64/qcom/qcs6490-rb3gen2.dts +++ b/src/arm64/qcom/qcs6490-rb3gen2.dts @@ -110,7 +110,7 @@ no-map; }; - trusted_apps_mem: trusted_apps@c1800000 { + trusted_apps_mem: trusted-apps@c1800000 { reg = <0x0 0xc1800000 0x0 0x1c00000>; no-map; }; @@ -124,8 +124,8 @@ vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <4350000>; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; }; }; @@ -413,6 +413,23 @@ }; }; +&gcc { + protected-clocks = , + , + , + , + , + , + , + , + , + , + , + , + , + ; +}; + &qupv3_id_0 { status = "okay"; }; diff --git a/src/arm64/qcom/qrb2210-rb1.dts b/src/arm64/qcom/qrb2210-rb1.dts index aa53b6af6d9..6e9dd0312ad 100644 --- a/src/arm64/qcom/qrb2210-rb1.dts +++ b/src/arm64/qcom/qrb2210-rb1.dts @@ -7,7 +7,7 @@ #include #include "qcm2290.dtsi" -#include "pm2250.dtsi" +#include "pm4125.dtsi" / { model = "Qualcomm Technologies, Inc. Robotics RB1"; @@ -177,6 +177,24 @@ }; }; +&CPU_PD0 { + /delete-property/ power-domains; +}; + +&CPU_PD1 { + /delete-property/ power-domains; +}; + +&CPU_PD2 { + /delete-property/ power-domains; +}; + +&CPU_PD3 { + /delete-property/ power-domains; +}; + +/delete-node/ &CLUSTER_PD; + &gpi_dma0 { status = "okay"; }; @@ -226,7 +244,7 @@ }; &mdss_dsi0 { - vdda-supply = <&pm2250_l5>; + vdda-supply = <&pm4125_l5>; status = "okay"; }; @@ -239,7 +257,7 @@ status = "okay"; }; -&pm2250_resin { +&pm4125_resin { linux,code = ; status = "okay"; }; @@ -263,23 +281,23 @@ compatible = "qcom,rpm-pm2250-regulators"; vdd_s3-supply = <&vph_pwr>; vdd_s4-supply = <&vph_pwr>; - vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12-supply = <&pm2250_s3>; + vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12-supply = <&pm4125_s3>; vdd_l4_l17_l18_l19_l20_l21_l22-supply = <&vph_pwr>; - vdd_l13_l14_l15_l16-supply = <&pm2250_s4>; + vdd_l13_l14_l15_l16-supply = <&pm4125_s4>; /* * S1 - VDD_APC * S2 - VDD_CX */ - pm2250_s3: s3 { + pm4125_s3: s3 { /* 0.4V-1.6625V -> 1.3V (Power tree requirements) */ regulator-min-microvolt = <1352000>; regulator-max-microvolt = <1352000>; regulator-boot-on; }; - pm2250_s4: s4 { + pm4125_s4: s4 { /* 1.2V-2.35V -> 2.05V (Power tree requirements) */ regulator-min-microvolt = <2072000>; regulator-max-microvolt = <2072000>; @@ -288,7 +306,7 @@ /* L1 - VDD_MX */ - pm2250_l2: l2 { + pm4125_l2: l2 { /* LPDDR4X VDD2 */ regulator-min-microvolt = <1136000>; regulator-max-microvolt = <1136000>; @@ -296,7 +314,7 @@ regulator-boot-on; }; - pm2250_l3: l3 { + pm4125_l3: l3 { /* LPDDR4X VDDQ */ regulator-min-microvolt = <616000>; regulator-max-microvolt = <616000>; @@ -304,14 +322,14 @@ regulator-boot-on; }; - pm2250_l4: l4 { + pm4125_l4: l4 { /* max = 3.05V -> max = 2.7 to disable 3V signaling (SDHCI2) */ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2700000>; regulator-allow-set-load; }; - pm2250_l5: l5 { + pm4125_l5: l5 { /* CSI/DSI */ regulator-min-microvolt = <1232000>; regulator-max-microvolt = <1232000>; @@ -319,7 +337,7 @@ regulator-boot-on; }; - pm2250_l6: l6 { + pm4125_l6: l6 { /* DRAM PLL */ regulator-min-microvolt = <928000>; regulator-max-microvolt = <928000>; @@ -327,7 +345,7 @@ regulator-boot-on; }; - pm2250_l7: l7 { + pm4125_l7: l7 { /* Wi-Fi CX/MX */ regulator-min-microvolt = <664000>; regulator-max-microvolt = <664000>; @@ -338,20 +356,20 @@ * L9 - VDD_LPI_MX */ - pm2250_l10: l10 { + pm4125_l10: l10 { /* Wi-Fi RFA */ regulator-min-microvolt = <1304000>; regulator-max-microvolt = <1304000>; }; - pm2250_l11: l11 { + pm4125_l11: l11 { /* GPS RF1 */ regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; }; - pm2250_l12: l12 { + pm4125_l12: l12 { /* USB PHYs */ regulator-min-microvolt = <928000>; regulator-max-microvolt = <928000>; @@ -359,7 +377,7 @@ regulator-boot-on; }; - pm2250_l13: l13 { + pm4125_l13: l13 { /* USB/QFPROM/PLLs */ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -367,7 +385,7 @@ regulator-boot-on; }; - pm2250_l14: l14 { + pm4125_l14: l14 { /* SDHCI1 VQMMC */ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -376,7 +394,7 @@ regulator-always-on; }; - pm2250_l15: l15 { + pm4125_l15: l15 { /* WCD/DSI/BT VDDIO */ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -385,38 +403,38 @@ regulator-boot-on; }; - pm2250_l16: l16 { + pm4125_l16: l16 { /* GPS RF2 */ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; }; - pm2250_l17: l17 { + pm4125_l17: l17 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; }; - pm2250_l18: l18 { + pm4125_l18: l18 { /* VDD_PXn */ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - pm2250_l19: l19 { + pm4125_l19: l19 { /* VDD_PXn */ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - pm2250_l20: l20 { + pm4125_l20: l20 { /* SDHCI1 VMMC */ regulator-min-microvolt = <2400000>; regulator-max-microvolt = <3600000>; regulator-allow-set-load; }; - pm2250_l21: l21 { + pm4125_l21: l21 { /* SDHCI2 VMMC */ regulator-min-microvolt = <2960000>; regulator-max-microvolt = <3300000>; @@ -424,7 +442,7 @@ regulator-boot-on; }; - pm2250_l22: l22 { + pm4125_l22: l22 { /* Wi-Fi */ regulator-min-microvolt = <3312000>; regulator-max-microvolt = <3312000>; @@ -433,8 +451,8 @@ }; &sdhc_1 { - vmmc-supply = <&pm2250_l20>; - vqmmc-supply = <&pm2250_l14>; + vmmc-supply = <&pm4125_l20>; + vqmmc-supply = <&pm4125_l14>; pinctrl-0 = <&sdc1_state_on>; pinctrl-1 = <&sdc1_state_off>; pinctrl-names = "default", "sleep"; @@ -446,8 +464,8 @@ }; &sdhc_2 { - vmmc-supply = <&pm2250_l21>; - vqmmc-supply = <&pm2250_l4>; + vmmc-supply = <&pm4125_l21>; + vqmmc-supply = <&pm4125_l4>; cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>; pinctrl-0 = <&sdc2_state_on &sd_det_in_on>; pinctrl-1 = <&sdc2_state_off &sd_det_in_off>; @@ -518,8 +536,8 @@ }; &usb_qmpphy { - vdda-phy-supply = <&pm2250_l12>; - vdda-pll-supply = <&pm2250_l13>; + vdda-phy-supply = <&pm4125_l12>; + vdda-pll-supply = <&pm4125_l13>; status = "okay"; }; @@ -528,17 +546,17 @@ }; &usb_hsphy { - vdd-supply = <&pm2250_l12>; - vdda-pll-supply = <&pm2250_l13>; - vdda-phy-dpdm-supply = <&pm2250_l21>; + vdd-supply = <&pm4125_l12>; + vdda-pll-supply = <&pm4125_l13>; + vdda-phy-dpdm-supply = <&pm4125_l21>; status = "okay"; }; &wifi { - vdd-0.8-cx-mx-supply = <&pm2250_l7>; - vdd-1.8-xo-supply = <&pm2250_l13>; - vdd-1.3-rfa-supply = <&pm2250_l10>; - vdd-3.3-ch0-supply = <&pm2250_l22>; + vdd-0.8-cx-mx-supply = <&pm4125_l7>; + vdd-1.8-xo-supply = <&pm4125_l13>; + vdd-1.3-rfa-supply = <&pm4125_l10>; + vdd-3.3-ch0-supply = <&pm4125_l22>; qcom,ath10k-calibration-variant = "Thundercomm_RB1"; status = "okay"; }; diff --git a/src/arm64/qcom/qrb4210-rb2.dts b/src/arm64/qcom/qrb4210-rb2.dts index 7c19f874fa7..696d6d43c56 100644 --- a/src/arm64/qcom/qrb4210-rb2.dts +++ b/src/arm64/qcom/qrb4210-rb2.dts @@ -6,8 +6,10 @@ /dts-v1/; #include +#include #include "sm4250.dtsi" #include "pm6125.dtsi" +#include "pmi632.dtsi" / { model = "Qualcomm Technologies, Inc. QRB4210 RB2"; @@ -256,6 +258,46 @@ }; }; +&pmi632_typec { + status = "okay"; + + connector { + compatible = "usb-c-connector"; + + power-role = "dual"; + data-role = "dual"; + self-powered; + + typec-power-opmode = "default"; + pd-disable; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + pmi632_hs_in: endpoint { + remote-endpoint = <&usb_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + pmi632_ss_in: endpoint { + remote-endpoint = <&usb_qmpphy_out>; + }; + }; + }; + }; +}; + +&pmi632_vbus { + regulator-min-microamp = <500000>; + regulator-max-microamp = <3000000>; + status = "okay"; +}; + &pon_pwrkey { status = "okay"; }; @@ -607,8 +649,8 @@ status = "okay"; }; -&usb_dwc3 { - maximum-speed = "super-speed"; +&usb_dwc3_hs { + remote-endpoint = <&pmi632_hs_in>; }; &usb_hsphy { @@ -626,6 +668,10 @@ status = "okay"; }; +&usb_qmpphy_out { + remote-endpoint = <&pmi632_ss_in>; +}; + &wifi { vdd-0.8-cx-mx-supply = <&vreg_l8a_0p664>; vdd-1.8-xo-supply = <&vreg_l16a_1p3>; diff --git a/src/arm64/qcom/sa8155p-adp.dts b/src/arm64/qcom/sa8155p-adp.dts index 5e4287f8c8c..b2cf2c98833 100644 --- a/src/arm64/qcom/sa8155p-adp.dts +++ b/src/arm64/qcom/sa8155p-adp.dts @@ -367,6 +367,16 @@ }; }; +&pmm8155au_1_gpios { + pmm8155au_1_sdc2_cd: sdc2-cd-default-state { + pins = "gpio4"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; +}; + &qupv3_id_1 { status = "okay"; }; @@ -384,10 +394,10 @@ &sdhc_2 { status = "okay"; - cd-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; + cd-gpios = <&pmm8155au_1_gpios 4 GPIO_ACTIVE_LOW>; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_on>; - pinctrl-1 = <&sdc2_off>; + pinctrl-0 = <&sdc2_on &pmm8155au_1_sdc2_cd>; + pinctrl-1 = <&sdc2_off &pmm8155au_1_sdc2_cd>; vqmmc-supply = <&vreg_l13c_2p96>; /* IO line power */ vmmc-supply = <&vreg_l17a_2p96>; /* Card power line */ bus-width = <4>; @@ -505,13 +515,6 @@ bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; - - sd-cd-pins { - pins = "gpio96"; - function = "gpio"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; }; sdc2_off: sdc2-off-state { @@ -532,13 +535,6 @@ bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; - - sd-cd-pins { - pins = "gpio96"; - function = "gpio"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; }; usb2phy_ac_en1_default: usb2phy-ac-en1-default-state { diff --git a/src/arm64/qcom/sa8295p-adp.dts b/src/arm64/qcom/sa8295p-adp.dts index fd253942e5e..78e933c42c3 100644 --- a/src/arm64/qcom/sa8295p-adp.dts +++ b/src/arm64/qcom/sa8295p-adp.dts @@ -108,6 +108,13 @@ }; }; }; + + reserved-memory { + gpu_mem: gpu-mem@8bf00000 { + reg = <0 0x8bf00000 0 0x2000>; + no-map; + }; + }; }; &apps_rsc { @@ -266,6 +273,48 @@ status = "okay"; }; +&i2c12 { + pinctrl-0 = <&qup1_i2c4_state>; + pinctrl-names = "default"; + + status = "okay"; + + vdd_gfx: regulator@39 { + compatible = "maxim,max20411"; + reg = <0x39>; + + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + + enable-gpios = <&pmm8540a_gpios 2 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&max20411_en>; + pinctrl-names = "default"; + }; +}; + +&gpucc { + vdd-gfx-supply = <&vdd_gfx>; + status = "okay"; +}; + +&gmu { + status = "okay"; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sa8295p/a690_zap.mbn"; + }; +}; + +&gpu_smmu { + status = "okay"; +}; + &mdss0 { status = "okay"; }; @@ -476,6 +525,10 @@ status = "okay"; }; +&qup1 { + status = "okay"; +}; + &qup2 { status = "okay"; }; @@ -636,6 +689,14 @@ /* PINCTRL */ +&pmm8540a_gpios { + max20411_en: max20411-en-state { + pins = "gpio2"; + function = "normal"; + output-enable; + }; +}; + &tlmm { pcie2a_default: pcie2a-default-state { clkreq-n-pins { @@ -728,4 +789,11 @@ bias-pull-up; }; }; + + qup1_i2c4_state: qup1-i2c4-state { + pins = "gpio0", "gpio1"; + function = "qup12"; + drive-strength = <2>; + bias-pull-up; + }; }; diff --git a/src/arm64/qcom/sa8540p-ride.dts b/src/arm64/qcom/sa8540p-ride.dts index b04f72ec097..177b9dad6ff 100644 --- a/src/arm64/qcom/sa8540p-ride.dts +++ b/src/arm64/qcom/sa8540p-ride.dts @@ -376,14 +376,14 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie2a_default>; - status = "okay"; + status = "disabled"; }; &pcie2a_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; - status = "okay"; + status = "disabled"; }; &pcie3a { diff --git a/src/arm64/qcom/sa8540p.dtsi b/src/arm64/qcom/sa8540p.dtsi index 96b2c59ad02..23888029cc1 100644 --- a/src/arm64/qcom/sa8540p.dtsi +++ b/src/arm64/qcom/sa8540p.dtsi @@ -168,6 +168,9 @@ }; &gpucc { + /* SA8295P and SA8540P doesn't provide gfx.lvl */ + /delete-property/ power-domains; + status = "disabled"; }; diff --git a/src/arm64/qcom/sa8775p.dtsi b/src/arm64/qcom/sa8775p.dtsi index a7eaca33d32..231cea1f0fa 100644 --- a/src/arm64/qcom/sa8775p.dtsi +++ b/src/arm64/qcom/sa8775p.dtsi @@ -356,13 +356,18 @@ no-map; }; - reserved_mem: reserved@908f0000 { - reg = <0x0 0x908f0000 0x0 0xf000>; + ddr_training_checksum: ddr-training-checksum@908c0000 { + reg = <0x0 0x908c0000 0x0 0x1000>; no-map; }; - secdata_apss_mem: secdata-apss@908ff000 { - reg = <0x0 0x908ff000 0x0 0x1000>; + reserved_mem: reserved@908f0000 { + reg = <0x0 0x908f0000 0x0 0xe000>; + no-map; + }; + + secdata_apss_mem: secdata-apss@908fe000 { + reg = <0x0 0x908fe000 0x0 0x2000>; no-map; }; @@ -373,8 +378,43 @@ hwlocks = <&tcsr_mutex 3>; }; - cpucp_fw_mem: cpucp-fw@90b00000 { - reg = <0x0 0x90b00000 0x0 0x100000>; + tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 { + reg = <0x0 0x90c00000 0x0 0x100000>; + no-map; + }; + + sail_mailbox_mem: sail-ss@90d00000 { + reg = <0x0 0x90d00000 0x0 0x100000>; + no-map; + }; + + sail_ota_mem: sail-ss@90e00000 { + reg = <0x0 0x90e00000 0x0 0x300000>; + no-map; + }; + + aoss_backup_mem: aoss-backup@91b00000 { + reg = <0x0 0x91b00000 0x0 0x40000>; + no-map; + }; + + cpucp_backup_mem: cpucp-backup@91b40000 { + reg = <0x0 0x91b40000 0x0 0x40000>; + no-map; + }; + + tz_config_backup_mem: tz-config-backup@91b80000 { + reg = <0x0 0x91b80000 0x0 0x10000>; + no-map; + }; + + ddr_training_data_mem: ddr-training-data@91b90000 { + reg = <0x0 0x91b90000 0x0 0x10000>; + no-map; + }; + + cdt_data_backup_mem: cdt-data-backup@91ba0000 { + reg = <0x0 0x91ba0000 0x0 0x1000>; no-map; }; @@ -433,13 +473,43 @@ no-map; }; + audio_mdf_mem: audio-mdf-region@ae000000 { + reg = <0x0 0xae000000 0x0 0x1000000>; + no-map; + }; + + firmware_mem: firmware-region@b0000000 { + reg = <0x0 0xb0000000 0x0 0x800000>; + no-map; + }; + hyptz_reserved_mem: hyptz-reserved@beb00000 { reg = <0x0 0xbeb00000 0x0 0x11500000>; no-map; }; - tz_stat_mem: tz-stat@d0000000 { - reg = <0x0 0xd0000000 0x0 0x100000>; + scmi_mem: scmi-region@d0000000 { + reg = <0x0 0xd0000000 0x0 0x40000>; + no-map; + }; + + firmware_logs_mem: firmware-logs@d0040000 { + reg = <0x0 0xd0040000 0x0 0x10000>; + no-map; + }; + + firmware_audio_mem: firmware-audio@d0050000 { + reg = <0x0 0xd0050000 0x0 0x4000>; + no-map; + }; + + firmware_reserved_mem: firmware-reserved@d0054000 { + reg = <0x0 0xd0054000 0x0 0x9c000>; + no-map; + }; + + firmware_quantum_test_mem: firmware-quantum-test@d00f0000 { + reg = <0x0 0xd00f0000 0x0 0x10000>; no-map; }; @@ -453,8 +523,23 @@ no-map; }; - trusted_apps_mem: trusted-apps@d1800000 { - reg = <0x0 0xd1800000 0x0 0x3900000>; + deepsleep_backup_mem: deepsleep-backup@d1800000 { + reg = <0x0 0xd1800000 0x0 0x100000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@d1900000 { + reg = <0x0 0xd1900000 0x0 0x3800000>; + no-map; + }; + + tz_stat_mem: tz-stat@db100000 { + reg = <0x0 0xdb100000 0x0 0x100000>; + no-map; + }; + + cpucp_fw_mem: cpucp-fw@db200000 { + reg = <0x0 0xdb200000 0x0 0x100000>; no-map; }; }; @@ -1615,10 +1700,12 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pwr_event", + "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; @@ -1702,10 +1789,12 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, <&pdc 8 IRQ_TYPE_EDGE_BOTH>, <&pdc 7 IRQ_TYPE_EDGE_BOTH>, <&pdc 13 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pwr_event", + "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; @@ -1765,9 +1854,11 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, <&pdc 10 IRQ_TYPE_EDGE_BOTH>, <&pdc 9 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "pwr_event", + "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq"; @@ -2394,8 +2485,9 @@ <0x0 0x23016000 0x0 0x100>; reg-names = "stmmaceth", "rgmii"; - interrupts = ; - interrupt-names = "macirq"; + interrupts = , + ; + interrupt-names = "macirq", "sfty"; clocks = <&gcc GCC_EMAC1_AXI_CLK>, <&gcc GCC_EMAC1_SLV_AHB_CLK>, @@ -2427,8 +2519,9 @@ <0x0 0x23056000 0x0 0x100>; reg-names = "stmmaceth", "rgmii"; - interrupts = ; - interrupt-names = "macirq"; + interrupts = , + ; + interrupt-names = "macirq", "sfty"; clocks = <&gcc GCC_EMAC0_AXI_CLK>, <&gcc GCC_EMAC0_SLV_AHB_CLK>, diff --git a/src/arm64/qcom/sc7180-trogdor.dtsi b/src/arm64/qcom/sc7180-trogdor.dtsi index 46aaeba2860..5260c63db00 100644 --- a/src/arm64/qcom/sc7180-trogdor.dtsi +++ b/src/arm64/qcom/sc7180-trogdor.dtsi @@ -649,6 +649,7 @@ ap_ec_spi: &spi6 { pinctrl-names = "default"; pinctrl-0 = <&ap_ec_int_l>; spi-max-frequency = <3000000>; + wakeup-source; cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; @@ -943,6 +944,8 @@ ap_spi_fp: &spi10 { vddrf-supply = <&pp1300_l2c>; vddch0-supply = <&pp3300_l10c>; max-speed = <3200000>; + + qcom,local-bd-address-broken; }; }; diff --git a/src/arm64/qcom/sc7180.dtsi b/src/arm64/qcom/sc7180.dtsi index 4dcaa15caef..2b481e20ae3 100644 --- a/src/arm64/qcom/sc7180.dtsi +++ b/src/arm64/qcom/sc7180.dtsi @@ -817,7 +817,7 @@ bits = <1 3>; }; - gpu_speed_bin: gpu_speed_bin@1d2 { + gpu_speed_bin: gpu-speed-bin@1d2 { reg = <0x1d2 0x2>; bits = <5 8>; }; @@ -1532,6 +1532,76 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + ufs_mem_hc: ufshc@1d84000 { + compatible = "qcom,sc7180-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0 0x01d84000 0 0x3000>; + interrupts = ; + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + lanes-per-direction = <1>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc UFS_PHY_GDSC>; + + iommus = <&apps_smmu 0xa0 0x0>; + + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; + freq-table-hz = <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <0 0>, + <0 0>, + <0 0>; + + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + qcom,ice = <&ice>; + + status = "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sc7180-qmp-ufs-phy", + "qcom,sm7150-qmp-ufs-phy"; + reg = <0 0x01d87000 0 0x1000>; + clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + clock-names = "ref", "ref_aux"; + power-domains = <&gcc UFS_PHY_GDSC>; + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + #phy-cells = <0>; + status = "disabled"; + }; + + ice: crypto@1d90000 { + compatible = "qcom,sc7180-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0 0x01d90000 0 0x8000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + ipa: ipa@1e40000 { compatible = "qcom,sc7180-ipa"; @@ -2964,12 +3034,16 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <150000000>; - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 9 IRQ_TYPE_EDGE_BOTH>, <&pdc 8 IRQ_TYPE_EDGE_BOTH>, - <&pdc 9 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; required-opps = <&rpmhpd_opp_nom>; diff --git a/src/arm64/qcom/sc7280-chrome-common.dtsi b/src/arm64/qcom/sc7280-chrome-common.dtsi index c4d00a81da3..cecb3e89f7f 100644 --- a/src/arm64/qcom/sc7280-chrome-common.dtsi +++ b/src/arm64/qcom/sc7280-chrome-common.dtsi @@ -18,6 +18,7 @@ */ /delete-node/ &cdsp_mem; +/delete-node/ &domain_idle_states; /delete-node/ &gpu_zap_mem; /delete-node/ &gpu_zap_shader; /delete-node/ &hyp_mem; @@ -26,6 +27,18 @@ /delete-node/ &sec_apps_mem; / { + cpus { + domain_idle_states: domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x40003444>; + entry-latency-us = <2752>; + exit-latency-us = <6562>; + min-residency-us = <9926>; + }; + }; + }; + reserved-memory { camera_mem: memory@8ad00000 { reg = <0x0 0x8ad00000 0x0 0x500000>; @@ -39,6 +52,10 @@ }; }; +&CLUSTER_PD { + domain-idle-states = <&CLUSTER_SLEEP_0>; +}; + &lpass_aon { status = "okay"; }; @@ -119,6 +136,17 @@ dma-coherent; }; +&venus { + iommus = <&apps_smmu 0x2180 0x20>, + <&apps_smmu 0x2184 0x20>; + + status = "okay"; + + video-firmware { + iommus = <&apps_smmu 0x21a2 0x0>; + }; +}; + &watchdog { status = "okay"; }; diff --git a/src/arm64/qcom/sc7280-herobrine.dtsi b/src/arm64/qcom/sc7280-herobrine.dtsi index 9ea6636125a..2ba4ea60cb1 100644 --- a/src/arm64/qcom/sc7280-herobrine.dtsi +++ b/src/arm64/qcom/sc7280-herobrine.dtsi @@ -548,6 +548,7 @@ ap_ec_spi: &spi10 { pinctrl-names = "default"; pinctrl-0 = <&ap_ec_int_l>; spi-max-frequency = <3000000>; + wakeup-source; cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; diff --git a/src/arm64/qcom/sc7280-idp-ec-h1.dtsi b/src/arm64/qcom/sc7280-idp-ec-h1.dtsi index ebae545c587..fbfac7534d3 100644 --- a/src/arm64/qcom/sc7280-idp-ec-h1.dtsi +++ b/src/arm64/qcom/sc7280-idp-ec-h1.dtsi @@ -19,6 +19,7 @@ ap_ec_spi: &spi10 { pinctrl-names = "default"; pinctrl-0 = <&ap_ec_int_l>; spi-max-frequency = <3000000>; + wakeup-source; cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; diff --git a/src/arm64/qcom/sc7280.dtsi b/src/arm64/qcom/sc7280.dtsi index 83b5b76ba17..41f51d32611 100644 --- a/src/arm64/qcom/sc7280.dtsi +++ b/src/arm64/qcom/sc7280.dtsi @@ -202,6 +202,8 @@ power-domain-names = "psci"; next-level-cache = <&L2_0>; operating-points-v2 = <&cpu0_opp_table>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -229,6 +231,8 @@ power-domain-names = "psci"; next-level-cache = <&L2_100>; operating-points-v2 = <&cpu0_opp_table>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -251,6 +255,8 @@ power-domain-names = "psci"; next-level-cache = <&L2_200>; operating-points-v2 = <&cpu0_opp_table>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -273,6 +279,8 @@ power-domain-names = "psci"; next-level-cache = <&L2_300>; operating-points-v2 = <&cpu0_opp_table>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -295,6 +303,8 @@ power-domain-names = "psci"; next-level-cache = <&L2_400>; operating-points-v2 = <&cpu4_opp_table>; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <520>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 1>; @@ -317,6 +327,8 @@ power-domain-names = "psci"; next-level-cache = <&L2_500>; operating-points-v2 = <&cpu4_opp_table>; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <520>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 1>; @@ -339,6 +351,8 @@ power-domain-names = "psci"; next-level-cache = <&L2_600>; operating-points-v2 = <&cpu4_opp_table>; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <520>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 1>; @@ -361,6 +375,8 @@ power-domain-names = "psci"; next-level-cache = <&L2_700>; operating-points-v2 = <&cpu7_opp_table>; + capacity-dmips-mhz = <1985>; + dynamic-power-coefficient = <552>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 2>; @@ -453,15 +469,29 @@ }; }; - domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + domain_idle_states: domain-idle-states { + CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { compatible = "domain-idle-state"; - idle-state-name = "cluster-power-down"; - arm,psci-suspend-param = <0x40003444>; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <2752>; + exit-latency-us = <3048>; + min-residency-us = <6118>; + }; + + CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41001344>; entry-latency-us = <3263>; + exit-latency-us = <4562>; + min-residency-us = <8467>; + }; + + CLUSTER_SLEEP_LLCC_OFF: cluster-sleep-2 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x4100b344>; + entry-latency-us = <3638>; exit-latency-us = <6562>; - min-residency-us = <9926>; - local-timer-stop; + min-residency-us = <9826>; }; }; }; @@ -872,7 +902,7 @@ CLUSTER_PD: power-domain-cluster { #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_SLEEP_0>; + domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_CX_RET &CLUSTER_SLEEP_LLCC_OFF>; }; }; @@ -966,7 +996,7 @@ #address-cells = <1>; #size-cells = <1>; - gpu_speed_bin: gpu_speed_bin@1e9 { + gpu_speed_bin: gpu-speed-bin@1e9 { reg = <0x1e9 0x2>; bits = <5 8>; }; @@ -2178,8 +2208,16 @@ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, @@ -2345,6 +2383,8 @@ <&apps_smmu 0x4e6 0x0011>; qcom,ee = <0>; qcom,controlled-remotely; + num-channels = <16>; + qcom,num-ees = <4>; }; crypto: crypto@1dfa000 { @@ -2648,6 +2688,31 @@ status = "disabled"; }; + slimbam: dma-controller@3a84000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0 0x03a84000 0 0x20000>; + interrupts = ; + #dma-cells = <1>; + qcom,controlled-remotely; + num-channels = <31>; + qcom,ee = <1>; + qcom,num-ees = <2>; + iommus = <&apps_smmu 0x1826 0x0>; + status = "disabled"; + }; + + slim: slim-ngd@3ac0000 { + compatible = "qcom,slim-ngd-v1.5.0"; + reg = <0 0x03ac0000 0 0x2c000>; + interrupts = ; + dmas = <&slimbam 3>, <&slimbam 4>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x1826 0x0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + lpass_hm: clock-controller@3c00000 { compatible = "qcom,sc7280-lpasshm"; reg = <0 0x03c00000 0 0x28>; @@ -3582,10 +3647,12 @@ <&gcc GCC_USB30_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, <&pdc 12 IRQ_TYPE_EDGE_BOTH>, <&pdc 13 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", + interrupt-names = "pwr_event", + "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq"; @@ -3640,7 +3707,7 @@ compatible = "qcom,sc7280-adsp-pas"; reg = <0 0x03700000 0 0x100>; - interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, @@ -3877,7 +3944,7 @@ compatible = "qcom,sc7280-cdsp-pas"; reg = <0 0x0a300000 0 0x10000>; - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, @@ -4035,11 +4102,13 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", + interrupt-names = "pwr_event", + "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; @@ -4065,6 +4134,25 @@ phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; maximum-speed = "super-speed"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + }; + }; + }; }; }; @@ -4091,10 +4179,11 @@ <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "cpu-cfg", "video-mem"; - iommus = <&apps_smmu 0x2180 0x20>, - <&apps_smmu 0x2184 0x20>; + iommus = <&apps_smmu 0x2180 0x20>; memory-region = <&video_mem>; + status = "disabled"; + video-decoder { compatible = "venus-decoder"; }; @@ -4103,10 +4192,6 @@ compatible = "venus-encoder"; }; - video-firmware { - iommus = <&apps_smmu 0x21a2 0x0>; - }; - venus_opp_table: opp-table { compatible = "operating-points-v2"; diff --git a/src/arm64/qcom/sc8180x.dtsi b/src/arm64/qcom/sc8180x.dtsi index 0430d99091e..053f7861c3c 100644 --- a/src/arm64/qcom/sc8180x.dtsi +++ b/src/arm64/qcom/sc8180x.dtsi @@ -290,7 +290,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <241>; + entry-latency-us = <2411>; exit-latency-us = <1461>; min-residency-us = <4488>; local-timer-stop; @@ -298,7 +298,15 @@ }; domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <3300>; + exit-latency-us = <3300>; + min-residency-us = <6000>; + }; + + CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 { compatible = "domain-idle-state"; arm,psci-suspend-param = <0x4100a344>; entry-latency-us = <3263>; @@ -582,7 +590,7 @@ CLUSTER_PD: power-domain-cpu-cluster0 { #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_SLEEP_0>; + domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>; }; }; @@ -782,6 +790,7 @@ clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + power-domains = <&rpmhpd SC8180X_CX>; }; qupv3_id_0: geniqup@8c0000 { @@ -1708,8 +1717,22 @@ ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>, <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1805,8 +1828,22 @@ ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1903,8 +1940,22 @@ ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>, <0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -2001,8 +2052,22 @@ ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>, <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -2131,9 +2196,11 @@ reg = <0 0x01d87000 0 0x1000>; clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_EN>; clock-names = "ref", - "ref_aux"; + "ref_aux", + "qref"; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; @@ -2173,6 +2240,8 @@ interconnect-names = "gfx-mem"; qcom,gmu = <&gmu>; + #cooling-cells = <2>; + status = "disabled"; gpu_opp_table: opp-table { @@ -2632,7 +2701,7 @@ resets = <&gcc GCC_USB30_SEC_BCR>; power-domains = <&gcc USB30_SEC_GDSC>; interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 7 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 40 IRQ_TYPE_LEVEL_HIGH>, <&pdc 10 IRQ_TYPE_EDGE_BOTH>, <&pdc 11 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "hs_phy_irq", "ss_phy_irq", @@ -2692,9 +2761,15 @@ interrupt-controller; #interrupt-cells = <1>; - interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, - <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; - interconnect-names = "mdp0-mem", "mdp1-mem"; + interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_MDP_PORT1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; iommus = <&apps_smmu 0x800 0x420>; @@ -2723,10 +2798,8 @@ "rot", "lut"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <460000000>, - <19200000>; + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmhpd SC8180X_MMCX>; @@ -3184,7 +3257,7 @@ <&dispcc DISP_CC_MDSS_AHB_CLK>; clock-names = "aux", "cfg_ahb"; - power-domains = <&dispcc MDSS_GDSC>; + power-domains = <&rpmhpd SC8180X_MX>; #clock-cells = <1>; #phy-cells = <0>; @@ -3210,6 +3283,7 @@ "edp_phy_pll_link_clk", "edp_phy_pll_vco_div_clk"; power-domains = <&rpmhpd SC8180X_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; @@ -3248,7 +3322,7 @@ aoss_qmp: power-controller@c300000 { compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp"; - reg = <0x0 0x0c300000 0x0 0x100000>; + reg = <0x0 0x0c300000 0x0 0x400>; interrupts = ; mboxes = <&apss_shared 0>; @@ -3256,6 +3330,11 @@ #power-domain-cells = <1>; }; + sram@c3f0000 { + compatible = "qcom,rpmh-stats"; + reg = <0x0 0x0c3f0000 0x0 0x400>; + }; + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0 0x0c440000 0x0 0x0001100>, @@ -3880,8 +3959,15 @@ thermal-sensors = <&tsens0 15>; + cooling-maps { + map0 { + trip = <&gpu_top_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpu_top_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -4030,8 +4116,15 @@ thermal-sensors = <&tsens1 11>; + cooling-maps { + map0 { + trip = <&gpu_bottom_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpu_bottom_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; diff --git a/src/arm64/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/src/arm64/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index eb657e54496..15ae94c1602 100644 --- a/src/arm64/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/src/arm64/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -6,10 +6,8 @@ /dts-v1/; -#include #include -#include -#include +#include #include #include #include @@ -855,27 +853,6 @@ }; &pmk8280_vadc { - status = "okay"; - - channel@3 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "pmk8350_die_temp"; - }; - - channel@44 { - reg = ; - qcom,hw-settle-time = <200>; - qcom,ratiometric; - label = "pmk8350_xo_therm"; - }; - - channel@103 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "pmc8280_1_die_temp"; - }; - channel@144 { reg = ; qcom,hw-settle-time = <200>; @@ -904,12 +881,6 @@ label = "sys_therm4"; }; - channel@303 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "pmc8280_2_die_temp"; - }; - channel@344 { reg = ; qcom,hw-settle-time = <200>; @@ -937,12 +908,6 @@ qcom,ratiometric; label = "sys_therm8"; }; - - channel@403 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "pmr735a_die_temp"; - }; }; &qup0 { @@ -1204,7 +1169,7 @@ }; &vamacro { - pinctrl-0 = <&dmic01_default>, <&dmic02_default>; + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; pinctrl-names = "default"; vdd-micb-supply = <&vreg_s10b>; diff --git a/src/arm64/qcom/sc8280xp-pmics.dtsi b/src/arm64/qcom/sc8280xp-pmics.dtsi index 80ee12ded4f..945de77911d 100644 --- a/src/arm64/qcom/sc8280xp-pmics.dtsi +++ b/src/arm64/qcom/sc8280xp-pmics.dtsi @@ -3,6 +3,9 @@ * Copyright (c) 2022, Linaro Limited */ +#include +#include +#include #include #include #include @@ -84,7 +87,37 @@ #address-cells = <1>; #size-cells = <0>; #io-channel-cells = <1>; - status = "disabled"; + + channel@3 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "pmk8350_die_temp"; + }; + + channel@44 { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "pmk8350_xo_therm"; + }; + + channel@103 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "pmc8280_1_die_temp"; + }; + + channel@303 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "pmc8280_2_die_temp"; + }; + + channel@403 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "pmr735a_die_temp"; + }; }; pmk8280_adc_tm: adc-tm@3400 { @@ -126,6 +159,8 @@ compatible = "qcom,spmi-temp-alarm"; reg = <0xa00>; interrupts-extended = <&spmi_bus 0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pmk8280_vadc PM8350_ADC7_DIE_TEMP(1)>; + io-channel-names = "thermal"; #thermal-sensor-cells = <0>; }; @@ -178,6 +213,8 @@ compatible = "qcom,spmi-temp-alarm"; reg = <0xa00>; interrupts-extended = <&spmi_bus 0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pmk8280_vadc PM8350_ADC7_DIE_TEMP(3)>; + io-channel-names = "thermal"; #thermal-sensor-cells = <0>; }; diff --git a/src/arm64/qcom/sc8280xp.dtsi b/src/arm64/qcom/sc8280xp.dtsi index febf28356ff..d0f82e12289 100644 --- a/src/arm64/qcom/sc8280xp.dtsi +++ b/src/arm64/qcom/sc8280xp.dtsi @@ -1774,6 +1774,7 @@ reset-names = "pci"; power-domains = <&gcc PCIE_4_GDSC>; + required-opps = <&rpmhpd_opp_nom>; phys = <&pcie4_phy>; phy-names = "pciephy"; @@ -1872,6 +1873,7 @@ reset-names = "pci"; power-domains = <&gcc PCIE_3B_GDSC>; + required-opps = <&rpmhpd_opp_nom>; phys = <&pcie3b_phy>; phy-names = "pciephy"; @@ -1970,6 +1972,7 @@ reset-names = "pci"; power-domains = <&gcc PCIE_3A_GDSC>; + required-opps = <&rpmhpd_opp_nom>; phys = <&pcie3a_phy>; phy-names = "pciephy"; @@ -2071,6 +2074,7 @@ reset-names = "pci"; power-domains = <&gcc PCIE_2B_GDSC>; + required-opps = <&rpmhpd_opp_nom>; phys = <&pcie2b_phy>; phy-names = "pciephy"; @@ -2169,6 +2173,7 @@ reset-names = "pci"; power-domains = <&gcc PCIE_2A_GDSC>; + required-opps = <&rpmhpd_opp_nom>; phys = <&pcie2a_phy>; phy-names = "pciephy"; @@ -2257,9 +2262,12 @@ compatible = "qcom,sc8280xp-qmp-ufs-phy"; reg = <0 0x01d87000 0 0x1000>; - clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - clock-names = "ref", "ref_aux"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_CARD_CLKREF_CLK>; + clock-names = "ref", + "ref_aux", + "qref"; power-domains = <&gcc UFS_PHY_GDSC>; @@ -2319,9 +2327,12 @@ compatible = "qcom,sc8280xp-qmp-ufs-phy"; reg = <0 0x01da7000 0 0x1000>; - clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>, - <&gcc GCC_UFS_CARD_PHY_AUX_CLK>; - clock-names = "ref", "ref_aux"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_CARD_PHY_AUX_CLK>, + <&gcc GCC_UFS_1_CARD_CLKREF_CLK>; + clock-names = "ref", + "ref_aux", + "qref"; power-domains = <&gcc UFS_CARD_GDSC>; @@ -2635,7 +2646,7 @@ compatible = "qcom,sc8280xp-adsp-pas"; reg = <0 0x03000000 0 0x100>; - interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, @@ -2978,7 +2989,7 @@ }; }; - dmic02_default: dmic02-default-state { + dmic23_default: dmic23-default-state { clk-pins { pins = "gpio8"; function = "dmic2_clk"; @@ -2994,7 +3005,7 @@ }; }; - dmic02_sleep: dmic02-sleep-state { + dmic23_sleep: dmic23-sleep-state { clk-pins { pins = "gpio8"; function = "dmic2_clk"; @@ -3451,6 +3462,404 @@ }; }; + cci0: cci@ac4a000 { + compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac4a000 0 0x1000>; + + interrupts = ; + + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_0_CLK>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci"; + + power-domains = <&camcc TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci0_default>; + pinctrl-1 = <&cci0_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci1: cci@ac4b000 { + compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac4b000 0 0x1000>; + + interrupts = ; + + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_1_CLK>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci"; + + power-domains = <&camcc TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci1_default>; + pinctrl-1 = <&cci1_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci2: cci@ac4c000 { + compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac4c000 0 0x1000>; + + interrupts = ; + + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_2_CLK>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci"; + power-domains = <&camcc TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci2_default>; + pinctrl-1 = <&cci2_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci2_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci2_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci3: cci@ac4d000 { + compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac4d000 0 0x1000>; + + interrupts = ; + + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_3_CLK>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci"; + + power-domains = <&camcc TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci3_default>; + pinctrl-1 = <&cci3_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci3_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci3_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + camss: camss@ac5a000 { + compatible = "qcom,sc8280xp-camss"; + + reg = <0 0x0ac5a000 0 0x2000>, + <0 0x0ac5c000 0 0x2000>, + <0 0x0ac65000 0 0x2000>, + <0 0x0ac67000 0 0x2000>, + <0 0x0acaf000 0 0x4000>, + <0 0x0acb3000 0 0x1000>, + <0 0x0acb6000 0 0x4000>, + <0 0x0acba000 0 0x1000>, + <0 0x0acbd000 0 0x4000>, + <0 0x0acc1000 0 0x1000>, + <0 0x0acc4000 0 0x4000>, + <0 0x0acc8000 0 0x1000>, + <0 0x0accb000 0 0x4000>, + <0 0x0accf000 0 0x1000>, + <0 0x0acd2000 0 0x4000>, + <0 0x0acd6000 0 0x1000>, + <0 0x0acd9000 0 0x4000>, + <0 0x0acdd000 0 0x1000>, + <0 0x0ace0000 0 0x4000>, + <0 0x0ace4000 0 0x1000>; + reg-names = "csiphy2", + "csiphy3", + "csiphy0", + "csiphy1", + "vfe0", + "csid0", + "vfe1", + "csid1", + "vfe2", + "csid2", + "vfe_lite0", + "csid0_lite", + "vfe_lite1", + "csid1_lite", + "vfe_lite2", + "csid2_lite", + "vfe_lite3", + "csid3_lite", + "vfe3", + "csid3"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "csid1_lite", + "vfe_lite1", + "csiphy3", + "csid0", + "vfe0", + "csid1", + "vfe1", + "csid0_lite", + "vfe_lite0", + "csiphy0", + "csiphy1", + "csiphy2", + "csid2", + "vfe2", + "csid3_lite", + "csid2_lite", + "vfe_lite3", + "vfe_lite2", + "csid3", + "vfe3"; + + power-domains = <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc IFE_2_GDSC>, + <&camcc IFE_3_GDSC>, + <&camcc TITAN_TOP_GDSC>; + power-domain-names = "ife0", + "ife1", + "ife2", + "ife3", + "top"; + + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CSIPHY0_CLK>, + <&camcc CAMCC_CSI0PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY1_CLK>, + <&camcc CAMCC_CSI1PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY2_CLK>, + <&camcc CAMCC_CSI2PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY3_CLK>, + <&camcc CAMCC_CSI3PHYTIMER_CLK>, + <&camcc CAMCC_IFE_0_AXI_CLK>, + <&camcc CAMCC_IFE_0_CLK>, + <&camcc CAMCC_IFE_0_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_0_CSID_CLK>, + <&camcc CAMCC_IFE_1_AXI_CLK>, + <&camcc CAMCC_IFE_1_CLK>, + <&camcc CAMCC_IFE_1_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_1_CSID_CLK>, + <&camcc CAMCC_IFE_2_AXI_CLK>, + <&camcc CAMCC_IFE_2_CLK>, + <&camcc CAMCC_IFE_2_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_2_CSID_CLK>, + <&camcc CAMCC_IFE_3_AXI_CLK>, + <&camcc CAMCC_IFE_3_CLK>, + <&camcc CAMCC_IFE_3_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_3_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_0_CLK>, + <&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_0_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_1_CLK>, + <&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_1_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_2_CLK>, + <&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_2_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_3_CLK>, + <&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_3_CSID_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "vfe0_axi", + "vfe0", + "vfe0_cphy_rx", + "vfe0_csid", + "vfe1_axi", + "vfe1", + "vfe1_cphy_rx", + "vfe1_csid", + "vfe2_axi", + "vfe2", + "vfe2_cphy_rx", + "vfe2_csid", + "vfe3_axi", + "vfe3", + "vfe3_cphy_rx", + "vfe3_csid", + "vfe_lite0", + "vfe_lite0_cphy_rx", + "vfe_lite0_csid", + "vfe_lite1", + "vfe_lite1_cphy_rx", + "vfe_lite1_csid", + "vfe_lite2", + "vfe_lite2_cphy_rx", + "vfe_lite2_csid", + "vfe_lite3", + "vfe_lite3_cphy_rx", + "vfe_lite3_csid", + "gcc_axi_hf", + "gcc_axi_sf"; + + iommus = <&apps_smmu 0x2000 0x4e0>, + <&apps_smmu 0x2020 0x4e0>, + <&apps_smmu 0x2040 0x4e0>, + <&apps_smmu 0x2060 0x4e0>, + <&apps_smmu 0x2080 0x4e0>, + <&apps_smmu 0x20e0 0x4e0>, + <&apps_smmu 0x20c0 0x4e0>, + <&apps_smmu 0x20a0 0x4e0>, + <&apps_smmu 0x2400 0x4e0>, + <&apps_smmu 0x2420 0x4e0>, + <&apps_smmu 0x2440 0x4e0>, + <&apps_smmu 0x2460 0x4e0>, + <&apps_smmu 0x2480 0x4e0>, + <&apps_smmu 0x24e0 0x4e0>, + <&apps_smmu 0x24c0 0x4e0>, + <&apps_smmu 0x24a0 0x4e0>; + + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "cam_ahb", + "cam_hf_mnoc", + "cam_sf_mnoc", + "cam_sf_icp_mnoc"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + port@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + port@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + camcc: clock-controller@ad00000 { compatible = "qcom,sc8280xp-camcc"; reg = <0 0x0ad00000 0 0x20000>; @@ -4011,6 +4420,28 @@ interrupt-controller; }; + tsens2: thermal-sensor@c251000 { + compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; + reg = <0 0x0c251000 0 0x1ff>, + <0 0x0c224000 0 0x8>; + #qcom,sensors = <11>; + interrupts-extended = <&pdc 122 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 124 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + tsens3: thermal-sensor@c252000 { + compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; + reg = <0 0x0c252000 0 0x1ff>, + <0 0x0c225000 0 0x8>; + #qcom,sensors = <5>; + interrupts-extended = <&pdc 123 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 125 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + tsens0: thermal-sensor@c263000 { compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; reg = <0 0x0c263000 0 0x1ff>, /* TM */ @@ -4076,6 +4507,150 @@ #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 230>; wakeup-parent = <&pdc>; + + cci0_default: cci0-default-state { + cci0_i2c0_default: cci0-i2c0-default-pins { + /* cci_i2c_sda0, cci_i2c_scl0 */ + pins = "gpio113", "gpio114"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci0_i2c1_default: cci0-i2c1-default-pins { + /* cci_i2c_sda1, cci_i2c_scl1 */ + pins = "gpio115", "gpio116"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + cci0_sleep: cci0-sleep-state { + cci0_i2c0_sleep: cci0-i2c0-sleep-pins { + /* cci_i2c_sda0, cci_i2c_scl0 */ + pins = "gpio113", "gpio114"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci0_i2c1_sleep: cci0-i2c1-sleep-pins { + /* cci_i2c_sda1, cci_i2c_scl1 */ + pins = "gpio115", "gpio116"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci1_default: cci1-default-state { + cci1_i2c0_default: cci1-i2c0-default-pins { + /* cci_i2c_sda2, cci_i2c_scl2 */ + pins = "gpio10","gpio11"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci1_i2c1_default: cci1-i2c1-default-pins { + /* cci_i2c_sda3, cci_i2c_scl3 */ + pins = "gpio123","gpio124"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + cci1_sleep: cci1-sleep-state { + cci1_i2c0_sleep: cci1-i2c0-sleep-pins { + /* cci_i2c_sda2, cci_i2c_scl2 */ + pins = "gpio10","gpio11"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci1_i2c1_sleep: cci1-i2c1-sleep-pins { + /* cci_i2c_sda3, cci_i2c_scl3 */ + pins = "gpio123","gpio124"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci2_default: cci2-default-state { + cci2_i2c0_default: cci2-i2c0-default-pins { + /* cci_i2c_sda4, cci_i2c_scl4 */ + pins = "gpio117","gpio118"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci2_i2c1_default: cci2-i2c1-default-pins { + /* cci_i2c_sda5, cci_i2c_scl5 */ + pins = "gpio12","gpio13"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + cci2_sleep: cci2-sleep-state { + cci2_i2c0_sleep: cci2-i2c0-sleep-pins { + /* cci_i2c_sda4, cci_i2c_scl4 */ + pins = "gpio117","gpio118"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci2_i2c1_sleep: cci2-i2c1-sleep-pins { + /* cci_i2c_sda5, cci_i2c_scl5 */ + pins = "gpio12","gpio13"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci3_default: cci3-default-state { + cci3_i2c0_default: cci3-i2c0-default-pins { + /* cci_i2c_sda6, cci_i2c_scl6 */ + pins = "gpio145","gpio146"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci3_i2c1_default: cci3-i2c1-default-pins { + /* cci_i2c_sda7, cci_i2c_scl7 */ + pins = "gpio164","gpio165"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + cci3_sleep: cci3-sleep-state { + cci3_i2c0_sleep: cci3-i2c0-sleep-pins { + /* cci_i2c_sda6, cci_i2c_scl6 */ + pins = "gpio145","gpio146"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci3_i2c1_sleep: cci3-i2c1-sleep-pins { + /* cci_i2c_sda7, cci_i2c_scl7 */ + pins = "gpio164","gpio165"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + }; }; apps_smmu: iommu@15000000 { @@ -4407,7 +4982,7 @@ compatible = "qcom,sc8280xp-nsp0-pas"; reg = <0 0x1b300000 0 0x100>; - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>, @@ -4538,7 +5113,7 @@ compatible = "qcom,sc8280xp-nsp1-pas"; reg = <0 0x21300000 0 0x100>; - interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_EDGE_RISING>, <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>, @@ -5212,6 +5787,21 @@ }; }; + gpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens2 2>; + + trips { + gpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + mem-thermal { polling-delay-passive = <250>; polling-delay = <1000>; diff --git a/src/arm64/qcom/sda660-inforce-ifc6560.dts b/src/arm64/qcom/sda660-inforce-ifc6560.dts index 2ed39d402d3..702ab49bbc5 100644 --- a/src/arm64/qcom/sda660-inforce-ifc6560.dts +++ b/src/arm64/qcom/sda660-inforce-ifc6560.dts @@ -461,3 +461,8 @@ dr_mode = "peripheral"; extcon = <&extcon_usb>; }; + +&usb3_qmpphy { + vdda-phy-supply = <&vreg_l1b_0p925>; + status = "okay"; +}; diff --git a/src/arm64/qcom/sdm450-motorola-ali.dts b/src/arm64/qcom/sdm450-motorola-ali.dts index 362be5719dd..e27f3c5d5bb 100644 --- a/src/arm64/qcom/sdm450-motorola-ali.dts +++ b/src/arm64/qcom/sdm450-motorola-ali.dts @@ -4,7 +4,7 @@ */ /dts-v1/; -#include "msm8953.dtsi" +#include "sdm450.dtsi" #include "pm8953.dtsi" #include "pmi8950.dtsi" diff --git a/src/arm64/qcom/sdm450.dtsi b/src/arm64/qcom/sdm450.dtsi new file mode 100644 index 00000000000..b222aeb459a --- /dev/null +++ b/src/arm64/qcom/sdm450.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* Copyright (c) 2023, Luca Weiss */ + +#include "msm8953.dtsi" + +&gpu_opp_table { + /delete-node/ opp-650000000; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_turbo>; + }; +}; diff --git a/src/arm64/qcom/sdm630-sony-xperia-nile.dtsi b/src/arm64/qcom/sdm630-sony-xperia-nile.dtsi index 87d0293c728..819a5f8825e 100644 --- a/src/arm64/qcom/sdm630-sony-xperia-nile.dtsi +++ b/src/arm64/qcom/sdm630-sony-xperia-nile.dtsi @@ -241,6 +241,16 @@ }; }; +&pm660l_wled { + status = "okay"; + + qcom,switching-freq = <800>; + qcom,ovp-millivolt = <29600>; + qcom,current-boost-limit = <970>; + qcom,current-limit-microamp = <17500>; + qcom,num-strings = <2>; +}; + &pon_pwrkey { status = "okay"; }; @@ -658,10 +668,16 @@ }; &usb3 { + qcom,select-utmi-as-pipe-clk; + status = "okay"; }; &usb3_dwc3 { + maximum-speed = "high-speed"; + phys = <&qusb2phy0>; + phy-names = "usb2-phy"; + dr_mode = "peripheral"; extcon = <&extcon_usb>; }; diff --git a/src/arm64/qcom/sdm630.dtsi b/src/arm64/qcom/sdm630.dtsi index 513fe5e76b6..f5921b80ef9 100644 --- a/src/arm64/qcom/sdm630.dtsi +++ b/src/arm64/qcom/sdm630.dtsi @@ -13,6 +13,7 @@ #include #include #include +#include #include / { @@ -1100,6 +1101,7 @@ interconnect-names = "gfx-mem"; operating-points-v2 = <&gpu_sdm630_opp_table>; + #cooling-cells = <2>; status = "disabled"; @@ -1281,12 +1283,16 @@ <&gcc GCC_USB30_MASTER_CLK>; assigned-clock-rates = <19200000>, <120000000>; - interrupts = , + interrupts = , + , + , ; - interrupt-names = "hs_phy_irq", "ss_phy_irq"; + interrupt-names = "pwr_event", + "qusb2_phy", + "hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB_30_GDSC>; - qcom,select-utmi-as-pipe-clk; resets = <&gcc GCC_USB_30_BCR>; @@ -1297,17 +1303,38 @@ snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; - /* - * SDM630 technically supports USB3 but I - * haven't seen any devices making use of it. - */ - maximum-speed = "high-speed"; - phys = <&qusb2phy0>; - phy-names = "usb2-phy"; + phys = <&qusb2phy0>, <&usb3_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; snps,hird-threshold = /bits/ 8 <0>; }; }; + usb3_qmpphy: phy@c010000 { + compatible = "qcom,sdm660-qmp-usb3-phy"; + reg = <0x0c010000 0x1000>; + + clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, + <&gcc GCC_USB3_CLKREF_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "cfg_ahb", + "pipe"; + clock-output-names = "usb3_phy_pipe_clk_src"; + #clock-cells = <0>; + #phy-cells = <0>; + + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "phy", + "phy_phy"; + + qcom,tcsr-reg = <&tcsr_regs_1 0x6b244>; + + status = "disabled"; + }; + qusb2phy0: phy@c012000 { compatible = "qcom,sdm660-qusb2-phy"; reg = <0x0c012000 0x180>; @@ -1463,8 +1490,12 @@ <&gcc GCC_USB20_MASTER_CLK>; assigned-clock-rates = <19200000>, <60000000>; - interrupts = ; - interrupt-names = "hs_phy_irq"; + interrupts = , + , + ; + interrupt-names = "pwr_event", + "qusb2_phy", + "hs_phy_irq"; qcom,select-utmi-as-pipe-clk; @@ -2551,6 +2582,13 @@ thermal-sensors = <&tsens 8>; + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = <&adreno_gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { gpu_alert0: trip-point0 { temperature = <90000>; diff --git a/src/arm64/qcom/sdm632.dtsi b/src/arm64/qcom/sdm632.dtsi index 645b9f6a801..95b025ea260 100644 --- a/src/arm64/qcom/sdm632.dtsi +++ b/src/arm64/qcom/sdm632.dtsi @@ -79,3 +79,11 @@ compatible = "qcom,kryo250"; capacity-dmips-mhz = <1980>; }; + +&gpu_opp_table { + opp-725000000 { + opp-hz = /bits/ 64 <725000000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_turbo>; + }; +}; diff --git a/src/arm64/qcom/sdm660-xiaomi-lavender.dts b/src/arm64/qcom/sdm660-xiaomi-lavender.dts index 3c47410ba94..7167f75bced 100644 --- a/src/arm64/qcom/sdm660-xiaomi-lavender.dts +++ b/src/arm64/qcom/sdm660-xiaomi-lavender.dts @@ -413,10 +413,16 @@ }; &usb3 { + qcom,select-utmi-as-pipe-clk; + status = "okay"; }; &usb3_dwc3 { + maximum-speed = "high-speed"; + phys = <&qusb2phy0>; + phy-names = "usb2-phy"; + dr_mode = "peripheral"; extcon = <&extcon_usb>; }; diff --git a/src/arm64/qcom/sdm670.dtsi b/src/arm64/qcom/sdm670.dtsi index 4d7b77a2315..80e81c4233b 100644 --- a/src/arm64/qcom/sdm670.dtsi +++ b/src/arm64/qcom/sdm670.dtsi @@ -1320,12 +1320,16 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <150000000>; - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 9 IRQ_TYPE_EDGE_BOTH>, <&pdc 8 IRQ_TYPE_EDGE_BOTH>, - <&pdc 9 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; diff --git a/src/arm64/qcom/sdm845-cheza.dtsi b/src/arm64/qcom/sdm845-cheza.dtsi index 0ab5e8f53ac..e8276db9eab 100644 --- a/src/arm64/qcom/sdm845-cheza.dtsi +++ b/src/arm64/qcom/sdm845-cheza.dtsi @@ -852,6 +852,7 @@ ap_ts_i2c: &i2c14 { pinctrl-names = "default"; pinctrl-0 = <&ec_ap_int_l>; spi-max-frequency = <3000000>; + wakeup-source; cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; diff --git a/src/arm64/qcom/sdm845-db845c.dts b/src/arm64/qcom/sdm845-db845c.dts index ab622045651..1f517328199 100644 --- a/src/arm64/qcom/sdm845-db845c.dts +++ b/src/arm64/qcom/sdm845-db845c.dts @@ -580,7 +580,7 @@ &pcie0 { status = "okay"; perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - enable-gpio = <&tlmm 134 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 134 GPIO_ACTIVE_HIGH>; vddpe-3v3-supply = <&pcie0_3p3v_dual>; diff --git a/src/arm64/qcom/sdm845-oneplus-common.dtsi b/src/arm64/qcom/sdm845-oneplus-common.dtsi index e821103d49c..46e25c53829 100644 --- a/src/arm64/qcom/sdm845-oneplus-common.dtsi +++ b/src/arm64/qcom/sdm845-oneplus-common.dtsi @@ -508,13 +508,13 @@ }; &q6afedai { - qi2s@22 { - reg = <22>; + dai@22 { + reg = ; qcom,sd-lines = <1>; }; - qi2s@23 { - reg = <23>; + dai@23 { + reg = ; qcom,sd-lines = <0>; }; }; diff --git a/src/arm64/qcom/sdm845-shift-axolotl.dts b/src/arm64/qcom/sdm845-shift-axolotl.dts index fbb8655653f..486ce175e6b 100644 --- a/src/arm64/qcom/sdm845-shift-axolotl.dts +++ b/src/arm64/qcom/sdm845-shift-axolotl.dts @@ -60,7 +60,7 @@ }; reserved-memory { - framebuffer_region@9d400000 { + framebuffer@9d400000 { reg = <0x0 0x9d400000 0x0 (1080 * 2160 * 4)>; no-map; }; diff --git a/src/arm64/qcom/sdm845.dtsi b/src/arm64/qcom/sdm845.dtsi index c2244824355..2f20be99ee7 100644 --- a/src/arm64/qcom/sdm845.dtsi +++ b/src/arm64/qcom/sdm845.dtsi @@ -2639,10 +2639,12 @@ compatible = "qcom,sdm845-qmp-ufs-phy"; reg = <0 0x01d87000 0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>; clock-names = "ref", - "ref_aux"; - clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + "ref_aux", + "qref"; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; @@ -3366,8 +3368,8 @@ qcom,qmp = <&aoss_qmp>; - power-domains = <&rpmhpd SDM845_CX>, - <&rpmhpd SDM845_MX>; + power-domains = <&rpmhpd SDM845_LCX>, + <&rpmhpd SDM845_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&slpi_mem>; @@ -4058,12 +4060,16 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <150000000>; - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc_intc 6 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>, <&pdc_intc 8 IRQ_TYPE_EDGE_BOTH>, - <&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + <&pdc_intc 6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; @@ -4109,12 +4115,16 @@ <&gcc GCC_USB30_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <150000000>; - interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <&pdc_intc 7 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>, <&pdc_intc 10 IRQ_TYPE_EDGE_BOTH>, - <&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + <&pdc_intc 7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_SEC_GDSC>; @@ -4760,6 +4770,7 @@ operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; + #cooling-cells = <2>; interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "gfx-mem"; @@ -5568,7 +5579,7 @@ hysteresis = <2000>; type = "hot"; }; - cluster0_crit: cluster0_crit { + cluster0_crit: cluster0-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -5588,7 +5599,7 @@ hysteresis = <2000>; type = "hot"; }; - cluster1_crit: cluster1_crit { + cluster1_crit: cluster1-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -5602,8 +5613,15 @@ thermal-sensors = <&tsens0 11>; + cooling-maps { + map0 { + trip = <&gpu_top_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - gpu1_alert0: trip-point0 { + gpu_top_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -5617,8 +5635,15 @@ thermal-sensors = <&tsens0 12>; + cooling-maps { + map0 { + trip = <&gpu_bottom_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - gpu2_alert0: trip-point0 { + gpu_bottom_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; diff --git a/src/arm64/qcom/sm4450.dtsi b/src/arm64/qcom/sm4450.dtsi index 3e7ae3bebbe..603c962661c 100644 --- a/src/arm64/qcom/sm4450.dtsi +++ b/src/arm64/qcom/sm4450.dtsi @@ -17,7 +17,7 @@ chosen { }; - clocks{ + clocks { xo_board: xo-board { compatible = "fixed-clock"; clock-frequency = <76800000>; diff --git a/src/arm64/qcom/sm6115.dtsi b/src/arm64/qcom/sm6115.dtsi index f9849b8befb..aca0a87092e 100644 --- a/src/arm64/qcom/sm6115.dtsi +++ b/src/arm64/qcom/sm6115.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -614,6 +615,11 @@ #hwlock-cells = <1>; }; + tcsr_regs: syscon@3c0000 { + compatible = "qcom,sm6115-tcsr", "syscon"; + reg = <0x0 0x003c0000 0x0 0x40000>; + }; + tlmm: pinctrl@500000 { compatible = "qcom,sm6115-tlmm"; reg = <0x0 0x00500000 0x0 0x400000>, @@ -878,8 +884,31 @@ clock-output-names = "usb3_phy_pipe_clk_src"; #phy-cells = <0>; + orientation-switch; + + qcom,tcsr-reg = <&tcsr_regs 0xb244>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_dwc3_ss>; + }; + }; + }; }; system_noc: interconnect@1880000 { @@ -1194,8 +1223,12 @@ compatible = "qcom,sm6115-qmp-ufs-phy"; reg = <0x0 0x04807000 0x0 0x1000>; - clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - clock-names = "ref", "ref_aux"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_CLKREF_CLK>; + clock-names = "ref", + "ref_aux", + "qref"; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; @@ -1589,9 +1622,14 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <66666667>; - interrupts = , + interrupts = , + , + , ; - interrupt-names = "hs_phy_irq", "ss_phy_irq"; + interrupt-names = "pwr_event", + "qusb2_phy", + "hs_phy_irq", + "ss_phy_irq"; resets = <&gcc GCC_USB30_PRIM_BCR>; power-domains = <&gcc GCC_USB30_PRIM_GDSC>; @@ -1603,7 +1641,6 @@ interconnect-names = "usb-ddr", "apps-usb"; - qcom,select-utmi-as-pipe-clk; status = "disabled"; usb_dwc3: usb@4e00000 { @@ -1618,6 +1655,28 @@ snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3_lpm_capable; + + usb-role-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dwc3_ss: endpoint { + remote-endpoint = <&usb_qmpphy_usb_ss_in>; + }; + }; + }; }; }; @@ -1649,6 +1708,7 @@ nvmem-cells = <&gpu_speed_bin>; nvmem-cell-names = "speed_bin"; + #cooling-cells = <2>; status = "disabled"; @@ -3088,7 +3148,7 @@ type = "passive"; }; - cpu4_crit: cpu_crit { + cpu4_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3114,7 +3174,7 @@ type = "passive"; }; - cpu5_crit: cpu_crit { + cpu5_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3140,7 +3200,7 @@ type = "passive"; }; - cpu6_crit: cpu_crit { + cpu6_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3166,7 +3226,7 @@ type = "passive"; }; - cpu7_crit: cpu_crit { + cpu7_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3192,7 +3252,7 @@ type = "passive"; }; - cpu45_crit: cpu_crit { + cpu45_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3218,7 +3278,7 @@ type = "passive"; }; - cpu67_crit: cpu_crit { + cpu67_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3244,7 +3304,7 @@ type = "passive"; }; - cpu0123_crit: cpu_crit { + cpu0123_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3297,8 +3357,15 @@ polling-delay = <0>; thermal-sensors = <&tsens0 15>; + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpu_alert0: trip-point0 { temperature = <115000>; hysteresis = <5000>; type = "passive"; @@ -3307,7 +3374,7 @@ trip-point1 { temperature = <125000>; hysteresis = <1000>; - type = "passive"; + type = "critical"; }; }; }; diff --git a/src/arm64/qcom/sm6125.dtsi b/src/arm64/qcom/sm6125.dtsi index 1dd3a4056e2..98ab0835608 100644 --- a/src/arm64/qcom/sm6125.dtsi +++ b/src/arm64/qcom/sm6125.dtsi @@ -812,10 +812,12 @@ compatible = "qcom,sm6125-qmp-ufs-phy"; reg = <0x04807000 0xdb8>; - clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>; clock-names = "ref", - "ref_aux"; + "ref_aux", + "qref"; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; @@ -1185,9 +1187,14 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <66666667>; - interrupts = , + interrupts = , + , + , ; - interrupt-names = "hs_phy_irq", "ss_phy_irq"; + interrupt-names = "pwr_event", + "qusb2_phy", + "hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; qcom,select-utmi-as-pipe-clk; diff --git a/src/arm64/qcom/sm6350.dtsi b/src/arm64/qcom/sm6350.dtsi index 43cffe8e124..0be05355560 100644 --- a/src/arm64/qcom/sm6350.dtsi +++ b/src/arm64/qcom/sm6350.dtsi @@ -19,6 +19,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -1189,10 +1190,12 @@ compatible = "qcom,sm6350-qmp-ufs-phy"; reg = <0 0x01d87000 0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>; clock-names = "ref", - "ref_aux"; - clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + "ref_aux", + "qref"; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; @@ -1249,7 +1252,7 @@ compatible = "qcom,sm6350-adsp-pas"; reg = <0 0x03000000 0 0x100>; - interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, @@ -1325,10 +1328,11 @@ qcom,gmu = <&gmu>; nvmem-cells = <&gpu_speed_bin>; nvmem-cell-names = "speed_bin"; + #cooling-cells = <2>; status = "disabled"; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&pil_gpu_mem>; }; @@ -1439,8 +1443,6 @@ operating-points-v2 = <&gmu_opp_table>; - status = "disabled"; - gmu_opp_table: opp-table { compatible = "operating-points-v2"; @@ -1509,7 +1511,7 @@ compatible = "qcom,sm6350-cdsp-pas"; reg = <0 0x08300000 0 0x10000>; - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, @@ -1830,12 +1832,15 @@ "mock_utmi"; interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>; - - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; @@ -1966,6 +1971,13 @@ interrupt-controller; #interrupt-cells = <1>; + interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; + clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>; @@ -2698,6 +2710,569 @@ }; }; + thermal-zones { + aoss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 0>; + + trips { + aoss0-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + aoss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 0>; + + trips { + aoss1-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + audio-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 2>; + + trips { + audio-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + camera-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 5>; + + trips { + camera-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 1>; + + trips { + cpu0_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu0_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 2>; + + trips { + cpu1_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu1_alert0>; + cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 3>; + + trips { + cpu2_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu2_alert0>; + cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 4>; + + trips { + cpu3_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu3_alert0>; + cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu4-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 5>; + + trips { + cpu4_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu4_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu5-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 6>; + + trips { + cpu5_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu5_alert0>; + cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu6-left-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 9>; + + trips { + cpu6_left_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6-left-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu6_left_alert0>; + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu6-right-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 10>; + + trips { + cpu6_right_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6-right-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu6_right_alert0>; + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu7-left-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 11>; + + trips { + cpu7_left_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7-left-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu7_left_alert0>; + cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu7-right-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 12>; + + trips { + cpu7_right_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7-right-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu7_right_alert0>; + cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpuss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 7>; + + trips { + cpuss0-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 8>; + + trips { + cpuss1-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cwlan-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 1>; + + trips { + cwlan-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + ddr-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 3>; + + trips { + ddr-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 13>; + + trips { + gpuss0_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpuss0-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpuss0_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpuss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 14>; + + trips { + gpuss1_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpuss1-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpuss1_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + modem-core0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 6>; + + trips { + modem-core0-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem-core1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 7>; + + trips { + modem-core1-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem-scl-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 9>; + + trips { + modem-scl-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem-vec-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 8>; + + trips { + modem-vec-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + npu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 10>; + + trips { + npu-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + q6-hvx-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 4>; + + trips { + q6-hvx-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 11>; + + trips { + video-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; clock-frequency = <19200000>; diff --git a/src/arm64/qcom/sm6375.dtsi b/src/arm64/qcom/sm6375.dtsi index 7ac8bf26dda..f40509d91bb 100644 --- a/src/arm64/qcom/sm6375.dtsi +++ b/src/arm64/qcom/sm6375.dtsi @@ -1431,13 +1431,15 @@ assigned-clock-rates = <19200000>, <133333333>; interrupts-extended = <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, - <&mpm 12 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <&mpm 94 IRQ_TYPE_EDGE_BOTH>, <&mpm 93 IRQ_TYPE_EDGE_BOTH>, - <&mpm 94 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", - "ss_phy_irq", + <&mpm 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", - "dp_hs_phy_irq"; + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; @@ -1559,7 +1561,7 @@ compatible = "qcom,sm6375-adsp-pas"; reg = <0 0x0a400000 0 0x100>; - interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, diff --git a/src/arm64/qcom/sm7125-xiaomi-common.dtsi b/src/arm64/qcom/sm7125-xiaomi-common.dtsi index e55cd83c19b..29289fa41b1 100644 --- a/src/arm64/qcom/sm7125-xiaomi-common.dtsi +++ b/src/arm64/qcom/sm7125-xiaomi-common.dtsi @@ -152,6 +152,9 @@ regulator-min-microvolt = <824000>; regulator-max-microvolt = <928000>; regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; }; vreg_l5a_2p7: ldo5 { @@ -188,6 +191,9 @@ regulator-min-microvolt = <1696000>; regulator-max-microvolt = <1952000>; regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; }; vreg_l13a_1p8: ldo13 { @@ -230,6 +236,9 @@ regulator-min-microvolt = <2696000>; regulator-max-microvolt = <3304000>; regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; }; }; @@ -258,6 +267,9 @@ regulator-min-microvolt = <1144000>; regulator-max-microvolt = <1304000>; regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; }; vreg_l4c_1p8: ldo4 { @@ -398,6 +410,20 @@ }; }; +&ufs_mem_hc { + vcc-supply = <&vreg_l19a_3p0>; + vcc-max-microamp = <600000>; + vccq2-supply = <&vreg_l12a_1p8>; + vccq2-max-microamp = <600000>; + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l4a_0p88>; + vdda-pll-supply = <&vreg_l3c_1p23>; + status = "okay"; +}; + &usb_1 { qcom,select-utmi-as-pipe-clk; status = "okay"; diff --git a/src/arm64/qcom/sm7125-xiaomi-curtana.dts b/src/arm64/qcom/sm7125-xiaomi-curtana.dts new file mode 100644 index 00000000000..12f517a8492 --- /dev/null +++ b/src/arm64/qcom/sm7125-xiaomi-curtana.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023, Joe Mason + */ + +/dts-v1/; + +#include "sm7125-xiaomi-common.dtsi" + +/ { + model = "Xiaomi Redmi Note 9S"; + compatible = "xiaomi,curtana", "qcom,sm7125"; + + /* required for bootloader to select correct board */ + qcom,board-id = <0x20022 1>; +}; diff --git a/src/arm64/qcom/sm7225-fairphone-fp4.dts b/src/arm64/qcom/sm7225-fairphone-fp4.dts index ade61980551..bc67e8c1fe4 100644 --- a/src/arm64/qcom/sm7225-fairphone-fp4.dts +++ b/src/arm64/qcom/sm7225-fairphone-fp4.dts @@ -68,6 +68,14 @@ }; }; + /* Dummy regulator until PM6150L has LCDB VSP/VSN support */ + lcdb_dummy: regulator-lcdb-dummy { + compatible = "regulator-fixed"; + regulator-name = "lcdb_dummy"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + }; + reserved-memory { /* * The rmtfs memory region in downstream is 'dynamically allocated' @@ -116,7 +124,7 @@ }; &adsp { - firmware-name = "qcom/sm7225/fairphone4/adsp.mdt"; + firmware-name = "qcom/sm7225/fairphone4/adsp.mbn"; status = "okay"; }; @@ -361,7 +369,7 @@ }; &cdsp { - firmware-name = "qcom/sm7225/fairphone4/cdsp.mdt"; + firmware-name = "qcom/sm7225/fairphone4/cdsp.mbn"; status = "okay"; }; @@ -373,6 +381,14 @@ status = "okay"; }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/sm7225/fairphone4/a615_zap.mbn"; +}; + &i2c0 { clock-frequency = <400000>; status = "okay"; @@ -400,12 +416,49 @@ &ipa { qcom,gsi-loader = "self"; memory-region = <&pil_ipa_fw_mem>; - firmware-name = "qcom/sm7225/fairphone4/ipa_fws.mdt"; + firmware-name = "qcom/sm7225/fairphone4/ipa_fws.mbn"; + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l22a>; + status = "okay"; + + panel@0 { + compatible = "djn,9a-3r063-1102b"; + reg = <0>; + + backlight = <&pm6150l_wled>; + reset-gpios = <&pm6150l_gpios 9 GPIO_ACTIVE_LOW>; + + vdd1-supply = <&vreg_l1e>; + vsn-supply = <&lcdb_dummy>; + vsp-supply = <&lcdb_dummy>; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&panel_in>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l18a>; status = "okay"; }; &mpss { - firmware-name = "qcom/sm7225/fairphone4/modem.mdt"; + firmware-name = "qcom/sm7225/fairphone4/modem.mbn"; status = "okay"; }; diff --git a/src/arm64/qcom/sm8150.dtsi b/src/arm64/qcom/sm8150.dtsi index 761a6757dc2..a35c0852b5a 100644 --- a/src/arm64/qcom/sm8150.dtsi +++ b/src/arm64/qcom/sm8150.dtsi @@ -967,7 +967,7 @@ #address-cells = <1>; #size-cells = <1>; - gpu_speed_bin: gpu_speed_bin@133 { + gpu_speed_bin: gpu-speed-bin@133 { reg = <0x133 0x1>; bits = <5 3>; }; @@ -1843,8 +1843,22 @@ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1858,14 +1872,16 @@ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, <&gcc GCC_PCIE_0_SLV_AXI_CLK>, <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&rpmhcc RPMH_CXO_CLK>; clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave", "slave_q2a", - "tbu"; + "tbu", + "ref"; iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, <0x100 &apps_smmu 0x1d81 0x1>; @@ -1879,7 +1895,7 @@ phy-names = "pciephy"; perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; - enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; @@ -1934,8 +1950,22 @@ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1949,14 +1979,16 @@ <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&rpmhcc RPMH_CXO_CLK>; clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave", "slave_q2a", - "tbu"; + "tbu", + "ref"; assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>; @@ -2063,10 +2095,12 @@ compatible = "qcom,sm8150-qmp-ufs-phy"; reg = <0 0x01d87000 0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>; clock-names = "ref", - "ref_aux"; - clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + "ref_aux", + "qref"; power-domains = <&gcc UFS_PHY_GDSC>; @@ -2198,6 +2232,7 @@ nvmem-cells = <&gpu_speed_bin>; nvmem-cell-names = "speed_bin"; + #cooling-cells = <2>; status = "disabled"; @@ -2428,7 +2463,7 @@ bias-disable; }; - qup_spi6_default: qup-spi6_default-state { + qup_spi6_default: qup-spi6-default-state { pins = "gpio4", "gpio5", "gpio6", "gpio7"; function = "qup6"; drive-strength = <6>; @@ -2442,7 +2477,7 @@ bias-disable; }; - qup_spi7_default: qup-spi7_default-state { + qup_spi7_default: qup-spi7-default-state { pins = "gpio98", "gpio99", "gpio100", "gpio101"; function = "qup7"; drive-strength = <6>; @@ -3573,12 +3608,16 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 9 IRQ_TYPE_EDGE_BOTH>, <&pdc 8 IRQ_TYPE_EDGE_BOTH>, - <&pdc 9 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; @@ -3645,12 +3684,16 @@ <&gcc GCC_USB30_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 7 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 11 IRQ_TYPE_EDGE_BOTH>, <&pdc 10 IRQ_TYPE_EDGE_BOTH>, - <&pdc 11 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + <&pdc 7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_SEC_GDSC>; @@ -5067,7 +5110,7 @@ hysteresis = <2000>; type = "hot"; }; - cluster0_crit: cluster0_crit { + cluster0_crit: cluster0-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -5087,7 +5130,7 @@ hysteresis = <2000>; type = "hot"; }; - cluster1_crit: cluster1_crit { + cluster1_crit: cluster1-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -5101,8 +5144,15 @@ thermal-sensors = <&tsens0 15>; + cooling-maps { + map0 { + trip = <&gpu_top_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - gpu1_alert0: trip-point0 { + gpu_top_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -5281,8 +5331,15 @@ thermal-sensors = <&tsens1 11>; + cooling-maps { + map0 { + trip = <&gpu_bottom_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - gpu2_alert0: trip-point0 { + gpu_bottom_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; diff --git a/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi b/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi index 946365f15a5..6f54f50a70b 100644 --- a/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2022, 2023 Jianhua Lu + * Copyright (c) 2022-2024 Jianhua Lu */ #include @@ -551,6 +551,7 @@ vddio-supply = <&vreg_l14a_1p88>; reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>; backlight = <&backlight>; + rotation = <90>; status = "disabled"; diff --git a/src/arm64/qcom/sm8250.dtsi b/src/arm64/qcom/sm8250.dtsi index 760501c1301..7f2333c9d17 100644 --- a/src/arm64/qcom/sm8250.dtsi +++ b/src/arm64/qcom/sm8250.dtsi @@ -975,7 +975,7 @@ #address-cells = <1>; #size-cells = <1>; - gpu_speed_bin: gpu_speed_bin@19b { + gpu_speed_bin: gpu-speed-bin@19b { reg = <0x19b 0x1>; bits = <5 3>; }; @@ -2152,8 +2152,14 @@ , , ; - interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7"; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -2248,8 +2254,22 @@ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -2349,8 +2369,22 @@ ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>, <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -2506,10 +2540,12 @@ compatible = "qcom,sm8250-qmp-ufs-phy"; reg = <0 0x01d87000 0 0x1000>; - clock-names = "ref", - "ref_aux"; clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_1X_CLKREF_EN>; + clock-names = "ref", + "ref_aux", + "qref"; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; @@ -2888,6 +2924,7 @@ nvmem-cells = <&gpu_speed_bin>; nvmem-cell-names = "speed_bin"; + #cooling-cells = <2>; status = "disabled"; @@ -3025,7 +3062,7 @@ compatible = "qcom,sm8250-slpi-pas"; reg = <0 0x05c00000 0 0x4000>; - interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, @@ -3729,7 +3766,7 @@ compatible = "qcom,sm8250-cdsp-pas"; reg = <0 0x08300000 0 0x10000>; - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, @@ -4128,14 +4165,16 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", - "ss_phy_irq", + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", - "dp_hs_phy_irq"; + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; wakeup-source; @@ -4197,14 +4236,16 @@ <&gcc GCC_USB30_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 12 IRQ_TYPE_EDGE_BOTH>, <&pdc 13 IRQ_TYPE_EDGE_BOTH>, - <&pdc 12 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", - "ss_phy_irq", + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", - "dp_hs_phy_irq"; + "ss_phy_irq"; power-domains = <&gcc USB30_SEC_GDSC>; wakeup-source; @@ -5887,7 +5928,7 @@ compatible = "qcom,sm8250-adsp-pas"; reg = <0 0x17300000 0 0x100>; - interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, @@ -6757,7 +6798,7 @@ hysteresis = <2000>; type = "hot"; }; - cluster0_crit: cluster0_crit { + cluster0_crit: cluster0-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -6777,7 +6818,7 @@ hysteresis = <2000>; type = "hot"; }; - cluster1_crit: cluster1_crit { + cluster1_crit: cluster1-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -6791,8 +6832,15 @@ thermal-sensors = <&tsens0 15>; + cooling-maps { + map0 { + trip = <&gpu_top_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - gpu1_alert0: trip-point0 { + gpu_top_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -6926,8 +6974,15 @@ thermal-sensors = <&tsens1 8>; + cooling-maps { + map0 { + trip = <&gpu_bottom_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - gpu2_alert0: trip-point0 { + gpu_bottom_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; diff --git a/src/arm64/qcom/sm8350.dtsi b/src/arm64/qcom/sm8350.dtsi index e78c83a897c..a5e7dbbd8c6 100644 --- a/src/arm64/qcom/sm8350.dtsi +++ b/src/arm64/qcom/sm8350.dtsi @@ -1526,8 +1526,14 @@ , , ; - interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7"; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1611,8 +1617,22 @@ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1726,10 +1746,12 @@ compatible = "qcom,sm8350-qmp-ufs-phy"; reg = <0 0x01d87000 0 0x1000>; - clock-names = "ref", - "ref_aux"; clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_1_CLKREF_EN>; + clock-names = "ref", + "ref_aux", + "qref"; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; @@ -1847,6 +1869,7 @@ operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; + #cooling-cells = <2>; status = "disabled"; @@ -2312,14 +2335,16 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", - "ss_phy_irq", + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", - "dp_hs_phy_irq"; + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; @@ -2385,14 +2410,16 @@ <&gcc GCC_USB30_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 12 IRQ_TYPE_EDGE_BOTH>, <&pdc 13 IRQ_TYPE_EDGE_BOTH>, - <&pdc 12 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", - "ss_phy_irq", + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", - "dp_hs_phy_irq"; + "ss_phy_irq"; power-domains = <&gcc USB30_SEC_GDSC>; @@ -4165,7 +4192,7 @@ hysteresis = <2000>; type = "hot"; }; - cluster0_crit: cluster0_crit { + cluster0_crit: cluster0-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4185,7 +4212,7 @@ hysteresis = <2000>; type = "hot"; }; - cluster1_crit: cluster1_crit { + cluster1_crit: cluster1-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4214,8 +4241,15 @@ thermal-sensors = <&tsens1 1>; + cooling-maps { + map0 { + trip = <&gpu_top_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - gpu1_alert0: trip-point0 { + gpu_top_alert0: trip-point0 { temperature = <90000>; hysteresis = <1000>; type = "hot"; @@ -4229,8 +4263,15 @@ thermal-sensors = <&tsens1 2>; + cooling-maps { + map0 { + trip = <&gpu_bottom_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - gpu2_alert0: trip-point0 { + gpu_bottom_alert0: trip-point0 { temperature = <90000>; hysteresis = <1000>; type = "hot"; diff --git a/src/arm64/qcom/sm8450-hdk.dts b/src/arm64/qcom/sm8450-hdk.dts index a20d5d76af3..0786cff07b8 100644 --- a/src/arm64/qcom/sm8450-hdk.dts +++ b/src/arm64/qcom/sm8450-hdk.dts @@ -938,8 +938,8 @@ "TX DMIC3", "MIC BIAS1", "TX SWR_INPUT0", "ADC1_OUTPUT", "TX SWR_INPUT1", "ADC2_OUTPUT", - "TX SWR_INPUT2", "ADC3_OUTPUT", - "TX SWR_INPUT3", "ADC4_OUTPUT"; + "TX SWR_INPUT0", "ADC3_OUTPUT", + "TX SWR_INPUT1", "ADC4_OUTPUT"; wcd-playback-dai-link { link-name = "WCD Playback"; @@ -1147,7 +1147,7 @@ }; &vamacro { - pinctrl-0 = <&dmic01_default>, <&dmic02_default>; + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; pinctrl-names = "default"; vdd-micb-supply = <&vreg_s10b_1p8>; qcom,dmic-sample-rate = <600000>; diff --git a/src/arm64/qcom/sm8450.dtsi b/src/arm64/qcom/sm8450.dtsi index 01e4dfc4bab..024d2653cc3 100644 --- a/src/arm64/qcom/sm8450.dtsi +++ b/src/arm64/qcom/sm8450.dtsi @@ -1028,6 +1028,12 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart20_default>; interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; status = "disabled"; }; @@ -1420,6 +1426,12 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; status = "disabled"; }; }; @@ -1765,15 +1777,25 @@ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; - /* - * MSIs for BDF (1:0.0) only works with Device ID 0x5980. - * Hence, the IDs are swapped. - */ - msi-map = <0x0 &gic_its 0x5981 0x1>, - <0x100 &gic_its 0x5980 0x1>; + msi-map = <0x0 &gic_its 0x5980 0x1>, + <0x100 &gic_its 0x5981 0x1>; msi-map-mask = <0xff00>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1874,15 +1896,25 @@ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; - /* - * MSIs for BDF (1:0.0) only works with Device ID 0x5a00. - * Hence, the IDs are swapped. - */ - msi-map = <0x0 &gic_its 0x5a01 0x1>, - <0x100 &gic_its 0x5a00 0x1>; + msi-map = <0x0 &gic_its 0x5a00 0x1>, + <0x100 &gic_its 0x5a01 0x1>; msi-map-mask = <0xff00>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -2038,6 +2070,7 @@ operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; + #cooling-cells = <2>; status = "disabled"; @@ -3934,7 +3967,7 @@ }; }; - dmic02_default: dmic02-default-state { + dmic23_default: dmic23-default-state { clk-pins { pins = "gpio8"; function = "dmic2_clk"; @@ -4485,13 +4518,15 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", - "ss_phy_irq", + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", - "dp_hs_phy_irq"; + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; @@ -4890,6 +4925,13 @@ polling-delay = <0>; thermal-sensors = <&tsens0 14>; + cooling-maps { + map0 { + trip = <&gpu_top_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { thermal-engine-config { temperature = <125000>; @@ -4909,7 +4951,7 @@ type = "passive"; }; - gpu0_tj_cfg: tj-cfg { + gpu_top_alert0: trip-point0 { temperature = <95000>; hysteresis = <5000>; type = "passive"; @@ -4922,6 +4964,13 @@ polling-delay = <0>; thermal-sensors = <&tsens0 15>; + cooling-maps { + map0 { + trip = <&gpu_bottom_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { thermal-engine-config { temperature = <125000>; @@ -4941,7 +4990,7 @@ type = "passive"; }; - gpu1_tj_cfg: tj-cfg { + gpu_bottom_alert0: trip-point0 { temperature = <95000>; hysteresis = <5000>; type = "passive"; diff --git a/src/arm64/qcom/sm8550-hdk.dts b/src/arm64/qcom/sm8550-hdk.dts new file mode 100644 index 00000000000..12d60a0ee09 --- /dev/null +++ b/src/arm64/qcom/sm8550-hdk.dts @@ -0,0 +1,1306 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Linaro Limited + */ + +/dts-v1/; + +#include +#include +#include "sm8550.dtsi" +#include "pm8010.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#define PMK8550VE_SID 5 +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" +#include "pmr735d_a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8550 HDK"; + compatible = "qcom,sm8550-hdk", "qcom,sm8550"; + chassis-type = "embedded"; + + aliases { + serial0 = &uart7; + serial1 = &uart14; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcd_default>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 108 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_out: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&volume_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_BLUETOOTH; + color = ; + gpios = <&tlmm 159 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + default-state = "off"; + }; + + led-1 { + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&tlmm 160 GPIO_ACTIVE_HIGH>; + default-state = "off"; + panic-indicator; + }; + + led-2 { + function = LED_FUNCTION_WLAN; + color = ; + gpios = <&tlmm 162 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + }; + + pmic-glink { + compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&fsa4480_sbu_mux>; + }; + }; + }; + }; + }; + + lt9611_1v2: regulator-lt9611-1v2 { + compatible = "regulator-fixed"; + + regulator-name = "LT9611_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + vin-supply = <&vph_pwr>; + gpio = <&tlmm 152 GPIO_ACTIVE_HIGH>; + + enable-active-high; + }; + + lt9611_3v3: regulator-lt9611-3v3 { + compatible = "regulator-fixed"; + + regulator-name = "LT9611_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vreg_bob_3v3>; + gpio = <&tlmm 6 GPIO_ACTIVE_HIGH>; + + enable-active-high; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + regulator-boot-on; + }; + + vreg_bob_3v3: regulator-vreg-bob-3v3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_BOB_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vph_pwr>; + }; + + sound { + compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard"; + model = "SM8550-HDK"; + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "AMIC5", "MIC BIAS4", + "TX SWR_INPUT0", "ADC1_OUTPUT", + "TX SWR_INPUT1", "ADC2_OUTPUT", + "TX SWR_INPUT1", "ADC4_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 0>, <&lpass_txmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&north_spkr>, <&south_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s6g_1p86>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l3-supply = <&vreg_s4g_1p25>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob1>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l11-supply = <&vreg_s4g_1p25>; + vdd-l12-supply = <&vreg_s6g_1p86>; + vdd-l15-supply = <&vreg_s6g_1p86>; + vdd-l17-supply = <&vreg_bob2>; + + qcom,pmic-id = "b"; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2720000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name = "vreg_l5b_3p1"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name = "vreg_l7b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name = "vreg_l8b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l11b_1p2: ldo11 { + regulator-name = "vreg_l11b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name = "vreg_l12b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name = "vreg_l14b_3p2"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name = "vreg_l16b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s4g_1p25>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4e_0p95>; + + qcom,pmic-id = "c"; + + vreg_l3c_0p9: ldo3 { + regulator-name = "vreg_l3c_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-2 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s4e_0p95>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4e_0p95>; + + qcom,pmic-id = "d"; + + vreg_l1d_0p88: ldo1 { + regulator-name = "vreg_l1d_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + /* ldo2 supplies SM8550 VDD_LPI_MX */ + }; + + regulators-3 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s4e_0p95>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4g_1p25>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + + qcom,pmic-id = "e"; + + vreg_s4e_0p95: smps4 { + regulator-name = "vreg_s4e_0p95"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <984000>; + regulator-initial-mode = ; + }; + + vreg_s5e_1p08: smps5 { + regulator-name = "vreg_s5e_1p08"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = ; + }; + + vreg_l1e_0p88: ldo1 { + regulator-name = "vreg_l1e_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2e_0p9: ldo2 { + regulator-name = "vreg_l2e_0p9"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-4 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s4e_0p95>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4e_0p95>; + vdd-s4-supply = <&vph_pwr>; + + qcom,pmic-id = "f"; + + vreg_s4f_0p5: smps4 { + regulator-name = "vreg_s4f_0p5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <700000>; + regulator-initial-mode = ; + }; + + vreg_l1f_0p9: ldo1 { + regulator-name = "vreg_l1f_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2f_0p88: ldo2 { + regulator-name = "vreg_l2f_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3f_0p88: ldo3 { + regulator-name = "vreg_l3f_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-5 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s4g_1p25>; + vdd-l2-supply = <&vreg_s4g_1p25>; + vdd-l3-supply = <&vreg_s4g_1p25>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + qcom,pmic-id = "g"; + + vreg_s1g_1p25: smps1 { + regulator-name = "vreg_s1g_1p25"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + }; + + vreg_s2g_0p85: smps2 { + regulator-name = "vreg_s2g_0p85"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = ; + }; + + vreg_s3g_0p8: smps3 { + regulator-name = "vreg_s3g_0p8"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = ; + }; + + vreg_s4g_1p25: smps4 { + regulator-name = "vreg_s4g_1p25"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = ; + }; + + vreg_s5g_0p85: smps5 { + regulator-name = "vreg_s5g_0p85"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = ; + }; + + vreg_s6g_1p86: smps6 { + regulator-name = "vreg_s6g_1p86"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1g_1p2: ldo1 { + regulator-name = "vreg_l1g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name = "vreg_l3g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-6 { + compatible = "qcom,pm8010-rpmh-regulators"; + + vdd-l1-l2-supply = <&vreg_s4g_1p25>; + vdd-l3-l4-supply = <&vreg_bob2>; + vdd-l5-supply = <&vreg_s6g_1p86>; + vdd-l6-supply = <&vreg_s6g_1p86>; + vdd-l7-supply = <&vreg_bob1>; + + qcom,pmic-id = "m"; + + vreg_l1m_1p056: ldo1 { + regulator-name = "vreg_l1m_1p056"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2m_1p056: ldo2 { + regulator-name = "vreg_l2m_1p056"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3m_2p8: ldo3 { + regulator-name = "vreg_l3m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l4m_2p8: ldo4 { + regulator-name = "vreg_l4m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l5m_1p8: ldo5 { + regulator-name = "vreg_l5m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l6m_1p8: ldo6 { + regulator-name = "vreg_l6m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l7m_2p9: ldo7 { + regulator-name = "vreg_l7m_2p9"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2904000>; + regulator-initial-mode = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8010-rpmh-regulators"; + + vdd-l1-l2-supply = <&vreg_s4g_1p25>; + vdd-l3-l4-supply = <&vreg_bob2>; + vdd-l5-supply = <&vreg_s6g_1p86>; + vdd-l6-supply = <&vreg_bob1>; + vdd-l7-supply = <&vreg_bob1>; + + qcom,pmic-id = "n"; + + vreg_l1n_1p1: ldo1 { + regulator-name = "vreg_l1n_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2n_1p1: ldo2 { + regulator-name = "vreg_l2n_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3n_2p8: ldo3 { + regulator-name = "vreg_l3n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l4n_2p8: ldo4 { + regulator-name = "vreg_l4n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l5n_1p8: ldo5 { + regulator-name = "vreg_l5n_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l6n_3p3: ldo6 { + regulator-name = "vreg_l6n_3p3"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l7n_2p96: ldo7 { + regulator-name = "vreg_l7n_2p96"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + lt9611_codec: hdmi-bridge@2b { + compatible = "lontium,lt9611uxc"; + reg = <0x2b>; + + interrupts-extended = <&tlmm 8 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>; + + vdd-supply = <<9611_1v2>; + vcc-supply = <<9611_3v3>; + + pinctrl-0 = <<9611_irq_pin>, <<9611_rst_pin>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_connector_out>; + }; + }; + }; + }; +}; + +&i2c_hub_2 { + status = "okay"; + + typec-mux@42 { + compatible = "fcs,fsa4480"; + reg = <0x42>; + + vcc-supply = <&vreg_bob1>; + + mode-switch; + orientation-switch; + + port { + fsa4480_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + }; +}; + +&i2c_master_hub_0 { + status = "okay"; +}; + +&ipa { + qcom,gsi-loader = "self"; + memory-region = <&ipa_fw_mem>; + firmware-name = "qcom/sm8550/ipa_fws.mbn"; + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm8550/a740_zap.mbn"; + }; +}; + +&lpass_tlmm { + spkr_1_sd_n_active: spkr-1-sd-n-active-state { + pins = "gpio17"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + spkr_2_sd_n_active: spkr-2-sd-n-active-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l3e_1p2>; + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l1e_0p88>; + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + remote-endpoint = <&usb_dp_qmpphy_dp_in>; + data-lanes = <0 1>; +}; + +&pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l1e_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie1 { + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie1_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l3c_0p9>; + vdda-pll-supply = <&vreg_l3e_1p2>; + vdda-qref-supply = <&vreg_l1e_0p88>; + + status = "okay"; +}; + +&pcie_1_phy_aux_clk { + clock-frequency = <1000>; +}; + +&pm8550_gpios { + sdc2_card_det_n: sdc2-card-det-state { + pins = "gpio12"; + function = "normal"; + input-enable; + output-disable; + bias-pull-up; + power-source = <1>; /* 1.8 V */ + }; + + volume_up_n: volume-up-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + +/* The RGB signals are routed to 3 separate LEDs on the HDK8550 */ +&pm8550_pwm { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + led@1 { + reg = <1>; + function = LED_FUNCTION_STATUS; + color = ; + default-state = "off"; + }; + + led@2 { + reg = <2>; + function = LED_FUNCTION_STATUS; + color = ; + default-state = "off"; + }; + + led@3 { + reg = <3>; + function = LED_FUNCTION_STATUS; + color = ; + default-state = "off"; + }; +}; + +&pm8550b_eusb2_repeater { + vdd18-supply = <&vreg_l15b_1p8>; + vdd3-supply = <&vreg_l5b_3p1>; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm8550/adsp.mbn", + "qcom/sm8550/adsp_dtb.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm8550/cdsp.mbn", + "qcom/sm8550/cdsp_dtb.mbn"; + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm8550/modem.mbn", + "qcom/sm8550/modem_dtb.mbn"; + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&sdc2_default>, <&sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep>, <&sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l8b_1p8>; + + bus-width = <4>; + no-sdio; + no-mmc; + + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&swr0 { + status = "okay"; + + /* WSA8845, Speaker North */ + north_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-names = "default"; + + powerdown-gpios = <&lpass_tlmm 17 GPIO_ACTIVE_LOW>; + + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + }; + + /* WSA8845, Speaker South */ + south_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + + pinctrl-0 = <&spkr_2_sd_n_active>; + pinctrl-names = "default"; + + powerdown-gpios = <&lpass_tlmm 18 GPIO_ACTIVE_LOW>; + + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + + /* + * WCD9385 RX Port 1 (HPH_L/R) <=> SWR1 Port 1 (HPH_L/R) + * WCD9385 RX Port 2 (CLSH) <=> SWR1 Port 2 (CLSH) + * WCD9385 RX Port 3 (COMP_L/R) <=> SWR1 Port 3 (COMP_L/R) + * WCD9385 RX Port 4 (LO) <=> SWR1 Port 4 (LO) + * WCD9385 RX Port 5 (DSD_L/R) <=> SWR1 Port 5 (DSD_L/R) + */ + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + + /* + * WCD9385 TX Port 1 (ADC1,2) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3) + * WCD9385 TX Port 2 (ADC3,4) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3) + * WCD9385 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3 (TX SWR_INPUT 4,5,6,7) + * WCD9385 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4 (TX SWR_INPUT 8,9,10,11) + */ + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&tlmm { + /* Reserved I/Os for NFC */ + gpio-reserved-ranges = <32 8>; + + bt_default: bt-default-state { + bt-en-pins { + pins = "gpio81"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + sw-ctrl-pins { + pins = "gpio82"; + function = "gpio"; + bias-pull-down; + }; + }; + + lt9611_irq_pin: lt9611-irq-state { + pins = "gpio8"; + function = "gpio"; + bias-disable; + }; + + lt9611_rst_pin: lt9611-rst-state { + pins = "gpio7"; + function = "gpio"; + output-high; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio108"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&uart7 { + status = "okay"; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_s4e_0p95>; + vdddig-supply = <&vreg_s4e_0p95>; + vddrfa0p8-supply = <&vreg_s4e_0p95>; + vddrfa1p2-supply = <&vreg_s4g_1p25>; + vddrfa1p9-supply = <&vreg_s6g_1p86>; + + max-speed = <3200000>; + + enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; + swctrl-gpios = <&tlmm 82 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&bt_default>; + pinctrl-names = "default"; + }; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <1300000>; + vccq-supply = <&vreg_l1g_1p2>; + vccq-max-microamp = <1200000>; + vdd-hba-supply = <&vreg_l3g_1p2>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l1d_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_dwc3_ss { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l1e_0p88>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&pm8550b_eusb2_repeater>; + + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3f_0p88>; + + orientation-switch; + + status = "okay"; +}; + +&usb_dp_qmpphy_dp_in { + remote-endpoint = <&mdss_dp0_out>; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_dp_qmpphy_usb_ss_in { + remote-endpoint = <&usb_1_dwc3_ss>; +}; + +&xo_board { + clock-frequency = <76800000>; +}; diff --git a/src/arm64/qcom/sm8550-mtp.dts b/src/arm64/qcom/sm8550-mtp.dts index c1135ad5fa6..3d4ad5aac70 100644 --- a/src/arm64/qcom/sm8550-mtp.dts +++ b/src/arm64/qcom/sm8550-mtp.dts @@ -106,14 +106,21 @@ "SpkrRight IN", "WSA_SPK2 OUT", "IN1_HPHL", "HPHL_OUT", "IN2_HPHR", "HPHR_OUT", + "AMIC1", "MIC BIAS1", "AMIC2", "MIC BIAS2", + "AMIC3", "MIC BIAS3", + "AMIC4", "MIC BIAS3", + "AMIC5", "MIC BIAS4", "VA DMIC0", "MIC BIAS1", "VA DMIC1", "MIC BIAS1", "VA DMIC2", "MIC BIAS3", "TX DMIC0", "MIC BIAS1", "TX DMIC1", "MIC BIAS2", "TX DMIC2", "MIC BIAS3", - "TX SWR_ADC1", "ADC2_OUTPUT"; + "TX SWR_INPUT0", "ADC1_OUTPUT", + "TX SWR_INPUT1", "ADC2_OUTPUT", + "TX SWR_INPUT0", "ADC3_OUTPUT", + "TX SWR_INPUT1", "ADC4_OUTPUT"; wcd-playback-dai-link { link-name = "WCD Playback"; @@ -874,7 +881,7 @@ wcd_tx: codec@0,3 { compatible = "sdw20217010d00"; reg = <0 3>; - qcom,tx-port-mapping = <1 1 2 3>; + qcom,tx-port-mapping = <2 2 3 4>; }; }; diff --git a/src/arm64/qcom/sm8550-qrd.dts b/src/arm64/qcom/sm8550-qrd.dts index d401d63e5c4..92f01501741 100644 --- a/src/arm64/qcom/sm8550-qrd.dts +++ b/src/arm64/qcom/sm8550-qrd.dts @@ -124,14 +124,21 @@ "SpkrRight IN", "WSA_SPK2 OUT", "IN1_HPHL", "HPHL_OUT", "IN2_HPHR", "HPHR_OUT", + "AMIC1", "MIC BIAS1", "AMIC2", "MIC BIAS2", + "AMIC3", "MIC BIAS3", + "AMIC4", "MIC BIAS3", + "AMIC5", "MIC BIAS4", "VA DMIC0", "MIC BIAS1", "VA DMIC1", "MIC BIAS1", "VA DMIC2", "MIC BIAS3", "TX DMIC0", "MIC BIAS1", "TX DMIC1", "MIC BIAS2", "TX DMIC2", "MIC BIAS3", - "TX SWR_ADC1", "ADC2_OUTPUT"; + "TX SWR_INPUT0", "ADC1_OUTPUT", + "TX SWR_INPUT1", "ADC2_OUTPUT", + "TX SWR_INPUT0", "ADC3_OUTPUT", + "TX SWR_INPUT1", "ADC4_OUTPUT"; wcd-playback-dai-link { link-name = "WCD Playback"; @@ -724,6 +731,10 @@ <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; }; +&gpi_dma1 { + status = "okay"; +}; + &gpu { status = "okay"; @@ -960,6 +971,30 @@ }; }; +&spi4 { + status = "okay"; + + touchscreen@0 { + compatible = "goodix,gt9916"; + reg = <0>; + + interrupt-parent = <&tlmm>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&tlmm 24 GPIO_ACTIVE_LOW>; + + avdd-supply = <&vreg_l14b_3p2>; + + spi-max-frequency = <1000000>; + + touchscreen-size-x = <1080>; + touchscreen-size-y = <2400>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_irq>, <&ts_reset>; + }; +}; + &swr1 { status = "okay"; @@ -978,7 +1013,7 @@ wcd_tx: codec@0,3 { compatible = "sdw20217010d00"; reg = <0 3>; - qcom,tx-port-mapping = <1 1 2 3>; + qcom,tx-port-mapping = <2 2 3 4>; }; }; @@ -1028,6 +1063,20 @@ bias-pull-down; }; + ts_irq: ts-irq-state { + pins = "gpio25"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + ts_reset: ts-reset-state { + pins = "gpio24"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + wcd_default: wcd-reset-n-active-state { pins = "gpio108"; function = "gpio"; diff --git a/src/arm64/qcom/sm8550.dtsi b/src/arm64/qcom/sm8550.dtsi index ee1ba5a8c8f..3348bc06db4 100644 --- a/src/arm64/qcom/sm8550.dtsi +++ b/src/arm64/qcom/sm8550.dtsi @@ -1713,9 +1713,22 @@ linux,pci-domain = <0>; num-lanes = <2>; - interrupts = ; - interrupt-names = "msi"; - + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1742,6 +1755,8 @@ <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; interconnect-names = "pcie-mem", "cpu-pcie"; + msi-map = <0x0 &gic_its 0x1400 0x1>, + <0x100 &gic_its 0x1401 0x1>; iommu-map = <0x0 &apps_smmu 0x1400 0x1>, <0x100 &apps_smmu 0x1401 0x1>; @@ -1804,9 +1819,22 @@ linux,pci-domain = <1>; num-lanes = <2>; - interrupts = ; - interrupt-names = "msi"; - + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1838,6 +1866,8 @@ <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>; interconnect-names = "pcie-mem", "cpu-pcie"; + msi-map = <0x0 &gic_its 0x1480 0x1>, + <0x100 &gic_its 0x1481 0x1>; iommu-map = <0x0 &apps_smmu 0x1480 0x1>, <0x100 &apps_smmu 0x1481 0x1>; @@ -1907,9 +1937,12 @@ ufs_mem_phy: phy@1d80000 { compatible = "qcom,sm8550-qmp-ufs-phy"; reg = <0x0 0x01d80000 0x0 0x2000>; - clocks = <&tcsr TCSR_UFS_CLKREF_EN>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - clock-names = "ref", "ref_aux"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsr TCSR_UFS_CLKREF_EN>; + clock-names = "ref", + "ref_aux", + "qref"; power-domains = <&gcc UFS_MEM_PHY_GDSC>; @@ -1940,6 +1973,7 @@ iommus = <&apps_smmu 0x60 0x0>; dma-coherent; + operating-points-v2 = <&ufs_opp_table>; interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; @@ -1960,18 +1994,49 @@ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; - freq-table-hz = - <75000000 300000000>, - <0 0>, - <0 0>, - <75000000 300000000>, - <100000000 403000000>, - <0 0>, - <0 0>, - <0 0>; qcom,ice = <&ice>; status = "disabled"; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <300000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; ice: crypto@1d88000 { @@ -2012,6 +2077,7 @@ operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; + #cooling-cells = <2>; status = "disabled"; @@ -2507,7 +2573,7 @@ }; }; - dmic02_default: dmic02-default-state { + dmic23_default: dmic23-default-state { clk-pins { pins = "gpio8"; function = "dmic2_clk"; @@ -3133,13 +3199,15 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", - "ss_phy_irq", + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", - "dp_hs_phy_irq"; + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; required-opps = <&rpmhpd_opp_nom>; @@ -3248,7 +3316,7 @@ spmi_bus: spmi@c400000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c400000 0 0x3000>, - <0 0x0c500000 0 0x4000000>, + <0 0x0c500000 0 0x400000>, <0 0x0c440000 0 0x80000>, <0 0x0c4c0000 0 0x20000>, <0 0x0c42d000 0 0x4000>; @@ -4254,6 +4322,7 @@ reg = <3>; iommus = <&apps_smmu 0x1003 0x80>, <&apps_smmu 0x1063 0x0>; + dma-coherent; }; compute-cb@4 { @@ -4261,6 +4330,7 @@ reg = <4>; iommus = <&apps_smmu 0x1004 0x80>, <&apps_smmu 0x1064 0x0>; + dma-coherent; }; compute-cb@5 { @@ -4268,6 +4338,7 @@ reg = <5>; iommus = <&apps_smmu 0x1005 0x80>, <&apps_smmu 0x1065 0x0>; + dma-coherent; }; compute-cb@6 { @@ -4275,6 +4346,7 @@ reg = <6>; iommus = <&apps_smmu 0x1006 0x80>, <&apps_smmu 0x1066 0x0>; + dma-coherent; }; compute-cb@7 { @@ -4282,6 +4354,7 @@ reg = <7>; iommus = <&apps_smmu 0x1007 0x80>, <&apps_smmu 0x1067 0x0>; + dma-coherent; }; }; @@ -4388,6 +4461,7 @@ iommus = <&apps_smmu 0x1961 0x0>, <&apps_smmu 0x0c01 0x20>, <&apps_smmu 0x19c1 0x10>; + dma-coherent; }; compute-cb@2 { @@ -4396,6 +4470,7 @@ iommus = <&apps_smmu 0x1962 0x0>, <&apps_smmu 0x0c02 0x20>, <&apps_smmu 0x19c2 0x10>; + dma-coherent; }; compute-cb@3 { @@ -4404,6 +4479,7 @@ iommus = <&apps_smmu 0x1963 0x0>, <&apps_smmu 0x0c03 0x20>, <&apps_smmu 0x19c3 0x10>; + dma-coherent; }; compute-cb@4 { @@ -4412,6 +4488,7 @@ iommus = <&apps_smmu 0x1964 0x0>, <&apps_smmu 0x0c04 0x20>, <&apps_smmu 0x19c4 0x10>; + dma-coherent; }; compute-cb@5 { @@ -4420,6 +4497,7 @@ iommus = <&apps_smmu 0x1965 0x0>, <&apps_smmu 0x0c05 0x20>, <&apps_smmu 0x19c5 0x10>; + dma-coherent; }; compute-cb@6 { @@ -4428,6 +4506,7 @@ iommus = <&apps_smmu 0x1966 0x0>, <&apps_smmu 0x0c06 0x20>, <&apps_smmu 0x19c6 0x10>; + dma-coherent; }; compute-cb@7 { @@ -4436,6 +4515,7 @@ iommus = <&apps_smmu 0x1967 0x0>, <&apps_smmu 0x0c07 0x20>, <&apps_smmu 0x19c7 0x10>; + dma-coherent; }; compute-cb@8 { @@ -4444,6 +4524,7 @@ iommus = <&apps_smmu 0x1968 0x0>, <&apps_smmu 0x0c08 0x20>, <&apps_smmu 0x19c8 0x10>; + dma-coherent; }; /* note: secure cb9 in downstream */ @@ -5304,6 +5385,13 @@ polling-delay = <0>; thermal-sensors = <&tsens2 1>; + cooling-maps { + map0 { + trip = <&gpu0_junction_config>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { thermal-engine-config { temperature = <125000>; @@ -5336,6 +5424,13 @@ polling-delay = <0>; thermal-sensors = <&tsens2 2>; + cooling-maps { + map0 { + trip = <&gpu1_junction_config>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { thermal-engine-config { temperature = <125000>; @@ -5368,6 +5463,13 @@ polling-delay = <0>; thermal-sensors = <&tsens2 3>; + cooling-maps { + map0 { + trip = <&gpu2_junction_config>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { thermal-engine-config { temperature = <125000>; @@ -5400,6 +5502,13 @@ polling-delay = <0>; thermal-sensors = <&tsens2 4>; + cooling-maps { + map0 { + trip = <&gpu3_junction_config>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { thermal-engine-config { temperature = <125000>; @@ -5432,6 +5541,13 @@ polling-delay = <0>; thermal-sensors = <&tsens2 5>; + cooling-maps { + map0 { + trip = <&gpu4_junction_config>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { thermal-engine-config { temperature = <125000>; @@ -5464,6 +5580,13 @@ polling-delay = <0>; thermal-sensors = <&tsens2 6>; + cooling-maps { + map0 { + trip = <&gpu5_junction_config>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { thermal-engine-config { temperature = <125000>; @@ -5496,6 +5619,13 @@ polling-delay = <0>; thermal-sensors = <&tsens2 7>; + cooling-maps { + map0 { + trip = <&gpu6_junction_config>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { thermal-engine-config { temperature = <125000>; @@ -5528,6 +5658,13 @@ polling-delay = <0>; thermal-sensors = <&tsens2 8>; + cooling-maps { + map0 { + trip = <&gpu7_junction_config>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { thermal-engine-config { temperature = <125000>; diff --git a/src/arm64/qcom/sm8650-mtp.dts b/src/arm64/qcom/sm8650-mtp.dts index be133a3d5cb..4450273f966 100644 --- a/src/arm64/qcom/sm8650-mtp.dts +++ b/src/arm64/qcom/sm8650-mtp.dts @@ -66,6 +66,29 @@ }; }; + sound { + compatible = "qcom,sm8650-sndcard", "qcom,sm8450-sndcard"; + model = "SM8650-MTP"; + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT"; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; @@ -428,6 +451,138 @@ RPMH_REGULATOR_MODE_HPM>; }; }; + + regulators-6 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "m"; + + vdd-l1-l2-supply = <&vreg_s1c_1p2>; + vdd-l3-l4-supply = <&vreg_bob2>; + vdd-l5-supply = <&vreg_s6c_1p8>; + vdd-l6-supply = <&vreg_bob1>; + vdd-l7-supply = <&vreg_bob1>; + + vreg_l1m_1p1: ldo1 { + regulator-name = "vreg_l1m_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2m_1p056: ldo2 { + regulator-name = "vreg_l2m_1p056"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3m_2p8: ldo3 { + regulator-name = "vreg_l3m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l4m_2p8: ldo4 { + regulator-name = "vreg_l4m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l5m_1p8: ldo5 { + regulator-name = "vreg_l5m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l6m_2p8: ldo6 { + regulator-name = "vreg_l6m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l7m_2p96: ldo7 { + regulator-name = "vreg_l7m_2p96"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "n"; + + vdd-l1-l2-supply = <&vreg_s1c_1p2>; + vdd-l3-l4-supply = <&vreg_s6c_1p8>; + vdd-l5-supply = <&vreg_bob2>; + vdd-l6-supply = <&vreg_bob2>; + vdd-l7-supply = <&vreg_bob1>; + + vreg_l1n_1p1: ldo1 { + regulator-name = "vreg_l1n_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2n_1p056: ldo2 { + regulator-name = "vreg_l2n_1p056"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3n_1p8: ldo3 { + regulator-name = "vreg_l3n_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l4n_1p8: ldo4 { + regulator-name = "vreg_l4n_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l5n_2p8: ldo5 { + regulator-name = "vreg_l5n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l6n_2p8: ldo6 { + regulator-name = "vreg_l6n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l7n_3p3: ldo7 { + regulator-name = "vreg_l7n_3p3"; + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + }; }; &dispcc { diff --git a/src/arm64/qcom/sm8650-qrd.dts b/src/arm64/qcom/sm8650-qrd.dts index b9151c2ddf2..b07cac2e5bc 100644 --- a/src/arm64/qcom/sm8650-qrd.dts +++ b/src/arm64/qcom/sm8650-qrd.dts @@ -77,9 +77,83 @@ reg = <1>; pmic_glink_ss_in: endpoint { - remote-endpoint = <&usb_1_dwc3_ss>; + remote-endpoint = <&redriver_ss_out>; }; }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&wcd_usbss_sbu_mux>; + }; + }; + }; + }; + }; + + sound { + compatible = "qcom,sm8650-sndcard", "qcom,sm8450-sndcard"; + model = "SM8650-QRD"; + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "AMIC3", "MIC BIAS3", + "AMIC4", "MIC BIAS3", + "AMIC5", "MIC BIAS4", + "TX SWR_INPUT0", "ADC1_OUTPUT", + "TX SWR_INPUT1", "ADC2_OUTPUT", + "TX SWR_INPUT2", "ADC3_OUTPUT", + "TX SWR_INPUT3", "ADC4_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd939x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd939x 1>, <&swr2 0>, <&lpass_txmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; }; }; }; @@ -94,6 +168,41 @@ regulator-always-on; regulator-boot-on; }; + + wcd939x: audio-codec { + compatible = "qcom,wcd9395-codec", "qcom,wcd9390-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + + mode-switch; + orientation-switch; + + port { + wcd_codec_headset_in: endpoint { + remote-endpoint = <&wcd_usbss_headset_out>; + }; + }; + }; }; &apps_rsc { @@ -436,6 +545,138 @@ RPMH_REGULATOR_MODE_HPM>; }; }; + + regulators-6 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "m"; + + vdd-l1-l2-supply = <&vreg_s1c_1p2>; + vdd-l3-l4-supply = <&vreg_bob2>; + vdd-l5-supply = <&vreg_s6c_1p8>; + vdd-l6-supply = <&vreg_bob1>; + vdd-l7-supply = <&vreg_bob1>; + + vreg_l1m_1p1: ldo1 { + regulator-name = "vreg_l1m_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2m_1p056: ldo2 { + regulator-name = "vreg_l2m_1p056"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3m_2p8: ldo3 { + regulator-name = "vreg_l3m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l4m_2p8: ldo4 { + regulator-name = "vreg_l4m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l5m_1p8: ldo5 { + regulator-name = "vreg_l5m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l6m_2p8: ldo6 { + regulator-name = "vreg_l6m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l7m_2p96: ldo7 { + regulator-name = "vreg_l7m_2p96"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "n"; + + vdd-l1-l2-supply = <&vreg_s1c_1p2>; + vdd-l3-l4-supply = <&vreg_s6c_1p8>; + vdd-l5-supply = <&vreg_bob2>; + vdd-l6-supply = <&vreg_bob2>; + vdd-l7-supply = <&vreg_bob1>; + + vreg_l1n_1p1: ldo1 { + regulator-name = "vreg_l1n_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2n_1p056: ldo2 { + regulator-name = "vreg_l2n_1p056"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3n_1p8: ldo3 { + regulator-name = "vreg_l3n_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l4n_1p8: ldo4 { + regulator-name = "vreg_l4n_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l5n_2p8: ldo5 { + regulator-name = "vreg_l5n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l6n_2p8: ldo6 { + regulator-name = "vreg_l6n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l7n_3p3: ldo7 { + regulator-name = "vreg_l7n_3p3"; + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + }; }; &dispcc { @@ -446,6 +687,78 @@ status = "okay"; }; +&i2c3 { + status = "okay"; + + wcd_usbss: typec-mux@e { + compatible = "qcom,wcd9395-usbss", "qcom,wcd9390-usbss"; + reg = <0xe>; + + vdd-supply = <&vreg_l15b_1p8>; + reset-gpios = <&tlmm 152 GPIO_ACTIVE_HIGH>; + + mode-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + wcd_usbss_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + + port@1 { + reg = <1>; + + wcd_usbss_headset_out: endpoint { + remote-endpoint = <&wcd_codec_headset_in>; + }; + }; + }; + }; +}; + +&i2c6 { + status = "okay"; + + typec-mux@1c { + compatible = "onnn,nb7vpq904m"; + reg = <0x1c>; + + vcc-supply = <&vreg_l15b_1p8>; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + redriver_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + redriver_ss_in: endpoint { + data-lanes = <3 2 1 0>; + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + }; + }; +}; + &ipa { qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; @@ -453,6 +766,16 @@ status = "okay"; }; +&lpass_tlmm { + spkr_1_sd_n_active: spkr-1-sd-n-active-state { + pins = "gpio21"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + &mdss { status = "okay"; }; @@ -495,6 +818,15 @@ status = "okay"; }; +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1>; + remote-endpoint = <&usb_dp_qmpphy_dp_in>; +}; + &mdss_mdp { status = "okay"; }; @@ -600,6 +932,11 @@ status = "okay"; }; +&qup_i2c3_data_clk { + /* Use internal I2C pull-up */ + bias-pull-up = <2200>; +}; + &qupv3_id_0 { status = "okay"; }; @@ -657,6 +994,74 @@ }; }; +&swr0 { + status = "okay"; + + /* WSA8845, Speaker Left */ + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-names = "default"; + powerdown-gpios = <&lpass_tlmm 21 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l3c_1p2>; + }; + + /* WSA8845, Speaker Right */ + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + pinctrl-0 = <&spkr_2_sd_n_active>; + pinctrl-names = "default"; + powerdown-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l3c_1p2>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9395 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010e00"; + reg = <0 4>; + + /* + * WCD9395 RX Port 1 (HPH_L/R) <=> SWR1 Port 1 (HPH_L/R) + * WCD9395 RX Port 2 (CLSH) <=> SWR1 Port 2 (CLSH) + * WCD9395 RX Port 3 (COMP_L/R) <=> SWR1 Port 3 (COMP_L/R) + * WCD9395 RX Port 4 (LO) <=> SWR1 Port 4 (LO) + * WCD9395 RX Port 5 (DSD_L/R) <=> SWR1 Port 5 (DSD_L/R) + * WCD9395 RX Port 6 (HIFI_PCM_L/R) <=> SWR1 Port 9 (HIFI_PCM_L/R) + */ + qcom,rx-port-mapping = <1 2 3 4 5 9>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9395 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010e00"; + reg = <0 3>; + + /* + * WCD9395 TX Port 1 (ADC1,2,3,4) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3) + * WCD9395 TX Port 2 (ADC3,4 & DMIC0,1) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3) + * WCD9395 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3 (TX SWR_INPUT 4,5,6,7) + * WCD9395 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4 (TX SWR_INPUT 8,9,10,11) + */ + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + &tlmm { /* Reserved I/Os for NFC */ gpio-reserved-ranges = <32 8>, <74 1>; @@ -704,6 +1109,14 @@ bias-pull-down; }; + spkr_2_sd_n_active: spkr-2-sd-n-active-state { + pins = "gpio77"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + ts_irq: ts-irq-state { pins = "gpio161"; function = "gpio"; @@ -718,6 +1131,14 @@ drive-strength = <8>; bias-pull-up; }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio107"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; }; &uart14 { @@ -787,7 +1208,7 @@ }; &usb_1_dwc3_ss { - remote-endpoint = <&pmic_glink_ss_in>; + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; }; &usb_1_hsphy { @@ -803,9 +1224,23 @@ vdda-phy-supply = <&vreg_l3i_1p2>; vdda-pll-supply = <&vreg_l3g_0p91>; + orientation-switch; + status = "okay"; }; +&usb_dp_qmpphy_dp_in { + remote-endpoint = <&mdss_dp0_out>; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&redriver_ss_in>; +}; + +&usb_dp_qmpphy_usb_ss_in { + remote-endpoint = <&usb_1_dwc3_ss>; +}; + &xo_board { clock-frequency = <76800000>; }; diff --git a/src/arm64/qcom/sm8650.dtsi b/src/arm64/qcom/sm8650.dtsi index 2df77123a8c..eb117866e59 100644 --- a/src/arm64/qcom/sm8650.dtsi +++ b/src/arm64/qcom/sm8650.dtsi @@ -525,6 +525,11 @@ no-map; }; + qlink_logging_mem: qlink-logging@84800000 { + reg = <0 0x84800000 0 0x200000>; + no-map; + }; + mpss_dsm_mem: mpss-dsm@86b00000 { reg = <0 0x86b00000 0 0x4900000>; no-map; @@ -1228,7 +1233,7 @@ clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; @@ -1250,7 +1255,7 @@ clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; @@ -2213,8 +2218,22 @@ <0 0x60100000 0 0x100000>; reg-names = "parf", "dbi", "elbi", "atu", "config"; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; clocks = <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, @@ -2255,6 +2274,10 @@ interrupt-map-mask = <0 0 0 0x7>; #interrupt-cells = <1>; + msi-map = <0x0 &gic_its 0x1400 0x1>, + <0x100 &gic_its 0x1401 0x1>; + msi-map-mask = <0xff00>; + linux,pci-domain = <0>; num-lanes = <2>; bus-range = <0 0xff>; @@ -2317,8 +2340,22 @@ "atu", "config"; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; clocks = <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, @@ -2364,6 +2401,10 @@ interrupt-map-mask = <0 0 0 0x7>; #interrupt-cells = <1>; + msi-map = <0x0 &gic_its 0x1480 0x1>, + <0x100 &gic_its 0x1481 0x1>; + msi-map-mask = <0xff00>; + linux,pci-domain = <1>; num-lanes = <2>; bus-range = <0 0xff>; @@ -2448,10 +2489,12 @@ compatible = "qcom,sm8650-qmp-ufs-phy"; reg = <0 0x01d80000 0 0x2000>; - clocks = <&tcsr TCSR_UFS_CLKREF_EN>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsr TCSR_UFS_CLKREF_EN>; clock-names = "ref", - "ref_aux"; + "ref_aux", + "qref"; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; @@ -2627,7 +2670,8 @@ "mss"; memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, - <&mpss_dsm_mem>, <&mpss_dsm_mem_2>; + <&mpss_dsm_mem>, <&mpss_dsm_mem_2>, + <&qlink_logging_mem>; qcom,qmp = <&aoss_qmp>; @@ -2919,7 +2963,7 @@ }; }; - dmic02_default: dmic02-default-state { + dmic23_default: dmic23-default-state { clk-pins { pins = "gpio8"; function = "dmic2_clk"; @@ -3703,7 +3747,7 @@ spmi_bus: spmi@c400000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c400000 0 0x3000>, - <0 0x0c500000 0 0x4000000>, + <0 0x0c500000 0 0x400000>, <0 0x0c440000 0 0x80000>, <0 0x0c4c0000 0 0x20000>, <0 0x0c42d000 0 0x4000>; @@ -4808,6 +4852,7 @@ iommus = <&apps_smmu 0x1003 0x80>, <&apps_smmu 0x1043 0x20>; + dma-coherent; }; compute-cb@4 { @@ -4816,6 +4861,7 @@ iommus = <&apps_smmu 0x1004 0x80>, <&apps_smmu 0x1044 0x20>; + dma-coherent; }; compute-cb@5 { @@ -4824,6 +4870,7 @@ iommus = <&apps_smmu 0x1005 0x80>, <&apps_smmu 0x1045 0x20>; + dma-coherent; }; compute-cb@6 { @@ -4832,6 +4879,7 @@ iommus = <&apps_smmu 0x1006 0x80>, <&apps_smmu 0x1046 0x20>; + dma-coherent; }; compute-cb@7 { @@ -4841,6 +4889,7 @@ iommus = <&apps_smmu 0x1007 0x40>, <&apps_smmu 0x1067 0x0>, <&apps_smmu 0x1087 0x0>; + dma-coherent; }; }; @@ -4961,6 +5010,7 @@ iommus = <&apps_smmu 0x1961 0x0>, <&apps_smmu 0x0c01 0x20>, <&apps_smmu 0x19c1 0x0>; + dma-coherent; }; compute-cb@2 { @@ -4970,6 +5020,7 @@ iommus = <&apps_smmu 0x1962 0x0>, <&apps_smmu 0x0c02 0x20>, <&apps_smmu 0x19c2 0x0>; + dma-coherent; }; compute-cb@3 { @@ -4979,6 +5030,7 @@ iommus = <&apps_smmu 0x1963 0x0>, <&apps_smmu 0x0c03 0x20>, <&apps_smmu 0x19c3 0x0>; + dma-coherent; }; compute-cb@4 { @@ -4988,6 +5040,7 @@ iommus = <&apps_smmu 0x1964 0x0>, <&apps_smmu 0x0c04 0x20>, <&apps_smmu 0x19c4 0x0>; + dma-coherent; }; compute-cb@5 { @@ -4997,6 +5050,7 @@ iommus = <&apps_smmu 0x1965 0x0>, <&apps_smmu 0x0c05 0x20>, <&apps_smmu 0x19c5 0x0>; + dma-coherent; }; compute-cb@6 { @@ -5006,6 +5060,7 @@ iommus = <&apps_smmu 0x1966 0x0>, <&apps_smmu 0x0c06 0x20>, <&apps_smmu 0x19c6 0x0>; + dma-coherent; }; compute-cb@7 { @@ -5015,6 +5070,7 @@ iommus = <&apps_smmu 0x1967 0x0>, <&apps_smmu 0x0c07 0x20>, <&apps_smmu 0x19c7 0x0>; + dma-coherent; }; compute-cb@8 { @@ -5024,6 +5080,7 @@ iommus = <&apps_smmu 0x1968 0x0>, <&apps_smmu 0x0c08 0x20>, <&apps_smmu 0x19c8 0x0>; + dma-coherent; }; }; }; diff --git a/src/arm64/qcom/x1e80100-crd.dts b/src/arm64/qcom/x1e80100-crd.dts index 7532d8eca2d..6a0a54532e5 100644 --- a/src/arm64/qcom/x1e80100-crd.dts +++ b/src/arm64/qcom/x1e80100-crd.dts @@ -18,10 +18,124 @@ serial0 = &uart21; }; + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcd_default>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + chosen { stdout-path = "serial0:115200n8"; }; + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-CRD"; + audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT", + "TwitterLeft IN", "WSA WSA_SPK2 OUT", + "WooferRight IN", "WSA2 WSA_SPK2 OUT", + "TwitterRight IN", "WSA2 WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS3", + "VA DMIC1", "MIC BIAS3", + "VA DMIC2", "MIC BIAS1", + "VA DMIC3", "MIC BIAS1", + "VA DMIC0", "VA MIC BIAS3", + "VA DMIC1", "VA MIC BIAS3", + "VA DMIC2", "VA MIC BIAS1", + "VA DMIC3", "VA MIC BIAS1", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 0>, <&lpass_txmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_woofer>, <&left_tweeter>, + <&swr0 0>, <&lpass_wsamacro 0>, + <&right_woofer>, <&right_tweeter>, + <&swr3 0>, <&lpass_wsa2macro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; @@ -401,10 +515,251 @@ }; }; +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + spkr_23_sd_n_active: spkr-23-sd-n-active-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp3 { + compatible = "qcom,x1e80100-dp"; + /delete-property/ #sound-dai-cells; + + data-lanes = <0 1 2 3>; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + power-supply = <&vreg_edp_3p3>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + mdss_dp3_out: endpoint { + remote-endpoint = <&edp_panel_in>; + }; + }; + }; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie6a { + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + &qupv3_2 { status = "okay"; }; +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/adsp.mbn", + "qcom/x1e80100/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/cdsp.mbn", + "qcom/x1e80100/cdsp_dtb.mbn"; + + status = "okay"; +}; + +&swr0 { + status = "okay"; + + /* WSA8845, Left Woofer */ + left_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + pinctrl-0 = <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + powerdown-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + }; + + /* WSA8845, Left Tweeter */ + left_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + /* pinctrl in left_woofer node because of sharing the GPIO*/ + powerdown-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TwitterLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <1 1 2 3>; + }; +}; + +&swr3 { + status = "okay"; + + /* WSA8845, Right Woofer */ + right_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + pinctrl-0 = <&spkr_23_sd_n_active>; + pinctrl-names = "default"; + powerdown-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + }; + + /* WSA8845, Right Tweeter */ + right_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + /* pinctrl in right_woofer node because of sharing the GPIO*/ + powerdown-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TwitterRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + }; +}; + &tlmm { gpio-reserved-ranges = <34 2>, /* Unused */ <44 4>, /* SPI (TPM) */ @@ -416,9 +771,104 @@ drive-strength = <16>; bias-disable; }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-disable; + }; + + ts0_default: ts0-default-state { + int-n-pins { + pins = "gpio51"; + function = "gpio"; + bias-disable; + }; + + reset-n-pins { + pins = "gpio48"; + function = "gpio"; + output-high; + drive-strength = <16>; + }; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; }; &uart21 { compatible = "qcom,geni-debug-uart"; status = "okay"; }; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + status = "okay"; +}; + +&usb_1_ss0 { + status = "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode = "host"; + usb-role-switch; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + status = "okay"; +}; + +&usb_1_ss1 { + status = "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode = "host"; + usb-role-switch; +}; + +&usb_1_ss2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1_ss2_qmpphy { + status = "okay"; +}; + +&usb_1_ss2 { + status = "okay"; +}; + +&usb_1_ss2_dwc3 { + dr_mode = "host"; + usb-role-switch; +}; diff --git a/src/arm64/qcom/x1e80100-qcp.dts b/src/arm64/qcom/x1e80100-qcp.dts index a37ad9475c9..e76d29053d7 100644 --- a/src/arm64/qcom/x1e80100-qcp.dts +++ b/src/arm64/qcom/x1e80100-qcp.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include #include "x1e80100.dtsi" @@ -31,6 +32,23 @@ regulator-always-on; regulator-boot-on; }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-always-on; + regulator-boot-on; + }; }; &apps_rsc { @@ -243,7 +261,7 @@ qcom,pmic-id = "e"; vdd-l2-supply = <&vreg_s1f_0p7>; - vdd-l3-supply = <&vph_pwr>; + vdd-l3-supply = <&vreg_s5j_1p2>; vreg_l2e_0p8: ldo2 { regulator-name = "vreg_l2e_0p8"; @@ -349,7 +367,7 @@ qcom,pmic-id = "j"; vdd-l1-supply = <&vreg_s1f_0p7>; - vdd-l2-supply = <&vph_pwr>; + vdd-l2-supply = <&vreg_s5j_1p2>; vdd-l3-supply = <&vreg_s1f_0p7>; vdd-s5-supply = <&vph_pwr>; @@ -383,17 +401,170 @@ }; }; +&mdss { + status = "okay"; +}; + +&mdss_dp3 { + compatible = "qcom,x1e80100-dp"; + /delete-property/ #sound-dai-cells; + + data-lanes = <0 1 2 3>; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + power-supply = <&vreg_edp_3p3>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + mdss_dp3_out: endpoint { + remote-endpoint = <&edp_panel_in>; + }; + }; + }; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie6a { + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + &qupv3_2 { status = "okay"; }; +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/adsp.mbn", + "qcom/x1e80100/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/cdsp.mbn", + "qcom/x1e80100/cdsp_dtb.mbn"; + + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <33 3>, /* Unused */ <44 4>, /* SPI (TPM) */ <238 1>; /* UFS Reset */ + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; }; &uart21 { compatible = "qcom,geni-debug-uart"; status = "okay"; }; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + status = "okay"; +}; + +&usb_1_ss0 { + status = "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode = "host"; + usb-role-switch; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + status = "okay"; +}; + +&usb_1_ss1 { + status = "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode = "host"; + usb-role-switch; +}; + +&usb_1_ss2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1_ss2_qmpphy { + status = "okay"; +}; + +&usb_1_ss2 { + status = "okay"; +}; + +&usb_1_ss2_dwc3 { + dr_mode = "host"; + usb-role-switch; +}; diff --git a/src/arm64/qcom/x1e80100.dtsi b/src/arm64/qcom/x1e80100.dtsi index 6f75fc342ce..6b40082bac6 100644 --- a/src/arm64/qcom/x1e80100.dtsi +++ b/src/arm64/qcom/x1e80100.dtsi @@ -4,14 +4,20 @@ */ #include +#include #include +#include #include #include #include #include +#include +#include #include #include +#include #include +#include / { interrupt-parent = <&intc>; @@ -278,7 +284,7 @@ domain-idle-states { CLUSTER_CL4: cluster-sleep-0 { - compatible = "arm,idle-state"; + compatible = "domain-idle-state"; idle-state-name = "l2-ret"; arm,psci-suspend-param = <0x01000044>; entry-latency-us = <350>; @@ -287,7 +293,7 @@ }; CLUSTER_CL5: cluster-sleep-1 { - compatible = "arm,idle-state"; + compatible = "domain-idle-state"; idle-state-name = "ret-pll-off"; arm,psci-suspend-param = <0x01000054>; entry-latency-us = <2200>; @@ -395,16 +401,24 @@ CLUSTER_PD0: power-domain-cpu-cluster0 { #power-domain-cells = <0>; domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; + power-domains = <&SYSTEM_PD>; }; CLUSTER_PD1: power-domain-cpu-cluster1 { #power-domain-cells = <0>; domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; + power-domains = <&SYSTEM_PD>; }; CLUSTER_PD2: power-domain-cpu-cluster2 { #power-domain-cells = <0>; domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; + power-domains = <&SYSTEM_PD>; + }; + + SYSTEM_PD: power-domain-system { + #power-domain-cells = <0>; + /* TODO: system-wide idle states */ }; }; @@ -662,6 +676,58 @@ }; }; + smp2p-adsp { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <443>, <429>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <94>, <432>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { compatible = "simple-bus"; @@ -677,13 +743,13 @@ clocks = <&bi_tcxo_div2>, <&sleep_clk>, <0>, + <&pcie4_phy>, <0>, + <&pcie6a_phy>, <0>, - <0>, - <0>, - <0>, - <0>, - <0>; + <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; power-domains = <&rpmhpd RPMHPD_CX>; #clock-cells = <1>; @@ -691,6 +757,17 @@ #power-domain-cells = <1>; }; + ipcc: mailbox@408000 { + compatible = "qcom,x1e80100-ipcc", "qcom,ipcc"; + reg = <0 0x00408000 0 0x1000>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + + #mbox-cells = <2>; + }; + gpi_dma2: dma-controller@800000 { compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x00800000 0 0x60000>; @@ -1139,7 +1216,7 @@ clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; @@ -2428,6 +2505,126 @@ }; }; + usb_1_ss0_hsphy: phy@fd3000 { + compatible = "qcom,x1e80100-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg = <0 0x00fd3000 0 0x154>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + status = "disabled"; + }; + + usb_1_ss0_qmpphy: phy@fd5000 { + compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; + reg = <0 0x00fd5000 0 0x4000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe"; + + power-domains = <&gcc GCC_USB_0_PHY_GDSC>; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB4_0_DP0_PHY_PRIM_BCR>; + reset-names = "phy", + "common"; + + #clock-cells = <1>; + #phy-cells = <1>; + + status = "disabled"; + }; + + usb_1_ss1_hsphy: phy@fd9000 { + compatible = "qcom,x1e80100-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg = <0 0x00fd9000 0 0x154>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + + status = "disabled"; + }; + + usb_1_ss1_qmpphy: phy@fda000 { + compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; + reg = <0 0x00fda000 0 0x4000>; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe"; + + power-domains = <&gcc GCC_USB_1_PHY_GDSC>; + + resets = <&gcc GCC_USB3_PHY_SEC_BCR>, + <&gcc GCC_USB4_1_DP0_PHY_SEC_BCR>; + reset-names = "phy", + "common"; + + #clock-cells = <1>; + #phy-cells = <1>; + + status = "disabled"; + }; + + usb_1_ss2_hsphy: phy@fde000 { + compatible = "qcom,x1e80100-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg = <0 0x00fde000 0 0x154>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; + + status = "disabled"; + }; + + usb_1_ss2_qmpphy: phy@fdf000 { + compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; + reg = <0 0x00fdf000 0 0x4000>; + + clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe"; + + power-domains = <&gcc GCC_USB_2_PHY_GDSC>; + + resets = <&gcc GCC_USB3_PHY_TERT_BCR>, + <&gcc GCC_USB4_2_DP0_PHY_TERT_BCR>; + reset-names = "phy", + "common"; + + #clock-cells = <1>; + #phy-cells = <1>; + + status = "disabled"; + }; + cnoc_main: interconnect@1500000 { compatible = "qcom,x1e80100-cnoc-main"; reg = <0 0x1500000 0 0x14400>; @@ -2536,12 +2733,258 @@ #interconnect-cells = <2>; }; + pcie6a: pci@1bf8000 { + device_type = "pci"; + compatible = "qcom,pcie-x1e80100"; + reg = <0 0x01bf8000 0 0x3000>, + <0 0x70000000 0 0xf1d>, + <0 0x70000f20 0 0xa8>, + <0 0x70001000 0 0x1000>, + <0 0x70100000 0 0x100000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0 0x00000000 0 0x70200000 0 0x100000>, + <0x02000000 0 0x70300000 0 0x70300000 0 0x3d00000>; + bus-range = <0 0xff>; + + dma-coherent; + + linux,pci-domain = <7>; + num-lanes = <2>; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 844 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 845 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 772 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_6A_AUX_CLK>, + <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, + <&gcc GCC_PCIE_6A_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_6A_SLV_AXI_CLK>, + <&gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>, + <&gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr", + "cnoc_sf_axi"; + + assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + resets = <&gcc GCC_PCIE_6A_BCR>, + <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc GCC_PCIE_6A_GDSC>; + + phys = <&pcie6a_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie6a_phy: phy@1bfc000 { + compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy"; + reg = <0 0x01bfc000 0 0x2000>; + + clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>, + <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_6A_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe"; + + resets = <&gcc GCC_PCIE_6A_PHY_BCR>, + <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; + + assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie6a_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie4: pci@1c08000 { + device_type = "pci"; + compatible = "qcom,pcie-x1e80100"; + reg = <0 0x01c08000 0 0x3000>, + <0 0x7c000000 0 0xf1d>, + <0 0x7c000f40 0 0xa8>, + <0 0x7c001000 0 0x1000>, + <0 0x7c100000 0 0x100000>, + <0 0x01c0b000 0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0 0x00000000 0 0x7c200000 0 0x100000>, + <0x02000000 0 0x7c300000 0 0x7c300000 0 0x3d00000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <5>; + num-lanes = <2>; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_4_AUX_CLK>, + <&gcc GCC_PCIE_4_CFG_AHB_CLK>, + <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_4_SLV_AXI_CLK>, + <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, + <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr", + "cnoc_sf_axi"; + + assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_south_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + resets = <&gcc GCC_PCIE_4_BCR>, + <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc GCC_PCIE_4_GDSC>; + + phys = <&pcie4_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie4_phy: phy@1c0e000 { + compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy"; + reg = <0 0x01c0e000 0 0x2000>; + + clocks = <&gcc GCC_PCIE_4_AUX_CLK>, + <&gcc GCC_PCIE_4_CFG_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_4_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe"; + + resets = <&gcc GCC_PCIE_4_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie4_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0 0x01f40000 0 0x20000>; #hwlock-cells = <1>; }; + tcsr: clock-controller@1fc0000 { + compatible = "qcom,x1e80100-tcsr", "syscon"; + reg = <0 0x01fc0000 0 0x30000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + gem_noc: interconnect@26400000 { compatible = "qcom,x1e80100-gem-noc"; reg = <0 0x26400000 0 0x311200>; @@ -2560,6 +3003,331 @@ #interconnect-cells = <2>; }; + lpass_wsa2macro: codec@6aa0000 { + compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; + reg = <0 0x06aa0000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "wsa2-mclk"; + #sound-dai-cells = <1>; + sound-name-prefix = "WSA2"; + }; + + swr3: soundwire@6ab0000 { + compatible = "qcom,soundwire-v2.0.0"; + reg = <0 0x06ab0000 0 0x10000>; + clocks = <&lpass_wsa2macro>; + clock-names = "iface"; + interrupts = ; + label = "WSA2"; + + pinctrl-0 = <&wsa2_swr_active>; + pinctrl-names = "default"; + + qcom,din-ports = <4>; + qcom,dout-ports = <9>; + + qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; + qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; + qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + status = "disabled"; + }; + + lpass_rxmacro: codec@6ac0000 { + compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; + reg = <0 0x06ac0000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + }; + + swr1: soundwire@6ad0000 { + compatible = "qcom,soundwire-v2.0.0"; + reg = <0 0x06ad0000 0 0x10000>; + clocks = <&lpass_rxmacro>; + clock-names = "iface"; + interrupts = ; + label = "RX"; + + pinctrl-0 = <&rx_swr_active>; + pinctrl-names = "default"; + + qcom,din-ports = <1>; + qcom,dout-ports = <11>; + + qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + status = "disabled"; + }; + + lpass_txmacro: codec@6ae0000 { + compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; + reg = <0 0x06ae0000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + }; + + lpass_wsamacro: codec@6b00000 { + compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; + reg = <0 0x06b00000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + sound-name-prefix = "WSA"; + }; + + swr0: soundwire@6b10000 { + compatible = "qcom,soundwire-v2.0.0"; + reg = <0 0x06b10000 0 0x10000>; + clocks = <&lpass_wsamacro>; + clock-names = "iface"; + interrupts = ; + label = "WSA"; + + pinctrl-0 = <&wsa_swr_active>; + pinctrl-names = "default"; + + qcom,din-ports = <4>; + qcom,dout-ports = <9>; + + qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; + qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; + qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + status = "disabled"; + }; + + swr2: soundwire@6d30000 { + compatible = "qcom,soundwire-v2.0.0"; + reg = <0 0x06d30000 0 0x10000>; + clocks = <&lpass_txmacro>; + clock-names = "iface"; + interrupts = , + ; + interrupt-names = "core", "wakeup"; + label = "TX"; + + pinctrl-0 = <&tx_swr_active>; + pinctrl-names = "default"; + + qcom,din-ports = <4>; + qcom,dout-ports = <1>; + + qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>; + + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + status = "disabled"; + }; + + lpass_vamacro: codec@6d44000 { + compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; + reg = <0 0x06d44000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk", + "macro", + "dcodec"; + + #clock-cells = <0>; + clock-output-names = "fsgen"; + #sound-dai-cells = <1>; + }; + + lpass_tlmm: pinctrl@6e80000 { + compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl"; + reg = <0 0x06e80000 0 0x20000>, + <0 0x07250000 0 0x10000>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 23>; + + tx_swr_active: tx-swr-active-state { + clk-pins { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio1", "gpio2"; + function = "swr_tx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + rx_swr_active: rx-swr-active-state { + clk-pins { + pins = "gpio3"; + function = "swr_rx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio4", "gpio5"; + function = "swr_rx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + dmic01_default: dmic01-default-state { + clk-pins { + pins = "gpio6"; + function = "dmic1_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio7"; + function = "dmic1_data"; + drive-strength = <8>; + input-enable; + }; + }; + + dmic23_default: dmic23-default-state { + clk-pins { + pins = "gpio8"; + function = "dmic2_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio9"; + function = "dmic2_data"; + drive-strength = <8>; + input-enable; + }; + }; + + wsa_swr_active: wsa-swr-active-state { + clk-pins { + pins = "gpio10"; + function = "wsa_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio11"; + function = "wsa_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + wsa2_swr_active: wsa2-swr-active-state { + clk-pins { + pins = "gpio15"; + function = "wsa2_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio16"; + function = "wsa2_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + }; + lpass_ag_noc: interconnect@7e40000 { compatible = "qcom,x1e80100-lpass-ag-noc"; reg = <0 0x7e40000 0 0xE080>; @@ -2587,6 +3355,849 @@ #interconnect-cells = <2>; }; + usb_2_hsphy: phy@88e0000 { + compatible = "qcom,x1e80100-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg = <0 0x088e0000 0 0x154>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; + + status = "disabled"; + }; + + usb_1_ss2: usb@a0f8800 { + compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; + reg = <0 0x0a0f8800 0 0x400>; + + clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, + <&gcc GCC_USB30_TERT_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, + <&gcc GCC_USB30_TERT_SLEEP_CLK>, + <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr", + "noc_aggr_north", + "noc_aggr_south", + "noc_sys"; + + assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_TERT_MASTER_CLK>; + assigned-clock-rates = <19200000>, + <200000000>; + + interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 58 IRQ_TYPE_EDGE_BOTH>, + <&pdc 57 IRQ_TYPE_EDGE_BOTH>, + <&pdc 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc GCC_USB30_TERT_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_TERT_BCR>; + + interconnects = <&usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "usb-ddr", + "apps-usb"; + + wakeup-source; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + usb_1_ss2_dwc3: usb@a000000 { + compatible = "snps,dwc3"; + reg = <0 0x0a000000 0 0xcd00>; + + interrupts = ; + + iommus = <&apps_smmu 0x14a0 0x0>; + + phys = <&usb_1_ss2_hsphy>, + <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,usb3_lpm_capable; + + dma-coherent; + + port { + usb_1_ss2_role_switch: endpoint { + }; + }; + }; + }; + + usb_2: usb@a2f8800 { + compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; + reg = <0 0x0a2f8800 0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr", + "noc_aggr_north", + "noc_aggr_south", + "noc_sys"; + + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 50 IRQ_TYPE_EDGE_BOTH>, + <&pdc 49 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq"; + + power-domains = <&gcc GCC_USB20_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB20_PRIM_BCR>; + + interconnects = <&usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "usb-ddr", + "apps-usb"; + + wakeup-source; + + status = "disabled"; + + usb_2_dwc3: usb@a200000 { + compatible = "snps,dwc3"; + reg = <0 0x0a200000 0 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x14e0 0x0>; + phys = <&usb_2_hsphy>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + + port { + usb_2_role_switch: endpoint { + }; + }; + }; + }; + + usb_1_ss0: usb@a6f8800 { + compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr", + "noc_aggr_north", + "noc_aggr_south", + "noc_sys"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, + <200000000>; + + interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 61 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + wakeup-source; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + usb_1_ss0_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xcd00>; + + interrupts = ; + + iommus = <&apps_smmu 0x1420 0x0>; + + phys = <&usb_1_ss0_hsphy>, + <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,usb3_lpm_capable; + + dma-coherent; + + port { + usb_1_ss0_role_switch: endpoint { + }; + }; + }; + }; + + usb_1_ss1: usb@a8f8800 { + compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; + reg = <0 0x0a8f8800 0 0x400>; + + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr", + "noc_aggr_north", + "noc_aggr_south", + "noc_sys"; + + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>; + assigned-clock-rates = <19200000>, + <200000000>; + + interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 60 IRQ_TYPE_EDGE_BOTH>, + <&pdc 11 IRQ_TYPE_EDGE_BOTH>, + <&pdc 47 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc GCC_USB30_SEC_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_SEC_BCR>; + + interconnects = <&usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "usb-ddr", + "apps-usb"; + + wakeup-source; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + usb_1_ss1_dwc3: usb@a800000 { + compatible = "snps,dwc3"; + reg = <0 0x0a800000 0 0xcd00>; + + interrupts = ; + + iommus = <&apps_smmu 0x1460 0x0>; + + phys = <&usb_1_ss1_hsphy>, + <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,usb3_lpm_capable; + + dma-coherent; + + port { + usb_1_ss1_role_switch: endpoint { + }; + }; + }; + }; + + mdss: display-subsystem@ae00000 { + compatible = "qcom,x1e80100-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + interrupts = ; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; + + power-domains = <&dispcc MDSS_GDSC>; + + iommus = <&apps_smmu 0x1c00 0x2>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,x1e80100-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", + "vbif"; + + interrupts-extended = <&mdss 0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; + + port@4 { + reg = <4>; + + mdss_intf4_out: endpoint { + remote-endpoint = <&mdss_dp1_in>; + }; + }; + + port@5 { + reg = <5>; + + mdss_intf5_out: endpoint { + remote-endpoint = <&mdss_dp3_in>; + }; + }; + + port@6 { + reg = <6>; + + mdss_intf6_out: endpoint { + remote-endpoint = <&mdss_dp2_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz = /bits/ 64 <514000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-575000000 { + opp-hz = /bits/ 64 <575000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + }; + }; + + mdss_dp0: displayport-controller@ae90000 { + compatible = "qcom,x1e80100-dp"; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0x600>, + <0 0xae91000 0 0x400>, + <0 0xae91400 0 0x400>; + + interrupts-extended = <&mdss 12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp0_in: endpoint { + remote-endpoint = <&mdss_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { + }; + }; + }; + + mdss_dp0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dp1: displayport-controller@ae98000 { + compatible = "qcom,x1e80100-dp"; + reg = <0 0xae98000 0 0x200>, + <0 0xae98200 0 0x200>, + <0 0xae98400 0 0x600>, + <0 0xae99000 0 0x400>, + <0 0xae99400 0 0x400>; + + interrupts-extended = <&mdss 13>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp1_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp1_in: endpoint { + remote-endpoint = <&mdss_intf4_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp1_out: endpoint { + }; + }; + }; + + mdss_dp1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dp2: displayport-controller@ae9a000 { + compatible = "qcom,x1e80100-dp"; + reg = <0 0xae9a000 0 0x200>, + <0 0xae9a200 0 0x200>, + <0 0xae9a400 0 0x600>, + <0 0xae9b000 0 0x400>, + <0 0xae9b400 0 0x400>; + + interrupts-extended = <&mdss 14>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss_dp2_phy 0>, + <&mdss_dp2_phy 1>; + + operating-points-v2 = <&mdss_dp2_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dp2_phy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dp2_in: endpoint { + remote-endpoint = <&mdss_intf6_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + mdss_dp2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dp3: displayport-controller@aea0000 { + compatible = "qcom,x1e80100-dp"; + reg = <0 0xaea0000 0 0x200>, + <0 0xaea0200 0 0x200>, + <0 0xaea0400 0 0x600>, + <0 0xaea1000 0 0x400>, + <0 0xaea1400 0 0x400>; + + interrupts-extended = <&mdss 15>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss_dp3_phy 0>, + <&mdss_dp3_phy 1>; + + operating-points-v2 = <&mdss_dp3_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dp3_phy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp3_in: endpoint { + remote-endpoint = <&mdss_intf5_out>; + + link-frequencies = /bits/ 64 <8100000000>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + mdss_dp3_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + }; + + mdss_dp2_phy: phy@aec2a00 { + compatible = "qcom,x1e80100-dp-phy"; + reg = <0 0x0aec2a00 0 0x19c>, + <0 0x0aec2200 0 0xec>, + <0 0x0aec2600 0 0xec>, + <0 0x0aec2000 0 0x1c8>; + + clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", + "cfg_ahb"; + + power-domains = <&rpmhpd RPMHPD_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss_dp3_phy: phy@aec5a00 { + compatible = "qcom,x1e80100-dp-phy"; + reg = <0 0x0aec5a00 0 0x19c>, + <0 0x0aec5200 0 0xec>, + <0 0x0aec5600 0 0xec>, + <0 0x0aec5000 0 0x1c8>; + + clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", + "cfg_ahb"; + + power-domains = <&rpmhpd RPMHPD_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,x1e80100-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + clocks = <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <0>, /* dsi0 */ + <0>, + <0>, /* dsi1 */ + <0>, + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ + <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&mdss_dp2_phy 0>, /* dp2 */ + <&mdss_dp2_phy 1>, + <&mdss_dp3_phy 0>, /* dp3 */ + <&mdss_dp3_phy 1>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,x1e80100-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; @@ -2599,6 +4210,18 @@ interrupt-controller; }; + aoss_qmp: power-management@c300000 { + compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp"; + reg = <0 0x0c300000 0 0x400>; + interrupt-parent = <&ipcc>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + }; + + tlmm: pinctrl@f100000 { compatible = "qcom,x1e80100-tlmm"; reg = <0 0x0f100000 0 0xf00000>; @@ -3170,7 +4793,7 @@ /* TX, RX */ pins = "gpio86", "gpio87"; function = "qup2_se5"; - drive-strength= <2>; + drive-strength = <2>; bias-disable; }; }; @@ -3315,7 +4938,6 @@ <0 0x17510000 0 0x10000>, <0 0x17520000 0 0x10000>; reg-names = "drv-0", "drv-1", "drv-2"; - qcom,drv-count = <3>; interrupts = , , @@ -3326,6 +4948,7 @@ , ; label = "apps_rsc"; + power-domains = <&SYSTEM_PD>; apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; @@ -3514,6 +5137,144 @@ "llcc_broadcast_base"; interrupts = ; }; + + remoteproc_adsp: remoteproc@30000000 { + compatible = "qcom,x1e80100-adsp-pas"; + reg = <0 0x30000000 0 0x100>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names = "lcx", + "lmx"; + + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + memory-region = <&adspslpi_mem>, + <&q6_adsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + + gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = ; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = ; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1001 0x80>, + <&apps_smmu 0x1061 0x0>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = ; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; + }; + }; + + remoteproc_cdsp: remoteproc@32300000 { + compatible = "qcom,x1e80100-cdsp-pas"; + reg = <0 0x32300000 0 0x1400000>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_NSP>; + power-domain-names = "cx", + "mxc", + "nsp"; + + interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + memory-region = <&cdsp_mem>, + <&q6_cdsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_cdsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "cdsp"; + qcom,remote-pid = <5>; + }; + }; }; timer { diff --git a/src/arm64/renesas/r8a774a1.dtsi b/src/arm64/renesas/r8a774a1.dtsi index 95b0a1f6deb..a8a44fe5e83 100644 --- a/src/arm64/renesas/r8a774a1.dtsi +++ b/src/arm64/renesas/r8a774a1.dtsi @@ -529,6 +529,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; @@ -541,7 +542,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; @@ -554,7 +557,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; @@ -568,6 +573,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; @@ -581,6 +587,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; diff --git a/src/arm64/renesas/r8a774b1.dtsi b/src/arm64/renesas/r8a774b1.dtsi index 786660fcdea..4fff511e994 100644 --- a/src/arm64/renesas/r8a774b1.dtsi +++ b/src/arm64/renesas/r8a774b1.dtsi @@ -413,6 +413,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; @@ -425,7 +426,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; @@ -438,7 +441,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; @@ -452,6 +457,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; @@ -465,6 +471,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; diff --git a/src/arm64/renesas/r8a774c0.dtsi b/src/arm64/renesas/r8a774c0.dtsi index eed94ffed7c..1ef43d78c3a 100644 --- a/src/arm64/renesas/r8a774c0.dtsi +++ b/src/arm64/renesas/r8a774c0.dtsi @@ -384,6 +384,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; @@ -396,7 +397,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; @@ -409,7 +412,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; @@ -423,6 +428,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; @@ -436,6 +442,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; diff --git a/src/arm64/renesas/r8a774e1.dtsi b/src/arm64/renesas/r8a774e1.dtsi index 175e5d296da..be55ae83944 100644 --- a/src/arm64/renesas/r8a774e1.dtsi +++ b/src/arm64/renesas/r8a774e1.dtsi @@ -593,6 +593,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; @@ -605,7 +606,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; @@ -618,7 +621,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; @@ -632,6 +637,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; @@ -645,6 +651,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; diff --git a/src/arm64/renesas/r8a77951.dtsi b/src/arm64/renesas/r8a77951.dtsi index a4260d9291b..bea4edd17d5 100644 --- a/src/arm64/renesas/r8a77951.dtsi +++ b/src/arm64/renesas/r8a77951.dtsi @@ -614,6 +614,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -626,7 +627,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -639,7 +642,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -653,6 +658,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -666,6 +672,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; diff --git a/src/arm64/renesas/r8a77960.dtsi b/src/arm64/renesas/r8a77960.dtsi index a631ead171b..7846fea8e40 100644 --- a/src/arm64/renesas/r8a77960.dtsi +++ b/src/arm64/renesas/r8a77960.dtsi @@ -578,6 +578,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -590,7 +591,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -603,7 +606,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -617,6 +622,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -630,6 +636,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; diff --git a/src/arm64/renesas/r8a77961.dtsi b/src/arm64/renesas/r8a77961.dtsi index 7254912a241..58f9286a5ab 100644 --- a/src/arm64/renesas/r8a77961.dtsi +++ b/src/arm64/renesas/r8a77961.dtsi @@ -578,6 +578,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; @@ -590,7 +591,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; @@ -603,7 +606,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; @@ -617,6 +622,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; @@ -630,6 +636,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; diff --git a/src/arm64/renesas/r8a77965.dtsi b/src/arm64/renesas/r8a77965.dtsi index e57b9027066..692940662d3 100644 --- a/src/arm64/renesas/r8a77965.dtsi +++ b/src/arm64/renesas/r8a77965.dtsi @@ -449,6 +449,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; @@ -461,7 +462,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; @@ -474,7 +477,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; @@ -488,6 +493,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; @@ -501,6 +507,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; diff --git a/src/arm64/renesas/r8a77970.dtsi b/src/arm64/renesas/r8a77970.dtsi index ed6e2e47c60..d2d3cecc76d 100644 --- a/src/arm64/renesas/r8a77970.dtsi +++ b/src/arm64/renesas/r8a77970.dtsi @@ -328,6 +328,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; @@ -340,7 +341,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; @@ -353,7 +356,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; @@ -367,6 +372,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; @@ -380,6 +386,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; diff --git a/src/arm64/renesas/r8a77980.dtsi b/src/arm64/renesas/r8a77980.dtsi index 5ed2daaca1f..c0ba110c74d 100644 --- a/src/arm64/renesas/r8a77980.dtsi +++ b/src/arm64/renesas/r8a77980.dtsi @@ -357,6 +357,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; @@ -369,7 +370,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; @@ -382,7 +385,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; @@ -395,7 +400,9 @@ reg = <0 0xe6fe0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; @@ -408,7 +415,9 @@ reg = <0 0xffc00000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; diff --git a/src/arm64/renesas/r8a77990.dtsi b/src/arm64/renesas/r8a77990.dtsi index 8c2b2834238..37063e3f4e1 100644 --- a/src/arm64/renesas/r8a77990.dtsi +++ b/src/arm64/renesas/r8a77990.dtsi @@ -415,6 +415,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; @@ -427,7 +428,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; @@ -440,7 +443,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; @@ -454,6 +459,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; @@ -467,6 +473,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; diff --git a/src/arm64/renesas/r8a77995.dtsi b/src/arm64/renesas/r8a77995.dtsi index 8cf6473c63d..89990dd8ebf 100644 --- a/src/arm64/renesas/r8a77995.dtsi +++ b/src/arm64/renesas/r8a77995.dtsi @@ -336,6 +336,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; @@ -348,7 +349,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; @@ -361,7 +364,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; @@ -375,6 +380,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; @@ -388,6 +394,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; diff --git a/src/arm64/renesas/r8a779a0.dtsi b/src/arm64/renesas/r8a779a0.dtsi index 4e67a035649..cfa70b441e3 100644 --- a/src/arm64/renesas/r8a779a0.dtsi +++ b/src/arm64/renesas/r8a779a0.dtsi @@ -370,6 +370,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 713>; clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -382,7 +383,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 714>; clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -395,7 +398,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 715>; clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -408,7 +413,9 @@ reg = <0 0xe6fe0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 716>; clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -421,7 +428,9 @@ reg = <0 0xffc00000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 717>; clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -658,7 +667,7 @@ avb0: ethernet@e6800000 { compatible = "renesas,etheravb-r8a779a0", "renesas,etheravb-rcar-gen4"; - reg = <0 0xe6800000 0 0x800>; + reg = <0 0xe6800000 0 0x1000>; interrupts = , , , @@ -706,7 +715,7 @@ avb1: ethernet@e6810000 { compatible = "renesas,etheravb-r8a779a0", "renesas,etheravb-rcar-gen4"; - reg = <0 0xe6810000 0 0x800>; + reg = <0 0xe6810000 0 0x1000>; interrupts = , , , diff --git a/src/arm64/renesas/r8a779f0.dtsi b/src/arm64/renesas/r8a779f0.dtsi index 7fb4989cce8..72cf30341fc 100644 --- a/src/arm64/renesas/r8a779f0.dtsi +++ b/src/arm64/renesas/r8a779f0.dtsi @@ -501,6 +501,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 713>; clock-names = "fck"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; @@ -513,7 +514,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 714>; clock-names = "fck"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; @@ -526,7 +529,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 715>; clock-names = "fck"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; @@ -539,7 +544,9 @@ reg = <0 0xe6fe0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 716>; clock-names = "fck"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; @@ -552,7 +559,9 @@ reg = <0 0xffc00000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 717>; clock-names = "fck"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; diff --git a/src/arm64/renesas/r8a779g0-white-hawk-cpu.dts b/src/arm64/renesas/r8a779g0-white-hawk-cpu.dts new file mode 100644 index 00000000000..c8b1bb50a8c --- /dev/null +++ b/src/arm64/renesas/r8a779g0-white-hawk-cpu.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the standalone R-Car V4H White Hawk CPU board + * + * Copyright (C) 2023 Glider bv + */ + +/dts-v1/; +#include "r8a779g0-white-hawk-cpu.dtsi" + +/ { + model = "Renesas White Hawk CPU board based on r8a779g0"; +}; diff --git a/src/arm64/renesas/r8a779g0-white-hawk-cpu.dtsi b/src/arm64/renesas/r8a779g0-white-hawk-cpu.dtsi index 913f70fe6c5..b1fe1aedc27 100644 --- a/src/arm64/renesas/r8a779g0-white-hawk-cpu.dtsi +++ b/src/arm64/renesas/r8a779g0-white-hawk-cpu.dtsi @@ -1,378 +1,14 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Source for the White Hawk CPU board + * Device Tree Source for the R-Car V4H White Hawk CPU board * * Copyright (C) 2022 Renesas Electronics Corp. */ #include "r8a779g0.dtsi" - -#include -#include -#include +#include "white-hawk-cpu-common.dtsi" / { model = "Renesas White Hawk CPU board"; compatible = "renesas,white-hawk-cpu", "renesas,r8a779g0"; - - aliases { - ethernet0 = &avb0; - serial0 = &hscif0; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:921600n8"; - }; - - keys { - compatible = "gpio-keys"; - - pinctrl-0 = <&keys_pins>; - pinctrl-names = "default"; - - key-1 { - gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW47"; - wakeup-source; - debounce-interval = <20>; - }; - - key-2 { - gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW48"; - wakeup-source; - debounce-interval = <20>; - }; - - key-3 { - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW49"; - wakeup-source; - debounce-interval = <20>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-1 { - gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <1>; - }; - - led-2 { - gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <2>; - }; - - led-3 { - gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <3>; - }; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@480000000 { - device_type = "memory"; - reg = <0x4 0x80000000 0x0 0x80000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x1 0x00000000>; - }; - - mini-dp-con { - compatible = "dp-connector"; - label = "CN5"; - type = "mini"; - - port { - mini_dp_con_in: endpoint { - remote-endpoint = <&sn65dsi86_out>; - }; - }; - }; - - reg_1p2v: regulator-1p2v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sn65dsi86_refclk: clk-x6 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - }; -}; - -&avb0 { - pinctrl-0 = <&avb0_pins>; - pinctrl-names = "default"; - phy-handle = <&phy0>; - tx-internal-delay-ps = <2000>; - status = "okay"; - - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id0022.1622", - "ethernet-phy-ieee802.3-c22"; - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio7>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; - }; -}; - -&dsi0 { - status = "okay"; - - ports { - port@1 { - dsi0_out: endpoint { - remote-endpoint = <&sn65dsi86_in>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&du { - status = "okay"; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&hscif0 { - pinctrl-0 = <&hscif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - io_expander_a: gpio@20 { - compatible = "onnn,pca9654"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - eeprom@50 { - compatible = "rohm,br24g01", "atmel,24c01"; - label = "cpu-board"; - reg = <0x50>; - pagesize = <8>; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - bridge@2c { - compatible = "ti,sn65dsi86"; - reg = <0x2c>; - - clocks = <&sn65dsi86_refclk>; - clock-names = "refclk"; - - interrupt-parent = <&intc_ex>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - - enable-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - - vccio-supply = <®_1p8v>; - vpll-supply = <®_1p8v>; - vcca-supply = <®_1p2v>; - vcc-supply = <®_1p2v>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - sn65dsi86_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - - port@1 { - reg = <1>; - sn65dsi86_out: endpoint { - remote-endpoint = <&mini_dp_con_in>; - }; - }; - }; - }; -}; - -&mmc0 { - pinctrl-0 = <&mmc_pins>; - pinctrl-1 = <&mmc_pins>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - bus-width = <8>; - no-sd; - no-sdio; - non-removable; - full-pwr-cycle-in-suspend; - status = "okay"; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - avb0_pins: avb0 { - mux { - groups = "avb0_link", "avb0_mdio", "avb0_rgmii", - "avb0_txcrefclk"; - function = "avb0"; - }; - - pins_mdio { - groups = "avb0_mdio"; - drive-strength = <21>; - }; - - pins_mii { - groups = "avb0_rgmii"; - drive-strength = <21>; - }; - - }; - hscif0_pins: hscif0 { - groups = "hscif0_data"; - function = "hscif0"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - keys_pins: keys { - pins = "GP_5_0", "GP_5_1", "GP_5_2"; - bias-pull-up; - }; - - mmc_pins: mmc { - groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; - function = "mmc"; - power-source = <1800>; - }; - - qspi0_pins: qspi0 { - groups = "qspi0_ctrl", "qspi0_data4"; - function = "qspi0"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; -}; - -&rpc { - pinctrl-0 = <&qspi0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fs512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - spi-rx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot@0 { - reg = <0x0 0x1200000>; - read-only; - }; - user@1200000 { - reg = <0x1200000 0x2e00000>; - }; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif_clk { - clock-frequency = <24000000>; }; diff --git a/src/arm64/renesas/r8a779g0-white-hawk.dts b/src/arm64/renesas/r8a779g0-white-hawk.dts index eff1ef6e2cc..784d4e8b204 100644 --- a/src/arm64/renesas/r8a779g0-white-hawk.dts +++ b/src/arm64/renesas/r8a779g0-white-hawk.dts @@ -1,69 +1,15 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Source for the White Hawk CPU and BreakOut boards + * Device Tree Source for the R-Car V4H White Hawk CPU and BreakOut boards * * Copyright (C) 2022 Renesas Electronics Corp. */ /dts-v1/; #include "r8a779g0-white-hawk-cpu.dtsi" -#include "r8a779g0-white-hawk-csi-dsi.dtsi" -#include "r8a779g0-white-hawk-ethernet.dtsi" +#include "white-hawk-common.dtsi" / { model = "Renesas White Hawk CPU and Breakout boards based on r8a779g0"; compatible = "renesas,white-hawk-breakout", "renesas,white-hawk-cpu", "renesas,r8a779g0"; - - can_transceiver0: can-phy0 { - compatible = "nxp,tjr1443"; - #phy-cells = <0>; - enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - max-bitrate = <5000000>; - }; -}; - -&can_clk { - clock-frequency = <40000000>; -}; - -&canfd { - pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>; - pinctrl-names = "default"; - - status = "okay"; - - channel0 { - status = "okay"; - phys = <&can_transceiver0>; - }; - - channel1 { - status = "okay"; - }; -}; - -&i2c0 { - eeprom@51 { - compatible = "rohm,br24g01", "atmel,24c01"; - label = "breakout-board"; - reg = <0x51>; - pagesize = <8>; - }; -}; - -&pfc { - can_clk_pins: can-clk { - groups = "can_clk"; - function = "can_clk"; - }; - - canfd0_pins: canfd0 { - groups = "canfd0_data"; - function = "canfd0"; - }; - - canfd1_pins: canfd1 { - groups = "canfd1_data"; - function = "canfd1"; - }; }; diff --git a/src/arm64/renesas/r8a779g0.dtsi b/src/arm64/renesas/r8a779g0.dtsi index d3d25e077c5..9bc542bc616 100644 --- a/src/arm64/renesas/r8a779g0.dtsi +++ b/src/arm64/renesas/r8a779g0.dtsi @@ -161,11 +161,6 @@ }; }; - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>; @@ -185,13 +180,24 @@ interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; - /* External SCIF clock - to be overridden by boards that provide it */ + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + /* External SCIF clocks - to be overridden by boards that provide them */ scif_clk: scif { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; + scif_clk2: scif2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; @@ -479,6 +485,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 713>; clock-names = "fck"; power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; @@ -491,7 +498,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 714>; clock-names = "fck"; power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; @@ -504,7 +513,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 715>; clock-names = "fck"; power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; @@ -517,7 +528,9 @@ reg = <0 0xe6fe0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 716>; clock-names = "fck"; power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; @@ -530,7 +543,9 @@ reg = <0 0xffc00000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 717>; clock-names = "fck"; power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; @@ -681,7 +696,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 516>, <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, - <&scif_clk>; + <&scif_clk2>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x35>, <&dmac0 0x34>, <&dmac1 0x35>, <&dmac1 0x34>; @@ -761,7 +776,7 @@ avb0: ethernet@e6800000 { compatible = "renesas,etheravb-r8a779g0", "renesas,etheravb-rcar-gen4"; - reg = <0 0xe6800000 0 0x800>; + reg = <0 0xe6800000 0 0x1000>; interrupts = , , , @@ -808,7 +823,7 @@ avb1: ethernet@e6810000 { compatible = "renesas,etheravb-r8a779g0", "renesas,etheravb-rcar-gen4"; - reg = <0 0xe6810000 0 0x800>; + reg = <0 0xe6810000 0 0x1000>; interrupts = , , , @@ -1057,7 +1072,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 705>, <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, - <&scif_clk>; + <&scif_clk2>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x59>, <&dmac0 0x58>, <&dmac1 0x59>, <&dmac1 0x58>; @@ -1777,6 +1792,37 @@ }; }; + mmc0: mmc@ee140000 { + compatible = "renesas,sdhi-r8a779g0", + "renesas,rcar-gen4-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 706>, + <&cpg CPG_CORE R8A779G0_CLK_SD0H>; + clock-names = "core", "clkh"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 706>; + max-frequency = <200000000>; + iommus = <&ipmmu_ds0 32>; + status = "disabled"; + }; + + rpc: spi@ee200000 { + compatible = "renesas,r8a779g0-rpc-if", + "renesas,rcar-gen4-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = ; + clocks = <&cpg CPG_MOD 629>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 629>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + ipmmu_rt0: iommu@ee480000 { compatible = "renesas,ipmmu-r8a779g0", "renesas,rcar-gen4-ipmmu-vmsa"; @@ -1886,37 +1932,6 @@ #iommu-cells = <1>; }; - mmc0: mmc@ee140000 { - compatible = "renesas,sdhi-r8a779g0", - "renesas,rcar-gen4-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 706>, - <&cpg CPG_CORE R8A779G0_CLK_SD0H>; - clock-names = "core", "clkh"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 706>; - max-frequency = <200000000>; - iommus = <&ipmmu_ds0 32>; - status = "disabled"; - }; - - rpc: spi@ee200000 { - compatible = "renesas,r8a779g0-rpc-if", - "renesas,rcar-gen4-rpc-if"; - reg = <0 0xee200000 0 0x200>, - <0 0x08000000 0 0x04000000>, - <0 0xee208000 0 0x100>; - reg-names = "regs", "dirmap", "wbuf"; - interrupts = ; - clocks = <&cpg CPG_MOD 629>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 629>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - gic: interrupt-controller@f1000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; diff --git a/src/arm64/renesas/r8a779g2-white-hawk-single.dts b/src/arm64/renesas/r8a779g2-white-hawk-single.dts new file mode 100644 index 00000000000..2f79e5a6124 --- /dev/null +++ b/src/arm64/renesas/r8a779g2-white-hawk-single.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4H ES2.0 White Hawk Single board + * + * Copyright (C) 2023 Glider bv + */ + +/dts-v1/; +#include "r8a779g2.dtsi" +#include "white-hawk-cpu-common.dtsi" +#include "white-hawk-common.dtsi" + +/ { + model = "Renesas White Hawk Single board based on r8a779g2"; + compatible = "renesas,white-hawk-single", "renesas,r8a779g2", + "renesas,r8a779g0"; +}; + +&hscif0 { + uart-has-rtscts; +}; + +&hscif0_pins { + groups = "hscif0_data", "hscif0_ctrl"; + function = "hscif0"; +}; diff --git a/src/arm64/renesas/r8a779g2.dtsi b/src/arm64/renesas/r8a779g2.dtsi new file mode 100644 index 00000000000..e08f531843e --- /dev/null +++ b/src/arm64/renesas/r8a779g2.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4H (R8A779G2) SoC + * + * Copyright (C) 2023 Glider bv + */ + +#include "r8a779g0.dtsi" + +/ { + compatible = "renesas,r8a779g2", "renesas,r8a779g0"; +}; diff --git a/src/arm64/renesas/r8a779h0-gray-hawk-single.dts b/src/arm64/renesas/r8a779h0-gray-hawk-single.dts new file mode 100644 index 00000000000..bc8616a56c0 --- /dev/null +++ b/src/arm64/renesas/r8a779h0-gray-hawk-single.dts @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4M Gray Hawk Single board + * + * Copyright (C) 2023 Renesas Electronics Corp. + * Copyright (C) 2024 Glider bv + */ + +/dts-v1/; + +#include + +#include "r8a779h0.dtsi" + +/ { + model = "Renesas Gray Hawk Single board based on r8a779h0"; + compatible = "renesas,gray-hawk-single", "renesas,r8a779h0"; + + aliases { + serial0 = &hscif0; + ethernet0 = &avb0; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:921600n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@480000000 { + device_type = "memory"; + reg = <0x4 0x80000000 0x1 0x80000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&avb0 { + pinctrl-0 = <&avb0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + tx-internal-delay-ps = <2000>; + status = "okay"; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio7>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&hscif0 { + pinctrl-0 = <&hscif0_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + eeprom@50 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "cpu-board"; + reg = <0x50>; + pagesize = <8>; + }; + + eeprom@51 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "breakout-board"; + reg = <0x51>; + pagesize = <8>; + }; + + eeprom@52 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "csi-dsi-sub-board-id"; + reg = <0x52>; + pagesize = <8>; + }; + + eeprom@53 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "ethernet-sub-board-id"; + reg = <0x53>; + pagesize = <8>; + }; +}; + +&mmc0 { + pinctrl-0 = <&mmc_pins>; + pinctrl-1 = <&mmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + avb0_pins: avb0 { + mux { + groups = "avb0_link", "avb0_mdio", "avb0_rgmii", + "avb0_txcrefclk"; + function = "avb0"; + }; + + pins_mdio { + groups = "avb0_mdio"; + drive-strength = <21>; + }; + + pins_mii { + groups = "avb0_rgmii"; + drive-strength = <21>; + }; + }; + + hscif0_pins: hscif0 { + groups = "hscif0_data", "hscif0_ctrl"; + function = "hscif0"; + }; + + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + mmc_pins: mmc { + groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; + function = "mmc"; + power-source = <1800>; + }; + + qspi0_pins: qspi0 { + groups = "qspi0_ctrl", "qspi0_data4"; + function = "qspi0"; + }; + + scif_clk_pins: scif-clk { + groups = "scif_clk"; + function = "scif_clk"; + }; +}; + +&rpc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + flash@0 { + compatible = "spansion,s25fs512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + reg = <0x0 0x1200000>; + read-only; + }; + user@1200000 { + reg = <0x1200000 0x2e00000>; + }; + }; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&scif_clk { + clock-frequency = <24000000>; +}; diff --git a/src/arm64/renesas/r8a779h0.dtsi b/src/arm64/renesas/r8a779h0.dtsi new file mode 100644 index 00000000000..11885729181 --- /dev/null +++ b/src/arm64/renesas/r8a779h0.dtsi @@ -0,0 +1,664 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4M (R8A779H0) SoC + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include +#include +#include + +/ { + compatible = "renesas,r8a779h0"; + #address-cells = <2>; + #size-cells = <2>; + + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <825000>; + clock-latency-ns = <500000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <825000>; + clock-latency-ns = <500000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&a76_0>; + }; + core1 { + cpu = <&a76_1>; + }; + core2 { + cpu = <&a76_2>; + }; + core3 { + cpu = <&a76_3>; + }; + }; + }; + + a76_0: cpu@0 { + compatible = "arm,cortex-a76"; + reg = <0>; + device_type = "cpu"; + power-domains = <&sysc R8A779H0_PD_A1E0D0C0>; + next-level-cache = <&L3_CA76>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC0>; + operating-points-v2 = <&cluster0_opp>; + }; + + a76_1: cpu@100 { + compatible = "arm,cortex-a76"; + reg = <0x100>; + device_type = "cpu"; + power-domains = <&sysc R8A779H0_PD_A1E0D0C1>; + next-level-cache = <&L3_CA76>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC1>; + operating-points-v2 = <&cluster0_opp>; + }; + + a76_2: cpu@200 { + compatible = "arm,cortex-a76"; + reg = <0x200>; + device_type = "cpu"; + power-domains = <&sysc R8A779H0_PD_A1E0D0C2>; + next-level-cache = <&L3_CA76>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC2>; + operating-points-v2 = <&cluster0_opp>; + }; + + a76_3: cpu@300 { + compatible = "arm,cortex-a76"; + reg = <0x300>; + device_type = "cpu"; + power-domains = <&sysc R8A779H0_PD_A1E0D0C3>; + next-level-cache = <&L3_CA76>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC3>; + operating-points-v2 = <&cluster0_opp>; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <4000>; + }; + }; + + L3_CA76: cache-controller { + compatible = "cache"; + power-domains = <&sysc R8A779H0_PD_A2E0D0>; + cache-unified; + cache-level = <3>; + }; + }; + + extal_clk: extal-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + pmu-a76 { + compatible = "arm,cortex-a76-pmu"; + interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a779h0-wdt", + "renesas,rcar-gen4-wdt"; + reg = <0 0xe6020000 0 0x0c>; + interrupts = ; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 907>; + status = "disabled"; + }; + + pfc: pinctrl@e6050000 { + compatible = "renesas,pfc-r8a779h0"; + reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, + <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, + <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, + <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>; + }; + + gpio0: gpio@e6050180 { + compatible = "renesas,gpio-r8a779h0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6050180 0 0x54>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 19>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + }; + + gpio1: gpio@e6050980 { + compatible = "renesas,gpio-r8a779h0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6050980 0 0x54>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 30>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + }; + + gpio2: gpio@e6058180 { + compatible = "renesas,gpio-r8a779h0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6058180 0 0x54>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 20>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 916>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 916>; + }; + + gpio3: gpio@e6058980 { + compatible = "renesas,gpio-r8a779h0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6058980 0 0x54>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 916>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 916>; + }; + + gpio4: gpio@e6060180 { + compatible = "renesas,gpio-r8a779h0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6060180 0 0x54>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 25>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 917>; + }; + + gpio5: gpio@e6060980 { + compatible = "renesas,gpio-r8a779h0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6060980 0 0x54>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 21>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 917>; + }; + + gpio6: gpio@e6061180 { + compatible = "renesas,gpio-r8a779h0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6061180 0 0x54>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 21>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 917>; + }; + + gpio7: gpio@e6061980 { + compatible = "renesas,gpio-r8a779h0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6061980 0 0x54>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 21>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 917>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a779h0-cpg-mssr"; + reg = <0 0xe6150000 0 0x4000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a779h0-rst"; + reg = <0 0xe6160000 0 0x4000>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a779h0-sysc"; + reg = <0 0xe6180000 0 0x4000>; + #power-domain-cells = <1>; + }; + + i2c0: i2c@e6500000 { + compatible = "renesas,i2c-r8a779h0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 518>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 518>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + compatible = "renesas,i2c-r8a779h0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 519>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 519>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + compatible = "renesas,i2c-r8a779h0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 520>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 520>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + compatible = "renesas,i2c-r8a779h0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 521>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 521>; + dmas = <&dmac1 0x97>, <&dmac1 0x96>, + <&dmac2 0x97>, <&dmac2 0x96>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a779h0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 514>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 514>; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + status = "disabled"; + }; + + avb0: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a779h0", + "renesas,etheravb-rcar-gen4"; + reg = <0 0xe6800000 0 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 211>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 211>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + avb1: ethernet@e6810000 { + compatible = "renesas,etheravb-r8a779h0", + "renesas,etheravb-rcar-gen4"; + reg = <0 0xe6810000 0 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 212>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 212>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + avb2: ethernet@e6820000 { + compatible = "renesas,etheravb-r8a779h0", + "renesas,etheravb-rcar-gen4"; + reg = <0 0xe6820000 0 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 213>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 213>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + dmac1: dma-controller@e7350000 { + compatible = "renesas,dmac-r8a779h0", + "renesas,rcar-gen4-dmac"; + reg = <0 0xe7350000 0 0x1000>, + <0 0xe7300000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7", "ch8", "ch9", + "ch10", "ch11", "ch12", "ch13", + "ch14", "ch15"; + clocks = <&cpg CPG_MOD 709>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 709>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + dmac2: dma-controller@e7351000 { + compatible = "renesas,dmac-r8a779h0", + "renesas,rcar-gen4-dmac"; + reg = <0 0xe7351000 0 0x1000>, + <0 0xe7310000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7"; + clocks = <&cpg CPG_MOD 710>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 710>; + #dma-cells = <1>; + dma-channels = <8>; + }; + + mmc0: mmc@ee140000 { + compatible = "renesas,sdhi-r8a779h0", + "renesas,rcar-gen4-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 706>, + <&cpg CPG_CORE R8A779H0_CLK_SD0H>; + clock-names = "core", "clkh"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 706>; + max-frequency = <200000000>; + status = "disabled"; + }; + + rpc: spi@ee200000 { + compatible = "renesas,r8a779h0-rpc-if", + "renesas,rcar-gen4-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = ; + clocks = <&cpg CPG_MOD 629>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 629>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + gic: interrupt-controller@f1000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1000000 0 0x20000>, + <0x0 0xf1060000 0 0x110000>; + interrupts = ; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + }; +}; diff --git a/src/arm64/renesas/r9a07g043u.dtsi b/src/arm64/renesas/r9a07g043u.dtsi index 2ab231572d9..964b0a475ee 100644 --- a/src/arm64/renesas/r9a07g043u.dtsi +++ b/src/arm64/renesas/r9a07g043u.dtsi @@ -61,6 +61,75 @@ &soc { interrupt-parent = <&gic>; + cru: video@10830000 { + compatible = "renesas,r9a07g043-cru", "renesas,rzg2l-cru"; + reg = <0 0x10830000 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G043_CRU_VCLK>, + <&cpg CPG_MOD R9A07G043_CRU_PCLK>, + <&cpg CPG_MOD R9A07G043_CRU_ACLK>; + clock-names = "video", "apb", "axi"; + interrupts = , + , + ; + interrupt-names = "image_conv", "image_conv_err", "axi_mst_err"; + resets = <&cpg R9A07G043_CRU_PRESETN>, + <&cpg R9A07G043_CRU_ARESETN>; + reset-names = "presetn", "aresetn"; + power-domains = <&cpg>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + crucsi2: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi2cru>; + }; + }; + }; + }; + + csi2: csi2@10830400 { + compatible = "renesas,r9a07g043-csi2", "renesas,rzg2l-csi2"; + reg = <0 0x10830400 0 0xfc00>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G043_CRU_SYSCLK>, + <&cpg CPG_MOD R9A07G043_CRU_VCLK>, + <&cpg CPG_MOD R9A07G043_CRU_PCLK>; + clock-names = "system", "video", "apb"; + resets = <&cpg R9A07G043_CRU_PRESETN>, + <&cpg R9A07G043_CRU_CMN_RSTB>; + reset-names = "presetn", "cmn-rstb"; + power-domains = <&cpg>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + csi2cru: endpoint@0 { + reg = <0>; + remote-endpoint = <&crucsi2>; + }; + }; + }; + }; + irqc: interrupt-controller@110a0000 { compatible = "renesas,r9a07g043u-irqc", "renesas,rzg2l-irqc"; @@ -109,7 +178,13 @@ , , , - ; + , + , + , + , + , + , + ; interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3", "irq4", "irq5", "irq6", "irq7", @@ -121,7 +196,9 @@ "tint20", "tint21", "tint22", "tint23", "tint24", "tint25", "tint26", "tint27", "tint28", "tint29", "tint30", "tint31", - "bus-err"; + "bus-err", "ec7tie1-0", "ec7tie2-0", + "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1", + "ec7tiovf-1"; clocks = <&cpg CPG_MOD R9A07G043_IA55_CLK>, <&cpg CPG_MOD R9A07G043_IA55_PCLK>; clock-names = "clk", "pclk"; diff --git a/src/arm64/renesas/r9a07g043u11-smarc-cru-csi-ov5645.dtso b/src/arm64/renesas/r9a07g043u11-smarc-cru-csi-ov5645.dtso new file mode 100644 index 00000000000..b41bb4b31a2 --- /dev/null +++ b/src/arm64/renesas/r9a07g043u11-smarc-cru-csi-ov5645.dtso @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree overlay for the RZ/G2UL SMARC EVK with OV5645 camera + * connected to CSI and CRU enabled. + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#define OV5645_PARENT_I2C i2c0 +#include "rz-smarc-cru-csi-ov5645.dtsi" + +&ov5645 { + enable-gpios = <&pinctrl RZG2L_GPIO(4, 4) GPIO_ACTIVE_HIGH>; + reset-gpios = <&pinctrl RZG2L_GPIO(0, 1) GPIO_ACTIVE_LOW>; +}; diff --git a/src/arm64/renesas/r9a07g044.dtsi b/src/arm64/renesas/r9a07g044.dtsi index 66f68fc2b24..9f00b75d2bd 100644 --- a/src/arm64/renesas/r9a07g044.dtsi +++ b/src/arm64/renesas/r9a07g044.dtsi @@ -793,6 +793,22 @@ reset-names = "rst", "arst", "prst"; power-domains = <&cpg>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&du_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + }; + }; }; vspd: vsp@10870000 { @@ -820,6 +836,36 @@ resets = <&cpg R9A07G044_LCDC_RESET_N>; }; + du: display@10890000 { + compatible = "renesas,r9a07g044-du"; + reg = <0 0x10890000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_LCDC_RESET_N>; + renesas,vsps = <&vspd 0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_dsi: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a07g044-cpg"; reg = <0 0x11010000 0 0x10000>; @@ -905,7 +951,27 @@ , , , - ; + , + , + , + , + , + , + , + ; + interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "bus-err", "ec7tie1-0", "ec7tie2-0", + "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1", + "ec7tiovf-1"; clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>, <&cpg CPG_MOD R9A07G044_IA55_PCLK>; clock-names = "clk", "pclk"; diff --git a/src/arm64/renesas/r9a07g054.dtsi b/src/arm64/renesas/r9a07g054.dtsi index 1f1d481dc78..53d8905f367 100644 --- a/src/arm64/renesas/r9a07g054.dtsi +++ b/src/arm64/renesas/r9a07g054.dtsi @@ -798,6 +798,22 @@ reset-names = "rst", "arst", "prst"; power-domains = <&cpg>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&du_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + }; + }; }; vspd: vsp@10870000 { @@ -826,6 +842,37 @@ resets = <&cpg R9A07G054_LCDC_RESET_N>; }; + du: display@10890000 { + compatible = "renesas,r9a07g054-du", + "renesas,r9a07g044-du"; + reg = <0 0x10890000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_LCDC_RESET_N>; + renesas,vsps = <&vspd 0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_dsi: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a07g054-cpg"; reg = <0 0x11010000 0 0x10000>; @@ -912,7 +959,27 @@ , , , - ; + , + , + , + , + , + , + , + ; + interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "bus-err", "ec7tie1-0", "ec7tie2-0", + "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1", + "ec7tiovf-1"; clocks = <&cpg CPG_MOD R9A07G054_IA55_CLK>, <&cpg CPG_MOD R9A07G054_IA55_PCLK>; clock-names = "clk", "pclk"; diff --git a/src/arm64/renesas/r9a08g045.dtsi b/src/arm64/renesas/r9a08g045.dtsi index 5facfad9615..f5f3f4f4c8d 100644 --- a/src/arm64/renesas/r9a08g045.dtsi +++ b/src/arm64/renesas/r9a08g045.dtsi @@ -42,6 +42,11 @@ clock-frequency = <0>; }; + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; @@ -152,7 +157,10 @@ , , , - ; + , + , + , + ; interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3", "irq4", "irq5", "irq6", "irq7", @@ -164,7 +172,8 @@ "tint20", "tint21", "tint22", "tint23", "tint24", "tint25", "tint26", "tint27", "tint28", "tint29", "tint30", "tint31", - "bus-err"; + "bus-err", "ec7tie1-0", "ec7tie2-0", + "ec7tiovf-0"; clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>, <&cpg CPG_MOD R9A08G045_IA55_PCLK>; clock-names = "clk", "pclk"; @@ -264,6 +273,20 @@ <0x0 0x12440000 0 0x60000>; interrupts = ; }; + + wdt0: watchdog@12800800 { + compatible = "renesas,r9a08g045-wdt", "renesas,rzg2l-wdt"; + reg = <0 0x12800800 0 0x400>; + clocks = <&cpg CPG_MOD R9A08G045_WDT0_PCLK>, + <&cpg CPG_MOD R9A08G045_WDT0_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = , + ; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A08G045_WDT0_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; + }; }; timer { diff --git a/src/arm64/renesas/rzg2l-smarc.dtsi b/src/arm64/renesas/rzg2l-smarc.dtsi index 37807f1bda4..887dffe1491 100644 --- a/src/arm64/renesas/rzg2l-smarc.dtsi +++ b/src/arm64/renesas/rzg2l-smarc.dtsi @@ -40,17 +40,7 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi0_in: endpoint { - }; - }; - port@1 { - reg = <1>; dsi0_out: endpoint { data-lanes = <1 2 3 4>; remote-endpoint = <&adv7535_in>; @@ -59,6 +49,10 @@ }; }; +&du { + status = "okay"; +}; + &i2c1 { adv7535: hdmi@3d { compatible = "adi,adv7535"; diff --git a/src/arm64/renesas/rzg2lc-smarc.dtsi b/src/arm64/renesas/rzg2lc-smarc.dtsi index 859bc8745e6..f21508640b6 100644 --- a/src/arm64/renesas/rzg2lc-smarc.dtsi +++ b/src/arm64/renesas/rzg2lc-smarc.dtsi @@ -56,17 +56,7 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi0_in: endpoint { - }; - }; - port@1 { - reg = <1>; dsi0_out: endpoint { data-lanes = <1 2 3 4>; remote-endpoint = <&adv7535_in>; @@ -75,6 +65,10 @@ }; }; +&du { + status = "okay"; +}; + &i2c1 { adv7535: hdmi@3d { compatible = "adi,adv7535"; diff --git a/src/arm64/renesas/rzg3s-smarc-som.dtsi b/src/arm64/renesas/rzg3s-smarc-som.dtsi index f062d4ad78b..acac4666ae5 100644 --- a/src/arm64/renesas/rzg3s-smarc-som.dtsi +++ b/src/arm64/renesas/rzg3s-smarc-som.dtsi @@ -193,12 +193,14 @@ #endif &pinctrl { +#if SW_CONFIG3 == SW_ON eth0-phy-irq-hog { gpio-hog; gpios = ; input; line-name = "eth0-phy-irq"; }; +#endif eth0_pins: eth0 { txc { @@ -234,12 +236,14 @@ }; }; +#if SW_CONFIG3 == SW_ON eth1-phy-irq-hog { gpio-hog; gpios = ; input; line-name = "eth1-phy-irq"; }; +#endif eth1_pins: eth1 { txc { @@ -336,3 +340,8 @@ }; }; }; + +&wdt0 { + timeout-sec = <60>; + status = "okay"; +}; diff --git a/src/arm64/renesas/rzg3s-smarc.dtsi b/src/arm64/renesas/rzg3s-smarc.dtsi index 21452013723..deb2ad37bb2 100644 --- a/src/arm64/renesas/rzg3s-smarc.dtsi +++ b/src/arm64/renesas/rzg3s-smarc.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include / { @@ -14,6 +15,37 @@ mmc1 = &sdhi1; }; + keys { + compatible = "gpio-keys"; + + key-1 { + interrupts = ; + interrupt-parent = <&pinctrl>; + linux,code = ; + label = "USER_SW1"; + wakeup-source; + debounce-interval = <20>; + }; + + key-2 { + interrupts = ; + interrupt-parent = <&pinctrl>; + linux,code = ; + label = "USER_SW2"; + wakeup-source; + debounce-interval = <20>; + }; + + key-3 { + interrupts = ; + interrupt-parent = <&pinctrl>; + linux,code = ; + label = "USER_SW3"; + wakeup-source; + debounce-interval = <20>; + }; + }; + vcc_sdhi1: regulator-vcc-sdhi1 { compatible = "regulator-fixed"; regulator-name = "SDHI1 Vcc"; @@ -35,6 +67,27 @@ }; &pinctrl { + key-1-gpio-hog { + gpio-hog; + gpios = ; + input; + line-name = "key-1-gpio-irq"; + }; + + key-2-gpio-hog { + gpio-hog; + gpios = ; + input; + line-name = "key-2-gpio-irq"; + }; + + key-3-gpio-hog { + gpio-hog; + gpios = ; + input; + line-name = "key-3-gpio-irq"; + }; + scif0_pins: scif0 { pinmux = , /* RXD */ ; /* TXD */ diff --git a/src/arm64/renesas/ulcb-kf.dtsi b/src/arm64/renesas/ulcb-kf.dtsi index 50de17e4fb3..431b37bf566 100644 --- a/src/arm64/renesas/ulcb-kf.dtsi +++ b/src/arm64/renesas/ulcb-kf.dtsi @@ -32,39 +32,40 @@ }; }; - accel_3v3: regulator-acc-3v3 { + reg_t1p8v: regulator-t1p8v { compatible = "regulator-fixed"; - regulator-name = "accel-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - hdmi_1v8: regulator-hdmi-1v8 { - compatible = "regulator-fixed"; - regulator-name = "hdmi-1v8"; + regulator-name = "T1.8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; }; - hdmi_3v3: regulator-hdmi-3v3 { + pcie_1v5: regulator-pcie-1v5 { compatible = "regulator-fixed"; - regulator-name = "hdmi-3v3"; + regulator-name = "pcie-1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&gpio_exp_77 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + pcie_3v3: regulator-pcie-3v3 { + compatible = "regulator-fixed"; + regulator-name = "pcie-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + gpio = <&gpio_exp_77 14 GPIO_ACTIVE_HIGH>; + enable-active-high; }; - snd_3p3v: regulator-snd_3p3v { + reg_5v: regulator-5v { compatible = "regulator-fixed"; - regulator-name = "snd-3.3v"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - snd_vcc5v: regulator-snd_vcc5v { - compatible = "regulator-fixed"; - regulator-name = "snd-vcc5v"; + regulator-name = "fixed-5V"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; }; wlan_en: regulator-wlan_en { @@ -157,11 +158,11 @@ pd-gpios = <&gpio_exp_75 5 GPIO_ACTIVE_LOW>; - avdd-supply = <&hdmi_1v8>; - dvdd-supply = <&hdmi_1v8>; - pvdd-supply = <&hdmi_1v8>; - dvdd-3v-supply = <&hdmi_3v3>; - bgvdd-supply = <&hdmi_1v8>; + avdd-supply = <®_t1p8v>; + dvdd-supply = <®_t1p8v>; + pvdd-supply = <®_t1p8v>; + dvdd-3v-supply = <®_3p3v>; + bgvdd-supply = <®_t1p8v>; adi,input-depth = <8>; adi,input-colorspace = "rgb"; @@ -198,8 +199,8 @@ compatible = "st,lsm9ds0-imu"; reg = <0x1d>; - vdd-supply = <&accel_3v3>; - vddio-supply = <&accel_3v3>; + vdd-supply = <®_3p3v>; + vddio-supply = <®_3p3v>; }; pcm3168a: audio-codec@44 { @@ -209,20 +210,20 @@ clocks = <&clksndsel>; clock-names = "scki"; - VDD1-supply = <&snd_3p3v>; - VDD2-supply = <&snd_3p3v>; - VCCAD1-supply = <&snd_vcc5v>; - VCCAD2-supply = <&snd_vcc5v>; - VCCDA1-supply = <&snd_vcc5v>; - VCCDA2-supply = <&snd_vcc5v>; + VDD1-supply = <®_3p3v>; + VDD2-supply = <®_3p3v>; + VCCAD1-supply = <®_5v>; + VCCAD2-supply = <®_5v>; + VCCDA1-supply = <®_5v>; + VCCDA2-supply = <®_5v>; }; gyroscope@6b { compatible = "st,lsm9ds0-gyro"; reg = <0x6b>; - vdd-supply = <&accel_3v3>; - vddio-supply = <&accel_3v3>; + vdd-supply = <®_3p3v>; + vddio-supply = <®_3p3v>; }; }; }; @@ -348,6 +349,9 @@ &pciec1 { status = "okay"; + + vpcie1v5-supply = <&pcie_1v5>; + vpcie3v3-supply = <&pcie_3v3>; }; &pfc { @@ -417,6 +421,13 @@ pinctrl-names = "default"; status = "okay"; + + gnss { + compatible = "u-blox,neo-m8"; + reset-gpios = <&gpio_exp_75 6 GPIO_ACTIVE_LOW>; + vcc-supply = <®_3p3v>; + current-speed = <9600>; + }; }; &sdhi3 { diff --git a/src/arm64/renesas/white-hawk-common.dtsi b/src/arm64/renesas/white-hawk-common.dtsi new file mode 100644 index 00000000000..c99086edadc --- /dev/null +++ b/src/arm64/renesas/white-hawk-common.dtsi @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the common parts shared by the White Hawk BreakOut + * and White Hawk Single boards + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include "white-hawk-csi-dsi.dtsi" +#include "white-hawk-ethernet.dtsi" + +/ { + can_transceiver0: can-phy0 { + compatible = "nxp,tjr1443"; + #phy-cells = <0>; + enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + max-bitrate = <5000000>; + }; +}; + +&can_clk { + clock-frequency = <40000000>; +}; + +&canfd { + pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>; + pinctrl-names = "default"; + + status = "okay"; + + channel0 { + status = "okay"; + phys = <&can_transceiver0>; + }; + + channel1 { + status = "okay"; + }; +}; + +&i2c0 { + eeprom@51 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "breakout-board"; + reg = <0x51>; + pagesize = <8>; + }; +}; + +&pfc { + can_clk_pins: can-clk { + groups = "can_clk"; + function = "can_clk"; + }; + + canfd0_pins: canfd0 { + groups = "canfd0_data"; + function = "canfd0"; + }; + + canfd1_pins: canfd1 { + groups = "canfd1_data"; + function = "canfd1"; + }; +}; diff --git a/src/arm64/renesas/white-hawk-cpu-common.dtsi b/src/arm64/renesas/white-hawk-cpu-common.dtsi new file mode 100644 index 00000000000..8ac17370ff3 --- /dev/null +++ b/src/arm64/renesas/white-hawk-cpu-common.dtsi @@ -0,0 +1,375 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the common parts shared by the White Hawk CPU and + * White Hawk Single boards + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include +#include +#include + +/ { + aliases { + ethernet0 = &avb0; + serial0 = &hscif0; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial0:921600n8"; + }; + + sn65dsi86_refclk: clk-x6 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + }; + + keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&keys_pins>; + pinctrl-names = "default"; + + key-1 { + gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW47"; + wakeup-source; + debounce-interval = <20>; + }; + + key-2 { + gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW48"; + wakeup-source; + debounce-interval = <20>; + }; + + key-3 { + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW49"; + wakeup-source; + debounce-interval = <20>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-1 { + gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + }; + + led-2 { + gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <2>; + }; + + led-3 { + gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <3>; + }; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@480000000 { + device_type = "memory"; + reg = <0x4 0x80000000 0x0 0x80000000>; + }; + + memory@600000000 { + device_type = "memory"; + reg = <0x6 0x00000000 0x1 0x00000000>; + }; + + mini-dp-con { + compatible = "dp-connector"; + label = "CN5"; + type = "mini"; + + port { + mini_dp_con_in: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + + reg_1p2v: regulator-1p2v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&avb0 { + pinctrl-0 = <&avb0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + tx-internal-delay-ps = <2000>; + status = "okay"; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio7>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; + }; +}; + +&dsi0 { + status = "okay"; + + ports { + port@1 { + dsi0_out: endpoint { + remote-endpoint = <&sn65dsi86_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&du { + status = "okay"; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&hscif0 { + pinctrl-0 = <&hscif0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + io_expander_a: gpio@20 { + compatible = "onnn,pca9654"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + eeprom@50 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "cpu-board"; + reg = <0x50>; + pagesize = <8>; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + + clocks = <&sn65dsi86_refclk>; + clock-names = "refclk"; + + interrupt-parent = <&intc_ex>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + + vccio-supply = <®_1p8v>; + vpll-supply = <®_1p8v>; + vcca-supply = <®_1p2v>; + vcc-supply = <®_1p2v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + sn65dsi86_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + sn65dsi86_out: endpoint { + remote-endpoint = <&mini_dp_con_in>; + }; + }; + }; + }; +}; + +&mmc0 { + pinctrl-0 = <&mmc_pins>; + pinctrl-1 = <&mmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + avb0_pins: avb0 { + mux { + groups = "avb0_link", "avb0_mdio", "avb0_rgmii", + "avb0_txcrefclk"; + function = "avb0"; + }; + + pins_mdio { + groups = "avb0_mdio"; + drive-strength = <21>; + }; + + pins_mii { + groups = "avb0_rgmii"; + drive-strength = <21>; + }; + + }; + + hscif0_pins: hscif0 { + groups = "hscif0_data"; + function = "hscif0"; + }; + + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + + keys_pins: keys { + pins = "GP_5_0", "GP_5_1", "GP_5_2"; + bias-pull-up; + }; + + mmc_pins: mmc { + groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; + function = "mmc"; + power-source = <1800>; + }; + + qspi0_pins: qspi0 { + groups = "qspi0_ctrl", "qspi0_data4"; + function = "qspi0"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk"; + function = "scif_clk"; + }; +}; + +&rpc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + flash@0 { + compatible = "spansion,s25fs512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + reg = <0x0 0x1200000>; + read-only; + }; + user@1200000 { + reg = <0x1200000 0x2e00000>; + }; + }; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&scif_clk { + clock-frequency = <24000000>; +}; diff --git a/src/arm64/renesas/r8a779g0-white-hawk-csi-dsi.dtsi b/src/arm64/renesas/white-hawk-csi-dsi.dtsi similarity index 97% rename from src/arm64/renesas/r8a779g0-white-hawk-csi-dsi.dtsi rename to src/arm64/renesas/white-hawk-csi-dsi.dtsi index f8537f7ea4d..3006b0a64f4 100644 --- a/src/arm64/renesas/r8a779g0-white-hawk-csi-dsi.dtsi +++ b/src/arm64/renesas/white-hawk-csi-dsi.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Source for the R-Car V4H White Hawk CSI/DSI sub-board + * Device Tree Source for the White Hawk CSI/DSI sub-board * * Copyright (C) 2022 Glider bv */ diff --git a/src/arm64/renesas/r8a779g0-white-hawk-ethernet.dtsi b/src/arm64/renesas/white-hawk-ethernet.dtsi similarity index 76% rename from src/arm64/renesas/r8a779g0-white-hawk-ethernet.dtsi rename to src/arm64/renesas/white-hawk-ethernet.dtsi index 4f411f95c67..a218fda337c 100644 --- a/src/arm64/renesas/r8a779g0-white-hawk-ethernet.dtsi +++ b/src/arm64/renesas/white-hawk-ethernet.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Source for the R-Car V4H White Hawk RAVB/Ethernet(1000Base-T1) + * Device Tree Source for the White Hawk RAVB/Ethernet(1000Base-T1) * sub-board * * Copyright (C) 2022 Glider bv diff --git a/src/arm64/rockchip/px30-ringneck-haikou.dts b/src/arm64/rockchip/px30-ringneck-haikou.dts index 16798eb7707..ae398acdcf4 100644 --- a/src/arm64/rockchip/px30-ringneck-haikou.dts +++ b/src/arm64/rockchip/px30-ringneck-haikou.dts @@ -227,6 +227,7 @@ &uart5 { pinctrl-0 = <&uart5_xfer>; + rts-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/src/arm64/rockchip/px30-ringneck.dtsi b/src/arm64/rockchip/px30-ringneck.dtsi index 12397755830..bb1aea82e66 100644 --- a/src/arm64/rockchip/px30-ringneck.dtsi +++ b/src/arm64/rockchip/px30-ringneck.dtsi @@ -347,6 +347,12 @@ }; }; +&pmu_io_domains { + pmuio1-supply = <&vcc_3v3>; + pmuio2-supply = <&vcc_3v3>; + status = "okay"; +}; + &saradc { vref-supply = <&vcc_1v8>; status = "okay"; diff --git a/src/arm64/rockchip/rk3328-rock-pi-e.dts b/src/arm64/rockchip/rk3328-rock-pi-e.dts index 3cda6c627b6..f09d60bbe6c 100644 --- a/src/arm64/rockchip/rk3328-rock-pi-e.dts +++ b/src/arm64/rockchip/rk3328-rock-pi-e.dts @@ -148,7 +148,7 @@ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; clock_in_out = "input"; - phy-handle = <&rtl8211e>; + phy-handle = <&rtl8211>; phy-mode = "rgmii"; phy-supply = <&vcc_io>; pinctrl-names = "default"; @@ -165,7 +165,7 @@ #address-cells = <1>; #size-cells = <0>; - rtl8211e: ethernet-phy@1 { + rtl8211: ethernet-phy@1 { reg = <1>; pinctrl-0 = <ð_phy_int_pin>, <ð_phy_reset_pin>; pinctrl-names = "default"; diff --git a/src/arm64/rockchip/rk3328.dtsi b/src/arm64/rockchip/rk3328.dtsi index 7b4c15c4a9c..b6f045069ee 100644 --- a/src/arm64/rockchip/rk3328.dtsi +++ b/src/arm64/rockchip/rk3328.dtsi @@ -744,11 +744,20 @@ status = "disabled"; ports { - hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + hdmi_in_vop: endpoint { remote-endpoint = <&vop_out_hdmi>; }; }; + + hdmi_out: port@1 { + reg = <1>; + }; }; }; diff --git a/src/arm64/rockchip/rk3399-gru-scarlet.dtsi b/src/arm64/rockchip/rk3399-gru-scarlet.dtsi index 5846a11f0e8..d5e035823eb 100644 --- a/src/arm64/rockchip/rk3399-gru-scarlet.dtsi +++ b/src/arm64/rockchip/rk3399-gru-scarlet.dtsi @@ -663,7 +663,7 @@ camera: &i2c7 { port@1 { reg = <1>; - mipi1_in_panel: endpoint@1 { + mipi1_in_panel: endpoint { remote-endpoint = <&mipi1_out_panel>; }; }; @@ -689,7 +689,6 @@ camera: &i2c7 { ep-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* PERST# asserted in S3 */ - pcie-reset-suspend = <1>; vpcie3v3-supply = <&wlan_3v3>; vpcie1v8-supply = <&pp1800_pcie>; diff --git a/src/arm64/rockchip/rk3399-kobol-helios64.dts b/src/arm64/rockchip/rk3399-kobol-helios64.dts index 9e3aec4440b..9586bb12a5d 100644 --- a/src/arm64/rockchip/rk3399-kobol-helios64.dts +++ b/src/arm64/rockchip/rk3399-kobol-helios64.dts @@ -22,9 +22,6 @@ ethernet0 = &gmac; mmc0 = &sdmmc; mmc1 = &sdhci; - spi1 = &spi1; - spi2 = &spi2; - spi5 = &spi5; }; avdd_0v9_s0: avdd-0v9-s0 { @@ -614,7 +611,7 @@ #size-cells = <0>; interface@0 { /* interface 0 of configuration 1 */ - compatible = "usbbda,8156.config1.0"; + compatible = "usbifbda,8156.config1.0"; reg = <0 1>; }; }; diff --git a/src/arm64/rockchip/rk3399-orangepi.dts b/src/arm64/rockchip/rk3399-orangepi.dts index e7551449e71..e26e2d86279 100644 --- a/src/arm64/rockchip/rk3399-orangepi.dts +++ b/src/arm64/rockchip/rk3399-orangepi.dts @@ -14,7 +14,7 @@ / { model = "Orange Pi RK3399 Board"; - compatible = "rockchip,rk3399-orangepi", "rockchip,rk3399"; + compatible = "xunlong,rk3399-orangepi", "rockchip,rk3399"; aliases { ethernet0 = &gmac; diff --git a/src/arm64/rockchip/rk3399-pinebook-pro.dts b/src/arm64/rockchip/rk3399-pinebook-pro.dts index 054c6a4d1a4..294eb2de263 100644 --- a/src/arm64/rockchip/rk3399-pinebook-pro.dts +++ b/src/arm64/rockchip/rk3399-pinebook-pro.dts @@ -779,7 +779,6 @@ }; &pcie0 { - bus-scan-delay-ms = <1000>; ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; num-lanes = <4>; pinctrl-names = "default"; diff --git a/src/arm64/rockchip/rk3399-puma-haikou.dts b/src/arm64/rockchip/rk3399-puma-haikou.dts index 18a98c4648e..f6f15946579 100644 --- a/src/arm64/rockchip/rk3399-puma-haikou.dts +++ b/src/arm64/rockchip/rk3399-puma-haikou.dts @@ -194,6 +194,8 @@ num-lanes = <4>; pinctrl-names = "default"; pinctrl-0 = <&pcie_clkreqn_cpm>; + vpcie3v3-supply = <&vcc3v3_baseboard>; + vpcie12v-supply = <&dc_12v>; status = "okay"; }; @@ -273,11 +275,12 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + pinctrl-0 = <&uart0_xfer>; status = "okay"; }; &uart2 { + rts-gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/src/arm64/rockchip/rk3399-puma.dtsi b/src/arm64/rockchip/rk3399-puma.dtsi index c08e69391c0..ccbe3a7a1d2 100644 --- a/src/arm64/rockchip/rk3399-puma.dtsi +++ b/src/arm64/rockchip/rk3399-puma.dtsi @@ -79,6 +79,26 @@ regulator-max-microvolt = <5000000>; }; + vcca_0v9: vcca-0v9-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcca_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc_1v8>; + }; + + vcca_1v8: vcca-1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; @@ -416,16 +436,28 @@ gpio1830-supply = <&vcc_1v8>; }; -&pmu_io_domains { - status = "okay"; - pmu1830-supply = <&vcc_1v8>; +&pcie0 { + /* PCIe PHY supplies */ + vpcie0v9-supply = <&vcca_0v9>; + vpcie1v8-supply = <&vcca_1v8>; }; -&pwm2 { - status = "okay"; +&pcie_clkreqn_cpm { + rockchip,pins = + <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; }; &pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&q7_thermal_pin>; + + gpios { + q7_thermal_pin: q7-thermal-pin { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + i2c8 { i2c8_xfer_a: i2c8-xfer { rockchip,pins = @@ -458,11 +490,20 @@ usb3 { usb3_id: usb3-id { rockchip,pins = - <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; }; }; }; +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_1v8>; +}; + +&pwm2 { + status = "okay"; +}; + &sdhci { /* * Signal integrity isn't great at 200MHz but 100MHz has proven stable diff --git a/src/arm64/rockchip/rk3399-rock-pi-4a.dts b/src/arm64/rockchip/rk3399-rock-pi-4a.dts index d5df8939a65..c68f45849c4 100644 --- a/src/arm64/rockchip/rk3399-rock-pi-4a.dts +++ b/src/arm64/rockchip/rk3399-rock-pi-4a.dts @@ -19,6 +19,6 @@ flash@0 { compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <10000000>; + spi-max-frequency = <108000000>; }; }; diff --git a/src/arm64/rockchip/rk3399-rock-pi-4b.dts b/src/arm64/rockchip/rk3399-rock-pi-4b.dts index bee6d758830..6ea3180e57c 100644 --- a/src/arm64/rockchip/rk3399-rock-pi-4b.dts +++ b/src/arm64/rockchip/rk3399-rock-pi-4b.dts @@ -37,7 +37,7 @@ flash@0 { compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <10000000>; + spi-max-frequency = <108000000>; }; }; diff --git a/src/arm64/rockchip/rk3399-rock-pi-4c.dts b/src/arm64/rockchip/rk3399-rock-pi-4c.dts index de2ebe4cb4f..5274938bf1b 100644 --- a/src/arm64/rockchip/rk3399-rock-pi-4c.dts +++ b/src/arm64/rockchip/rk3399-rock-pi-4c.dts @@ -49,7 +49,7 @@ flash@0 { compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <10000000>; + spi-max-frequency = <108000000>; }; }; diff --git a/src/arm64/rockchip/rk3399.dtsi b/src/arm64/rockchip/rk3399.dtsi index 6e12c5a920c..9d5f5b083e3 100644 --- a/src/arm64/rockchip/rk3399.dtsi +++ b/src/arm64/rockchip/rk3399.dtsi @@ -38,6 +38,12 @@ serial2 = &uart2; serial3 = &uart3; serial4 = &uart4; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + spi4 = &spi4; + spi5 = &spi5; }; cpus { @@ -45,7 +51,7 @@ #size-cells = <0>; cpu-map { - cluster0 { + cluster0 { /* Cortex-A53 */ core0 { cpu = <&cpu_l0>; }; @@ -60,7 +66,7 @@ }; }; - cluster1 { + cluster1 { /* Cortex-A72 */ core0 { cpu = <&cpu_b0>; }; @@ -80,6 +86,13 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l>; }; cpu_l1: cpu@1 { @@ -92,6 +105,13 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l>; }; cpu_l2: cpu@2 { @@ -104,6 +124,13 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l>; }; cpu_l3: cpu@3 { @@ -116,6 +143,13 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l>; }; cpu_b0: cpu@100 { @@ -128,6 +162,13 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <436>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b>; thermal-idle { #cooling-cells = <2>; @@ -146,6 +187,13 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <436>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b>; thermal-idle { #cooling-cells = <2>; @@ -154,6 +202,24 @@ }; }; + l2_cache_l: l2-cache-cluster0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + }; + + l2_cache_b: l2-cache-cluster1 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; + }; + idle-states { entry-method = "psci"; @@ -1956,6 +2022,7 @@ hdmi: hdmi@ff940000 { compatible = "rockchip,rk3399-dw-hdmi"; reg = <0x0 0xff940000 0x0 0x20000>; + reg-io-width = <4>; interrupts = ; clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, @@ -1964,13 +2031,16 @@ <&cru PLL_VPLL>; clock-names = "iahb", "isfr", "cec", "grf", "ref"; power-domains = <&power RK3399_PD_HDCP>; - reg-io-width = <4>; rockchip,grf = <&grf>; #sound-dai-cells = <0>; status = "disabled"; ports { - hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; #address-cells = <1>; #size-cells = <0>; @@ -1983,6 +2053,10 @@ remote-endpoint = <&vopl_out_hdmi>; }; }; + + hdmi_out: port@1 { + reg = <1>; + }; }; }; diff --git a/src/arm64/rockchip/rk3566-anbernic-rg-arc-d.dts b/src/arm64/rockchip/rk3566-anbernic-rg-arc-d.dts new file mode 100644 index 00000000000..ab83e8a6161 --- /dev/null +++ b/src/arm64/rockchip/rk3566-anbernic-rg-arc-d.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include "rk3566-anbernic-rg-arc.dtsi" + +/ { + model = "Anbernic RG ARC-D"; + compatible = "anbernic,rg-arc-d", "rockchip,rk3566"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc1; + mmc3 = &sdmmc2; + }; +}; + +&i2c2 { + pinctrl-0 = <&i2c2m1_xfer>; + pinctrl-names = "default"; + status = "okay"; + + touchscreen@14 { + compatible = "goodix,gt927"; + reg = <0x14>; + interrupt-parent = <&gpio4>; + interrupts = ; + irq-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&touch_int>; + pinctrl-names = "default"; + reset-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + touchscreen-inverted-y; + touchscreen-size-x = <640>; + touchscreen-size-y = <480>; + }; +}; + +&pinctrl { + touchscreen { + touch_int: touch_int { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>, + <&emmc_datastrobe>, <&emmc_rstnout>; + pinctrl-names = "default"; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; diff --git a/src/arm64/rockchip/rk3566-anbernic-rg-arc-s.dts b/src/arm64/rockchip/rk3566-anbernic-rg-arc-s.dts new file mode 100644 index 00000000000..6264a8c78d0 --- /dev/null +++ b/src/arm64/rockchip/rk3566-anbernic-rg-arc-s.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include "rk3566-anbernic-rg-arc.dtsi" + +/ { + model = "Anbernic RG ARC-S"; + compatible = "anbernic,rg-arc-s", "rockchip,rk3566"; + + aliases { + mmc1 = &sdmmc0; + mmc2 = &sdmmc1; + mmc3 = &sdmmc2; + }; +}; diff --git a/src/arm64/rockchip/rk3566-anbernic-rg-arc.dtsi b/src/arm64/rockchip/rk3566-anbernic-rg-arc.dtsi new file mode 100644 index 00000000000..a4a60e4a53d --- /dev/null +++ b/src/arm64/rockchip/rk3566-anbernic-rg-arc.dtsi @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include "rk3566-anbernic-rgxx3.dtsi" + +/ { + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&vcc_sys>; + pwms = <&pwm4 0 25000 0>; + }; + + battery: battery { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <3472000>; + charge-term-current-microamp = <300000>; + constant-charge-current-max-microamp = <2000000>; + constant-charge-voltage-max-microvolt = <4200000>; + factory-internal-resistance-micro-ohms = <117000>; + voltage-max-design-microvolt = <4172000>; + voltage-min-design-microvolt = <3400000>; + + ocv-capacity-celsius = <20>; + ocv-capacity-table-0 = <4172000 100>, <4054000 95>, <3984000 90>, <3926000 85>, + <3874000 80>, <3826000 75>, <3783000 70>, <3746000 65>, + <3714000 60>, <3683000 55>, <3650000 50>, <3628000 45>, + <3612000 40>, <3600000 35>, <3587000 30>, <3571000 25>, + <3552000 20>, <3525000 15>, <3492000 10>, <3446000 5>, + <3400000 0>; + }; + + /* Channels reversed for both headphones and speakers. */ + sound { + compatible = "simple-audio-card"; + pinctrl-0 = <&hp_det>; + pinctrl-names = "default"; + simple-audio-card,name = "rk817_ext"; + simple-audio-card,aux-devs = <&spk_amp>; + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphones", + "Speaker", "Internal Speakers"; + simple-audio-card,routing = + "MICL", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR", + "Internal Speakers", "Speaker Amp OUTL", + "Internal Speakers", "Speaker Amp OUTR", + "Speaker Amp INL", "HPOL", + "Speaker Amp INR", "HPOR"; + simple-audio-card,pin-switches = "Internal Speakers"; + + simple-audio-card,codec { + sound-dai = <&rk817>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + }; + + spk_amp: audio-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&spk_amp_enable_h>; + pinctrl-names = "default"; + sound-name-prefix = "Speaker Amp"; + }; +}; + +&cru { + assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, + <&pmucru PLL_PPLL>, <&cru PLL_VPLL>; + assigned-clock-rates = <32768>, <1200000000>, + <200000000>, <128000000>; +}; + +&dsi_dphy0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + dsi0_in: port@0 { + reg = <0>; + dsi0_in_vp1: endpoint { + remote-endpoint = <&vp1_out_dsi0>; + }; + }; + + dsi0_out: port@1 { + reg = <1>; + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; + }; + }; + + panel: panel@0 { + compatible = "anbernic,rg-arc-panel", "sitronix,st7701"; + reg = <0>; + backlight = <&backlight>; + IOVCC-supply = <&vcc3v3_lcd0_n>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst>; + reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + rotation = <90>; + VCC-supply = <&vcc3v3_lcd0_n>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + +/* + * Device uses a non-standard six button layout for a gamepad with X, + * Y, and Z on the top row of buttons and A, B, and C under the bottom + * row. + */ +&gpio_keys_control { + button-a { + gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_LOW>; + label = "A"; + linux,code = ; + }; + + button-b { + gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; + label = "B"; + linux,code = ; + }; + + button-c { + gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>; + label = "C"; + linux,code = ; + }; + + button-left { + gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; + label = "DPAD-LEFT"; + linux,code = ; + }; + + button-r1 { + gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; + label = "TR"; + linux,code = ; + }; + + button-r2 { + gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; + label = "TR2"; + linux,code = ; + }; + + button-right { + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; + label = "DPAD-RIGHT"; + linux,code = ; + }; + + button-x { + gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + label = "X"; + linux,code = ; + }; + + button-y { + gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; + label = "Y"; + linux,code = ; + }; + + button-z { + gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; + label = "Z"; + linux,code = ; + }; +}; + +&pinctrl { + audio-amplifier { + spk_amp_enable_h: spk-amp-enable-h { + rockchip,pins = + <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gpio-lcd { + lcd_rst: lcd-rst { + rockchip,pins = + <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = + <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm4 { + status = "okay"; +}; + +&rk817 { + rk817_charger: charger { + monitored-battery = <&battery>; + rockchip,resistor-sense-micro-ohms = <10000>; + rockchip,sleep-enter-current-microamp = <300000>; + rockchip,sleep-filter-current-microamp = <100000>; + }; +}; + +&vp1 { + vp1_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 { + reg = ; + remote-endpoint = <&dsi0_in_vp1>; + }; +}; diff --git a/src/arm64/rockchip/rk3566-anbernic-rg353x.dtsi b/src/arm64/rockchip/rk3566-anbernic-rg353x.dtsi index 2a2821f4c58..63a18ff36ce 100644 --- a/src/arm64/rockchip/rk3566-anbernic-rg353x.dtsi +++ b/src/arm64/rockchip/rk3566-anbernic-rg353x.dtsi @@ -8,11 +8,73 @@ #include "rk3566-anbernic-rgxx3.dtsi" / { + adc-joystick { + compatible = "adc-joystick"; + io-channels = <&adc_mux 0>, + <&adc_mux 1>, + <&adc_mux 2>, + <&adc_mux 3>; + pinctrl-0 = <&joy_mux_en>; + pinctrl-names = "default"; + poll-interval = <60>; + #address-cells = <1>; + #size-cells = <0>; + + axis@0 { + reg = <0>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <1023 15>; + linux,code = ; + }; + + axis@1 { + reg = <1>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <15 1023>; + linux,code = ; + }; + + axis@2 { + reg = <2>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <15 1023>; + linux,code = ; + }; + + axis@3 { + reg = <3>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <1023 15>; + linux,code = ; + }; + }; + + adc_mux: adc-mux { + compatible = "io-channel-mux"; + channels = "left_x", "right_x", "left_y", "right_y"; + #io-channel-cells = <1>; + io-channels = <&saradc 3>; + io-channel-names = "parent"; + mux-controls = <&gpio_mux>; + settle-time-us = <100>; + }; + backlight: backlight { compatible = "pwm-backlight"; power-supply = <&vcc_sys>; pwms = <&pwm4 0 25000 0>; }; + + gpio_mux: mux-controller { + compatible = "gpio-mux"; + mux-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>, + <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + #mux-control-cells = <0>; + }; }; &cru { @@ -83,6 +145,18 @@ linux,code = ; }; + button-thumbl { + gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; + label = "THUMBL"; + linux,code = ; + }; + + button-thumbr { + gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>; + label = "THUMBR"; + linux,code = ; + }; + button-y { gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; label = "WEST"; diff --git a/src/arm64/rockchip/rk3566-anbernic-rg503.dts b/src/arm64/rockchip/rk3566-anbernic-rg503.dts index c763c7f3b1b..94e6dd61a2d 100644 --- a/src/arm64/rockchip/rk3566-anbernic-rg503.dts +++ b/src/arm64/rockchip/rk3566-anbernic-rg503.dts @@ -17,6 +17,61 @@ mmc2 = &sdmmc2; }; + adc-joystick { + compatible = "adc-joystick"; + io-channels = <&adc_mux 0>, + <&adc_mux 1>, + <&adc_mux 2>, + <&adc_mux 3>; + pinctrl-0 = <&joy_mux_en>; + pinctrl-names = "default"; + poll-interval = <60>; + #address-cells = <1>; + #size-cells = <0>; + + axis@0 { + reg = <0>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <1023 15>; + linux,code = ; + }; + + axis@1 { + reg = <1>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <15 1023>; + linux,code = ; + }; + + axis@2 { + reg = <2>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <15 1023>; + linux,code = ; + }; + + axis@3 { + reg = <3>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <1023 15>; + linux,code = ; + }; + }; + + adc_mux: adc-mux { + compatible = "io-channel-mux"; + channels = "left_x", "right_x", "left_y", "right_y"; + #io-channel-cells = <1>; + io-channels = <&saradc 3>; + io-channel-names = "parent"; + mux-controls = <&gpio_mux>; + settle-time-us = <100>; + }; + battery: battery { compatible = "simple-battery"; charge-full-design-microamp-hours = <3472000>; @@ -36,6 +91,13 @@ <3400000 0>; }; + gpio_mux: mux-controller { + compatible = "gpio-mux"; + mux-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>, + <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + #mux-control-cells = <0>; + }; + gpio_spi: spi { compatible = "spi-gpio"; pinctrl-names = "default"; @@ -174,6 +236,18 @@ linux,code = ; }; + button-thumbl { + gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; + label = "THUMBL"; + linux,code = ; + }; + + button-thumbr { + gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>; + label = "THUMBR"; + linux,code = ; + }; + button-y { gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; label = "WEST"; diff --git a/src/arm64/rockchip/rk3566-anbernic-rgxx3.dtsi b/src/arm64/rockchip/rk3566-anbernic-rgxx3.dtsi index 8cbf3d9a4f2..18b8c2e7bef 100644 --- a/src/arm64/rockchip/rk3566-anbernic-rgxx3.dtsi +++ b/src/arm64/rockchip/rk3566-anbernic-rgxx3.dtsi @@ -14,51 +14,6 @@ stdout-path = "serial2:1500000n8"; }; - adc-joystick { - compatible = "adc-joystick"; - io-channels = <&adc_mux 0>, - <&adc_mux 1>, - <&adc_mux 2>, - <&adc_mux 3>; - pinctrl-0 = <&joy_mux_en>; - pinctrl-names = "default"; - poll-interval = <60>; - #address-cells = <1>; - #size-cells = <0>; - - axis@0 { - reg = <0>; - abs-flat = <32>; - abs-fuzz = <32>; - abs-range = <1023 15>; - linux,code = ; - }; - - axis@1 { - reg = <1>; - abs-flat = <32>; - abs-fuzz = <32>; - abs-range = <15 1023>; - linux,code = ; - }; - - axis@2 { - reg = <2>; - abs-flat = <32>; - abs-fuzz = <32>; - abs-range = <15 1023>; - linux,code = ; - }; - - axis@3 { - reg = <3>; - abs-flat = <32>; - abs-fuzz = <32>; - abs-range = <1023 15>; - linux,code = ; - }; - }; - adc_keys: adc-keys { compatible = "adc-keys"; io-channels = <&saradc 0>; @@ -77,16 +32,6 @@ }; }; - adc_mux: adc-mux { - compatible = "io-channel-mux"; - channels = "left_x", "right_x", "left_y", "right_y"; - #io-channel-cells = <1>; - io-channels = <&saradc 3>; - io-channel-names = "parent"; - mux-controls = <&gpio_mux>; - settle-time-us = <100>; - }; - gpio_keys_control: gpio-keys-control { compatible = "gpio-keys"; pinctrl-0 = <&btn_pins_ctrl>; @@ -128,18 +73,6 @@ linux,code = ; }; - button-thumbl { - gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; - label = "THUMBL"; - linux,code = ; - }; - - button-thumbr { - gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>; - label = "THUMBR"; - linux,code = ; - }; - button-up { gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>; label = "DPAD-UP"; @@ -172,13 +105,6 @@ }; }; - gpio_mux: mux-controller { - compatible = "gpio-mux"; - mux-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>, - <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; - #mux-control-cells = <0>; - }; - hdmi-con { compatible = "hdmi-connector"; ddc-i2c-bus = <&i2c5>; diff --git a/src/arm64/rockchip/rk3566-lubancat-1.dts b/src/arm64/rockchip/rk3566-lubancat-1.dts index 6ecdf5d2833..c1194d1e438 100644 --- a/src/arm64/rockchip/rk3566-lubancat-1.dts +++ b/src/arm64/rockchip/rk3566-lubancat-1.dts @@ -447,7 +447,6 @@ &pcie2x1 { reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - disable-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie>; status = "okay"; }; diff --git a/src/arm64/rockchip/rk3566-pinetab2-v0.1.dts b/src/arm64/rockchip/rk3566-pinetab2-v0.1.dts new file mode 100644 index 00000000000..5fe6ca5da9d --- /dev/null +++ b/src/arm64/rockchip/rk3566-pinetab2-v0.1.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-pinetab2.dtsi" + +/ { + model = "Pine64 PineTab2 v0.1"; + compatible = "pine64,pinetab2-v0.1", "pine64,pinetab2", "rockchip,rk3566"; +}; + +&lcd { + reset-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pwren_h &lcd0_rst_l>; +}; + +&pinctrl { + lcd0 { + lcd0_rst_l: lcd0-rst-l { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc1 { + vmmc-supply = <&vcc3v3_sys>; +}; diff --git a/src/arm64/rockchip/rk3566-pinetab2-v2.0.dts b/src/arm64/rockchip/rk3566-pinetab2-v2.0.dts new file mode 100644 index 00000000000..9349541cbbd --- /dev/null +++ b/src/arm64/rockchip/rk3566-pinetab2-v2.0.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-pinetab2.dtsi" + +/ { + model = "Pine64 PineTab2 v2.0"; + compatible = "pine64,pinetab2-v2.0", "pine64,pinetab2", "rockchip,rk3566"; +}; + +&gpio_keys { + pinctrl-0 = <&kb_id_det>, <&hall_int_l>; + + event-hall-sensor { + debounce-interval = <20>; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + label = "Hall Sensor"; + linux,code = ; + linux,input-type = ; + wakeup-event-action = ; + wakeup-source; + }; +}; + +&lcd { + reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pwren_h &lcd0_rst_l>; +}; + +&pinctrl { + lcd0 { + lcd0_rst_l: lcd0-rst-l { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hall { + hall_int_l: hall-int-l { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc1 { + vmmc-supply = <&vcc_sys>; +}; diff --git a/src/arm64/rockchip/rk3566-pinetab2.dtsi b/src/arm64/rockchip/rk3566-pinetab2.dtsi new file mode 100644 index 00000000000..db40281eafb --- /dev/null +++ b/src/arm64/rockchip/rk3566-pinetab2.dtsi @@ -0,0 +1,943 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include +#include +#include +#include +#include +#include +#include +#include "rk3566.dtsi" + +/ { + chassis-type = "tablet"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc0; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <25>; + + button-vol-up { + label = "Volume Up"; + linux,code = ; + press-threshold-microvolt = <297500>; + }; + + button-vol-down { + label = "Volume Down"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = <20 220>; + num-interpolated-steps = <200>; + default-brightness-level = <100>; + power-supply = <&vcc_sys>; + }; + + battery: battery { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <6000000>; + charge-term-current-microamp = <300000>; + constant-charge-current-max-microamp = <2000000>; + constant-charge-voltage-max-microvolt = <4300000>; + voltage-max-design-microvolt = <4350000>; + voltage-min-design-microvolt = <3400000>; + + ocv-capacity-celsius = <20>; + ocv-capacity-table-0 = <4322000 100>, <4250000 95>, <4192000 90>, <4136000 85>, + <4080000 80>, <4022000 75>, <3972000 70>, <3928000 65>, + <3885000 60>, <3833000 55>, <3798000 50>, <3780000 45>, + <3776000 40>, <3773000 35>, <3755000 30>, <3706000 25>, + <3640000 20>, <3589000 15>, <3535000 10>, <3492000 5>, + <3400000 0>; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&kb_id_det>; + + tablet-mode-switch { + debounce-interval = <20>; + gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + label = "Tablet Mode"; + linux,input-type = ; + linux,code = ; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + led-0 { + compatible = "regulator-led"; + vled-supply = <&vcc5v0_flashled>; + color = ; + function = LED_FUNCTION_FLASH; + }; + + rk817-sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det_l>; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rk817_ext"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphones", + "Speaker", "Internal Speakers"; + + simple-audio-card,routing = + "MICR", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR", + "Internal Speakers", "Speaker Amplifier OUTL", + "Internal Speakers", "Speaker Amplifier OUTR", + "Speaker Amplifier INL", "HPOL", + "Speaker Amplifier INR", "HPOR"; + simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + simple-audio-card,aux-devs = <&speaker_amp>; + simple-audio-card,pin-switches = "Internal Speakers"; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk817>; + }; + }; + + speaker_amp: speaker-amplifier { + compatible = "simple-audio-amplifier"; + pinctrl-names = "default"; + pinctrl-0 = <&spk_ctl>; + enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + sound-name-prefix = "Speaker Amplifier"; + VCC-supply = <&vcc_bat>; + }; + + vcc_3v3: vcc-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_minipcie: vcc3v3-minipcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwren_h>; + regulator-name = "vcc3v3_minipcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + vcc3v3_sd: vcc3v3-sd-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwren_l>; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc5v0_flashled: vcc5v0-flashled-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&flash_led_en_h>; + regulator-name = "vcc5v0_flashled"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v_midu>; + }; + + vcc5v0_usb_host0: vcc5v0-usb-host0-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren1_h>; + regulator-name = "vcc5v0_usb_host0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v_midu>; + }; + + vcc5v0_usb_host2: vcc5v0-usb-host2-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren2_h>; + regulator-name = "vcc5v0_usb_host2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v_midu>; + }; + + vcc_bat: vcc-bat-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_bat"; + regulator-always-on; + regulator-boot-on; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_bat>; + }; + + vdd1v2_dvp: vdd1v2-dvp-regulator { + compatible = "regulator-fixed"; + regulator-name = "vdd1v2_dvp"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc_3v3>; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&cru { + assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, + <&pmucru PLL_PPLL>, <&cru PLL_VPLL>; + assigned-clock-rates = <32768>, <1200000000>, <200000000>, <500000000>; + assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>; +}; + +&csi_dphy { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + clock-master; + #address-cells = <1>; + #size-cells = <0>; + + lcd: panel@0 { + compatible = "boe,th101mb31ig002-28a"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + rotation = <90>; + power-supply = <&vcc_3v3>; + + port@0 { + panel_in_dsi: endpoint@0 { + remote-endpoint = <&dsi0_out_con>; + }; + }; + }; +}; + +&dsi0_in { + dsi0_in_vp1: endpoint { + remote-endpoint = <&vp1_out_dsi0>; + }; +}; + +&dsi0_out { + dsi0_out_con: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; +}; + +&dsi_dphy0 { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_npu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda_0v9_p>; + avdd-1v8-supply = <&vcc_1v8>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; + rockchip,system-power-controller; + #sound-dai-cells = <0>; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&vcc5v_midu>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu_npu: DCDC_REG2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc3v3_sys"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdda_0v9_p: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9_p"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v_midu: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "boost"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vbus: OTG_SWITCH { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "otg_switch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + charger { + monitored-battery = <&battery>; + rockchip,resistor-sense-micro-ohms = <10000>; + rockchip,sleep-enter-current-microamp = <300000>; + rockchip,sleep-filter-current-microamp = <100000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + touchscreen@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int_l_pmuio2>, <&tp_rst_l_pmuio2>; + AVDD28-supply = <&vcc3v3_pmu>; + VDDIO-supply = <&vcca1v8_pmu>; + irq-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c2m1_xfer>; + status = "okay"; + + vcm@c { + compatible = "dongwoon,dw9714"; + reg = <0x0c>; + vcc-supply = <&vcc1v8_dvp>; + }; + + camera@36 { + compatible = "ovti,ov5648"; + reg = <0x36>; + pinctrl-names = "default"; + pinctrl-0 = <&camerab_pdn_l &camerab_rst_l>; + + clocks = <&cru CLK_CIF_OUT>; + assigned-clocks = <&cru CLK_CIF_OUT>; + assigned-clock-rates = <24000000>; + + avdd-supply = <&vcc2v8_dvp>; + dvdd-supply = <&vdd1v2_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + powerdown-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>; + + port { + endpoint { + data-lanes = <1 2>; + remote-endpoint = <0>; + link-frequencies = /bits/ 64 <210000000 168000000>; + }; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + accelerometer@18 { + compatible = "silan,sc7a20"; + reg = <0x18>; + interrupt-parent = <&gpio3>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&gsensor_int_l>; + st,drdy-int-pin = <1>; + vdd-supply = <&vcc_1v8>; + vddio-supply = <&vcc_1v8>; + mount-matrix = "1", "0", "0", + "0", "0", "1", + "0", "1", "0"; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_minipcie>; + status = "okay"; +}; + +&pinctrl { + camerab { + camerab_pdn_l: camerab-pdn-l { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + camerab_rst_l: camerab-rst-l { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + cameraf { + cameraf_pdn_l: cameraf-pdn-l { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cameraf_rst_l: cameraf-rst-l { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + flash { + flash_led_en_h: flash-led-en-h { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + fspi { + fspi_dual_io_pins: fspi-dual-io-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PD0 1 &pcfg_pull_none>, + /* fspi_cs0n */ + <1 RK_PD3 1 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PD1 1 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PD2 1 &pcfg_pull_none>; + }; + }; + + gsensor { + gsensor_int_l: gsensor-int-l { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + kb { + kb_id_det: kb-id-det { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_pwren_h: lcd-pwren-h { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_pwren_h: pcie-pwren-h { + rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_reset_h: pcie-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_pwren_l: sdmmc-pwren-l { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sound { + hp_det_l: hp-det-l { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + spk_ctl: spk-ctl { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + tp { + tp_int_l_pmuio2: tp-int-l-pmuio2 { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + tp_rst_l_pmuio2: tp-rst-l-pmuio2 { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usbcc_int_l: usbcc-int-l { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_host_pwren1_h: usb-host-pwren1-h { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_host_pwren2_h: usb-host-pwren2-h { + rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + host_wake_wl: host-wake-wl { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_wake_host_h: wifi-wake-host-h { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcca1v8_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_1v8>; + vccio6-supply = <&vcc1v8_dvp>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs200-1_8v; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 + &emmc_clk + &emmc_cmd + &emmc_datastrobe + &emmc_rstnout>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 + &sdmmc0_clk + &sdmmc0_cmd + &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 + &sdmmc1_cmd + &sdmmc1_clk>; + sd-uhs-sdr104; + vqmmc-supply = <&vcca1v8_pmu>; + status = "okay"; +}; + +&sfc { + pinctrl-names = "default"; + pinctrl-0 = <&fspi_dual_io_pins>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <1>; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host0>; + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb_host2>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; + +&vp1 { + vp1_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 { + reg = ; + remote-endpoint = <&dsi0_in_vp1>; + }; +}; diff --git a/src/arm64/rockchip/rk3566-powkiddy-rgb10max3.dts b/src/arm64/rockchip/rk3566-powkiddy-rgb10max3.dts new file mode 100644 index 00000000000..e5a474e681d --- /dev/null +++ b/src/arm64/rockchip/rk3566-powkiddy-rgb10max3.dts @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include "rk3566-powkiddy-rk2023.dtsi" + +/ { + model = "Powkiddy RGB10MAX3"; + compatible = "powkiddy,rgb10max3", "rockchip,rk3566"; +}; + +&bluetooth { + compatible = "realtek,rtl8723ds-bt"; +}; + +&cru { + assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, + <&pmucru PLL_PPLL>, <&cru PLL_VPLL>; + assigned-clock-rates = <32768>, <1200000000>, + <200000000>, <126400000>; +}; + +&dsi0 { + panel: panel@0 { + compatible = "powkiddy,rgb10max3-panel"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc3v3_lcd0_n>; + pinctrl-0 = <&lcd_rst>; + pinctrl-names = "default"; + reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; + rotation = <270>; + vcc-supply = <&vcc3v3_lcd0_n>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + +&green_led { + default-state = "on"; + function = LED_FUNCTION_POWER; +}; + +&i2c0 { + vdd_cpu: regulator@40 { + compatible = "fcs,fan53555"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-name = "vdd_cpu"; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&leds { + amber_led: led-2 { + color = ; + function = LED_FUNCTION_CHARGING; + max-brightness = <255>; + pwms = <&pwm0 0 25000 0>; + }; +}; + +&pwm0 { + pinctrl-0 = <&pwm0m1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&red_led { + default-state = "off"; + function = LED_FUNCTION_STATUS; +}; diff --git a/src/arm64/rockchip/rk3566-powkiddy-rgb30.dts b/src/arm64/rockchip/rk3566-powkiddy-rgb30.dts index 0ac64f043b8..1f567a14ac8 100644 --- a/src/arm64/rockchip/rk3566-powkiddy-rgb30.dts +++ b/src/arm64/rockchip/rk3566-powkiddy-rgb30.dts @@ -37,3 +37,21 @@ }; }; }; + +&i2c0 { + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-name = "vdd_cpu"; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; diff --git a/src/arm64/rockchip/rk3566-powkiddy-rk2023.dts b/src/arm64/rockchip/rk3566-powkiddy-rk2023.dts index ba32d0793dc..bc9933d9e26 100644 --- a/src/arm64/rockchip/rk3566-powkiddy-rk2023.dts +++ b/src/arm64/rockchip/rk3566-powkiddy-rk2023.dts @@ -36,3 +36,21 @@ }; }; }; + +&i2c0 { + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-name = "vdd_cpu"; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; diff --git a/src/arm64/rockchip/rk3566-powkiddy-rk2023.dtsi b/src/arm64/rockchip/rk3566-powkiddy-rk2023.dtsi index 0fa8f06f94c..3ab751a01cb 100644 --- a/src/arm64/rockchip/rk3566-powkiddy-rk2023.dtsi +++ b/src/arm64/rockchip/rk3566-powkiddy-rk2023.dtsi @@ -614,22 +614,6 @@ rockchip,sleep-filter-current-microamp = <100000>; }; }; - - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1390000>; - regulator-name = "vdd_cpu"; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc_sys>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; }; &i2c5 { @@ -805,7 +789,7 @@ uart-has-rtscts; status = "okay"; - bluetooth { + bluetooth: bluetooth { compatible = "realtek,rtl8821cs-bt", "realtek,rtl8723bs-bt"; device-wake-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; enable-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; diff --git a/src/arm64/rockchip/rk3568-bpi-r2-pro.dts b/src/arm64/rockchip/rk3568-bpi-r2-pro.dts index f9127ddfbb7..c87fad2c34c 100644 --- a/src/arm64/rockchip/rk3568-bpi-r2-pro.dts +++ b/src/arm64/rockchip/rk3568-bpi-r2-pro.dts @@ -13,7 +13,7 @@ / { model = "Bananapi-R2 Pro (RK3568) DDR4 Board"; - compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568"; + compatible = "sinovoip,rk3568-bpi-r2pro", "rockchip,rk3568"; aliases { ethernet0 = &gmac0; @@ -416,6 +416,8 @@ vccio_sd: LDO_REG5 { regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; @@ -525,9 +527,9 @@ #address-cells = <1>; #size-cells = <0>; - switch@0 { + switch@1f { compatible = "mediatek,mt7531"; - reg = <0>; + reg = <0x1f>; ports { #address-cells = <1>; diff --git a/src/arm64/rockchip/rk3568-lubancat-2.dts b/src/arm64/rockchip/rk3568-lubancat-2.dts index a8a4cc190eb..a3112d5df20 100644 --- a/src/arm64/rockchip/rk3568-lubancat-2.dts +++ b/src/arm64/rockchip/rk3568-lubancat-2.dts @@ -523,7 +523,6 @@ &pcie2x1 { reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; - disable-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_mini_pcie>; status = "okay"; }; diff --git a/src/arm64/rockchip/rk3568-qnap-ts433.dts b/src/arm64/rockchip/rk3568-qnap-ts433.dts new file mode 100644 index 00000000000..6a998166003 --- /dev/null +++ b/src/arm64/rockchip/rk3568-qnap-ts433.dts @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2024 Uwe Kleine-König + */ + +/dts-v1/; + +#include +#include "rk3568.dtsi" + +/ { + model = "Qnap TS-433-4G NAS System 4-Bay"; + compatible = "qnap,ts433", "rockchip,rk3568"; +}; + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + rx_delay = <0x2f>; + tx_delay = <0x3c>; + status = "okay"; +}; + +&i2c0 { + pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c1 { + status = "okay"; + + rtc@51 { + compatible = "microcrystal,rv8263"; + reg = <0x51>; + wakeup-source; + }; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x1 { + /* The downstream dts has: rockchip,bifurcation, XXX: find out what this is about */ + reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + status = "okay"; +}; + +/* + * Pins available on CN3 connector at TTL voltage level (3V3). + * ,_ _. + * |1234| 1=TX 2=VCC + * `----' 3=RX 4=GND + */ +&uart2 { + status = "okay"; +}; diff --git a/src/arm64/rockchip/rk356x.dtsi b/src/arm64/rockchip/rk356x.dtsi index c19c0f1b377..92f96ec0138 100644 --- a/src/arm64/rockchip/rk356x.dtsi +++ b/src/arm64/rockchip/rk356x.dtsi @@ -597,6 +597,7 @@ compatible = "rockchip,rk3568-vpu"; reg = <0x0 0xfdea0000 0x0 0x800>; interrupts = ; + interrupt-names = "vdpu"; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; clock-names = "aclk", "hclk"; iommus = <&vdpu_mmu>; @@ -1123,7 +1124,7 @@ dmas = <&dmac1 4>, <&dmac1 5>; dma-names = "tx", "rx"; resets = <&cru SRST_M_I2S2_2CH>; - reset-names = "m"; + reset-names = "tx-m"; rockchip,grf = <&grf>; pinctrl-names = "default"; pinctrl-0 = <&i2s2m0_sclktx diff --git a/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi b/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi index cce1c8e8358..94ecb9b4f98 100644 --- a/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi +++ b/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi @@ -216,9 +216,9 @@ pinctrl-0 = <&i2c7m0_xfer>; status = "okay"; - es8316: audio-codec@11 { + es8316: audio-codec@10 { compatible = "everest,es8316"; - reg = <0x11>; + reg = <0x10>; assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; assigned-clock-rates = <12288000>; clocks = <&cru I2S0_8CH_MCLKOUT>; diff --git a/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi b/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi new file mode 100644 index 00000000000..c0d4a15323e --- /dev/null +++ b/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi @@ -0,0 +1,466 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. + */ + +#include +#include + +/ { + aliases { + mmc0 = &sdhci; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led_user: led-0 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&led_user_en>; + }; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&pinctrl { + leds { + led_user_en: led_user_en { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + + pmic@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name = "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-name = "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-name = "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-name = "vdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; diff --git a/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dts b/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dts index be6a4f4f90f..46d5e21d4d2 100644 --- a/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dts +++ b/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dts @@ -6,18 +6,10 @@ /dts-v1/; #include "rk3588.dtsi" #include "rk3588-edgeble-neu6a.dtsi" +#include "rk3588-edgeble-neu6a-io.dtsi" / { model = "Edgeble Neu6A IO Board"; compatible = "edgeble,neural-compute-module-6a-io", "edgeble,neural-compute-module-6a", "rockchip,rk3588"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; -}; - -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; }; diff --git a/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi b/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi new file mode 100644 index 00000000000..963e880ccc1 --- /dev/null +++ b/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. + */ + +#include + +/ { + chosen { + stdout-path = "serial2:1500000n8"; + }; + + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc3v3_pcie3x2: vcc3v3-pcie3x2-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; /* PCIE_4G_PWEN */ + pinctrl-names = "default"; + pinctrl-0 = <&pcie3x2_vcc3v3_en>; + regulator-name = "vcc3v3_pcie3x2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie3x4: vcc3v3-pcie3x4-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; /* PCIE30x4_PWREN_H */ + pinctrl-names = "default"; + pinctrl-0 = <&pcie3x4_vcc3v3_en>; + regulator-name = "vcc3v3_pcie3x4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +/* ETH */ +&pcie2x1l0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_0_rst>; + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; /* PCIE20_1_PERST_L */ + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +/* B-Key and E-Key */ +&pcie3x2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3x2_rst>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTn_M1_L */ + vpcie3v3-supply = <&vcc3v3_pcie3x2>; + status = "okay"; +}; + +/* M-Key */ +&pcie3x4 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3x4_rst>; + reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; /* PCIE30X2_PERSTn_M1_L */ + vpcie3v3-supply = <&vcc3v3_pcie3x4>; + status = "okay"; +}; + +&pinctrl { + pcie2 { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie3 { + pcie3x2_rst: pcie3x2-rst { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie3x2_vcc3v3_en: pcie3x2-vcc3v3-en { + rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie3x4_rst: pcie3x4-rst { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie3x4_vcc3v3_en: pcie3x4-vcc3v3-en { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +/* FAN */ +&pwm2 { + pinctrl-0 = <&pwm2m1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +/* RS232 */ +&uart6 { + pinctrl-0 = <&uart6m0_xfer>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* RS485 */ +&uart7 { + pinctrl-0 = <&uart7m2_xfer>; + pinctrl-names = "default"; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + /* connected to USB hub, which is powered by vcc5v0_sys */ + phy-supply = <&vcc5v0_sys>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/src/arm64/rockchip/rk3588-edgeble-neu6a-wifi.dtso b/src/arm64/rockchip/rk3588-edgeble-neu6a-wifi.dtso new file mode 100644 index 00000000000..e9a3855e875 --- /dev/null +++ b/src/arm64/rockchip/rk3588-edgeble-neu6a-wifi.dtso @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + * + * DT-overlay for Edgeble On-SoM WiFi6/BT M.2 1216 modules, + * - AW-XM548NF + * - Intel 8260D2W + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + vcc3v3_pcie2x1l1: vcc3v3-pcie2x1l1-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; /* WIFI_3V3_EN */ + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_1_vcc3v3_en>; + regulator-name = "vcc3v3_pcie2x1l1"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy2_psu { + status = "okay"; +}; + +/* WiFi6 */ +&pcie2x1l1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_1_rst>; + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; /* PCIE20_2_WIFI_PERSTn */ + vpcie3v3-supply = <&vcc3v3_pcie2x1l1>; + status = "okay"; +}; + +&pinctrl { + pcie2 { + pcie2_1_rst: pcie2-1-rst { + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_1_vcc3v3_en: pcie2-1-vcc-en { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/src/arm64/rockchip/rk3588-edgeble-neu6a.dtsi b/src/arm64/rockchip/rk3588-edgeble-neu6a.dtsi index 727580aaa10..4c76a00b41e 100644 --- a/src/arm64/rockchip/rk3588-edgeble-neu6a.dtsi +++ b/src/arm64/rockchip/rk3588-edgeble-neu6a.dtsi @@ -3,29 +3,8 @@ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. */ +#include "rk3588-edgeble-neu6a-common.dtsi" + / { compatible = "edgeble,neural-compute-module-6a", "rockchip,rk3588"; - - aliases { - mmc0 = &sdhci; - }; - - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - status = "okay"; }; diff --git a/src/arm64/rockchip/rk3588-edgeble-neu6b-io.dts b/src/arm64/rockchip/rk3588-edgeble-neu6b-io.dts index 070baeb6343..0d6f1be69ac 100644 --- a/src/arm64/rockchip/rk3588-edgeble-neu6b-io.dts +++ b/src/arm64/rockchip/rk3588-edgeble-neu6b-io.dts @@ -6,84 +6,10 @@ /dts-v1/; #include "rk3588j.dtsi" #include "rk3588-edgeble-neu6b.dtsi" +#include "rk3588-edgeble-neu6a-io.dtsi" / { model = "Edgeble Neu6B IO Board"; compatible = "edgeble,neural-compute-module-6a-io", "edgeble,neural-compute-module-6b", "rockchip,rk3588"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&i2c6 { - status = "okay"; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <0>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - wakeup-source; - }; -}; - -&pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -/* FAN */ -&pwm2 { - pinctrl-0 = <&pwm2m1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sata0 { - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - no-sdio; - no-mmc; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_s3>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; -}; - -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; - -/* RS232 */ -&uart6 { - pinctrl-0 = <&uart6m0_xfer>; - pinctrl-names = "default"; - status = "okay"; -}; - -/* RS485 */ -&uart7 { - pinctrl-0 = <&uart7m2_xfer>; - pinctrl-names = "default"; - status = "okay"; }; diff --git a/src/arm64/rockchip/rk3588-edgeble-neu6b.dtsi b/src/arm64/rockchip/rk3588-edgeble-neu6b.dtsi index 017559bba37..c4634bc09fb 100644 --- a/src/arm64/rockchip/rk3588-edgeble-neu6b.dtsi +++ b/src/arm64/rockchip/rk3588-edgeble-neu6b.dtsi @@ -3,387 +3,8 @@ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. */ +#include "rk3588-edgeble-neu6a-common.dtsi" + / { compatible = "edgeble,neural-compute-module-6b", "rockchip,rk3588"; - - aliases { - mmc0 = &sdhci; - }; - - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - status = "okay"; -}; - -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - num-cs = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - - pmic@0 { - compatible = "rockchip,rk806"; - spi-max-frequency = <1000000>; - reg = <0x0>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { - regulator-name = "vdd_gpu_s0"; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <400>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { - regulator-name = "vdd_cpu_lit_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-name = "vdd_log_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { - regulator-name = "vdd_vdenc_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-init-microvolt = <750000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg5 { - regulator-name = "vdd_ddr_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: dcdc-reg6 { - regulator-name = "vdd2_ddr_s3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-name = "vdd_2v0_pldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: dcdc-reg8 { - regulator-name = "vcc_3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-name = "vddq_ddr_s0"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: dcdc-reg10 { - regulator-name = "vcc_1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-name = "avcc_1v8_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s0: pldo-reg2 { - regulator-name = "vcc_1v8_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: pldo-reg3 { - regulator-name = "avdd_1v2_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: pldo-reg4 { - regulator-name = "vcc_3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-name = "vccio_sd_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-name = "pldo6_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-name = "vdd_0v75_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_ddr_pll_s0: nldo-reg2 { - regulator-name = "vdd_ddr_pll_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: nldo-reg3 { - regulator-name = "avdd_0v75_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: nldo-reg4 { - regulator-name = "vdd_0v85_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: nldo-reg5 { - regulator-name = "vdd_0v75_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; }; diff --git a/src/arm64/rockchip/rk3588-nanopc-t6.dts b/src/arm64/rockchip/rk3588-nanopc-t6.dts index 997b516c253..ad8e36a339d 100644 --- a/src/arm64/rockchip/rk3588-nanopc-t6.dts +++ b/src/arm64/rockchip/rk3588-nanopc-t6.dts @@ -159,6 +159,29 @@ regulator-max-microvolt = <3300000>; vin-supply = <&vcc5v0_sys>; }; + + vcc3v3_sd_s0: vcc3v3-sd-s0-regulator { + compatible = "regulator-fixed"; + enable-active-low; + gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_LOW>; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc3v3_sd_s0"; + vin-supply = <&vcc_3v3_s3>; + }; + + vdd_4g_3v3: vdd-4g-3v3-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pin_4g_lte_pwren>; + regulator-name = "vdd_4g_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; }; &combphy0_ps { @@ -504,6 +527,10 @@ }; usb { + pin_4g_lte_pwren: 4g-lte-pwren { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + typec5v_pwren: typec5v-pwren { rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; }; @@ -539,11 +566,12 @@ bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; disable-wp; no-mmc; no-sdio; sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_s3>; + vmmc-supply = <&vcc3v3_sd_s0>; vqmmc-supply = <&vccio_sd_s0>; status = "okay"; }; @@ -884,6 +912,7 @@ }; &u2phy2_host { + phy-supply = <&vdd_4g_3v3>; status = "okay"; }; diff --git a/src/arm64/rockchip/rk3588-orangepi-5-plus.dts b/src/arm64/rockchip/rk3588-orangepi-5-plus.dts index 3e660ff6cd5..1a604429fb2 100644 --- a/src/arm64/rockchip/rk3588-orangepi-5-plus.dts +++ b/src/arm64/rockchip/rk3588-orangepi-5-plus.dts @@ -444,7 +444,6 @@ &sdmmc { bus-width = <4>; cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; disable-wp; max-frequency = <150000000>; no-sdio; @@ -486,6 +485,7 @@ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; spi-max-frequency = <1000000>; + system-power-controller; vcc1-supply = <&vcc5v0_sys>; vcc2-supply = <&vcc5v0_sys>; @@ -507,7 +507,7 @@ #gpio-cells = <2>; rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; + pins = "gpio_pwrctrl1"; function = "pin_fun0"; }; diff --git a/src/arm64/rockchip/rk3588-quartzpro64.dts b/src/arm64/rockchip/rk3588-quartzpro64.dts index 87a0abf95f7..22bbfbe729c 100644 --- a/src/arm64/rockchip/rk3588-quartzpro64.dts +++ b/src/arm64/rockchip/rk3588-quartzpro64.dts @@ -429,7 +429,6 @@ &sdmmc { bus-width = <4>; cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; disable-wp; max-frequency = <150000000>; no-sdio; @@ -457,6 +456,7 @@ <&rk806_dvs2_null>, <&rk806_dvs3_null>; pinctrl-names = "default"; spi-max-frequency = <1000000>; + system-power-controller; vcc1-supply = <&vcc4v0_sys>; vcc2-supply = <&vcc4v0_sys>; diff --git a/src/arm64/rockchip/rk3588-rock-5b.dts b/src/arm64/rockchip/rk3588-rock-5b.dts index a0e303c3a1d..1fe8b2a0ed7 100644 --- a/src/arm64/rockchip/rk3588-rock-5b.dts +++ b/src/arm64/rockchip/rk3588-rock-5b.dts @@ -58,6 +58,13 @@ #cooling-cells = <2>; }; + rfkill { + compatible = "rfkill-gpio"; + label = "rfkill-pcie-wlan"; + radio-type = "wlan"; + shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + }; + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -371,7 +378,6 @@ bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; disable-wp; sd-uhs-sdr104; vmmc-supply = <&vcc_3v3_s3>; diff --git a/src/arm64/rockchip/rk3588-tiger-haikou.dts b/src/arm64/rockchip/rk3588-tiger-haikou.dts new file mode 100644 index 00000000000..d672198c6b6 --- /dev/null +++ b/src/arm64/rockchip/rk3588-tiger-haikou.dts @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH + */ + +/dts-v1/; +#include +#include "rk3588-tiger.dtsi" + +/ { + model = "Theobroma Systems RK3588-Q7 SoM on Haikou devkit"; + compatible = "tsd,rk3588-tiger-haikou", "tsd,rk3588-tiger", "rockchip,rk3588"; + + aliases { + ethernet0 = &gmac0; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + dc_12v: dc-12v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&haikou_keys_pin>; + + button-batlow-n { + label = "BATLOW#"; + linux,code = ; + gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>; + }; + + button-slp-btn-n { + label = "SLP_BTN#"; + linux,code = ; + gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + }; + + button-wake-n { + label = "WAKE#"; + linux,code = ; + gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + switch-lid-btn-n { + label = "LID_BTN#"; + linux,code = ; + linux,input-type = ; + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + }; + }; + + i2s3-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Haikou,I2S-codec"; + simple-audio-card,mclk-fs = <512>; + simple-audio-card,frame-master = <&sgtl5000_codec>; + simple-audio-card,bitclock-master = <&sgtl5000_codec>; + + sgtl5000_codec: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s3_2ch>; + }; + }; + + sgtl5000_clk: sgtl5000-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + vcc3v3_baseboard: vcc3v3-baseboard-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_baseboard"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_low_noise: vcc3v3-low-noise-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_low_noise"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_baseboard: vcc5v0-baseboard-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_baseboard"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vddd_audio_1v6: vddd-audio-1v6-regulator { + compatible = "regulator-fixed"; + regulator-name = "vddd_audio_1v6"; + regulator-boot-on; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1600000>; + vin-supply = <&vcc5v0_usb>; + }; +}; + +&combphy2_psu { + status = "okay"; +}; + +&gmac0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + eeprom@50 { + reg = <0x50>; + compatible = "atmel,24c01"; + pagesize = <8>; + size = <128>; + vcc-supply = <&vcc3v3_baseboard>; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&sgtl5000_clk>; + #sound-dai-cells = <0>; + VDDA-supply = <&vcc3v3_low_noise>; + VDDIO-supply = <&vcc3v3_baseboard>; + VDDD-supply = <&vddd_audio_1v6>; + }; +}; + +&i2c8 { + status = "okay"; +}; + +&i2s3_2ch { + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + vpcie3v3-supply = <&vcc3v3_baseboard>; + status = "okay"; +}; + +&pinctrl { + haikou { + haikou_keys_pin: haikou-keys-pin { + rockchip,pins = + /* BATLOW# */ + <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, + /* SLP_BTN# */ + <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>, + /* WAKE# */ + <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>, + /* LID_BTN */ + <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sdmmc { + /* while the same pin, sdmmc_det does not detect card changes */ + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_cmd &sdmmc_clk>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_baseboard>; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m2_xfer>; + status = "okay"; +}; + +&uart5 { + rts-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/* host0 on Q7_USB_P2, lower usb3 port */ +&usb_host0_ehci { + status = "okay"; +}; + +/* host0 on Q7_USB_P2, lower usb3 port */ +&usb_host0_ohci { + status = "okay"; +}; + +/* host1 on Q7_USB_P3, usb2 port */ +&usb_host1_ehci { + status = "okay"; +}; + +/* host1 on Q7_USB_P3, usb2 port */ +&usb_host1_ohci { + status = "okay"; +}; + +/* host2 on Q7_USB_P2, lower usb3 port */ +&usb_host2_xhci { + status = "okay"; +}; diff --git a/src/arm64/rockchip/rk3588-tiger.dtsi b/src/arm64/rockchip/rk3588-tiger.dtsi new file mode 100644 index 00000000000..1eb2543a5fd --- /dev/null +++ b/src/arm64/rockchip/rk3588-tiger.dtsi @@ -0,0 +1,690 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH + */ + +#include +#include +#include +#include "rk3588.dtsi" + +/ { + compatible = "tsd,rk3588-tiger", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + rtc0 = &rtc_twi; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-0 = <&emmc_reset>; + pinctrl-names = "default"; + reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&module_led_pin>; + + /* Named LED1 on the board */ + led-1 { + gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + linux,default-trigger = "heartbeat"; + color = ; + }; + }; + + /* + * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE + * clock generator. + * The clock output is gated via the OE pin on the clock generator. + * This is modeled as a fixed-clock plus a gpio-gate-clock. + */ + pcie_refclk_gen: pcie-refclk-gen-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000000>; + }; + + pcie_refclk: pcie-refclk-clock { + compatible = "gpio-gate-clock"; + clocks = <&pcie_refclk_gen>; + #clock-cells = <0>; + enable-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; /* PCIE30X4_CLKREQN_M1_L */ + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v2_s3: vcc-1v2-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v2_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_baseboard>; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii"; + phy-supply = <&vcc_1v2_s3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_rx_bus2 + &gmac0_tx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus + ð0_pins + ð_reset>; + tx_delay = <0x10>; + rx_delay = <0x10>; + snps,reset-gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 100000>; +}; + +&i2c1 { + pinctrl-0 = <&i2c1m0_xfer>; +}; + +&i2c1m0_xfer { + rockchip,pins = + /* i2c1_scl_m0 */ + <0 RK_PB5 9 &pcfg_pull_none_drv_level_0>, + /* i2c1_sda_m0 */ + <0 RK_PB6 9 &pcfg_pull_none_drv_level_0>; +}; + +&i2c2 { + pinctrl-0 = <&i2c2m3_xfer>; + status = "okay"; +}; + +&i2c2m3_xfer { + rockchip,pins = + /* i2c2_scl_m3 */ + <1 RK_PC5 9 &pcfg_pull_none_drv_level_0>, + /* i2c2_sda_m3 */ + <1 RK_PC4 9 &pcfg_pull_none_drv_level_0>; +}; + +&i2c3 { + pinctrl-0 = <&i2c3m0_xfer>; +}; + +&i2c4 { + pinctrl-0 = <&i2c4m4_xfer>; + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c5 { + pinctrl-0 = <&i2c5m1_xfer>; +}; + +&i2c5m1_xfer { + rockchip,pins = + /* i2c5_scl_m1 */ + <4 RK_PB6 9 &pcfg_pull_none_drv_level_0>, + /* i2c5_sda_m1 */ + <4 RK_PB7 9 &pcfg_pull_none_drv_level_0>; +}; + +&i2c6 { + /* + * Mule-ATtiny can handle up to Fast mode Plus (1MHz) on I2C bus, + * but SOC can handle only up to (400kHz). + */ + clock-frequency = <400000>; + status = "okay"; + + fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + }; + + rtc_twi: rtc@6f { + compatible = "isil,isl1208"; + reg = <0x6f>; + }; +}; + +&i2c6m0_xfer { + rockchip,pins = + /* i2c6_scl_m0 */ + <0 RK_PD0 9 &pcfg_pull_none_drv_level_0>, + /* i2c6_sda_m0 */ + <0 RK_PC7 9 &pcfg_pull_none_drv_level_0>; +}; + +&i2c7 { + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c7m0_xfer { + rockchip,pins = + /* i2c7_scl_m0 */ + <1 RK_PD0 9 &pcfg_pull_none_drv_level_0>, + /* i2c7_sda_m0 */ + <1 RK_PD1 9 &pcfg_pull_none_drv_level_0>; +}; + +&i2c8 { + pinctrl-0 = <&i2c8m2_xfer>; +}; + +&mdio0 { + rgmii_phy: ethernet-phy@6 { + /* KSZ9031 or KSZ9131 */ + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x6>; + clocks = <&cru REFCLKO25M_ETH0_OUT>; + }; +}; + +&pcie3x4 { + /* + * The board has a gpio-controlled "pcie_refclk" generator, + * so add it to the list of clocks. + */ + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>, + <&pcie_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe", + "ref"; + reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; +}; + +&pinctrl { + emmc { + emmc_reset: emmc-reset { + rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ethernet { + eth_reset: eth-reset { + rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + module_led_pin: module-led-pin { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + mmc-pwrseq = <&emmc_pwrseq>; + no-sdio; + no-sd; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_data_strobe>; + supports-cqe; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vcc_1v8_s3>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <150000000>; + vqmmc-supply = <&vccio_sd_s0>; +}; + +&spi0 { + pinctrl-0 = <&spi0m1_cs0 &spi0m1_cs1 &spi0m3_pins>; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vcc_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-name = "vcca_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-name = "vdda_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-name = "vcca_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdda_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdda_0v75_s0: nldo-reg3 { + regulator-name = "vdda_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-name = "vdda_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +/* Mule-ATtiny UPDI */ +&uart4 { + pinctrl-0 = <&uart4m2_xfer>; + status = "okay"; +}; diff --git a/src/arm64/rockchip/rk3588-toybrick-x0.dts b/src/arm64/rockchip/rk3588-toybrick-x0.dts new file mode 100644 index 00000000000..9090c5c99f2 --- /dev/null +++ b/src/arm64/rockchip/rk3588-toybrick-x0.dts @@ -0,0 +1,688 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include "rk3588.dtsi" + +/ { + model = "Rockchip Toybrick TB-RK3588X Board"; + compatible = "rockchip,rk3588-toybrick-x0", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-vol-up { + label = "Volume Up"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + + button-vol-down { + label = "Volume Down"; + linux,code = ; + press-threshold-microvolt = <417000>; + }; + + button-menu { + label = "Menu"; + linux,code = ; + press-threshold-microvolt = <890000>; + }; + + button-escape { + label = "Escape"; + linux,code = ; + press-threshold-microvolt = <1235000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&vcc12v_dcin>; + pwms = <&pwm2 0 25000 0>; + }; + + pcie20_avdd0v85: pcie20-avdd0v85-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-rxid"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + pinctrl-names = "default"; + rx_delay = <0x00>; + tx_delay = <0x43>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&mdio0 { + rgmii_phy: ethernet-phy@1 { + /* RTL8211F */ + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8211f_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + rtl8211f { + rtl8211f_rst: rtl8211f-rst { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-init-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name = "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-name = "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-name = "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-name = "vdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/src/arm64/rockchip/rk3588s-indiedroid-nova.dts b/src/arm64/rockchip/rk3588s-indiedroid-nova.dts index 3c227888685..ce8119cbb82 100644 --- a/src/arm64/rockchip/rk3588s-indiedroid-nova.dts +++ b/src/arm64/rockchip/rk3588s-indiedroid-nova.dts @@ -141,6 +141,10 @@ status = "okay"; }; +&combphy2_psu { + status = "okay"; +}; + &cpu_l0 { cpu-supply = <&vdd_cpu_lit_s0>; }; @@ -842,3 +846,7 @@ &usb_host1_ohci { status = "okay"; }; + +&usb_host2_xhci { + status = "okay"; +}; diff --git a/src/arm64/rockchip/rk3588s-nanopi-r6c.dts b/src/arm64/rockchip/rk3588s-nanopi-r6c.dts new file mode 100644 index 00000000000..497bbb57071 --- /dev/null +++ b/src/arm64/rockchip/rk3588s-nanopi-r6c.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3588s-nanopi-r6s.dts" + +/ { + model = "FriendlyElec NanoPi R6C"; + compatible = "friendlyarm,nanopi-r6c", "rockchip,rk3588s"; +}; + +&lan2_led { + label = "user_led"; +}; diff --git a/src/arm64/rockchip/rk3588s-nanopi-r6s.dts b/src/arm64/rockchip/rk3588s-nanopi-r6s.dts new file mode 100644 index 00000000000..4fa644ae510 --- /dev/null +++ b/src/arm64/rockchip/rk3588s-nanopi-r6s.dts @@ -0,0 +1,764 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include "rk3588s.dtsi" + +/ { + model = "FriendlyElec NanoPi R6S"; + compatible = "friendlyarm,nanopi-r6s", "rockchip,rk3588s"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdmmc; + mmc1 = &sdhci; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-maskrom { + label = "Maskrom"; + linux,code = ; + press-threshold-microvolt = <1800>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key1_pin>; + + button-user { + label = "User"; + linux,code = ; + gpios = <&gpio1 RK_PC0 GPIO_ACTIVE_LOW>; + debounce-interval = <50>; + }; + }; + + leds { + compatible = "gpio-leds"; + + sys_led: led-0 { + label = "sys_led"; + gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&sys_led_pin>; + }; + + wan_led: led-1 { + label = "wan_led"; + gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wan_led_pin>; + }; + + lan1_led: led-2 { + label = "lan1_led"; + gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lan1_led_pin>; + }; + + lan2_led: led-3 { + label = "lan2_led"; + gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lan2_led_pin>; + }; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3_s0: vcc-3v3-s0-regulator { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s0"; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sd_s0_pwr>; + regulator-name = "vcc_3v3_sd_s0"; + regulator-boot-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_3v3_pcie20: vcc3v3-pcie20-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_pcie20"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb_otg0: vcc5v0-usb-otg0-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + regulator-name = "vcc5v0_usb_otg0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_host_20: vcc5v0-host-20-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host20_en>; + regulator-name = "vcc5v0_host_20"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-rxid"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + pinctrl-names = "default"; + tx_delay = <0x42>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + regulator-boot-on; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + clock-frequency = <200000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8211f_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_pcie20>; + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_pcie20>; + status = "okay"; +}; + +&pinctrl { + gpio-key { + key1_pin: key1-pin { + rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-leds { + sys_led_pin: sys-led-pin { + rockchip,pins = + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan1_led_pin: lan1-led-pin { + rockchip,pins = + <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan2_led_pin: lan2-led-pin { + rockchip,pins = + <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sd_s0_pwr: sd-s0-pwr { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + typec5v_pwren: typec5v-pwren { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_host20_en: vcc5v0-host20-en { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtl8211f { + rtl8211f_rst: rtl8211f-rst { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + mmc-hs200-1_8v; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + no-mmc; + no-sdio; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_sd_s0>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; + + pmic@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "avcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + avdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "avdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "avdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host_20>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; diff --git a/src/arm64/rockchip/rk3588s-rock-5a.dts b/src/arm64/rockchip/rk3588s-rock-5a.dts index 2002fd0221f..00afb90d4eb 100644 --- a/src/arm64/rockchip/rk3588s-rock-5a.dts +++ b/src/arm64/rockchip/rk3588s-rock-5a.dts @@ -366,7 +366,6 @@ bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; disable-wp; max-frequency = <150000000>; no-sdio; diff --git a/src/arm64/rockchip/rk3588s.dtsi b/src/arm64/rockchip/rk3588s.dtsi index 36b1b7acfe6..87b83c87bd5 100644 --- a/src/arm64/rockchip/rk3588s.dtsi +++ b/src/arm64/rockchip/rk3588s.dtsi @@ -519,6 +519,7 @@ vo1_grf: syscon@fd5a8000 { compatible = "rockchip,rk3588-vo-grf", "syscon"; reg = <0x0 0xfd5a8000 0x0 0x100>; + clocks = <&cru PCLK_VO1GRF>; }; php_grf: syscon@fd5b0000 { @@ -586,6 +587,11 @@ }; }; + hdptxphy0_grf: syscon@fd5e0000 { + compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; + reg = <0x0 0xfd5e0000 0x0 0x100>; + }; + ioc: syscon@fd5f0000 { compatible = "rockchip,rk3588-ioc", "syscon"; reg = <0x0 0xfd5f0000 0x0 0x10000>; @@ -1704,7 +1710,6 @@ dmas = <&dmac1 0>, <&dmac1 1>; dma-names = "tx", "rx"; power-domains = <&power RK3588_PD_AUDIO>; - rockchip,trcm-sync-tx-only; pinctrl-names = "default"; pinctrl-0 = <&i2s2m1_lrck &i2s2m1_sclk @@ -1725,7 +1730,6 @@ dmas = <&dmac1 2>, <&dmac1 3>; dma-names = "tx", "rx"; power-domains = <&power RK3588_PD_AUDIO>; - rockchip,trcm-sync-tx-only; pinctrl-names = "default"; pinctrl-0 = <&i2s3_lrck &i2s3_sclk @@ -2360,6 +2364,22 @@ #dma-cells = <1>; }; + hdptxphy_hdmi0: phy@fed60000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0xfed60000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; + clock-names = "ref", "apb"; + #phy-cells = <0>; + resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, + <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, + <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, + <&cru SRST_HDPTX0_LCPLL>; + reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", + "lcpll"; + rockchip,grf = <&hdptxphy0_grf>; + status = "disabled"; + }; + combphy0_ps: phy@fee00000 { compatible = "rockchip,rk3588-naneng-combphy"; reg = <0x0 0xfee00000 0x0 0x100>; diff --git a/src/arm64/st/stm32mp251.dtsi b/src/arm64/st/stm32mp251.dtsi index 96859d098ef..5dd4f3580a6 100644 --- a/src/arm64/st/stm32mp251.dtsi +++ b/src/arm64/st/stm32mp251.dtsi @@ -52,6 +52,18 @@ compatible = "fixed-clock"; clock-frequency = <200000000>; }; + + ck_icn_p_vdec: ck-icn-p-vdec { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + + ck_icn_p_venc: ck-icn-p-venc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; }; firmware { diff --git a/src/arm64/st/stm32mp255.dtsi b/src/arm64/st/stm32mp255.dtsi index e6fa596211f..17f197c5b22 100644 --- a/src/arm64/st/stm32mp255.dtsi +++ b/src/arm64/st/stm32mp255.dtsi @@ -6,4 +6,21 @@ #include "stm32mp253.dtsi" / { + soc@0 { + rifsc: rifsc-bus@42080000 { + vdec: vdec@480d0000 { + compatible = "st,stm32mp25-vdec"; + reg = <0x480d0000 0x3c8>; + interrupts = ; + clocks = <&ck_icn_p_vdec>; + }; + + venc: venc@480e0000 { + compatible = "st,stm32mp25-venc"; + reg = <0x480e0000 0x800>; + interrupts = ; + clocks = <&ck_icn_ls_mcu>; + }; + }; + }; }; diff --git a/src/arm64/tesla/fsd.dtsi b/src/arm64/tesla/fsd.dtsi index aaffb50b8b6..047a83cee60 100644 --- a/src/arm64/tesla/fsd.dtsi +++ b/src/arm64/tesla/fsd.dtsi @@ -601,6 +601,7 @@ clocks = <&clock_peric PERIC_PCLK_UART0>, <&clock_peric PERIC_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <64>; status = "disabled"; }; @@ -613,6 +614,7 @@ clocks = <&clock_peric PERIC_PCLK_UART1>, <&clock_peric PERIC_SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <64>; status = "disabled"; }; diff --git a/src/arm64/ti/k3-am62-lp-sk.dts b/src/arm64/ti/k3-am62-lp-sk.dts index 5e6feb8cd12..c4149059a4c 100644 --- a/src/arm64/ti/k3-am62-lp-sk.dts +++ b/src/arm64/ti/k3-am62-lp-sk.dts @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * AM62x LP SK: https://www.ti.com/tool/SK-AM62-LP * - * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am62-main.dtsi b/src/arm64/ti/k3-am62-main.dtsi index 464b7565d08..e9cffca073e 100644 --- a/src/arm64/ti/k3-am62-main.dtsi +++ b/src/arm64/ti/k3-am62-main.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM625 SoC Family Main Domain peripherals * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_main { @@ -42,9 +42,8 @@ }; }; - main_conf: syscon@100000 { - compatible = "syscon", "simple-mfd"; - reg = <0x00 0x00100000 0x00 0x20000>; + main_conf: bus@100000 { + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x00 0x00100000 0x20000>; @@ -559,10 +558,9 @@ clock-names = "clk_ahb", "clk_xin"; assigned-clocks = <&k3_clks 57 6>; assigned-clock-parents = <&k3_clks 57 8>; + bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; - ti,trm-icp = <0x2>; - bus-width = <8>; ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; @@ -580,7 +578,8 @@ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x8>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0x0>; @@ -592,8 +591,6 @@ ti,itap-del-sel-sd-hs = <0x1>; ti,itap-del-sel-sdr12 = <0xa>; ti,itap-del-sel-sdr25 = <0x1>; - ti,clkbuf-sel = <0x7>; - bus-width = <4>; status = "disabled"; }; @@ -604,7 +601,8 @@ power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x8>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0x0>; @@ -616,7 +614,6 @@ ti,itap-del-sel-sd-hs = <0xa>; ti,itap-del-sel-sdr12 = <0xa>; ti,itap-del-sel-sdr25 = <0x1>; - ti,clkbuf-sel = <0x7>; status = "disabled"; }; @@ -640,6 +637,8 @@ interrupt-names = "host", "peripheral"; maximum-speed = "high-speed"; dr_mode = "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; }; }; @@ -663,6 +662,8 @@ interrupt-names = "host", "peripheral"; maximum-speed = "high-speed"; dr_mode = "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; }; }; @@ -779,9 +780,10 @@ <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ - <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */ + <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ + <0x00 0x30201000 0x00 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 186 6>, <&dss_vp1_clk>, diff --git a/src/arm64/ti/k3-am62-mcu.dtsi b/src/arm64/ti/k3-am62-mcu.dtsi index 0e0b234581c..e66d486ef1f 100644 --- a/src/arm64/ti/k3-am62-mcu.dtsi +++ b/src/arm64/ti/k3-am62-mcu.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM625 SoC Family MCU Domain peripherals * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu { diff --git a/src/arm64/ti/k3-am62-phycore-som.dtsi b/src/arm64/ti/k3-am62-phycore-som.dtsi index aa43e7407ee..43488cc8bcb 100644 --- a/src/arm64/ti/k3-am62-phycore-som.dtsi +++ b/src/arm64/ti/k3-am62-phycore-som.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2022 - 2023 PHYTEC Messtechnik GmbH + * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH * Author: Wadim Egorov * * Product homepage: @@ -317,7 +317,6 @@ &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&main_mmc0_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; non-removable; status = "okay"; diff --git a/src/arm64/ti/k3-am62-thermal.dtsi b/src/arm64/ti/k3-am62-thermal.dtsi index a358757e26f..12ba833002a 100644 --- a/src/arm64/ti/k3-am62-thermal.dtsi +++ b/src/arm64/ti/k3-am62-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include diff --git a/src/arm64/ti/k3-am62-verdin-dahlia.dtsi b/src/arm64/ti/k3-am62-verdin-dahlia.dtsi index bf6d27e70bc..6c4cec8728e 100644 --- a/src/arm64/ti/k3-am62-verdin-dahlia.dtsi +++ b/src/arm64/ti/k3-am62-verdin-dahlia.dtsi @@ -185,7 +185,6 @@ /* Verdin SD_1 */ &sdhci1 { - ti,driver-strength-ohm = <33>; status = "okay"; }; diff --git a/src/arm64/ti/k3-am62-verdin-dev.dtsi b/src/arm64/ti/k3-am62-verdin-dev.dtsi index 680071688dc..be62648e781 100644 --- a/src/arm64/ti/k3-am62-verdin-dev.dtsi +++ b/src/arm64/ti/k3-am62-verdin-dev.dtsi @@ -206,7 +206,6 @@ /* Verdin SD_1 */ &sdhci1 { - ti,driver-strength-ohm = <33>; status = "okay"; }; diff --git a/src/arm64/ti/k3-am62-verdin-mallow.dtsi b/src/arm64/ti/k3-am62-verdin-mallow.dtsi index 17b93534f65..77b1beb638a 100644 --- a/src/arm64/ti/k3-am62-verdin-mallow.dtsi +++ b/src/arm64/ti/k3-am62-verdin-mallow.dtsi @@ -127,6 +127,16 @@ <&pinctrl_qspi1_cs2_gpio>; cs-gpios = <0>, <&main_gpio0 12 GPIO_ACTIVE_LOW>; status = "okay"; + + tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_dqs_gpio>; + interrupt-parent = <&main_gpio1>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <18500000>; + }; }; /* Verdin UART_3 */ diff --git a/src/arm64/ti/k3-am62-verdin-wifi.dtsi b/src/arm64/ti/k3-am62-verdin-wifi.dtsi index a6808b10c7b..4768ef42c4f 100644 --- a/src/arm64/ti/k3-am62-verdin-wifi.dtsi +++ b/src/arm64/ti/k3-am62-verdin-wifi.dtsi @@ -26,7 +26,6 @@ mmc-pwrseq = <&wifi_pwrseq>; non-removable; ti,fails-without-test-cd; - ti,driver-strength-ohm = <50>; vmmc-supply = <®_3v3>; status = "okay"; }; diff --git a/src/arm64/ti/k3-am62-verdin.dtsi b/src/arm64/ti/k3-am62-verdin.dtsi index 6a06724b6d1..e8d8857ad51 100644 --- a/src/arm64/ti/k3-am62-verdin.dtsi +++ b/src/arm64/ti/k3-am62-verdin.dtsi @@ -42,6 +42,22 @@ usb1 = &usb1; }; + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_id>; + id-gpios = <&main_gpio1 19 GPIO_ACTIVE_HIGH>; + label = "USB_1"; + self-powered; + vbus-supply = <®_usb0_vbus>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb0_ep>; + }; + }; + }; + verdin_gpio_keys: gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -151,6 +167,18 @@ vin-supply = <®_sd_3v3_1v8>; }; + reg_usb0_vbus: regulator-usb0-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_en>; + enable-active-high; + /* Verdin USB_1_EN (SODIMM 155) */ + gpio = <&main_gpio1 50 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "USB_1_EN"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -436,6 +464,13 @@ >; }; + /* Verdin USB_1_EN */ + pinctrl_usb0_en: main-gpio1-50-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0254, PIN_INPUT, 7) /* (C20) USB0_DRVVBUS.GPIO1_50 */ /* SODIMM 155 */ + >; + }; + /* On-module I2C - PMIC_I2C */ pinctrl_i2c0: main-i2c0-default-pins { pinctrl-single,pins = < @@ -660,13 +695,6 @@ >; }; - /* Verdin USB_1 */ - pinctrl_usb0: main-usb0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0254, PIN_OUTPUT, 0) /* (C20) USB0_DRVVBUS */ /* SODIMM 155 */ - >; - }; - /* Verdin USB_2 */ pinctrl_usb1: main-usb1-default-pins { pinctrl-single,pins = < @@ -1013,7 +1041,7 @@ "", "", "SODIMM_17", - "", /* 50 */ + "SODIMM_155", /* 50 */ "", "", "", @@ -1118,7 +1146,7 @@ regulator-always-on; regulator-boot-on; regulator-max-microvolt = <850000>; - regulator-min-microvolt = <850000>; + regulator-min-microvolt = <750000>; regulator-name = "+VDD_CORE (PMIC BUCK1)"; }; @@ -1407,7 +1435,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0>; non-removable; - ti,driver-strength-ohm = <50>; status = "okay"; }; @@ -1416,7 +1443,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1>; disable-wp; - ti,driver-strength-ohm = <50>; vmmc-supply = <®_sdhc1_vmmc>; vqmmc-supply = <®_sdhc1_vqmmc>; status = "disabled"; @@ -1428,11 +1454,16 @@ status = "disabled"; }; -/* TODO: role swich using ID pin */ &usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb0_id>; + adp-disable; + usb-role-switch; status = "disabled"; + + port { + usb0_ep: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; + }; }; /* Verdin USB_2 */ diff --git a/src/arm64/ti/k3-am62-wakeup.dtsi b/src/arm64/ti/k3-am62-wakeup.dtsi index fef76f52a52..23ce1bfda8d 100644 --- a/src/arm64/ti/k3-am62-wakeup.dtsi +++ b/src/arm64/ti/k3-am62-wakeup.dtsi @@ -1,10 +1,12 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM625 SoC Family Wakeup Domain peripherals * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ +#include + &cbass_wakeup { wkup_conf: syscon@43000000 { bootph-all; @@ -21,14 +23,34 @@ }; }; - wkup_uart0: serial@2b300000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x2b300000 0x00 0x100>; - interrupts = ; + target-module@2b300050 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x00 0x2b300050 0x00 0x4>, + <0x00 0x2b300054 0x00 0x4>, + <0x00 0x2b300058 0x00 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + ti,no-reset-on-init; power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 114 0>; - clock-names = "fclk"; - status = "disabled"; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x2b300000 0x100000>; + + wkup_uart0: serial@0 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x0 0x100>; + interrupts = ; + status = "disabled"; + }; }; wkup_i2c0: i2c@2b200000 { diff --git a/src/arm64/ti/k3-am62.dtsi b/src/arm64/ti/k3-am62.dtsi index f1e15206e1c..f0781f2bea2 100644 --- a/src/arm64/ti/k3-am62.dtsi +++ b/src/arm64/ti/k3-am62.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM62 SoC Family * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include diff --git a/src/arm64/ti/k3-am625-beagleplay-csi2-ov5640.dtso b/src/arm64/ti/k3-am625-beagleplay-csi2-ov5640.dtso index 5e80ca7033b..3b4643b7d19 100644 --- a/src/arm64/ti/k3-am625-beagleplay-csi2-ov5640.dtso +++ b/src/arm64/ti/k3-am625-beagleplay-csi2-ov5640.dtso @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * ALINX AN5641 & Digilent PCam 5C - OV5640 camera module - * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am625-beagleplay-csi2-tevi-ov5640.dtso b/src/arm64/ti/k3-am625-beagleplay-csi2-tevi-ov5640.dtso index 5e1cbbc27c8..81a2763d43c 100644 --- a/src/arm64/ti/k3-am625-beagleplay-csi2-tevi-ov5640.dtso +++ b/src/arm64/ti/k3-am625-beagleplay-csi2-tevi-ov5640.dtso @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Technexion TEVI-OV5640-*-RPI - OV5640 camera module - * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am625-beagleplay.dts b/src/arm64/ti/k3-am625-beagleplay.dts index eadbdd9ffe3..a34e0df2ab8 100644 --- a/src/arm64/ti/k3-am625-beagleplay.dts +++ b/src/arm64/ti/k3-am625-beagleplay.dts @@ -1,9 +1,9 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * https://beagleplay.org/ * - * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ - * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Robert Nelson, BeagleBoard.org Foundation */ /dts-v1/; @@ -29,7 +29,6 @@ i2c3 = &main_i2c3; i2c4 = &wkup_i2c0; i2c5 = &mcu_i2c0; - mdio-gpio0 = &mdio0; mmc0 = &sdhci0; mmc1 = &sdhci1; mmc2 = &sdhci2; @@ -231,27 +230,6 @@ }; }; - /* Workaround for errata i2329 - just use mdio bitbang */ - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&mdio0_pins_default>; - gpios = <&main_gpio0 86 GPIO_ACTIVE_HIGH>, /* MDC */ - <&main_gpio0 85 GPIO_ACTIVE_HIGH>; /* MDIO */ - #address-cells = <1>; - #size-cells = <0>; - - cpsw3g_phy0: ethernet-phy@0 { - reg = <0>; - }; - - cpsw3g_phy1: ethernet-phy@1 { - reg = <1>; - reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>; - reset-assert-us = <25>; - reset-deassert-us = <60000>; /* T2 */ - }; - }; }; &main_pmx0 { @@ -312,8 +290,8 @@ mdio0_pins_default: mdio0-default-pins { pinctrl-single,pins = < - AM62X_IOPAD(0x0160, PIN_OUTPUT, 7) /* (AD24) MDIO0_MDC.GPIO0_86 */ - AM62X_IOPAD(0x015c, PIN_INPUT, 7) /* (AB22) MDIO0_MDIO.GPIO0_85 */ + AM62X_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ + AM62X_IOPAD(0x015c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ >; }; @@ -573,11 +551,13 @@ }; &usbss0 { + bootph-all; ti,vbus-divider; status = "okay"; }; &usb0 { + bootph-all; dr_mode = "peripheral"; }; @@ -611,8 +591,20 @@ }; &cpsw3g_mdio { - /* Workaround for errata i2329 - Use mdio bitbang */ - status = "disabled"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_pins_default>; + + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + }; + + cpsw3g_phy1: ethernet-phy@1 { + reg = <1>; + reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <25>; + reset-deassert-us = <60000>; /* T2 */ + }; }; &main_gpio0 { @@ -827,7 +819,6 @@ bootph-all; pinctrl-names = "default"; pinctrl-0 = <&emmc_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; status = "okay"; }; @@ -840,7 +831,6 @@ vmmc-supply = <&vdd_3v3_sd>; vqmmc-supply = <&vdd_sd_dv>; - ti,driver-strength-ohm = <50>; disable-wp; cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>; cd-debounce-delay-ms = <100>; @@ -852,12 +842,10 @@ vmmc-supply = <&wlan_en>; pinctrl-names = "default"; pinctrl-0 = <&wifi_pins_default>, <&wifi_32k_clk>; - bus-width = <4>; non-removable; ti,fails-without-test-cd; cap-power-off-card; keep-power-in-suspend; - ti,driver-strength-ohm = <50>; assigned-clocks = <&k3_clks 157 158>; assigned-clock-parents = <&k3_clks 157 160>; #address-cells = <1>; diff --git a/src/arm64/ti/k3-am625-phyboard-lyra-rdk.dts b/src/arm64/ti/k3-am625-phyboard-lyra-rdk.dts index 4bc0134c987..a83a9049785 100644 --- a/src/arm64/ti/k3-am625-phyboard-lyra-rdk.dts +++ b/src/arm64/ti/k3-am625-phyboard-lyra-rdk.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2022 - 2023 PHYTEC Messtechnik GmbH + * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH * Author: Wadim Egorov * * Product homepage: @@ -222,6 +222,7 @@ cpsw3g_phy3: ethernet-phy@3 { compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; reg = <3>; + ti,clk-output-sel = ; ti,rx-internal-delay = ; ti,fifo-depth = ; }; @@ -333,7 +334,6 @@ vqmmc-supply = <&vddshv5_sdio>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; no-1-8-v; status = "okay"; diff --git a/src/arm64/ti/k3-am625-sk.dts b/src/arm64/ti/k3-am625-sk.dts index b18092497c9..ae81ebb39d0 100644 --- a/src/arm64/ti/k3-am625-sk.dts +++ b/src/arm64/ti/k3-am625-sk.dts @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * AM625 SK: https://www.ti.com/lit/zip/sprr448 * - * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am625.dtsi b/src/arm64/ti/k3-am625.dtsi index 4193c2b3eed..4014add6320 100644 --- a/src/arm64/ti/k3-am625.dtsi +++ b/src/arm64/ti/k3-am625.dtsi @@ -1,10 +1,10 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM625 SoC family in Quad core configuration * * TRM: https://www.ti.com/lit/pdf/spruiv7 * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am62a-main.dtsi b/src/arm64/ti/k3-am62a-main.dtsi index f0b8c9ab145..aa1e057082f 100644 --- a/src/arm64/ti/k3-am62a-main.dtsi +++ b/src/arm64/ti/k3-am62a-main.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM62A SoC Family Main Domain peripherals * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_main { @@ -42,9 +42,8 @@ }; }; - main_conf: syscon@100000 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00 0x00100000 0x00 0x20000>; + main_conf: bus@100000 { + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00 0x00 0x00100000 0x20000>; @@ -536,6 +535,24 @@ status = "disabled"; }; + sdhci0: mmc@fa10000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; + interrupts = ; + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; + clock-names = "clk_ahb", "clk_xin"; + assigned-clocks = <&k3_clks 57 6>; + assigned-clock-parents = <&k3_clks 57 8>; + bus-width = <8>; + mmc-hs200-1_8v; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; + ti,otap-del-sel-hs200 = <0x6>; + status = "disabled"; + }; + sdhci1: mmc@fa00000 { compatible = "ti,am62-sdhci"; reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; @@ -543,7 +560,8 @@ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; @@ -555,8 +573,30 @@ ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; - ti,clkbuf-sel = <0x7>; + no-1-8-v; + status = "disabled"; + }; + + sdhci2: mmc@fa20000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0xfa20000 0x00 0x260>, <0x00 0xfa28000 0x00 0x134>; + interrupts = ; + power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; + clock-names = "clk_ahb", "clk_xin"; bus-width = <4>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; no-1-8-v; status = "disabled"; }; @@ -985,4 +1025,30 @@ power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; + + dss: dss@30200000 { + compatible = "ti,am62a7-dss"; + reg = <0x00 0x30200000 0x00 0x1000>, /* common */ + <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ + <0x00 0x30206000 0x00 0x1000>, /* vid */ + <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ + <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ + <0x00 0x3020a000 0x00 0x1000>, /* vp1: Tied OFF in the SoC */ + <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ + <0x00 0x30201000 0x00 0x1000>; /* common1 */ + reg-names = "common", "vidl1", "vid", + "ovr1", "ovr2", "vp1", "vp2", "common1"; + power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 186 6>, + <&k3_clks 186 0>, + <&k3_clks 186 2>; + clock-names = "fck", "vp1", "vp2"; + interrupts = ; + status = "disabled"; + + dss_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; diff --git a/src/arm64/ti/k3-am62a-mcu.dtsi b/src/arm64/ti/k3-am62a-mcu.dtsi index a6d16a94088..8c36e56f413 100644 --- a/src/arm64/ti/k3-am62a-mcu.dtsi +++ b/src/arm64/ti/k3-am62a-mcu.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM625 SoC Family MCU Domain peripherals * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu { diff --git a/src/arm64/ti/k3-am62a-thermal.dtsi b/src/arm64/ti/k3-am62a-thermal.dtsi index 85ce545633e..c7486fb2a5b 100644 --- a/src/arm64/ti/k3-am62a-thermal.dtsi +++ b/src/arm64/ti/k3-am62a-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include diff --git a/src/arm64/ti/k3-am62a-wakeup.dtsi b/src/arm64/ti/k3-am62a-wakeup.dtsi index 4e8279fa01e..f7bec484705 100644 --- a/src/arm64/ti/k3-am62a-wakeup.dtsi +++ b/src/arm64/ti/k3-am62a-wakeup.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM62A SoC Family Wakeup Domain peripherals * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_wakeup { diff --git a/src/arm64/ti/k3-am62a.dtsi b/src/arm64/ti/k3-am62a.dtsi index 61a210ecd5f..b1b88460029 100644 --- a/src/arm64/ti/k3-am62a.dtsi +++ b/src/arm64/ti/k3-am62a.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM62A SoC Family * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include diff --git a/src/arm64/ti/k3-am62a7-sk.dts b/src/arm64/ti/k3-am62a7-sk.dts index 7b714258629..f241637a564 100644 --- a/src/arm64/ti/k3-am62a7-sk.dts +++ b/src/arm64/ti/k3-am62a7-sk.dts @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * AM62A SK: https://www.ti.com/lit/zip/sprr459 * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -20,6 +20,7 @@ serial0 = &wkup_uart0; serial2 = &main_uart0; serial3 = &main_uart1; + mmc0 = &sdhci0; mmc1 = &sdhci1; }; @@ -132,6 +133,18 @@ clock-frequency = <12288000>; }; + hdmi0: connector-hdmi { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&sii9022_out>; + }; + }; + }; + codec_audio: sound { compatible = "simple-audio-card"; simple-audio-card,name = "AM62Ax-SKEVM"; @@ -181,6 +194,39 @@ }; &main_pmx0 { + main_dss0_pins_default: main-dss0-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x100, PIN_OUTPUT, 0) /* (V17) VOUT0_VSYNC */ + AM62AX_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (T18) VOUT0_HSYNC */ + AM62AX_IOPAD(0x104, PIN_OUTPUT, 0) /* (AA22) VOUT0_PCLK */ + AM62AX_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (U17) VOUT0_DE */ + AM62AX_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */ + AM62AX_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (U21) VOUT0_DATA1 */ + AM62AX_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (U20) VOUT0_DATA2 */ + AM62AX_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (U19) VOUT0_DATA3 */ + AM62AX_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (T19) VOUT0_DATA4 */ + AM62AX_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (U18) VOUT0_DATA5 */ + AM62AX_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (V22) VOUT0_DATA6 */ + AM62AX_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA7 */ + AM62AX_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V19) VOUT0_DATA8 */ + AM62AX_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (V18) VOUT0_DATA9 */ + AM62AX_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (W22) VOUT0_DATA10 */ + AM62AX_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA11 */ + AM62AX_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (W20) VOUT0_DATA12 */ + AM62AX_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (W19) VOUT0_DATA13 */ + AM62AX_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y21) VOUT0_DATA14 */ + AM62AX_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA15 */ + AM62AX_IOPAD(0x05c, PIN_OUTPUT, 1) /* (P22) GPMC0_AD8.VOUT0_DATA16 */ + AM62AX_IOPAD(0x060, PIN_OUTPUT, 1) /* (R19) GPMC0_AD9.VOUT0_DATA17 */ + AM62AX_IOPAD(0x064, PIN_OUTPUT, 1) /* (R20) GPMC0_AD10.VOUT0_DATA18 */ + AM62AX_IOPAD(0x068, PIN_OUTPUT, 1) /* (R22) GPMC0_AD11.VOUT0_DATA19 */ + AM62AX_IOPAD(0x06c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */ + AM62AX_IOPAD(0x070, PIN_OUTPUT, 1) /* (R21) GPMC0_AD13.VOUT0_DATA21 */ + AM62AX_IOPAD(0x074, PIN_OUTPUT, 1) /* (T20) GPMC0_AD14.VOUT0_DATA22 */ + AM62AX_IOPAD(0x078, PIN_OUTPUT, 1) /* (T21) GPMC0_AD15.VOUT0_DATA23 */ + >; + }; + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */ @@ -218,6 +264,22 @@ >; }; + main_mmc0_pins_default: main-mmc0-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ + AM62AX_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLKLB */ + AM62AX_IOPAD(0x21c, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ + AM62AX_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ + AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */ + AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */ + AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */ + AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */ + AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */ + AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ + AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ @@ -466,6 +528,36 @@ "CSI_EN", "AUTO_100M_1000M_CONFIG", "CSI_VLDO_SEL", "SoC_WLAN_SDIO_RST"; }; + + sii9022: bridge-hdmi@3b { + compatible = "sil,sii9022"; + reg = <0x3b>; + interrupt-parent = <&exp1>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + #sound-dai-cells = <0>; + sil,i2s-data-lanes = < 0 >; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in: endpoint { + remote-endpoint = <&dpi1_out>; + }; + }; + + port@1 { + reg = <1>; + + sii9022_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; }; &main_i2c2 { @@ -475,13 +567,21 @@ clock-frequency = <400000>; }; +&sdhci0 { + /* eMMC */ + status = "okay"; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + disable-wp; +}; + &sdhci1 { /* SD/MMC */ status = "okay"; vmmc-supply = <&vdd_mmc1>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; @@ -583,3 +683,20 @@ tx-num-evt = <32>; rx-num-evt = <32>; }; + +&dss { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_dss0_pins_default>; +}; + +&dss_ports { + /* VP2: DPI Output */ + port@1 { + reg = <1>; + + dpi1_out: endpoint { + remote-endpoint = <&sii9022_in>; + }; + }; +}; diff --git a/src/arm64/ti/k3-am62a7.dtsi b/src/arm64/ti/k3-am62a7.dtsi index 58f1c43edcf..f86a23404e6 100644 --- a/src/arm64/ti/k3-am62a7.dtsi +++ b/src/arm64/ti/k3-am62a7.dtsi @@ -1,10 +1,10 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM62A7 SoC family in Quad core configuration * * TRM: https://www.ti.com/lit/zip/spruj16 * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am62p-main.dtsi b/src/arm64/ti/k3-am62p-main.dtsi index 4c51bae06b5..7337a9e1353 100644 --- a/src/arm64/ti/k3-am62p-main.dtsi +++ b/src/arm64/ti/k3-am62p-main.dtsi @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree file for the AM62P main domain peripherals - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_main { @@ -158,6 +158,43 @@ }; }; + dmss_csi: bus@4e000000 { + compatible = "simple-bus"; + ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x408000>; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges; + ti,sci-dev-id = <198>; + + inta_main_dmss_csi: interrupt-controller@4e400000 { + compatible = "ti,sci-inta"; + reg = <0x00 0x4e400000 0x00 0x8000>; + #interrupt-cells = <0>; + interrupt-controller; + interrupt-parent = <&gic500>; + msi-controller; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <200>; + ti,interrupt-ranges = <0 237 8>; + ti,unmapped-event-sources = <&main_bcdma_csi>; + }; + + main_bcdma_csi: dma-controller@4e230000 { + compatible = "ti,am62a-dmss-bcdma-csirx"; + reg = <0x00 0x4e230000 0x00 0x100>, + <0x00 0x4e180000 0x00 0x8000>, + <0x00 0x4e100000 0x00 0x10000>; + reg-names = "gcfg", "rchanrt", "ringrt"; + #dma-cells = <3>; + msi-parent = <&inta_main_dmss_csi>; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <199>; + ti,sci-rm-range-rchan = <0x21>; + }; + }; + dmsc: system-controller@44043000 { compatible = "ti,k2g-sci"; ti,host-id = <12>; @@ -534,7 +571,21 @@ clock-names = "clk_ahb", "clk_xin"; assigned-clocks = <&k3_clks 57 2>; assigned-clock-parents = <&k3_clks 57 4>; - ti,otap-del-sel-legacy = <0x0>; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + ti,clkbuf-sel = <0x7>; + ti,strobe-sel = <0x77>; + ti,trm-icp = <0x8>; + ti,otap-del-sel-legacy = <0x1>; + ti,otap-del-sel-mmc-hs = <0x1>; + ti,otap-del-sel-ddr52 = <0x6>; + ti,otap-del-sel-hs200 = <0x8>; + ti,otap-del-sel-hs400 = <0x5>; + ti,itap-del-sel-legacy = <0x10>; + ti,itap-del-sel-mmc-hs = <0xa>; + ti,itap-del-sel-ddr52 = <0x3>; status = "disabled"; }; @@ -545,7 +596,19 @@ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; - ti,otap-del-sel-legacy = <0x8>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; status = "disabled"; }; @@ -556,7 +619,19 @@ power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; clock-names = "clk_ahb", "clk_xin"; - ti,otap-del-sel-legacy = <0x8>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; status = "disabled"; }; @@ -891,4 +966,73 @@ power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; + + ti_csi2rx0: ticsi2rx@30102000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x30102000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x5000 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@30101000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x30101000 0x00 0x1000>; + clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, + <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@30110000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x30110000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + vpu: video-codec@30210000 { + compatible = "ti,j721s2-wave521c", "cnm,wave521c"; + reg = <0x00 0x30210000 0x00 0x10000>; + interrupts = ; + clocks = <&k3_clks 204 2>; + power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; + }; }; diff --git a/src/arm64/ti/k3-am62p-mcu.dtsi b/src/arm64/ti/k3-am62p-mcu.dtsi index c4b0b91d70c..b973b550eb9 100644 --- a/src/arm64/ti/k3-am62p-mcu.dtsi +++ b/src/arm64/ti/k3-am62p-mcu.dtsi @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree file for the AM62P MCU domain peripherals - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu { @@ -187,6 +187,8 @@ ranges = <0x79000000 0x00 0x79000000 0x8000>, <0x79020000 0x00 0x79020000 0x8000>; power-domains = <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + mcu_r5fss0_core0: r5f@79000000 { compatible = "ti,am62-r5f"; reg = <0x79000000 0x00008000>, diff --git a/src/arm64/ti/k3-am62p-thermal.dtsi b/src/arm64/ti/k3-am62p-thermal.dtsi index 85ce545633e..c7486fb2a5b 100644 --- a/src/arm64/ti/k3-am62p-thermal.dtsi +++ b/src/arm64/ti/k3-am62p-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include diff --git a/src/arm64/ti/k3-am62p-wakeup.dtsi b/src/arm64/ti/k3-am62p-wakeup.dtsi index 19f42b39394..a84756c336d 100644 --- a/src/arm64/ti/k3-am62p-wakeup.dtsi +++ b/src/arm64/ti/k3-am62p-wakeup.dtsi @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree file for the AM62P wakeup domain peripherals - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_wakeup { @@ -78,6 +78,7 @@ ranges = <0x78000000 0x00 0x78000000 0x8000>, <0x78100000 0x00 0x78100000 0x8000>; power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; wkup_r5fss0_core0: r5f@78000000 { compatible = "ti,am62-r5f"; diff --git a/src/arm64/ti/k3-am62p.dtsi b/src/arm64/ti/k3-am62p.dtsi index 84ffe7b9dca..94babc41257 100644 --- a/src/arm64/ti/k3-am62p.dtsi +++ b/src/arm64/ti/k3-am62p.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM62P SoC Family * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include @@ -71,7 +71,7 @@ <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ - <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */ + <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */ <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ diff --git a/src/arm64/ti/k3-am62p5-sk.dts b/src/arm64/ti/k3-am62p5-sk.dts index 1773c05f752..e86f34e835c 100644 --- a/src/arm64/ti/k3-am62p5-sk.dts +++ b/src/arm64/ti/k3-am62p5-sk.dts @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree file for the AM62P5-SK - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ * * Schematics: https://www.ti.com/lit/zip/sprr487 */ @@ -413,6 +413,7 @@ status = "okay"; ti,driver-strength-ohm = <50>; disable-wp; + bootph-all; }; &sdhci1 { @@ -422,9 +423,7 @@ vqmmc-supply = <&vddshv_sdio>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; - no-1-8-v; bootph-all; }; @@ -445,6 +444,10 @@ }; &cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&main_mdio1_pins_default>; + status = "okay"; + cpsw3g_phy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = ; diff --git a/src/arm64/ti/k3-am62p5.dtsi b/src/arm64/ti/k3-am62p5.dtsi index 50147bb63e0..41f479dca45 100644 --- a/src/arm64/ti/k3-am62p5.dtsi +++ b/src/arm64/ti/k3-am62p5.dtsi @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree file for the AM62P5 SoC family (quad core) - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ * * TRM: https://www.ti.com/lit/pdf/spruj83 */ diff --git a/src/arm64/ti/k3-am62x-phyboard-lyra-gpio-fan.dtso b/src/arm64/ti/k3-am62x-phyboard-lyra-gpio-fan.dtso new file mode 100644 index 00000000000..f0b2fd4165a --- /dev/null +++ b/src/arm64/ti/k3-am62x-phyboard-lyra-gpio-fan.dtso @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2024 PHYTEC America LLC + * Author: Garrett Giordano + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "k3-pinctrl.h" + +&{/} { + fan: gpio-fan { + compatible = "gpio-fan"; + gpio-fan,speed-map = <0 0 8600 1>; + gpios = <&main_gpio0 40 GPIO_ACTIVE_LOW>; + #cooling-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_fan_pins_default>; + }; +}; + +&main_pmx0 { + gpio_fan_pins_default: gpio-fan-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0a4, PIN_OUTPUT, 7) /* (M22) GPMC0_DIR.GPIO0_40 */ + >; + }; +}; + +&thermal_zones { + main0_thermal: main0-thermal { + trips { + main0_thermal_trip0: main0-thermal-trip { + temperature = <65000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + }; + + cooling-maps { + map0 { + trip = <&main0_thermal_trip0>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/src/arm64/ti/k3-am62x-sk-common.dtsi b/src/arm64/ti/k3-am62x-sk-common.dtsi index 33768c02d8e..3c45782ab2b 100644 --- a/src/arm64/ti/k3-am62x-sk-common.dtsi +++ b/src/arm64/ti/k3-am62x-sk-common.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Common dtsi for AM62x SK and derivatives * - * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include @@ -411,7 +411,6 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mmc0_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; @@ -421,7 +420,6 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; @@ -460,6 +458,7 @@ }; &usbss0 { + bootph-all; status = "okay"; ti,vbus-divider; }; @@ -470,6 +469,7 @@ }; &usb0 { + bootph-all; #address-cells = <1>; #size-cells = <0>; usb-role-switch; diff --git a/src/arm64/ti/k3-am62x-sk-csi2-imx219.dtso b/src/arm64/ti/k3-am62x-sk-csi2-imx219.dtso index 6f4cd73c2f4..76ca02127f9 100644 --- a/src/arm64/ti/k3-am62x-sk-csi2-imx219.dtso +++ b/src/arm64/ti/k3-am62x-sk-csi2-imx219.dtso @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * IMX219 (RPi v2) Camera Module - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am62x-sk-csi2-ov5640.dtso b/src/arm64/ti/k3-am62x-sk-csi2-ov5640.dtso index 9323a4b3838..ccc7f5e4318 100644 --- a/src/arm64/ti/k3-am62x-sk-csi2-ov5640.dtso +++ b/src/arm64/ti/k3-am62x-sk-csi2-ov5640.dtso @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * ALINX AN5641 & Digilent PCam 5C - OV5640 camera module - * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso b/src/arm64/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso index dcaa33a4c8d..4eaf9d757dd 100644 --- a/src/arm64/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso +++ b/src/arm64/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Technexion TEVI-OV5640-*-RPI - OV5640 camera module - * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am62x-sk-hdmi-audio.dtso b/src/arm64/ti/k3-am62x-sk-hdmi-audio.dtso index 43a0ddc123e..18c3082f68e 100644 --- a/src/arm64/ti/k3-am62x-sk-hdmi-audio.dtso +++ b/src/arm64/ti/k3-am62x-sk-hdmi-audio.dtso @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * Audio playback via HDMI for AM625-SK and AM62-LP SK. * @@ -6,7 +6,7 @@ * AM625 SK: https://www.ti.com/tool/SK-AM62 * AM62-LP SK: https://www.ti.com/tool/SK-AM62-LP * - * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am64-main.dtsi b/src/arm64/ti/k3-am64-main.dtsi index e348114f42e..6f9aa5e0213 100644 --- a/src/arm64/ti/k3-am64-main.dtsi +++ b/src/arm64/ti/k3-am64-main.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM642 SoC Family Main Domain peripherals * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include @@ -51,10 +51,11 @@ reg = <0x00000014 0x4>; }; - serdes_ln_ctrl: mux-controller { - compatible = "mmio-mux"; + serdes_ln_ctrl: mux-controller@4080 { + compatible = "reg-mux"; + reg = <0x4080 0x4>; #mux-control-cells = <1>; - mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */ + mux-reg-masks = <0x0 0x3>; /* SERDES0 lane0 select */ }; phy_gmii_sel: phy@4044 { @@ -626,13 +627,18 @@ power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 57 0>, <&k3_clks 57 1>; clock-names = "clk_ahb", "clk_xin"; + bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; + ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x2>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-ddr52 = <0x6>; ti,otap-del-sel-hs200 = <0x7>; + ti,itap-del-sel-legacy = <0x10>; + ti,itap-del-sel-mmc-hs = <0xa>; + ti,itap-del-sel-ddr52 = <0x3>; status = "disabled"; }; @@ -643,15 +649,19 @@ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-sdr104 = <0x6>; ti,otap-del-sel-ddr50 = <0x9>; - ti,clkbuf-sel = <0x7>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; status = "disabled"; }; @@ -1041,25 +1051,6 @@ status = "disabled"; }; - pcie0_ep: pcie-ep@f102000 { - compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep"; - reg = <0x00 0x0f102000 0x00 0x1000>, - <0x00 0x0f100000 0x00 0x400>, - <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x68000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = ; - ti,syscon-pcie-ctrl = <&main_conf 0x4070>; - max-link-speed = <2>; - num-lanes = <1>; - power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 114 0>; - clock-names = "fck"; - max-functions = /bits/ 8 <1>; - status = "disabled"; - }; - epwm0: pwm@23000000 { compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; @@ -1244,6 +1235,18 @@ }; }; + icssg0_iep0: iep@2e000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2e000 0x1000>; + clocks = <&icssg0_iepclk_mux>; + }; + + icssg0_iep1: iep@2f000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2f000 0x1000>; + clocks = <&icssg0_iepclk_mux>; + }; + icssg0_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x100>; @@ -1385,6 +1388,18 @@ }; }; + icssg1_iep0: iep@2e000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2e000 0x1000>; + clocks = <&icssg1_iepclk_mux>; + }; + + icssg1_iep1: iep@2f000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2f000 0x1000>; + clocks = <&icssg1_iepclk_mux>; + }; + icssg1_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x100>; diff --git a/src/arm64/ti/k3-am64-mcu.dtsi b/src/arm64/ti/k3-am64-mcu.dtsi index b9508072beb..ec17285869d 100644 --- a/src/arm64/ti/k3-am64-mcu.dtsi +++ b/src/arm64/ti/k3-am64-mcu.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM64 SoC Family MCU Domain peripherals * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu { diff --git a/src/arm64/ti/k3-am64-phycore-som.dtsi b/src/arm64/ti/k3-am64-phycore-som.dtsi index 1678e74cb75..125e507966f 100644 --- a/src/arm64/ti/k3-am64-phycore-som.dtsi +++ b/src/arm64/ti/k3-am64-phycore-som.dtsi @@ -1,9 +1,9 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com + * Copyright (C) 2021-2024 PHYTEC America, LLC - https://www.phytec.com * Author: Matt McKee * - * Copyright (C) 2022 PHYTEC Messtechnik GmbH + * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH * Author: Wadim Egorov * * Product homepage: @@ -318,3 +318,10 @@ disable-wp; keep-power-in-suspend; }; + +&tscadc0 { + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; diff --git a/src/arm64/ti/k3-am64-thermal.dtsi b/src/arm64/ti/k3-am64-thermal.dtsi index 036db56ba79..b1cd5542428 100644 --- a/src/arm64/ti/k3-am64-thermal.dtsi +++ b/src/arm64/ti/k3-am64-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include diff --git a/src/arm64/ti/k3-am64.dtsi b/src/arm64/ti/k3-am64.dtsi index 0187c42aed4..74e56cc68d4 100644 --- a/src/arm64/ti/k3-am64.dtsi +++ b/src/arm64/ti/k3-am64.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM642 SoC Family * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include diff --git a/src/arm64/ti/k3-am642-evm-icssg1-dualemac.dtso b/src/arm64/ti/k3-am642-evm-icssg1-dualemac.dtso new file mode 100644 index 00000000000..af2fd3e7448 --- /dev/null +++ b/src/arm64/ti/k3-am642-evm-icssg1-dualemac.dtso @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT overlay for enabling 2nd ICSSG1 port on AM642 EVM + * + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 = "/icssg1-eth/ethernet-ports/port@1"; + }; + + mdio-mux-2 { + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mdio_mux>; + mdio-parent-bus = <&icssg1_mdio>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + icssg1_phy2: ethernet-phy@3 { + reg = <3>; + tx-internal-delay-ps = <250>; + rx-internal-delay-ps = <2000>; + }; + }; + }; +}; + +&main_pmx0 { + icssg1_rgmii2_pins_default: icssg1-rgmii2-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ + AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ + AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ + AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ + AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ + AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ + AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ + AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ + AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ + AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ + AM64X_IOPAD(0x0148, PIN_OUTPUT, 2) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ + AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ + >; + }; +}; + +&cpsw3g { + pinctrl-0 = <&rgmii1_pins_default>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&mdio_mux_1 { + status = "disabled"; +}; + +&icssg1_eth { + pinctrl-0 = <&icssg1_rgmii1_pins_default>, <&icssg1_rgmii2_pins_default>; +}; + +&icssg1_emac1 { + status = "okay"; + phy-handle = <&icssg1_phy2>; + phy-mode = "rgmii-id"; +}; diff --git a/src/arm64/ti/k3-am642-evm.dts b/src/arm64/ti/k3-am642-evm.dts index 8c5651d2cf5..53fe1d065dd 100644 --- a/src/arm64/ti/k3-am642-evm.dts +++ b/src/arm64/ti/k3-am642-evm.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -32,6 +32,7 @@ mmc1 = &sdhci1; ethernet0 = &cpsw_port1; ethernet1 = &cpsw_port2; + ethernet2 = &icssg1_emac0; }; memory@80000000 { @@ -198,7 +199,7 @@ mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>; }; - mdio-mux-1 { + mdio_mux_1: mdio-mux-1 { compatible = "mdio-mux-multiplexer"; mux-controls = <&mdio_mux>; mdio-parent-bus = <&cpsw3g_mdio>; @@ -229,6 +230,64 @@ max-bitrate = <5000000>; standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>; }; + + icssg1_eth: icssg1-eth { + compatible = "ti,am642-icssg-prueth"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg1_rgmii1_pins_default>; + sram = <&oc_sram>; + ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>; + firmware-name = "ti-pruss/am64x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am64x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am64x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am64x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am64x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am64x-sr2-txpru1-prueth-fw.elf"; + + ti,pruss-gp-mux-sel = <2>, /* MII mode */ + <2>, + <2>, + <2>, /* MII mode */ + <2>, + <2>; + ti,mii-g-rt = <&icssg1_mii_g_rt>; + ti,mii-rt = <&icssg1_mii_rt>; + ti,iep = <&icssg1_iep0>, <&icssg1_iep1>; + interrupt-parent = <&icssg1_intc>; + interrupts = <24 0 2>, <25 1 3>; + interrupt-names = "tx_ts0", "tx_ts1"; + dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */ + <&main_pktdma 0xc201 15>, /* egress slice 0 */ + <&main_pktdma 0xc202 15>, /* egress slice 0 */ + <&main_pktdma 0xc203 15>, /* egress slice 0 */ + <&main_pktdma 0xc204 15>, /* egress slice 1 */ + <&main_pktdma 0xc205 15>, /* egress slice 1 */ + <&main_pktdma 0xc206 15>, /* egress slice 1 */ + <&main_pktdma 0xc207 15>, /* egress slice 1 */ + <&main_pktdma 0x4200 15>, /* ingress slice 0 */ + <&main_pktdma 0x4201 15>; /* ingress slice 1 */ + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + icssg1_emac0: port@0 { + reg = <0>; + phy-handle = <&icssg1_phy1>; + phy-mode = "rgmii-id"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + icssg1_emac1: port@1 { + reg = <1>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + }; + }; + }; }; &main_pmx0 { @@ -383,6 +442,30 @@ AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */ >; }; + + icssg1_mdio1_pins_default: icssg1-mdio1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (Y6) PRG1_MDIO0_MDC */ + AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA6) PRG1_MDIO0_MDIO */ + >; + }; + + icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins{ + pinctrl-single,pins = < + AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */ + AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */ + AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */ + AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */ + AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */ + AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */ + AM64X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */ + AM64X_IOPAD(0x00e8, PIN_INPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */ + AM64X_IOPAD(0x00ec, PIN_INPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */ + AM64X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */ + AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */ + AM64X_IOPAD(0x00f4, PIN_INPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */ + >; + }; }; &main_uart0 { @@ -494,10 +577,10 @@ /* eMMC */ &sdhci0 { status = "okay"; - bus-width = <8>; non-removable; ti,driver-strength-ohm = <50>; disable-wp; + bootph-all; }; /* SD/MMC */ @@ -506,9 +589,7 @@ status = "okay"; vmmc-supply = <&vdd_mmc1>; pinctrl-names = "default"; - bus-width = <4>; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; @@ -660,25 +741,25 @@ }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; @@ -705,12 +786,6 @@ num-lanes = <1>; }; -&pcie0_ep { - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <1>; -}; - &ecap0 { status = "okay"; /* PWM is available on Pin 1 of header J12 */ @@ -731,3 +806,15 @@ pinctrl-0 = <&main_mcan1_pins_default>; phys = <&transceiver2>; }; + +&icssg1_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg1_mdio1_pins_default>; + + icssg1_phy1: ethernet-phy@f { + reg = <0xf>; + tx-internal-delay-ps = <250>; + rx-internal-delay-ps = <2000>; + }; +}; diff --git a/src/arm64/ti/k3-am642-hummingboard-t-pcie.dtso b/src/arm64/ti/k3-am642-hummingboard-t-pcie.dtso new file mode 100644 index 00000000000..bd9a5caf20d --- /dev/null +++ b/src/arm64/ti/k3-am642-hummingboard-t-pcie.dtso @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Josua Mayer + * + * Overlay for SolidRun AM642 HummingBoard-T to enable PCI-E. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-serdes.h" + +&pcie0_rc { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_pins>; + reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; + status = "okay"; +}; + +&serdes0 { + #address-cells = <1>; + #size-cells = <0>; + + serdes0_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + cdns,phy-type = ; + #phy-cells = <0>; + resets = <&serdes_wiz0 1>; + }; +}; + +&serdes_ln_ctrl { + idle-states = ; +}; + +&serdes_mux { + idle-state = <1>; +}; diff --git a/src/arm64/ti/k3-am642-hummingboard-t-usb3.dtso b/src/arm64/ti/k3-am642-hummingboard-t-usb3.dtso new file mode 100644 index 00000000000..ffcc3bd3c7b --- /dev/null +++ b/src/arm64/ti/k3-am642-hummingboard-t-usb3.dtso @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Josua Mayer + * + * Overlay for SolidRun AM642 HummingBoard-T to enable USB-3.1. + */ + +/dts-v1/; +/plugin/; + +#include + +#include "k3-serdes.h" + +&serdes0 { + #address-cells = <1>; + #size-cells = <0>; + + serdes0_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + cdns,phy-type = ; + #phy-cells = <0>; + resets = <&serdes_wiz0 1>; + }; +}; + +&serdes_ln_ctrl { + idle-states = ; +}; + +&serdes_mux { + idle-state = <0>; +}; + +&usbss0 { + /delete-property/ ti,usb2-only; +}; + +&usb0 { + maximum-speed = "super-speed"; + phys = <&serdes0_link>; + phy-names = "cdns3,usb3-phy"; +}; diff --git a/src/arm64/ti/k3-am642-hummingboard-t.dts b/src/arm64/ti/k3-am642-hummingboard-t.dts new file mode 100644 index 00000000000..234d76e4e94 --- /dev/null +++ b/src/arm64/ti/k3-am642-hummingboard-t.dts @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Josua Mayer + * + * DTS for SolidRun AM642 HummingBoard-T, + * running on Cortex A53. + * + */ + +/dts-v1/; + +#include +#include + +#include "k3-am642.dtsi" +#include "k3-am642-sr-som.dtsi" + +/ { + model = "SolidRun AM642 HummingBoard-T"; + compatible = "solidrun,am642-hummingboard-t", "solidrun,am642-sr-som", "ti,am642"; + + aliases { + serial5 = &main_uart3; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_default_pins>; + + /* D24 */ + led1: led-1 { + label = "led1"; + gpios = <&main_gpio0 29 GPIO_ACTIVE_HIGH>; + color = ; + }; + + /* D25 */ + led2: led-2 { + label = "led2"; + gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>; + color = ; + }; + + /* D26 */ + led3: led-3 { + label = "led3"; + gpios = <&main_gpio0 33 GPIO_ACTIVE_HIGH>; + color = ; + }; + }; + + regulator-m2-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <®ulator_pcie_3v3_default_pins>; + regulator-name = "m2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&main_gpio1 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + regulator-vpp-1v8 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <®ulator_vpp_1v8_default_pins>; + regulator-name = "vpp-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&main_gpio1 78 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + serdes_mux: mux-controller { + compatible = "gpio-mux"; + pinctrl-names = "default"; + pinctrl-0 = <&serdes_mux_default_pins>; + #mux-control-cells = <0>; + /* + * Mux has 2 IOs: + * - select: 0 = USB-3 (M2); 1 = PCIE (M1) + * - shutdown: 0 = active; 1 = disabled (high impedance) + */ + mux-gpios = <&main_gpio1 40 GPIO_ACTIVE_HIGH>, <&main_gpio1 41 GPIO_ACTIVE_HIGH>; + /* default disabled */ + idle-state = <2>; + }; +}; + +&main_gpio0 { + m2-reset-hog { + gpio-hog; + gpios = <12 GPIO_ACTIVE_LOW>; + output-low; /* deasserted */ + line-name = "m2-reset"; + }; + + m1-m2-w-disable1-hog { + gpio-hog; + gpios = <32 GPIO_ACTIVE_LOW>; + output-low; /* deasserted */ + line-name = "m1-m2-pcie-w-disable1"; + }; + + m1-m2-w-disable2-hog { + gpio-hog; + gpios = <34 GPIO_ACTIVE_LOW>; + output-low; /* deasserted */ + line-name = "m1-m2-pcie-w-disable2"; + }; +}; + +&main_gpio1 { + m1-pcie-clkreq0-hog { + gpio-hog; + gpios = <11 GPIO_ACTIVE_LOW>; + input; + line-name = "m1-pcie-clkreq0"; + }; + + m2-pcie-clkreq-hog { + gpio-hog; + gpios = <35 GPIO_ACTIVE_LOW>; + input; + line-name = "m2-pcie-clkreq"; + }; +}; + +&main_i2c0 { + pinctrl-0 = <&main_i2c0_default_pins>, <&main_i2c0_int_default_pins>; + + humidity-sensor@41 { + compatible = "ti,hdc2010"; + reg = <0x41>; + interrupt-parent = <&main_gpio0>; + interrupts = <37 IRQ_TYPE_EDGE_FALLING>; + }; + + light-sensor@44 { + compatible = "ti,opt3001"; + reg = <0x44>; + interrupt-parent = <&main_gpio0>; + interrupts = <37 IRQ_TYPE_EDGE_FALLING>; + }; + + /* charger@6a */ +}; + +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_default_pins>; + status = "okay"; + + rtc@69 { + compatible = "abracon,abx80x"; + reg = <0x69>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int_default_pins>; + abracon,tc-diode = "schottky"; + abracon,tc-resistor = <3>; + interrupt-parent = <&main_gpio0>; + interrupts = <44 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&main_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan0_default_pins>; + status = "okay"; + + can-transceiver { + max-bitrate = <8000000>; + }; +}; + +&main_mcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan1_default_pins>; + status = "okay"; + + can-transceiver { + max-bitrate = <8000000>; + }; +}; + +&main_pmx0 { + leds_default_pins: leds-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0074, PIN_OUTPUT, 7) /* GPMC0_AD14.GPIO0_29 */ + AM64X_IOPAD(0x0078, PIN_OUTPUT, 7) /* GPMC0_AD15.GPIO0_30 */ + AM64X_IOPAD(0x0088, PIN_OUTPUT, 7) /* GPMC0_OEn_REn.GPIO0_33 */ + >; + }; + + main_i2c0_int_default_pins: main-i2c0-int-default-pins { + pinctrl-single,pins = < + /* external pull-up on Carrier */ + AM64X_IOPAD(0x0098, PIN_INPUT, 7) /* GPMC0_WAIT0.GPIO0_37 */ + >; + }; + + main_i2c1_default_pins: main-i2c1-default-pins { + pinctrl-single,pins = < + /* external pull-up on SoM */ + AM64X_IOPAD(0x0268, PIN_INPUT, 0) /* I2C1_SCL.I2C1_SCL */ + AM64X_IOPAD(0x026c, PIN_INPUT, 0) /* I2C1_SDA.I2C1_SDA */ + >; + }; + + main_mcan0_default_pins: main-mcan0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* MCAN0_RX.MCAN0_RX */ + AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* MCAN0_TX.MCAN0_TX */ + >; + }; + + main_mcan1_default_pins: main-mcan1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* MCAN1_RX.MCAN1_RX */ + AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* MCAN1_TX.MCAN1_TX */ + >; + }; + + main_uart3_default_pins: main-uart3-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x016c, PIN_INPUT, 10) /* PRG0_PRU0_GPO3.UART3_CTSn */ + AM64X_IOPAD(0x0170, PIN_OUTPUT, 10) /* PRG0_PRU0_GPO4.UART3_TXD */ + AM64X_IOPAD(0x0174, PIN_OUTPUT, 10) /* PRG0_PRU0_GPO5.UART3_RTSn */ + AM64X_IOPAD(0x01ac, PIN_INPUT, 10) /* PRG0_PRU0_GPO19.UART3_RXD */ + >; + }; + + pcie0_default_pins: pcie0-default-pins { + pinctrl-single,pins = < + /* connector M2 RESET */ + AM64X_IOPAD(0x0030, PIN_OUTPUT, 7) /* OSPI0_CSn1.GPIO0_12 */ + /* connectors M1 & M2 W_DISABLE1 */ + AM64X_IOPAD(0x0084, PIN_OUTPUT, 7) /* GPMC0_ADVN_ALE.GPIO0_32 */ + /* connectors M1 & M2 W_DISABLE2 */ + AM64X_IOPAD(0x008c, PIN_OUTPUT, 7) /* GPMC0_WEN.GPIO0_34 */ + /* connectors M1 & M2 PERST0 (PCI Reset) */ + AM64X_IOPAD(0x019c, PIN_OUTPUT, 7) /* PRG0_PRU0_GPO15.GPIO1_15 */ + /* connector M1 CLKREQ0 */ + AM64X_IOPAD(0x018c, PIN_INPUT, 7) /* PRG0_PRU0_GPO11.GPIO1_11 */ + /* connector M2 CLKREQ0 */ + AM64X_IOPAD(0x01ec, PIN_INPUT, 7) /* PRG0_PRU1_GPO15.GPIO1_35 */ + >; + }; + + regulator_pcie_3v3_default_pins: regulator-pcie-3v3-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x01a4, PIN_OUTPUT, 7) /* PRG0_PRU0_GPO17.GPIO1_17 */ + >; + }; + + regulator_vpp_1v8_default_pins: regulator-vpp-1v8-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x029c, PIN_OUTPUT, 7) /* MMC1_SDWP.GPIO1_78 */ + >; + }; + + rtc_int_default_pins: rtc-int-default-pins { + pinctrl-single,pins = < + /* external pull-up on Carrier */ + AM64X_IOPAD(0x00b4, PIN_INPUT, 7) /* GPMC0_CSn3.GPIO0_44 */ + >; + }; + + serdes_mux_default_pins: serdes-mux-default-pins { + pinctrl-single,pins = < + /* SEL, 10k pull-down on carrier, 2.2k pullup on SoM */ + AM64X_IOPAD(0x0200, PIN_OUTPUT, 7) /* PRG0_MDIO0_MDIO.GPIO1_40 */ + /* EN */ + AM64X_IOPAD(0x0204, PIN_OUTPUT, 7) /* PRG0_MDIO0_MDC.GPIO1_41 */ + >; + }; +}; + +&main_uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart3_default_pins>; + uart-has-rtscts; + rs485-rts-active-low; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&usb0 { + dr_mode = "host"; +}; diff --git a/src/arm64/ti/k3-am642-phyboard-electra-rdk.dts b/src/arm64/ti/k3-am642-phyboard-electra-rdk.dts index 53b64e55413..8237b8c815b 100644 --- a/src/arm64/ti/k3-am642-phyboard-electra-rdk.dts +++ b/src/arm64/ti/k3-am642-phyboard-electra-rdk.dts @@ -1,9 +1,9 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com + * Copyright (C) 2021-2024 PHYTEC America, LLC - https://www.phytec.com * Author: Matt McKee * - * Copyright (C) 2022 PHYTEC Messtechnik GmbH + * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH * Author: Wadim Egorov * * Product homepage: @@ -159,6 +159,15 @@ >; }; + main_spi0_pins_default: main-spi0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x020c, PIN_OUTPUT, 7) /* (C13) SPI0_CS1.GPIO1_43 */ + AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */ + AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */ + AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */ + >; + }; + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ @@ -248,6 +257,20 @@ phys = <&can_tc2>; }; +&main_spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_spi0_pins_default>; + cs-gpios = <0>, <&main_gpio1 43 GPIO_ACTIVE_LOW>; + ti,pindir-d0-out-d1-in; + + tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <1>; + spi-max-frequency = <10000000>; + }; +}; + &main_uart0 { status = "okay"; pinctrl-names = "default"; @@ -269,7 +292,6 @@ pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; bus-width = <4>; - ti,driver-strength-ohm = <50>; disable-wp; no-1-8-v; }; diff --git a/src/arm64/ti/k3-am642-sk.dts b/src/arm64/ti/k3-am642-sk.dts index 1dddd6fc1a0..67cd41bf806 100644 --- a/src/arm64/ti/k3-am642-sk.dts +++ b/src/arm64/ti/k3-am642-sk.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -469,9 +469,7 @@ status = "okay"; vmmc-supply = <&vdd_mmc1>; pinctrl-names = "default"; - bus-width = <4>; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; @@ -646,25 +644,25 @@ }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; diff --git a/src/arm64/ti/k3-am642-sr-som.dtsi b/src/arm64/ti/k3-am642-sr-som.dtsi new file mode 100644 index 00000000000..c19d0b8bbf0 --- /dev/null +++ b/src/arm64/ti/k3-am642-sr-som.dtsi @@ -0,0 +1,594 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Josua Mayer + * + */ + +#include + +/ { + model = "SolidRun AM642 SoM"; + compatible = "solidrun,am642-sr-som", "ti,am642"; + + aliases { + ethernet0 = &cpsw_port1; + ethernet1 = &icssg1_emac0; + ethernet2 = &icssg1_emac1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + serial2 = &main_uart0; + }; + + chosen { + /* SoC default UART console */ + stdout-path = "serial2:115200n8"; + }; + + /* PRU Ethernet Controller */ + ethernet { + compatible = "ti,am642-icssg-prueth"; + pinctrl-names = "default"; + pinctrl-0 = <&pru_rgmii1_default_pins>, <&pru_rgmii2_default_pins>; + + sram = <&oc_sram>; + ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>; + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; + + /* configure internal pinmux for mii mode */ + ti,pruss-gp-mux-sel = <2>, <2>, <2>, <2>, <2>, <2>; + + ti,mii-g-rt = <&icssg1_mii_g_rt>; + ti,mii-rt = <&icssg1_mii_rt>; + ti,iep = <&icssg1_iep0>, <&icssg1_iep1>; + + /* + * Configure icssg interrupt controller to map pru-internal + * interrupts 8/9 via channels 0/1 to host interrupts 0/1. + * + * For details see interrupt controller documentation: + * Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml + */ + interrupt-parent = <&icssg1_intc>; + interrupts = <24 0 2>, <25 1 3>; + interrupt-names = "tx_ts0", "tx_ts1"; + + dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */ + <&main_pktdma 0xc201 15>, /* egress slice 0 */ + <&main_pktdma 0xc202 15>, /* egress slice 0 */ + <&main_pktdma 0xc203 15>, /* egress slice 0 */ + <&main_pktdma 0xc204 15>, /* egress slice 1 */ + <&main_pktdma 0xc205 15>, /* egress slice 1 */ + <&main_pktdma 0xc206 15>, /* egress slice 1 */ + <&main_pktdma 0xc207 15>, /* egress slice 1 */ + <&main_pktdma 0x4200 15>, /* ingress slice 0 */ + <&main_pktdma 0x4201 15>; /* ingress slice 1 */ + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + icssg1_emac0: port@0 { + reg = <0>; + ti,syscon-rgmii-delay = <&main_conf 0x4110>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <ðernet_phy2>; + phy-mode = "rgmii-id"; + }; + + icssg1_emac1: port@1 { + reg = <1>; + ti,syscon-rgmii-delay = <&main_conf 0x4114>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <ðernet_phy1>; + phy-mode = "rgmii-id"; + }; + }; + }; + + /* DDR16SS0: + * - Bank 1 @ 0x080000000-0x0FFFFFFFF: max. 2GB in 32-bit address space + * - Bank 2 @ 0x880000000-0x9FFFFFFFF: max. 6GB in 64-bit address space + */ + memory@80000000 { + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000001 0x80000000>; + device_type = "memory"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + }; + + vdd_mmc0: regulator-vdd-mmc0 { + compatible = "regulator-fixed"; + regulator-name = "vdd-mmc0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_default_pins>; +}; + +&cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_default_pins>; + status = "okay"; + + ethernet_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id2000.a0f1"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <ðernet_phy0_default_pins>; + ti,clk-output-sel = ; + ti,op-mode = ; + /* + * Disable interrupts because ISR never clears 0x0040 + * + * interrupt-parent = <&main_gpio1>; + * interrupts = <70 IRQ_TYPE_LEVEL_LOW>; + */ + /* + * Disable HW Reset because clock signal is daisy-chained + * + * reset-gpios = <&main_gpio0 84 GPIO_ACTIVE_LOW>; + * reset-assert-us = <1>; + * reset-deassert-us = <30>; + */ + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy0>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&icssg1_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&pru1_mdio0_default_pins>; + status = "okay"; + + ethernet_phy1: ethernet-phy@3 { + compatible = "ethernet-phy-id2000.a0f1"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <ðernet_phy1_default_pins>; + ti,clk-output-sel = ; + ti,op-mode = ; + /* + * Disable interrupts because ISR never clears 0x0040 + * + * interrupt-parent = <&main_gpio1>; + * interrupts = <70 IRQ_TYPE_LEVEL_LOW>; + */ + /* + * Disable HW Reset because clock signal is daisy-chained + * + * reset-gpios = <&main_gpio0 20 GPIO_ACTIVE_LOW>; + * reset-assert-us = <1>; + * reset-deassert-us = <30>; + */ + }; + + ethernet_phy2: ethernet-phy@f { + compatible = "ethernet-phy-id2000.a0f1"; + reg = <0xf>; + pinctrl-names = "default"; + pinctrl-0 = <ðernet_phy2_default_pins>; + ti,op-mode = ; + /* + * Disable interrupts because ISR never clears 0x0040 + * + * interrupt-parent = <&main_gpio1>; + * interrupts = <70 IRQ_TYPE_LEVEL_LOW>; + */ + /* + * Disable HW Reset because clock signal is daisy-chained + * + * reset-gpios = <&main_gpio0 52 GPIO_ACTIVE_LOW>; + * reset-assert-us = <1>; + * reset-deassert-us = <30>; + */ + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 2>; + ti,mbox-tx = <3 0 2>; + }; +}; + +&mailbox0_cluster4 { + status = "okay"; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 2>; + ti,mbox-tx = <3 0 2>; + }; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_default_pins>; + status = "okay"; + + som_eeprom: eeprom@50 { + compatible = "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; + }; +}; + +&main_pmx0 { + /* hog global functions */ + pinctrl-names = "default"; + pinctrl-0 = <ðernet_phy_default_pins>; + + ethernet_phy_default_pins: ethernet-phy-default-pins { + pinctrl-single,pins = < + /* interrupt / power-down, external pull-up on SoM */ + AM64X_IOPAD(0x0278, PIN_INPUT, 7) /* EXTINTn.GPIO1_70 */ + >; + }; + + ethernet_phy0_default_pins: ethernet-phy0-default-pins { + pinctrl-single,pins = < + /* reset */ + AM64X_IOPAD(0x0154, PIN_OUTPUT, 7) /* PRG1_PRU1_GPO19.GPIO0_84 */ + /* reference clock */ + AM64X_IOPAD(0x0274, PIN_OUTPUT, 5) /* EXT_REFCLK1.CLKOUT0 */ + >; + }; + + ethernet_phy1_default_pins: ethernet-phy1-default-pins { + pinctrl-single,pins = < + /* reset */ + AM64X_IOPAD(0x0150, PIN_OUTPUT, 7) /* PRG1_PRU1_GPO18.GPIO0_20 */ + /* led0, external pull-down on SoM */ + AM64X_IOPAD(0x0128, PIN_INPUT, 7) /* PRG1_PRU1_GPO8.GPIO0_73 */ + /* led1/rxer */ + AM64X_IOPAD(0x011c, PIN_INPUT, 7) /* PRG1_PRU1_GPO5.GPIO0_70 */ + >; + }; + + ethernet_phy2_default_pins: ethernet-phy2-default-pins { + pinctrl-single,pins = < + /* reset */ + AM64X_IOPAD(0x00d4, PIN_OUTPUT, 7) /* PRG1_PRU0_GPO7.GPIO0_52 */ + /* led0, external pull-down on SoM */ + AM64X_IOPAD(0x00d8, PIN_INPUT, 7) /* PRG1_PRU0_GPO8.GPIO0_53 */ + /* led1/rxer */ + AM64X_IOPAD(0x00cc, PIN_INPUT, 7) /* PRG1_PRU0_GPO5.GPIO0_50 */ + >; + }; + + main_i2c0_default_pins: main-i2c0-default-pins { + pinctrl-single,pins = < + /* external pull-up on SoM */ + AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* I2C0_SCL.I2C0_SCL */ + AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* I2C0_SDA.I2C0_SDA */ + >; + }; + + /* + * main_mmc0_default_pins: main-mmc0-default-pins + * + * MMC0_CMD: no padconfig + * MMC0_CLK: no padconfig, external pull-up on SoM + * MMC0_DAT0: no padconfig + * MMC0_DAT1: no padconfig + * MMC0_DAT2: no padconfig + * MMC0_DAT3: no padconfig + * MMC0_DAT4: no padconfig + * MMC0_DAT5: no padconfig + * MMC0_DAT6: no padconfig + * MMC0_DAT7: no padconfig + * MMC0_DS: no padconfig, external pull-down on SoM + */ + + main_mmc1_default_pins: main-mmc1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ + AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* MMC1_CLK.MMC1_CLK */ + AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* MMC1_DAT0.MMC1_DAT0 */ + AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* MMC1_DAT1.MMC1_DAT1 */ + AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* MMC1_DAT2.MMC1_DAT2 */ + AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* MMC1_DAT3.MMC1_DAT3 */ + /* external pull-down on SoM & Carrier */ + AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* MMC1_SDCD.MMC1_SDCD */ + AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB: clock loopback */ + >; + }; + + main_uart0_default_pins: main-uart0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* UART0_RXD.UART0_RXD */ + AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* UART0_TXD.UART0_TXD */ + >; + }; + + mdio0_default_pins: mdio0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* PRG0_PRU1_GPO19.MDIO0_MDC */ + AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* PRG0_PRU1_GPO18.MDIO0_MDIO */ + >; + }; + + ospi0_default_pins: ospi0-default-pins { + pinctrl-single,pins = < + /* external pull-down on SoM */ + AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* OSPI0_CLK.OSPI0_CLK */ + AM64X_IOPAD(0x0008, PIN_OUTPUT, 0) /* OSPI0_DQS.OSPI0_DQS */ + /* external pull-up on SoM */ + AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* OSPI0_CSn0.OSPI0_CSn0 */ + AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* OSPI0_D0.OSPI0_D0 */ + AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* OSPI0_D1.OSPI0_D1 */ + AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* OSPI0_D2.OSPI0_D2 */ + AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* OSPI0_D3.OSPI0_D3 */ + AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* OSPI0_D4.OSPI0_D4 */ + AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* OSPI0_D5.OSPI0_D5 */ + AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* OSPI0_D6.OSPI0_D6 */ + AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* OSPI0_D7.OSPI0_D7 */ + >; + }; + + ospi0_flash0_default_pins: ospi0-flash0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0034, PIN_OUTPUT, 7) /* OSPI0_CSn2.GPIO0_13 */ + AM64X_IOPAD(0x0038, PIN_INPUT, 7) /* OSPI0_CSn3.GPIO0_14 */ + >; + }; + + pru1_mdio0_default_pins: pru1-mdio0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* PRG1_MDIO0_MDC.PRG1_MDIO0_MDC */ + AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* PRG1_MDIO0_MDIO.PRG1_MDIO0_MDIO */ + >; + }; + + pru_rgmii1_default_pins: pru-rgmii1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */ + AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */ + AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */ + AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */ + AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */ + AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */ + AM64X_IOPAD(0x00e4, PIN_OUTPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */ + AM64X_IOPAD(0x00e8, PIN_OUTPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */ + AM64X_IOPAD(0x00ec, PIN_OUTPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */ + AM64X_IOPAD(0x00f0, PIN_OUTPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */ + AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */ + AM64X_IOPAD(0x00f4, PIN_OUTPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */ + >; + }; + + pru_rgmii2_default_pins: pru-rgmii2-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* PRG1_PRU1_GPO0.RGMII2_RD0 */ + AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* PRG1_PRU1_GPO1.RGMII2_RD1 */ + AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* PRG1_PRU1_GPO2.RGMII2_RD2 */ + AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* PRG1_PRU1_GPO3.RGMII2_RD3 */ + AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* PRG1_PRU1_GPO6.RGMII2_RXC */ + AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* PRG1_PRU1_GPO4.RGMII2_RX_CTL */ + AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO11.RGMII2_TD0 */ + AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO12.RGMII2_TD1 */ + AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO13.RGMII2_TD2 */ + AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO14.RGMII2_TD3 */ + AM64X_IOPAD(0x0148, PIN_INPUT, 2) /* PRG1_PRU1_GPO16.RGMII2_TXC */ + AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO15.RGMII2_TX_CTL */ + >; + }; + + rgmii1_default_pins: rgmii1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* PRG0_PRU1_GPO7.RGMII1_RD0 */ + AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* PRG0_PRU1_GPO9.RGMII1_RD1 */ + AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* PRG0_PRU1_GPO10.RGMII1_RD2 */ + AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* PRG0_PRU1_GPO17.RGMII1_RD3 */ + AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* PRG0_PRU0_GPO10.RGMII1_RXC */ + AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* PRG0_PRU0_GPO9.RGMII1_RX_CTL */ + AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO7.RGMII1_TD0 */ + AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO9.RGMII1_TD1 */ + AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO10.RGMII1_TD2 */ + AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO17.RGMII1_TD3 */ + AM64X_IOPAD(0x00e0, PIN_INPUT, 4) /* PRG1_PRU0_GPO10.RGMII1_TXC */ + AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* PRG1_PRU0_GPO9.RGMII1_TX_CTL */ + >; + }; + + usb0_default_pins: usb0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* USB0_DRVVBUS.USB0_DRVVBUS */ + >; + }; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +/* SoC default UART console */ +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_default_pins>; + status = "okay"; +}; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_default_pins>; + num-cs = <1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_flash0_default_pins>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <200000000>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + cdns,read-delay = <0>; + interrupt-parent = <&main_gpio0>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&main_gpio0 13 GPIO_ACTIVE_LOW>; + }; +}; + +&sdhci0 { + /* mmc0 pins have no padconfig */ + bus-width = <8>; + ti,driver-strength-ohm = <50>; + disable-wp; + non-removable; + cap-mmc-hw-reset; + no-sd; + /* + * MMC controller supports switching between 1.8V and 3.3V signalling. + * However MMC0 (unlike MMC1) does not integrate an LDO. + * Explicitly link a regulator node for indicating to the driver which + * voltages are actually usable. + */ + vqmmc-supply = <&vdd_mmc0>; + status = "okay"; +}; + +/* + * microSD is on carrier - however since SoC can boot from it, + * configure it just in case. + */ +&sdhci1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_default_pins>; + bus-width = <4>; + ti,driver-strength-ohm = <50>; + disable-wp; + status = "okay"; +}; + +/* + * USB settings are a carrier choice - however since SoC can boot from it, + * configure as USB-2.0 OTG here, keeping USB-3 serdes disabled. + */ +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_default_pins>; + dr_mode = "otg"; + maximum-speed = "high-speed"; +}; + +&usbss0 { + ti,vbus-divider; + ti,usb2-only; +}; diff --git a/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts index 55102d35cec..1f4dc5ad169 100644 --- a/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts +++ b/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts @@ -422,7 +422,6 @@ cd-gpios = <&main_gpio1 77 GPIO_ACTIVE_LOW>; disable-wp; no-mmc; - ti,driver-strength-ohm = <50>; ti,fails-without-test-cd; /* Enabled by overlay */ }; diff --git a/src/arm64/ti/k3-am642.dtsi b/src/arm64/ti/k3-am642.dtsi index 7a6eedea3aa..8589ee55ef0 100644 --- a/src/arm64/ti/k3-am642.dtsi +++ b/src/arm64/ti/k3-am642.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM642 SoC family in Dual core configuration * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am65-iot2050-arduino-connector.dtsi b/src/arm64/ti/k3-am65-iot2050-arduino-connector.dtsi new file mode 100644 index 00000000000..7ff0abd7c62 --- /dev/null +++ b/src/arm64/ti/k3-am65-iot2050-arduino-connector.dtsi @@ -0,0 +1,768 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Siemens AG, 2018-2023 + * + * Authors: + * Le Jin + * Jan Kiszka + * + * Common bits for IOT2050 variants with Arduino connector + */ + +&wkup_pmx0 { + pinctrl-names = + "default", + "d0-uart0-rxd", "d0-gpio", "d0-gpio-pullup", "d0-gpio-pulldown", + "d1-uart0-txd", "d1-gpio", "d1-gpio-pullup", "d1-gpio-pulldown", + "d2-uart0-ctsn", "d2-gpio", "d2-gpio-pullup", "d2-gpio-pulldown", + "d3-uart0-rtsn", "d3-gpio", "d3-gpio-pullup", "d3-gpio-pulldown", + "d10-spi0-cs0", "d10-gpio", "d10-gpio-pullup", "d10-gpio-pulldown", + "d11-spi0-d0", "d11-gpio", "d11-gpio-pullup", "d11-gpio-pulldown", + "d12-spi0-d1", "d12-gpio", "d12-gpio-pullup", "d12-gpio-pulldown", + "d13-spi0-clk", "d13-gpio", "d13-gpio-pullup", "d13-gpio-pulldown", + "a0-gpio", "a0-gpio-pullup", "a0-gpio-pulldown", + "a1-gpio", "a1-gpio-pullup", "a1-gpio-pulldown", + "a2-gpio", "a2-gpio-pullup", "a2-gpio-pulldown", + "a3-gpio", "a3-gpio-pullup", "a3-gpio-pulldown", + "a4-gpio", "a4-gpio-pullup", "a4-gpio-pulldown", + "a5-gpio", "a5-gpio-pullup", "a5-gpio-pulldown"; + + pinctrl-0 = <&d0_uart0_rxd>; + pinctrl-1 = <&d0_uart0_rxd>; + pinctrl-2 = <&d0_gpio>; + pinctrl-3 = <&d0_gpio_pullup>; + pinctrl-4 = <&d0_gpio_pulldown>; + pinctrl-5 = <&d1_uart0_txd>; + pinctrl-6 = <&d1_gpio>; + pinctrl-7 = <&d1_gpio_pullup>; + pinctrl-8 = <&d1_gpio_pulldown>; + pinctrl-9 = <&d2_uart0_ctsn>; + pinctrl-10 = <&d2_gpio>; + pinctrl-11 = <&d2_gpio_pullup>; + pinctrl-12 = <&d2_gpio_pulldown>; + pinctrl-13 = <&d3_uart0_rtsn>; + pinctrl-14 = <&d3_gpio>; + pinctrl-15 = <&d3_gpio_pullup>; + pinctrl-16 = <&d3_gpio_pulldown>; + pinctrl-17 = <&d10_spi0_cs0>; + pinctrl-18 = <&d10_gpio>; + pinctrl-19 = <&d10_gpio_pullup>; + pinctrl-20 = <&d10_gpio_pulldown>; + pinctrl-21 = <&d11_spi0_d0>; + pinctrl-22 = <&d11_gpio>; + pinctrl-23 = <&d11_gpio_pullup>; + pinctrl-24 = <&d11_gpio_pulldown>; + pinctrl-25 = <&d12_spi0_d1>; + pinctrl-26 = <&d12_gpio>; + pinctrl-27 = <&d12_gpio_pullup>; + pinctrl-28 = <&d12_gpio_pulldown>; + pinctrl-29 = <&d13_spi0_clk>; + pinctrl-30 = <&d13_gpio>; + pinctrl-31 = <&d13_gpio_pullup>; + pinctrl-32 = <&d13_gpio_pulldown>; + pinctrl-33 = <&a0_gpio>; + pinctrl-34 = <&a0_gpio_pullup>; + pinctrl-35 = <&a0_gpio_pulldown>; + pinctrl-36 = <&a1_gpio>; + pinctrl-37 = <&a1_gpio_pullup>; + pinctrl-38 = <&a1_gpio_pulldown>; + pinctrl-39 = <&a2_gpio>; + pinctrl-40 = <&a2_gpio_pullup>; + pinctrl-41 = <&a2_gpio_pulldown>; + pinctrl-42 = <&a3_gpio>; + pinctrl-43 = <&a3_gpio_pullup>; + pinctrl-44 = <&a3_gpio_pulldown>; + pinctrl-45 = <&a4_gpio>; + pinctrl-46 = <&a4_gpio_pullup>; + pinctrl-47 = <&a4_gpio_pulldown>; + pinctrl-48 = <&a5_gpio>; + pinctrl-49 = <&a5_gpio_pullup>; + pinctrl-50 = <&a5_gpio_pulldown>; + + d0_uart0_rxd: d0-uart0-rxd-pins { + pinctrl-single,pins = < + /* (P4) MCU_UART0_RXD */ + AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) + >; + }; + + d0_gpio: d0-gpio-pins { + pinctrl-single,pins = < + /* (P4) WKUP_GPIO0_29 */ + AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 7) + >; + }; + + d0_gpio_pullup: d0-gpio-pullup-pins { + pinctrl-single,pins = < + /* (P4) WKUP_GPIO0_29 */ + AM65X_WKUP_IOPAD(0x0044, PIN_INPUT_PULLUP, 7) + >; + }; + + d0_gpio_pulldown: d0-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (P4) WKUP_GPIO0_29 */ + AM65X_WKUP_IOPAD(0x0044, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d1_uart0_txd: d1-uart0-txd-pins { + pinctrl-single,pins = < + /* (P5) MCU_UART0_TXD */ + AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) + >; + }; + + d1_gpio: d1-gpio-pins { + pinctrl-single,pins = < + /* (P5) WKUP_GPIO0_30 */ + AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7) + >; + }; + + d1_gpio_pullup: d1-gpio-pullup-pins { + pinctrl-single,pins = < + /* (P5) WKUP_GPIO0_30 */ + AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7) + >; + }; + + d1_gpio_pulldown: d1-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (P5) WKUP_GPIO0_30 */ + AM65X_WKUP_IOPAD(0x0048, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d2_uart0_ctsn: d2-uart0-ctsn-pins { + pinctrl-single,pins = < + /* (P1) MCU_UART0_CTSn */ + AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) + >; + }; + + d2_gpio: d2-gpio-pins { + pinctrl-single,pins = < + /* (P5) WKUP_GPIO0_31 */ + AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7) + >; + }; + + d2_gpio_pullup: d2-gpio-pullup-pins { + pinctrl-single,pins = < + /* (P5) WKUP_GPIO0_31 */ + AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7) + >; + }; + + d2_gpio_pulldown: d2-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (P5) WKUP_GPIO0_31 */ + AM65X_WKUP_IOPAD(0x004C, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d3_uart0_rtsn: d3-uart0-rtsn-pins { + pinctrl-single,pins = < + /* (N3) MCU_UART0_RTSn */ + AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) + >; + }; + + d3_gpio: d3-gpio-pins { + pinctrl-single,pins = < + /* (N3) WKUP_GPIO0_33 */ + AM65X_WKUP_IOPAD(0x0054, PIN_INPUT, 7) + >; + }; + + d3_gpio_pullup: d3-gpio-pullup-pins { + pinctrl-single,pins = < + /* (N3) WKUP_GPIO0_33 */ + AM65X_WKUP_IOPAD(0x0054, PIN_INPUT, 7) + >; + }; + + d3_gpio_pulldown: d3-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (N3) WKUP_GPIO0_33 */ + AM65X_WKUP_IOPAD(0x0054, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d10_spi0_cs0: d10-spi0-cs0-pins { + pinctrl-single,pins = < + /* (Y4) MCU_SPI0_CS0 */ + AM65X_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) + >; + }; + + d10_gpio: d10-gpio-pins { + pinctrl-single,pins = < + /* (Y4) WKUP_GPIO0_51 */ + AM65X_WKUP_IOPAD(0x009c, PIN_INPUT, 7) + >; + }; + + d10_gpio_pullup: d10-gpio-pullup-pins { + pinctrl-single,pins = < + /* (Y4) WKUP_GPIO0_51 */ + AM65X_WKUP_IOPAD(0x009c, PIN_INPUT, 7) + >; + }; + + d10_gpio_pulldown: d10-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (Y4) WKUP_GPIO0_51 */ + AM65X_WKUP_IOPAD(0x009c, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d11_spi0_d0: d11-spi0-d0-pins { + pinctrl-single,pins = < + /* (Y3) MCU_SPI0_D0 */ + AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 0) + >; + }; + + d11_gpio: d11-gpio-pins { + pinctrl-single,pins = < + /* (Y3) WKUP_GPIO0_49 */ + AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 7) + >; + }; + + d11_gpio_pullup: d11-gpio-pullup-pins { + pinctrl-single,pins = < + /* (Y3) WKUP_GPIO0_49 */ + AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 7) + >; + }; + + d11_gpio_pulldown: d11-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (Y3) WKUP_GPIO0_49 */ + AM65X_WKUP_IOPAD(0x0094, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d12_spi0_d1: d12-spi0-d1-pins { + pinctrl-single,pins = < + /* (Y2) MCU_SPI0_D1 */ + AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 0) + >; + }; + + d12_gpio: d12-gpio-pins { + pinctrl-single,pins = < + /* (Y2) WKUP_GPIO0_50 */ + AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 7) + >; + }; + + d12_gpio_pullup: d12-gpio-pullup-pins { + pinctrl-single,pins = < + /* (Y2) WKUP_GPIO0_50 */ + AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 7) + >; + }; + + d12_gpio_pulldown: d12-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (Y2) WKUP_GPIO0_50 */ + AM65X_WKUP_IOPAD(0x0098, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d13_spi0_clk: d13-spi0-clk-pins { + pinctrl-single,pins = < + /* (Y1) MCU_SPI0_CLK */ + AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0) + >; + }; + + d13_gpio: d13-gpio-pins { + pinctrl-single,pins = < + /* (Y1) WKUP_GPIO0_48 */ + AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 7) + >; + }; + + d13_gpio_pullup: d13-gpio-pullup-pins { + pinctrl-single,pins = < + /* (Y1) WKUP_GPIO0_48 */ + AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 7) + >; + }; + + d13_gpio_pulldown: d13-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (Y1) WKUP_GPIO0_48 */ + AM65X_WKUP_IOPAD(0x0090, PIN_INPUT_PULLDOWN, 7) + >; + }; + + a0_gpio: a0-gpio-pins { + pinctrl-single,pins = < + /* (L6) WKUP_GPIO0_45 */ + AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 7) + >; + }; + + a0_gpio_pullup: a0-gpio-pullup-pins { + pinctrl-single,pins = < + /* (L6) WKUP_GPIO0_45 */ + AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 7) + >; + }; + + a0_gpio_pulldown: a0-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (L6) WKUP_GPIO0_45 */ + AM65X_WKUP_IOPAD(0x0084, PIN_INPUT_PULLDOWN, 7) + >; + }; + + a1_gpio: a1-gpio-pins { + pinctrl-single,pins = < + /* (M6) WKUP_GPIO0_44 */ + AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 7) + >; + }; + + a1_gpio_pullup: a1-gpio-pullup-pins { + pinctrl-single,pins = < + /* (M6) WKUP_GPIO0_44 */ + AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 7) + >; + }; + + a1_gpio_pulldown: a1-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (M6) WKUP_GPIO0_44 */ + AM65X_WKUP_IOPAD(0x0080, PIN_INPUT_PULLDOWN, 7) + >; + }; + + a2_gpio: a2-gpio-pins { + pinctrl-single,pins = < + /* (L5) WKUP_GPIO0_43 */ + AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7) + >; + }; + + a2_gpio_pullup: a2-gpio-pullup-pins { + pinctrl-single,pins = < + /* (L5) WKUP_GPIO0_43 */ + AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7) + >; + }; + + a2_gpio_pulldown: a2-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (L5) WKUP_GPIO0_43 */ + AM65X_WKUP_IOPAD(0x007C, PIN_INPUT_PULLDOWN, 7) + >; + }; + + a3_gpio: a3-gpio-pins { + pinctrl-single,pins = < + /* (M5) WKUP_GPIO0_39 */ + AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7) + >; + }; + + a3_gpio_pullup: a3-gpio-pullup-pins { + pinctrl-single,pins = < + /* (M5) WKUP_GPIO0_39 */ + AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7) + >; + }; + + a3_gpio_pulldown: a3-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (M5) WKUP_GPIO0_39 */ + AM65X_WKUP_IOPAD(0x006C, PIN_INPUT_PULLDOWN, 7) + >; + }; + + a4_gpio: a4-gpio-pins { + pinctrl-single,pins = < + /* (L2) WKUP_GPIO0_42 */ + AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 7) + >; + }; + + a4_gpio_pullup: a4-gpio-pullup-pins { + pinctrl-single,pins = < + /* (L2) WKUP_GPIO0_42 */ + AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 7) + >; + }; + + a4_gpio_pulldown: a4-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (L2) WKUP_GPIO0_42 */ + AM65X_WKUP_IOPAD(0x0078, PIN_INPUT_PULLDOWN, 7) + >; + }; + + a5_gpio: a5-gpio-pins { + pinctrl-single,pins = < + /* (N5) WKUP_GPIO0_35 */ + AM65X_WKUP_IOPAD(0x005C, PIN_INPUT, 7) + >; + }; + + a5_gpio_pullup: a5-gpio-pullup-pins { + pinctrl-single,pins = < + /* (N5) WKUP_GPIO0_35 */ + AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLUP, 7) + >; + }; + + a5_gpio_pulldown: a5-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (N5) WKUP_GPIO0_35 */ + AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLDOWN, 7) + >; + }; + + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins = < + /* (AC7) WKUP_I2C0_SCL */ + AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) + /* (AD6) WKUP_I2C0_SDA */ + AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) + >; + }; + + arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-default-pins { + pinctrl-single,pins = < + /* (R2) WKUP_GPIO0_21 */ + AM65X_WKUP_IOPAD(0x0024, PIN_OUTPUT, 7) + >; + }; + + arduino_io_oe_pins_default: arduino-io-oe-default-pins { + pinctrl-single,pins = < + /* (N4) WKUP_GPIO0_34 */ + AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 7) + /* (M2) WKUP_GPIO0_36 */ + AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 7) + /* (M3) WKUP_GPIO0_37 */ + AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 7) + /* (M4) WKUP_GPIO0_38 */ + AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 7) + /* (M1) WKUP_GPIO0_41 */ + AM65X_WKUP_IOPAD(0x0074, PIN_OUTPUT, 7) + >; + }; +}; + +&main_pmx0 { + pinctrl-names = + "default", + "d4-ehrpwm0-a", "d4-gpio", "d4-gpio-pullup", "d4-gpio-pulldown", + "d5-ehrpwm1-a", "d5-gpio", "d5-gpio-pullup", "d5-gpio-pulldown", + "d6-ehrpwm2-a", "d6-gpio", "d6-gpio-pullup", "d6-gpio-pulldown", + "d7-ehrpwm3-a", "d7-gpio", "d7-gpio-pullup", "d7-gpio-pulldown", + "d8-ehrpwm4-a", "d8-gpio", "d8-gpio-pullup", "d8-gpio-pulldown", + "d9-ehrpwm5-a", "d9-gpio", "d9-gpio-pullup", "d9-gpio-pulldown"; + + pinctrl-0 = <&d4_ehrpwm0_a>; + pinctrl-1 = <&d4_ehrpwm0_a>; + pinctrl-2 = <&d4_gpio>; + pinctrl-3 = <&d4_gpio_pullup>; + pinctrl-4 = <&d4_gpio_pulldown>; + + pinctrl-5 = <&d5_ehrpwm1_a>; + pinctrl-6 = <&d5_gpio>; + pinctrl-7 = <&d5_gpio_pullup>; + pinctrl-8 = <&d5_gpio_pulldown>; + + pinctrl-9 = <&d6_ehrpwm2_a>; + pinctrl-10 = <&d6_gpio>; + pinctrl-11 = <&d6_gpio_pullup>; + pinctrl-12 = <&d6_gpio_pulldown>; + + pinctrl-13 = <&d7_ehrpwm3_a>; + pinctrl-14 = <&d7_gpio>; + pinctrl-15 = <&d7_gpio_pullup>; + pinctrl-16 = <&d7_gpio_pulldown>; + + pinctrl-17 = <&d8_ehrpwm4_a>; + pinctrl-18 = <&d8_gpio>; + pinctrl-19 = <&d8_gpio_pullup>; + pinctrl-20 = <&d8_gpio_pulldown>; + + pinctrl-21 = <&d9_ehrpwm5_a>; + pinctrl-22 = <&d9_gpio>; + pinctrl-23 = <&d9_gpio_pullup>; + pinctrl-24 = <&d9_gpio_pulldown>; + + d4_ehrpwm0_a: d4-ehrpwm0-a-pins { + pinctrl-single,pins = < + /* (AG18) EHRPWM0_A */ + AM65X_IOPAD(0x0084, PIN_OUTPUT, 5) + >; + }; + + d4_gpio: d4-gpio-pins { + pinctrl-single,pins = < + /* (AG18) GPIO0_33 */ + AM65X_IOPAD(0x0084, PIN_INPUT, 7) + >; + }; + + d4_gpio_pullup: d4-gpio-pullup-pins { + pinctrl-single,pins = < + /* (AG18) GPIO0_33 */ + AM65X_IOPAD(0x0084, PIN_INPUT_PULLUP, 7) + >; + }; + + d4_gpio_pulldown: d4-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (AG18) GPIO0_33 */ + AM65X_IOPAD(0x0084, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d5_ehrpwm1_a: d5-ehrpwm1-a-pins { + pinctrl-single,pins = < + /* (AF17) EHRPWM1_A */ + AM65X_IOPAD(0x008C, PIN_OUTPUT, 5) + >; + }; + + d5_gpio: d5-gpio-pins { + pinctrl-single,pins = < + /* (AF17) GPIO0_35 */ + AM65X_IOPAD(0x008C, PIN_INPUT, 7) + >; + }; + + d5_gpio_pullup: d5-gpio-pullup-pins { + pinctrl-single,pins = < + /* (AF17) GPIO0_35 */ + AM65X_IOPAD(0x008C, PIN_INPUT_PULLUP, 7) + >; + }; + + d5_gpio_pulldown: d5-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (AF17) GPIO0_35 */ + AM65X_IOPAD(0x008C, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d6_ehrpwm2_a: d6-ehrpwm2-a-pins { + pinctrl-single,pins = < + /* (AH16) EHRPWM2_A */ + AM65X_IOPAD(0x0098, PIN_OUTPUT, 5) + >; + }; + + d6_gpio: d6-gpio-pins { + pinctrl-single,pins = < + /* (AH16) GPIO0_38 */ + AM65X_IOPAD(0x0098, PIN_INPUT, 7) + >; + }; + + d6_gpio_pullup: d6-gpio-pullup-pins { + pinctrl-single,pins = < + /* (AH16) GPIO0_38 */ + AM65X_IOPAD(0x0098, PIN_INPUT_PULLUP, 7) + >; + }; + + d6_gpio_pulldown: d6-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (AH16) GPIO0_38 */ + AM65X_IOPAD(0x0098, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d7_ehrpwm3_a: d7-ehrpwm3-a-pins { + pinctrl-single,pins = < + /* (AH15) EHRPWM3_A */ + AM65X_IOPAD(0x00AC, PIN_OUTPUT, 5) + >; + }; + + d7_gpio: d7-gpio-pins { + pinctrl-single,pins = < + /* (AH15) GPIO0_43 */ + AM65X_IOPAD(0x00AC, PIN_INPUT, 7) + >; + }; + + d7_gpio_pullup: d7-gpio-pullup-pins { + pinctrl-single,pins = < + /* (AH15) GPIO0_43 */ + AM65X_IOPAD(0x00AC, PIN_INPUT_PULLUP, 7) + >; + }; + + d7_gpio_pulldown: d7-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (AH15) GPIO0_43 */ + AM65X_IOPAD(0x00AC, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d8_ehrpwm4_a: d8-ehrpwm4-a-pins { + pinctrl-single,pins = < + /* (AG15) EHRPWM4_A */ + AM65X_IOPAD(0x00C0, PIN_OUTPUT, 5) + >; + }; + + d8_gpio: d8-gpio-pins { + pinctrl-single,pins = < + /* (AG15) GPIO0_48 */ + AM65X_IOPAD(0x00C0, PIN_INPUT, 7) + >; + }; + + d8_gpio_pullup: d8-gpio-pullup-pins { + pinctrl-single,pins = < + /* (AG15) GPIO0_48 */ + AM65X_IOPAD(0x00C0, PIN_INPUT_PULLUP, 7) + >; + }; + + d8_gpio_pulldown: d8-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (AG15) GPIO0_48 */ + AM65X_IOPAD(0x00C0, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d9_ehrpwm5_a: d9-ehrpwm5-a-pins { + pinctrl-single,pins = < + /* (AD15) EHRPWM5_A */ + AM65X_IOPAD(0x00CC, PIN_OUTPUT, 5) + >; + }; + + d9_gpio: d9-gpio-pins { + pinctrl-single,pins = < + /* (AD15) GPIO0_51 */ + AM65X_IOPAD(0x00CC, PIN_INPUT, 7) + >; + }; + + d9_gpio_pullup: d9-gpio-pullup-pins { + pinctrl-single,pins = < + /* (AD15) GPIO0_51 */ + AM65X_IOPAD(0x00CC, PIN_INPUT_PULLUP, 7) + >; + }; + + d9_gpio_pulldown: d9-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (AD15) GPIO0_51 */ + AM65X_IOPAD(0x00CC, PIN_INPUT_PULLDOWN, 7) + >; + }; +}; + +&main_gpio0 { + gpio-line-names = + "main_gpio0-base", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "IO4", "", "IO5", "", "", "IO6", "", + "", "", "", "IO7", "", "", "", "", "IO8", "", + "", "IO9"; +}; + +&wkup_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = + <&arduino_i2c_aio_switch_pins_default>, + <&arduino_io_oe_pins_default>, + <&push_button_pins_default>, + <&db9_com_mode_pins_default>; + gpio-line-names = + /* 0..9 */ + "wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0", + "UART0-enable", "UART0-terminate", "", "WIFI-disable", + /* 10..19 */ + "", "", "", "", "", "", "", "", "", "", + /* 20..29 */ + "", "A4A5-I2C-mux", "", "", "", "USER-button", "", "", "","IO0", + /* 30..39 */ + "IO1", "IO2", "", "IO3", "IO17-direction", "A5", + "IO16-direction", "IO15-direction", "IO14-direction", "A3", + /* 40..49 */ + "", "IO18-direction", "A4", "A2", "A1", "A0", "", "", "IO13", + "IO11", + /* 50..51 */ + "IO12", "IO10"; +}; + +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; +}; + +&mcu_i2c0 { + /* D4200 */ + pcal9535_1: gpio@20 { + compatible = "nxp,pcal9535"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "A0-pull", "A1-pull", "A2-pull", "A3-pull", "A4-pull", + "A5-pull", "", "", + "IO14-enable", "IO15-enable", "IO16-enable", + "IO17-enable", "IO18-enable", "IO19-enable"; + }; + + /* D4201 */ + pcal9535_2: gpio@21 { + compatible = "nxp,pcal9535"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "IO0-direction", "IO1-direction", "IO2-direction", + "IO3-direction", "IO4-direction", "IO5-direction", + "IO6-direction", "IO7-direction", + "IO8-direction", "IO9-direction", "IO10-direction", + "IO11-direction", "IO12-direction", "IO13-direction", + "IO19-direction"; + }; + + /* D4202 */ + pcal9535_3: gpio@25 { + compatible = "nxp,pcal9535"; + reg = <0x25>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "IO0-pull", "IO1-pull", "IO2-pull", "IO3-pull", + "IO4-pull", "IO5-pull", "IO6-pull", "IO7-pull", + "IO8-pull", "IO9-pull", "IO10-pull", "IO11-pull", + "IO12-pull", "IO13-pull"; + }; +}; + +&mcu_uart0 { + status = "okay"; +}; + +&tscadc1 { + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5>; + }; +}; diff --git a/src/arm64/ti/k3-am65-iot2050-common-pg1.dtsi b/src/arm64/ti/k3-am65-iot2050-common-pg1.dtsi index 1d197985958..c50a585dd63 100644 --- a/src/arm64/ti/k3-am65-iot2050-common-pg1.dtsi +++ b/src/arm64/ti/k3-am65-iot2050-common-pg1.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) Siemens AG, 2021-2023 * @@ -8,10 +8,7 @@ * Common bits of the IOT2050 Basic and Advanced variants, PG1 */ -&dss { - assigned-clocks = <&k3_clks 67 2>; - assigned-clock-parents = <&k3_clks 67 5>; -}; +#include "k3-am65-iot2050-dp.dtsi" &serdes0 { status = "disabled"; diff --git a/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi b/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi index e9b57b87e42..e2584a5efe3 100644 --- a/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi +++ b/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) Siemens AG, 2021 + * Copyright (c) Siemens AG, 2021-2023 * * Authors: * Chao Zeng @@ -9,6 +9,11 @@ * Common bits of the IOT2050 Basic and Advanced variants, PG2 */ +&mcu_r5fss0 { + /* lock-step mode not supported on PG2 boards */ + ti,cluster-mode = <0>; +}; + &main_pmx0 { cp2102n_reset_pin_default: cp2102n-reset-default-pins { pinctrl-single,pins = < @@ -33,21 +38,3 @@ /* Workaround needed to get DP clock of 154Mhz */ assigned-clocks = <&k3_clks 67 0>; }; - -&serdes0 { - assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; - assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>; -}; - -&dwc3_0 { - assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ - <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */ - phys = <&serdes0 PHY_TYPE_USB3 0>; - phy-names = "usb3-phy"; -}; - -&usb0 { - maximum-speed = "super-speed"; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; -}; diff --git a/src/arm64/ti/k3-am65-iot2050-common.dtsi b/src/arm64/ti/k3-am65-iot2050-common.dtsi index 61a634afaa4..ef34b851e17 100644 --- a/src/arm64/ti/k3-am65-iot2050-common.dtsi +++ b/src/arm64/ti/k3-am65-iot2050-common.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) Siemens AG, 2018-2021 + * Copyright (c) Siemens AG, 2018-2024 * * Authors: * Le Jin @@ -9,6 +9,7 @@ * Common bits of the IOT2050 Basic and Advanced variants, PG1 and PG2 */ +#include #include #include @@ -75,6 +76,12 @@ alignment = <0x1000>; no-map; }; + + /* To reserve the power-on(PON) reason for watchdog reset */ + wdt_reset_memory_region: wdt-memory@a2200000 { + reg = <0x00 0xa2200000 0x00 0x1000>; + no-map; + }; }; leds { @@ -82,28 +89,46 @@ pinctrl-names = "default"; pinctrl-0 = <&leds_pins_default>; - status-led-red { + led-0 { + color = ; + function = LED_FUNCTION_STATUS; + label = "status-led-red"; gpios = <&wkup_gpio0 32 GPIO_ACTIVE_HIGH>; panic-indicator; }; - status-led-green { + led-1 { + color = ; + function = LED_FUNCTION_STATUS; + label = "status-led-green"; gpios = <&wkup_gpio0 24 GPIO_ACTIVE_HIGH>; }; - user-led1-red { + led-2 { + color = ; + function = LED_FUNCTION_INDICATOR; + label = "user-led1-red"; gpios = <&pcal9535_3 14 GPIO_ACTIVE_HIGH>; }; - user-led1-green { + led-3 { + color = ; + function = LED_FUNCTION_INDICATOR; + label = "user-led1-green"; gpios = <&pcal9535_2 15 GPIO_ACTIVE_HIGH>; }; - user-led2-red { + led-4 { + color = ; + function = LED_FUNCTION_INDICATOR; + label = "user-led2-red"; gpios = <&wkup_gpio0 17 GPIO_ACTIVE_HIGH>; }; - user-led2-green { + led-5 { + color = ; + function = LED_FUNCTION_INDICATOR; + label = "user-led2-green"; gpios = <&wkup_gpio0 22 GPIO_ACTIVE_HIGH>; }; }; @@ -186,434 +211,6 @@ }; &wkup_pmx0 { - pinctrl-names = - "default", - "d0-uart0-rxd", "d0-gpio", "d0-gpio-pullup", "d0-gpio-pulldown", - "d1-uart0-txd", "d1-gpio", "d1-gpio-pullup", "d1-gpio-pulldown", - "d2-uart0-ctsn", "d2-gpio", "d2-gpio-pullup", "d2-gpio-pulldown", - "d3-uart0-rtsn", "d3-gpio", "d3-gpio-pullup", "d3-gpio-pulldown", - "d10-spi0-cs0", "d10-gpio", "d10-gpio-pullup", "d10-gpio-pulldown", - "d11-spi0-d0", "d11-gpio", "d11-gpio-pullup", "d11-gpio-pulldown", - "d12-spi0-d1", "d12-gpio", "d12-gpio-pullup", "d12-gpio-pulldown", - "d13-spi0-clk", "d13-gpio", "d13-gpio-pullup", "d13-gpio-pulldown", - "a0-gpio", "a0-gpio-pullup", "a0-gpio-pulldown", - "a1-gpio", "a1-gpio-pullup", "a1-gpio-pulldown", - "a2-gpio", "a2-gpio-pullup", "a2-gpio-pulldown", - "a3-gpio", "a3-gpio-pullup", "a3-gpio-pulldown", - "a4-gpio", "a4-gpio-pullup", "a4-gpio-pulldown", - "a5-gpio", "a5-gpio-pullup", "a5-gpio-pulldown"; - - pinctrl-0 = <&d0_uart0_rxd>; - pinctrl-1 = <&d0_uart0_rxd>; - pinctrl-2 = <&d0_gpio>; - pinctrl-3 = <&d0_gpio_pullup>; - pinctrl-4 = <&d0_gpio_pulldown>; - pinctrl-5 = <&d1_uart0_txd>; - pinctrl-6 = <&d1_gpio>; - pinctrl-7 = <&d1_gpio_pullup>; - pinctrl-8 = <&d1_gpio_pulldown>; - pinctrl-9 = <&d2_uart0_ctsn>; - pinctrl-10 = <&d2_gpio>; - pinctrl-11 = <&d2_gpio_pullup>; - pinctrl-12 = <&d2_gpio_pulldown>; - pinctrl-13 = <&d3_uart0_rtsn>; - pinctrl-14 = <&d3_gpio>; - pinctrl-15 = <&d3_gpio_pullup>; - pinctrl-16 = <&d3_gpio_pulldown>; - pinctrl-17 = <&d10_spi0_cs0>; - pinctrl-18 = <&d10_gpio>; - pinctrl-19 = <&d10_gpio_pullup>; - pinctrl-20 = <&d10_gpio_pulldown>; - pinctrl-21 = <&d11_spi0_d0>; - pinctrl-22 = <&d11_gpio>; - pinctrl-23 = <&d11_gpio_pullup>; - pinctrl-24 = <&d11_gpio_pulldown>; - pinctrl-25 = <&d12_spi0_d1>; - pinctrl-26 = <&d12_gpio>; - pinctrl-27 = <&d12_gpio_pullup>; - pinctrl-28 = <&d12_gpio_pulldown>; - pinctrl-29 = <&d13_spi0_clk>; - pinctrl-30 = <&d13_gpio>; - pinctrl-31 = <&d13_gpio_pullup>; - pinctrl-32 = <&d13_gpio_pulldown>; - pinctrl-33 = <&a0_gpio>; - pinctrl-34 = <&a0_gpio_pullup>; - pinctrl-35 = <&a0_gpio_pulldown>; - pinctrl-36 = <&a1_gpio>; - pinctrl-37 = <&a1_gpio_pullup>; - pinctrl-38 = <&a1_gpio_pulldown>; - pinctrl-39 = <&a2_gpio>; - pinctrl-40 = <&a2_gpio_pullup>; - pinctrl-41 = <&a2_gpio_pulldown>; - pinctrl-42 = <&a3_gpio>; - pinctrl-43 = <&a3_gpio_pullup>; - pinctrl-44 = <&a3_gpio_pulldown>; - pinctrl-45 = <&a4_gpio>; - pinctrl-46 = <&a4_gpio_pullup>; - pinctrl-47 = <&a4_gpio_pulldown>; - pinctrl-48 = <&a5_gpio>; - pinctrl-49 = <&a5_gpio_pullup>; - pinctrl-50 = <&a5_gpio_pulldown>; - - d0_uart0_rxd: d0-uart0-rxd-pins { - pinctrl-single,pins = < - /* (P4) MCU_UART0_RXD */ - AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) - >; - }; - - d0_gpio: d0-gpio-pins { - pinctrl-single,pins = < - /* (P4) WKUP_GPIO0_29 */ - AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 7) - >; - }; - - d0_gpio_pullup: d0-gpio-pullup-pins { - pinctrl-single,pins = < - /* (P4) WKUP_GPIO0_29 */ - AM65X_WKUP_IOPAD(0x0044, PIN_INPUT_PULLUP, 7) - >; - }; - - d0_gpio_pulldown: d0-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (P4) WKUP_GPIO0_29 */ - AM65X_WKUP_IOPAD(0x0044, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d1_uart0_txd: d1-uart0-txd-pins { - pinctrl-single,pins = < - /* (P5) MCU_UART0_TXD */ - AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) - >; - }; - - d1_gpio: d1-gpio-pins { - pinctrl-single,pins = < - /* (P5) WKUP_GPIO0_30 */ - AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7) - >; - }; - - d1_gpio_pullup: d1-gpio-pullup-pins { - pinctrl-single,pins = < - /* (P5) WKUP_GPIO0_30 */ - AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7) - >; - }; - - d1_gpio_pulldown: d1-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (P5) WKUP_GPIO0_30 */ - AM65X_WKUP_IOPAD(0x0048, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d2_uart0_ctsn: d2-uart0-ctsn-pins { - pinctrl-single,pins = < - /* (P1) MCU_UART0_CTSn */ - AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) - >; - }; - - d2_gpio: d2-gpio-pins { - pinctrl-single,pins = < - /* (P5) WKUP_GPIO0_31 */ - AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7) - >; - }; - - d2_gpio_pullup: d2-gpio-pullup-pins { - pinctrl-single,pins = < - /* (P5) WKUP_GPIO0_31 */ - AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7) - >; - }; - - d2_gpio_pulldown: d2-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (P5) WKUP_GPIO0_31 */ - AM65X_WKUP_IOPAD(0x004C, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d3_uart0_rtsn: d3-uart0-rtsn-pins { - pinctrl-single,pins = < - /* (N3) MCU_UART0_RTSn */ - AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) - >; - }; - - d3_gpio: d3-gpio-pins { - pinctrl-single,pins = < - /* (N3) WKUP_GPIO0_33 */ - AM65X_WKUP_IOPAD(0x0054, PIN_INPUT, 7) - >; - }; - - d3_gpio_pullup: d3-gpio-pullup-pins { - pinctrl-single,pins = < - /* (N3) WKUP_GPIO0_33 */ - AM65X_WKUP_IOPAD(0x0054, PIN_INPUT, 7) - >; - }; - - d3_gpio_pulldown: d3-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (N3) WKUP_GPIO0_33 */ - AM65X_WKUP_IOPAD(0x0054, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d10_spi0_cs0: d10-spi0-cs0-pins { - pinctrl-single,pins = < - /* (Y4) MCU_SPI0_CS0 */ - AM65X_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) - >; - }; - - d10_gpio: d10-gpio-pins { - pinctrl-single,pins = < - /* (Y4) WKUP_GPIO0_51 */ - AM65X_WKUP_IOPAD(0x009c, PIN_INPUT, 7) - >; - }; - - d10_gpio_pullup: d10-gpio-pullup-pins { - pinctrl-single,pins = < - /* (Y4) WKUP_GPIO0_51 */ - AM65X_WKUP_IOPAD(0x009c, PIN_INPUT, 7) - >; - }; - - d10_gpio_pulldown: d10-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (Y4) WKUP_GPIO0_51 */ - AM65X_WKUP_IOPAD(0x009c, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d11_spi0_d0: d11-spi0-d0-pins { - pinctrl-single,pins = < - /* (Y3) MCU_SPI0_D0 */ - AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 0) - >; - }; - - d11_gpio: d11-gpio-pins { - pinctrl-single,pins = < - /* (Y3) WKUP_GPIO0_49 */ - AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 7) - >; - }; - - d11_gpio_pullup: d11-gpio-pullup-pins { - pinctrl-single,pins = < - /* (Y3) WKUP_GPIO0_49 */ - AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 7) - >; - }; - - d11_gpio_pulldown: d11-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (Y3) WKUP_GPIO0_49 */ - AM65X_WKUP_IOPAD(0x0094, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d12_spi0_d1: d12-spi0-d1-pins { - pinctrl-single,pins = < - /* (Y2) MCU_SPI0_D1 */ - AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 0) - >; - }; - - d12_gpio: d12-gpio-pins { - pinctrl-single,pins = < - /* (Y2) WKUP_GPIO0_50 */ - AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 7) - >; - }; - - d12_gpio_pullup: d12-gpio-pullup-pins { - pinctrl-single,pins = < - /* (Y2) WKUP_GPIO0_50 */ - AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 7) - >; - }; - - d12_gpio_pulldown: d12-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (Y2) WKUP_GPIO0_50 */ - AM65X_WKUP_IOPAD(0x0098, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d13_spi0_clk: d13-spi0-clk-pins { - pinctrl-single,pins = < - /* (Y1) MCU_SPI0_CLK */ - AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0) - >; - }; - - d13_gpio: d13-gpio-pins { - pinctrl-single,pins = < - /* (Y1) WKUP_GPIO0_48 */ - AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 7) - >; - }; - - d13_gpio_pullup: d13-gpio-pullup-pins { - pinctrl-single,pins = < - /* (Y1) WKUP_GPIO0_48 */ - AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 7) - >; - }; - - d13_gpio_pulldown: d13-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (Y1) WKUP_GPIO0_48 */ - AM65X_WKUP_IOPAD(0x0090, PIN_INPUT_PULLDOWN, 7) - >; - }; - - a0_gpio: a0-gpio-pins { - pinctrl-single,pins = < - /* (L6) WKUP_GPIO0_45 */ - AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 7) - >; - }; - - a0_gpio_pullup: a0-gpio-pullup-pins { - pinctrl-single,pins = < - /* (L6) WKUP_GPIO0_45 */ - AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 7) - >; - }; - - a0_gpio_pulldown: a0-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (L6) WKUP_GPIO0_45 */ - AM65X_WKUP_IOPAD(0x0084, PIN_INPUT_PULLDOWN, 7) - >; - }; - - a1_gpio: a1-gpio-pins { - pinctrl-single,pins = < - /* (M6) WKUP_GPIO0_44 */ - AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 7) - >; - }; - - a1_gpio_pullup: a1-gpio-pullup-pins { - pinctrl-single,pins = < - /* (M6) WKUP_GPIO0_44 */ - AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 7) - >; - }; - - a1_gpio_pulldown: a1-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (M6) WKUP_GPIO0_44 */ - AM65X_WKUP_IOPAD(0x0080, PIN_INPUT_PULLDOWN, 7) - >; - }; - - a2_gpio: a2-gpio-pins { - pinctrl-single,pins = < - /* (L5) WKUP_GPIO0_43 */ - AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7) - >; - }; - - a2_gpio_pullup: a2-gpio-pullup-pins { - pinctrl-single,pins = < - /* (L5) WKUP_GPIO0_43 */ - AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7) - >; - }; - - a2_gpio_pulldown: a2-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (L5) WKUP_GPIO0_43 */ - AM65X_WKUP_IOPAD(0x007C, PIN_INPUT_PULLDOWN, 7) - >; - }; - - a3_gpio: a3-gpio-pins { - pinctrl-single,pins = < - /* (M5) WKUP_GPIO0_39 */ - AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7) - >; - }; - - a3_gpio_pullup: a3-gpio-pullup-pins { - pinctrl-single,pins = < - /* (M5) WKUP_GPIO0_39 */ - AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7) - >; - }; - - a3_gpio_pulldown: a3-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (M5) WKUP_GPIO0_39 */ - AM65X_WKUP_IOPAD(0x006C, PIN_INPUT_PULLDOWN, 7) - >; - }; - - a4_gpio: a4-gpio-pins { - pinctrl-single,pins = < - /* (L2) WKUP_GPIO0_42 */ - AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 7) - >; - }; - - a4_gpio_pullup: a4-gpio-pullup-pins { - pinctrl-single,pins = < - /* (L2) WKUP_GPIO0_42 */ - AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 7) - >; - }; - - a4_gpio_pulldown: a4-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (L2) WKUP_GPIO0_42 */ - AM65X_WKUP_IOPAD(0x0078, PIN_INPUT_PULLDOWN, 7) - >; - }; - - a5_gpio: a5-gpio-pins { - pinctrl-single,pins = < - /* (N5) WKUP_GPIO0_35 */ - AM65X_WKUP_IOPAD(0x005C, PIN_INPUT, 7) - >; - }; - - a5_gpio_pullup: a5-gpio-pullup-pins { - pinctrl-single,pins = < - /* (N5) WKUP_GPIO0_35 */ - AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLUP, 7) - >; - }; - - a5_gpio_pulldown: a5-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (N5) WKUP_GPIO0_35 */ - AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLDOWN, 7) - >; - }; - - wkup_i2c0_pins_default: wkup-i2c0-default-pins { - pinctrl-single,pins = < - /* (AC7) WKUP_I2C0_SCL */ - AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) - /* (AD6) WKUP_I2C0_SDA */ - AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) - >; - }; - mcu_i2c0_pins_default: mcu-i2c0-default-pins { pinctrl-single,pins = < /* (AD8) MCU_I2C0_SCL */ @@ -623,13 +220,6 @@ >; }; - arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-default-pins { - pinctrl-single,pins = < - /* (R2) WKUP_GPIO0_21 */ - AM65X_WKUP_IOPAD(0x0024, PIN_OUTPUT, 7) - >; - }; - push_button_pins_default: push-button-default-pins { pinctrl-single,pins = < /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */ @@ -637,22 +227,6 @@ >; }; - - arduino_io_oe_pins_default: arduino-io-oe-default-pins { - pinctrl-single,pins = < - /* (N4) WKUP_GPIO0_34 */ - AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 7) - /* (M2) WKUP_GPIO0_36 */ - AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 7) - /* (M3) WKUP_GPIO0_37 */ - AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 7) - /* (M4) WKUP_GPIO0_38 */ - AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 7) - /* (M1) WKUP_GPIO0_41 */ - AM65X_WKUP_IOPAD(0x0074, PIN_OUTPUT, 7) - >; - }; - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins = < /* (V1) MCU_OSPI0_CLK */ @@ -716,214 +290,6 @@ }; &main_pmx0 { - pinctrl-names = - "default", - "d4-ehrpwm0-a", "d4-gpio", "d4-gpio-pullup", "d4-gpio-pulldown", - "d5-ehrpwm1-a", "d5-gpio", "d5-gpio-pullup", "d5-gpio-pulldown", - "d6-ehrpwm2-a", "d6-gpio", "d6-gpio-pullup", "d6-gpio-pulldown", - "d7-ehrpwm3-a", "d7-gpio", "d7-gpio-pullup", "d7-gpio-pulldown", - "d8-ehrpwm4-a", "d8-gpio", "d8-gpio-pullup", "d8-gpio-pulldown", - "d9-ehrpwm5-a", "d9-gpio", "d9-gpio-pullup", "d9-gpio-pulldown"; - - pinctrl-0 = <&d4_ehrpwm0_a>; - pinctrl-1 = <&d4_ehrpwm0_a>; - pinctrl-2 = <&d4_gpio>; - pinctrl-3 = <&d4_gpio_pullup>; - pinctrl-4 = <&d4_gpio_pulldown>; - - pinctrl-5 = <&d5_ehrpwm1_a>; - pinctrl-6 = <&d5_gpio>; - pinctrl-7 = <&d5_gpio_pullup>; - pinctrl-8 = <&d5_gpio_pulldown>; - - pinctrl-9 = <&d6_ehrpwm2_a>; - pinctrl-10 = <&d6_gpio>; - pinctrl-11 = <&d6_gpio_pullup>; - pinctrl-12 = <&d6_gpio_pulldown>; - - pinctrl-13 = <&d7_ehrpwm3_a>; - pinctrl-14 = <&d7_gpio>; - pinctrl-15 = <&d7_gpio_pullup>; - pinctrl-16 = <&d7_gpio_pulldown>; - - pinctrl-17 = <&d8_ehrpwm4_a>; - pinctrl-18 = <&d8_gpio>; - pinctrl-19 = <&d8_gpio_pullup>; - pinctrl-20 = <&d8_gpio_pulldown>; - - pinctrl-21 = <&d9_ehrpwm5_a>; - pinctrl-22 = <&d9_gpio>; - pinctrl-23 = <&d9_gpio_pullup>; - pinctrl-24 = <&d9_gpio_pulldown>; - - d4_ehrpwm0_a: d4-ehrpwm0-a-pins { - pinctrl-single,pins = < - /* (AG18) EHRPWM0_A */ - AM65X_IOPAD(0x0084, PIN_OUTPUT, 5) - >; - }; - - d4_gpio: d4-gpio-pins { - pinctrl-single,pins = < - /* (AG18) GPIO0_33 */ - AM65X_IOPAD(0x0084, PIN_INPUT, 7) - >; - }; - - d4_gpio_pullup: d4-gpio-pullup-pins { - pinctrl-single,pins = < - /* (AG18) GPIO0_33 */ - AM65X_IOPAD(0x0084, PIN_INPUT_PULLUP, 7) - >; - }; - - d4_gpio_pulldown: d4-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (AG18) GPIO0_33 */ - AM65X_IOPAD(0x0084, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d5_ehrpwm1_a: d5-ehrpwm1-a-pins { - pinctrl-single,pins = < - /* (AF17) EHRPWM1_A */ - AM65X_IOPAD(0x008C, PIN_OUTPUT, 5) - >; - }; - - d5_gpio: d5-gpio-pins { - pinctrl-single,pins = < - /* (AF17) GPIO0_35 */ - AM65X_IOPAD(0x008C, PIN_INPUT, 7) - >; - }; - - d5_gpio_pullup: d5-gpio-pullup-pins { - pinctrl-single,pins = < - /* (AF17) GPIO0_35 */ - AM65X_IOPAD(0x008C, PIN_INPUT_PULLUP, 7) - >; - }; - - d5_gpio_pulldown: d5-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (AF17) GPIO0_35 */ - AM65X_IOPAD(0x008C, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d6_ehrpwm2_a: d6-ehrpwm2-a-pins { - pinctrl-single,pins = < - /* (AH16) EHRPWM2_A */ - AM65X_IOPAD(0x0098, PIN_OUTPUT, 5) - >; - }; - - d6_gpio: d6-gpio-pins { - pinctrl-single,pins = < - /* (AH16) GPIO0_38 */ - AM65X_IOPAD(0x0098, PIN_INPUT, 7) - >; - }; - - d6_gpio_pullup: d6-gpio-pullup-pins { - pinctrl-single,pins = < - /* (AH16) GPIO0_38 */ - AM65X_IOPAD(0x0098, PIN_INPUT_PULLUP, 7) - >; - }; - - d6_gpio_pulldown: d6-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (AH16) GPIO0_38 */ - AM65X_IOPAD(0x0098, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d7_ehrpwm3_a: d7-ehrpwm3-a-pins { - pinctrl-single,pins = < - /* (AH15) EHRPWM3_A */ - AM65X_IOPAD(0x00AC, PIN_OUTPUT, 5) - >; - }; - - d7_gpio: d7-gpio-pins { - pinctrl-single,pins = < - /* (AH15) GPIO0_43 */ - AM65X_IOPAD(0x00AC, PIN_INPUT, 7) - >; - }; - - d7_gpio_pullup: d7-gpio-pullup-pins { - pinctrl-single,pins = < - /* (AH15) GPIO0_43 */ - AM65X_IOPAD(0x00AC, PIN_INPUT_PULLUP, 7) - >; - }; - - d7_gpio_pulldown: d7-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (AH15) GPIO0_43 */ - AM65X_IOPAD(0x00AC, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d8_ehrpwm4_a: d8-ehrpwm4-a-pins { - pinctrl-single,pins = < - /* (AG15) EHRPWM4_A */ - AM65X_IOPAD(0x00C0, PIN_OUTPUT, 5) - >; - }; - - d8_gpio: d8-gpio-pins { - pinctrl-single,pins = < - /* (AG15) GPIO0_48 */ - AM65X_IOPAD(0x00C0, PIN_INPUT, 7) - >; - }; - - d8_gpio_pullup: d8-gpio-pullup-pins { - pinctrl-single,pins = < - /* (AG15) GPIO0_48 */ - AM65X_IOPAD(0x00C0, PIN_INPUT_PULLUP, 7) - >; - }; - - d8_gpio_pulldown: d8-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (AG15) GPIO0_48 */ - AM65X_IOPAD(0x00C0, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d9_ehrpwm5_a: d9-ehrpwm5-a-pins { - pinctrl-single,pins = < - /* (AD15) EHRPWM5_A */ - AM65X_IOPAD(0x00CC, PIN_OUTPUT, 5) - >; - }; - - d9_gpio: d9-gpio-pins { - pinctrl-single,pins = < - /* (AD15) GPIO0_51 */ - AM65X_IOPAD(0x00CC, PIN_INPUT, 7) - >; - }; - - d9_gpio_pullup: d9-gpio-pullup-pins { - pinctrl-single,pins = < - /* (AD15) GPIO0_51 */ - AM65X_IOPAD(0x00CC, PIN_INPUT_PULLUP, 7) - >; - }; - - d9_gpio_pulldown: d9-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (AD15) GPIO0_51 */ - AM65X_IOPAD(0x00CC, PIN_INPUT_PULLDOWN, 7) - >; - }; - main_pcie_enable_pins_default: main-pcie-enable-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */ @@ -971,45 +337,6 @@ >; }; - dss_vout1_pins_default: dss-vout1-default-pins { - pinctrl-single,pins = < - AM65X_IOPAD(0x0000, PIN_OUTPUT, 1) /* VOUT1_DATA0 */ - AM65X_IOPAD(0x0004, PIN_OUTPUT, 1) /* VOUT1_DATA1 */ - AM65X_IOPAD(0x0008, PIN_OUTPUT, 1) /* VOUT1_DATA2 */ - AM65X_IOPAD(0x000c, PIN_OUTPUT, 1) /* VOUT1_DATA3 */ - AM65X_IOPAD(0x0010, PIN_OUTPUT, 1) /* VOUT1_DATA4 */ - AM65X_IOPAD(0x0014, PIN_OUTPUT, 1) /* VOUT1_DATA5 */ - AM65X_IOPAD(0x0018, PIN_OUTPUT, 1) /* VOUT1_DATA6 */ - AM65X_IOPAD(0x001c, PIN_OUTPUT, 1) /* VOUT1_DATA7 */ - AM65X_IOPAD(0x0020, PIN_OUTPUT, 1) /* VOUT1_DATA8 */ - AM65X_IOPAD(0x0024, PIN_OUTPUT, 1) /* VOUT1_DATA9 */ - AM65X_IOPAD(0x0028, PIN_OUTPUT, 1) /* VOUT1_DATA10 */ - AM65X_IOPAD(0x002c, PIN_OUTPUT, 1) /* VOUT1_DATA11 */ - AM65X_IOPAD(0x0030, PIN_OUTPUT, 1) /* VOUT1_DATA12 */ - AM65X_IOPAD(0x0034, PIN_OUTPUT, 1) /* VOUT1_DATA13 */ - AM65X_IOPAD(0x0038, PIN_OUTPUT, 1) /* VOUT1_DATA14 */ - AM65X_IOPAD(0x003c, PIN_OUTPUT, 1) /* VOUT1_DATA15 */ - AM65X_IOPAD(0x0040, PIN_OUTPUT, 1) /* VOUT1_DATA16 */ - AM65X_IOPAD(0x0044, PIN_OUTPUT, 1) /* VOUT1_DATA17 */ - AM65X_IOPAD(0x0048, PIN_OUTPUT, 1) /* VOUT1_DATA18 */ - AM65X_IOPAD(0x004c, PIN_OUTPUT, 1) /* VOUT1_DATA19 */ - AM65X_IOPAD(0x0050, PIN_OUTPUT, 1) /* VOUT1_DATA20 */ - AM65X_IOPAD(0x0054, PIN_OUTPUT, 1) /* VOUT1_DATA21 */ - AM65X_IOPAD(0x0058, PIN_OUTPUT, 1) /* VOUT1_DATA22 */ - AM65X_IOPAD(0x005c, PIN_OUTPUT, 1) /* VOUT1_DATA23 */ - AM65X_IOPAD(0x0060, PIN_OUTPUT, 1) /* VOUT1_VSYNC */ - AM65X_IOPAD(0x0064, PIN_OUTPUT, 1) /* VOUT1_HSYNC */ - AM65X_IOPAD(0x0068, PIN_OUTPUT, 1) /* VOUT1_PCLK */ - AM65X_IOPAD(0x006c, PIN_OUTPUT, 1) /* VOUT1_DE */ - >; - }; - - dp_pins_default: dp-default-pins { - pinctrl-single,pins = < - AM65X_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AF18) DP rst_n */ - >; - }; - main_i2c2_pins_default: main-i2c2-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) I2C2_SCL */ @@ -1082,57 +409,11 @@ pinctrl-0 = <&main_uart1_pins_default>; }; -&mcu_uart0 { - status = "okay"; -}; - -&main_gpio0 { - gpio-line-names = - "main_gpio0-base", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", - "", "", "", "IO4", "", "IO5", "", "", "IO6", "", - "", "", "", "IO7", "", "", "", "", "IO8", "", - "", "IO9"; -}; - &main_gpio1 { pinctrl-names = "default"; pinctrl-0 = <&main_pcie_enable_pins_default>; }; -&wkup_gpio0 { - pinctrl-names = "default"; - pinctrl-0 = - <&arduino_i2c_aio_switch_pins_default>, - <&arduino_io_oe_pins_default>, - <&push_button_pins_default>, - <&db9_com_mode_pins_default>; - gpio-line-names = - /* 0..9 */ - "wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0", - "UART0-enable", "UART0-terminate", "", "WIFI-disable", - /* 10..19 */ - "", "", "", "", "", "", "", "", "", "", - /* 20..29 */ - "", "A4A5-I2C-mux", "", "", "", "USER-button", "", "", "","IO0", - /* 30..39 */ - "IO1", "IO2", "", "IO3", "IO17-direction", "A5", - "IO16-direction", "IO15-direction", "IO14-direction", "A3", - /* 40..49 */ - "", "IO18-direction", "A4", "A2", "A1", "A0", "", "", "IO13", - "IO11", - /* 50..51 */ - "IO12", "IO10"; -}; - -&wkup_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <400000>; -}; - &mcu_i2c0 { status = "okay"; pinctrl-names = "default"; @@ -1150,47 +431,6 @@ ti,vsel1-state-high; ti,enable-vout-discharge; }; - - /* D4200 */ - pcal9535_1: gpio@20 { - compatible = "nxp,pcal9535"; - reg = <0x20>; - #gpio-cells = <2>; - gpio-controller; - gpio-line-names = - "A0-pull", "A1-pull", "A2-pull", "A3-pull", "A4-pull", - "A5-pull", "", "", - "IO14-enable", "IO15-enable", "IO16-enable", - "IO17-enable", "IO18-enable", "IO19-enable"; - }; - - /* D4201 */ - pcal9535_2: gpio@21 { - compatible = "nxp,pcal9535"; - reg = <0x21>; - #gpio-cells = <2>; - gpio-controller; - gpio-line-names = - "IO0-direction", "IO1-direction", "IO2-direction", - "IO3-direction", "IO4-direction", "IO5-direction", - "IO6-direction", "IO7-direction", - "IO8-direction", "IO9-direction", "IO10-direction", - "IO11-direction", "IO12-direction", "IO13-direction", - "IO19-direction"; - }; - - /* D4202 */ - pcal9535_3: gpio@25 { - compatible = "nxp,pcal9535"; - reg = <0x25>; - #gpio-cells = <2>; - gpio-controller; - gpio-line-names = - "IO0-pull", "IO1-pull", "IO2-pull", "IO3-pull", - "IO4-pull", "IO5-pull", "IO6-pull", "IO7-pull", - "IO8-pull", "IO9-pull", "IO10-pull", "IO11-pull", - "IO12-pull", "IO13-pull"; - }; }; &main_i2c0 { @@ -1233,32 +473,6 @@ #address-cells = <1>; #size-cells = <0>; - - edp-bridge@f { - compatible = "toshiba,tc358767"; - reg = <0x0f>; - pinctrl-names = "default"; - pinctrl-0 = <&dp_pins_default>; - reset-gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>; - - clock-names = "ref"; - clocks = <&dp_refclk>; - - toshiba,hpd-pin = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - bridge_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - }; }; &mcu_cpsw { @@ -1292,13 +506,6 @@ ti,pindir-d0-out-d1-in; }; -&tscadc1 { - status = "okay"; - adc { - ti,adc-channels = <0 1 2 3 4 5>; - }; -}; - &ospi0 { status = "okay"; pinctrl-names = "default"; @@ -1364,26 +571,6 @@ }; }; -&dss { - pinctrl-names = "default"; - pinctrl-0 = <&dss_vout1_pins_default>; - - assigned-clocks = <&k3_clks 67 2>; - assigned-clock-parents = <&k3_clks 67 5>; -}; - -&dss_ports { - #address-cells = <1>; - #size-cells = <0>; - port@1 { - reg = <1>; - - dpi_out: endpoint { - remote-endpoint = <&bridge_in>; - }; - }; -}; - &pcie1_rc { status = "okay"; pinctrl-names = "default"; @@ -1418,13 +605,17 @@ &mcu_r5fss0_core0 { memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; }; &mcu_r5fss0_core1 { memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; - mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; +}; + +&mcu_rti1 { + memory-region = <&wdt_reset_memory_region>; }; &icssg0_mdio { diff --git a/src/arm64/ti/k3-am65-iot2050-dp.dtsi b/src/arm64/ti/k3-am65-iot2050-dp.dtsi new file mode 100644 index 00000000000..984cc80913b --- /dev/null +++ b/src/arm64/ti/k3-am65-iot2050-dp.dtsi @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Siemens AG, 2024 + * + * Authors: + * Jan Kiszka + * + * Common bits for IOT2050 variants with Display Port + */ + +&main_pmx0 { + dss_vout1_pins_default: dss-vout1-default-pins { + pinctrl-single,pins = < + AM65X_IOPAD(0x0000, PIN_OUTPUT, 1) /* VOUT1_DATA0 */ + AM65X_IOPAD(0x0004, PIN_OUTPUT, 1) /* VOUT1_DATA1 */ + AM65X_IOPAD(0x0008, PIN_OUTPUT, 1) /* VOUT1_DATA2 */ + AM65X_IOPAD(0x000c, PIN_OUTPUT, 1) /* VOUT1_DATA3 */ + AM65X_IOPAD(0x0010, PIN_OUTPUT, 1) /* VOUT1_DATA4 */ + AM65X_IOPAD(0x0014, PIN_OUTPUT, 1) /* VOUT1_DATA5 */ + AM65X_IOPAD(0x0018, PIN_OUTPUT, 1) /* VOUT1_DATA6 */ + AM65X_IOPAD(0x001c, PIN_OUTPUT, 1) /* VOUT1_DATA7 */ + AM65X_IOPAD(0x0020, PIN_OUTPUT, 1) /* VOUT1_DATA8 */ + AM65X_IOPAD(0x0024, PIN_OUTPUT, 1) /* VOUT1_DATA9 */ + AM65X_IOPAD(0x0028, PIN_OUTPUT, 1) /* VOUT1_DATA10 */ + AM65X_IOPAD(0x002c, PIN_OUTPUT, 1) /* VOUT1_DATA11 */ + AM65X_IOPAD(0x0030, PIN_OUTPUT, 1) /* VOUT1_DATA12 */ + AM65X_IOPAD(0x0034, PIN_OUTPUT, 1) /* VOUT1_DATA13 */ + AM65X_IOPAD(0x0038, PIN_OUTPUT, 1) /* VOUT1_DATA14 */ + AM65X_IOPAD(0x003c, PIN_OUTPUT, 1) /* VOUT1_DATA15 */ + AM65X_IOPAD(0x0040, PIN_OUTPUT, 1) /* VOUT1_DATA16 */ + AM65X_IOPAD(0x0044, PIN_OUTPUT, 1) /* VOUT1_DATA17 */ + AM65X_IOPAD(0x0048, PIN_OUTPUT, 1) /* VOUT1_DATA18 */ + AM65X_IOPAD(0x004c, PIN_OUTPUT, 1) /* VOUT1_DATA19 */ + AM65X_IOPAD(0x0050, PIN_OUTPUT, 1) /* VOUT1_DATA20 */ + AM65X_IOPAD(0x0054, PIN_OUTPUT, 1) /* VOUT1_DATA21 */ + AM65X_IOPAD(0x0058, PIN_OUTPUT, 1) /* VOUT1_DATA22 */ + AM65X_IOPAD(0x005c, PIN_OUTPUT, 1) /* VOUT1_DATA23 */ + AM65X_IOPAD(0x0060, PIN_OUTPUT, 1) /* VOUT1_VSYNC */ + AM65X_IOPAD(0x0064, PIN_OUTPUT, 1) /* VOUT1_HSYNC */ + AM65X_IOPAD(0x0068, PIN_OUTPUT, 1) /* VOUT1_PCLK */ + AM65X_IOPAD(0x006c, PIN_OUTPUT, 1) /* VOUT1_DE */ + >; + }; + + dp_pins_default: dp-default-pins { + pinctrl-single,pins = < + AM65X_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AF18) DP rst_n */ + >; + }; +}; + +&main_i2c3 { + edp-bridge@f { + compatible = "toshiba,tc358767"; + reg = <0x0f>; + pinctrl-names = "default"; + pinctrl-0 = <&dp_pins_default>; + reset-gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>; + + clock-names = "ref"; + clocks = <&dp_refclk>; + + toshiba,hpd-pin = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + bridge_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + }; +}; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = <&dss_vout1_pins_default>; + + assigned-clocks = <&k3_clks 67 2>; + assigned-clock-parents = <&k3_clks 67 5>; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + port@1 { + reg = <1>; + + dpi_out: endpoint { + remote-endpoint = <&bridge_in>; + }; + }; +}; diff --git a/src/arm64/ti/k3-am65-iot2050-usb3.dtsi b/src/arm64/ti/k3-am65-iot2050-usb3.dtsi new file mode 100644 index 00000000000..e5bd7c301b1 --- /dev/null +++ b/src/arm64/ti/k3-am65-iot2050-usb3.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Siemens AG, 2024 + * + * Authors: + * Jan Kiszka + * + * Common bits for IOT2050 variants with USB3 support + */ + +&serdes0 { + assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>; +}; + +&dwc3_0 { + assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ + <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */ + phys = <&serdes0 PHY_TYPE_USB3 0>; + phy-names = "usb3-phy"; +}; + +&usb0 { + maximum-speed = "super-speed"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; +}; diff --git a/src/arm64/ti/k3-am65-main.dtsi b/src/arm64/ti/k3-am65-main.dtsi index fcea5446563..ff857117d71 100644 --- a/src/arm64/ti/k3-am65-main.dtsi +++ b/src/arm64/ti/k3-am65-main.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM6 SoC Family Main Domain peripherals * - * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include @@ -886,20 +886,6 @@ status = "disabled"; }; - pcie0_ep: pcie-ep@5500000 { - compatible = "ti,am654-pcie-ep"; - reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>; - reg-names = "app", "dbics", "addr_space", "atu"; - power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; - ti,syscon-pcie-mode = <&scm_conf 0x4060>; - num-ib-windows = <16>; - num-ob-windows = <16>; - max-link-speed = <2>; - dma-coherent; - interrupts = ; - status = "disabled"; - }; - pcie1_rc: pcie@5600000 { compatible = "ti,am654-pcie-rc"; reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>; @@ -921,20 +907,6 @@ status = "disabled"; }; - pcie1_ep: pcie-ep@5600000 { - compatible = "ti,am654-pcie-ep"; - reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>; - reg-names = "app", "dbics", "addr_space", "atu"; - power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; - ti,syscon-pcie-mode = <&scm_conf 0x4070>; - num-ib-windows = <16>; - num-ob-windows = <16>; - max-link-speed = <2>; - dma-coherent; - interrupts = ; - status = "disabled"; - }; - mcasp0: mcasp@2b00000 { compatible = "ti,am33xx-mcasp-audio"; reg = <0x0 0x02b00000 0x0 0x2000>, @@ -1019,9 +991,10 @@ <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ - <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ + <0x0 0x04a0b000 0x0 0x1000>, /* vp2 */ + <0x0 0x04a01000 0x0 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; @@ -1050,6 +1023,13 @@ }; }; + gpu: gpu@7000000 { + compatible = "ti,am6548-gpu", "img,powervr-sgx544"; + reg = <0x0 0x7000000 0x0 0x10000>; + interrupts = ; + power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; + }; + ehrpwm0: pwm@3000000 { compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; diff --git a/src/arm64/ti/k3-am65-mcu.dtsi b/src/arm64/ti/k3-am65-mcu.dtsi index ecd7356f331..6ff3ccc39fb 100644 --- a/src/arm64/ti/k3-am65-mcu.dtsi +++ b/src/arm64/ti/k3-am65-mcu.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM6 SoC Family MCU Domain peripherals * - * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu { diff --git a/src/arm64/ti/k3-am65-wakeup.dtsi b/src/arm64/ti/k3-am65-wakeup.dtsi index f037b36243c..37527890dde 100644 --- a/src/arm64/ti/k3-am65-wakeup.dtsi +++ b/src/arm64/ti/k3-am65-wakeup.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM6 SoC Family Wakeup Domain peripherals * - * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_wakeup { diff --git a/src/arm64/ti/k3-am65.dtsi b/src/arm64/ti/k3-am65.dtsi index 4d7b6155a76..c59baebc5a2 100644 --- a/src/arm64/ti/k3-am65.dtsi +++ b/src/arm64/ti/k3-am65.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM6 SoC Family * - * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include diff --git a/src/arm64/ti/k3-am652.dtsi b/src/arm64/ti/k3-am652.dtsi index 0f22e00faa9..cbb3caaf82c 100644 --- a/src/arm64/ti/k3-am652.dtsi +++ b/src/arm64/ti/k3-am652.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM65 SoC family in Dual core configuration * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-am65.dtsi" diff --git a/src/arm64/ti/k3-am6528-iot2050-basic-common.dtsi b/src/arm64/ti/k3-am6528-iot2050-basic-common.dtsi index 1d6cddb1199..eed6fe70d29 100644 --- a/src/arm64/ti/k3-am6528-iot2050-basic-common.dtsi +++ b/src/arm64/ti/k3-am6528-iot2050-basic-common.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) Siemens AG, 2018-2021 * @@ -11,6 +11,7 @@ #include "k3-am652.dtsi" #include "k3-am65-iot2050-common.dtsi" +#include "k3-am65-iot2050-arduino-connector.dtsi" / { memory@80000000 { @@ -40,8 +41,3 @@ pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; }; - -&mcu_r5fss0 { - /* lock-step mode not supported on Basic boards */ - ti,cluster-mode = <0>; -}; diff --git a/src/arm64/ti/k3-am6528-iot2050-basic-pg2.dts b/src/arm64/ti/k3-am6528-iot2050-basic-pg2.dts index c62549a4b43..c1faf9497b6 100644 --- a/src/arm64/ti/k3-am6528-iot2050-basic-pg2.dts +++ b/src/arm64/ti/k3-am6528-iot2050-basic-pg2.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) Siemens AG, 2018-2021 * @@ -17,6 +17,8 @@ #include "k3-am6528-iot2050-basic-common.dtsi" #include "k3-am65-iot2050-common-pg2.dtsi" +#include "k3-am65-iot2050-dp.dtsi" +#include "k3-am65-iot2050-usb3.dtsi" / { compatible = "siemens,iot2050-basic-pg2", "ti,am654"; diff --git a/src/arm64/ti/k3-am6528-iot2050-basic.dts b/src/arm64/ti/k3-am6528-iot2050-basic.dts index 87928ff2821..29a31891b3d 100644 --- a/src/arm64/ti/k3-am6528-iot2050-basic.dts +++ b/src/arm64/ti/k3-am6528-iot2050-basic.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) Siemens AG, 2018-2021 * @@ -22,3 +22,8 @@ compatible = "siemens,iot2050-basic", "ti,am654"; model = "SIMATIC IOT2050 Basic"; }; + +&mcu_r5fss0 { + /* lock-step mode not supported on this board */ + ti,cluster-mode = <0>; +}; diff --git a/src/arm64/ti/k3-am654-base-board-rocktech-rk101-panel.dtso b/src/arm64/ti/k3-am654-base-board-rocktech-rk101-panel.dtso index 3be92c39ecb..364c57b3b3a 100644 --- a/src/arm64/ti/k3-am654-base-board-rocktech-rk101-panel.dtso +++ b/src/arm64/ti/k3-am654-base-board-rocktech-rk101-panel.dtso @@ -1,10 +1,10 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * OLDI-LCD1EVM Rocktech integrated panel and touch DT overlay for AM654-EVM. * Panel Link: https://www.digimax.it/en/tft-lcd/20881-RK101II01D-CT * AM654 LCD EVM: https://www.ti.com/tool/TMDSLCD1EVM * - * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am654-base-board.dts b/src/arm64/ti/k3-am654-base-board.dts index 822c288d279..aba0c52b121 100644 --- a/src/arm64/ti/k3-am654-base-board.dts +++ b/src/arm64/ti/k3-am654-base-board.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -531,13 +531,13 @@ &mcu_r5fss0_core0 { memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; }; &mcu_r5fss0_core1 { memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; - mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; }; &ospi0 { diff --git a/src/arm64/ti/k3-am654-icssg2.dtso b/src/arm64/ti/k3-am654-icssg2.dtso index ec8cf20ca3a..0a6e75265ba 100644 --- a/src/arm64/ti/k3-am654-icssg2.dtso +++ b/src/arm64/ti/k3-am654-icssg2.dtso @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * DT overlay for IDK application board on AM654 EVM * - * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am654-idk.dtso b/src/arm64/ti/k3-am654-idk.dtso index 150428dfce6..8bdb87fcbde 100644 --- a/src/arm64/ti/k3-am654-idk.dtso +++ b/src/arm64/ti/k3-am654-idk.dtso @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * DT overlay for IDK application board on AM654 EVM * - * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-am654-industrial-thermal.dtsi b/src/arm64/ti/k3-am654-industrial-thermal.dtsi index 9021c738056..de5a2ed907a 100644 --- a/src/arm64/ti/k3-am654-industrial-thermal.dtsi +++ b/src/arm64/ti/k3-am654-industrial-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include diff --git a/src/arm64/ti/k3-am654-pcie-usb2.dtso b/src/arm64/ti/k3-am654-pcie-usb2.dtso new file mode 100644 index 00000000000..c3cb752f8cd --- /dev/null +++ b/src/arm64/ti/k3-am654-pcie-usb2.dtso @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT overlay for SERDES personality card: 2lane PCIe + USB2.0 Host on AM654 EVM + * + * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; +#include +#include +#include +#include "k3-pinctrl.h" + +&serdes0 { + assigned-clocks = <&k3_clks 153 4>, + <&serdes0 AM654_SERDES_CMU_REFCLK>, + <&serdes0 AM654_SERDES_RO_REFCLK>; + assigned-clock-parents = <&k3_clks 153 8>, + <&k3_clks 153 4>, + <&k3_clks 153 4>; + status = "okay"; +}; + +&serdes1 { + assigned-clocks = <&serdes1 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&serdes0 AM654_SERDES_RO_REFCLK>; + status = "okay"; +}; + +&pcie0_rc { + num-lanes = <2>; + phys = <&serdes0 PHY_TYPE_PCIE 1>, <&serdes1 PHY_TYPE_PCIE 1>; + phy-names = "pcie-phy0", "pcie-phy1"; + reset-gpios = <&pca9555 5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&main_pmx0 { + usb0_pins_default: usb0-default-pins { + pinctrl-single,pins = < + AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */ + >; + }; +}; + +&dwc3_0 { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins_default>; + dr_mode = "host"; +}; diff --git a/src/arm64/ti/k3-am654-pcie-usb3.dtso b/src/arm64/ti/k3-am654-pcie-usb3.dtso new file mode 100644 index 00000000000..333e423e8bb --- /dev/null +++ b/src/arm64/ti/k3-am654-pcie-usb3.dtso @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT overlay for SERDES personality card: 1lane PCIe + USB3.0 DRD on AM654 EVM + * + * Copyright (C) 2018-2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; +#include +#include +#include + +#include "k3-pinctrl.h" + +&serdes1 { + status = "okay"; +}; + +&pcie1_rc { + num-lanes = <1>; + phys = <&serdes1 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy0"; + reset-gpios = <&pca9555 5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&main_pmx0 { + usb0_pins_default: usb0-default-pins { + pinctrl-single,pins = < + AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */ + >; + }; +}; + +&serdes0 { + status = "okay"; + assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>; +}; + +&dwc3_0 { + status = "okay"; + assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ + <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */ + phys = <&serdes0 PHY_TYPE_USB3 0>; + phy-names = "usb3-phy"; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins_default>; + dr_mode = "host"; + maximum-speed = "super-speed"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; +}; + +&usb0_phy { + status = "okay"; +}; diff --git a/src/arm64/ti/k3-am654.dtsi b/src/arm64/ti/k3-am654.dtsi index 888567b921f..bb77c845473 100644 --- a/src/arm64/ti/k3-am654.dtsi +++ b/src/arm64/ti/k3-am654.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM6 SoC family in Quad core configuration * - * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-am65.dtsi" diff --git a/src/arm64/ti/k3-am6548-iot2050-advanced-common.dtsi b/src/arm64/ti/k3-am6548-iot2050-advanced-common.dtsi index 3864ec54e37..ae842b85b70 100644 --- a/src/arm64/ti/k3-am6548-iot2050-advanced-common.dtsi +++ b/src/arm64/ti/k3-am6548-iot2050-advanced-common.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) Siemens AG, 2018-2021 * diff --git a/src/arm64/ti/k3-am6548-iot2050-advanced-m2.dts b/src/arm64/ti/k3-am6548-iot2050-advanced-m2.dts index bd6f2e696e9..cc619bbec18 100644 --- a/src/arm64/ti/k3-am6548-iot2050-advanced-m2.dts +++ b/src/arm64/ti/k3-am6548-iot2050-advanced-m2.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) Siemens AG, 2018-2023 * @@ -15,17 +15,14 @@ #include "k3-am6548-iot2050-advanced-common.dtsi" #include "k3-am65-iot2050-common-pg2.dtsi" +#include "k3-am65-iot2050-arduino-connector.dtsi" +#include "k3-am65-iot2050-dp.dtsi" / { compatible = "siemens,iot2050-advanced-m2", "ti,am654"; model = "SIMATIC IOT2050 Advanced M2"; }; -&mcu_r5fss0 { - /* lock-step mode not supported on this board */ - ti,cluster-mode = <0>; -}; - &main_pmx0 { main_bkey_pcie_reset: main-bkey-pcie-reset-default-pins { pinctrl-single,pins = < @@ -96,16 +93,3 @@ &pcie1_rc { status = "disabled"; }; - -&dwc3_0 { - assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ - <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ - /delete-property/ phys; - /delete-property/ phy-names; -}; - -&usb0 { - maximum-speed = "high-speed"; - /delete-property/ snps,dis-u1-entry-quirk; - /delete-property/ snps,dis-u2-entry-quirk; -}; diff --git a/src/arm64/ti/k3-am6548-iot2050-advanced-pg2.dts b/src/arm64/ti/k3-am6548-iot2050-advanced-pg2.dts index f00dc86d01b..ec721275e8e 100644 --- a/src/arm64/ti/k3-am6548-iot2050-advanced-pg2.dts +++ b/src/arm64/ti/k3-am6548-iot2050-advanced-pg2.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) Siemens AG, 2018-2021 + * Copyright (c) Siemens AG, 2018-2023 * * Authors: * Le Jin @@ -17,13 +17,11 @@ #include "k3-am6548-iot2050-advanced-common.dtsi" #include "k3-am65-iot2050-common-pg2.dtsi" +#include "k3-am65-iot2050-arduino-connector.dtsi" +#include "k3-am65-iot2050-dp.dtsi" +#include "k3-am65-iot2050-usb3.dtsi" / { compatible = "siemens,iot2050-advanced-pg2", "ti,am654"; model = "SIMATIC IOT2050 Advanced PG2"; }; - -&mcu_r5fss0 { - /* lock-step mode not supported on this board */ - ti,cluster-mode = <0>; -}; diff --git a/src/arm64/ti/k3-am6548-iot2050-advanced-sm.dts b/src/arm64/ti/k3-am6548-iot2050-advanced-sm.dts new file mode 100644 index 00000000000..b829f4bcab6 --- /dev/null +++ b/src/arm64/ti/k3-am6548-iot2050-advanced-sm.dts @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Siemens AG, 2023 + * + * Authors: + * Baocheng Su + * Chao Zeng + * Huaqian Li + * + * AM6548-based (quad-core) IOT2050 SM variant, Product Generation 2 + * 4 GB RAM, 16 GB eMMC, USB-serial converter on connector X30 + * + * Product homepage: + * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html + */ + +/dts-v1/; + +#include "k3-am6548-iot2050-advanced-common.dtsi" +#include "k3-am65-iot2050-common-pg2.dtsi" + +/ { + compatible = "siemens,iot2050-advanced-sm", "ti,am654"; + model = "SIMATIC IOT2050 Advanced SM"; + + memory@80000000 { + device_type = "memory"; + /* 4G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000000 0x80000000>; + }; + + aliases { + spi1 = &main_spi0; + }; + + leds { + pinctrl-0 = <&leds_pins_default>, <&user1_led_pins>; + + led-2 { + gpios = <&wkup_gpio0 52 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + gpios = <&wkup_gpio0 53 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&main_pmx0 { + main_pcie_enable_pins_default: main-pcie-enable-default-pins { + pinctrl-single,pins = < + AM65X_IOPAD(0x01d8, PIN_OUTPUT, 7) /* (AH12) GPIO1_22 */ + >; + }; + + main_spi0_pins: main-spi0-default-pins { + pinctrl-single,pins = < + AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */ + AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */ + AM65X_IOPAD(0x01cc, PIN_INPUT, 0) /* (AD13) SPI0_D1 */ + AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */ + >; + }; +}; + +&main_pmx1 { + asic_spi_mux_ctrl_pin: asic-spi-mux-ctrl-default-pins { + pinctrl-single,pins = < + AM65X_IOPAD(0x0010, PIN_OUTPUT, 7) /* (D21) GPIO1_86 */ + >; + }; +}; + +&wkup_pmx0 { + user1_led_pins: user1-led-default-pins { + pinctrl-single,pins = < + /* (AB1) WKUP_UART0_RXD:WKUP_GPIO0_52, as USER 1 led red */ + AM65X_WKUP_IOPAD(0x00a0, PIN_OUTPUT, 7) + /* (AB5) WKUP_UART0_TXD:WKUP_GPIO0_53, as USER 1 led green */ + AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 7) + >; + }; + + soc_asic_pins: soc-asic-default-pins { + pinctrl-single,pins = < + AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 7) /* (P4) WKUP_GPIO0_29 */ + AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7) /* (P5) WKUP_GPIO0_30 */ + AM65X_WKUP_IOPAD(0x004c, PIN_INPUT, 7) /* (P1) WKUP_GPIO0_31 */ + >; + }; +}; + +&main_gpio0 { + gpio-line-names = "main_gpio0-base"; +}; + +&main_gpio1 { + pinctrl-names = "default"; + pinctrl-0 = + <&cp2102n_reset_pin_default>, + <&main_pcie_enable_pins_default>, + <&asic_spi_mux_ctrl_pin>; + gpio-line-names = + /* 0..9 */ + "", "", "", "", "", "", "", "", "", "", + /* 10..19 */ + "", "", "", "", "", "", "", "", "", "", + /* 20..29 */ + "", "", "", "", "CP2102N-RESET", "", "", "", "", "", + /* 30..39 */ + "", "", "", "", "", "", "", "", "", "", + /* 40..49 */ + "", "", "", "", "", "", "", "", "", "", + /* 50..59 */ + "", "", "", "", "", "", "", "", "", "", + /* 60..69 */ + "", "", "", "", "", "", "", "", "", "", + /* 70..79 */ + "", "", "", "", "", "", "", "", "", "", + /* 80..86 */ + "", "", "", "", "", "", "ASIC-spi-mux-ctrl"; +}; + +&wkup_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = + <&push_button_pins_default>, + <&db9_com_mode_pins_default>, + <&soc_asic_pins>; + gpio-line-names = + /* 0..9 */ + "wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0", + "UART0-enable", "UART0-terminate", "", "WIFI-disable", + /* 10..19 */ + "", "", "", "", "", "", "", "", "", "", + /* 20..29 */ + "", "", "", "", "", "USER-button", "", "", "","ASIC-gpio-0", + /* 30..31 */ + "ASIC-gpio-1", "ASIC-gpio-2"; +}; + +&main_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_spi0_pins>; + + #address-cells = <1>; + #size-cells= <0>; +}; + +&mcu_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_spi0_pins_default>; +}; + +&main_i2c3 { + accelerometer: lsm6dso@6a { + compatible = "st,lsm6dso"; + reg = <0x6a>; + }; +}; + +&dss { + status = "disabled"; +}; + +&serdes0 { + assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; +}; + +&serdes1 { + status = "disabled"; +}; + +&pcie0_rc { + pinctrl-names = "default"; + pinctrl-0 = <&minipcie_pins_default>; + + num-lanes = <1>; + phys = <&serdes0 PHY_TYPE_PCIE 1>; + phy-names = "pcie-phy0"; + reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie1_rc { + status = "disabled"; +}; diff --git a/src/arm64/ti/k3-am6548-iot2050-advanced.dts b/src/arm64/ti/k3-am6548-iot2050-advanced.dts index 077f165bdc6..649652a540e 100644 --- a/src/arm64/ti/k3-am6548-iot2050-advanced.dts +++ b/src/arm64/ti/k3-am6548-iot2050-advanced.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) Siemens AG, 2018-2021 * @@ -17,6 +17,7 @@ #include "k3-am6548-iot2050-advanced-common.dtsi" #include "k3-am65-iot2050-common-pg1.dtsi" +#include "k3-am65-iot2050-arduino-connector.dtsi" / { compatible = "siemens,iot2050-advanced", "ti,am654"; diff --git a/src/arm64/ti/k3-am68-sk-base-board.dts b/src/arm64/ti/k3-am68-sk-base-board.dts index d0cfdeac21f..d743f023cdd 100644 --- a/src/arm64/ti/k3-am68-sk-base-board.dts +++ b/src/arm64/ti/k3-am68-sk-base-board.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ * * Base Board: https://www.ti.com/lit/zip/SPRR463 */ @@ -169,6 +169,13 @@ }; }; }; + + csi_mux: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp3 1 GPIO_ACTIVE_HIGH>; + idle-state = <0>; + }; }; &main_pmx0 { @@ -186,6 +193,13 @@ >; }; + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0ac, PIN_INPUT, 13) /* (AC25) MCASP0_AXR15.I2C1_SCL */ + J721S2_IOPAD(0x0b0, PIN_INPUT, 13) /* (AD26) MCASP1_AXR3.I2C1_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ @@ -431,6 +445,42 @@ }; }; +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + status = "okay"; + + exp3: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI_VIO_SEL", "CSI_SEL_FPC_EXPn", + "IO_EXP_CSI2_EXP_RSTz","CSI0_B_GPIO1", + "CSI1_B_GPIO1"; + }; + + i2c-mux@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + cam0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + cam1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + }; +}; + &main_i2c4 { status = "okay"; pinctrl-names = "default"; diff --git a/src/arm64/ti/k3-am68-sk-som.dtsi b/src/arm64/ti/k3-am68-sk-som.dtsi index 20861a0a46b..0f4a5da0ebc 100644 --- a/src/arm64/ti/k3-am68-sk-som.dtsi +++ b/src/arm64/ti/k3-am68-sk-som.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -209,51 +209,51 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &c71_0 { status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; &c71_1 { status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>; + mboxes = <&mailbox0_cluster4 &mbox_c71_1>; memory-region = <&c71_1_dma_memory_region>, <&c71_1_memory_region>; }; diff --git a/src/arm64/ti/k3-am69-sk.dts b/src/arm64/ti/k3-am69-sk.dts index 8da59157986..50de2a448a3 100644 --- a/src/arm64/ti/k3-am69-sk.dts +++ b/src/arm64/ti/k3-am69-sk.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ * * Design Files: https://www.ti.com/lit/zip/SPRR466 * TRM: https://www.ti.com/lit/zip/spruj52 @@ -33,6 +33,7 @@ memory@80000000 { device_type = "memory"; + bootph-all; /* 32G RAM */ reg = <0x00 0x80000000 0x00 0x80000000>, <0x08 0x80000000 0x07 0x80000000>; @@ -321,6 +322,38 @@ }; }; }; + + csi_mux: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp2 1 GPIO_ACTIVE_HIGH>; + idle-state = <0>; + }; + + transceiver1: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver2: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver3: can-phy2 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver4: can-phy3 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + }; &main_pmx0 { @@ -340,6 +373,13 @@ >; }; + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0ac, PIN_INPUT_PULLUP, 13) /* (AE34) MCASP0_AXR15.I2C1_SCL */ + J784S4_IOPAD(0x0b0, PIN_INPUT_PULLUP, 13) /* (AL33) MCASP1_AXR3.I2C1_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { bootph-all; pinctrl-single,pins = < @@ -429,6 +469,40 @@ J784S4_IOPAD(0x000, PIN_INPUT, 7) /* (AN35) EXTINTN.GPIO0_0 */ >; }; + + main_mcan6_pins_default: main-mcan6-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x098, PIN_INPUT, 0) /* (AH36) MCAN6_RX */ + J784S4_IOPAD(0x094, PIN_OUTPUT, 0) /* (AG35) MCAN6_TX */ + >; + }; + + main_mcan7_pins_default: main-mcan7-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0A0, PIN_INPUT, 0) /* (AD34) MCAN7_RX */ + J784S4_IOPAD(0x09C, PIN_OUTPUT, 0) /* (AF35) MCAN7_TX */ + >; + }; + +}; + +&wkup_pmx0 { + bootph-all; + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ + J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ + J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ + J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ + J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ + J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ + J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ + >; + }; }; &wkup_pmx2 { @@ -525,6 +599,21 @@ J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 7) /* (H37) WKUP_GPIO0_14 */ >; }; + + mcu_mcan0_pins_default: mcu-mcan0-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */ + J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */ + J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0)/* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */ + >; + }; + }; &wkup_pmx3 { @@ -646,7 +735,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pmic_irq_pins_default>; interrupt-parent = <&wkup_gpio0>; - interrupts = <39 IRQ_TYPE_EDGE_FALLING>; + interrupts = <83 IRQ_TYPE_EDGE_FALLING>; gpio-controller; #gpio-cells = <2>; ti,primary-pmic; @@ -774,6 +863,42 @@ }; }; +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + exp2: gpio@21 { + compatible = "ti,tca6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI_VIO_SEL", "CSI_MUX_SEL_2", "CSI2_RSTz", + "IO_EXP_CAM0_GPIO1", "IO_EXP_CAM1_GPIO1"; + }; + + i2c-mux@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + cam0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + cam1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + }; +}; + &main_sdhci0 { bootph-all; /* eMMC */ @@ -822,77 +947,77 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &main_r5fss2_core0 { - mboxes = <&mailbox0_cluster3>, <&mbox_main_r5fss2_core0>; + mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; memory-region = <&main_r5fss2_core0_dma_memory_region>, <&main_r5fss2_core0_memory_region>; }; &main_r5fss2_core1 { - mboxes = <&mailbox0_cluster3>, <&mbox_main_r5fss2_core1>; + mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; memory-region = <&main_r5fss2_core1_dma_memory_region>, <&main_r5fss2_core1_memory_region>; }; &c71_0 { status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; &c71_1 { status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>; + mboxes = <&mailbox0_cluster4 &mbox_c71_1>; memory-region = <&c71_1_dma_memory_region>, <&c71_1_memory_region>; }; &c71_2 { status = "okay"; - mboxes = <&mailbox0_cluster5>, <&mbox_c71_2>; + mboxes = <&mailbox0_cluster5 &mbox_c71_2>; memory-region = <&c71_2_dma_memory_region>, <&c71_2_memory_region>; }; &c71_3 { status = "okay"; - mboxes = <&mailbox0_cluster5>, <&mbox_c71_3>; + mboxes = <&mailbox0_cluster5 &mbox_c71_3>; memory-region = <&c71_3_dma_memory_region>, <&c71_3_memory_region>; }; @@ -918,13 +1043,9 @@ pinctrl-names = "default"; pinctrl-0 = <&dss_vout0_pins_default>; assigned-clocks = <&k3_clks 218 2>, - <&k3_clks 218 5>, - <&k3_clks 218 14>, - <&k3_clks 218 18>; + <&k3_clks 218 5>; assigned-clock-parents = <&k3_clks 218 3>, - <&k3_clks 218 7>, - <&k3_clks 218 16>, - <&k3_clks 218 22>; + <&k3_clks 218 7>; }; &serdes_wiz4 { @@ -992,3 +1113,93 @@ }; }; }; + +&mcu_mcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver1>; +}; + +&mcu_mcan1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver2>; +}; + +&main_mcan6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan6_pins_default>; + phys = <&transceiver3>; +}; + +&main_mcan7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan7_pins_default>; + phys = <&transceiver4>; +}; + +&ospi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + + partitions { + bootph-all; + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "ospi.tispl"; + reg = <0x100000 0x200000>; + }; + + partition@300000 { + label = "ospi.u-boot"; + reg = <0x300000 0x400000>; + }; + + partition@700000 { + label = "ospi.env"; + reg = <0x700000 0x40000>; + }; + + partition@740000 { + label = "ospi.env.backup"; + reg = <0x740000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + bootph-pre-ram; + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; +}; diff --git a/src/arm64/ti/k3-j7200-common-proc-board.dts b/src/arm64/ti/k3-j7200-common-proc-board.dts index cee2b4b0eb8..6593c5da82c 100644 --- a/src/arm64/ti/k3-j7200-common-proc-board.dts +++ b/src/arm64/ti/k3-j7200-common-proc-board.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -88,27 +88,56 @@ states = <1800000 0x0>, <3300000 0x1>; }; + + transceiver1: can-phy1 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; + standby-gpios = <&wkup_gpio0 58 GPIO_ACTIVE_LOW>; + enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>; + }; + + transceiver2: can-phy2 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; + standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; + }; + + transceiver3: can-phy3 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>; + enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; + mux-states = <&mux0 1>; + }; }; &wkup_pmx0 { +}; + +&wkup_pmx2 { mcu_uart0_pins_default: mcu-uart0-default-pins { pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ - J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ - J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */ - J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ + J721E_WKUP_IOPAD(0x90, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */ + J721E_WKUP_IOPAD(0x94, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ + J721E_WKUP_IOPAD(0x8c, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ + J721E_WKUP_IOPAD(0x88, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ >; }; wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ - J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ + J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0x4c, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ >; }; -}; -&wkup_pmx2 { mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ @@ -138,6 +167,33 @@ J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ >; }; + + mcu_mcan0_pins_default: mcu-mcan0-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x54, PIN_INPUT, 0) /* (A17) MCU_MCAN0_RX */ + J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (A16) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x6c, PIN_INPUT, 0) /* (B16) WKUP_GPIO0_5.MCU_MCAN1_RX */ + J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (D13) WKUP_GPIO0_4.MCU_MCAN1_TX */ + >; + }; + + mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x58, PIN_INPUT, 7) /* (B18) WKUP_GPIO0_0 */ + J721E_WKUP_IOPAD(0x40, PIN_INPUT, 7) /* (B17) MCU_SPI0_D1 */ + >; + }; + + mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x60, PIN_INPUT, 7) /* (D14) WKUP_GPIO0_2 */ + >; + }; }; &main_pmx0 { @@ -189,6 +245,13 @@ J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ >; }; + + main_mcan3_pins_default: main-mcan3-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x3c, PIN_INPUT, 0) /* (W16) MCAN3_RX */ + J721E_IOPAD(0x38, PIN_OUTPUT, 0) /* (Y21) MCAN3_TX */ + >; + }; }; &main_pmx1 { @@ -210,7 +273,6 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_uart0_pins_default>; - clock-frequency = <96000000>; }; &main_uart0 { @@ -382,15 +444,30 @@ }; &pcie1_rc { + status = "okay"; reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; phys = <&serdes0_pcie_link>; phy-names = "pcie-phy"; num-lanes = <2>; }; -&pcie1_ep { - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; - status = "disabled"; +&mcu_mcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver1>; +}; + +&mcu_mcan1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver2>; +}; + +&main_mcan3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan3_pins_default>; + phys = <&transceiver3>; }; diff --git a/src/arm64/ti/k3-j7200-evm-quad-port-eth-exp.dtso b/src/arm64/ti/k3-j7200-evm-quad-port-eth-exp.dtso index 32d905235ed..6432ca08ee8 100644 --- a/src/arm64/ti/k3-j7200-evm-quad-port-eth-exp.dtso +++ b/src/arm64/ti/k3-j7200-evm-quad-port-eth-exp.dtso @@ -1,9 +1,9 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * DT Overlay for CPSW5G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with * J7200 board. * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-j7200-main.dtsi b/src/arm64/ti/k3-j7200-main.dtsi index da67bf8fe70..657f9cc9f4e 100644 --- a/src/arm64/ti/k3-j7200-main.dtsi +++ b/src/arm64/ti/k3-j7200-main.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J7200 SoC Family Main Domain peripherals * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ / { @@ -33,10 +33,11 @@ ranges = <0x00 0x00 0x00100000 0x1c000>; serdes_ln_ctrl: mux-controller@4080 { - compatible = "mmio-mux"; + compatible = "reg-mux"; + reg = <0x4080 0x20>; #mux-control-cells = <1>; - mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ - <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ + mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ + <0x8 0x3>, <0xc 0x3>; /* SERDES0 lane2/3 select */ }; cpsw0_phy_gmii_sel: phy@4044 { @@ -47,9 +48,10 @@ }; usb_serdes_mux: mux-controller@4000 { - compatible = "mmio-mux"; + compatible = "reg-mux"; + reg = <0x4000 0x4>; #mux-control-cells = <1>; - mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ + mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ }; }; @@ -399,7 +401,7 @@ /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ main_timerio_input: pinctrl@104200 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; reg = <0x0 0x104200 0x0 0x50>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; @@ -408,7 +410,7 @@ /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ main_timerio_output: pinctrl@104280 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; reg = <0x0 0x104280 0x0 0x20>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; @@ -416,7 +418,7 @@ }; main_pmx0: pinctrl@11c000 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x11c000 0x00 0x10c>; #pinctrl-cells = <1>; @@ -425,7 +427,7 @@ }; main_pmx1: pinctrl@11c11c { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x11c11c 0x00 0xc>; #pinctrl-cells = <1>; @@ -770,26 +772,7 @@ ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - }; - - pcie1_ep: pcie-ep@2910000 { - compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; - reg = <0x00 0x02910000 0x00 0x1000>, - <0x00 0x02917000 0x00 0x400>, - <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = ; - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; - max-link-speed = <3>; - num-lanes = <4>; - power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 240 6>; - clock-names = "fck"; - max-functions = /bits/ 8 <6>; - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; - dma-coherent; + status = "disabled"; }; usbss0: cdns-usb@4104000 { @@ -895,6 +878,276 @@ status = "disabled"; }; + main_mcan0: can@2701000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02701000 0x00 0x200>, + <0x00 0x02708000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 156 0>, <&k3_clks 156 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan1: can@2711000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02711000 0x00 0x200>, + <0x00 0x02718000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 158 0>, <&k3_clks 158 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan2: can@2721000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02721000 0x00 0x200>, + <0x00 0x02728000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 160 0>, <&k3_clks 160 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan3: can@2731000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02731000 0x00 0x200>, + <0x00 0x02738000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 161 0>, <&k3_clks 161 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan4: can@2741000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02741000 0x00 0x200>, + <0x00 0x02748000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 162 0>, <&k3_clks 162 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan5: can@2751000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02751000 0x00 0x200>, + <0x00 0x02758000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 163 0>, <&k3_clks 163 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan6: can@2761000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02761000 0x00 0x200>, + <0x00 0x02768000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 164 0>, <&k3_clks 164 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan7: can@2771000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02771000 0x00 0x200>, + <0x00 0x02778000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 165 0>, <&k3_clks 165 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan8: can@2781000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02781000 0x00 0x200>, + <0x00 0x02788000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 166 0>, <&k3_clks 166 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan9: can@2791000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02791000 0x00 0x200>, + <0x00 0x02798000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 167 0>, <&k3_clks 167 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan10: can@27a1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027a1000 0x00 0x200>, + <0x00 0x027a8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 168 0>, <&k3_clks 168 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan11: can@27b1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027b1000 0x00 0x200>, + <0x00 0x027b8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 169 0>, <&k3_clks 169 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan12: can@27c1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027c1000 0x00 0x200>, + <0x00 0x027c8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 170 0>, <&k3_clks 170 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan13: can@27d1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027d1000 0x00 0x200>, + <0x00 0x027d8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 171 0>, <&k3_clks 171 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan14: can@2681000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02681000 0x00 0x200>, + <0x00 0x02688000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 150 0>, <&k3_clks 150 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan15: can@2691000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02691000 0x00 0x200>, + <0x00 0x02698000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 151 0>, <&k3_clks 151 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan16: can@26a1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x026a1000 0x00 0x200>, + <0x00 0x026a8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 152 0>, <&k3_clks 152 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan17: can@26b1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x026b1000 0x00 0x200>, + <0x00 0x026b8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 153 0>, <&k3_clks 153 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + main_spi0: spi@2100000 { compatible = "ti,am654-mcspi","ti,omap4-mcspi"; reg = <0x00 0x02100000 0x00 0x400>; diff --git a/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi b/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi index 60b26374ae0..7cf21c99956 100644 --- a/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi +++ b/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu_wakeup { @@ -192,7 +192,7 @@ /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ mcu_timerio_input: pinctrl@40f04200 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; reg = <0x0 0x40f04200 0x0 0x28>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; @@ -202,7 +202,7 @@ /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ mcu_timerio_output: pinctrl@40f04280 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; reg = <0x0 0x40f04280 0x0 0x28>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; @@ -211,7 +211,7 @@ }; wkup_pmx0: pinctrl@4301c000 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c000 0x00 0x34>; #pinctrl-cells = <1>; @@ -220,7 +220,7 @@ }; wkup_pmx1: pinctrl@4301c038 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c038 0x00 0x8>; #pinctrl-cells = <1>; @@ -229,7 +229,7 @@ }; wkup_pmx2: pinctrl@4301c068 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c068 0x00 0xec>; #pinctrl-cells = <1>; @@ -238,7 +238,7 @@ }; wkup_pmx3: pinctrl@4301c174 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c174 0x00 0x20>; #pinctrl-cells = <1>; @@ -518,17 +518,18 @@ status = "disabled"; }; - fss: syscon@47000000 { - compatible = "syscon", "simple-mfd"; + fss: bus@47000000 { + compatible = "simple-bus"; reg = <0x00 0x47000000 0x00 0x100>; #address-cells = <2>; #size-cells = <2>; ranges; - hbmc_mux: hbmc-mux { - compatible = "mmio-mux"; + hbmc_mux: mux-controller@47000004 { + compatible = "reg-mux"; + reg = <0x00 0x47000004 0x00 0x4>; #mux-control-cells = <1>; - mux-reg-masks = <0x4 0x2>; /* HBMC select */ + mux-reg-masks = <0x0 0x2>; /* HBMC select */ }; hbmc: hyperbus@47034000 { @@ -655,4 +656,34 @@ ti,esm-pins = <95>; bootph-pre-ram; }; + + mcu_mcan0: can@40528000 { + compatible = "bosch,m_can"; + reg = <0x00 0x40528000 0x00 0x200>, + <0x00 0x40500000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 172 0>, <&k3_clks 172 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + mcu_mcan1: can@40568000 { + compatible = "bosch,m_can"; + reg = <0x00 0x40568000 0x00 0x200>, + <0x00 0x40540000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 173 0>, <&k3_clks 173 2>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; }; diff --git a/src/arm64/ti/k3-j7200-som-p0.dtsi b/src/arm64/ti/k3-j7200-som-p0.dtsi index ea47f10d393..7e6a584ac6f 100644 --- a/src/arm64/ti/k3-j7200-som-p0.dtsi +++ b/src/arm64/ti/k3-j7200-som-p0.dtsi @@ -1,10 +1,12 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; +#include + #include "k3-j7200.dtsi" / { @@ -80,6 +82,25 @@ no-map; }; }; + + mux0: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>; + }; + + mux1: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>; + }; + + transceiver0: can-phy0 { + /* standby pin has been grounded by default */ + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; }; &wkup_pmx0 { @@ -142,6 +163,13 @@ J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ >; }; + + main_mcan0_pins_default: main-mcan0-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x24, PIN_INPUT, 0) /* (V20) MCAN0_RX */ + J721E_IOPAD(0x20, PIN_OUTPUT, 0) /* (V18) MCAN0_TX */ + >; + }; }; &hbmc { @@ -222,25 +250,25 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; @@ -478,3 +506,10 @@ }; }; }; + +&main_mcan0 { + status = "okay"; + pinctrl-0 = <&main_mcan0_pins_default>; + pinctrl-names = "default"; + phys = <&transceiver0>; +}; diff --git a/src/arm64/ti/k3-j7200-thermal.dtsi b/src/arm64/ti/k3-j7200-thermal.dtsi index e7e3a643a6f..2d22a95a6fd 100644 --- a/src/arm64/ti/k3-j7200-thermal.dtsi +++ b/src/arm64/ti/k3-j7200-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include diff --git a/src/arm64/ti/k3-j7200.dtsi b/src/arm64/ti/k3-j7200.dtsi index ef73e6d7e85..d411911fdf7 100644 --- a/src/arm64/ti/k3-j7200.dtsi +++ b/src/arm64/ti/k3-j7200.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J7200 SoC Family * - * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include diff --git a/src/arm64/ti/k3-j721e-beagleboneai64.dts b/src/arm64/ti/k3-j721e-beagleboneai64.dts index 2f954729f35..a2925555fe8 100644 --- a/src/arm64/ti/k3-j721e-beagleboneai64.dts +++ b/src/arm64/ti/k3-j721e-beagleboneai64.dts @@ -1,9 +1,9 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * https://beagleboard.org/ai-64 - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ - * Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation - * Copyright (C) 2022 Robert Nelson, BeagleBoard.org Foundation + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Jason Kridner, BeagleBoard.org Foundation + * Copyright (C) 2022-2024 Robert Nelson, BeagleBoard.org Foundation */ /dts-v1/; @@ -936,58 +936,58 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &c66_0 { status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; + mboxes = <&mailbox0_cluster3 &mbox_c66_0>; memory-region = <&c66_0_dma_memory_region>, <&c66_0_memory_region>; }; &c66_1 { status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; + mboxes = <&mailbox0_cluster3 &mbox_c66_1>; memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; }; &c71_0 { status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; diff --git a/src/arm64/ti/k3-j721e-common-proc-board.dts b/src/arm64/ti/k3-j721e-common-proc-board.dts index fe5207ac7d8..8230d53cd69 100644 --- a/src/arm64/ti/k3-j721e-common-proc-board.dts +++ b/src/arm64/ti/k3-j721e-common-proc-board.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2019-2024 Texas Instruments Incorporated - https://www.ti.com/ * * Product Link: https://www.ti.com/tool/J721EXCPXEVM */ diff --git a/src/arm64/ti/k3-j721e-evm-gesi-exp-board.dtso b/src/arm64/ti/k3-j721e-evm-gesi-exp-board.dtso index 6a7d37575da..f84aa9f9454 100644 --- a/src/arm64/ti/k3-j721e-evm-gesi-exp-board.dtso +++ b/src/arm64/ti/k3-j721e-evm-gesi-exp-board.dtso @@ -1,11 +1,11 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * DT Overlay for CPSW9G in RGMII mode using J7 GESI EXP BRD board with * J721E board. * * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-j721e-evm-pcie0-ep.dtso b/src/arm64/ti/k3-j721e-evm-pcie0-ep.dtso index 0c82a13b65a..4062709d657 100644 --- a/src/arm64/ti/k3-j721e-evm-pcie0-ep.dtso +++ b/src/arm64/ti/k3-j721e-evm-pcie0-ep.dtso @@ -1,11 +1,11 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * DT Overlay for enabling PCIE0 instance in Endpoint Configuration with the * J7 common processor board. * * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-j721e-evm-quad-port-eth-exp.dtso b/src/arm64/ti/k3-j721e-evm-quad-port-eth-exp.dtso index d4c51ffc3d6..8376fa4b6ee 100644 --- a/src/arm64/ti/k3-j721e-evm-quad-port-eth-exp.dtso +++ b/src/arm64/ti/k3-j721e-evm-quad-port-eth-exp.dtso @@ -1,9 +1,9 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with * J721E board. * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-j721e-main.dtsi b/src/arm64/ti/k3-j721e-main.dtsi index 2569b4c08ff..c7eafbc862f 100644 --- a/src/arm64/ti/k3-j721e-main.dtsi +++ b/src/arm64/ti/k3-j721e-main.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J721E SoC Family Main Domain peripherals * - * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include #include @@ -45,15 +45,15 @@ ranges = <0x0 0x0 0x00100000 0x1c000>; serdes_ln_ctrl: mux-controller@4080 { - compatible = "mmio-mux"; - reg = <0x00004080 0x50>; + compatible = "reg-mux"; + reg = <0x4080 0x50>; #mux-control-cells = <1>; - mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ - <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ - <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ - <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ - <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; - /* SERDES4 lane0/1/2/3 select */ + mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ + <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */ + <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */ + <0x30 0x3>, <0x34 0x3>, /* SERDES3 lane0/1 select */ + <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */ + <0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */ idle-states = , , , , , , @@ -70,10 +70,11 @@ }; usb_serdes_mux: mux-controller@4000 { - compatible = "mmio-mux"; + compatible = "reg-mux"; + reg = <0x4000 0x20>; #mux-control-cells = <1>; - mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ - <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ + mux-reg-masks = <0x0 0x8000000>, /* USB0 to SERDES0/3 mux */ + <0x10 0x8000000>; /* USB1 to SERDES1/2 mux */ }; ehrpwm_tbclk: clock-controller@4140 { @@ -572,6 +573,128 @@ pinctrl-single,function-mask = <0x0000001f>; }; + ti_csi2rx0: ticsi2rx@4500000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x0 0x4500000 0x0 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_udmap 0x4940>; + dma-names = "rx0"; + power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x0 0x4504000 0x0 0x1000>; + clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>, + <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x0 0x4510000 0x0 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_udmap 0x4960>; + dma-names = "rx0"; + power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x0 0x4514000 0x0 0x1000>; + clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>, + <&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy1>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + compatible = "cdns,dphy-rx"; + reg = <0x0 0x4580000 0x0 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy1: phy@4590000 { + compatible = "cdns,dphy-rx"; + reg = <0x0 0x4590000 0x0 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + serdes_wiz0: wiz@5000000 { compatible = "ti,j721e-wiz-16g"; #address-cells = <1>; diff --git a/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi b/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi index a74912d9e4d..4618b697fbc 100644 --- a/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi +++ b/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals * - * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu_wakeup { @@ -353,9 +353,9 @@ hbmc_mux: mux-controller@47000004 { compatible = "reg-mux"; - reg = <0x00 0x47000004 0x00 0x2>; + reg = <0x00 0x47000004 0x00 0x4>; #mux-control-cells = <1>; - mux-reg-masks = <0x4 0x2>; /* HBMC select */ + mux-reg-masks = <0x0 0x2>; /* HBMC select */ }; hbmc: hyperbus@47034000 { diff --git a/src/arm64/ti/k3-j721e-sk-csi2-dual-imx219.dtso b/src/arm64/ti/k3-j721e-sk-csi2-dual-imx219.dtso new file mode 100644 index 00000000000..47bb5480b5b --- /dev/null +++ b/src/arm64/ti/k3-j721e-sk-csi2-dual-imx219.dtso @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for dual RPi Camera V2.1 (Sony IMX219) interfaced with CSI2 + * on J721E SK, AM68 SK or AM69-SK board. + * https://datasheets.raspberrypi.org/camera/camera-v2-schematic.pdf + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + clk_imx219_fixed: imx219-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&csi_mux { + idle-state = <1>; +}; + +/* CAM0 I2C */ +&cam0_i2c { + #address-cells = <1>; + #size-cells = <0>; + imx219_0: imx219-0@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +/* CAM1 I2C */ +&cam1_i2c { + #address-cells = <1>; + #size-cells = <0>; + imx219_1: imx219-1@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + + port { + csi2_cam1: endpoint { + remote-endpoint = <&csi2rx1_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; +}; + +&dphy0 { + status = "okay"; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&cdns_csi2rx1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx1_in_sensor: endpoint { + remote-endpoint = <&csi2_cam1>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; +}; + +&dphy1 { + status = "okay"; +}; + +&ti_csi2rx1 { + status = "okay"; +}; diff --git a/src/arm64/ti/k3-j721e-sk.dts b/src/arm64/ti/k3-j721e-sk.dts index 188dfe291a3..0c4575ad8d7 100644 --- a/src/arm64/ti/k3-j721e-sk.dts +++ b/src/arm64/ti/k3-j721e-sk.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ * * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM */ @@ -286,6 +286,15 @@ }; }; }; + + csi_mux: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&main_gpio0 88 GPIO_ACTIVE_HIGH>; + idle-state = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&main_csi_mux_sel_pins_default>; + }; }; &main_pmx0 { @@ -352,6 +361,12 @@ >; }; + main_csi_mux_sel_pins_default: main-csi-mux-sel-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x164, PIN_OUTPUT, 7) /* (V29) RGMII5_TD2 */ + >; + }; + dp0_pins_default: dp0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ @@ -574,7 +589,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pmic_irq_pins_default>; interrupt-parent = <&wkup_gpio0>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; gpio-controller; #gpio-cells = <2>; ti,primary-pmic; @@ -651,7 +666,7 @@ reg = <0x4c>; system-power-controller; interrupt-parent = <&wkup_gpio0>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; gpio-controller; #gpio-cells = <2>; buck1234-supply = <&vsys_3v3>; @@ -858,14 +873,14 @@ reg = <0x70>; /* CSI0 I2C */ - i2c@0 { + cam0_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; }; /* CSI1 I2C */ - i2c@1 { + cam1_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; @@ -1168,58 +1183,58 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &c66_0 { status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; + mboxes = <&mailbox0_cluster3 &mbox_c66_0>; memory-region = <&c66_0_dma_memory_region>, <&c66_0_memory_region>; }; &c66_1 { status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; + mboxes = <&mailbox0_cluster3 &mbox_c66_1>; memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; }; &c71_0 { status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; diff --git a/src/arm64/ti/k3-j721e-som-p0.dtsi b/src/arm64/ti/k3-j721e-som-p0.dtsi index a75611eec79..1fae6495db0 100644 --- a/src/arm64/ti/k3-j721e-som-p0.dtsi +++ b/src/arm64/ti/k3-j721e-som-p0.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2019-2024 Texas Instruments Incorporated - https://www.ti.com/ * * Product Link: https://www.ti.com/tool/J721EXSOMXEVM */ @@ -549,58 +549,58 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &c66_0 { status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; + mboxes = <&mailbox0_cluster3 &mbox_c66_0>; memory-region = <&c66_0_dma_memory_region>, <&c66_0_memory_region>; }; &c66_1 { status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; + mboxes = <&mailbox0_cluster3 &mbox_c66_1>; memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; }; &c71_0 { status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; diff --git a/src/arm64/ti/k3-j721e-thermal.dtsi b/src/arm64/ti/k3-j721e-thermal.dtsi index c2523279001..927f7614ae7 100644 --- a/src/arm64/ti/k3-j721e-thermal.dtsi +++ b/src/arm64/ti/k3-j721e-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include diff --git a/src/arm64/ti/k3-j721e.dtsi b/src/arm64/ti/k3-j721e.dtsi index a200810df54..5a72c518ceb 100644 --- a/src/arm64/ti/k3-j721e.dtsi +++ b/src/arm64/ti/k3-j721e.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J721E SoC Family * - * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include diff --git a/src/arm64/ti/k3-j721s2-common-proc-board.dts b/src/arm64/ti/k3-j721s2-common-proc-board.dts index c6b85bbf9a1..c5a0b7cbb14 100644 --- a/src/arm64/ti/k3-j721s2-common-proc-board.dts +++ b/src/arm64/ti/k3-j721s2-common-proc-board.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ * * Common Processor Board: https://www.ti.com/tool/J721EXCPXEVM */ @@ -147,6 +147,13 @@ >; }; + main_i2c5_pins_default: main-i2c5-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x01c, PIN_INPUT, 8) /* (Y24) MCAN15_TX.I2C5_SCL */ + J721S2_IOPAD(0x018, PIN_INPUT, 8) /* (W23) MCAN14_RX.I2C5_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ @@ -190,8 +197,6 @@ &wkup_pmx2 { wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */ - J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */ J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ >; @@ -356,6 +361,24 @@ }; }; +&main_i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c5_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + exp5: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", + "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO2", + "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", + "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; + }; +}; + &main_sdhci0 { /* eMMC */ status = "okay"; diff --git a/src/arm64/ti/k3-j721s2-evm-gesi-exp-board.dtso b/src/arm64/ti/k3-j721s2-evm-gesi-exp-board.dtso index b78feea31b5..1be28283c7d 100644 --- a/src/arm64/ti/k3-j721s2-evm-gesi-exp-board.dtso +++ b/src/arm64/ti/k3-j721s2-evm-gesi-exp-board.dtso @@ -1,10 +1,10 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * DT Overlay for MAIN CPSW2G using GESI Expansion Board with J7 common processor board. * * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-j721s2-evm-pcie1-ep.dtso b/src/arm64/ti/k3-j721s2-evm-pcie1-ep.dtso index 43568eb67d9..5ff390915b7 100644 --- a/src/arm64/ti/k3-j721s2-evm-pcie1-ep.dtso +++ b/src/arm64/ti/k3-j721s2-evm-pcie1-ep.dtso @@ -1,11 +1,11 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * DT Overlay for enabling PCIE1 instance in Endpoint Configuration with the * J7 common processor board. * * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/src/arm64/ti/k3-j721s2-main.dtsi b/src/arm64/ti/k3-j721s2-main.dtsi index ea7f2b2ab16..b70c8615e3c 100644 --- a/src/arm64/ti/k3-j721s2-main.dtsi +++ b/src/arm64/ti/k3-j721s2-main.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J721S2 SoC Family Main Domain peripherals * - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include @@ -45,7 +45,7 @@ ranges = <0x00 0x00 0x00104000 0x18000>; usb_serdes_mux: mux-controller@0 { - compatible = "mmio-mux"; + compatible = "reg-mux"; reg = <0x0 0x4>; #mux-control-cells = <1>; mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ @@ -58,11 +58,11 @@ }; serdes_ln_ctrl: mux-controller@80 { - compatible = "mmio-mux"; + compatible = "reg-mux"; reg = <0x80 0x10>; #mux-control-cells = <1>; - mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */ - <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */ + mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ + <0x8 0x3>, <0xc 0x3>; /* SERDES0 lane2/3 select */ }; ehrpwm_tbclk: clock-controller@140 { @@ -716,6 +716,14 @@ status = "disabled"; }; + vpu: video-codec@4210000 { + compatible = "ti,j721s2-wave521c", "cnm,wave521c"; + reg = <0x00 0x4210000 0x00 0x10000>; + interrupts = ; + clocks = <&k3_clks 179 2>; + power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; + }; + main_sdhci0: mmc@4f80000 { compatible = "ti,j721e-sdhci-8bit"; reg = <0x00 0x04f80000 0x00 0x1000>, @@ -1122,7 +1130,6 @@ ti,sci-dev-id = <225>; ti,sci-rm-range-rchan = <0x21>; ti,sci-rm-range-tchan = <0x22>; - status = "disabled"; }; cpts@310d0000 { @@ -1233,6 +1240,128 @@ }; }; + ti_csi2rx0: ticsi2rx@4500000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x04500000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x4940 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04504000 0x00 0x1000>; + clocks = <&k3_clks 38 3>, <&k3_clks 38 1>, <&k3_clks 38 3>, + <&k3_clks 38 3>, <&k3_clks 38 4>, <&k3_clks 38 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x04510000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x4960 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04514000 0x00 0x1000>; + clocks = <&k3_clks 39 3>, <&k3_clks 39 1>, <&k3_clks 39 3>, + <&k3_clks 39 3>, <&k3_clks 39 4>, <&k3_clks 39 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy1>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x04580000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy1: phy@4590000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x04590000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + serdes_wiz0: wiz@5060000 { compatible = "ti,j721s2-wiz-10g"; #address-cells = <1>; diff --git a/src/arm64/ti/k3-j721s2-mcu-wakeup.dtsi b/src/arm64/ti/k3-j721s2-mcu-wakeup.dtsi index 80aa33c58a4..eaf7f709440 100644 --- a/src/arm64/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/src/arm64/ti/k3-j721s2-mcu-wakeup.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals * - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu_wakeup { @@ -663,7 +663,7 @@ compatible = "ti,j7200-vtm"; reg = <0x00 0x42040000 0x0 0x350>, <0x00 0x42050000 0x0 0x350>; - power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>; + power-domains = <&k3_pds 180 TI_SCI_PD_SHARED>; #thermal-sensor-cells = <1>; }; diff --git a/src/arm64/ti/k3-j721s2-som-p0.dtsi b/src/arm64/ti/k3-j721s2-som-p0.dtsi index da3237b23b6..623c8421525 100644 --- a/src/arm64/ti/k3-j721s2-som-p0.dtsi +++ b/src/arm64/ti/k3-j721s2-som-p0.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * SoM: https://www.ti.com/lit/zip/sprr439 * - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -504,51 +504,51 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &c71_0 { status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; &c71_1 { status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>; + mboxes = <&mailbox0_cluster4 &mbox_c71_1>; memory-region = <&c71_1_dma_memory_region>, <&c71_1_memory_region>; }; diff --git a/src/arm64/ti/k3-j721s2-thermal.dtsi b/src/arm64/ti/k3-j721s2-thermal.dtsi index f7b1a15b8fa..e3ef61c1658 100644 --- a/src/arm64/ti/k3-j721s2-thermal.dtsi +++ b/src/arm64/ti/k3-j721s2-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include diff --git a/src/arm64/ti/k3-j721s2.dtsi b/src/arm64/ti/k3-j721s2.dtsi index 1f636acd4ee..be4502fe1c9 100644 --- a/src/arm64/ti/k3-j721s2.dtsi +++ b/src/arm64/ti/k3-j721s2.dtsi @@ -1,10 +1,10 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J721S2 SoC Family * * TRM (SPRUJ28 NOVEMBER 2021): https://www.ti.com/lit/pdf/spruj28 * - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ * */ diff --git a/src/arm64/ti/k3-j722s-evm.dts b/src/arm64/ti/k3-j722s-evm.dts new file mode 100644 index 00000000000..cee3a8661d5 --- /dev/null +++ b/src/arm64/ti/k3-j722s-evm.dts @@ -0,0 +1,383 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree file for the J722S EVM + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * + * Schematics: https://www.ti.com/lit/zip/sprr495 + */ + +/dts-v1/; + +#include +#include "k3-j722s.dtsi" + +/ { + compatible = "ti,j722s-evm", "ti,j722s"; + model = "Texas Instruments J722S EVM"; + + aliases { + serial0 = &wkup_uart0; + serial2 = &main_uart0; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + }; + + chosen { + stdout-path = &main_uart0; + }; + + memory@80000000 { + /* 8G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000001 0x80000000>; + device_type = "memory"; + bootph-pre-ram; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + }; + + vmain_pd: regulator-0 { + /* TPS65988 PD CONTROLLER OUTPUT */ + compatible = "regulator-fixed"; + regulator-name = "vmain_pd"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vsys_5v0: regulator-vsys5v0 { + /* Output of LM5140 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-mmc1 { + /* TPS22918DBVR */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&exp1 15 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vdd_sd_dv: regulator-TLV71033 { + compatible = "regulator-gpio"; + regulator-name = "tlv71033"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vsys_5v0>; + gpios = <&main_gpio0 70 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + + vsys_io_1v8: regulator-vsys-io-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_io_1v2: regulator-vsys-io-1v2 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&main_pmx0 { + + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D23) I2C0_SCL */ + J722S_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (B22) I2C0_SDA */ + >; + bootph-all; + }; + + main_uart0_pins_default: main-uart0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x01c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ + J722S_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ + >; + bootph-all; + }; + + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0120, PIN_INPUT, 7) /* (F27) MMC2_CMD.GPIO0_70 */ + >; + bootph-all; + }; + + main_mmc1_pins_default: main-mmc1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x023c, PIN_INPUT, 0) /* (H22) MMC1_CMD */ + J722S_IOPAD(0x0234, PIN_OUTPUT, 0) /* (H24) MMC1_CLK */ + J722S_IOPAD(0x0230, PIN_INPUT, 0) /* (H23) MMC1_DAT0 */ + J722S_IOPAD(0x022c, PIN_INPUT_PULLUP, 0) /* (H20) MMC1_DAT1 */ + J722S_IOPAD(0x0228, PIN_INPUT_PULLUP, 0) /* (J23) MMC1_DAT2 */ + J722S_IOPAD(0x0224, PIN_INPUT_PULLUP, 0) /* (H25) MMC1_DAT3 */ + J722S_IOPAD(0x0240, PIN_INPUT, 0) /* (B24) MMC1_SDCD */ + >; + bootph-all; + }; + + mdio_pins_default: mdio-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */ + J722S_IOPAD(0x015c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */ + >; + }; + + ospi0_pins_default: ospi0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0000, PIN_OUTPUT, 0) /* (L24) OSPI0_CLK */ + J722S_IOPAD(0x002c, PIN_OUTPUT, 0) /* (K26) OSPI0_CSn0 */ + J722S_IOPAD(0x000c, PIN_INPUT, 0) /* (K27) OSPI0_D0 */ + J722S_IOPAD(0x0010, PIN_INPUT, 0) /* (L27) OSPI0_D1 */ + J722S_IOPAD(0x0014, PIN_INPUT, 0) /* (L26) OSPI0_D2 */ + J722S_IOPAD(0x0018, PIN_INPUT, 0) /* (L25) OSPI0_D3 */ + J722S_IOPAD(0x001c, PIN_INPUT, 0) /* (L21) OSPI0_D4 */ + J722S_IOPAD(0x0020, PIN_INPUT, 0) /* (M26) OSPI0_D5 */ + J722S_IOPAD(0x0024, PIN_INPUT, 0) /* (N27) OSPI0_D6 */ + J722S_IOPAD(0x0028, PIN_INPUT, 0) /* (M27) OSPI0_D7 */ + J722S_IOPAD(0x0008, PIN_INPUT, 0) /* (L22) OSPI0_DQS */ + >; + bootph-all; + }; + + rgmii1_pins_default: rgmii1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x014c, PIN_INPUT, 0) /* (AC25) RGMII1_RD0 */ + J722S_IOPAD(0x0150, PIN_INPUT, 0) /* (AD27) RGMII1_RD1 */ + J722S_IOPAD(0x0154, PIN_INPUT, 0) /* (AE24) RGMII1_RD2 */ + J722S_IOPAD(0x0158, PIN_INPUT, 0) /* (AE26) RGMII1_RD3 */ + J722S_IOPAD(0x0148, PIN_INPUT, 0) /* (AE27) RGMII1_RXC */ + J722S_IOPAD(0x0144, PIN_INPUT, 0) /* (AD23) RGMII1_RX_CTL */ + J722S_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AF27) RGMII1_TD0 */ + J722S_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AE23) RGMII1_TD1 */ + J722S_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AG25) RGMII1_TD2 */ + J722S_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AF24) RGMII1_TD3 */ + J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */ + J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ + >; + }; +}; + +&cpsw3g { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins_default>; +}; + +&cpsw3g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins_default>; + + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&main_gpio1 { + status = "okay"; +}; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + status = "okay"; + bootph-all; +}; + +&mcu_pmx0 { + + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */ + J722S_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */ + J722S_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */ + J722S_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */ + >; + bootph-all; + }; + + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x04c, PIN_INPUT_PULLUP, 0) /* (C7) WKUP_I2C0_SCL */ + J722S_MCU_IOPAD(0x050, PIN_INPUT_PULLUP, 0) /* (C6) WKUP_I2C1_SDA */ + >; + bootph-all; + }; +}; + +&wkup_uart0 { + /* WKUP UART0 is used by Device Manager firmware */ + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; + status = "reserved"; + bootph-all; +}; + +&wkup_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + status = "okay"; + bootph-all; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + status = "okay"; + bootph-all; + + exp1: gpio@23 { + compatible = "ti,tca6424"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "TRC_MUX_SEL", "OSPI/ONAND_MUX_SEL", + "MCASP1_FET_SEL", "CTRL_PM_I2C_OE#", + "CSI_VIO_SEL", "USB2.0_MUX_SEL", + "CSI01_MUX_SEL_2", "CSI23_MUX_SEL_2", + "LMK1_OE1", "LMK1_OE0", + "LMK2_OE0", "LMK2_OE1", + "GPIO_RGMII1_RST#", "GPIO_AUD_RSTn", + "GPIO_eMMC_RSTn", "GPIO_uSD_PWR_EN", + "USER_LED2", "MCAN0_STB", + "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#", + "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN", + "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ"; + }; +}; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + bootph-all; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x00 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; + +}; + +&sdhci1 { + /* SD/MMC */ + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; + no-1-8-v; + status = "okay"; + bootph-all; +}; diff --git a/src/arm64/ti/k3-j722s.dtsi b/src/arm64/ti/k3-j722s.dtsi new file mode 100644 index 00000000000..c75744edb14 --- /dev/null +++ b/src/arm64/ti/k3-j722s.dtsi @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree Source for J722S SoC Family + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include +#include +#include + +#include "k3-am62p5.dtsi" + +/ { + model = "Texas Instruments K3 J722S SoC"; + compatible = "ti,j722s"; + + cbass_main: bus@f0000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ + <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ + <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ + <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ + <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ + <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_0 */ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ + <0x00 0x0fd80000 0x00 0x0fd80000 0x00 0x00080000>, /* GPU */ + <0x00 0x0fd20000 0x00 0x0fd20000 0x00 0x00000100>, /* JPEGENC0_CORE */ + <0x00 0x0fd20200 0x00 0x0fd20200 0x00 0x00000200>, /* JPEGENC0_CORE_MMU */ + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ + <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ + <0x00 0x301C0000 0x00 0x301C0000 0x00 0x00001000>, /* DPHY-TX */ + <0x00 0x30101000 0x00 0x30101000 0x00 0x00080100>, /* CSI window */ + <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ + <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */ + <0x00 0x30220000 0x00 0x30220000 0x00 0x00010000>, /* DSS1 */ + <0x00 0x30270000 0x00 0x30270000 0x00 0x00010000>, /* DSI-base1 */ + <0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI-base2 */ + <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ + <0x00 0x31200000 0x00 0x31200000 0x00 0x00040000>, /* USB1 DWC3 Core window */ + <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ + <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ + <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ + <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ + <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */ + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ + <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe0 DAT0 */ + <0x00 0x70000000 0x00 0x70000000 0x00 0x00040000>, /* OCSRAM */ + <0x00 0x78400000 0x00 0x78400000 0x00 0x00008000>, /* MAIN R5FSS0 ATCM */ + <0x00 0x78500000 0x00 0x78500000 0x00 0x00008000>, /* MAIN R5FSS0 BTCM */ + <0x00 0x7e000000 0x00 0x7e000000 0x00 0x00200000>, /* C7X_0 L2SRAM */ + <0x00 0x7e200000 0x00 0x7e200000 0x00 0x00200000>, /* C7X_1 L2SRAM */ + <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ + <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */ + + /* MCU Domain Range */ + <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, + <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, + <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, + <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, + <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, + + /* Wakeup Domain Range */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; + }; +}; + +/* Main domain overrides */ + +&inta_main_dmss { + ti,interrupt-ranges = <7 71 21>; +}; + +&oc_sram { + reg = <0x00 0x70000000 0x00 0x40000>; + ranges = <0x00 0x00 0x70000000 0x40000>; +}; diff --git a/src/arm64/ti/k3-j784s4-evm.dts b/src/arm64/ti/k3-j784s4-evm.dts index f34b92acc56..81fd7afac8c 100644 --- a/src/arm64/ti/k3-j784s4-evm.dts +++ b/src/arm64/ti/k3-j784s4-evm.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ * * EVM Board Schematics: https://www.ti.com/lit/zip/sprr458 */ @@ -31,6 +31,7 @@ memory@80000000 { device_type = "memory"; + bootph-all; /* 32G RAM */ reg = <0x00 0x80000000 0x00 0x80000000>, <0x08 0x80000000 0x07 0x80000000>; @@ -296,6 +297,13 @@ >; }; + main_i2c5_pins_default: main-i2c5-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x01c, PIN_INPUT, 8) /* (AG34) MCAN15_TX.I2C5_SCL */ + J784S4_IOPAD(0x018, PIN_INPUT, 8) /* (AK36) MCAN14_RX.I2C5_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { bootph-all; pinctrl-single,pins = < @@ -335,8 +343,6 @@ wkup_uart0_pins_default: wkup-uart0-default-pins { bootph-all; pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ - J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ >; @@ -760,6 +766,24 @@ }; }; +&main_i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c5_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + exp5: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", + "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO3", + "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", + "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; + }; +}; + &main_sdhci0 { bootph-all; /* eMMC */ diff --git a/src/arm64/ti/k3-j784s4-main.dtsi b/src/arm64/ti/k3-j784s4-main.dtsi index f2b720ed1e4..b67c37460a7 100644 --- a/src/arm64/ti/k3-j784s4-main.dtsi +++ b/src/arm64/ti/k3-j784s4-main.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J784S4 SoC Family Main Domain peripherals * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include @@ -52,12 +52,12 @@ compatible = "reg-mux"; reg = <0x00004080 0x30>; #mux-control-cells = <1>; - mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ - <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */ - <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ - <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */ - <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ - <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */ + mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ + <0x8 0x3>, <0xc 0x3>, /* SERDES0 lane2/3 select */ + <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */ + <0x18 0x3>, <0x1c 0x3>, /* SERDES1 lane2/3 select */ + <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */ + <0x28 0x3>, <0x2c 0x3>; /* SERDES2 lane2/3 select */ idle-states = , , , @@ -662,6 +662,204 @@ status = "disabled"; }; + ti_csi2rx0: ticsi2rx@4500000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x04500000 0x00 0x00001000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x4940 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04504000 0x00 0x00001000>; + clocks = <&k3_clks 72 2>, <&k3_clks 72 0>, <&k3_clks 72 2>, + <&k3_clks 72 2>, <&k3_clks 72 3>, <&k3_clks 72 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x04510000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x4960 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04514000 0x00 0x00001000>; + clocks = <&k3_clks 73 2>, <&k3_clks 73 0>, <&k3_clks 73 2>, + <&k3_clks 73 2>, <&k3_clks 73 3>, <&k3_clks 73 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy1>; + phy-names = "dphy"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx2: ticsi2rx@4520000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x04520000 0x00 0x00001000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x4980 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx2: csi-bridge@4524000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04524000 0x00 0x00001000>; + clocks = <&k3_clks 74 2>, <&k3_clks 74 0>, <&k3_clks 74 2>, + <&k3_clks 74 2>, <&k3_clks 74 3>, <&k3_clks 74 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy2>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi2_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi2_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi2_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi2_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x04580000 0x00 0x00001100>; + #phy-cells = <0>; + power-domains = <&k3_pds 212 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy1: phy@4590000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x04590000 0x00 0x00001100>; + #phy-cells = <0>; + power-domains = <&k3_pds 213 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy2: phy@45a0000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x045a0000 0x00 0x00001100>; + #phy-cells = <0>; + power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + vpu0: video-codec@4210000 { + compatible = "ti,j721s2-wave521c", "cnm,wave521c"; + reg = <0x00 0x4210000 0x00 0x10000>; + interrupts = ; + clocks = <&k3_clks 241 2>; + power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; + }; + + vpu1: video-codec@4220000 { + compatible = "ti,j721s2-wave521c", "cnm,wave521c"; + reg = <0x00 0x4220000 0x00 0x10000>; + interrupts = ; + clocks = <&k3_clks 242 2>; + power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; + }; + main_sdhci0: mmc@4f80000 { compatible = "ti,j721e-sdhci-8bit"; reg = <0x00 0x04f80000 0x00 0x1000>, @@ -1224,7 +1422,6 @@ ti,sci-dev-id = <281>; ti,sci-rm-range-rchan = <0x21>; ti,sci-rm-range-tchan = <0x22>; - status = "disabled"; }; cpts@310d0000 { diff --git a/src/arm64/ti/k3-j784s4-mcu-wakeup.dtsi b/src/arm64/ti/k3-j784s4-mcu-wakeup.dtsi index 3902a921d7e..77a8d99139e 100644 --- a/src/arm64/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/src/arm64/ti/k3-j784s4-mcu-wakeup.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J784S4 SoC Family MCU/WAKEUP Domain peripherals * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu_wakeup { @@ -628,7 +628,7 @@ compatible = "ti,j7200-vtm"; reg = <0x00 0x42040000 0x00 0x350>, <0x00 0x42050000 0x00 0x350>; - power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>; + power-domains = <&k3_pds 243 TI_SCI_PD_SHARED>; #thermal-sensor-cells = <1>; }; diff --git a/src/arm64/ti/k3-j784s4-thermal.dtsi b/src/arm64/ti/k3-j784s4-thermal.dtsi index f7b1a15b8fa..e3ef61c1658 100644 --- a/src/arm64/ti/k3-j784s4-thermal.dtsi +++ b/src/arm64/ti/k3-j784s4-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include diff --git a/src/arm64/ti/k3-j784s4.dtsi b/src/arm64/ti/k3-j784s4.dtsi index 4398c3a463e..6e2e92ffe74 100644 --- a/src/arm64/ti/k3-j784s4.dtsi +++ b/src/arm64/ti/k3-j784s4.dtsi @@ -1,10 +1,10 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J784S4 SoC Family * * TRM (SPRUJ43 JULY 2022): https://www.ti.com/lit/zip/spruj52 * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ * */ @@ -235,6 +235,8 @@ ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ + <0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */ + <0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/ <0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */ <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ diff --git a/src/arm64/ti/k3-pinctrl.h b/src/arm64/ti/k3-pinctrl.h index 2a4e0e084d6..4cd2df467d0 100644 --- a/src/arm64/ti/k3-pinctrl.h +++ b/src/arm64/ti/k3-pinctrl.h @@ -1,9 +1,9 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ /* * This header provides constants for pinctrl bindings for TI's K3 SoC * family. * - * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef DTS_ARM64_TI_K3_PINCTRL_H #define DTS_ARM64_TI_K3_PINCTRL_H @@ -59,6 +59,9 @@ #define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J722S_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J722S_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + #define J784S4_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define J784S4_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) diff --git a/src/arm64/ti/k3-serdes.h b/src/arm64/ti/k3-serdes.h index 21b4886c47b..a011ad893b4 100644 --- a/src/arm64/ti/k3-serdes.h +++ b/src/arm64/ti/k3-serdes.h @@ -1,8 +1,8 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ /* * This header provides constants for SERDES MUX for TI SoCs * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef DTS_ARM64_TI_K3_SERDES_H diff --git a/src/arm64/xilinx/zynqmp-clk-ccf.dtsi b/src/arm64/xilinx/zynqmp-clk-ccf.dtsi index ccaca29200b..dd4569e7bd9 100644 --- a/src/arm64/xilinx/zynqmp-clk-ccf.dtsi +++ b/src/arm64/xilinx/zynqmp-clk-ccf.dtsi @@ -230,18 +230,30 @@ &uart0 { clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; + assigned-clocks = <&zynqmp_clk UART0_REF>; }; &uart1 { clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; + assigned-clocks = <&zynqmp_clk UART1_REF>; +}; + +&usb0 { + clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; + assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; &dwc3_0 { - clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; + clocks = <&zynqmp_clk USB3_DUAL_REF>; +}; + +&usb1 { + clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; + assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; &dwc3_1 { - clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; + clocks = <&zynqmp_clk USB3_DUAL_REF>; }; &watchdog0 { diff --git a/src/arm64/xilinx/zynqmp-sck-kv-g-revA.dtso b/src/arm64/xilinx/zynqmp-sck-kv-g-revA.dtso index 92f4190d564..d7535a77b45 100644 --- a/src/arm64/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/src/arm64/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -139,7 +139,7 @@ bus-width = <4>; }; -&gem3 { /* required by spec */ +&gem3 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; @@ -166,9 +166,28 @@ }; }; -&pinctrl0 { /* required by spec */ +&pinctrl0 { status = "okay"; + pinctrl_gpio0_default: gpio0-default { + conf { + groups = "gpio0_38_grp"; + bias-pull-up; + power-source = ; + }; + + mux { + groups = "gpio0_38_grp"; + function = "gpio0"; + }; + + conf-tx { + pins = "MIO38"; + bias-disable; + output-enable; + }; + }; + pinctrl_uart1_default: uart1-default { conf { groups = "uart1_9_grp"; @@ -185,6 +204,7 @@ conf-tx { pins = "MIO36"; bias-disable; + output-enable; }; mux { @@ -207,7 +227,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { conf { groups = "gpio0_24_grp", "gpio0_25_grp"; slew-rate = ; @@ -236,6 +256,7 @@ conf-bootstrap { pins = "MIO71", "MIO73", "MIO75"; bias-disable; + output-enable; low-power-disable; }; @@ -243,6 +264,7 @@ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; + output-enable; low-power-enable; }; @@ -251,6 +273,7 @@ slew-rate = ; power-source = ; bias-disable; + output-enable; }; mux-mdio { @@ -281,6 +304,7 @@ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + output-enable; drive-strength = <4>; slew-rate = ; }; @@ -319,6 +343,12 @@ }; }; +&gpio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + &uart1 { status = "okay"; pinctrl-names = "default"; diff --git a/src/arm64/xilinx/zynqmp-sck-kv-g-revB.dtso b/src/arm64/xilinx/zynqmp-sck-kv-g-revB.dtso index f88b71f5b07..a7b8fffad49 100644 --- a/src/arm64/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/src/arm64/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -94,6 +94,7 @@ pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; + assigned-clock-rates = <250000000>, <20000000>; }; &dwc3_0 { @@ -122,7 +123,7 @@ bus-width = <4>; }; -&gem3 { /* required by spec */ +&gem3 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; @@ -149,9 +150,28 @@ }; }; -&pinctrl0 { /* required by spec */ +&pinctrl0 { status = "okay"; + pinctrl_gpio0_default: gpio0-default { + conf { + groups = "gpio0_38_grp"; + bias-pull-up; + power-source = ; + }; + + mux { + groups = "gpio0_38_grp"; + function = "gpio0"; + }; + + conf-tx { + pins = "MIO38"; + bias-disable; + output-enable; + }; + }; + pinctrl_uart1_default: uart1-default { conf { groups = "uart1_9_grp"; @@ -168,6 +188,7 @@ conf-tx { pins = "MIO36"; bias-disable; + output-enable; }; mux { @@ -190,7 +211,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { conf { groups = "gpio0_24_grp", "gpio0_25_grp"; slew-rate = ; @@ -219,6 +240,7 @@ conf-bootstrap { pins = "MIO71", "MIO73", "MIO75"; bias-disable; + output-enable; low-power-disable; }; @@ -226,6 +248,7 @@ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; + output-enable; low-power-enable; }; @@ -234,6 +257,7 @@ slew-rate = ; power-source = ; bias-disable; + output-enable; }; mux-mdio { @@ -264,6 +288,7 @@ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + output-enable; drive-strength = <4>; slew-rate = ; }; @@ -302,6 +327,12 @@ }; }; +&gpio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + &uart1 { status = "okay"; pinctrl-names = "default"; diff --git a/src/arm64/xilinx/zynqmp-zc1751-xm015-dc1.dts b/src/arm64/xilinx/zynqmp-zc1751-xm015-dc1.dts index 73491626e01..6aff22d4336 100644 --- a/src/arm64/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/src/arm64/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -148,7 +148,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; diff --git a/src/arm64/xilinx/zynqmp-zc1751-xm016-dc2.dts b/src/arm64/xilinx/zynqmp-zc1751-xm016-dc2.dts index f767708fb50..1850325e1d6 100644 --- a/src/arm64/xilinx/zynqmp-zc1751-xm016-dc2.dts +++ b/src/arm64/xilinx/zynqmp-zc1751-xm016-dc2.dts @@ -219,7 +219,7 @@ }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_6_grp", "gpio0_7_grp"; function = "gpio0"; diff --git a/src/arm64/xilinx/zynqmp-zc1751-xm019-dc5.dts b/src/arm64/xilinx/zynqmp-zc1751-xm019-dc5.dts index b1857e17ab7..53aa3dca1dc 100644 --- a/src/arm64/xilinx/zynqmp-zc1751-xm019-dc5.dts +++ b/src/arm64/xilinx/zynqmp-zc1751-xm019-dc5.dts @@ -125,7 +125,7 @@ }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_74_grp", "gpio0_75_grp"; function = "gpio0"; @@ -152,7 +152,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_76_grp", "gpio0_77_grp"; function = "gpio0"; diff --git a/src/arm64/xilinx/zynqmp-zcu100-revC.dts b/src/arm64/xilinx/zynqmp-zcu100-revC.dts index 52f998c2253..c5945067cd5 100644 --- a/src/arm64/xilinx/zynqmp-zcu100-revC.dts +++ b/src/arm64/xilinx/zynqmp-zcu100-revC.dts @@ -275,7 +275,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; diff --git a/src/arm64/xilinx/zynqmp-zcu102-revA.dts b/src/arm64/xilinx/zynqmp-zcu102-revA.dts index 84952c14f02..ad8f23a0ec6 100644 --- a/src/arm64/xilinx/zynqmp-zcu102-revA.dts +++ b/src/arm64/xilinx/zynqmp-zcu102-revA.dts @@ -603,7 +603,7 @@ reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; - clock-frequency = <148500000>; + clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; @@ -689,7 +689,7 @@ }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; @@ -716,7 +716,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; diff --git a/src/arm64/xilinx/zynqmp-zcu104-revA.dts b/src/arm64/xilinx/zynqmp-zcu104-revA.dts index 5084ddcee00..b1eca1bb6a6 100644 --- a/src/arm64/xilinx/zynqmp-zcu104-revA.dts +++ b/src/arm64/xilinx/zynqmp-zcu104-revA.dts @@ -272,7 +272,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; diff --git a/src/arm64/xilinx/zynqmp-zcu104-revC.dts b/src/arm64/xilinx/zynqmp-zcu104-revC.dts index b273bd1d920..ddc74d963a0 100644 --- a/src/arm64/xilinx/zynqmp-zcu104-revC.dts +++ b/src/arm64/xilinx/zynqmp-zcu104-revC.dts @@ -284,7 +284,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; diff --git a/src/arm64/xilinx/zynqmp-zcu106-revA.dts b/src/arm64/xilinx/zynqmp-zcu106-revA.dts index 50c384aa253..7beedd730f9 100644 --- a/src/arm64/xilinx/zynqmp-zcu106-revA.dts +++ b/src/arm64/xilinx/zynqmp-zcu106-revA.dts @@ -605,7 +605,7 @@ reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; - clock-frequency = <148500000>; + clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; @@ -700,7 +700,7 @@ }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; @@ -727,7 +727,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; diff --git a/src/arm64/xilinx/zynqmp-zcu111-revA.dts b/src/arm64/xilinx/zynqmp-zcu111-revA.dts index 617cb0405a7..b67ff7ecf3c 100644 --- a/src/arm64/xilinx/zynqmp-zcu111-revA.dts +++ b/src/arm64/xilinx/zynqmp-zcu111-revA.dts @@ -589,7 +589,7 @@ }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; @@ -616,7 +616,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; diff --git a/src/arm64/xilinx/zynqmp-zcu1275-revA.dts b/src/arm64/xilinx/zynqmp-zcu1275-revA.dts index c406017b034..a38c2baeba6 100644 --- a/src/arm64/xilinx/zynqmp-zcu1275-revA.dts +++ b/src/arm64/xilinx/zynqmp-zcu1275-revA.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * dts file for Xilinx ZynqMP ZC1275 + * dts file for Xilinx ZynqMP ZCU1275 * * (C) Copyright 2017 - 2021, Xilinx, Inc. * diff --git a/src/arm64/xilinx/zynqmp.dtsi b/src/arm64/xilinx/zynqmp.dtsi index eaba466804b..25d20d80323 100644 --- a/src/arm64/xilinx/zynqmp.dtsi +++ b/src/arm64/xilinx/zynqmp.dtsi @@ -24,6 +24,13 @@ #address-cells = <2>; #size-cells = <2>; + options { + u-boot { + compatible = "u-boot,config"; + bootscr-address = /bits/ 64 <0x20000000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -180,13 +187,18 @@ }; firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; #power-domain-cells = <1>; method = "smc"; bootph-all; - zynqmp_power: zynqmp-power { + zynqmp_power: power-management { bootph-all; compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; @@ -281,6 +293,7 @@ interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + resets = <&zynqmp_reset ZYNQMP_RESET_CAN0>; power-domains = <&zynqmp_firmware PD_CAN_0>; }; @@ -293,6 +306,7 @@ interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + resets = <&zynqmp_reset ZYNQMP_RESET_CAN1>; power-domains = <&zynqmp_firmware PD_CAN_1>; }; @@ -326,7 +340,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14e8>; + /* iommus = <&smmu 0x14e8>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -339,7 +353,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14e9>; + /* iommus = <&smmu 0x14e9>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -352,7 +366,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ea>; + /* iommus = <&smmu 0x14ea>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -365,7 +379,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14eb>; + /* iommus = <&smmu 0x14eb>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -378,7 +392,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ec>; + /* iommus = <&smmu 0x14ec>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -391,7 +405,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ed>; + /* iommus = <&smmu 0x14ed>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -404,7 +418,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ee>; + /* iommus = <&smmu 0x14ee>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -417,7 +431,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ef>; + /* iommus = <&smmu 0x14ef>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -462,7 +476,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x868>; + /* iommus = <&smmu 0x868>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -475,7 +489,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x869>; + /* iommus = <&smmu 0x869>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -488,7 +502,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86a>; + /* iommus = <&smmu 0x86a>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -501,7 +515,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86b>; + /* iommus = <&smmu 0x86b>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -514,7 +528,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86c>; + /* iommus = <&smmu 0x86c>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -527,7 +541,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86d>; + /* iommus = <&smmu 0x86d>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -540,7 +554,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86e>; + /* iommus = <&smmu 0x86e>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -553,7 +567,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86f>; + /* iommus = <&smmu 0x86f>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -573,7 +587,7 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - iommus = <&smmu 0x872>; + /* iommus = <&smmu 0x872>; */ power-domains = <&zynqmp_firmware PD_NAND>; }; @@ -585,7 +599,7 @@ ; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - iommus = <&smmu 0x874>; + /* iommus = <&smmu 0x874>; */ power-domains = <&zynqmp_firmware PD_ETH_0>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; reset-names = "gem0_rst"; @@ -599,7 +613,7 @@ ; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - iommus = <&smmu 0x875>; + /* iommus = <&smmu 0x875>; */ power-domains = <&zynqmp_firmware PD_ETH_1>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; reset-names = "gem1_rst"; @@ -613,7 +627,7 @@ ; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - iommus = <&smmu 0x876>; + /* iommus = <&smmu 0x876>; */ power-domains = <&zynqmp_firmware PD_ETH_2>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; reset-names = "gem2_rst"; @@ -627,7 +641,7 @@ ; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - iommus = <&smmu 0x877>; + /* iommus = <&smmu 0x877>; */ power-domains = <&zynqmp_firmware PD_ETH_3>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; reset-names = "gem3_rst"; @@ -689,7 +703,7 @@ msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, - <0x80 0x00000000 0x0 0x1000000>; + <0x80 0x00000000 0x0 0x10000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */ <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ @@ -699,7 +713,7 @@ <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; - iommus = <&smmu 0x4d0>; + /* iommus = <&smmu 0x4d0>; */ power-domains = <&zynqmp_firmware PD_PCIE>; pcie_intc: legacy-interrupt-controller { interrupt-controller; @@ -720,7 +734,7 @@ <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; - iommus = <&smmu 0x873>; + /* iommus = <&smmu 0x873>; */ power-domains = <&zynqmp_firmware PD_QSPI>; }; @@ -752,8 +766,7 @@ interrupts = ; power-domains = <&zynqmp_firmware PD_SATA>; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; - iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, - <&smmu 0x4c2>, <&smmu 0x4c3>; + /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */ }; sdhci0: mmc@ff160000 { @@ -764,7 +777,7 @@ interrupts = ; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; - iommus = <&smmu 0x870>; + /* iommus = <&smmu 0x870>; */ #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; power-domains = <&zynqmp_firmware PD_SD_0>; @@ -779,7 +792,7 @@ interrupts = ; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; - iommus = <&smmu 0x871>; + /* iommus = <&smmu 0x871>; */ #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; power-domains = <&zynqmp_firmware PD_SD_1>; @@ -912,6 +925,7 @@ status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; + clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_0>; resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, @@ -922,14 +936,15 @@ dwc3_0: usb@fe200000 { compatible = "snps,dwc3"; + status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "host", "peripheral", "otg"; interrupts = , , ; - clock-names = "bus_early", "ref"; - iommus = <&smmu 0x860>; + clock-names = "ref"; + /* iommus = <&smmu 0x860>; */ snps,quirk-frame-length-adjustment = <0x20>; snps,resume-hs-terminations; /* dma-coherent; */ @@ -942,6 +957,7 @@ status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; + clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_1>; resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, @@ -951,14 +967,15 @@ dwc3_1: usb@fe300000 { compatible = "snps,dwc3"; + status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "host", "peripheral", "otg"; interrupts = , , ; - clock-names = "bus_early", "ref"; - iommus = <&smmu 0x861>; + clock-names = "ref"; + /* iommus = <&smmu 0x861>; */ snps,quirk-frame-length-adjustment = <0x20>; snps,resume-hs-terminations; /* dma-coherent; */ @@ -1018,6 +1035,7 @@ interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&zynqmp_firmware PD_DP>; + /* iommus = <&smmu 0xce4>; */ #dma-cells = <1>; }; @@ -1032,6 +1050,7 @@ reg-names = "dp", "blend", "av_buf", "aud"; interrupts = ; interrupt-parent = <&gic>; + /* iommus = <&smmu 0xce3>; */ clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; power-domains = <&zynqmp_firmware PD_DP>; diff --git a/src/loongarch/loongson-2k1000.dtsi b/src/loongarch/loongson-2k1000.dtsi index 49a70f8c3ca..b6aeb1f70e2 100644 --- a/src/loongarch/loongson-2k1000.dtsi +++ b/src/loongarch/loongson-2k1000.dtsi @@ -100,6 +100,13 @@ #size-cells = <2>; dma-coherent; + isa@18000000 { + compatible = "isa"; + #size-cells = <1>; + #address-cells = <2>; + ranges = <1 0x0 0x0 0x18000000 0x4000>; + }; + liointc0: interrupt-controller@1fe01400 { compatible = "loongson,liointc-2.0"; reg = <0x0 0x1fe01400 0x0 0x40>, diff --git a/src/loongarch/loongson-2k2000-ref.dts b/src/loongarch/loongson-2k2000-ref.dts index dca91caf895..74b99bd234c 100644 --- a/src/loongarch/loongson-2k2000-ref.dts +++ b/src/loongarch/loongson-2k2000-ref.dts @@ -61,12 +61,45 @@ &gmac0 { status = "okay"; + + phy-mode = "gmii"; + phy-handle = <&phy0>; + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { + reg = <2>; + }; + }; }; &gmac1 { status = "okay"; + + phy-mode = "gmii"; + phy-handle = <&phy1>; + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + phy1: ethernet-phy@1 { + reg = <2>; + }; + }; }; &gmac2 { status = "okay"; + + phy-mode = "rgmii"; + phy-handle = <&phy2>; + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + phy2: ethernet-phy@2 { + reg = <0>; + }; + }; }; diff --git a/src/loongarch/loongson-2k2000.dtsi b/src/loongarch/loongson-2k2000.dtsi index a231949b5f5..9eab2d02cbe 100644 --- a/src/loongarch/loongson-2k2000.dtsi +++ b/src/loongarch/loongson-2k2000.dtsi @@ -51,6 +51,13 @@ #address-cells = <2>; #size-cells = <2>; + isa@18400000 { + compatible = "isa"; + #size-cells = <1>; + #address-cells = <2>; + ranges = <1 0x0 0x0 0x18400000 0x4000>; + }; + pmc: power-management@100d0000 { compatible = "loongson,ls2k2000-pmc", "loongson,ls2k0500-pmc", "syscon"; reg = <0x0 0x100d0000 0x0 0x58>; @@ -109,6 +116,8 @@ msi: msi-controller@1fe01140 { compatible = "loongson,pch-msi-1.0"; reg = <0x0 0x1fe01140 0x0 0x8>; + interrupt-controller; + #interrupt-cells = <1>; msi-controller; loongson,msi-base-vec = <64>; loongson,msi-num-vecs = <192>; @@ -140,27 +149,34 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + msi-parent = <&msi>; bus-range = <0x0 0xff>; - ranges = <0x01000000 0x0 0x00008000 0x0 0x18400000 0x0 0x00008000>, + ranges = <0x01000000 0x0 0x00008000 0x0 0x18408000 0x0 0x00008000>, <0x02000000 0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>; gmac0: ethernet@3,0 { reg = <0x1800 0x0 0x0 0x0 0x0>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>, + <13 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_lpi"; interrupt-parent = <&pic>; status = "disabled"; }; gmac1: ethernet@3,1 { reg = <0x1900 0x0 0x0 0x0 0x0>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, + <15 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_lpi"; interrupt-parent = <&pic>; status = "disabled"; }; gmac2: ethernet@3,2 { reg = <0x1a00 0x0 0x0 0x0 0x0>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, + <18 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_lpi"; interrupt-parent = <&pic>; status = "disabled"; }; diff --git a/src/mips/mobileye/eyeq5-epm5.dts b/src/mips/mobileye/eyeq5-epm5.dts new file mode 100644 index 00000000000..6898b2d8267 --- /dev/null +++ b/src/mips/mobileye/eyeq5-epm5.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright 2023 Mobileye Vision Technologies Ltd. + */ + +/dts-v1/; + +#include "eyeq5.dtsi" + +/ { + compatible = "mobileye,eyeq5-epm5", "mobileye,eyeq5"; + model = "Mobile EyeQ5 MP5 Evaluation board"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000 0x0 0x02000000>, + <0x8 0x02000000 0x0 0x7E000000>; + }; +}; diff --git a/src/mips/mobileye/eyeq5-fixed-clocks.dtsi b/src/mips/mobileye/eyeq5-fixed-clocks.dtsi new file mode 100644 index 00000000000..78f5533a95c --- /dev/null +++ b/src/mips/mobileye/eyeq5-fixed-clocks.dtsi @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright 2023 Mobileye Vision Technologies Ltd. + */ + +/ { + /* Fixed clock */ + pll_cpu: pll-cpu { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1500000000>; + }; + + pll_vdi: pll-vdi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1280000000>; + }; + + pll_per: pll-per { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2000000000>; + }; + + pll_ddr0: pll-ddr0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1857210000>; + }; + + pll_ddr1: pll-ddr1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1857210000>; + }; + +/* PLL_CPU derivatives */ + occ_cpu: occ-cpu { + compatible = "fixed-factor-clock"; + clocks = <&pll_cpu>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + si_css0_ref_clk: si-css0-ref-clk { /* gate ClkRstGen_si_css0_ref */ + compatible = "fixed-factor-clock"; + clocks = <&occ_cpu>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + cpc_clk: cpc-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + core0_clk: core0-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + core1_clk: core1-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + core2_clk: core2-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + core3_clk: core3-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + cm_clk: cm-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + mem_clk: mem-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + occ_isram: occ-isram { + compatible = "fixed-factor-clock"; + clocks = <&pll_cpu>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + isram_clk: isram-clk { /* gate ClkRstGen_isram */ + compatible = "fixed-factor-clock"; + clocks = <&occ_isram>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + occ_dbu: occ-dbu { + compatible = "fixed-factor-clock"; + clocks = <&pll_cpu>; + #clock-cells = <0>; + clock-div = <10>; + clock-mult = <1>; + }; + si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu */ + compatible = "fixed-factor-clock"; + clocks = <&occ_dbu>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; +/* PLL_VDI derivatives */ + occ_vdi: occ-vdi { + compatible = "fixed-factor-clock"; + clocks = <&pll_vdi>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */ + compatible = "fixed-factor-clock"; + clocks = <&occ_vdi>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + occ_can_ser: occ-can-ser { + compatible = "fixed-factor-clock"; + clocks = <&pll_vdi>; + #clock-cells = <0>; + clock-div = <16>; + clock-mult = <1>; + }; + can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */ + compatible = "fixed-factor-clock"; + clocks = <&occ_can_ser>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + i2c_ser_clk: i2c-ser-clk { + compatible = "fixed-factor-clock"; + clocks = <&pll_vdi>; + #clock-cells = <0>; + clock-div = <20>; + clock-mult = <1>; + }; +/* PLL_PER derivatives */ + occ_periph: occ-periph { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <16>; + clock-mult = <1>; + }; + periph_clk: periph-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + can_clk: can-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + spi_clk: spi-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + i2c_clk: i2c-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "i2c_clk"; + }; + timer_clk: timer-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "timer_clk"; + }; + gpio_clk: gpio-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "gpio_clk"; + }; + emmc_sys_clk: emmc-sys-clk { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <10>; + clock-mult = <1>; + clock-output-names = "emmc_sys_clk"; + }; + ccf_ctrl_clk: ccf-ctrl-clk { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "ccf_ctrl_clk"; + }; + occ_mjpeg_core: occ-mjpeg-core { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "occ_mjpeg_core"; + }; + hsm_clk: hsm-clk { /* gate ClkRstGen_hsm */ + compatible = "fixed-factor-clock"; + clocks = <&occ_mjpeg_core>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "hsm_clk"; + }; + mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpeg_gen */ + compatible = "fixed-factor-clock"; + clocks = <&occ_mjpeg_core>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "mjpeg_core_clk"; + }; + fcmu_a_clk: fcmu-a-clk { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <20>; + clock-mult = <1>; + clock-output-names = "fcmu_a_clk"; + }; + occ_pci_sys: occ-pci-sys { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "occ_pci_sys"; + }; + pclk: pclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; /* 250MHz */ + }; + tsu_clk: tsu-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; /* 125MHz */ + }; +}; diff --git a/src/mips/mobileye/eyeq5.dtsi b/src/mips/mobileye/eyeq5.dtsi new file mode 100644 index 00000000000..6cc5980e2fa --- /dev/null +++ b/src/mips/mobileye/eyeq5.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* +* Copyright 2023 Mobileye Vision Technologies Ltd. +*/ + +#include + +#include "eyeq5-fixed-clocks.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "img,i6500"; + reg = <0>; + clocks = <&core0_clk>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* These reserved memory regions are also defined in bootmanager + * for configuring inbound translation for BARS, don't change + * these without syncing with bootmanager + */ + shmem0_reserved: shmem@804000000 { + reg = <0x8 0x04000000 0x0 0x1000000>; + }; + shmem1_reserved: shmem@805000000 { + reg = <0x8 0x05000000 0x0 0x1000000>; + }; + pci0_msi_reserved: pci0-msi@806000000 { + reg = <0x8 0x06000000 0x0 0x100000>; + }; + pci1_msi_reserved: pci1-msi@806100000 { + reg = <0x8 0x06100000 0x0 0x100000>; + }; + + mini_coredump0_reserved: mini-coredump0@806200000 { + reg = <0x8 0x06200000 0x0 0x100000>; + }; + mhm_reserved_0: the-mhm-reserved-0@0 { + reg = <0x8 0x00000000 0x0 0x0000800>; + }; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + }; + + cpu_intc: interrupt-controller { + compatible = "mti,cpu-interrupt-controller"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + + soc: soc { + #address-cells = <2>; + #size-cells = <2>; + ranges; + compatible = "simple-bus"; + + uart0: serial@800000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x800000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&uart_clk>, <&occ_periph>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart1: serial@900000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x900000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&uart_clk>, <&occ_periph>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart2: serial@a00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0xa00000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&uart_clk>, <&occ_periph>; + clock-names = "uartclk", "apb_pclk"; + }; + + gic: interrupt-controller@140000 { + compatible = "mti,gic"; + reg = <0x0 0x140000 0x0 0x20000>; + interrupt-controller; + #interrupt-cells = <3>; + + /* + * Declare the interrupt-parent even though the mti,gic + * binding doesn't require it, such that the kernel can + * figure out that cpu_intc is the root interrupt + * controller & should be probed first. + */ + interrupt-parent = <&cpu_intc>; + + timer { + compatible = "mti,gic-timer"; + interrupts = ; + clocks = <&core0_clk>; + }; + }; + }; +}; diff --git a/src/mips/ralink/mt7621.dtsi b/src/mips/ralink/mt7621.dtsi index 35a10258f23..6e95e6f19a6 100644 --- a/src/mips/ralink/mt7621.dtsi +++ b/src/mips/ralink/mt7621.dtsi @@ -115,14 +115,58 @@ compatible = "ns16550a"; reg = <0xc00 0x100>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&sysc MT7621_CLK_UART1>; interrupt-parent = <&gic>; interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; no-loopback-test; + + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + }; + + serial1: serial@d00 { + compatible = "ns16550a"; + reg = <0xd00 0x100>; + + reg-io-width = <4>; + reg-shift = <2>; + + clocks = <&sysc MT7621_CLK_UART2>; + + interrupt-parent = <&gic>; + interrupts = ; + + no-loopback-test; + + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + + status = "disabled"; + }; + + serial2: serial@e00 { + compatible = "ns16550a"; + reg = <0xe00 0x100>; + + reg-io-width = <4>; + reg-shift = <2>; + + clocks = <&sysc MT7621_CLK_UART3>; + + interrupt-parent = <&gic>; + interrupts = ; + + no-loopback-test; + + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + + status = "disabled"; }; spi0: spi@b00 { @@ -263,6 +307,9 @@ 0x1e1d0700 0x0100>; reg-names = "mac", "ippc"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&sysc MT7621_CLK_XTAL>; clock-names = "sys_ck"; diff --git a/src/powerpc/akebono.dts b/src/powerpc/akebono.dts index df18f8dc464..343326c3038 100644 --- a/src/powerpc/akebono.dts +++ b/src/powerpc/akebono.dts @@ -126,7 +126,7 @@ interrupts = <93 2>; }; - EHCI0: ehci@30010000000 { + EHCI0: usb@30010000000 { compatible = "ibm,476gtr-ehci", "generic-ehci"; reg = <0x300 0x10000000 0x0 0x10000>; interrupt-parent = <&MPIC>; @@ -140,14 +140,14 @@ interrupt-parent = <&MPIC>; }; - OHCI0: ohci@30010010000 { + OHCI0: usb@30010010000 { compatible = "ibm,476gtr-ohci", "generic-ohci"; reg = <0x300 0x10010000 0x0 0x10000>; interrupt-parent = <&MPIC>; interrupts = <89 1>; }; - OHCI1: ohci@30010020000 { + OHCI1: usb@30010020000 { compatible = "ibm,476gtr-ohci", "generic-ohci"; reg = <0x300 0x10020000 0x0 0x10000>; interrupt-parent = <&MPIC>; diff --git a/src/riscv/microchip/mpfs.dtsi b/src/riscv/microchip/mpfs.dtsi index 59fd2d4ea52..9883ca3554c 100644 --- a/src/riscv/microchip/mpfs.dtsi +++ b/src/riscv/microchip/mpfs.dtsi @@ -243,7 +243,7 @@ }; pdma: dma-controller@3000000 { - compatible = "sifive,fu540-c000-pdma", "sifive,pdma0"; + compatible = "microchip,mpfs-pdma", "sifive,pdma0"; reg = <0x0 0x3000000 0x0 0x8000>; interrupt-parent = <&plic>; interrupts = <5 6>, <7 8>, <9 10>, <11 12>; @@ -422,7 +422,7 @@ can0: can@2010c000 { compatible = "microchip,mpfs-can"; reg = <0x0 0x2010c000 0x0 0x1000>; - clocks = <&clkcfg CLK_CAN0>; + clocks = <&clkcfg CLK_CAN0>, <&clkcfg CLK_MSSPLL3>; interrupt-parent = <&plic>; interrupts = <56>; status = "disabled"; @@ -431,7 +431,7 @@ can1: can@2010d000 { compatible = "microchip,mpfs-can"; reg = <0x0 0x2010d000 0x0 0x1000>; - clocks = <&clkcfg CLK_CAN1>; + clocks = <&clkcfg CLK_CAN1>, <&clkcfg CLK_MSSPLL3>; interrupt-parent = <&plic>; interrupts = <57>; status = "disabled"; diff --git a/src/riscv/renesas/r9a07g043f.dtsi b/src/riscv/renesas/r9a07g043f.dtsi index a92cfcfc021..f35324b9173 100644 --- a/src/riscv/renesas/r9a07g043f.dtsi +++ b/src/riscv/renesas/r9a07g043f.dtsi @@ -27,7 +27,7 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xandespmu"; mmu-type = "riscv,sv39"; i-cache-size = <0x8000>; i-cache-line-size = <0x40>; @@ -39,13 +39,17 @@ cpu0_intc: interrupt-controller { #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; + compatible = "andestech,cpu-intc", "riscv,cpu-intc"; interrupt-controller; }; }; }; }; +&pinctrl { + gpio-ranges = <&pinctrl 0 0 232>; +}; + &soc { dma-noncoherent; interrupt-parent = <&plic>; diff --git a/src/riscv/sophgo/sg2042.dtsi b/src/riscv/sophgo/sg2042.dtsi index ead1cc35d88..81fda312f98 100644 --- a/src/riscv/sophgo/sg2042.dtsi +++ b/src/riscv/sophgo/sg2042.dtsi @@ -6,6 +6,8 @@ /dts-v1/; #include +#include + #include "sg2042-cpus.dtsi" / { @@ -327,6 +329,12 @@ riscv,ndev = <224>; }; + rstgen: reset-controller@7030013000 { + compatible = "sophgo,sg2042-reset"; + reg = <0x00000070 0x30013000 0x00000000 0x0000000c>; + #reset-cells = <1>; + }; + uart0: serial@7040000000 { compatible = "snps,dw-apb-uart"; reg = <0x00000070 0x40000000 0x00000000 0x00001000>; @@ -335,6 +343,7 @@ clock-frequency = <500000000>; reg-shift = <2>; reg-io-width = <4>; + resets = <&rstgen RST_UART0>; status = "disabled"; }; }; diff --git a/src/riscv/starfive/jh7100-beaglev-starlight.dts b/src/riscv/starfive/jh7100-beaglev-starlight.dts index 7cda3a89020..168f5d9895a 100644 --- a/src/riscv/starfive/jh7100-beaglev-starlight.dts +++ b/src/riscv/starfive/jh7100-beaglev-starlight.dts @@ -11,3 +11,14 @@ model = "BeagleV Starlight Beta"; compatible = "beagle,beaglev-starlight-jh7100-r0", "starfive,jh7100"; }; + +&gmac { + phy-handle = <&phy>; +}; + +&mdio { + phy: ethernet-phy@7 { + reg = <7>; + reset-gpios = <&gpio 63 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/src/riscv/starfive/jh7100-common.dtsi b/src/riscv/starfive/jh7100-common.dtsi index 42fb61c3606..ae1a6aeb0ae 100644 --- a/src/riscv/starfive/jh7100-common.dtsi +++ b/src/riscv/starfive/jh7100-common.dtsi @@ -72,7 +72,91 @@ }; }; +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; +}; + &gpio { + gmac_pins: gmac-0 { + gtxclk-pins { + pins = ; + bias-pull-up; + drive-strength = <35>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + miitxclk-pins { + pins = ; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + tx-pins { + pins = , + , + , + , + , + , + , + , + ; + bias-pull-up; + drive-strength = <35>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + rxclk-pins { + pins = ; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-disable; + slew-rate = <6>; + }; + rxer-pins { + pins = ; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + rx-pins { + pins = , + , + , + , + , + , + , + , + , + , + , + , + ; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + i2c0_pins: i2c0-0 { i2c-pins { pinmux = , + ; + bias-disable; + drive-strength = <35>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + sdio0_pins: sdio0-0 { clk-pins { pinmux = ; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + &sdio0 { broken-cd; bus-width = <4>; diff --git a/src/riscv/starfive/jh7100-starfive-visionfive-v1.dts b/src/riscv/starfive/jh7100-starfive-visionfive-v1.dts index e82af72f1aa..692c696e1ab 100644 --- a/src/riscv/starfive/jh7100-starfive-visionfive-v1.dts +++ b/src/riscv/starfive/jh7100-starfive-visionfive-v1.dts @@ -6,7 +6,6 @@ /dts-v1/; #include "jh7100-common.dtsi" -#include / { model = "StarFive VisionFive V1"; @@ -18,3 +17,24 @@ priority = <224>; }; }; + +&gmac { + phy-handle = <&phy>; +}; + +/* + * The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires + * manual adjustment of the RX internal delay to work properly. The default + * RX delay provided by the driver (1.95ns) is too high, but applying a 50% + * reduction seems to mitigate the issue. + * + * It is worth noting the adjustment is not necessary on BeagleV Starlight SBC, + * which uses a Microchip PHY. Hence, most likely the Motorcomm PHY is the one + * responsible for the misbehaviour, not the GMAC. + */ +&mdio { + phy: ethernet-phy@0 { + reg = <0>; + rx-internal-delay-ps = <900>; + }; +}; diff --git a/src/riscv/starfive/jh7100.dtsi b/src/riscv/starfive/jh7100.dtsi index 8bcf36d07f3..9a2e9583af8 100644 --- a/src/riscv/starfive/jh7100.dtsi +++ b/src/riscv/starfive/jh7100.dtsi @@ -116,6 +116,7 @@ osc_sys: osc-sys { compatible = "fixed-clock"; #clock-cells = <0>; + clock-output-names = "osc_sys"; /* This value must be overridden by the board */ clock-frequency = <0>; }; @@ -123,6 +124,7 @@ osc_aud: osc-aud { compatible = "fixed-clock"; #clock-cells = <0>; + clock-output-names = "osc_aud"; /* This value must be overridden by the board */ clock-frequency = <0>; }; @@ -130,6 +132,7 @@ gmac_rmii_ref: gmac-rmii-ref { compatible = "fixed-clock"; #clock-cells = <0>; + clock-output-names = "gmac_rmii_ref"; /* Should be overridden by the board when needed */ clock-frequency = <0>; }; @@ -137,6 +140,7 @@ gmac_gr_mii_rxclk: gmac-gr-mii-rxclk { compatible = "fixed-clock"; #clock-cells = <0>; + clock-output-names = "gmac_gr_mii_rxclk"; /* Should be overridden by the board when needed */ clock-frequency = <0>; }; @@ -204,6 +208,37 @@ status = "disabled"; }; + gmac: ethernet@10020000 { + compatible = "starfive,jh7100-dwmac", "snps,dwmac"; + reg = <0x0 0x10020000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>, + <&clkgen JH7100_CLK_GMAC_AHB>, + <&clkgen JH7100_CLK_GMAC_PTP_REF>, + <&clkgen JH7100_CLK_GMAC_TX_INV>, + <&clkgen JH7100_CLK_GMAC_GTX>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx"; + resets = <&rstgen JH7100_RSTN_GMAC_AHB>; + reset-names = "ahb"; + interrupts = <6>, <7>; + interrupt-names = "macirq", "eth_wake_irq"; + max-frame-size = <9000>; + snps,multicast-filter-bins = <32>; + snps,perfect-filter-entries = <128>; + starfive,syscon = <&sysmain 0x70 0>; + rx-fifo-depth = <32768>; + tx-fifo-depth = <16384>; + snps,axi-config = <&stmmac_axi_setup>; + snps,fixed-burst; + snps,force_thresh_dma_mode; + status = "disabled"; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <16>; + snps,rd_osr_lmt = <16>; + snps,blen = <256 128 64 32 0 0 0>; + }; + }; + clkgen: clock-controller@11800000 { compatible = "starfive,jh7100-clkgen"; reg = <0x0 0x11800000 0x0 0x10000>; @@ -218,6 +253,11 @@ #reset-cells = <1>; }; + sysmain: syscon@11850000 { + compatible = "starfive,jh7100-sysmain", "syscon"; + reg = <0x0 0x11850000 0x0 0x10000>; + }; + i2c0: i2c@118b0000 { compatible = "snps,designware-i2c"; reg = <0x0 0x118b0000 0x0 0x10000>; @@ -320,6 +360,15 @@ <&rstgen JH7100_RSTN_WDT>; }; + pwm: pwm@12490000 { + compatible = "starfive,jh7100-pwm", "opencores,pwm-v1"; + reg = <0x0 0x12490000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_PWM_APB>; + resets = <&rstgen JH7100_RSTN_PWM_APB>; + #pwm-cells = <3>; + status = "disabled"; + }; + sfctemp: temperature-sensor@124a0000 { compatible = "starfive,jh7100-temp"; reg = <0x0 0x124a0000 0x0 0x10000>; diff --git a/src/riscv/starfive/jh7110-starfive-visionfive-2.dtsi b/src/riscv/starfive/jh7110-starfive-visionfive-2.dtsi index b89e9791efa..45b58b6f3df 100644 --- a/src/riscv/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/src/riscv/starfive/jh7110-starfive-visionfive-2.dtsi @@ -125,6 +125,55 @@ clock-frequency = <49152000>; }; +&camss { + assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>, + <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>; + assigned-clock-rates = <49500000>, <198000000>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + camss_from_csi2rx: endpoint { + remote-endpoint = <&csi2rx_to_camss>; + }; + }; + }; +}; + +&csi2rx { + assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>; + assigned-clock-rates = <297000000>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + /* remote MIPI sensor endpoint */ + }; + + port@1 { + reg = <1>; + + csi2rx_to_camss: endpoint { + remote-endpoint = <&camss_from_csi2rx>; + }; + }; + }; +}; + &gmac0 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; @@ -323,6 +372,12 @@ }; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + &spi0 { pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; @@ -513,6 +568,22 @@ }; }; + pwm_pins: pwm-0 { + pwm-pins { + pinmux = , + ; + bias-disable; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + spi0_pins: spi0-0 { mosi-pins { pinmux = ; + clocks = <&syscrg JH7110_SYSCLK_PWM_APB>; + resets = <&syscrg JH7110_SYSRST_PWM_APB>; + #pwm-cells = <3>; + status = "disabled"; + }; + sfctemp: temperature-sensor@120e0000 { compatible = "starfive,jh7110-temp"; reg = <0x0 0x120e0000 0x0 0x10000>; @@ -1104,6 +1113,32 @@ #power-domain-cells = <1>; }; + csi2rx: csi@19800000 { + compatible = "starfive,jh7110-csi2rx", "cdns,csi2rx"; + reg = <0x0 0x19800000 0x0 0x10000>; + clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>, + <&ispcrg JH7110_ISPCLK_VIN_APB>, + <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF0>, + <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF1>, + <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF2>, + <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF3>; + clock-names = "sys_clk", "p_clk", + "pixel_if0_clk", "pixel_if1_clk", + "pixel_if2_clk", "pixel_if3_clk"; + resets = <&ispcrg JH7110_ISPRST_VIN_SYS>, + <&ispcrg JH7110_ISPRST_VIN_APB>, + <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF0>, + <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF1>, + <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF2>, + <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF3>; + reset-names = "sys", "reg_bank", + "pixel_if0", "pixel_if1", + "pixel_if2", "pixel_if3"; + phys = <&csi_phy>; + phy-names = "dphy"; + status = "disabled"; + }; + ispcrg: clock-controller@19810000 { compatible = "starfive,jh7110-ispcrg"; reg = <0x0 0x19810000 0x0 0x10000>; @@ -1121,6 +1156,47 @@ power-domains = <&pwrc JH7110_PD_ISP>; }; + csi_phy: phy@19820000 { + compatible = "starfive,jh7110-dphy-rx"; + reg = <0x0 0x19820000 0x0 0x10000>; + clocks = <&ispcrg JH7110_ISPCLK_M31DPHY_CFG_IN>, + <&ispcrg JH7110_ISPCLK_M31DPHY_REF_IN>, + <&ispcrg JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0>; + clock-names = "cfg", "ref", "tx"; + resets = <&ispcrg JH7110_ISPRST_M31DPHY_HW>, + <&ispcrg JH7110_ISPRST_M31DPHY_B09_AON>; + power-domains = <&aon_syscon JH7110_AON_PD_DPHY_RX>; + #phy-cells = <0>; + }; + + camss: isp@19840000 { + compatible = "starfive,jh7110-camss"; + reg = <0x0 0x19840000 0x0 0x10000>, + <0x0 0x19870000 0x0 0x30000>; + reg-names = "syscon", "isp"; + clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>, + <&ispcrg JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C>, + <&ispcrg JH7110_ISPCLK_DVP_INV>, + <&ispcrg JH7110_ISPCLK_VIN_P_AXI_WR>, + <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>, + <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>, + <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>; + clock-names = "apb_func", "wrapper_clk_c", "dvp_inv", + "axiwr", "mipi_rx0_pxl", "ispcore_2x", + "isp_axi"; + resets = <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_P>, + <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_C>, + <&ispcrg JH7110_ISPRST_VIN_P_AXI_RD>, + <&ispcrg JH7110_ISPRST_VIN_P_AXI_WR>, + <&syscrg JH7110_SYSRST_ISP_TOP>, + <&syscrg JH7110_SYSRST_ISP_TOP_AXI>; + reset-names = "wrapper_p", "wrapper_c", "axird", + "axiwr", "isp_top_n", "isp_top_axi"; + power-domains = <&pwrc JH7110_PD_ISP>; + interrupts = <92>, <87>, <90>, <88>; + status = "disabled"; + }; + voutcrg: clock-controller@295c0000 { compatible = "starfive,jh7110-voutcrg"; reg = <0x0 0x295c0000 0x0 0x10000>; From 03de305ec48b0bb28554372abb40ccd46dbe0bf9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 20 May 2024 13:35:03 -0600 Subject: [PATCH 037/383] Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet" As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman Signed-off-by: Tom Rini --- MAINTAINERS | 16 + api/api.c | 4 +- api/api_display.c | 2 +- api/api_net.c | 1 - api/api_platform-arm.c | 1 - api/api_platform-mips.c | 1 - api/api_platform-powerpc.c | 1 - api/api_storage.c | 2 +- arch/arc/include/asm/global_data.h | 2 + arch/arm/Kconfig | 5 + arch/arm/Makefile | 1 + arch/arm/cpu/arm11/cpu.c | 1 - arch/arm/cpu/arm1136/mx31/devices.c | 1 - arch/arm/cpu/arm1136/mx31/generic.c | 1 - arch/arm/cpu/arm1136/mx31/timer.c | 1 - arch/arm/cpu/arm720t/interrupts.c | 2 +- arch/arm/cpu/arm920t/cpu.c | 1 - arch/arm/cpu/arm920t/start.S | 1 - arch/arm/cpu/arm926ejs/cache.c | 1 - arch/arm/cpu/arm926ejs/cpu.c | 1 - arch/arm/cpu/arm926ejs/mxs/clock.c | 1 - arch/arm/cpu/arm926ejs/mxs/iomux.c | 1 - arch/arm/cpu/arm926ejs/mxs/mxs.c | 1 - arch/arm/cpu/arm926ejs/mxs/spl_boot.c | 1 - arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c | 1 - arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 1 - arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 1 - arch/arm/cpu/arm926ejs/mxs/start.S | 1 - arch/arm/cpu/arm926ejs/mxs/timer.c | 1 - arch/arm/cpu/arm926ejs/start.S | 1 - arch/arm/cpu/arm946es/cpu.c | 1 - arch/arm/cpu/armv7/arch_timer.c | 2 +- arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c | 1 - arch/arm/cpu/armv7/bcm235xx/clk-bsc.c | 1 - arch/arm/cpu/armv7/bcm235xx/clk-core.c | 1 - arch/arm/cpu/armv7/bcm235xx/clk-eth.c | 1 - arch/arm/cpu/armv7/bcm235xx/clk-sdio.c | 1 - arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c | 1 - arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c | 1 - arch/arm/cpu/armv7/bcm281xx/clk-bsc.c | 1 - arch/arm/cpu/armv7/bcm281xx/clk-core.c | 1 - arch/arm/cpu/armv7/bcm281xx/clk-eth.c | 1 - arch/arm/cpu/armv7/bcm281xx/clk-sdio.c | 1 - arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c | 1 - arch/arm/cpu/armv7/bcm281xx/reset.c | 1 - arch/arm/cpu/armv7/bcmcygnus/reset.c | 1 - arch/arm/cpu/armv7/bcmnsp/reset.c | 1 - arch/arm/cpu/armv7/cache_v7.c | 1 - arch/arm/cpu/armv7/cp15.c | 1 - arch/arm/cpu/armv7/cpu.c | 1 - arch/arm/cpu/armv7/exception_level.c | 1 - arch/arm/cpu/armv7/iproc-common/armpll.c | 1 - .../cpu/armv7/iproc-common/hwinit-common.c | 1 - arch/arm/cpu/armv7/iproc-common/timer.c | 1 - arch/arm/cpu/armv7/ls102xa/clock.c | 2 +- arch/arm/cpu/armv7/ls102xa/cpu.c | 1 - arch/arm/cpu/armv7/ls102xa/fdt.c | 2 +- arch/arm/cpu/armv7/ls102xa/fsl_epu.c | 1 - arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c | 2 +- arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c | 2 +- arch/arm/cpu/armv7/ls102xa/soc.c | 2 +- arch/arm/cpu/armv7/ls102xa/spl.c | 1 - arch/arm/cpu/armv7/ls102xa/timer.c | 1 - arch/arm/cpu/armv7/mpu_v7r.c | 1 - arch/arm/cpu/armv7/s5p-common/cpu_info.c | 1 - arch/arm/cpu/armv7/s5p-common/pwm.c | 2 +- arch/arm/cpu/armv7/s5p-common/sromc.c | 2 +- arch/arm/cpu/armv7/s5p-common/timer.c | 1 - arch/arm/cpu/armv7/s5p4418/cpu.c | 1 - arch/arm/cpu/armv7/sunxi/psci.c | 1 - arch/arm/cpu/armv7/sunxi/sram.c | 1 - arch/arm/cpu/armv7/syslib.c | 1 - arch/arm/cpu/armv7/vf610/generic.c | 1 - arch/arm/cpu/armv7/vf610/timer.c | 1 - arch/arm/cpu/armv7/virt-dt.c | 1 - arch/arm/cpu/armv7/virt-v7.c | 1 - arch/arm/cpu/armv7m/cache.c | 1 - arch/arm/cpu/armv7m/cpu.c | 1 - arch/arm/cpu/armv7m/systick-timer.c | 2 +- arch/arm/cpu/armv8/cache_v8.c | 1 - arch/arm/cpu/armv8/cpu-dt.c | 1 - arch/arm/cpu/armv8/cpu.c | 1 - arch/arm/cpu/armv8/exception_level.c | 1 - arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 2 +- .../armv8/fsl-layerscape/fsl_lsch2_serdes.c | 3 +- .../armv8/fsl-layerscape/fsl_lsch2_speed.c | 2 +- .../armv8/fsl-layerscape/fsl_lsch3_serdes.c | 2 +- .../armv8/fsl-layerscape/fsl_lsch3_speed.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/icid.c | 2 +- .../cpu/armv8/fsl-layerscape/ls1012a_serdes.c | 2 +- .../arm/cpu/armv8/fsl-layerscape/ls1028_ids.c | 2 +- .../cpu/armv8/fsl-layerscape/ls1028a_serdes.c | 3 +- .../arm/cpu/armv8/fsl-layerscape/ls1043_ids.c | 3 +- .../cpu/armv8/fsl-layerscape/ls1043a_serdes.c | 2 +- .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 3 +- .../cpu/armv8/fsl-layerscape/ls1046a_serdes.c | 2 +- .../arm/cpu/armv8/fsl-layerscape/ls1088_ids.c | 3 +- .../cpu/armv8/fsl-layerscape/ls1088a_serdes.c | 2 +- .../cpu/armv8/fsl-layerscape/ls2080a_serdes.c | 2 +- .../arm/cpu/armv8/fsl-layerscape/ls2088_ids.c | 3 +- .../arm/cpu/armv8/fsl-layerscape/lx2160_ids.c | 3 +- .../cpu/armv8/fsl-layerscape/lx2160a_serdes.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/mp.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 2 +- arch/arm/cpu/armv8/generic_timer.c | 1 - arch/arm/cpu/armv8/hisilicon/pinmux.c | 1 - arch/arm/cpu/armv8/sec_firmware.c | 2 +- arch/arm/cpu/armv8/sha1_ce_glue.c | 1 - arch/arm/cpu/armv8/sha256_ce_glue.c | 1 - arch/arm/cpu/armv8/spin_table.c | 1 - arch/arm/cpu/armv8/spl_data.c | 1 - arch/arm/dts/k3-j7200-binman.dtsi | 95 +- arch/arm/dts/k3-j721e-binman.dtsi | 90 +- arch/arm/include/asm/arch-adi/sc5xx/sc5xx.h | 39 + arch/arm/include/asm/arch-adi/sc5xx/soc.h | 18 + arch/arm/include/asm/arch-adi/sc5xx/spl.h | 43 + .../include/asm/arch-am33xx/clk_synthesizer.h | 2 + .../arm/include/asm/arch-aspeed/scu_ast2500.h | 1 + .../arm/include/asm/arch-aspeed/scu_ast2600.h | 2 + .../asm/arch-fsl-layerscape/fsl_serdes.h | 2 + .../asm/arch-fsl-layerscape/immap_lsch2.h | 1 + arch/arm/include/asm/arch-imx8m/ddr.h | 2 +- .../arm/include/asm/arch-ls102xa/fsl_serdes.h | 2 + arch/arm/include/asm/arch-mx5/clock.h | 2 + arch/arm/include/asm/arch-mx7/sys_proto.h | 2 + arch/arm/include/asm/arch-rockchip/bootrom.h | 2 + arch/arm/include/asm/arch-rockchip/clock.h | 2 + .../include/asm/arch-rockchip/grf_rk3308.h | 2 + arch/arm/include/asm/arch-sunxi/pmic_bus.h | 2 + arch/arm/include/asm/arch-sunxi/tve.h | 2 + arch/arm/include/asm/arch-tegra/ap.h | 1 + arch/arm/include/asm/arch-tegra/cboot.h | 2 + arch/arm/include/asm/arch-tegra/gpio.h | 1 + arch/arm/include/asm/arch-tegra/tegra_i2c.h | 1 + arch/arm/include/asm/esr.h | 1 + arch/arm/include/asm/global_data.h | 1 + arch/arm/include/asm/mach-imx/gpio.h | 2 + arch/arm/include/asm/ti-common/davinci_nand.h | 1 + arch/arm/lib/asm-offsets.c | 1 - arch/arm/lib/bdinfo.c | 2 +- arch/arm/lib/bootm-fdt.c | 1 - arch/arm/lib/bootm.c | 1 - arch/arm/lib/cache-cp15.c | 1 - arch/arm/lib/cache-pl310.c | 1 - arch/arm/lib/cache.c | 2 +- arch/arm/lib/cmd_boot.c | 1 - arch/arm/lib/eabi_compat.c | 4 +- arch/arm/lib/gic-v3-its.c | 1 - arch/arm/lib/image.c | 1 - arch/arm/lib/interrupts.c | 1 - arch/arm/lib/interrupts_64.c | 1 - arch/arm/lib/interrupts_m.c | 3 +- arch/arm/lib/psci-dt.c | 1 - arch/arm/lib/reset.c | 1 - arch/arm/lib/save_prev_bl_data.c | 1 - arch/arm/lib/spl.c | 1 - arch/arm/lib/stack.c | 1 - arch/arm/lib/zimage.c | 1 - arch/arm/mach-apple/board.c | 1 - arch/arm/mach-apple/rtkit.c | 3 +- arch/arm/mach-aspeed/ast2500/board_common.c | 2 +- arch/arm/mach-aspeed/ast2500/clk_ast2500.c | 1 - arch/arm/mach-aspeed/ast2600/board_common.c | 2 +- arch/arm/mach-aspeed/ast2600/spl.c | 1 - arch/arm/mach-aspeed/ast_wdt.c | 1 - .../mach-at91/arm920t/at91rm9200_devices.c | 1 - arch/arm/mach-at91/arm920t/clock.c | 2 +- arch/arm/mach-at91/arm920t/cpu.c | 2 +- arch/arm/mach-at91/arm920t/reset.c | 1 - arch/arm/mach-at91/arm920t/timer.c | 2 +- .../mach-at91/arm926ejs/at91sam9260_devices.c | 1 - .../mach-at91/arm926ejs/at91sam9261_devices.c | 1 - .../mach-at91/arm926ejs/at91sam9263_devices.c | 1 - .../arm926ejs/at91sam9m10g45_devices.c | 1 - .../mach-at91/arm926ejs/at91sam9n12_devices.c | 1 - .../mach-at91/arm926ejs/at91sam9rl_devices.c | 1 - .../mach-at91/arm926ejs/at91sam9x5_devices.c | 1 - arch/arm/mach-at91/arm926ejs/clock.c | 3 +- arch/arm/mach-at91/arm926ejs/cpu.c | 2 +- arch/arm/mach-at91/arm926ejs/eflash.c | 1 - arch/arm/mach-at91/arm926ejs/reset.c | 1 - .../arm/mach-at91/arm926ejs/sam9x60_devices.c | 1 - arch/arm/mach-at91/arm926ejs/timer.c | 1 - arch/arm/mach-at91/armv7/clock.c | 2 +- arch/arm/mach-at91/armv7/cpu.c | 2 +- arch/arm/mach-at91/armv7/sama5d2_devices.c | 1 - arch/arm/mach-at91/armv7/sama5d3_devices.c | 1 - arch/arm/mach-at91/armv7/sama5d4_devices.c | 1 - arch/arm/mach-at91/armv7/timer.c | 1 - arch/arm/mach-at91/atmel_sfr.c | 2 +- arch/arm/mach-at91/clock.c | 2 +- arch/arm/mach-at91/include/mach/at91_common.h | 2 + arch/arm/mach-at91/matrix.c | 1 - arch/arm/mach-at91/mpddrc.c | 1 - arch/arm/mach-at91/phy.c | 2 +- arch/arm/mach-at91/sdram.c | 1 - arch/arm/mach-at91/spl.c | 1 - arch/arm/mach-at91/spl_at91.c | 2 +- arch/arm/mach-at91/spl_atmel.c | 2 +- arch/arm/mach-bcm283x/init.c | 1 - arch/arm/mach-bcm283x/mbox.c | 2 +- arch/arm/mach-bcm283x/msg.c | 1 - arch/arm/mach-bcm283x/reset.c | 2 +- arch/arm/mach-bcmbca/bcm4908/mmu_table.c | 1 - arch/arm/mach-bcmbca/bcm4912/mmu_table.c | 1 - arch/arm/mach-bcmbca/bcm63146/mmu_table.c | 1 - arch/arm/mach-bcmbca/bcm63158/mmu_table.c | 1 - arch/arm/mach-bcmbca/bcm6813/mmu_table.c | 1 - arch/arm/mach-bcmbca/bcm6856/mmu_table.c | 1 - arch/arm/mach-bcmbca/bcm6858/mmu_table.c | 1 - arch/arm/mach-davinci/cpu.c | 2 +- arch/arm/mach-davinci/da850_lowlevel.c | 2 +- arch/arm/mach-davinci/da850_pinmux.c | 1 - .../mach-davinci/include/mach/davinci_misc.h | 1 + arch/arm/mach-davinci/misc.c | 2 +- arch/arm/mach-davinci/pinmux.c | 1 - arch/arm/mach-davinci/psc.c | 1 - arch/arm/mach-davinci/reset.c | 1 - arch/arm/mach-davinci/spl.c | 2 - arch/arm/mach-davinci/timer.c | 2 +- arch/arm/mach-exynos/clock.c | 3 +- arch/arm/mach-exynos/clock_init_exynos4.c | 1 - arch/arm/mach-exynos/clock_init_exynos5.c | 1 - arch/arm/mach-exynos/common_setup.h | 2 + arch/arm/mach-exynos/dmc_common.c | 2 +- arch/arm/mach-exynos/dmc_init_ddr3.c | 1 - arch/arm/mach-exynos/exynos5_setup.h | 1 + arch/arm/mach-exynos/include/mach/power.h | 2 + arch/arm/mach-exynos/lowlevel_init.c | 1 - arch/arm/mach-exynos/mmu-arm64.c | 1 - arch/arm/mach-exynos/pinmux.c | 1 - arch/arm/mach-exynos/power.c | 2 +- arch/arm/mach-exynos/soc.c | 1 - arch/arm/mach-exynos/spl_boot.c | 1 - arch/arm/mach-exynos/system.c | 2 +- arch/arm/mach-exynos/tzpc.c | 2 +- arch/arm/mach-highbank/timer.c | 1 - arch/arm/mach-histb/board_common.c | 1 - arch/arm/mach-histb/sysmap-histb.c | 1 - arch/arm/mach-imx/cache.c | 2 +- arch/arm/mach-imx/cmd_bmode.c | 1 - arch/arm/mach-imx/cmd_dek.c | 3 +- arch/arm/mach-imx/cmd_hdmidet.c | 1 - arch/arm/mach-imx/cmd_mfgprot.c | 2 +- arch/arm/mach-imx/cmd_nandbcb.c | 1 - arch/arm/mach-imx/cpu.c | 1 - arch/arm/mach-imx/ddrmc-vf610-calibration.c | 1 - arch/arm/mach-imx/ddrmc-vf610.c | 1 - arch/arm/mach-imx/ele_ahab.c | 1 - arch/arm/mach-imx/hab.c | 1 - arch/arm/mach-imx/i2c-mxv7.c | 2 +- arch/arm/mach-imx/image-container.c | 2 +- arch/arm/mach-imx/imx8/ahab.c | 1 - arch/arm/mach-imx/imx8/clock.c | 1 - arch/arm/mach-imx/imx8/cpu.c | 1 - arch/arm/mach-imx/imx8/fdt.c | 1 - arch/arm/mach-imx/imx8/iomux.c | 1 - arch/arm/mach-imx/imx8/misc.c | 1 - arch/arm/mach-imx/imx8/snvs_security_sc.c | 1 - arch/arm/mach-imx/imx8m/clock_imx8mm.c | 1 - arch/arm/mach-imx/imx8m/clock_imx8mq.c | 1 - arch/arm/mach-imx/imx8m/clock_slice.c | 1 - arch/arm/mach-imx/imx8m/psci.c | 1 - arch/arm/mach-imx/imx8m/soc.c | 2 +- arch/arm/mach-imx/imx8ulp/cgc.c | 1 - arch/arm/mach-imx/imx8ulp/clock.c | 1 - arch/arm/mach-imx/imx8ulp/iomux.c | 1 - arch/arm/mach-imx/imx8ulp/pcc.c | 1 - arch/arm/mach-imx/imx8ulp/rdc.c | 3 +- arch/arm/mach-imx/imx9/clock.c | 1 - arch/arm/mach-imx/imx9/clock_root.c | 2 +- arch/arm/mach-imx/imx9/imx_bootaux.c | 3 +- arch/arm/mach-imx/imx9/soc.c | 2 +- arch/arm/mach-imx/imx9/trdc.c | 2 +- arch/arm/mach-imx/imx_bootaux.c | 5 +- arch/arm/mach-imx/imxrt/soc.c | 1 - arch/arm/mach-imx/iomux-v3.c | 1 - arch/arm/mach-imx/mac.c | 1 - arch/arm/mach-imx/misc.c | 1 - arch/arm/mach-imx/mmc_env.c | 1 - arch/arm/mach-imx/mmdc_size.c | 2 +- arch/arm/mach-imx/mx5/clock.c | 1 - arch/arm/mach-imx/mx5/mx53_dram.c | 1 - arch/arm/mach-imx/mx5/soc.c | 1 - arch/arm/mach-imx/mx6/clock.c | 2 +- arch/arm/mach-imx/mx6/ddr.c | 1 - arch/arm/mach-imx/mx6/litesom.c | 2 +- arch/arm/mach-imx/mx6/module_fuse.c | 1 - arch/arm/mach-imx/mx6/mp.c | 1 - arch/arm/mach-imx/mx6/opos6ul.c | 2 +- arch/arm/mach-imx/mx6/soc.c | 1 - arch/arm/mach-imx/mx7/clock.c | 3 +- arch/arm/mach-imx/mx7/clock_slice.c | 1 - arch/arm/mach-imx/mx7/ddr.c | 1 - arch/arm/mach-imx/mx7/psci-mx7.c | 1 - arch/arm/mach-imx/mx7/soc.c | 1 - arch/arm/mach-imx/mx7ulp/clock.c | 2 +- arch/arm/mach-imx/mx7ulp/iomux.c | 1 - arch/arm/mach-imx/mx7ulp/pcc.c | 1 - arch/arm/mach-imx/mx7ulp/scg.c | 2 +- arch/arm/mach-imx/mx7ulp/soc.c | 2 +- arch/arm/mach-imx/priblob.c | 1 - arch/arm/mach-imx/rdc-sema.c | 1 - arch/arm/mach-imx/speed.c | 2 +- arch/arm/mach-imx/spl.c | 2 +- arch/arm/mach-imx/spl_imx_romapi.c | 1 - arch/arm/mach-imx/syscounter.c | 2 +- arch/arm/mach-imx/timer.c | 1 - arch/arm/mach-imx/video.c | 3 +- arch/arm/mach-k3/am64x/Makefile | 1 + arch/arm/mach-k3/am64x/am642_init.c | 92 +- arch/arm/mach-k3/am64x/boot.c | 105 ++ arch/arm/mach-kirkwood/cache.c | 1 - arch/arm/mach-kirkwood/cpu.c | 1 - arch/arm/mach-kirkwood/include/mach/mpp.h | 2 + arch/arm/mach-kirkwood/mpp.c | 1 - arch/arm/mach-lpc32xx/clk.c | 1 - arch/arm/mach-lpc32xx/cpu.c | 1 - arch/arm/mach-lpc32xx/devices.c | 2 +- arch/arm/mach-lpc32xx/dram.c | 1 - arch/arm/mach-lpc32xx/timer.c | 1 - arch/arm/mach-mediatek/Kconfig | 1 + arch/arm/mach-mediatek/cpu.c | 1 - arch/arm/mach-mediatek/mt7622/init.c | 1 - arch/arm/mach-mediatek/mt7623/init.c | 2 +- arch/arm/mach-mediatek/mt7629/init.c | 2 +- arch/arm/mach-mediatek/mt7981/init.c | 1 - arch/arm/mach-mediatek/mt7986/init.c | 1 - arch/arm/mach-mediatek/mt7988/init.c | 1 - arch/arm/mach-mediatek/mt8183/init.c | 1 - arch/arm/mach-mediatek/mt8512/init.c | 1 - arch/arm/mach-mediatek/mt8516/init.c | 1 - arch/arm/mach-mediatek/mt8518/init.c | 1 - arch/arm/mach-mediatek/spl.c | 1 - arch/arm/mach-meson/board-a1.c | 2 +- arch/arm/mach-meson/board-axg.c | 1 - arch/arm/mach-meson/board-common.c | 1 - arch/arm/mach-meson/board-g12a.c | 1 - arch/arm/mach-meson/board-gx.c | 1 - arch/arm/mach-meson/board-info.c | 1 - arch/arm/mach-meson/sm.c | 1 - arch/arm/mach-mvebu/alleycat5/cpu.c | 2 +- arch/arm/mach-mvebu/alleycat5/soc.c | 1 - arch/arm/mach-mvebu/arm64-common.c | 2 +- arch/arm/mach-mvebu/armada3700/cpu.c | 1 - arch/arm/mach-mvebu/armada3700/efuse.c | 3 +- arch/arm/mach-mvebu/armada3700/mbox.c | 2 +- arch/arm/mach-mvebu/armada8k/cpu.c | 1 - arch/arm/mach-mvebu/armada8k/dram.c | 2 +- arch/arm/mach-mvebu/cpu.c | 2 +- arch/arm/mach-mvebu/dram.c | 1 - arch/arm/mach-mvebu/efuse.c | 1 - arch/arm/mach-mvebu/gpio.c | 1 - arch/arm/mach-mvebu/mbus.c | 2 +- .../serdes/a38x/high_speed_env_spec-38x.c | 1 - .../serdes/a38x/high_speed_env_spec.c | 2 +- arch/arm/mach-mvebu/serdes/a38x/seq_exec.c | 1 - arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c | 1 - .../serdes/axp/high_speed_env_lib.c | 2 +- .../serdes/axp/high_speed_env_spec.c | 1 - arch/arm/mach-mvebu/spl.c | 1 - arch/arm/mach-mvebu/system-controller.c | 1 - arch/arm/mach-nexell/clock.c | 2 +- .../mach-nexell/include/mach/mipi_display.h | 2 + arch/arm/mach-nexell/include/mach/reset.h | 2 + arch/arm/mach-nexell/reset.c | 1 - arch/arm/mach-nexell/tieoff.c | 1 - arch/arm/mach-nexell/timer.c | 1 - arch/arm/mach-npcm/npcm7xx/cpu.c | 1 - arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c | 2 +- arch/arm/mach-npcm/npcm8xx/cpu.c | 1 - arch/arm/mach-npcm/npcm8xx/reset.c | 1 - arch/arm/mach-octeontx/clock.c | 1 - arch/arm/mach-octeontx/cpu.c | 1 - arch/arm/mach-octeontx2/clock.c | 1 - arch/arm/mach-octeontx2/cpu.c | 1 - arch/arm/mach-omap2/abb.c | 1 - arch/arm/mach-omap2/am33xx/board.c | 2 +- arch/arm/mach-omap2/am33xx/chilisom.c | 1 - arch/arm/mach-omap2/am33xx/clk_synthesizer.c | 3 +- arch/arm/mach-omap2/am33xx/clock.c | 1 - arch/arm/mach-omap2/am33xx/clock_am33xx.c | 1 - arch/arm/mach-omap2/am33xx/clock_am43xx.c | 1 - arch/arm/mach-omap2/am33xx/ddr.c | 2 +- arch/arm/mach-omap2/am33xx/emif4.c | 1 - arch/arm/mach-omap2/am33xx/fdt.c | 1 - arch/arm/mach-omap2/am33xx/mux.c | 1 - arch/arm/mach-omap2/am33xx/sys_info.c | 1 - arch/arm/mach-omap2/boot-common.c | 1 - arch/arm/mach-omap2/clocks-common.c | 1 - arch/arm/mach-omap2/emif-common.c | 2 +- arch/arm/mach-omap2/fdt-common.c | 2 +- arch/arm/mach-omap2/hwinit-common.c | 1 - arch/arm/mach-omap2/mem-common.c | 2 +- arch/arm/mach-omap2/omap-cache.c | 2 +- arch/arm/mach-omap2/omap3/am35x_musb.c | 2 +- arch/arm/mach-omap2/omap3/board.c | 1 - arch/arm/mach-omap2/omap3/boot.c | 1 - arch/arm/mach-omap2/omap3/clock.c | 3 +- arch/arm/mach-omap2/omap3/emac.c | 1 - arch/arm/mach-omap2/omap3/emif4.c | 2 +- arch/arm/mach-omap2/omap3/sdrc.c | 1 - arch/arm/mach-omap2/omap3/spl_id_nand.c | 1 - arch/arm/mach-omap2/omap3/sys_info.c | 3 +- arch/arm/mach-omap2/omap4/boot.c | 1 - arch/arm/mach-omap2/omap4/emif.c | 1 - arch/arm/mach-omap2/omap4/hw_data.c | 1 - arch/arm/mach-omap2/omap4/hwinit.c | 1 - arch/arm/mach-omap2/omap4/sdram_elpida.c | 1 - arch/arm/mach-omap2/omap5/abb.c | 2 +- arch/arm/mach-omap2/omap5/boot.c | 1 - arch/arm/mach-omap2/omap5/dra7xx_iodelay.c | 2 +- arch/arm/mach-omap2/omap5/emif.c | 1 - arch/arm/mach-omap2/omap5/fdt.c | 2 +- arch/arm/mach-omap2/omap5/hw_data.c | 1 - arch/arm/mach-omap2/omap5/hwinit.c | 1 - arch/arm/mach-omap2/omap5/sdram.c | 1 - arch/arm/mach-omap2/sec-common.c | 2 +- arch/arm/mach-omap2/timer.c | 2 +- arch/arm/mach-omap2/utils.c | 2 +- arch/arm/mach-omap2/vc.c | 2 +- arch/arm/mach-orion5x/cpu.c | 1 - arch/arm/mach-orion5x/dram.c | 1 - arch/arm/mach-orion5x/timer.c | 2 +- arch/arm/mach-owl/soc.c | 2 +- arch/arm/mach-owl/sysmap-owl.c | 1 - arch/arm/mach-renesas/memmap-gen3.c | 1 - arch/arm/mach-renesas/memmap-rzg2l.c | 1 - arch/arm/mach-rockchip/board.c | 2 +- arch/arm/mach-rockchip/boot_mode.c | 1 - arch/arm/mach-rockchip/bootrom.c | 1 - arch/arm/mach-rockchip/cpu-info.c | 1 - arch/arm/mach-rockchip/px30-board-tpl.c | 1 - arch/arm/mach-rockchip/px30/clk_px30.c | 1 - arch/arm/mach-rockchip/px30/px30.c | 1 - arch/arm/mach-rockchip/px30/syscon_px30.c | 1 - arch/arm/mach-rockchip/rk3036-board-spl.c | 1 - arch/arm/mach-rockchip/rk3036/clk_rk3036.c | 1 - arch/arm/mach-rockchip/rk3036/rk3036.c | 1 - arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 2 +- arch/arm/mach-rockchip/rk3036/syscon_rk3036.c | 1 - arch/arm/mach-rockchip/rk3066/clk_rk3066.c | 1 - arch/arm/mach-rockchip/rk3066/rk3066.c | 1 - arch/arm/mach-rockchip/rk3066/syscon_rk3066.c | 1 - arch/arm/mach-rockchip/rk3128/clk_rk3128.c | 1 - arch/arm/mach-rockchip/rk3128/syscon_rk3128.c | 1 - arch/arm/mach-rockchip/rk3188/clk_rk3188.c | 1 - arch/arm/mach-rockchip/rk3188/rk3188.c | 1 - arch/arm/mach-rockchip/rk3188/syscon_rk3188.c | 1 - arch/arm/mach-rockchip/rk322x/clk_rk322x.c | 1 - arch/arm/mach-rockchip/rk322x/syscon_rk322x.c | 1 - arch/arm/mach-rockchip/rk3288/clk_rk3288.c | 1 - arch/arm/mach-rockchip/rk3288/rk3288.c | 1 - arch/arm/mach-rockchip/rk3288/syscon_rk3288.c | 1 - arch/arm/mach-rockchip/rk3308/clk_rk3308.c | 1 - arch/arm/mach-rockchip/rk3308/rk3308.c | 1 - arch/arm/mach-rockchip/rk3308/syscon_rk3308.c | 1 - arch/arm/mach-rockchip/rk3328/clk_rk3328.c | 1 - arch/arm/mach-rockchip/rk3328/rk3328.c | 1 - arch/arm/mach-rockchip/rk3328/syscon_rk3328.c | 1 - arch/arm/mach-rockchip/rk3368/clk_rk3368.c | 1 - arch/arm/mach-rockchip/rk3368/rk3368.c | 1 - arch/arm/mach-rockchip/rk3368/syscon_rk3368.c | 1 - arch/arm/mach-rockchip/rk3399/clk_rk3399.c | 1 - arch/arm/mach-rockchip/rk3399/rk3399.c | 1 - arch/arm/mach-rockchip/rk3399/syscon_rk3399.c | 1 - arch/arm/mach-rockchip/rk3568/clk_rk3568.c | 1 - arch/arm/mach-rockchip/rk3568/rk3568.c | 1 - arch/arm/mach-rockchip/rk3568/syscon_rk3568.c | 1 - arch/arm/mach-rockchip/rk3588/clk_rk3588.c | 1 - arch/arm/mach-rockchip/rk3588/rk3588.c | 1 - arch/arm/mach-rockchip/rk3588/syscon_rk3588.c | 1 - arch/arm/mach-rockchip/rv1108/clk_rv1108.c | 1 - arch/arm/mach-rockchip/rv1108/syscon_rv1108.c | 1 - arch/arm/mach-rockchip/rv1126/clk_rv1126.c | 1 - arch/arm/mach-rockchip/rv1126/rv1126.c | 1 - arch/arm/mach-rockchip/rv1126/syscon_rv1126.c | 1 - arch/arm/mach-rockchip/sdram.c | 2 +- arch/arm/mach-rockchip/spl-boot-order.c | 1 - arch/arm/mach-rockchip/tpl.c | 1 - arch/arm/mach-s5pc1xx/cache.c | 1 - arch/arm/mach-s5pc1xx/clock.c | 2 +- arch/arm/mach-s5pc1xx/pinmux.c | 1 - arch/arm/mach-sc5xx/Kconfig | 475 +++++++ arch/arm/mach-sc5xx/Makefile | 19 + arch/arm/mach-sc5xx/config.mk | 16 + arch/arm/mach-sc5xx/init/Makefile | 11 + arch/arm/mach-sc5xx/init/clkinit.c | 558 ++++++++ arch/arm/mach-sc5xx/init/clkinit.h | 18 + arch/arm/mach-sc5xx/init/dmcinit.c | 954 ++++++++++++++ arch/arm/mach-sc5xx/init/dmcinit.h | 31 + arch/arm/mach-sc5xx/init/mem/is43tr16512bl.h | 62 + arch/arm/mach-sc5xx/init/mem/mt41k128m16jt.h | 50 + arch/arm/mach-sc5xx/init/mem/mt41k512m16ha.h | 50 + arch/arm/mach-sc5xx/init/mem/mt47h128m16rt.h | 49 + arch/arm/mach-sc5xx/rcu.c | 22 + arch/arm/mach-sc5xx/sc57x.c | 32 + arch/arm/mach-sc5xx/sc58x.c | 32 + arch/arm/mach-sc5xx/sc59x.c | 43 + arch/arm/mach-sc5xx/sc59x_64.c | 97 ++ arch/arm/mach-sc5xx/soc.c | 179 +++ arch/arm/mach-sc5xx/spl.c | 102 ++ arch/arm/mach-socfpga/board.c | 2 +- arch/arm/mach-socfpga/clock_manager.c | 1 - arch/arm/mach-socfpga/clock_manager_agilex.c | 1 - arch/arm/mach-socfpga/clock_manager_agilex5.c | 1 - arch/arm/mach-socfpga/clock_manager_arria10.c | 1 - arch/arm/mach-socfpga/clock_manager_gen5.c | 1 - arch/arm/mach-socfpga/clock_manager_n5x.c | 1 - arch/arm/mach-socfpga/clock_manager_s10.c | 2 +- arch/arm/mach-socfpga/firewall.c | 2 +- arch/arm/mach-socfpga/fpga_manager.c | 2 +- arch/arm/mach-socfpga/freeze_controller.c | 2 +- .../mach-socfpga/include/mach/clock_manager.h | 2 + .../include/mach/secure_reg_helper.h | 2 + arch/arm/mach-socfpga/mailbox_s10.c | 1 - arch/arm/mach-socfpga/misc.c | 2 +- arch/arm/mach-socfpga/misc_arria10.c | 2 +- arch/arm/mach-socfpga/misc_gen5.c | 2 +- arch/arm/mach-socfpga/misc_soc64.c | 1 - arch/arm/mach-socfpga/mmu-arm64_s10.c | 1 - arch/arm/mach-socfpga/pinmux_arria10.c | 2 +- arch/arm/mach-socfpga/reset_manager_arria10.c | 1 - arch/arm/mach-socfpga/reset_manager_gen5.c | 2 +- arch/arm/mach-socfpga/reset_manager_s10.c | 1 - arch/arm/mach-socfpga/scan_manager.c | 2 +- arch/arm/mach-socfpga/secure_reg_helper.c | 1 - arch/arm/mach-socfpga/secure_vab.c | 1 - arch/arm/mach-socfpga/smc_api.c | 3 +- arch/arm/mach-socfpga/spl_a10.c | 3 +- arch/arm/mach-socfpga/spl_agilex.c | 2 - arch/arm/mach-socfpga/spl_gen5.c | 2 - arch/arm/mach-socfpga/spl_n5x.c | 2 - arch/arm/mach-socfpga/spl_s10.c | 2 - arch/arm/mach-socfpga/spl_soc64.c | 1 - arch/arm/mach-socfpga/system_manager_gen5.c | 1 - arch/arm/mach-socfpga/system_manager_soc64.c | 1 - arch/arm/mach-socfpga/timer.c | 2 +- arch/arm/mach-socfpga/timer_s10.c | 1 - arch/arm/mach-socfpga/vab.c | 2 +- arch/arm/mach-socfpga/wrap_handoff_soc64.c | 1 - arch/arm/mach-socfpga/wrap_iocsr_config.c | 2 +- arch/arm/mach-socfpga/wrap_pinmux_config.c | 3 +- arch/arm/mach-socfpga/wrap_pll_config.c | 2 +- arch/arm/mach-socfpga/wrap_pll_config_soc64.c | 1 - arch/arm/mach-socfpga/wrap_sdram_config.c | 4 +- arch/arm/mach-stm32/soc.c | 1 - arch/arm/mach-stm32mp/boot_params.c | 2 +- arch/arm/mach-stm32mp/bsec.c | 1 - arch/arm/mach-stm32mp/cmd_stm32key.c | 1 - .../cmd_stm32prog/cmd_stm32prog.c | 1 - .../cmd_stm32prog/stm32prog_serial.c | 2 +- .../cmd_stm32prog/stm32prog_usb.c | 1 - arch/arm/mach-stm32mp/dram_init.c | 1 - arch/arm/mach-stm32mp/stm32mp1/cpu.c | 1 - arch/arm/mach-stm32mp/stm32mp1/fdt.c | 2 +- arch/arm/mach-stm32mp/stm32mp1/psci.c | 2 +- .../arm/mach-stm32mp/stm32mp1/pwr_regulator.c | 2 +- arch/arm/mach-stm32mp/stm32mp1/spl.c | 2 +- arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c | 2 +- arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c | 1 - arch/arm/mach-stm32mp/syscon.c | 1 - arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c | 1 - arch/arm/mach-sunxi/dram_timings/ddr3_1333.c | 1 - .../mach-sunxi/dram_timings/h616_ddr3_1333.c | 1 - .../arm/mach-sunxi/dram_timings/h616_lpddr3.c | 1 - .../dram_timings/h616_lpddr4_2133.c | 1 - .../mach-sunxi/dram_timings/h6_ddr3_1333.c | 1 - arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c | 1 - .../mach-sunxi/dram_timings/lpddr3_stock.c | 1 - arch/arm/mach-tegra/ap.c | 2 +- arch/arm/mach-tegra/arm64-mmu.c | 1 - arch/arm/mach-tegra/board.c | 2 +- arch/arm/mach-tegra/board2.c | 2 +- arch/arm/mach-tegra/cache.c | 1 - arch/arm/mach-tegra/cboot.c | 1 - arch/arm/mach-tegra/clock.c | 1 - arch/arm/mach-tegra/cmd_enterrcm.c | 1 - arch/arm/mach-tegra/cpu.c | 1 - arch/arm/mach-tegra/crypto.c | 1 - arch/arm/mach-tegra/dt-setup.c | 1 - arch/arm/mach-tegra/emc.c | 1 - arch/arm/mach-tegra/fuse.c | 1 - arch/arm/mach-tegra/gpu.c | 1 - arch/arm/mach-tegra/ivc.c | 2 +- arch/arm/mach-tegra/pmc.c | 1 - arch/arm/mach-tegra/powergate.c | 2 +- arch/arm/mach-tegra/spl.c | 1 - arch/arm/mach-tegra/sys_info.c | 1 - arch/arm/mach-tegra/tegra114/clock.c | 1 - arch/arm/mach-tegra/tegra114/cpu.c | 1 - arch/arm/mach-tegra/tegra124/clock.c | 2 +- arch/arm/mach-tegra/tegra124/cpu.c | 1 - arch/arm/mach-tegra/tegra124/pmc.c | 1 - arch/arm/mach-tegra/tegra124/psci.c | 1 - arch/arm/mach-tegra/tegra124/xusb-padctl.c | 2 +- arch/arm/mach-tegra/tegra20/bct.c | 1 - arch/arm/mach-tegra/tegra20/clock.c | 1 - arch/arm/mach-tegra/tegra20/cpu.c | 1 - arch/arm/mach-tegra/tegra20/display.c | 1 - arch/arm/mach-tegra/tegra20/emc.c | 2 +- arch/arm/mach-tegra/tegra20/pmu.c | 1 - arch/arm/mach-tegra/tegra20/warmboot.c | 1 - arch/arm/mach-tegra/tegra20/warmboot_avp.c | 2 +- arch/arm/mach-tegra/tegra210/clock.c | 2 +- arch/arm/mach-tegra/tegra210/xusb-padctl.c | 2 +- arch/arm/mach-tegra/tegra30/bct.c | 2 +- arch/arm/mach-tegra/tegra30/clock.c | 1 - arch/arm/mach-tegra/tegra30/cpu.c | 1 - arch/arm/mach-tegra/xusb-padctl-common.c | 1 - arch/arm/mach-tegra/xusb-padctl-dummy.c | 2 +- arch/arm/mach-u8500/cache.c | 2 +- arch/arm/mach-u8500/cpuinfo.c | 1 - arch/arm/mach-uniphier/dram_init.c | 1 - arch/arm/mach-versal-net/clk.c | 1 - arch/arm/mach-versal-net/cpu.c | 1 - arch/arm/mach-versal/clk.c | 1 - arch/arm/mach-versal/cpu.c | 1 - arch/arm/mach-versal/mp.c | 3 +- arch/arm/mach-versatile/Makefile | 7 - arch/arm/mach-versatile/reset.S | 28 - arch/arm/mach-versatile/timer.c | 62 - arch/arm/mach-zynq/clk.c | 1 - arch/arm/mach-zynq/cpu.c | 3 +- arch/arm/mach-zynq/ddrc.c | 2 +- arch/arm/mach-zynq/slcr.c | 1 - arch/arm/mach-zynq/spl.c | 1 - arch/arm/mach-zynqmp-r5/cpu.c | 1 - arch/arm/mach-zynqmp/aes.c | 3 +- arch/arm/mach-zynqmp/clk.c | 1 - arch/arm/mach-zynqmp/cpu.c | 3 +- arch/arm/mach-zynqmp/ecc_spl_init.c | 1 - arch/arm/mach-zynqmp/handoff.c | 1 - .../arm/mach-zynqmp/include/mach/zynqmp_aes.h | 2 + arch/arm/mach-zynqmp/mp.c | 4 +- arch/arm/mach-zynqmp/psu_spl_init.c | 1 - arch/arm/mach-zynqmp/spl.c | 1 - arch/m68k/include/asm/global_data.h | 2 + arch/m68k/lib/bdinfo.c | 1 - arch/microblaze/cpu/spl.c | 1 - arch/microblaze/include/asm/global_data.h | 1 + arch/mips/include/asm/global_data.h | 1 + arch/mips/lib/traps.c | 1 - arch/mips/mach-mtmips/Kconfig | 1 + arch/nios2/cpu/cpu.c | 2 +- arch/nios2/cpu/interrupts.c | 1 - arch/nios2/cpu/traps.c | 2 +- arch/nios2/include/asm/global_data.h | 1 + arch/nios2/lib/bootm.c | 1 - arch/nios2/lib/cache.c | 1 - arch/powerpc/cpu/mpc83xx/cpu.c | 1 - arch/powerpc/cpu/mpc83xx/ecc.c | 1 - arch/powerpc/cpu/mpc83xx/fdt.c | 1 - arch/powerpc/cpu/mpc83xx/interrupts.c | 1 - arch/powerpc/cpu/mpc83xx/law.c | 1 - arch/powerpc/cpu/mpc83xx/pci.c | 1 - arch/powerpc/cpu/mpc83xx/pcie.c | 1 - arch/powerpc/cpu/mpc83xx/qe_io.c | 1 - arch/powerpc/cpu/mpc83xx/serdes.c | 1 - arch/powerpc/cpu/mpc83xx/spd_sdram.c | 1 - arch/powerpc/cpu/mpc83xx/speed.c | 1 - arch/powerpc/cpu/mpc83xx/spl_minimal.c | 2 +- arch/powerpc/cpu/mpc83xx/traps.c | 1 - arch/powerpc/cpu/mpc85xx/b4860_ids.c | 3 +- arch/powerpc/cpu/mpc85xx/b4860_serdes.c | 1 - arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c | 1 - arch/powerpc/cpu/mpc85xx/c29x_serdes.c | 1 - arch/powerpc/cpu/mpc85xx/cmd_errata.c | 1 - arch/powerpc/cpu/mpc85xx/cpu.c | 1 - arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 3 +- arch/powerpc/cpu/mpc85xx/fdt.c | 2 +- .../powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 1 - arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 2 +- arch/powerpc/cpu/mpc85xx/interrupts.c | 2 +- arch/powerpc/cpu/mpc85xx/liodn.c | 2 +- arch/powerpc/cpu/mpc85xx/mp.c | 2 +- arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c | 1 - arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c | 1 - arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c | 1 - arch/powerpc/cpu/mpc85xx/p1010_serdes.c | 1 - arch/powerpc/cpu/mpc85xx/p1021_serdes.c | 1 - arch/powerpc/cpu/mpc85xx/p1023_serdes.c | 1 - arch/powerpc/cpu/mpc85xx/p2020_serdes.c | 1 - arch/powerpc/cpu/mpc85xx/p2041_ids.c | 3 +- arch/powerpc/cpu/mpc85xx/p2041_serdes.c | 1 - arch/powerpc/cpu/mpc85xx/p3041_ids.c | 3 +- arch/powerpc/cpu/mpc85xx/p3041_serdes.c | 1 - arch/powerpc/cpu/mpc85xx/p4080_ids.c | 3 +- arch/powerpc/cpu/mpc85xx/p4080_serdes.c | 1 - arch/powerpc/cpu/mpc85xx/p5040_ids.c | 3 +- arch/powerpc/cpu/mpc85xx/p5040_serdes.c | 1 - arch/powerpc/cpu/mpc85xx/portals.c | 1 - arch/powerpc/cpu/mpc85xx/qe_io.c | 2 +- arch/powerpc/cpu/mpc85xx/speed.c | 1 - arch/powerpc/cpu/mpc85xx/spl_minimal.c | 1 - arch/powerpc/cpu/mpc85xx/t1024_ids.c | 3 +- arch/powerpc/cpu/mpc85xx/t1024_serdes.c | 1 - arch/powerpc/cpu/mpc85xx/t1040_ids.c | 3 +- arch/powerpc/cpu/mpc85xx/t1040_serdes.c | 3 +- arch/powerpc/cpu/mpc85xx/t2080_ids.c | 3 +- arch/powerpc/cpu/mpc85xx/t2080_serdes.c | 3 +- arch/powerpc/cpu/mpc85xx/t4240_ids.c | 3 +- arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 1 - arch/powerpc/cpu/mpc85xx/tlb.c | 2 +- arch/powerpc/cpu/mpc85xx/traps.c | 2 +- arch/powerpc/cpu/mpc8xxx/cpu.c | 1 - arch/powerpc/cpu/mpc8xxx/fdt.c | 1 - arch/powerpc/cpu/mpc8xxx/fsl_lbc.c | 1 - arch/powerpc/cpu/mpc8xxx/fsl_pamu.c | 4 +- arch/powerpc/cpu/mpc8xxx/law.c | 1 - arch/powerpc/cpu/mpc8xxx/pamu_table.c | 1 - arch/powerpc/cpu/mpc8xxx/srio.c | 2 +- arch/powerpc/include/asm/cache.h | 2 + arch/powerpc/include/asm/fsl_dma.h | 2 +- arch/powerpc/include/asm/fsl_liodn.h | 4 +- arch/powerpc/include/asm/fsl_portals.h | 2 + arch/powerpc/include/asm/fsl_serdes.h | 1 + arch/powerpc/include/asm/global_data.h | 2 + arch/powerpc/include/asm/immap_8xx.h | 2 + arch/powerpc/lib/bdinfo.c | 1 - arch/powerpc/lib/bootm.c | 2 +- arch/powerpc/lib/cache.c | 1 - arch/powerpc/lib/extable.c | 1 - arch/powerpc/lib/interrupts.c | 2 +- arch/powerpc/lib/kgdb.c | 1 - arch/powerpc/lib/spl.c | 1 - arch/powerpc/lib/stack.c | 1 - arch/powerpc/lib/time.c | 1 - arch/riscv/lib/boot.c | 3 +- arch/sandbox/include/asm/global_data.h | 1 + arch/sh/cpu/sh4/cache.c | 1 - arch/sh/cpu/sh4/cpu.c | 1 - arch/sh/cpu/sh4/interrupts.c | 1 - arch/sh/cpu/sh4/watchdog.c | 1 - arch/sh/include/asm/global_data.h | 2 + arch/sh/lib/board.c | 2 +- arch/sh/lib/bootm.c | 2 +- arch/sh/lib/time.c | 1 - arch/sh/lib/time_sh2.c | 1 - arch/sh/lib/zimageboot.c | 2 +- arch/x86/cpu/acpi_gpe.c | 2 +- arch/x86/cpu/apollolake/acpi.c | 1 - arch/x86/cpu/apollolake/cpu.c | 1 - arch/x86/cpu/apollolake/cpu_common.c | 1 - arch/x86/cpu/apollolake/cpu_spl.c | 1 - arch/x86/cpu/apollolake/fsp_bindings.c | 1 - arch/x86/cpu/apollolake/fsp_m.c | 1 - arch/x86/cpu/apollolake/fsp_s.c | 1 - arch/x86/cpu/apollolake/hostbridge.c | 1 - arch/x86/cpu/apollolake/lpc.c | 1 - arch/x86/cpu/apollolake/pch.c | 1 - arch/x86/cpu/apollolake/pmc.c | 1 - arch/x86/cpu/apollolake/punit.c | 2 +- arch/x86/cpu/apollolake/spl.c | 1 - arch/x86/cpu/apollolake/systemagent.c | 1 - arch/x86/cpu/apollolake/uart.c | 1 - arch/x86/cpu/baytrail/acpi.c | 1 - arch/x86/cpu/baytrail/cpu.c | 1 - arch/x86/cpu/baytrail/early_uart.c | 1 - arch/x86/cpu/baytrail/fsp_configs.c | 1 - arch/x86/cpu/baytrail/valleyview.c | 2 +- arch/x86/cpu/braswell/braswell.c | 2 +- arch/x86/cpu/braswell/early_uart.c | 1 - arch/x86/cpu/braswell/fsp_configs.c | 1 - arch/x86/cpu/broadwell/adsp.c | 1 - arch/x86/cpu/broadwell/cpu.c | 1 - arch/x86/cpu/broadwell/cpu_from_spl.c | 2 +- arch/x86/cpu/broadwell/cpu_full.c | 1 - arch/x86/cpu/broadwell/iobp.c | 1 - arch/x86/cpu/broadwell/lpc.c | 1 - arch/x86/cpu/broadwell/me.c | 1 - arch/x86/cpu/broadwell/northbridge.c | 1 - arch/x86/cpu/broadwell/pch.c | 1 - arch/x86/cpu/broadwell/pinctrl_broadwell.c | 1 - arch/x86/cpu/broadwell/power_state.c | 1 - arch/x86/cpu/broadwell/refcode.c | 2 +- arch/x86/cpu/broadwell/sata.c | 1 - arch/x86/cpu/broadwell/sdram.c | 1 - arch/x86/cpu/coreboot/coreboot.c | 1 - arch/x86/cpu/coreboot/coreboot_spl.c | 1 - arch/x86/cpu/coreboot/sdram.c | 1 - arch/x86/cpu/coreboot/timestamp.c | 2 +- arch/x86/cpu/cpu.c | 1 - arch/x86/cpu/cpu_x86.c | 1 - arch/x86/cpu/efi/app.c | 2 +- arch/x86/cpu/efi/payload.c | 2 +- arch/x86/cpu/efi/sdram.c | 1 - arch/x86/cpu/i386/cpu.c | 2 +- arch/x86/cpu/i386/interrupt.c | 1 - arch/x86/cpu/intel_common/acpi.c | 1 - arch/x86/cpu/intel_common/car.S | 1 - arch/x86/cpu/intel_common/cpu.c | 1 - arch/x86/cpu/intel_common/cpu_from_spl.c | 1 - arch/x86/cpu/intel_common/fast_spi.c | 1 - arch/x86/cpu/intel_common/generic_wifi.c | 1 - arch/x86/cpu/intel_common/intel_opregion.c | 1 - arch/x86/cpu/intel_common/itss.c | 1 - arch/x86/cpu/intel_common/lpc.c | 1 - arch/x86/cpu/intel_common/lpss.c | 1 - arch/x86/cpu/intel_common/me_status.c | 1 - arch/x86/cpu/intel_common/microcode.c | 1 - arch/x86/cpu/intel_common/mrc.c | 4 +- arch/x86/cpu/intel_common/p2sb.c | 1 - arch/x86/cpu/intel_common/pch.c | 1 - arch/x86/cpu/intel_common/report_platform.c | 2 +- arch/x86/cpu/ioapic.c | 1 - arch/x86/cpu/irq.c | 1 - arch/x86/cpu/ivybridge/bd82x6x.c | 1 - arch/x86/cpu/ivybridge/cpu.c | 1 - arch/x86/cpu/ivybridge/early_me.c | 1 - arch/x86/cpu/ivybridge/fsp_configs.c | 1 - arch/x86/cpu/ivybridge/ivybridge.c | 2 +- arch/x86/cpu/ivybridge/lpc.c | 1 - arch/x86/cpu/ivybridge/model_206ax.c | 1 - arch/x86/cpu/ivybridge/northbridge.c | 1 - arch/x86/cpu/ivybridge/sata.c | 1 - arch/x86/cpu/ivybridge/sdram.c | 1 - arch/x86/cpu/ivybridge/sdram_nop.c | 1 - arch/x86/cpu/lapic.c | 1 - arch/x86/cpu/mp_init.c | 2 +- arch/x86/cpu/mtrr.c | 1 - arch/x86/cpu/pci.c | 1 - arch/x86/cpu/qemu/cpu.c | 1 - arch/x86/cpu/qemu/dram.c | 1 - arch/x86/cpu/qemu/e820.c | 1 - arch/x86/cpu/qemu/qemu.c | 2 +- arch/x86/cpu/qfw_cpu.c | 1 - arch/x86/cpu/quark/acpi.c | 2 +- arch/x86/cpu/quark/dram.c | 1 - arch/x86/cpu/quark/hte.c | 1 - arch/x86/cpu/quark/mrc.c | 2 +- arch/x86/cpu/quark/mrc_util.c | 2 +- arch/x86/cpu/quark/msg_port.c | 1 - arch/x86/cpu/quark/quark.c | 2 +- arch/x86/cpu/quark/smc.c | 3 +- arch/x86/cpu/queensbay/fsp_configs.c | 1 - arch/x86/cpu/queensbay/tnc.c | 1 - arch/x86/cpu/slimbootloader/sdram.c | 1 - arch/x86/cpu/slimbootloader/serial.c | 1 - arch/x86/cpu/slimbootloader/slimbootloader.c | 1 - arch/x86/cpu/tangier/acpi.c | 1 - arch/x86/cpu/tangier/pinmux.c | 1 - arch/x86/cpu/tangier/sdram.c | 1 - arch/x86/cpu/tangier/sysreset.c | 1 - arch/x86/cpu/tangier/tangier.c | 1 - arch/x86/cpu/turbo.c | 1 - arch/x86/cpu/x86_64/cpu.c | 1 - arch/x86/cpu/x86_64/interrupts.c | 1 - arch/x86/cpu/x86_64/misc.c | 1 - arch/x86/include/asm/arch-quark/mrc.h | 2 + arch/x86/include/asm/arch-quark/msg_port.h | 2 + arch/x86/include/asm/arch-quark/quark.h | 2 + arch/x86/include/asm/cb_sysinfo.h | 1 + arch/x86/include/asm/coreboot_tables.h | 3 + arch/x86/include/asm/early_cmos.h | 2 + arch/x86/include/asm/global_data.h | 1 + arch/x86/include/asm/handoff.h | 2 + arch/x86/include/asm/me_common.h | 1 + arch/x86/include/asm/mp.h | 1 + arch/x86/lib/acpi.c | 1 - arch/x86/lib/acpi_nhlt.c | 1 - arch/x86/lib/acpi_s3.c | 1 - arch/x86/lib/acpi_table.c | 1 - arch/x86/lib/acpigen.c | 1 - arch/x86/lib/asm-offsets.c | 1 - arch/x86/lib/bdinfo.c | 1 - arch/x86/lib/bios.c | 1 - arch/x86/lib/bios_interrupts.c | 1 - arch/x86/lib/bootm.c | 1 - arch/x86/lib/cmd_boot.c | 1 - arch/x86/lib/coreboot/cb_support.c | 2 +- arch/x86/lib/coreboot/cb_sysinfo.c | 2 +- arch/x86/lib/coreboot_table.c | 1 - arch/x86/lib/div64.c | 2 +- arch/x86/lib/e820.c | 1 - arch/x86/lib/early_cmos.c | 1 - arch/x86/lib/fsp/fsp_common.c | 1 - arch/x86/lib/fsp/fsp_dram.c | 1 - arch/x86/lib/fsp/fsp_graphics.c | 1 - arch/x86/lib/fsp/fsp_support.c | 1 - arch/x86/lib/fsp1/fsp_common.c | 1 - arch/x86/lib/fsp1/fsp_dram.c | 1 - arch/x86/lib/fsp1/fsp_support.c | 1 - arch/x86/lib/fsp2/fsp_common.c | 1 - arch/x86/lib/fsp2/fsp_dram.c | 1 - arch/x86/lib/fsp2/fsp_init.c | 1 - arch/x86/lib/fsp2/fsp_meminit.c | 1 - arch/x86/lib/fsp2/fsp_silicon_init.c | 1 - arch/x86/lib/fsp2/fsp_support.c | 1 - arch/x86/lib/hob.c | 1 - arch/x86/lib/i8254.c | 2 +- arch/x86/lib/i8259.c | 1 - arch/x86/lib/init_helpers.c | 2 +- arch/x86/lib/interrupts.c | 1 - arch/x86/lib/lpc-uclass.c | 1 - arch/x86/lib/mpspec.c | 1 - arch/x86/lib/mrccache.c | 1 - arch/x86/lib/northbridge-uclass.c | 1 - arch/x86/lib/physmem.c | 1 - arch/x86/lib/pinctrl_ich6.c | 1 - arch/x86/lib/pirq_routing.c | 1 - arch/x86/lib/pmu.c | 1 - arch/x86/lib/ramtest.c | 2 +- arch/x86/lib/reloc_ia32_efi.c | 1 - arch/x86/lib/reloc_x86_64_efi.c | 1 - arch/x86/lib/relocate.c | 1 - arch/x86/lib/scu.c | 1 - arch/x86/lib/sfi.c | 1 - arch/x86/lib/spl.c | 2 +- arch/x86/lib/tables.c | 1 - arch/x86/lib/tpl.c | 1 - arch/x86/lib/zimage.c | 1 - arch/xtensa/cpu/cpu.c | 2 +- arch/xtensa/cpu/exceptions.c | 2 +- arch/xtensa/include/asm/global_data.h | 2 + arch/xtensa/lib/bootm.c | 1 - arch/xtensa/lib/cache.c | 1 - arch/xtensa/lib/time.c | 1 - board/BuR/brppt1/board.c | 2 +- board/BuR/brppt1/mux.c | 1 - board/BuR/brppt2/board.c | 1 - board/BuR/brsmarc1/board.c | 1 - board/BuR/brsmarc1/mux.c | 1 - board/BuR/brxre1/board.c | 1 - board/BuR/brxre1/mux.c | 1 - board/BuR/common/br_resetc.c | 1 - board/BuR/common/common.c | 1 - board/BuS/eb_cpu5282/eb_cpu5282.c | 2 +- board/CZ.NIC/turris_mox/mox_sp.c | 2 +- board/CZ.NIC/turris_mox/turris_mox.c | 2 +- board/CZ.NIC/turris_omnia/turris_omnia.c | 2 +- board/LaCie/common/common.c | 1 - board/LaCie/net2big_v2/net2big_v2.c | 2 +- board/LaCie/netspace_v2/netspace_v2.c | 1 - board/Marvell/db-88f6720/db-88f6720.c | 1 - board/Marvell/db-88f6820-amc/db-88f6820-amc.c | 2 +- board/Marvell/db-88f6820-gp/db-88f6820-gp.c | 2 +- board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c | 1 - board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c | 1 - board/Marvell/dreamplug/dreamplug.c | 1 - board/Marvell/guruplug/guruplug.c | 1 - board/Marvell/mvebu_alleycat-5/board.c | 2 +- board/Marvell/mvebu_armada-37xx/board.c | 2 +- board/Marvell/mvebu_armada-8k/board.c | 2 +- board/Marvell/octeontx2/soc-utils.c | 1 - board/Marvell/openrd/openrd.c | 1 - board/Marvell/sheevaplug/sheevaplug.c | 1 - board/Seagate/dockstar/dockstar.c | 1 - board/Seagate/goflexhome/goflexhome.c | 1 - board/Seagate/nas220/nas220.c | 1 - board/Synology/ds109/ds109.c | 2 +- board/Synology/ds414/cmd_syno.c | 1 - board/Synology/ds414/ds414.c | 1 - .../imx8mp_rsb3720a1/imx8mp_rsb3720a1.c | 1 - board/advantech/imx8mp_rsb3720a1/spl.c | 2 +- .../imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c | 1 - board/advantech/imx8qm_dmsse20_a1/spl.c | 2 +- .../imx8qm_rom7720_a1/imx8qm_rom7720_a1.c | 1 - board/advantech/imx8qm_rom7720_a1/spl.c | 2 +- .../som-db5800-som-6867/som-db5800-som-6867.c | 1 - board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c | 1 - .../alliedtelesis/SBx81LIFXCAT/sbx81lifxcat.c | 1 - board/alliedtelesis/common/gpio_hog.c | 1 - board/alliedtelesis/x240/x240.c | 2 +- board/alliedtelesis/x530/x530.c | 2 +- board/amarula/vyasa-rk3288/vyasa-rk3288.c | 1 - board/amlogic/beelink-s922x/beelink-s922x.c | 1 - board/amlogic/jethub-j100/jethub-j100.c | 1 - board/amlogic/jethub-j80/jethub-j80.c | 1 - .../amlogic/odroid-go-ultra/odroid-go-ultra.c | 2 +- board/amlogic/odroid-n2/odroid-n2.c | 1 - board/amlogic/p200/p200.c | 1 - board/amlogic/p201/p201.c | 1 - board/amlogic/p212/p212.c | 1 - board/amlogic/q200/q200.c | 1 - board/amlogic/s400/s400.c | 1 - board/amlogic/sei510/sei510.c | 1 - board/amlogic/sei610/sei610.c | 1 - board/amlogic/u200/u200.c | 1 - board/amlogic/vim3/vim3.c | 1 - board/amlogic/w400/w400.c | 1 - board/aristainetos/aristainetos.c | 1 - board/armadeus/opos6uldev/board.c | 1 - board/armltd/corstone1000/corstone1000.c | 1 - board/armltd/integrator/integrator.c | 2 +- board/armltd/integrator/timer.c | 2 +- board/armltd/total_compute/total_compute.c | 2 +- board/armltd/vexpress/vexpress_common.c | 2 +- board/armltd/vexpress64/pcie.c | 1 - board/armltd/vexpress64/vexpress64.c | 2 +- board/astro/mcf5373l/fpga.c | 1 - board/astro/mcf5373l/mcf5373l.c | 3 +- board/atmel/at91sam9260ek/at91sam9260ek.c | 2 +- board/atmel/at91sam9261ek/at91sam9261ek.c | 2 +- board/atmel/at91sam9263ek/at91sam9263ek.c | 2 +- .../atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 2 +- board/atmel/at91sam9n12ek/at91sam9n12ek.c | 2 +- board/atmel/at91sam9rlek/at91sam9rlek.c | 2 +- board/atmel/at91sam9x5ek/at91sam9x5ek.c | 2 +- board/atmel/common/board.c | 1 - board/atmel/common/mac-spi-nor.c | 1 - board/atmel/common/mac_eeprom.c | 2 - board/atmel/common/video_display.c | 1 - .../sam9x60_curiosity/sam9x60_curiosity.c | 1 - board/atmel/sam9x60ek/sam9x60ek.c | 2 +- .../atmel/sama5d27_som1_ek/sama5d27_som1_ek.c | 1 - .../sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c | 2 +- .../sama5d29_curiosity/sama5d29_curiosity.c | 1 - board/atmel/sama5d2_icp/sama5d2_icp.c | 2 +- board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c | 2 +- .../atmel/sama5d2_xplained/sama5d2_xplained.c | 1 - .../atmel/sama5d3_xplained/sama5d3_xplained.c | 2 +- board/atmel/sama5d3xek/sama5d3xek.c | 2 +- .../atmel/sama5d4_xplained/sama5d4_xplained.c | 2 +- board/atmel/sama5d4ek/sama5d4ek.c | 2 +- .../sama7g54_curiosity/sama7g54_curiosity.c | 1 - board/atmel/sama7g5ek/sama7g5ek.c | 2 +- board/avionic-design/common/tamonten-ng.c | 1 - board/avionic-design/common/tamonten.c | 1 - board/avionic-design/tec-ng/tec-ng-spl.c | 1 - board/beacon/beacon-rzg2m/beacon-rzg2m.c | 1 - board/beacon/imx8mm/lpddr4_timing.c | 1 - board/beacon/imx8mm/spl.c | 1 - board/beacon/imx8mn/spl.c | 1 - board/beacon/imx8mp/imx8mp_beacon.c | 1 - board/beacon/imx8mp/spl.c | 1 - board/beagle/beagle/beagle.c | 2 +- board/beagle/beagle/led.c | 1 - board/beckhoff/mx53cx9020/mx53cx9020.c | 1 - board/beckhoff/mx53cx9020/mx53cx9020_video.c | 1 - board/bluewater/gurnard/gurnard.c | 2 +- board/bosch/acc/acc.c | 2 +- board/bosch/guardian/board.c | 2 +- board/bosch/guardian/mux.c | 1 - board/bosch/shc/board.c | 2 +- board/bosch/shc/mux.c | 1 - board/boundary/nitrogen6x/nitrogen6x.c | 1 - board/broadcom/bcmbca/board.c | 1 - board/broadcom/bcmns/ns.c | 1 - board/broadcom/bcmns3/ns3.c | 2 +- board/broadcom/bcmstb/bcmstb.c | 1 - board/bsh/imx6ulz_smm_m2/imx6ulz_smm_m2.c | 1 - board/bsh/imx6ulz_smm_m2/spl.c | 1 - board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c | 1 - board/bticino/mamoj/mamoj.c | 1 - board/bticino/mamoj/spl.c | 1 - board/buffalo/lsxl/lsxl.c | 1 - board/cadence/xtfpga/xtfpga.c | 2 +- board/calao/usb_a9263/usb_a9263.c | 2 +- board/cavium/thunderx/atf.c | 3 +- board/cavium/thunderx/thunderx.c | 2 +- board/cei/cei-tk1-som/cei-tk1-som.c | 2 +- .../popmetal_rk3288/popmetal-rk3288.c | 1 - board/cloos/imx8mm_phg/imx8mm_phg.c | 1 - board/cloos/imx8mm_phg/spl.c | 1 - board/cloudengines/pogo_e02/pogo_e02.c | 1 - board/cloudengines/pogo_v4/pogo_v4.c | 1 - board/cobra5272/cobra5272.c | 2 +- board/cobra5272/flash.c | 6 +- board/compulab/cl-som-imx7/cl-som-imx7.c | 2 +- board/compulab/cl-som-imx7/common.c | 1 - board/compulab/cl-som-imx7/mux.c | 2 +- board/compulab/cl-som-imx7/spl.c | 1 - board/compulab/cm_fx6/cm_fx6.c | 2 +- board/compulab/cm_fx6/common.c | 1 - board/compulab/cm_fx6/spl.c | 1 - board/compulab/cm_t43/cm_t43.c | 2 +- board/compulab/cm_t43/mux.c | 1 - board/compulab/cm_t43/spl.c | 2 +- board/compulab/common/common.c | 1 - board/compulab/common/eeprom.c | 4 +- board/compulab/common/omap3_smc911x.c | 1 - board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c | 1 - .../ddr/lpddr4_timing_01061010.1_2.c | 1 - .../ddr/lpddr4_timing_01061010.c | 1 - .../ddr/lpddr4_timing_ff000110.c | 1 - .../ddr/lpddr4_timing_ff020008.c | 1 - .../compulab/imx8mm-cl-iot-gate/eeprom_spl.c | 2 +- .../imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c | 1 - board/compulab/imx8mm-cl-iot-gate/spl.c | 1 - board/compulab/trimslice/trimslice.c | 1 - .../conclusive/kstr-sama5d27/kstr-sama5d27.c | 2 +- board/congatec/cgtqmx8/cgtqmx8.c | 2 +- board/congatec/cgtqmx8/spl.c | 1 - board/congatec/common/mmc.c | 3 +- .../conga-qeval20-qa3.c | 1 - board/coreboot/coreboot/coreboot.c | 1 - board/cortina/presidio-asic/presidio.c | 2 +- board/cssi/cmpcpro/cmpcpro.c | 1 - board/d-link/dns325/dns325.c | 1 - board/data_modul/common/common.c | 1 - .../imx8mm_data_modul_edm_sbc.c | 1 - board/data_modul/imx8mm_edm_sbc/spl.c | 1 - .../imx8mp_data_modul_edm_sbc.c | 1 - board/data_modul/imx8mp_edm_sbc/spl.c | 1 - board/davinci/da8xxevm/da850evm.c | 2 +- board/davinci/da8xxevm/omapl138_lcdk.c | 2 +- board/dfi/dfi-bt700/dfi-bt700.c | 1 - board/dhelectronics/common/dh_common.c | 1 - board/dhelectronics/common/dh_imx.c | 2 +- board/dhelectronics/dh_imx6/dh_imx6.c | 2 - board/dhelectronics/dh_imx6/dh_imx6_spl.c | 1 - board/dhelectronics/dh_imx8mp/common.c | 1 - .../dh_imx8mp/imx8mp_dhcom_pdk2.c | 1 - board/dhelectronics/dh_imx8mp/spl.c | 1 - board/dhelectronics/dh_stm32mp1/board.c | 1 - .../ea-lpc3250devkitv2/ea-lpc3250devkitv2.c | 2 +- board/ea/mx7ulp_com/mx7ulp_com.c | 1 - board/eets/pdu001/board.c | 2 +- board/eets/pdu001/mux.c | 2 +- board/efi/efi-x86_payload/payload.c | 1 - board/egnite/ethernut5/ethernut5.c | 2 +- board/egnite/ethernut5/ethernut5_pwrman.c | 2 +- board/elgin/elgin_rv1108/elgin_rv1108.c | 1 - board/embest/mx6boards/mx6boards.c | 1 - board/emulation/common/qemu_dfu.c | 1 - board/emulation/common/qemu_mtdparts.c | 1 - board/emulation/qemu-arm/qemu-arm.c | 2 +- board/emulation/qemu-ppce500/qemu-ppce500.c | 2 +- board/emulation/qemu-riscv/qemu-riscv.c | 1 - board/engicam/common/board.c | 1 - board/engicam/common/spl.c | 1 - board/engicam/imx6q/imx6q.c | 1 - board/engicam/imx6ul/imx6ul.c | 1 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board/freescale/common/mc34vr500.c | 1 - board/freescale/common/mmc.c | 2 +- board/freescale/common/ngpixis.c | 1 - board/freescale/common/ns_access.c | 2 +- board/freescale/common/p_corenet/law.c | 2 +- board/freescale/common/p_corenet/tlb.c | 3 +- board/freescale/common/pfuze.c | 1 - board/freescale/common/qixis.c | 2 +- board/freescale/common/sdhc_boot.c | 1 - board/freescale/common/sys_eeprom.c | 1 - board/freescale/common/vid.c | 3 +- board/freescale/imx8mm_evk/imx8mm_evk.c | 1 - board/freescale/imx8mm_evk/spl.c | 1 - board/freescale/imx8mn_evk/imx8mn_evk.c | 1 - board/freescale/imx8mn_evk/spl.c | 1 - board/freescale/imx8mp_evk/spl.c | 1 - board/freescale/imx8mq_evk/imx8mq_evk.c | 1 - board/freescale/imx8mq_evk/lpddr4_timing.c | 1 - board/freescale/imx8mq_evk/lpddr4_timing_b0.c | 1 - board/freescale/imx8mq_evk/spl.c | 2 +- board/freescale/imx8qm_mek/imx8qm_mek.c | 1 - board/freescale/imx8qm_mek/spl.c | 1 - board/freescale/imx8qxp_mek/imx8qxp_mek.c | 1 - board/freescale/imx8qxp_mek/spl.c | 1 - board/freescale/imx8ulp_evk/imx8ulp_evk.c | 1 - board/freescale/imx8ulp_evk/spl.c | 1 - board/freescale/imx93_evk/imx93_evk.c | 1 - board/freescale/imx93_evk/spl.c | 1 - board/freescale/imxrt1020-evk/imxrt1020-evk.c | 1 - board/freescale/imxrt1050-evk/imxrt1050-evk.c | 1 - board/freescale/imxrt1170-evk/imxrt1170-evk.c | 1 - board/freescale/ls1012afrdm/eth.c | 1 - board/freescale/ls1012afrdm/ls1012afrdm.c | 2 +- board/freescale/ls1012aqds/eth.c | 2 +- board/freescale/ls1012aqds/ls1012aqds.c | 2 +- board/freescale/ls1012ardb/eth.c | 2 +- board/freescale/ls1012ardb/ls1012ardb.c | 2 +- board/freescale/ls1021aiot/ls1021aiot.c | 2 +- board/freescale/ls1021aqds/ddr.c | 2 +- board/freescale/ls1028a/ddr.c | 1 - board/freescale/ls1028a/ls1028a.c | 2 +- board/freescale/ls1043aqds/ddr.c | 1 - board/freescale/ls1043aqds/eth.c | 2 +- board/freescale/ls1043aqds/ls1043aqds.c | 2 +- board/freescale/ls1043ardb/cpld.c | 2 +- board/freescale/ls1043ardb/ddr.c | 1 - board/freescale/ls1043ardb/eth.c | 2 +- board/freescale/ls1046afrwy/ddr.c | 1 - board/freescale/ls1046afrwy/eth.c | 2 +- board/freescale/ls1046afrwy/ls1046afrwy.c | 2 +- board/freescale/ls1046aqds/ddr.c | 1 - board/freescale/ls1046aqds/eth.c | 2 +- board/freescale/ls1046aqds/ls1046aqds.c | 2 +- board/freescale/ls1046ardb/cpld.c | 2 +- board/freescale/ls1046ardb/ddr.c | 1 - board/freescale/ls1046ardb/eth.c | 2 +- board/freescale/ls1046ardb/ls1046ardb.c | 2 +- board/freescale/ls1088a/ddr.c | 1 - board/freescale/ls1088a/ls1088a.c | 2 +- board/freescale/ls2080aqds/ddr.c | 1 - board/freescale/ls2080aqds/ls2080aqds.c | 2 +- board/freescale/ls2080ardb/ddr.c | 1 - board/freescale/ls2080ardb/ls2080ardb.c | 2 +- board/freescale/lx2160a/ddr.c | 1 - board/freescale/lx2160a/eth_lx2160ardb.c | 1 - board/freescale/lx2160a/lx2160a.c | 2 +- board/freescale/m5208evbe/m5208evbe.c | 1 - board/freescale/m5235evb/m5235evb.c | 1 - board/freescale/m5249evb/m5249evb.c | 2 +- board/freescale/m5253demo/flash.c | 3 +- board/freescale/m5253demo/m5253demo.c | 2 +- board/freescale/m5272c3/m5272c3.c | 2 +- board/freescale/m5275evb/m5275evb.c | 2 +- board/freescale/m5282evb/m5282evb.c | 2 +- board/freescale/m53017evb/m53017evb.c | 1 - board/freescale/m5329evb/m5329evb.c | 1 - board/freescale/m5329evb/nand.c | 1 - board/freescale/m5373evb/m5373evb.c | 1 - board/freescale/m5373evb/nand.c | 1 - board/freescale/mpc837xerdb/mpc837xerdb.c | 2 +- board/freescale/mpc8548cds/ddr.c | 1 - board/freescale/mpc8548cds/law.c | 2 +- board/freescale/mpc8548cds/mpc8548cds.c | 2 +- board/freescale/mpc8548cds/tlb.c | 3 +- board/freescale/mx23evk/mx23evk.c | 1 - board/freescale/mx23evk/spl_boot.c | 1 - board/freescale/mx28evk/iomux.c | 1 - board/freescale/mx28evk/mx28evk.c | 1 - board/freescale/mx51evk/mx51evk.c | 2 +- board/freescale/mx53loco/mx53loco.c | 2 +- board/freescale/mx6memcal/mx6memcal.c | 1 - board/freescale/mx6memcal/spl.c | 1 - board/freescale/mx6sabreauto/mx6sabreauto.c | 1 - board/freescale/mx6slevk/mx6slevk.c | 1 - board/freescale/mx6sllevk/mx6sllevk.c | 1 - .../freescale/mx6sxsabreauto/mx6sxsabreauto.c | 2 +- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 1 - .../mx6ul_14x14_evk/mx6ul_14x14_evk.c | 2 +- board/freescale/mx6ullevk/mx6ullevk.c | 2 +- board/freescale/mx7dsabresd/mx7dsabresd.c | 1 - board/freescale/mx7ulp_evk/mx7ulp_evk.c | 1 - board/freescale/p1010rdb/ddr.c | 1 - board/freescale/p1010rdb/law.c | 2 +- board/freescale/p1010rdb/p1010rdb.c | 2 +- board/freescale/p1010rdb/spl.c | 2 +- board/freescale/p1010rdb/spl_minimal.c | 2 +- board/freescale/p1010rdb/tlb.c | 3 +- board/freescale/p1_p2_rdb_pc/ddr.c | 5 +- board/freescale/p1_p2_rdb_pc/law.c | 2 +- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 +- board/freescale/p1_p2_rdb_pc/spl.c | 2 +- board/freescale/p1_p2_rdb_pc/spl_minimal.c | 2 +- board/freescale/p1_p2_rdb_pc/tlb.c | 3 +- board/freescale/p2041rdb/cpld.c | 1 - board/freescale/p2041rdb/ddr.c | 1 - board/freescale/p2041rdb/eth.c | 2 +- board/freescale/p2041rdb/p2041rdb.c | 2 +- board/freescale/t102xrdb/cpld.c | 2 +- board/freescale/t102xrdb/ddr.c | 2 +- board/freescale/t102xrdb/eth_t102xrdb.c | 2 +- board/freescale/t102xrdb/law.c | 2 +- board/freescale/t102xrdb/spl.c | 2 +- board/freescale/t102xrdb/t102xrdb.c | 2 +- board/freescale/t102xrdb/tlb.c | 3 +- board/freescale/t104xrdb/cpld.c | 2 +- board/freescale/t104xrdb/ddr.c | 2 +- board/freescale/t104xrdb/eth.c | 2 +- board/freescale/t104xrdb/law.c | 2 +- board/freescale/t104xrdb/spl.c | 2 +- board/freescale/t104xrdb/t104xrdb.c | 2 +- board/freescale/t104xrdb/tlb.c | 3 +- board/freescale/t208xqds/ddr.c | 1 - board/freescale/t208xqds/eth_t208xqds.c | 2 +- board/freescale/t208xqds/law.c | 2 +- board/freescale/t208xqds/spl.c | 2 +- board/freescale/t208xqds/t208xqds.c | 2 +- board/freescale/t208xqds/tlb.c | 3 +- board/freescale/t208xrdb/cpld.c | 3 +- board/freescale/t208xrdb/ddr.c | 1 - board/freescale/t208xrdb/eth_t208xrdb.c | 1 - board/freescale/t208xrdb/law.c | 2 +- board/freescale/t208xrdb/spl.c | 2 +- board/freescale/t208xrdb/t208xrdb.c | 2 +- board/freescale/t208xrdb/tlb.c | 3 +- board/freescale/t4rdb/cpld.c | 2 +- board/freescale/t4rdb/ddr.c | 1 - board/freescale/t4rdb/eth.c | 2 +- board/freescale/t4rdb/law.c | 2 +- board/freescale/t4rdb/spl.c | 2 +- board/freescale/t4rdb/t4240rdb.c | 2 +- board/freescale/t4rdb/tlb.c | 3 +- board/freescale/vf610twr/vf610twr.c | 1 - board/friendlyarm/nanopi2/board.c | 1 - board/friendlyarm/nanopi2/hwrev.c | 1 - board/friendlyarm/nanopi2/lcds.c | 1 - board/friendlyarm/nanopi2/onewire.c | 1 - board/gardena/smart-gateway-at91sam/board.c | 2 +- board/gardena/smart-gateway-at91sam/spl.c | 2 +- board/gardena/smart-gateway-mt7688/board.c | 1 - board/gateworks/gw_ventana/common.c | 1 - board/gateworks/gw_ventana/eeprom.c | 1 - board/gateworks/gw_ventana/gw_ventana.c | 1 - board/gateworks/gw_ventana/gw_ventana_spl.c | 2 +- board/gateworks/venice/eeprom.c | 1 - board/gateworks/venice/lpddr4_timing_imx8mm.c | 1 - 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board/k+p/kp_imx53/kp_imx53.c | 1 - board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c | 1 - board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c | 1 - board/keymile/common/common.c | 2 +- board/keymile/common/ivm.c | 3 +- board/keymile/common/qrio.c | 2 +- board/keymile/km83xx/km83xx.c | 2 +- board/keymile/kmcent2/tlb.c | 2 +- board/keymile/pg-wcom-ls102xa/ddr.c | 2 +- board/keymile/secu1/socfpga.c | 1 - board/kobol/helios4/helios4.c | 2 +- board/kontron/pitx_imx8m/pitx_imx8m.c | 1 - board/kontron/pitx_imx8m/spl.c | 2 +- board/kontron/sl-mx8mm/lpddr4_timing.c | 1 - board/kontron/sl28/cmds.c | 3 +- board/kontron/sl28/common.c | 2 +- board/kontron/sl28/ddr.c | 2 +- board/kontron/sl28/sl28.c | 1 - board/kontron/sl28/spl.c | 2 +- board/kontron/sl28/spl_atf.c | 2 +- board/kosagi/novena/novena.c | 1 - board/kosagi/novena/novena_spl.c | 2 +- board/kosagi/novena/video.c | 1 - board/l+g/vinco/vinco.c | 2 +- board/lego/ev3/legoev3.c | 2 +- board/lg/sniper/sniper.c | 1 - board/liebherr/display5/display5.c | 1 - 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board/olimex/mx23_olinuxino/mx23_olinuxino.c | 1 - board/olimex/mx23_olinuxino/spl_boot.c | 1 - board/openpiton/riscv64/openpiton-riscv64.c | 1 - board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c | 1 - board/phytec/common/Makefile | 2 + board/phytec/common/imx8m_som_detection.c | 1 - board/phytec/common/k3/Makefile | 2 + board/phytec/common/k3/board.c | 73 ++ board/phytec/common/phytec_som_detection.c | 1 - board/phytec/pcl063/spl.c | 2 +- board/phytec/pcm052/pcm052.c | 1 - board/phytec/pcm058/pcm058.c | 1 - board/phytec/phycore_am335x_r2/board.c | 2 +- board/phytec/phycore_am335x_r2/mux.c | 1 - board/phytec/phycore_am62x/phycore-am62x.c | 67 - board/phytec/phycore_imx8mm/phycore-imx8mm.c | 1 - board/phytec/phycore_imx8mm/spl.c | 1 - board/phytec/phycore_imx8mp/phycore-imx8mp.c | 1 - board/phytec/phycore_imx8mp/spl.c | 1 - board/phytec/phycore_rk3288/phycore-rk3288.c | 2 - board/phytium/durian/durian.c | 1 - board/phytium/pe2201/pe2201.c | 1 - board/phytium/pomelo/pomelo.c | 1 - .../imx8mp_debix_model_a.c | 1 - board/polyhex/imx8mp_debix_model_a/spl.c | 1 - board/purism/librem5/librem5.c | 1 - board/purism/librem5/lpddr4_timing.c | 1 - board/purism/librem5/lpddr4_timing_b0.c | 1 - board/purism/librem5/spl.c | 2 +- board/qca/ap121/ap121.c | 1 - board/qca/ap143/ap143.c | 1 - board/qca/ap152/ap152.c | 1 - .../dragonboard410c/dragonboard410c.c | 1 - .../dragonboard820c/dragonboard820c.c | 1 - board/raidsonic/ib62x0/ib62x0.c | 1 - board/raspberrypi/rpi/rpi.c | 1 - board/renesas/falcon/falcon.c | 1 - board/renesas/grpeach/grpeach.c | 1 - board/rockchip/evb_rk3036/evb_rk3036.c | 1 - board/rockchip/evb_rk3308/evb_rk3308.c | 1 - board/rockchip/evb_rv1108/evb_rv1108.c | 1 - board/rockchip/kylin_rk3036/kylin_rk3036.c | 1 - board/rockchip/tinker_rk3288/tinker-rk3288.c | 2 - board/ronetix/imx7-cm/imx7-cm.c | 1 - board/ronetix/imx7-cm/spl.c | 1 - board/ronetix/imx8mq-cm/imx8mq_cm.c | 1 - board/ronetix/imx8mq-cm/lpddr4_timing.c | 1 - board/ronetix/imx8mq-cm/spl.c | 2 +- board/ronetix/pm9261/pm9261.c | 2 +- board/ronetix/pm9263/pm9263.c | 2 +- board/ronetix/pm9g45/pm9g45.c | 2 +- board/samsung/arndale/arndale.c | 2 +- board/samsung/arndale/arndale_spl.c | 1 - board/samsung/common/board.c | 2 +- board/samsung/common/exynos5-dt-types.c | 2 +- board/samsung/common/exynos5-dt.c | 2 +- board/samsung/common/gadget.c | 2 +- board/samsung/common/misc.c | 2 +- board/samsung/common/sromc.c | 1 - board/samsung/goni/goni.c | 1 - board/samsung/goni/onenand.c | 2 +- board/samsung/odroid/odroid.c | 2 +- board/samsung/origen/origen.c | 1 - board/samsung/smdk5250/smdk5250_spl.c | 1 - board/samsung/smdk5420/smdk5420_spl.c | 1 - board/samsung/smdkc100/onenand.c | 1 - board/samsung/smdkc100/smdkc100.c | 2 +- board/samsung/smdkv310/smdkv310.c | 2 +- board/samsung/trats/trats.c | 1 - board/samsung/trats2/trats2.c | 1 - board/samsung/universal_c210/onenand.c | 2 +- board/samsung/universal_c210/universal.c | 1 - board/schneider/rzn1-snarc/rzn1.c | 1 - board/seeed/linkit-smart-7688/board.c | 1 - board/seeed/npi_imx6ull/spl.c | 2 +- board/siemens/capricorn/board.c | 1 - board/siemens/capricorn/spl.c | 1 - board/siemens/corvus/board.c | 2 +- board/siemens/iot2050/board.c | 2 +- board/siemens/smartweb/smartweb.c | 2 +- board/siemens/taurus/taurus.c | 2 +- board/silinux/ek874/ek874.c | 2 +- board/sipeed/maix/maix.c | 2 +- .../skyworth/hc2910-2aghd05/hc2910-2aghd05.c | 1 - board/socionext/developerbox/developerbox.c | 2 +- board/socrates/ddr.c | 1 - board/socrates/law.c | 2 +- board/socrates/nand.c | 2 +- board/socrates/sdram.c | 2 +- board/socrates/socrates.c | 2 +- board/socrates/tlb.c | 3 +- board/softing/vining_2000/vining_2000.c | 2 +- board/softing/vining_fpga/socfpga.c | 2 +- board/solidrun/clearfog/clearfog.c | 2 +- board/solidrun/common/tlv_data.c | 2 +- board/solidrun/mx6cuboxi/mx6cuboxi.c | 2 +- board/somlabs/visionsom-6ull/visionsom-6ull.c | 1 - board/sr1500/socfpga.c | 1 - board/st/common/cmd_stboard.c | 1 - board/st/common/stm32mp_dfu.c | 1 - board/st/common/stm32mp_dfu_virt.c | 1 - board/st/common/stpmic1.c | 1 - board/st/common/stusb160x.c | 1 - board/st/stih410-b2260/board.c | 1 - board/st/stm32f429-discovery/led.c | 1 - .../stm32f429-discovery/stm32f429-discovery.c | 1 - .../stm32f429-evaluation.c | 1 - .../stm32f469-discovery/stm32f469-discovery.c | 1 - board/st/stm32f746-disco/stm32f746-disco.c | 2 +- board/st/stm32h743-disco/stm32h743-disco.c | 1 - board/st/stm32h743-eval/stm32h743-eval.c | 1 - board/st/stm32h750-art-pi/stm32h750-art-pi.c | 1 - board/st/stm32mp1/spl.c | 1 - board/st/stm32mp1/stm32mp1.c | 1 - board/ste/stemmy/stemmy.c | 2 +- board/storopack/smegw01/smegw01.c | 1 - board/sunxi/board.c | 1 - board/sunxi/chip.c | 1 - board/sunxi/dram_sun4i_auto.c | 1 - board/sunxi/dram_sun5i_auto.c | 1 - board/sunxi/gmac.c | 1 - board/sysam/amcore/amcore.c | 2 +- board/sysam/stmark2/stmark2.c | 2 +- board/tcl/sl50/board.c | 2 +- board/tcl/sl50/mux.c | 1 - board/technexion/pico-imx6/pico-imx6.c | 1 - board/technexion/pico-imx6/spl.c | 1 - board/technexion/pico-imx6ul/pico-imx6ul.c | 1 - board/technexion/pico-imx6ul/spl.c | 1 - board/technexion/pico-imx7d/pico-imx7d.c | 1 - board/technexion/pico-imx7d/spl.c | 2 +- .../pico-imx8mq/lpddr4_timing_1gb.c | 1 - .../pico-imx8mq/lpddr4_timing_2gb.c | 1 - .../pico-imx8mq/lpddr4_timing_3gb.c | 1 - .../pico-imx8mq/lpddr4_timing_4gb.c | 1 - board/technexion/pico-imx8mq/pico-imx8mq.c | 1 - board/technexion/pico-imx8mq/spl.c | 1 - board/terasic/de1-soc/socfpga.c | 1 - board/thead/th1520_lpi4a/board.c | 1 - board/theadorable/fpga.c | 2 +- board/theadorable/theadorable.c | 1 - board/ti/am335x/board.c | 2 +- board/ti/am335x/board.h | 2 + board/ti/am335x/mux.c | 2 +- board/ti/am43xx/board.c | 3 +- board/ti/am43xx/board.h | 1 + board/ti/am43xx/mux.c | 1 - board/ti/am57xx/board.c | 2 +- board/ti/common/board_detect.c | 3 +- board/ti/common/cape_detect.c | 3 +- board/ti/dra7xx/evm.c | 2 +- board/ti/ks2_evm/board.c | 2 +- board/ti/ks2_evm/board_k2e.c | 1 - board/ti/ks2_evm/board_k2g.c | 3 +- board/ti/ks2_evm/board_k2hk.c | 1 - board/ti/ks2_evm/board_k2l.c | 1 - board/ti/ks2_evm/ddr3_cfg.c | 1 - board/ti/ks2_evm/ddr3_k2e.c | 1 - board/ti/ks2_evm/ddr3_k2g.c | 1 - board/ti/ks2_evm/ddr3_k2hk.c | 1 - board/ti/ks2_evm/ddr3_k2l.c | 1 - board/ti/omap3evm/evm.c | 2 +- board/ti/panda/panda.c | 1 - board/ti/sdp4430/cmd_bat.c | 1 - board/ti/sdp4430/sdp.c | 1 - board/timll/devkit3250/devkit3250.c | 2 +- board/timll/devkit3250/devkit3250_spl.c | 1 - board/timll/devkit8000/devkit8000.c | 2 +- board/toradex/apalis-imx8/apalis-imx8.c | 1 - board/toradex/apalis-tk1/apalis-tk1.c | 1 - board/toradex/apalis-tk1/as3722_init.c | 1 - board/toradex/apalis_imx6/apalis_imx6.c | 2 +- board/toradex/apalis_imx6/do_fuse.c | 1 - board/toradex/apalis_imx6/pf0100.c | 1 - board/toradex/apalis_t30/apalis_t30-spl.c | 1 - board/toradex/apalis_t30/apalis_t30.c | 1 - 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drivers/spi/nxp_fspi.c | 1 - drivers/spi/omap3_spi.c | 2 +- drivers/spi/pic32_spi.c | 1 - drivers/spi/pl022_spi.c | 1 - drivers/spi/renesas_rpc_spi.c | 1 - drivers/spi/rk_spi.c | 1 - drivers/spi/sandbox_spi.c | 1 - drivers/spi/sh_qspi.c | 1 - drivers/spi/soft_spi.c | 1 - drivers/spi/spi-aspeed-smc.c | 1 - drivers/spi/spi-emul-uclass.c | 1 - drivers/spi/spi-mem.c | 1 - drivers/spi/spi-mxic.c | 1 - drivers/spi/spi-qup.c | 1 - drivers/spi/spi-sifive.c | 1 - drivers/spi/spi-sn-f-ospi.c | 1 - drivers/spi/spi-sunxi.c | 1 - drivers/spi/spi-synquacer.c | 1 - drivers/spi/spi-uclass.c | 1 - drivers/spi/spi.c | 1 - drivers/spi/stm32_qspi.c | 1 - drivers/spi/stm32_spi.c | 1 - drivers/spi/tegra114_spi.c | 1 - drivers/spi/tegra20_sflash.c | 1 - drivers/spi/tegra20_slink.c | 1 - drivers/spi/tegra210_qspi.c | 1 - drivers/spi/ti_qspi.c | 1 - drivers/spi/uniphier_spi.c | 1 - drivers/spi/xilinx_spi.c | 1 - drivers/spi/zynq_qspi.c | 1 - drivers/spi/zynq_spi.c | 1 - drivers/spi/zynqmp_gqspi.c | 1 - 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drivers/sysreset/sysreset_syscon.c | 1 - drivers/sysreset/sysreset_watchdog.c | 1 - drivers/sysreset/sysreset_x86.c | 1 - drivers/sysreset/sysreset_xtfpga.c | 2 +- drivers/thermal/imx_scu_thermal.c | 1 - drivers/thermal/imx_thermal.c | 1 - drivers/thermal/imx_tmu.c | 1 - drivers/thermal/thermal-uclass.c | 1 - drivers/thermal/thermal_sandbox.c | 1 - drivers/timer/Kconfig | 8 + drivers/timer/Makefile | 1 + drivers/timer/adi_sc5xx_timer.c | 145 ++ drivers/timer/altera_timer.c | 1 - drivers/timer/andes_plmt_timer.c | 1 - drivers/timer/arc_timer.c | 1 - drivers/timer/arm_global_timer.c | 2 +- drivers/timer/arm_twd_timer.c | 1 - drivers/timer/ast_timer.c | 1 - drivers/timer/atmel_pit_timer.c | 1 - drivers/timer/atmel_tcb_timer.c | 1 - drivers/timer/cadence-ttc.c | 1 - drivers/timer/dw-apb-timer.c | 1 - drivers/timer/fttmr010_timer.c | 1 - drivers/timer/imx-gpt-timer.c | 2 +- drivers/timer/mchp-pit64b-timer.c | 1 - drivers/timer/mpc83xx_timer.c | 2 +- drivers/timer/mtk_timer.c | 1 - drivers/timer/nomadik-mtu-timer.c | 1 - drivers/timer/npcm-timer.c | 1 - drivers/timer/omap-timer.c | 1 - drivers/timer/orion-timer.c | 2 +- drivers/timer/ostm_timer.c | 1 - drivers/timer/riscv_aclint_timer.c | 2 +- drivers/timer/riscv_timer.c | 2 +- drivers/timer/rockchip_timer.c | 1 - drivers/timer/sandbox_timer.c | 1 - drivers/timer/sp804_timer.c | 1 - drivers/timer/starfive-timer.c | 1 - drivers/timer/stm32_timer.c | 2 +- drivers/timer/tegra-timer.c | 1 - drivers/timer/timer-uclass.c | 1 - drivers/timer/tsc_timer.c | 1 - drivers/timer/xilinx-timer.c | 1 - drivers/tpm/cr50_i2c.c | 2 +- drivers/tpm/sandbox_common.c | 1 - drivers/tpm/tpm-uclass.c | 2 +- drivers/tpm/tpm2_ftpm_tee.c | 1 - drivers/tpm/tpm2_tis_core.c | 2 +- drivers/tpm/tpm2_tis_i2c.c | 1 - drivers/tpm/tpm2_tis_mmio.c | 1 - drivers/tpm/tpm2_tis_sandbox.c | 1 - drivers/tpm/tpm2_tis_spi.c | 2 +- drivers/tpm/tpm_atmel_twi.c | 2 +- drivers/tpm/tpm_tis_infineon.c | 2 +- drivers/tpm/tpm_tis_lpc.c | 1 - drivers/tpm/tpm_tis_sandbox.c | 1 - drivers/tpm/tpm_tis_st33zp24_i2c.c | 1 - drivers/tpm/tpm_tis_st33zp24_spi.c | 1 - drivers/ufs/cdns-platform.c | 1 - drivers/ufs/ti-j721e-ufs.c | 1 - drivers/ufs/ufs-pci.c | 1 - drivers/ufs/ufs-uclass.c | 1 - drivers/ufs/ufs.c | 1 - drivers/ufs/ufs.h | 1 + drivers/usb/cdns3/cdns3-ti.c | 1 - drivers/usb/cdns3/core.c | 1 - drivers/usb/common/common.c | 1 - drivers/usb/common/fsl-dt-fixup.c | 1 - drivers/usb/common/fsl-errata.c | 1 - drivers/usb/dwc3/core.c | 1 - drivers/usb/dwc3/dwc3-generic.c | 1 - drivers/usb/dwc3/dwc3-layerscape.c | 1 - drivers/usb/dwc3/dwc3-meson-g12a.c | 1 - drivers/usb/dwc3/dwc3-meson-gxl.c | 1 - drivers/usb/dwc3/dwc3-omap.c | 1 - drivers/usb/dwc3/ep0.c | 1 - drivers/usb/dwc3/gadget.c | 1 - drivers/usb/dwc3/samsung_usb_phy.c | 2 +- drivers/usb/dwc3/ti_usb_phy.c | 1 - drivers/usb/emul/sandbox_flash.c | 1 - drivers/usb/emul/sandbox_hub.c | 1 - drivers/usb/emul/sandbox_keyb.c | 1 - drivers/usb/emul/usb-emul-uclass.c | 1 - drivers/usb/eth/asix.c | 1 - drivers/usb/eth/asix88179.c | 1 - drivers/usb/eth/mcs7830.c | 1 - drivers/usb/eth/r8152.c | 1 - drivers/usb/eth/r8152_fw.c | 1 - drivers/usb/eth/smsc95xx.c | 1 - drivers/usb/eth/usb_ether.c | 1 - drivers/usb/gadget/at91_udc.c | 1 - drivers/usb/gadget/atmel_usba_udc.c | 1 - drivers/usb/gadget/bcm_udc_otg_phy.c | 1 - drivers/usb/gadget/ci_udc.c | 1 - drivers/usb/gadget/config.c | 1 - drivers/usb/gadget/dwc2_udc_otg.c | 1 - drivers/usb/gadget/dwc2_udc_otg_phy.c | 1 - drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c | 1 - drivers/usb/gadget/ep0.c | 1 - drivers/usb/gadget/epautoconf.c | 1 - drivers/usb/gadget/ether.c | 1 - drivers/usb/gadget/f_acm.c | 1 - drivers/usb/gadget/f_dfu.c | 1 - drivers/usb/gadget/f_fastboot.c | 1 - drivers/usb/gadget/f_mass_storage.c | 1 - drivers/usb/gadget/f_rockusb.c | 1 - drivers/usb/gadget/f_sdp.c | 1 - drivers/usb/gadget/f_thor.c | 1 - drivers/usb/gadget/g_dnl.c | 1 - drivers/usb/gadget/max3420_udc.c | 1 - drivers/usb/gadget/rndis.c | 1 - drivers/usb/gadget/udc/udc-core.c | 1 - drivers/usb/gadget/udc/udc-uclass.c | 1 - drivers/usb/gadget/usbstring.c | 1 - drivers/usb/host/dwc2.c | 1 - drivers/usb/host/dwc3-of-simple.c | 1 - drivers/usb/host/dwc3-sti-glue.c | 1 - drivers/usb/host/ehci-atmel.c | 1 - drivers/usb/host/ehci-exynos.c | 1 - drivers/usb/host/ehci-fsl.c | 1 - drivers/usb/host/ehci-generic.c | 1 - drivers/usb/host/ehci-hcd.c | 1 - drivers/usb/host/ehci-marvell.c | 1 - drivers/usb/host/ehci-msm.c | 1 - drivers/usb/host/ehci-mx5.c | 1 - drivers/usb/host/ehci-mx6.c | 1 - drivers/usb/host/ehci-mxs.c | 1 - drivers/usb/host/ehci-npcm.c | 1 - drivers/usb/host/ehci-omap.c | 2 +- drivers/usb/host/ehci-pci.c | 1 - drivers/usb/host/ehci-tegra.c | 1 - drivers/usb/host/ehci-vf.c | 1 - drivers/usb/host/ehci-zynq.c | 1 - drivers/usb/host/ohci-at91.c | 1 - drivers/usb/host/ohci-da8xx.c | 1 - drivers/usb/host/ohci-generic.c | 1 - drivers/usb/host/ohci-hcd.c | 2 +- drivers/usb/host/ohci-lpc32xx.c | 1 - drivers/usb/host/ohci-npcm.c | 1 - drivers/usb/host/ohci-pci.c | 1 - drivers/usb/host/r8a66597-hcd.c | 1 - drivers/usb/host/usb-sandbox.c | 1 - drivers/usb/host/usb-uclass.c | 1 - drivers/usb/host/usb_bootdev.c | 1 - drivers/usb/host/xhci-brcm.c | 1 - drivers/usb/host/xhci-dwc3.c | 1 - drivers/usb/host/xhci-exynos5.c | 1 - drivers/usb/host/xhci-fsl.c | 1 - drivers/usb/host/xhci-mem.c | 1 - drivers/usb/host/xhci-mtk.c | 1 - drivers/usb/host/xhci-mvebu.c | 1 - drivers/usb/host/xhci-omap.c | 1 - drivers/usb/host/xhci-pci.c | 1 - drivers/usb/host/xhci-rcar.c | 1 - drivers/usb/host/xhci-ring.c | 1 - drivers/usb/host/xhci.c | 1 - drivers/usb/isp1760/isp1760-hcd.c | 1 - drivers/usb/isp1760/isp1760-if.c | 1 - drivers/usb/isp1760/isp1760-uboot.c | 1 - drivers/usb/mtu3/mtu3_plat.c | 1 - drivers/usb/musb-new/am35x.c | 1 - drivers/usb/musb-new/da8xx.c | 1 - drivers/usb/musb-new/mt85xx.c | 1 - drivers/usb/musb-new/musb_core.c | 1 - drivers/usb/musb-new/musb_dsps.c | 1 - drivers/usb/musb-new/musb_gadget.c | 1 - drivers/usb/musb-new/musb_gadget_ep0.c | 1 - drivers/usb/musb-new/musb_host.c | 1 - drivers/usb/musb-new/musb_uboot.c | 1 - drivers/usb/musb-new/omap2430.c | 1 - drivers/usb/musb-new/pic32.c | 1 - drivers/usb/musb-new/sunxi.c | 1 - drivers/usb/musb-new/ti-musb.c | 1 - drivers/usb/musb-new/ux500.c | 1 - drivers/usb/musb/am35x.c | 1 - drivers/usb/musb/musb_core.c | 1 - drivers/usb/musb/musb_hcd.c | 1 - drivers/usb/musb/musb_udc.c | 1 - drivers/usb/phy/rockchip_usb2_phy.c | 1 - drivers/usb/ulpi/omap-ulpi-viewport.c | 1 - drivers/usb/ulpi/ulpi-viewport.c | 1 - drivers/usb/ulpi/ulpi.c | 1 - drivers/video/anx9804.c | 1 - drivers/video/atmel_hlcdfb.c | 1 - drivers/video/atmel_lcdfb.c | 1 - drivers/video/backlight-uclass.c | 1 - drivers/video/backlight_gpio.c | 1 - drivers/video/bcm2835.c | 1 - drivers/video/bmp.c | 1 - drivers/video/bochs.c | 1 - drivers/video/bridge/anx6345.c | 1 - drivers/video/bridge/ps862x.c | 1 - drivers/video/bridge/ptn3460.c | 1 - drivers/video/bridge/ssd2825.c | 1 - drivers/video/bridge/video-bridge-uclass.c | 1 - drivers/video/broadwell_igd.c | 2 +- drivers/video/console_normal.c | 1 - drivers/video/console_rotate.c | 1 - drivers/video/console_truetype.c | 1 - drivers/video/coreboot.c | 1 - drivers/video/display-uclass.c | 1 - drivers/video/dsi-host-uclass.c | 1 - drivers/video/dw_hdmi.c | 3 +- drivers/video/dw_mipi_dsi.c | 1 - drivers/video/efi.c | 1 - drivers/video/endeavoru-panel.c | 1 - drivers/video/exynos/exynos_dp.c | 1 - drivers/video/exynos/exynos_dp_lowlevel.c | 1 - drivers/video/exynos/exynos_fb.c | 1 - drivers/video/exynos/exynos_mipi_dsi.c | 1 - drivers/video/exynos/exynos_mipi_dsi_common.c | 1 - .../video/exynos/exynos_mipi_dsi_lowlevel.c | 1 - drivers/video/himax-hx8394.c | 1 - drivers/video/hitachi_tx18d42vm_lcd.c | 1 - drivers/video/hx8238d.c | 1 - drivers/video/ihs_video_out.c | 1 - drivers/video/imx/ipu_common.c | 2 +- drivers/video/imx/ipu_disp.c | 1 - drivers/video/imx/mxc_ipuv3_fb.c | 1 - drivers/video/ivybridge_igd.c | 1 - drivers/video/lm3533_backlight.c | 1 - drivers/video/logicore_dp_tx.c | 1 - drivers/video/mali_dp.c | 1 - drivers/video/mcde_simple.c | 1 - drivers/video/meson/meson_canvas.c | 1 - drivers/video/meson/meson_dw_hdmi.c | 1 - drivers/video/meson/meson_plane.c | 1 - drivers/video/meson/meson_vclk.c | 1 - drivers/video/meson/meson_venc.c | 1 - drivers/video/meson/meson_vpu.c | 1 - drivers/video/meson/meson_vpu_init.c | 1 - drivers/video/mipi_dsi.c | 1 - drivers/video/mvebu_lcd.c | 1 - drivers/video/mxsfb.c | 1 - drivers/video/nexell/s5pxx18_dp.c | 1 - drivers/video/nexell/s5pxx18_dp_hdmi.c | 1 - drivers/video/nexell/s5pxx18_dp_lvds.c | 2 +- drivers/video/nexell/s5pxx18_dp_mipi.c | 1 - drivers/video/nexell/s5pxx18_dp_rgb.c | 2 +- .../video/nexell/soc/s5pxx18_soc_disptop.h | 1 + drivers/video/nexell_display.c | 1 - drivers/video/omap3_dss.c | 1 - drivers/video/orisetech_otm8009a.c | 1 - drivers/video/panel-uclass.c | 1 - drivers/video/pwm_backlight.c | 1 - drivers/video/raydium-rm68200.c | 1 - drivers/video/renesas-r61307.c | 1 - drivers/video/renesas-r69328.c | 1 - drivers/video/rockchip/dw_mipi_dsi_rockchip.c | 1 - drivers/video/rockchip/rk3288_hdmi.c | 1 - drivers/video/rockchip/rk3288_mipi.c | 1 - drivers/video/rockchip/rk3288_vop.c | 1 - drivers/video/rockchip/rk3399_hdmi.c | 1 - drivers/video/rockchip/rk3399_mipi.c | 1 - drivers/video/rockchip/rk3399_vop.c | 1 - drivers/video/rockchip/rk_edp.c | 1 - drivers/video/rockchip/rk_hdmi.c | 1 - drivers/video/rockchip/rk_lvds.c | 1 - drivers/video/rockchip/rk_mipi.c | 1 - drivers/video/rockchip/rk_vop.c | 1 - drivers/video/sandbox_dsi_host.c | 1 - drivers/video/sandbox_osd.c | 1 - drivers/video/sandbox_sdl.c | 1 - drivers/video/seps525.c | 1 - drivers/video/simple_panel.c | 1 - drivers/video/simplefb.c | 1 - drivers/video/ssd2828.c | 1 - drivers/video/stm32/stm32_dsi.c | 1 - drivers/video/stm32/stm32_ltdc.c | 1 - drivers/video/sunxi/lcdc.c | 1 - drivers/video/sunxi/sunxi_de2.c | 1 - drivers/video/sunxi/sunxi_display.c | 2 +- drivers/video/sunxi/sunxi_dw_hdmi.c | 1 - drivers/video/sunxi/sunxi_lcd.c | 1 - drivers/video/sunxi/tve_common.c | 1 - drivers/video/tda19988.c | 1 - drivers/video/tdo-tl070wsh30.c | 1 - drivers/video/tegra124/display.c | 2 +- drivers/video/tegra124/dp.c | 2 +- drivers/video/tegra124/sor.c | 1 - drivers/video/tegra20/mipi-phy.c | 1 - drivers/video/tegra20/tegra-dsi.c | 1 - drivers/video/tegra20/tegra-pwm-backlight.c | 1 - drivers/video/ti/tilcdc-panel.c | 1 - drivers/video/ti/tilcdc.c | 1 - drivers/video/tidss/tidss_drv.c | 1 - drivers/video/vesa.c | 1 - drivers/video/vidconsole-uclass.c | 1 - drivers/video/video-uclass.c | 1 - drivers/video/video_bmp.c | 1 - drivers/video/video_osd-uclass.c | 1 - drivers/video/videomodes.c | 1 - drivers/video/zynqmp/zynqmp_dpsub.c | 1 - drivers/virtio/virtio-uclass.c | 1 - drivers/virtio/virtio_blk.c | 1 - drivers/virtio/virtio_mmio.c | 1 - drivers/virtio/virtio_net.c | 1 - drivers/virtio/virtio_pci_legacy.c | 1 - drivers/virtio/virtio_pci_modern.c | 1 - drivers/virtio/virtio_ring.c | 1 - drivers/virtio/virtio_rng.c | 1 - drivers/virtio/virtio_sandbox.c | 1 - drivers/w1-eeprom/ds24xxx.c | 1 - drivers/w1-eeprom/ds2502.c | 1 - drivers/w1-eeprom/eep_sandbox.c | 1 - drivers/w1-eeprom/w1-eeprom-uclass.c | 1 - drivers/w1/mxc_w1.c | 1 - drivers/w1/w1-gpio.c | 1 - drivers/w1/w1-uclass.c | 1 - drivers/watchdog/armada-37xx-wdt.c | 1 - drivers/watchdog/ast2600_wdt.c | 1 - drivers/watchdog/ast_wdt.c | 1 - drivers/watchdog/at91sam9_wdt.c | 1 - drivers/watchdog/bcm6345_wdt.c | 1 - drivers/watchdog/cdns_wdt.c | 1 - drivers/watchdog/cortina_wdt.c | 1 - drivers/watchdog/designware_wdt.c | 1 - drivers/watchdog/ftwdt010_wdt.c | 1 - drivers/watchdog/imx_watchdog.c | 1 - drivers/watchdog/mcf_wdt.c | 2 +- drivers/watchdog/mpc8xxx_wdt.c | 1 - drivers/watchdog/mt7621_wdt.c | 1 - drivers/watchdog/mtk_wdt.c | 1 - drivers/watchdog/omap_wdt.c | 1 - drivers/watchdog/orion_wdt.c | 1 - drivers/watchdog/rti_wdt.c | 1 - drivers/watchdog/s5p_wdt.c | 1 - drivers/watchdog/sandbox_alarm-wdt.c | 1 - drivers/watchdog/sandbox_wdt.c | 1 - drivers/watchdog/sbsa_gwdt.c | 1 - drivers/watchdog/sl28cpld-wdt.c | 1 - drivers/watchdog/sp805_wdt.c | 1 - drivers/watchdog/stm32mp_wdt.c | 1 - drivers/watchdog/tangier_wdt.c | 1 - drivers/watchdog/ulp_wdog.c | 1 - drivers/watchdog/wdt-uclass.c | 1 - drivers/watchdog/xilinx_tb_wdt.c | 1 - drivers/watchdog/xilinx_wwdt.c | 1 - drivers/xen/events.c | 1 - drivers/xen/gnttab.c | 1 - drivers/xen/hypervisor.c | 1 - drivers/xen/pvblock.c | 1 - drivers/xen/xenbus.c | 1 - env/Kconfig | 2 +- env/attr.c | 4 +- env/callback.c | 1 - env/common.c | 1 - env/eeprom.c | 1 - env/env.c | 2 +- env/ext4.c | 1 - env/fat.c | 1 - env/flags.c | 4 +- env/flash.c | 1 - env/mmc.c | 1 - env/nand.c | 1 - env/nowhere.c | 1 - env/nvram.c | 1 - env/onenand.c | 1 - env/remote.c | 2 +- env/sf.c | 1 - env/ubi.c | 1 - examples/api/demo.c | 2 +- examples/api/glue.c | 1 - examples/api/libgenwrap.c | 1 - examples/standalone/atmel_df_pow2.c | 1 - examples/standalone/sched.c | 1 - examples/standalone/stubs.c | 1 - fs/btrfs/dev.c | 1 - fs/btrfs/disk-io.c | 1 - fs/btrfs/volumes.c | 2 +- fs/cbfs/cbfs.c | 2 +- fs/cramfs/cramfs.c | 2 +- fs/cramfs/uncompress.c | 2 +- fs/ext4/dev.c | 1 - fs/ext4/ext4_common.c | 1 - fs/ext4/ext4_journal.c | 1 - fs/ext4/ext4_write.c | 1 - fs/ext4/ext4fs.c | 1 - fs/fat/fat.c | 1 - fs/fat/fat_write.c | 1 - fs/fs.c | 2 +- fs/fs_internal.c | 1 - fs/jffs2/compr_zlib.c | 2 - fs/jffs2/jffs2_1pass.c | 1 - fs/jffs2/mergesort.c | 1 - fs/sandbox/host_bootdev.c | 1 - fs/sandbox/sandboxfs.c | 2 +- fs/semihostingfs.c | 2 +- fs/ubifs/super.c | 1 - fs/ubifs/ubifs.c | 1 - fs/yaffs2/yaffs_mtdif.c | 1 - fs/yaffs2/yaffs_mtdif2.c | 1 - fs/yaffs2/yaffs_uboot_glue.c | 1 - fs/zfs/dev.c | 1 - fs/zfs/zfs.c | 1 - fs/zfs/zfs_fletcher.c | 1 - fs/zfs/zfs_lzjb.c | 1 - fs/zfs/zfs_sha256.c | 1 - include/acpi/acpi_s3.h | 3 + include/adc.h | 2 + include/android_ab.h | 2 + include/api_public.h | 2 + include/atf_common.h | 2 + include/audio_codec.h | 2 + include/autoboot.h | 1 + include/axi.h | 2 + include/bmp_layout.h | 2 + include/bootmeth.h | 2 + include/bootstd.h | 2 + include/cedit.h | 3 + include/common.h | 33 - include/configs/mt7621.h | 3 - include/configs/mt7623.h | 3 - include/configs/octeontx2_common.h | 5 - include/ddr_spd.h | 2 + include/display.h | 2 + include/dm/of.h | 1 - include/dm/test.h | 2 + include/dt-bindings/clock/adi-sc5xx-clock.h | 271 ++++ include/eeprom.h | 2 + include/env/adi/adi_boot.env | 122 ++ include/env_callback.h | 1 + include/env_default.h | 1 + include/env_flags.h | 2 + include/extension_board.h | 2 + include/flash.h | 2 + include/fsl_errata.h | 2 +- include/fsl_ifc.h | 2 + include/fsl_immap.h | 3 + include/fuse.h | 2 + include/gzip.h | 2 + include/handoff.h | 1 + include/i2c_eeprom.h | 1 + include/init.h | 2 + include/jffs2/load_kernel.h | 1 + include/libata.h | 1 + include/linux/compat.h | 1 + include/linux/mtd/omap_gpmc.h | 2 + include/mailbox.h | 2 + include/mmc.h | 9 +- include/mpc85xx.h | 1 + include/nand.h | 2 - include/netdev.h | 3 + include/pci.h | 1 + include/phy_interface.h | 1 + include/ram.h | 2 + include/s_record.h | 2 + include/sm.h | 2 +- include/splash.h | 1 + include/u-boot/sha1.h | 2 + include/u-boot/sha256.h | 2 + include/u-boot/sha512.h | 2 + include/virtio.h | 1 + include/xen/events.h | 1 + net/arp.c | 2 +- net/bootp.c | 1 - net/cdp.c | 1 - net/dhcpv6.c | 1 - net/dns.c | 1 - net/eth-uclass.c | 1 - net/eth_bootdev.c | 1 - net/eth_common.c | 1 - net/fastboot_tcp.c | 1 - net/fastboot_udp.c | 1 - net/link_local.c | 1 - net/mdio-mux-uclass.c | 1 - net/mdio-uclass.c | 1 - net/ndisc.c | 1 - net/net.c | 1 - net/net6.c | 2 +- net/nfs.c | 1 - net/pcap.c | 2 +- net/ping6.c | 1 - net/rarp.c | 1 - net/sntp.c | 1 - net/tcp.c | 1 - net/tftp.c | 1 - net/udp.c | 1 - net/wget.c | 1 - net/wol.c | 1 - post/cpu/mpc83xx/ecc.c | 2 +- post/drivers/flash.c | 2 +- post/drivers/i2c.c | 2 +- post/drivers/memory.c | 2 +- post/drivers/rtc.c | 2 +- post/lib_powerpc/andi.c | 2 +- post/lib_powerpc/b.c | 2 +- post/lib_powerpc/cmp.c | 2 +- post/lib_powerpc/cmpi.c | 2 +- post/lib_powerpc/complex.c | 2 +- post/lib_powerpc/cpu.c | 2 +- post/lib_powerpc/cr.c | 2 +- post/lib_powerpc/fpu/20001122-1.c | 2 +- post/lib_powerpc/fpu/20010114-2.c | 2 +- post/lib_powerpc/fpu/20010226-1.c | 2 +- post/lib_powerpc/fpu/980619-1.c | 2 +- post/lib_powerpc/fpu/acc1.c | 2 +- post/lib_powerpc/fpu/compare-fp-1.c | 2 +- post/lib_powerpc/fpu/fpu.c | 2 +- post/lib_powerpc/fpu/mul-subnormal-single-1.c | 2 +- post/lib_powerpc/load.c | 2 +- post/lib_powerpc/multi.c | 2 +- post/lib_powerpc/rlwimi.c | 2 +- post/lib_powerpc/rlwinm.c | 2 +- post/lib_powerpc/rlwnm.c | 2 +- post/lib_powerpc/srawi.c | 2 +- post/lib_powerpc/store.c | 2 +- post/lib_powerpc/string.c | 2 +- post/lib_powerpc/three.c | 2 +- post/lib_powerpc/threei.c | 2 +- post/lib_powerpc/threex.c | 2 +- post/lib_powerpc/two.c | 2 +- post/lib_powerpc/twox.c | 2 +- post/post.c | 2 +- post/tests.c | 3 +- scripts/Makefile.autoconf | 4 +- scripts/gen_ll_addressable_symbols.sh | 2 +- test/bloblist.c | 1 - test/boot/bootdev.c | 1 - test/boot/bootflow.c | 1 - test/boot/bootmeth.c | 1 - test/boot/bootstd_common.c | 1 - test/boot/cedit.c | 1 - test/boot/expo.c | 1 - test/boot/image.c | 1 - test/boot/measurement.c | 1 - test/boot/vbe_fixup.c | 1 - test/boot/vbe_simple.c | 1 - test/bootm.c | 1 - test/cmd/addrmap.c | 1 - test/cmd/armffa.c | 1 - test/cmd/bdinfo.c | 1 - test/cmd/exit.c | 1 - test/cmd/fdt.c | 1 - test/cmd/font.c | 1 - test/cmd/history.c | 1 - test/cmd/loadm.c | 1 - test/cmd/mem.c | 1 - test/cmd/mem_search.c | 1 - test/cmd/pci_mps.c | 1 - test/cmd/pinmux.c | 1 - test/cmd/rw.c | 1 - test/cmd/seama.c | 1 - test/cmd/setexpr.c | 1 - test/cmd/temperature.c | 1 - test/cmd/test_echo.c | 1 - test/cmd/test_pause.c | 1 - test/cmd/wget.c | 1 - test/cmd_ut.c | 2 +- test/command_ut.c | 1 - test/common/cmd_ut_common.c | 1 - test/common/cread.c | 2 +- test/common/cyclic.c | 1 - test/common/event.c | 1 - test/common/test_autoboot.c | 1 - test/compression.c | 1 - test/dm/acpi.c | 1 - test/dm/acpi_dp.c | 1 - test/dm/acpigen.c | 1 - test/dm/adc.c | 1 - test/dm/audio.c | 1 - test/dm/axi.c | 1 - test/dm/blk.c | 1 - test/dm/blkmap.c | 1 - test/dm/bootcount.c | 1 - test/dm/bus.c | 1 - test/dm/button.c | 1 - test/dm/cache.c | 1 - test/dm/clk.c | 1 - test/dm/clk_ccf.c | 1 - test/dm/core.c | 1 - test/dm/cpu.c | 1 - test/dm/cros_ec.c | 1 - test/dm/cros_ec_pwm.c | 1 - test/dm/devres.c | 1 - test/dm/dma.c | 1 - test/dm/dsi_host.c | 1 - test/dm/efi_media.c | 1 - test/dm/eth.c | 1 - test/dm/fastboot.c | 1 - test/dm/fdtdec.c | 1 - test/dm/ffa.c | 1 - test/dm/firmware.c | 1 - test/dm/fwu_mdata.c | 1 - test/dm/gpio.c | 1 - test/dm/host.c | 1 - test/dm/hwspinlock.c | 1 - test/dm/i2c.c | 1 - test/dm/i2s.c | 1 - test/dm/iommu.c | 1 - test/dm/irq.c | 1 - test/dm/k210_pll.c | 1 - test/dm/led.c | 1 - test/dm/mailbox.c | 1 - test/dm/mdio.c | 1 - test/dm/mdio_mux.c | 1 - test/dm/misc.c | 1 - test/dm/mmc.c | 1 - test/dm/mux-cmd.c | 2 +- test/dm/mux-emul.c | 1 - test/dm/mux-mmio.c | 1 - test/dm/nop.c | 1 - test/dm/nvmxip.c | 1 - test/dm/of_extra.c | 1 - test/dm/of_platdata.c | 1 - test/dm/ofnode.c | 1 - test/dm/ofread.c | 1 - test/dm/osd.c | 1 - test/dm/p2sb.c | 1 - test/dm/panel.c | 1 - test/dm/part.c | 1 - test/dm/pch.c | 1 - test/dm/pci.c | 1 - test/dm/pci_ep.c | 1 - test/dm/phy.c | 1 - test/dm/phys2bus.c | 1 - test/dm/pinmux.c | 1 - test/dm/pmc.c | 1 - test/dm/pmic.c | 1 - test/dm/power-domain.c | 1 - test/dm/pwm.c | 1 - test/dm/qfw.c | 1 - test/dm/ram.c | 1 - test/dm/read.c | 1 - test/dm/reboot-mode.c | 1 - test/dm/regmap.c | 2 +- test/dm/regulator.c | 1 - test/dm/remoteproc.c | 3 +- test/dm/reset.c | 1 - test/dm/rkmtd.c | 1 - test/dm/rng.c | 1 - test/dm/rtc.c | 1 - test/dm/scmi.c | 1 - test/dm/scsi.c | 1 - test/dm/serial.c | 1 - test/dm/sf.c | 1 - test/dm/simple-bus.c | 1 - test/dm/simple-pm-bus.c | 1 - test/dm/sm.c | 1 - test/dm/smem.c | 1 - test/dm/soc.c | 1 - test/dm/sound.c | 1 - test/dm/spi.c | 1 - test/dm/spmi.c | 1 - test/dm/syscon-reset.c | 1 - test/dm/syscon.c | 1 - test/dm/sysinfo-gpio.c | 1 - test/dm/sysinfo.c | 1 - test/dm/sysreset.c | 1 - test/dm/tag.c | 1 - test/dm/tee.c | 1 - test/dm/test-dm.c | 1 - test/dm/test-driver.c | 1 - test/dm/test-fdt.c | 1 - test/dm/test-uclass.c | 1 - test/dm/timer.c | 1 - test/dm/tpm.c | 1 - test/dm/usb.c | 1 - test/dm/video.c | 1 - test/dm/virtio.c | 1 - test/dm/virtio_device.c | 1 - test/dm/virtio_rng.c | 1 - test/dm/wdt.c | 2 +- test/env/attr.c | 1 - test/env/cmd_ut_env.c | 1 - test/env/fdt.c | 1 - test/env/hashtable.c | 2 +- test/fuzz/cmd_fuzz.c | 1 - test/fuzz/virtio.c | 1 - test/image/spl_load.c | 1 - test/image/spl_load_fs.c | 1 - test/image/spl_load_net.c | 1 - test/image/spl_load_nor.c | 1 - test/image/spl_load_os.c | 1 - test/image/spl_load_spi.c | 1 - test/lib/abuf.c | 1 - test/lib/asn1.c | 1 - test/lib/cmd_ut_lib.c | 1 - test/lib/efi_device_path.c | 1 - test/lib/efi_image_region.c | 1 - test/lib/getopt.c | 1 - test/lib/hexdump.c | 1 - test/lib/kconfig.c | 1 - test/lib/kconfig_spl.c | 1 - test/lib/lmb.c | 1 - test/lib/longjmp.c | 1 - test/lib/rsa.c | 1 - test/lib/sscanf.c | 1 - test/lib/string.c | 1 - test/lib/strlcat.c | 1 - test/lib/test_aes.c | 1 - test/lib/test_crypt.c | 1 - test/lib/test_errno_str.c | 1 - test/lib/test_print.c | 1 - test/lib/uuid.c | 1 - test/log/cont_test.c | 1 - test/log/log_filter.c | 1 - test/log/log_test.c | 1 - test/log/log_ut.c | 1 - test/log/nolog_ndebug.c | 1 - test/log/nolog_test.c | 1 - test/log/pr_cont_test.c | 1 - test/log/syslog_test.c | 1 - test/log/syslog_test_ndebug.c | 1 - test/optee/cmd_ut_optee.c | 1 - test/overlay/cmd_ut_overlay.c | 1 - test/print_ut.c | 1 - test/py/u_boot_console_base.py | 15 +- test/stdint/int-types.c | 2 +- test/str_ut.c | 1 - test/test-main.c | 1 - test/time_ut.c | 1 - test/unicode_ut.c | 1 - test/ut.c | 1 - tools/dtoc/dtb_platdata.py | 3 - tools/dtoc/test_dtoc.py | 3 - 4263 files changed, 8361 insertions(+), 4480 deletions(-) create mode 100644 arch/arm/include/asm/arch-adi/sc5xx/sc5xx.h create mode 100644 arch/arm/include/asm/arch-adi/sc5xx/soc.h create mode 100644 arch/arm/include/asm/arch-adi/sc5xx/spl.h create mode 100644 arch/arm/mach-k3/am64x/boot.c create mode 100644 arch/arm/mach-sc5xx/Kconfig create mode 100644 arch/arm/mach-sc5xx/Makefile create mode 100644 arch/arm/mach-sc5xx/config.mk create mode 100644 arch/arm/mach-sc5xx/init/Makefile create mode 100644 arch/arm/mach-sc5xx/init/clkinit.c create mode 100644 arch/arm/mach-sc5xx/init/clkinit.h create mode 100644 arch/arm/mach-sc5xx/init/dmcinit.c create mode 100644 arch/arm/mach-sc5xx/init/dmcinit.h create mode 100644 arch/arm/mach-sc5xx/init/mem/is43tr16512bl.h create mode 100644 arch/arm/mach-sc5xx/init/mem/mt41k128m16jt.h create mode 100644 arch/arm/mach-sc5xx/init/mem/mt41k512m16ha.h create mode 100644 arch/arm/mach-sc5xx/init/mem/mt47h128m16rt.h create mode 100644 arch/arm/mach-sc5xx/rcu.c create mode 100644 arch/arm/mach-sc5xx/sc57x.c create mode 100644 arch/arm/mach-sc5xx/sc58x.c create mode 100644 arch/arm/mach-sc5xx/sc59x.c create mode 100644 arch/arm/mach-sc5xx/sc59x_64.c create mode 100644 arch/arm/mach-sc5xx/soc.c create mode 100644 arch/arm/mach-sc5xx/spl.c delete mode 100644 arch/arm/mach-versatile/Makefile delete mode 100644 arch/arm/mach-versatile/reset.S delete mode 100644 arch/arm/mach-versatile/timer.c create mode 100644 board/phytec/common/k3/Makefile create mode 100644 board/phytec/common/k3/board.c create mode 100644 drivers/clk/adi/Kconfig create mode 100644 drivers/clk/adi/Makefile create mode 100644 drivers/clk/adi/clk-adi-pll.c create mode 100644 drivers/clk/adi/clk-adi-sc57x.c create mode 100644 drivers/clk/adi/clk-adi-sc58x.c create mode 100644 drivers/clk/adi/clk-adi-sc594.c create mode 100644 drivers/clk/adi/clk-adi-sc598.c create mode 100644 drivers/clk/adi/clk-shared.c create mode 100644 drivers/clk/adi/clk.h create mode 100644 drivers/net/dwc_eth_xgmac.c create mode 100644 drivers/net/dwc_eth_xgmac.h create mode 100644 drivers/net/dwc_eth_xgmac_socfpga.c create mode 100644 drivers/serial/serial_adi_uart4.c create mode 100644 drivers/timer/adi_sc5xx_timer.c delete mode 100644 include/common.h create mode 100644 include/dt-bindings/clock/adi-sc5xx-clock.h create mode 100644 include/env/adi/adi_boot.env diff --git a/MAINTAINERS b/MAINTAINERS index 638b2fdd442..6d021763a62 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -598,6 +598,22 @@ R: Marc Murphy S: Supported F: arch/arm/dts/am335x-sancloud* +ARM SC5XX +M: Nathan Barrett-Morrison +M: Greg Malysa +M: Ian Roberts +M: Vasileios Bimpikas +M: Utsav Agarwal +M: Arturs Artamonovs +S: Supported +T: git https://github.com/analogdevicesinc/lnxdsp-u-boot +F: arch/arm/include/asm/arch-adi/ +F: arch/arm/mach-sc5xx/ +F: drivers/clk/adi/ +F: drivers/serial/serial_adi_uart4.c +F: drivers/timer/adi_sc5xx_timer.c +F: include/env/adi/ + ARM SNAPDRAGON M: Caleb Connolly M: Neil Armstrong diff --git a/api/api.c b/api/api.c index 89003c161c2..d22132f62fe 100644 --- a/api/api.c +++ b/api/api.c @@ -7,11 +7,13 @@ #include #include -#include #include #include +#include #include +#include #include +#include #include #include #include diff --git a/api/api_display.c b/api/api_display.c index 2e877a85d14..8fd078c8c4a 100644 --- a/api/api_display.c +++ b/api/api_display.c @@ -3,9 +3,9 @@ * Copyright (c) 2011 The Chromium OS Authors. */ -#include #include #include +#include /* TODO(clchiou): add support of video device */ diff --git a/api/api_net.c b/api/api_net.c index 7515c26e8b4..264ff530563 100644 --- a/api/api_net.c +++ b/api/api_net.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/api/api_platform-arm.c b/api/api_platform-arm.c index 6cfd9e6cc20..9afba66c244 100644 --- a/api/api_platform-arm.c +++ b/api/api_platform-arm.c @@ -12,7 +12,6 @@ #include #include -#include #include #include "api_private.h" diff --git a/api/api_platform-mips.c b/api/api_platform-mips.c index e1509663af5..262b35a2777 100644 --- a/api/api_platform-mips.c +++ b/api/api_platform-mips.c @@ -9,7 +9,6 @@ #include #include -#include #include #include "api_private.h" diff --git a/api/api_platform-powerpc.c b/api/api_platform-powerpc.c index 847a4a3015b..3a04a9f691c 100644 --- a/api/api_platform-powerpc.c +++ b/api/api_platform-powerpc.c @@ -12,7 +12,6 @@ #include #include -#include #include #include "api_private.h" diff --git a/api/api_storage.c b/api/api_storage.c index 78becbe39fb..3d2d9d6ef4c 100644 --- a/api/api_storage.c +++ b/api/api_storage.c @@ -6,10 +6,10 @@ */ #include -#include #include #include #include +#include #if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE) #include diff --git a/arch/arc/include/asm/global_data.h b/arch/arc/include/asm/global_data.h index e35a26f1eb1..fd9b7fb5f8d 100644 --- a/arch/arc/include/asm/global_data.h +++ b/arch/arc/include/asm/global_data.h @@ -6,6 +6,8 @@ #ifndef __ASM_ARC_GLOBAL_DATA_H #define __ASM_ARC_GLOBAL_DATA_H +#include + #ifndef __ASSEMBLY__ /* Architecture-specific global data */ struct arch_global_data { diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 38fc757c1f0..39ad03acd2e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1853,6 +1853,9 @@ config TARGET_LS1046AFRWY development platform that supports the QorIQ LS1046A Layerscape Architecture processor. +config ARCH_SC5XX + bool "Analog Devices SC5XX-processor family" + config TARGET_SL28 bool "Support sl28" select ARCH_LS1028A @@ -2286,6 +2289,8 @@ source "arch/arm/mach-rockchip/Kconfig" source "arch/arm/mach-s5pc1xx/Kconfig" +source "arch/arm/mach-sc5xx/Kconfig" + source "arch/arm/mach-snapdragon/Kconfig" source "arch/arm/mach-socfpga/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index a4266a3e366..734c6d69926 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -78,6 +78,7 @@ machine-$(CONFIG_ARCH_OWL) += owl machine-$(CONFIG_ARCH_RENESAS) += renesas machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx +machine-$(CONFIG_ARCH_SC5XX) += sc5xx machine-$(CONFIG_ARCH_SNAPDRAGON) += snapdragon machine-$(CONFIG_ARCH_SOCFPGA) += socfpga machine-$(CONFIG_ARCH_STM32) += stm32 diff --git a/arch/arm/cpu/arm11/cpu.c b/arch/arm/cpu/arm11/cpu.c index 1e16b89d006..01d2e1a125d 100644 --- a/arch/arm/cpu/arm11/cpu.c +++ b/arch/arm/cpu/arm11/cpu.c @@ -14,7 +14,6 @@ * CPU specific code */ -#include #include #include #include diff --git a/arch/arm/cpu/arm1136/mx31/devices.c b/arch/arm/cpu/arm1136/mx31/devices.c index 9997e8fc339..87ca303e31b 100644 --- a/arch/arm/cpu/arm1136/mx31/devices.c +++ b/arch/arm/cpu/arm1136/mx31/devices.c @@ -6,7 +6,6 @@ * (c) 2007 Pengutronix, Sascha Hauer */ -#include #include #include diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index a3d4f147962..fc56baccfcd 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -4,7 +4,6 @@ * Sascha Hauer, Pengutronix */ -#include #include #include #include diff --git a/arch/arm/cpu/arm1136/mx31/timer.c b/arch/arm/cpu/arm1136/mx31/timer.c index a913860491c..b41ca68ae55 100644 --- a/arch/arm/cpu/arm1136/mx31/timer.c +++ b/arch/arm/cpu/arm1136/mx31/timer.c @@ -4,7 +4,6 @@ * Sascha Hauer, Pengutronix */ -#include #include #include #include diff --git a/arch/arm/cpu/arm720t/interrupts.c b/arch/arm/cpu/arm720t/interrupts.c index f0fc58deadb..e3d0216158f 100644 --- a/arch/arm/cpu/arm720t/interrupts.c +++ b/arch/arm/cpu/arm720t/interrupts.c @@ -9,7 +9,7 @@ * Alex Zuepke */ -#include +#include #if defined(CONFIG_ARCH_TEGRA) static ulong timestamp; diff --git a/arch/arm/cpu/arm920t/cpu.c b/arch/arm/cpu/arm920t/cpu.c index 305713e7861..61e18230573 100644 --- a/arch/arm/cpu/arm920t/cpu.c +++ b/arch/arm/cpu/arm920t/cpu.c @@ -12,7 +12,6 @@ * CPU specific code */ -#include #include #include #include diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index cba4a1f0358..e792e8e795e 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -8,7 +8,6 @@ */ #include -#include #include /* diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index 95963d2665f..5b87a3af91b 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -6,7 +6,6 @@ #include #include #include -#include #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void invalidate_dcache_all(void) diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c index 2ce413a7f86..07ab04b7b08 100644 --- a/arch/arm/cpu/arm926ejs/cpu.c +++ b/arch/arm/cpu/arm926ejs/cpu.c @@ -12,7 +12,6 @@ * CPU specific code */ -#include #include #include #include diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c index 4e1cf3a1e32..58f6cf80cae 100644 --- a/arch/arm/cpu/arm926ejs/mxs/clock.c +++ b/arch/arm/cpu/arm926ejs/mxs/clock.c @@ -9,7 +9,6 @@ * Copyright (C) 2010 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/arm/cpu/arm926ejs/mxs/iomux.c b/arch/arm/cpu/arm926ejs/mxs/iomux.c index 381264b8a18..851b4deb080 100644 --- a/arch/arm/cpu/arm926ejs/mxs/iomux.c +++ b/arch/arm/cpu/arm926ejs/mxs/iomux.c @@ -6,7 +6,6 @@ * */ -#include #include #include #include diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index 4f3cb63c56d..7b2bb09551b 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -9,7 +9,6 @@ * Copyright (C) 2010 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index 249f8de8fbe..76a69d7f958 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -6,7 +6,6 @@ * on behalf of DENX Software Engineering GmbH */ -#include #include #include #include diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c index 2cfbd780953..b2d3b2b13ef 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c @@ -6,7 +6,6 @@ * on behalf of DENX Software Engineering GmbH */ -#include #include #include #include diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index a94803ee93d..c3136dd8976 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -6,7 +6,6 @@ * on behalf of DENX Software Engineering GmbH */ -#include #include #include #include diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index 77bca7e331a..8b65c094a8a 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -6,7 +6,6 @@ * on behalf of DENX Software Engineering GmbH */ -#include #include #include #include diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S index 61982e38a1d..a6eb053cadb 100644 --- a/arch/arm/cpu/arm926ejs/mxs/start.S +++ b/arch/arm/cpu/arm926ejs/mxs/start.S @@ -20,7 +20,6 @@ #include #include -#include #include /* diff --git a/arch/arm/cpu/arm926ejs/mxs/timer.c b/arch/arm/cpu/arm926ejs/mxs/timer.c index 3dff3d768d1..cbd3b5d9958 100644 --- a/arch/arm/cpu/arm926ejs/mxs/timer.c +++ b/arch/arm/cpu/arm926ejs/mxs/timer.c @@ -9,7 +9,6 @@ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index c882bd39eab..5d6c9f0861e 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -16,7 +16,6 @@ #include #include -#include #include /* diff --git a/arch/arm/cpu/arm946es/cpu.c b/arch/arm/cpu/arm946es/cpu.c index 334bb542743..efd232d3423 100644 --- a/arch/arm/cpu/arm946es/cpu.c +++ b/arch/arm/cpu/arm946es/cpu.c @@ -12,7 +12,6 @@ * CPU specific code */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c index 17bd53dae84..f25a8674dea 100644 --- a/arch/arm/cpu/armv7/arch_timer.c +++ b/arch/arm/cpu/armv7/arch_timer.c @@ -4,7 +4,7 @@ * Texas Instruments Incorporated, */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c b/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c index 39217c5b2bf..7f73f893458 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c @@ -9,7 +9,6 @@ * */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c b/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c index 1b3f36aebe1..55dcc2fd78c 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c @@ -3,7 +3,6 @@ * Copyright 2013 Broadcom Corporation. */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-core.c b/arch/arm/cpu/armv7/bcm235xx/clk-core.c index d7edefee231..b769c451105 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-core.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-core.c @@ -9,7 +9,6 @@ * */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-eth.c b/arch/arm/cpu/armv7/bcm235xx/clk-eth.c index 209ceca9a06..5f7cc4a102d 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-eth.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-eth.c @@ -3,7 +3,6 @@ * Copyright 2014 Broadcom Corporation. */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c b/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c index f2ba354c24f..f3ff29bebe8 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c @@ -3,7 +3,6 @@ * Copyright 2013 Broadcom Corporation. */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c b/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c index f604aec62fa..87918059408 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c @@ -3,7 +3,6 @@ * Copyright 2014 Broadcom Corporation. */ -#include #include #include #include "clk-core.h" diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c index 8f6260e7857..b258fea45c8 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c @@ -9,7 +9,6 @@ * */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c b/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c index 1b3f36aebe1..55dcc2fd78c 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c @@ -3,7 +3,6 @@ * Copyright 2013 Broadcom Corporation. */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-core.c b/arch/arm/cpu/armv7/bcm281xx/clk-core.c index 26b673a5405..3f2e021a307 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-core.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-core.c @@ -9,7 +9,6 @@ * */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-eth.c b/arch/arm/cpu/armv7/bcm281xx/clk-eth.c index 209ceca9a06..5f7cc4a102d 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-eth.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-eth.c @@ -3,7 +3,6 @@ * Copyright 2014 Broadcom Corporation. */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c b/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c index f2ba354c24f..f3ff29bebe8 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c @@ -3,7 +3,6 @@ * Copyright 2013 Broadcom Corporation. */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c b/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c index f604aec62fa..87918059408 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c @@ -3,7 +3,6 @@ * Copyright 2014 Broadcom Corporation. */ -#include #include #include #include "clk-core.h" diff --git a/arch/arm/cpu/armv7/bcm281xx/reset.c b/arch/arm/cpu/armv7/bcm281xx/reset.c index 1491e5c88b2..87e4337be4e 100644 --- a/arch/arm/cpu/armv7/bcm281xx/reset.c +++ b/arch/arm/cpu/armv7/bcm281xx/reset.c @@ -3,7 +3,6 @@ * Copyright 2013 Broadcom Corporation. */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7/bcmcygnus/reset.c b/arch/arm/cpu/armv7/bcmcygnus/reset.c index 63992fd8701..617c8d68a2a 100644 --- a/arch/arm/cpu/armv7/bcmcygnus/reset.c +++ b/arch/arm/cpu/armv7/bcmcygnus/reset.c @@ -3,7 +3,6 @@ * Copyright 2014 Broadcom Corporation. */ -#include #include #include diff --git a/arch/arm/cpu/armv7/bcmnsp/reset.c b/arch/arm/cpu/armv7/bcmnsp/reset.c index a3137752e88..c3be33124c6 100644 --- a/arch/arm/cpu/armv7/bcmnsp/reset.c +++ b/arch/arm/cpu/armv7/bcmnsp/reset.c @@ -3,7 +3,6 @@ * Copyright 2014 Broadcom Corporation. */ -#include #include #include diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 19ff4323528..d11420d2fdd 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include diff --git a/arch/arm/cpu/armv7/cp15.c b/arch/arm/cpu/armv7/cp15.c index 0ac4e7ba8c8..b2c52db68dc 100644 --- a/arch/arm/cpu/armv7/cp15.c +++ b/arch/arm/cpu/armv7/cp15.c @@ -7,7 +7,6 @@ * CP15 specific code */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c index 6259ffa5108..aa981faef00 100644 --- a/arch/arm/cpu/armv7/cpu.c +++ b/arch/arm/cpu/armv7/cpu.c @@ -14,7 +14,6 @@ * CPU specific code */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7/exception_level.c b/arch/arm/cpu/armv7/exception_level.c index f6d25bb682c..7baade61b07 100644 --- a/arch/arm/cpu/armv7/exception_level.c +++ b/arch/arm/cpu/armv7/exception_level.c @@ -8,7 +8,6 @@ * secure mode before booting an operating system. */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7/iproc-common/armpll.c b/arch/arm/cpu/armv7/iproc-common/armpll.c index 8c3a323f065..b345671b0a6 100644 --- a/arch/arm/cpu/armv7/iproc-common/armpll.c +++ b/arch/arm/cpu/armv7/iproc-common/armpll.c @@ -3,7 +3,6 @@ * Copyright 2014 Broadcom Corporation. */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7/iproc-common/hwinit-common.c b/arch/arm/cpu/armv7/iproc-common/hwinit-common.c index 896d2f95694..eca7e8b512b 100644 --- a/arch/arm/cpu/armv7/iproc-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/iproc-common/hwinit-common.c @@ -3,7 +3,6 @@ * Copyright 2014 Broadcom Corporation. */ -#include #include #include diff --git a/arch/arm/cpu/armv7/iproc-common/timer.c b/arch/arm/cpu/armv7/iproc-common/timer.c index a4255a44c00..b60d90f7e6a 100644 --- a/arch/arm/cpu/armv7/iproc-common/timer.c +++ b/arch/arm/cpu/armv7/iproc-common/timer.c @@ -3,7 +3,6 @@ * Copyright 2014 Broadcom Corporation. */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c b/arch/arm/cpu/armv7/ls102xa/clock.c index 4e1fe281201..e885a85ce65 100644 --- a/arch/arm/cpu/armv7/ls102xa/clock.c +++ b/arch/arm/cpu/armv7/ls102xa/clock.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index c455969609f..74a2dcbc116 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -4,7 +4,6 @@ * Copyright 2021 NXP */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index 1c3d24bcad9..34eea22eb92 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.c b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c index e31a4fb6c31..664eae532d5 100644 --- a/arch/arm/cpu/armv7/ls102xa/fsl_epu.c +++ b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c @@ -3,7 +3,6 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include #include #include "fsl_epu.h" diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c index f74d819ea1e..c1eadb34523 100644 --- a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c +++ b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c index 8c030be8b36..3032e266c5d 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include +#include #include #include diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 84d4ea3a8f4..7ff59edd452 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -3,7 +3,7 @@ * Copyright 2015 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv7/ls102xa/spl.c b/arch/arm/cpu/armv7/ls102xa/spl.c index a1949686235..374de92d026 100644 --- a/arch/arm/cpu/armv7/ls102xa/spl.c +++ b/arch/arm/cpu/armv7/ls102xa/spl.c @@ -3,7 +3,6 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include #include u32 spl_boot_device(void) diff --git a/arch/arm/cpu/armv7/ls102xa/timer.c b/arch/arm/cpu/armv7/ls102xa/timer.c index c6126b10c35..6f32ced5aec 100644 --- a/arch/arm/cpu/armv7/ls102xa/timer.c +++ b/arch/arm/cpu/armv7/ls102xa/timer.c @@ -3,7 +3,6 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7/mpu_v7r.c b/arch/arm/cpu/armv7/mpu_v7r.c index 1d31c63e5fd..2d83e4c721d 100644 --- a/arch/arm/cpu/armv7/mpu_v7r.c +++ b/arch/arm/cpu/armv7/mpu_v7r.c @@ -6,7 +6,6 @@ * Lokesh Vutla */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7/s5p-common/cpu_info.c b/arch/arm/cpu/armv7/s5p-common/cpu_info.c index fb2920950d4..4331dde7643 100644 --- a/arch/arm/cpu/armv7/s5p-common/cpu_info.c +++ b/arch/arm/cpu/armv7/s5p-common/cpu_info.c @@ -3,7 +3,6 @@ * Copyright (C) 2009 Samsung Electronics * Minkyu Kang */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7/s5p-common/pwm.c b/arch/arm/cpu/armv7/s5p-common/pwm.c index 5068327d3c5..986b585b70e 100644 --- a/arch/arm/cpu/armv7/s5p-common/pwm.c +++ b/arch/arm/cpu/armv7/s5p-common/pwm.c @@ -5,7 +5,7 @@ * Donghwa Lee */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv7/s5p-common/sromc.c b/arch/arm/cpu/armv7/s5p-common/sromc.c index 0fc170936ae..c0035fb18eb 100644 --- a/arch/arm/cpu/armv7/s5p-common/sromc.c +++ b/arch/arm/cpu/armv7/s5p-common/sromc.c @@ -4,7 +4,7 @@ * Naveen Krishna Ch */ -#include +#include #include #include diff --git a/arch/arm/cpu/armv7/s5p-common/timer.c b/arch/arm/cpu/armv7/s5p-common/timer.c index 9d981cce145..12994ecc843 100644 --- a/arch/arm/cpu/armv7/s5p-common/timer.c +++ b/arch/arm/cpu/armv7/s5p-common/timer.c @@ -6,7 +6,6 @@ * Minkyu Kang */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7/s5p4418/cpu.c b/arch/arm/cpu/armv7/s5p4418/cpu.c index 8febfe52766..27ffb450378 100644 --- a/arch/arm/cpu/armv7/s5p4418/cpu.c +++ b/arch/arm/cpu/armv7/s5p4418/cpu.c @@ -4,7 +4,6 @@ * Hyunseok, Jung */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c index 5cb8cfa6cf3..4c30f3294b7 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.c +++ b/arch/arm/cpu/armv7/sunxi/psci.c @@ -7,7 +7,6 @@ * which was based on code by Carl van Schaik . */ #include -#include #include #include diff --git a/arch/arm/cpu/armv7/sunxi/sram.c b/arch/arm/cpu/armv7/sunxi/sram.c index 28ff6a1b7c2..bc25719c9c4 100644 --- a/arch/arm/cpu/armv7/sunxi/sram.c +++ b/arch/arm/cpu/armv7/sunxi/sram.c @@ -9,7 +9,6 @@ * SRAM init for older sunxi SoCs. */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7/syslib.c b/arch/arm/cpu/armv7/syslib.c index 7e29636972d..f0eda1ca98d 100644 --- a/arch/arm/cpu/armv7/syslib.c +++ b/arch/arm/cpu/armv7/syslib.c @@ -7,7 +7,6 @@ * Syed Mohammed Khasim */ -#include #include /************************************************************ diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c index c23ddc12b45..e61ad7b96e9 100644 --- a/arch/arm/cpu/armv7/vf610/generic.c +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -3,7 +3,6 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7/vf610/timer.c b/arch/arm/cpu/armv7/vf610/timer.c index a9c1a8fcebc..7bae0b5574a 100644 --- a/arch/arm/cpu/armv7/vf610/timer.c +++ b/arch/arm/cpu/armv7/vf610/timer.c @@ -3,7 +3,6 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c index c0422485ba4..5dc7ed5e270 100644 --- a/arch/arm/cpu/armv7/virt-dt.c +++ b/arch/arm/cpu/armv7/virt-dt.c @@ -15,7 +15,6 @@ * along with this program. If not, see . */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index 5ffeca13d91..811499367d4 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -8,7 +8,6 @@ * needed to enable ARMv7 virtualization for current hypervisors */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c index d1aecf6a85c..b6d08b7aad7 100644 --- a/arch/arm/cpu/armv7m/cache.c +++ b/arch/arm/cpu/armv7m/cache.c @@ -4,7 +4,6 @@ * Author(s): Vikas Manocha, for STMicroelectronics. */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7m/cpu.c b/arch/arm/cpu/armv7m/cpu.c index 65427b5312b..b4440d3f3f8 100644 --- a/arch/arm/cpu/armv7m/cpu.c +++ b/arch/arm/cpu/armv7m/cpu.c @@ -7,7 +7,6 @@ * Kamil Lulko, */ -#include #include #include #include diff --git a/arch/arm/cpu/armv7m/systick-timer.c b/arch/arm/cpu/armv7m/systick-timer.c index c30af4ff7a2..d8fa4f0c707 100644 --- a/arch/arm/cpu/armv7m/systick-timer.c +++ b/arch/arm/cpu/armv7m/systick-timer.c @@ -21,7 +21,7 @@ * using CFG_SYS_HZ_CLOCK. */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 57d06f0575d..d4c64f2d60d 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -7,7 +7,6 @@ * Alexander Graf */ -#include #include #include #include diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c index 9bfe3815e51..97667e607a8 100644 --- a/arch/arm/cpu/armv8/cpu-dt.c +++ b/arch/arm/cpu/armv8/cpu-dt.c @@ -3,7 +3,6 @@ * Copyright 2016 NXP Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c index 3c7f36ad8d8..d568efa427a 100644 --- a/arch/arm/cpu/armv8/cpu.c +++ b/arch/arm/cpu/armv8/cpu.c @@ -10,7 +10,6 @@ * Gary Jennejohn, DENX Software Engineering, */ -#include #include #include #include diff --git a/arch/arm/cpu/armv8/exception_level.c b/arch/arm/cpu/armv8/exception_level.c index b11936548fb..85c78f55789 100644 --- a/arch/arm/cpu/armv8/exception_level.c +++ b/arch/arm/cpu/armv8/exception_level.c @@ -8,7 +8,6 @@ * level before booting an operating system. */ -#include #include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 12d31184ad9..d2dbfdd08a0 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -4,7 +4,7 @@ * Copyright 2014-2015 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 22ce6992165..ca6be3626fb 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -4,7 +4,7 @@ * Copyright 2020-2021 NXP */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c index b1bb29bcaf5..78961d8089e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c @@ -3,11 +3,12 @@ * Copyright 2015 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include #include +#include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 4455eb1726d..9a24d4b3031 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -4,7 +4,7 @@ * Copyright 2019 NXP. */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index fbd5fd7d433..b768790437f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -4,7 +4,7 @@ * Copyright 2014-2015 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index 137778dc136..452246e0e67 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -6,7 +6,7 @@ * Derived from arch/power/cpu/mpc85xx/speed.c */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c index c22e73253c3..04ffefafbf7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c @@ -3,7 +3,7 @@ * Copyright 2018 NXP */ -#include +#include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c index 8d7beca7db3..c0e5455507a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c @@ -3,7 +3,7 @@ * Copyright 2016 Freescale Semiconductor, Inc. */ -#include +#include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c index 86a49b152e4..d48baa63816 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c @@ -3,9 +3,9 @@ * Copyright 2019 NXP */ -#include #include #include +#include #include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c index 80d2910f679..1b4eab3613e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c @@ -3,7 +3,8 @@ * Copyright 2019 NXP */ -#include +#include +#include #include struct serdes_config { diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c index e3c3fc6bfb5..ec80e42055d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c @@ -3,11 +3,12 @@ * Copyright 2018 NXP */ -#include +#include #include #include #include #include +#include #ifdef CONFIG_SYS_DPAA_QBMAN struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c index 6c5e52ebaa6..1911ca1a175 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c @@ -3,7 +3,7 @@ * Copyright 2015 Freescale Semiconductor, Inc. */ -#include +#include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c index 333d7e2fa21..a73dd316f8d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c @@ -3,10 +3,11 @@ * Copyright 2018 NXP */ -#include +#include #include #include #include +#include #ifdef CONFIG_SYS_DPAA_QBMAN struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c index 9347e516bf6..26ca4ca10f3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c @@ -4,7 +4,7 @@ * Copyright 2019 NXP */ -#include +#include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c index 23743ae10cf..3a076ca04f6 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c @@ -3,10 +3,11 @@ * Copyright 2019 NXP */ -#include +#include #include #include #include +#include struct icid_id_table icid_tbl[] = { SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c index fe667f06c39..154b727392e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c @@ -3,7 +3,7 @@ * Copyright 2017-2019 NXP */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c index 7997422840f..5088c8ebb7f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c @@ -3,7 +3,7 @@ * Copyright 2014-2015 Freescale Semiconductor, Inc. */ -#include +#include #include struct serdes_config { diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c index e6403b79526..c320e835c99 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c @@ -3,10 +3,11 @@ * Copyright 2019 NXP */ -#include +#include #include #include #include +#include struct icid_id_table icid_tbl[] = { SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c index 3a0ed1fa550..df9329df77e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c @@ -3,10 +3,11 @@ * Copyright 2019 NXP */ -#include +#include #include #include #include +#include struct icid_id_table icid_tbl[] = { SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c index 5941d90e036..43f0e8c87ba 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c @@ -3,7 +3,7 @@ * Copyright 2018, 2020 NXP */ -#include +#include #include struct serdes_config { diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index ce0c46ad0d4..db913208b9e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -3,7 +3,7 @@ * Copyright 2014-2015 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 4c61d28c20f..d85a630f8a3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -4,7 +4,7 @@ * Copyright 2019-2021 NXP */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 232adfa843a..a739ff2da58 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -3,7 +3,7 @@ * Copyright 2014-2015 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c index e18b5c81875..1de7ec596fc 100644 --- a/arch/arm/cpu/armv8/generic_timer.c +++ b/arch/arm/cpu/armv8/generic_timer.c @@ -4,7 +4,6 @@ * David Feng */ -#include #include #include #include diff --git a/arch/arm/cpu/armv8/hisilicon/pinmux.c b/arch/arm/cpu/armv8/hisilicon/pinmux.c index e14057c0a47..d7a5a792610 100644 --- a/arch/arm/cpu/armv8/hisilicon/pinmux.c +++ b/arch/arm/cpu/armv8/hisilicon/pinmux.c @@ -4,7 +4,6 @@ * Peter Griffin */ -#include #include #include #include diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index c0e8726346f..44372cbe4a1 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -3,7 +3,7 @@ * Copyright 2016 NXP Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv8/sha1_ce_glue.c b/arch/arm/cpu/armv8/sha1_ce_glue.c index 780b119a90b..c88b4dc66e1 100644 --- a/arch/arm/cpu/armv8/sha1_ce_glue.c +++ b/arch/arm/cpu/armv8/sha1_ce_glue.c @@ -5,7 +5,6 @@ * Copyright (C) 2022 Linaro Ltd */ -#include #include extern void sha1_armv8_ce_process(uint32_t state[5], uint8_t const *src, diff --git a/arch/arm/cpu/armv8/sha256_ce_glue.c b/arch/arm/cpu/armv8/sha256_ce_glue.c index 67dd796c122..d5d2b4f4ac7 100644 --- a/arch/arm/cpu/armv8/sha256_ce_glue.c +++ b/arch/arm/cpu/armv8/sha256_ce_glue.c @@ -5,7 +5,6 @@ * Copyright (C) 2022 Linaro Ltd */ -#include #include extern void sha256_armv8_ce_process(uint32_t state[8], uint8_t const *src, diff --git a/arch/arm/cpu/armv8/spin_table.c b/arch/arm/cpu/armv8/spin_table.c index 42a0962fdcd..485294b88d0 100644 --- a/arch/arm/cpu/armv8/spin_table.c +++ b/arch/arm/cpu/armv8/spin_table.c @@ -4,7 +4,6 @@ * Author: Masahiro Yamada */ -#include #include #include diff --git a/arch/arm/cpu/armv8/spl_data.c b/arch/arm/cpu/armv8/spl_data.c index 8f1231c86eb..259b49ff364 100644 --- a/arch/arm/cpu/armv8/spl_data.c +++ b/arch/arm/cpu/armv8/spl_data.c @@ -3,7 +3,6 @@ * Copyright 2020 NXP */ -#include #include char __data_save_start[0] __section(".__data_save_start"); diff --git a/arch/arm/dts/k3-j7200-binman.dtsi b/arch/arm/dts/k3-j7200-binman.dtsi index 06db8659876..e8020fec2dc 100644 --- a/arch/arm/dts/k3-j7200-binman.dtsi +++ b/arch/arm/dts/k3-j7200-binman.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-binman.dtsi" @@ -47,6 +47,52 @@ config = "pm-cfg_j7200.yaml"; }; +&binman { + tiboot3-j7200-hs-evm.bin { + filename = "tiboot3-j7200-hs-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl_sr1>, <&ti_fs_enc_sr1>, <&combined_tifs_cfg_sr1>, + <&combined_dm_cfg_sr1>, <&sysfw_inner_cert_sr1>; + combined; + dm-data; + core-opts = <2>; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl_sr1>; + content-sysfw = <&ti_fs_enc_sr1>; + content-sysfw-data = <&combined_tifs_cfg_sr1>; + content-sysfw-inner-cert = <&sysfw_inner_cert_sr1>; + content-dm-data = <&combined_dm_cfg_sr1>; + load = <0x41c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x7f000>; + load-dm-data = <0x41c80000>; + }; + u_boot_spl_sr1: u-boot-spl { + no-expanded; + }; + ti_fs_enc_sr1: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-j7200-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + combined_tifs_cfg_sr1: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + sysfw_inner_cert_sr1: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-j7200-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + combined_dm_cfg_sr1: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + &binman { tiboot3-j7200_sr2-hs-evm.bin { filename = "tiboot3-j7200_sr2-hs-evm.bin"; @@ -92,6 +138,53 @@ }; }; +&binman { + tiboot3-j7200-hs-fs-evm.bin { + filename = "tiboot3-j7200-hs-fs-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl_fs_sr1>, <&ti_fs_enc_fs_sr1>, + <&combined_tifs_cfg_fs_sr1>, <&combined_dm_cfg_fs_sr1>, + <&sysfw_inner_cert_fs_sr1>; + combined; + dm-data; + core-opts = <2>; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl_fs_sr1>; + content-sysfw = <&ti_fs_enc_fs_sr1>; + content-sysfw-data = <&combined_tifs_cfg_fs_sr1>; + content-sysfw-inner-cert = <&sysfw_inner_cert_fs_sr1>; + content-dm-data = <&combined_dm_cfg_fs_sr1>; + load = <0x41c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x7f000>; + load-dm-data = <0x41c80000>; + }; + u_boot_spl_fs_sr1: u-boot-spl { + no-expanded; + }; + ti_fs_enc_fs_sr1: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-j7200-hs-fs-enc.bin"; + type = "blob-ext"; + optional; + }; + combined_tifs_cfg_fs_sr1: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + sysfw_inner_cert_fs_sr1: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-j7200-hs-fs-cert.bin"; + type = "blob-ext"; + optional; + }; + combined_dm_cfg_fs_sr1: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + &binman { tiboot3-j7200_sr2-hs-fs-evm.bin { filename = "tiboot3-j7200_sr2-hs-fs-evm.bin"; diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi index 75a6e9599b9..1514d897634 100644 --- a/arch/arm/dts/k3-j721e-binman.dtsi +++ b/arch/arm/dts/k3-j721e-binman.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-binman.dtsi" @@ -129,6 +129,94 @@ }; }; +&binman { + tiboot3-j721e_sr1_1-hs-fs-evm.bin { + filename = "tiboot3-j721e_sr1_1-hs-fs-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl_fs_sr1_1>; + core = "public"; + core-opts = <2>; + load = ; + keyfile = "custMpk.pem"; + }; + u_boot_spl_fs_sr1_1: u-boot-spl { + no-expanded; + }; + }; + sysfw_fs_sr1_1 { + filename = "sysfw.bin_fs_sr1_1"; + ti-fs-cert-fs.bin { + filename = "ti-sysfw/ti-fs-firmware-j721e_sr1_1-hs-fs-cert.bin"; + type = "blob-ext"; + optional; + }; + ti-fs-firmware-j721e-hs-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-j721e_sr1_1-hs-fs-enc.bin"; + type = "blob-ext"; + optional; + }; + }; + itb_fs_sr1_1 { + filename = "sysfw-j721e_sr1_1-hs-fs-evm.itb"; + fit { + description = "SYSFW and Config fragments"; + #address-cells = <1>; + images { + sysfw.bin { + description = "sysfw"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "sysfw.bin_fs_sr1_1"; + }; + }; + board-cfg.bin { + description = "board-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + board-cfg { + filename = "board-cfg.bin"; + type = "blob-ext"; + }; + + }; + pm-cfg.bin { + description = "pm-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + pm-cfg { + filename = "pm-cfg.bin"; + type = "blob-ext"; + }; + }; + rm-cfg.bin { + description = "rm-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + rm-cfg { + filename = "rm-cfg.bin"; + type = "blob-ext"; + }; + }; + sec-cfg.bin { + description = "sec-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + sec-cfg { + filename = "sec-cfg.bin"; + type = "blob-ext"; + }; + }; + }; + }; + }; +}; + &binman { tiboot3-j721e_sr2-hs-fs-evm.bin { filename = "tiboot3-j721e_sr2-hs-fs-evm.bin"; diff --git a/arch/arm/include/asm/arch-adi/sc5xx/sc5xx.h b/arch/arm/include/asm/arch-adi/sc5xx/sc5xx.h new file mode 100644 index 00000000000..683e3d412ce --- /dev/null +++ b/arch/arm/include/asm/arch-adi/sc5xx/sc5xx.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison + * Contact: Greg Malysa + */ +#ifndef ARCH_ADI_SC5XX_SC5XX_H +#define ARCH_ADI_SC5XX_SC5XX_H + +#include + +#define TWI0_CLKDIV 0x31001400 // TWI0 SCL Clock Divider Register +#define TWI1_CLKDIV 0x31001500 // TWI1 SCL Clock Divider Register +#define TWI2_CLKDIV 0x31001600 // TWI2 SCL Clock Divider Register + +const char *sc5xx_get_boot_mode(u32 *bmode); +void sc5xx_enable_rgmii(void); + +void sc5xx_enable_ns_sharc_access(uintptr_t securec0_base); +void sc5xx_disable_spu0(uintptr_t spu0_start, uintptr_t spu0_end); +void sc5xx_enable_pmu(void); + +/** + * Per-SoC init function to be used to initialize hw-specific things. Examples: + * enable PMU on armv7, enable coresight timer on armv8, etc. + */ +void sc5xx_soc_init(void); + +/* + * Reconfigure SPI memory map region for OSPI use. The adi-spi3 driver + * does not use the memory map, while the OSPI driver requires it. Only + * available on sc59x and sc59x-64 + */ +void sc59x_remap_ospi(void); + +#endif diff --git a/arch/arm/include/asm/arch-adi/sc5xx/soc.h b/arch/arm/include/asm/arch-adi/sc5xx/soc.h new file mode 100644 index 00000000000..430dbe2dae4 --- /dev/null +++ b/arch/arm/include/asm/arch-adi/sc5xx/soc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison + * Contact: Greg Malysa + */ + +#ifndef BOARD_ADI_COMMON_SOC_H +#define BOARD_ADI_COMMON_SOC_H + +#include + +void fixup_dp83867_phy(struct phy_device *phydev); + +#endif diff --git a/arch/arm/include/asm/arch-adi/sc5xx/spl.h b/arch/arm/include/asm/arch-adi/sc5xx/spl.h new file mode 100644 index 00000000000..c215e6b892a --- /dev/null +++ b/arch/arm/include/asm/arch-adi/sc5xx/spl.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison + * Contact: Greg Malysa + */ +#ifndef ARCH_ADI_SC5XX_SPL_H +#define ARCH_ADI_SC5XX_SPL_H + +#include + +struct adi_boot_args { + phys_addr_t addr; + u32 flags; + u32 cmd; +}; + +extern u32 bmode; + +/** + * This table stores the arguments to the rom boot function per bootmode, + * and it is populated per SoC in the corresponding SoC support file (sc7x, sc58x, + * and so on). + */ +extern const struct adi_boot_args adi_rom_boot_args[8]; + +/** + * Struct layout for the boot config is also specific to an SoC, so you should + * only access it inside an SoC-specific boot hook function, which will be called + * from the boot rom while going from SPL to proper u-boot + */ +struct ADI_ROM_BOOT_CONFIG; +int32_t adi_rom_boot_hook(struct ADI_ROM_BOOT_CONFIG *cfg, int32_t cause); + +typedef void (*adi_rom_boot_fn)(void *address, uint32_t flags, int32_t count, + void *hook, uint32_t command); + +extern adi_rom_boot_fn adi_rom_boot; + +#endif diff --git a/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h b/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h index 8e3d55f3e76..393bc7a6a8a 100644 --- a/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h +++ b/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h @@ -10,6 +10,8 @@ #ifndef __CLK_SYNTHESIZER_H #define __CLK_SYNTHESIZER_H +#include + #define CLK_SYNTHESIZER_ID_REG 0x0 #define CLK_SYNTHESIZER_XCSEL 0x05 #define CLK_SYNTHESIZER_MUX_REG 0x14 diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h index 50d6a6bc760..a415693de6e 100644 --- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h @@ -140,6 +140,7 @@ #define SCU_CLKDUTY_RGMII2TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII2TXCK_SHIFT) #ifndef __ASSEMBLY__ +#include struct ast2500_clk_priv { struct ast2500_scu *scu; diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2600.h b/arch/arm/include/asm/arch-aspeed/scu_ast2600.h index 251bfa269bf..a2c8852db84 100644 --- a/arch/arm/include/asm/arch-aspeed/scu_ast2600.h +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2600.h @@ -125,6 +125,8 @@ #define SCU_MISC_CTRL1_UART5_DIV BIT(12) #ifndef __ASSEMBLY__ +#include + struct ast2600_scu { uint32_t prot_key1; /* 0x000 */ uint32_t chip_id1; /* 0x004 */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index 9e29350ca4b..a02bec9371c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -7,6 +7,8 @@ #ifndef __FSL_SERDES_H__ #define __FSL_SERDES_H__ +#include + #ifdef CONFIG_FSL_LSCH3 enum srds_prtcl { /* diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 9794db04499..147ca2f99de 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -6,6 +6,7 @@ #ifndef __ARCH_FSL_LSCH2_IMMAP_H__ #define __ARCH_FSL_LSCH2_IMMAP_H__ +#include #include #ifndef __ASSEMBLY__ #include diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h index c14855d177e..1f81d91977c 100644 --- a/arch/arm/include/asm/arch-imx8m/ddr.h +++ b/arch/arm/include/asm/arch-imx8m/ddr.h @@ -8,7 +8,7 @@ #include #include -#include +#include #define DDRC_DDR_SS_GPR0 0x3d000000 #define DDRC_IPS_BASE_ADDR_0 0x3f400000 diff --git a/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h b/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h index 9244e0a78fd..35e3ec7a987 100644 --- a/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h +++ b/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h @@ -6,6 +6,8 @@ #ifndef __FSL_SERDES_H #define __FSL_SERDES_H +#include + enum srds_prtcl { /* * Nobody will check whether the device 'NONE' has been configured, diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h index d585b5cf4b2..58013a85951 100644 --- a/arch/arm/include/asm/arch-mx5/clock.h +++ b/arch/arm/include/asm/arch-mx5/clock.h @@ -7,6 +7,8 @@ #ifndef __ASM_ARCH_CLOCK_H #define __ASM_ARCH_CLOCK_H +#include + #ifdef CONFIG_SYS_MX5_HCLK #define MXC_HCLK CONFIG_SYS_MX5_HCLK #else diff --git a/arch/arm/include/asm/arch-mx7/sys_proto.h b/arch/arm/include/asm/arch-mx7/sys_proto.h index 634736cc09c..5da0037b2c6 100644 --- a/arch/arm/include/asm/arch-mx7/sys_proto.h +++ b/arch/arm/include/asm/arch-mx7/sys_proto.h @@ -7,6 +7,8 @@ #include +struct wdog_regs; + void set_wdog_reset(struct wdog_regs *wdog); #endif /* __SYS_PROTO_IMX7_ */ diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h index ecf3b4e7428..e736772fda7 100644 --- a/arch/arm/include/asm/arch-rockchip/bootrom.h +++ b/arch/arm/include/asm/arch-rockchip/bootrom.h @@ -7,6 +7,8 @@ #ifndef _ASM_ARCH_BOOTROM_H #define _ASM_ARCH_BOOTROM_H +#include + /* * Saved Stack pointer address. * Access might be needed in some special cases. diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index f01c5aeb71c..73e5283108b 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -6,6 +6,8 @@ #ifndef _ASM_ARCH_CLOCK_H #define _ASM_ARCH_CLOCK_H +#include + struct udevice; /* define pll mode */ diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3308.h b/arch/arm/include/asm/arch-rockchip/grf_rk3308.h index a995bb950d9..f4bbc240131 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3308.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3308.h @@ -5,6 +5,8 @@ #ifndef _ASM_ARCH_GRF_rk3308_H #define _ASM_ARCH_GRF_rk3308_H +#include + struct rk3308_grf { unsigned int gpio0a_iomux; unsigned int reserved0; diff --git a/arch/arm/include/asm/arch-sunxi/pmic_bus.h b/arch/arm/include/asm/arch-sunxi/pmic_bus.h index 5ab9b2809f2..e26459fdd3b 100644 --- a/arch/arm/include/asm/arch-sunxi/pmic_bus.h +++ b/arch/arm/include/asm/arch-sunxi/pmic_bus.h @@ -8,6 +8,8 @@ #ifndef _SUNXI_PMIC_BUS_H #define _SUNXI_PMIC_BUS_H +#include + int pmic_bus_init(void); int pmic_bus_read(u8 reg, u8 *data); int pmic_bus_write(u8 reg, u8 data); diff --git a/arch/arm/include/asm/arch-sunxi/tve.h b/arch/arm/include/asm/arch-sunxi/tve.h index 46cd87e79e8..4fbb4b91c86 100644 --- a/arch/arm/include/asm/arch-sunxi/tve.h +++ b/arch/arm/include/asm/arch-sunxi/tve.h @@ -9,6 +9,8 @@ #ifndef _TVE_H #define _TVE_H +#include + enum tve_mode { tve_mode_vga, tve_mode_composite_pal, diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h index 78aeb25ac78..b922b2d30ea 100644 --- a/arch/arm/include/asm/arch-tegra/ap.h +++ b/arch/arm/include/asm/arch-tegra/ap.h @@ -4,6 +4,7 @@ * NVIDIA Corporation */ #include +#include /* Stabilization delays, in usec */ #define PLL_STABILIZATION_DELAY (300) diff --git a/arch/arm/include/asm/arch-tegra/cboot.h b/arch/arm/include/asm/arch-tegra/cboot.h index 4e1da98d1f2..d0ba83ae8bc 100644 --- a/arch/arm/include/asm/arch-tegra/cboot.h +++ b/arch/arm/include/asm/arch-tegra/cboot.h @@ -6,6 +6,8 @@ #ifndef _TEGRA_CBOOT_H_ #define _TEGRA_CBOOT_H_ +#include +#include #include #ifdef CONFIG_ARM64 diff --git a/arch/arm/include/asm/arch-tegra/gpio.h b/arch/arm/include/asm/arch-tegra/gpio.h index fe7b3a50e0d..3c1838cf137 100644 --- a/arch/arm/include/asm/arch-tegra/gpio.h +++ b/arch/arm/include/asm/arch-tegra/gpio.h @@ -6,6 +6,7 @@ #ifndef _TEGRA_GPIO_H_ #define _TEGRA_GPIO_H_ +#include #include #define TEGRA_GPIOS_PER_PORT 8 diff --git a/arch/arm/include/asm/arch-tegra/tegra_i2c.h b/arch/arm/include/asm/arch-tegra/tegra_i2c.h index afec6bbdda3..dc8db391221 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_i2c.h +++ b/arch/arm/include/asm/arch-tegra/tegra_i2c.h @@ -10,6 +10,7 @@ #include #include +#include struct udevice; diff --git a/arch/arm/include/asm/esr.h b/arch/arm/include/asm/esr.h index f19e4e726a1..99488730998 100644 --- a/arch/arm/include/asm/esr.h +++ b/arch/arm/include/asm/esr.h @@ -7,6 +7,7 @@ #ifndef __ASM_ESR_H #define __ASM_ESR_H +#include #include #include diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 452bcd1b8fd..45401d5e3c8 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -12,6 +12,7 @@ #include #include +#include /* Architecture-specific global data */ struct arch_global_data { diff --git a/arch/arm/include/asm/mach-imx/gpio.h b/arch/arm/include/asm/mach-imx/gpio.h index 1b7c9cd5249..25763526f5f 100644 --- a/arch/arm/include/asm/mach-imx/gpio.h +++ b/arch/arm/include/asm/mach-imx/gpio.h @@ -9,6 +9,8 @@ #define __ASM_ARCH_IMX_GPIO_H #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include + /* GPIO registers */ struct gpio_regs { u32 gpio_dr; /* data */ diff --git a/arch/arm/include/asm/ti-common/davinci_nand.h b/arch/arm/include/asm/ti-common/davinci_nand.h index 38a1a6ea0d7..84fe01e3b71 100644 --- a/arch/arm/include/asm/ti-common/davinci_nand.h +++ b/arch/arm/include/asm/ti-common/davinci_nand.h @@ -9,6 +9,7 @@ #ifndef _DAVINCI_NAND_H_ #define _DAVINCI_NAND_H_ +#include #include #define NAND_READ_START 0x00 diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c index 181a8ac4c27..9afd8375999 100644 --- a/arch/arm/lib/asm-offsets.c +++ b/arch/arm/lib/asm-offsets.c @@ -16,7 +16,6 @@ * Abdellatif El Khlifi */ -#include #include #include diff --git a/arch/arm/lib/bdinfo.c b/arch/arm/lib/bdinfo.c index b88b01eefdc..7c49462c8eb 100644 --- a/arch/arm/lib/bdinfo.c +++ b/arch/arm/lib/bdinfo.c @@ -6,7 +6,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c index 29020bd1c6b..2671f9a0ebf 100644 --- a/arch/arm/lib/bootm-fdt.c +++ b/arch/arm/lib/bootm-fdt.c @@ -14,7 +14,6 @@ * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) */ -#include #include #ifdef CONFIG_ARMV7_NONSEC #include diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index f30a483ed8b..192c120a7d2 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -11,7 +11,6 @@ * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) */ -#include #include #include #include diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 0893915b300..947012f2996 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c index d05314ee57f..0afd3880447 100644 --- a/arch/arm/lib/cache-pl310.c +++ b/arch/arm/lib/cache-pl310.c @@ -9,7 +9,6 @@ #include #include #include -#include struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE; diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 7a160158671..b2ae74a59f1 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -6,7 +6,7 @@ /* for now: just dummy functions to satisfy the linker */ -#include +#include #include #include #include diff --git a/arch/arm/lib/cmd_boot.c b/arch/arm/lib/cmd_boot.c index c905ecc4bd9..5df5bc305a2 100644 --- a/arch/arm/lib/cmd_boot.c +++ b/arch/arm/lib/cmd_boot.c @@ -17,7 +17,6 @@ * Copyright 2015 Konsulko Group, Matt Porter */ -#include #include /* diff --git a/arch/arm/lib/eabi_compat.c b/arch/arm/lib/eabi_compat.c index f7029918d4f..0a96ba1355f 100644 --- a/arch/arm/lib/eabi_compat.c +++ b/arch/arm/lib/eabi_compat.c @@ -5,7 +5,9 @@ * (C) Copyright 2009 Wolfgang Denk */ -#include +#include +#include +#include int raise (int signum) { diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c index f4bbd21da91..2cc0a32f9d4 100644 --- a/arch/arm/lib/gic-v3-its.c +++ b/arch/arm/lib/gic-v3-its.c @@ -2,7 +2,6 @@ /* * Copyright 2019 Broadcom. */ -#include #include #include #include diff --git a/arch/arm/lib/image.c b/arch/arm/lib/image.c index e394c1ad909..1f672eee2c8 100644 --- a/arch/arm/lib/image.c +++ b/arch/arm/lib/image.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c index 9961472f69f..333a5026a46 100644 --- a/arch/arm/lib/interrupts.c +++ b/arch/arm/lib/interrupts.c @@ -18,7 +18,6 @@ * Philippe Robin, ARM Ltd. */ -#include #include #include #include diff --git a/arch/arm/lib/interrupts_64.c b/arch/arm/lib/interrupts_64.c index 125dc0bb390..b3024ba514e 100644 --- a/arch/arm/lib/interrupts_64.c +++ b/arch/arm/lib/interrupts_64.c @@ -4,7 +4,6 @@ * David Feng */ -#include #include #include #include diff --git a/arch/arm/lib/interrupts_m.c b/arch/arm/lib/interrupts_m.c index 277854aa878..b977961bde8 100644 --- a/arch/arm/lib/interrupts_m.c +++ b/arch/arm/lib/interrupts_m.c @@ -4,9 +4,10 @@ * Kamil Lulko, */ -#include +#include #include #include +#include /* * Upon exception entry ARMv7-M processors automatically save stack diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c index 903b3357048..be800a3bc9e 100644 --- a/arch/arm/lib/psci-dt.c +++ b/arch/arm/lib/psci-dt.c @@ -3,7 +3,6 @@ * Copyright 2016 NXP Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c index 3e051e36f12..c9796a4435c 100644 --- a/arch/arm/lib/reset.c +++ b/arch/arm/lib/reset.c @@ -20,7 +20,6 @@ * (C) Copyright 2004 Texas Insturments */ -#include #include #include #include diff --git a/arch/arm/lib/save_prev_bl_data.c b/arch/arm/lib/save_prev_bl_data.c index b286bac9bf0..4357acaef6c 100644 --- a/arch/arm/lib/save_prev_bl_data.c +++ b/arch/arm/lib/save_prev_bl_data.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c index b13897495da..c43a63f1819 100644 --- a/arch/arm/lib/spl.c +++ b/arch/arm/lib/spl.c @@ -7,7 +7,6 @@ * Tom Rini */ -#include #include #include #include diff --git a/arch/arm/lib/stack.c b/arch/arm/lib/stack.c index 656084c7e51..ea1b937add7 100644 --- a/arch/arm/lib/stack.c +++ b/arch/arm/lib/stack.c @@ -10,7 +10,6 @@ * Sysgo Real-Time Solutions, GmbH * Marius Groeger */ -#include #include #include #include diff --git a/arch/arm/lib/zimage.c b/arch/arm/lib/zimage.c index 45e9c4506a9..51287251b3f 100644 --- a/arch/arm/lib/zimage.c +++ b/arch/arm/lib/zimage.c @@ -6,7 +6,6 @@ * bootz code: * Copyright (C) 2012 Marek Vasut */ -#include #include #define LINUX_ARM_ZIMAGE_MAGIC 0x016f2818 diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c index 7a6151a9722..8bace3005eb 100644 --- a/arch/arm/mach-apple/board.c +++ b/arch/arm/mach-apple/board.c @@ -3,7 +3,6 @@ * (C) Copyright 2021 Mark Kettenis */ -#include #include #include #include diff --git a/arch/arm/mach-apple/rtkit.c b/arch/arm/mach-apple/rtkit.c index a550b553b66..b8f4771e5e7 100644 --- a/arch/arm/mach-apple/rtkit.c +++ b/arch/arm/mach-apple/rtkit.c @@ -4,13 +4,14 @@ * (C) Copyright 2021 Copyright The Asahi Linux Contributors */ -#include #include #include #include #include #include +#include +#include #define APPLE_RTKIT_EP_MGMT 0 #define APPLE_RTKIT_EP_CRASHLOG 1 diff --git a/arch/arm/mach-aspeed/ast2500/board_common.c b/arch/arm/mach-aspeed/ast2500/board_common.c index bae10271844..531c2ad1562 100644 --- a/arch/arm/mach-aspeed/ast2500/board_common.c +++ b/arch/arm/mach-aspeed/ast2500/board_common.c @@ -2,7 +2,7 @@ /* * Copyright (c) 2016 Google, Inc */ -#include +#include #include #include #include diff --git a/arch/arm/mach-aspeed/ast2500/clk_ast2500.c b/arch/arm/mach-aspeed/ast2500/clk_ast2500.c index 02bd3f67c96..50d7f99b264 100644 --- a/arch/arm/mach-aspeed/ast2500/clk_ast2500.c +++ b/arch/arm/mach-aspeed/ast2500/clk_ast2500.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Google, Inc */ -#include #include #include #include diff --git a/arch/arm/mach-aspeed/ast2600/board_common.c b/arch/arm/mach-aspeed/ast2600/board_common.c index dc6cdc35d15..4c0b705ea88 100644 --- a/arch/arm/mach-aspeed/ast2600/board_common.c +++ b/arch/arm/mach-aspeed/ast2600/board_common.c @@ -2,7 +2,7 @@ /* * Copyright (c) Aspeed Technology Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-aspeed/ast2600/spl.c b/arch/arm/mach-aspeed/ast2600/spl.c index 0952e73a457..05390c16f3a 100644 --- a/arch/arm/mach-aspeed/ast2600/spl.c +++ b/arch/arm/mach-aspeed/ast2600/spl.c @@ -2,7 +2,6 @@ /* * Copyright (c) Aspeed Technology Inc. */ -#include #include #include #include diff --git a/arch/arm/mach-aspeed/ast_wdt.c b/arch/arm/mach-aspeed/ast_wdt.c index 5bc442ef33c..c420940d1cb 100644 --- a/arch/arm/mach-aspeed/ast_wdt.c +++ b/arch/arm/mach-aspeed/ast_wdt.c @@ -3,7 +3,6 @@ * (C) Copyright 2016 Google, Inc */ -#include #include #include #include diff --git a/arch/arm/mach-at91/arm920t/at91rm9200_devices.c b/arch/arm/mach-at91/arm920t/at91rm9200_devices.c index c849885bc2b..459edadb587 100644 --- a/arch/arm/mach-at91/arm920t/at91rm9200_devices.c +++ b/arch/arm/mach-at91/arm920t/at91rm9200_devices.c @@ -10,7 +10,6 @@ * Lead Tech Design */ -#include #include #include #include diff --git a/arch/arm/mach-at91/arm920t/clock.c b/arch/arm/mach-at91/arm920t/clock.c index 09ac66d619d..ac55a61be64 100644 --- a/arch/arm/mach-at91/arm920t/clock.c +++ b/arch/arm/mach-at91/arm920t/clock.c @@ -7,7 +7,7 @@ * Copyright (C) 2005 Ivan Kokshaysky * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD */ -#include +#include #include #include #include diff --git a/arch/arm/mach-at91/arm920t/cpu.c b/arch/arm/mach-at91/arm920t/cpu.c index 9bf03fd68ec..579e76b339d 100644 --- a/arch/arm/mach-at91/arm920t/cpu.c +++ b/arch/arm/mach-at91/arm920t/cpu.c @@ -10,7 +10,7 @@ * Jean-Christophe PLAGNIOL-VILLARD */ -#include +#include #include #include #include diff --git a/arch/arm/mach-at91/arm920t/reset.c b/arch/arm/mach-at91/arm920t/reset.c index 91e375146ad..7582cef417f 100644 --- a/arch/arm/mach-at91/arm920t/reset.c +++ b/arch/arm/mach-at91/arm920t/reset.c @@ -13,7 +13,6 @@ * Alex Zuepke */ -#include #include #include #include diff --git a/arch/arm/mach-at91/arm920t/timer.c b/arch/arm/mach-at91/arm920t/timer.c index 8ef5764e315..f7b4116344c 100644 --- a/arch/arm/mach-at91/arm920t/timer.c +++ b/arch/arm/mach-at91/arm920t/timer.c @@ -13,7 +13,7 @@ * Alex Zuepke */ -#include +#include #include #include #include diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c index c10571fa28a..201c99ade4e 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c @@ -5,7 +5,6 @@ * Lead Tech Design */ -#include #include #include #include diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c index 0c2b9f2ecc9..b8d209cbec8 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c @@ -5,7 +5,6 @@ * Lead Tech Design */ -#include #include #include #include diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c index 3b8a4623866..1749662dae9 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c @@ -9,7 +9,6 @@ * esd electronic system design gmbh */ -#include #include #include #include diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c index d517810c991..4c481484c3d 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c @@ -5,7 +5,6 @@ * Lead Tech Design */ -#include #include #include #include diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c index 9f98ce7a45c..4dc6e51aba8 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c @@ -4,7 +4,6 @@ * Josh Wu */ -#include #include #include #include diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c index b4002eb7504..4f5bafb8c2e 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c @@ -5,7 +5,6 @@ * Lead Tech Design */ -#include #include #include #include diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c index f44760bed31..40c8a58b563 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c @@ -3,7 +3,6 @@ * Copyright (C) 2012 Atmel Corporation */ -#include #include #include #include diff --git a/arch/arm/mach-at91/arm926ejs/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c index 013daf43b74..241de6a5378 100644 --- a/arch/arm/mach-at91/arm926ejs/clock.c +++ b/arch/arm/mach-at91/arm926ejs/clock.c @@ -7,7 +7,8 @@ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD */ -#include +#include +#include #include #include #include diff --git a/arch/arm/mach-at91/arm926ejs/cpu.c b/arch/arm/mach-at91/arm926ejs/cpu.c index 5e84b0a40e1..e476cd5bcf3 100644 --- a/arch/arm/mach-at91/arm926ejs/cpu.c +++ b/arch/arm/mach-at91/arm926ejs/cpu.c @@ -6,7 +6,7 @@ * Jean-Christophe PLAGNIOL-VILLARD */ -#include +#include #include #include #include diff --git a/arch/arm/mach-at91/arm926ejs/eflash.c b/arch/arm/mach-at91/arm926ejs/eflash.c index aade13cc014..bb66700566e 100644 --- a/arch/arm/mach-at91/arm926ejs/eflash.c +++ b/arch/arm/mach-at91/arm926ejs/eflash.c @@ -42,7 +42,6 @@ * someone puts a jffs2 into them) * do a read-modify-write for partially programmed pages */ -#include #include #include #include diff --git a/arch/arm/mach-at91/arm926ejs/reset.c b/arch/arm/mach-at91/arm926ejs/reset.c index 6acbfa33011..01b2663f96c 100644 --- a/arch/arm/mach-at91/arm926ejs/reset.c +++ b/arch/arm/mach-at91/arm926ejs/reset.c @@ -5,7 +5,6 @@ * Lead Tech Design */ -#include #include #include #include diff --git a/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c b/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c index e3d3dd880ca..97c572deaaf 100644 --- a/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c +++ b/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries */ -#include #include #include #include diff --git a/arch/arm/mach-at91/arm926ejs/timer.c b/arch/arm/mach-at91/arm926ejs/timer.c index a8cf0e4bd79..137a5e5b8fd 100644 --- a/arch/arm/mach-at91/arm926ejs/timer.c +++ b/arch/arm/mach-at91/arm926ejs/timer.c @@ -5,7 +5,6 @@ * Lead Tech Design */ -#include #include #include #include diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c index 6bfa02d1d0a..5357b4cffc2 100644 --- a/arch/arm/mach-at91/armv7/clock.c +++ b/arch/arm/mach-at91/armv7/clock.c @@ -9,7 +9,7 @@ * Copyright (C) 2015 Wenyou Yang */ -#include +#include #include #include #include diff --git a/arch/arm/mach-at91/armv7/cpu.c b/arch/arm/mach-at91/armv7/cpu.c index 5ea7e2609f5..f4b2f4f351c 100644 --- a/arch/arm/mach-at91/armv7/cpu.c +++ b/arch/arm/mach-at91/armv7/cpu.c @@ -8,7 +8,7 @@ * Bo Shen */ -#include +#include #include #include #include diff --git a/arch/arm/mach-at91/armv7/sama5d2_devices.c b/arch/arm/mach-at91/armv7/sama5d2_devices.c index edc20574c31..469c2211766 100644 --- a/arch/arm/mach-at91/armv7/sama5d2_devices.c +++ b/arch/arm/mach-at91/armv7/sama5d2_devices.c @@ -4,7 +4,6 @@ * Wenyou Yang */ -#include #include #include #include diff --git a/arch/arm/mach-at91/armv7/sama5d3_devices.c b/arch/arm/mach-at91/armv7/sama5d3_devices.c index 04b700a94d7..67b63208eda 100644 --- a/arch/arm/mach-at91/armv7/sama5d3_devices.c +++ b/arch/arm/mach-at91/armv7/sama5d3_devices.c @@ -4,7 +4,6 @@ * Bo Shen */ -#include #include #include #include diff --git a/arch/arm/mach-at91/armv7/sama5d4_devices.c b/arch/arm/mach-at91/armv7/sama5d4_devices.c index e68ae994078..76fff9cd466 100644 --- a/arch/arm/mach-at91/armv7/sama5d4_devices.c +++ b/arch/arm/mach-at91/armv7/sama5d4_devices.c @@ -4,7 +4,6 @@ * Bo Shen */ -#include #include #include #include diff --git a/arch/arm/mach-at91/armv7/timer.c b/arch/arm/mach-at91/armv7/timer.c index 1f54c5dcad9..bfdb75ce39a 100644 --- a/arch/arm/mach-at91/armv7/timer.c +++ b/arch/arm/mach-at91/armv7/timer.c @@ -8,7 +8,6 @@ * Bo Shen */ -#include #include #include #include diff --git a/arch/arm/mach-at91/atmel_sfr.c b/arch/arm/mach-at91/atmel_sfr.c index 62108d2bd0a..019ef930022 100644 --- a/arch/arm/mach-at91/atmel_sfr.c +++ b/arch/arm/mach-at91/atmel_sfr.c @@ -4,7 +4,7 @@ * Wenyou Yang */ -#include +#include #include #include #include diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index 8344daeb39a..442b822fe77 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -4,8 +4,8 @@ * Wenyou Yang */ -#include #include +#include #include #include #include diff --git a/arch/arm/mach-at91/include/mach/at91_common.h b/arch/arm/mach-at91/include/mach/at91_common.h index f7b411cf7df..683e539b1b3 100644 --- a/arch/arm/mach-at91/include/mach/at91_common.h +++ b/arch/arm/mach-at91/include/mach/at91_common.h @@ -8,6 +8,8 @@ #ifndef AT91_COMMON_H #define AT91_COMMON_H +#include + void at91_can_hw_init(void); void at91_gmac_hw_init(void); void at91_macb_hw_init(void); diff --git a/arch/arm/mach-at91/matrix.c b/arch/arm/mach-at91/matrix.c index 2fa8493a0bd..3bef5648d4a 100644 --- a/arch/arm/mach-at91/matrix.c +++ b/arch/arm/mach-at91/matrix.c @@ -4,7 +4,6 @@ * Wenyou Yang */ -#include #include #include #include diff --git a/arch/arm/mach-at91/mpddrc.c b/arch/arm/mach-at91/mpddrc.c index 5422c05456e..ac6a719d9c0 100644 --- a/arch/arm/mach-at91/mpddrc.c +++ b/arch/arm/mach-at91/mpddrc.c @@ -7,7 +7,6 @@ * Wenyou Yang */ -#include #include #include #include diff --git a/arch/arm/mach-at91/phy.c b/arch/arm/mach-at91/phy.c index f4484a77c7d..ec38f5bc931 100644 --- a/arch/arm/mach-at91/phy.c +++ b/arch/arm/mach-at91/phy.c @@ -11,7 +11,7 @@ * Copyright (C) 2013 DENX Software Engineering, hs@denx.de */ -#include +#include #include #include #include diff --git a/arch/arm/mach-at91/sdram.c b/arch/arm/mach-at91/sdram.c index 6638aa82bb6..be3e91c7dba 100644 --- a/arch/arm/mach-at91/sdram.c +++ b/arch/arm/mach-at91/sdram.c @@ -9,7 +9,6 @@ * Lead Tech Design */ -#include #include #include #include diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c index 8d537998c98..5feb8f73551 100644 --- a/arch/arm/mach-at91/spl.c +++ b/arch/arm/mach-at91/spl.c @@ -4,7 +4,6 @@ * Bo Shen */ -#include #include #include #include diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c index dfba9f730c1..cde1700a283 100644 --- a/arch/arm/mach-at91/spl_at91.c +++ b/arch/arm/mach-at91/spl_at91.c @@ -8,7 +8,7 @@ * Bo Shen */ -#include +#include #include #include #include diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c index a30c4f6c075..62a7df8a195 100644 --- a/arch/arm/mach-at91/spl_atmel.c +++ b/arch/arm/mach-at91/spl_atmel.c @@ -4,7 +4,7 @@ * Bo Shen */ -#include +#include #include #include #include diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index 016bc1eb412..1b459707bc6 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -6,7 +6,6 @@ * project. */ -#include #include #include #include diff --git a/arch/arm/mach-bcm283x/mbox.c b/arch/arm/mach-bcm283x/mbox.c index da9faafe1dd..c7cbfa72ffc 100644 --- a/arch/arm/mach-bcm283x/mbox.c +++ b/arch/arm/mach-bcm283x/mbox.c @@ -3,9 +3,9 @@ * (C) Copyright 2012 Stephen Warren */ -#include #include #include +#include #include #include #include diff --git a/arch/arm/mach-bcm283x/msg.c b/arch/arm/mach-bcm283x/msg.c index 2188b38d84b..4993c0bdb81 100644 --- a/arch/arm/mach-bcm283x/msg.c +++ b/arch/arm/mach-bcm283x/msg.c @@ -3,7 +3,6 @@ * (C) Copyright 2012 Stephen Warren */ -#include #include #include #include diff --git a/arch/arm/mach-bcm283x/reset.c b/arch/arm/mach-bcm283x/reset.c index f13ac0c6375..9199234917f 100644 --- a/arch/arm/mach-bcm283x/reset.c +++ b/arch/arm/mach-bcm283x/reset.c @@ -6,7 +6,7 @@ * project. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-bcmbca/bcm4908/mmu_table.c b/arch/arm/mach-bcmbca/bcm4908/mmu_table.c index 5ab04083cc6..ca403bae991 100644 --- a/arch/arm/mach-bcmbca/bcm4908/mmu_table.c +++ b/arch/arm/mach-bcmbca/bcm4908/mmu_table.c @@ -2,7 +2,6 @@ /* * Copyright 2022 Broadcom Ltd. */ -#include #include #include diff --git a/arch/arm/mach-bcmbca/bcm4912/mmu_table.c b/arch/arm/mach-bcmbca/bcm4912/mmu_table.c index 52a53a2c76d..b11effe0667 100644 --- a/arch/arm/mach-bcmbca/bcm4912/mmu_table.c +++ b/arch/arm/mach-bcmbca/bcm4912/mmu_table.c @@ -2,7 +2,6 @@ /* * Copyright 2022 Broadcom Ltd. */ -#include #include #include diff --git a/arch/arm/mach-bcmbca/bcm63146/mmu_table.c b/arch/arm/mach-bcmbca/bcm63146/mmu_table.c index c6b7a54fbdf..a883e74ac00 100644 --- a/arch/arm/mach-bcmbca/bcm63146/mmu_table.c +++ b/arch/arm/mach-bcmbca/bcm63146/mmu_table.c @@ -2,7 +2,6 @@ /* * Copyright 2022 Broadcom Ltd. */ -#include #include #include diff --git a/arch/arm/mach-bcmbca/bcm63158/mmu_table.c b/arch/arm/mach-bcmbca/bcm63158/mmu_table.c index fe7efb30e22..eb3cc3e5aec 100644 --- a/arch/arm/mach-bcmbca/bcm63158/mmu_table.c +++ b/arch/arm/mach-bcmbca/bcm63158/mmu_table.c @@ -2,7 +2,6 @@ /* * Copyright 2022 Broadcom Ltd. */ -#include #include #include diff --git a/arch/arm/mach-bcmbca/bcm6813/mmu_table.c b/arch/arm/mach-bcmbca/bcm6813/mmu_table.c index eb736bf7d50..458624e87aa 100644 --- a/arch/arm/mach-bcmbca/bcm6813/mmu_table.c +++ b/arch/arm/mach-bcmbca/bcm6813/mmu_table.c @@ -2,7 +2,6 @@ /* * Copyright 2022 Broadcom Ltd. */ -#include #include #include diff --git a/arch/arm/mach-bcmbca/bcm6856/mmu_table.c b/arch/arm/mach-bcmbca/bcm6856/mmu_table.c index 8e53b4929eb..83c07727573 100644 --- a/arch/arm/mach-bcmbca/bcm6856/mmu_table.c +++ b/arch/arm/mach-bcmbca/bcm6856/mmu_table.c @@ -2,7 +2,6 @@ /* * Copyright 2022 Broadcom Ltd. */ -#include #include #include diff --git a/arch/arm/mach-bcmbca/bcm6858/mmu_table.c b/arch/arm/mach-bcmbca/bcm6858/mmu_table.c index 898291075f5..82aba326dcb 100644 --- a/arch/arm/mach-bcmbca/bcm6858/mmu_table.c +++ b/arch/arm/mach-bcmbca/bcm6858/mmu_table.c @@ -2,7 +2,6 @@ /* * Copyright 2022 Broadcom Ltd. */ -#include #include #include diff --git a/arch/arm/mach-davinci/cpu.c b/arch/arm/mach-davinci/cpu.c index dae60262f5b..7c0a2638977 100644 --- a/arch/arm/mach-davinci/cpu.c +++ b/arch/arm/mach-davinci/cpu.c @@ -4,7 +4,7 @@ * Copyright (C) 2009 David Brownell */ -#include +#include #include #include #include diff --git a/arch/arm/mach-davinci/da850_lowlevel.c b/arch/arm/mach-davinci/da850_lowlevel.c index 08c8f592524..936b5e11667 100644 --- a/arch/arm/mach-davinci/da850_lowlevel.c +++ b/arch/arm/mach-davinci/da850_lowlevel.c @@ -5,7 +5,7 @@ * Copyright (C) 2011 * Heiko Schocher, DENX Software Engineering, hs@denx.de. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-davinci/da850_pinmux.c b/arch/arm/mach-davinci/da850_pinmux.c index f2536c8dd6d..4ee3cd0d5b3 100644 --- a/arch/arm/mach-davinci/da850_pinmux.c +++ b/arch/arm/mach-davinci/da850_pinmux.c @@ -5,7 +5,6 @@ * Copyright (C) 2011 OMICRON electronics GmbH */ -#include #include #include #include diff --git a/arch/arm/mach-davinci/include/mach/davinci_misc.h b/arch/arm/mach-davinci/include/mach/davinci_misc.h index 1133a23bdee..0d0ad1e593e 100644 --- a/arch/arm/mach-davinci/include/mach/davinci_misc.h +++ b/arch/arm/mach-davinci/include/mach/davinci_misc.h @@ -6,6 +6,7 @@ #ifndef __MISC_H #define __MISC_H +#include #include /* pin muxer definitions */ diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c index cfad28c43d0..6c97e5810cd 100644 --- a/arch/arm/mach-davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c @@ -8,7 +8,7 @@ * Copyright (C) 2004 Texas Instruments. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-davinci/pinmux.c b/arch/arm/mach-davinci/pinmux.c index 7904257b4a4..5ecb434b03b 100644 --- a/arch/arm/mach-davinci/pinmux.c +++ b/arch/arm/mach-davinci/pinmux.c @@ -8,7 +8,6 @@ * Copyright (C) 2004 Texas Instruments. */ -#include #include #include #include diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c index dae10aa03bb..90b817860a6 100644 --- a/arch/arm/mach-davinci/psc.c +++ b/arch/arm/mach-davinci/psc.c @@ -7,7 +7,6 @@ * Copyright (C) 2004 Texas Instruments. */ -#include #include #include diff --git a/arch/arm/mach-davinci/reset.c b/arch/arm/mach-davinci/reset.c index 0d59eb6e3ce..e3e2c56a676 100644 --- a/arch/arm/mach-davinci/reset.c +++ b/arch/arm/mach-davinci/reset.c @@ -6,7 +6,6 @@ * Copyright (C) 2007 Sergey Kubushyn */ -#include #include #include #include diff --git a/arch/arm/mach-davinci/spl.c b/arch/arm/mach-davinci/spl.c index 5f5b9ebbf97..8c6cf9c2192 100644 --- a/arch/arm/mach-davinci/spl.c +++ b/arch/arm/mach-davinci/spl.c @@ -3,12 +3,10 @@ * Copyright (C) 2011 * Heiko Schocher, DENX Software Engineering, hs@denx.de. */ -#include #include #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-davinci/timer.c b/arch/arm/mach-davinci/timer.c index 83c190b620e..f2990f71877 100644 --- a/arch/arm/mach-davinci/timer.c +++ b/arch/arm/mach-davinci/timer.c @@ -20,7 +20,7 @@ * Copyright (C) 2007 Sergey Kubushyn */ -#include +#include #include #include #include diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c index f91f2ee862d..ee71b95237d 100644 --- a/arch/arm/mach-exynos/clock.c +++ b/arch/arm/mach-exynos/clock.c @@ -4,9 +4,10 @@ * Minkyu Kang */ -#include #include #include +#include +#include #include #include #include diff --git a/arch/arm/mach-exynos/clock_init_exynos4.c b/arch/arm/mach-exynos/clock_init_exynos4.c index 584e4bac09f..95ed1956a07 100644 --- a/arch/arm/mach-exynos/clock_init_exynos4.c +++ b/arch/arm/mach-exynos/clock_init_exynos4.c @@ -23,7 +23,6 @@ * MA 02111-1307 USA */ -#include #include #include #include diff --git a/arch/arm/mach-exynos/clock_init_exynos5.c b/arch/arm/mach-exynos/clock_init_exynos5.c index 1cb8d391e7c..232a2482dc6 100644 --- a/arch/arm/mach-exynos/clock_init_exynos5.c +++ b/arch/arm/mach-exynos/clock_init_exynos5.c @@ -5,7 +5,6 @@ * Copyright (C) 2012 Samsung Electronics */ -#include #include #include #include diff --git a/arch/arm/mach-exynos/common_setup.h b/arch/arm/mach-exynos/common_setup.h index d7f02231fdf..4f56160ee50 100644 --- a/arch/arm/mach-exynos/common_setup.h +++ b/arch/arm/mach-exynos/common_setup.h @@ -23,6 +23,8 @@ * MA 02111-1307 USA */ +#include +#include #include #define DMC_OFFSET 0x10000 diff --git a/arch/arm/mach-exynos/dmc_common.c b/arch/arm/mach-exynos/dmc_common.c index 44923dd5520..a96ded443b9 100644 --- a/arch/arm/mach-exynos/dmc_common.c +++ b/arch/arm/mach-exynos/dmc_common.c @@ -5,7 +5,7 @@ * Copyright (C) 2012 Samsung Electronics */ -#include +#include #include #include "clock_init.h" diff --git a/arch/arm/mach-exynos/dmc_init_ddr3.c b/arch/arm/mach-exynos/dmc_init_ddr3.c index cad8ccc5315..193de4c3a59 100644 --- a/arch/arm/mach-exynos/dmc_init_ddr3.c +++ b/arch/arm/mach-exynos/dmc_init_ddr3.c @@ -5,7 +5,6 @@ * Copyright (C) 2012 Samsung Electronics */ -#include #include #include #include diff --git a/arch/arm/mach-exynos/exynos5_setup.h b/arch/arm/mach-exynos/exynos5_setup.h index e9874a8c1b2..4e508edba0c 100644 --- a/arch/arm/mach-exynos/exynos5_setup.h +++ b/arch/arm/mach-exynos/exynos5_setup.h @@ -8,6 +8,7 @@ #ifndef _SMDK5250_SETUP_H #define _SMDK5250_SETUP_H +#include #include #define NOT_AVAILABLE 0 diff --git a/arch/arm/mach-exynos/include/mach/power.h b/arch/arm/mach-exynos/include/mach/power.h index a3d8974dcb5..757e1586bde 100644 --- a/arch/arm/mach-exynos/include/mach/power.h +++ b/arch/arm/mach-exynos/include/mach/power.h @@ -8,6 +8,8 @@ #define __ASM_ARM_ARCH_POWER_H_ #ifndef __ASSEMBLY__ +#include + struct exynos4_power { unsigned int om_stat; unsigned char res1[0x8]; diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c index c57b8aee798..0967ab995a9 100644 --- a/arch/arm/mach-exynos/lowlevel_init.c +++ b/arch/arm/mach-exynos/lowlevel_init.c @@ -23,7 +23,6 @@ * MA 02111-1307 USA */ -#include #include #include #include diff --git a/arch/arm/mach-exynos/mmu-arm64.c b/arch/arm/mach-exynos/mmu-arm64.c index 30e522804fb..e2f32547adf 100644 --- a/arch/arm/mach-exynos/mmu-arm64.c +++ b/arch/arm/mach-exynos/mmu-arm64.c @@ -4,7 +4,6 @@ * Thomas Abraham */ -#include #include #include diff --git a/arch/arm/mach-exynos/pinmux.c b/arch/arm/mach-exynos/pinmux.c index ad3fbf2da7a..4061dd4aafa 100644 --- a/arch/arm/mach-exynos/pinmux.c +++ b/arch/arm/mach-exynos/pinmux.c @@ -4,7 +4,6 @@ * Abhilash Kesavan */ -#include #include #include #include diff --git a/arch/arm/mach-exynos/power.c b/arch/arm/mach-exynos/power.c index f2a6c00dd62..599d3ccff60 100644 --- a/arch/arm/mach-exynos/power.c +++ b/arch/arm/mach-exynos/power.c @@ -4,7 +4,7 @@ * Donghwa Lee */ -#include +#include #include #include diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c index aff2b5e1b6e..be18f181a7a 100644 --- a/arch/arm/mach-exynos/soc.c +++ b/arch/arm/mach-exynos/soc.c @@ -4,7 +4,6 @@ * Minkyu Kang */ -#include #include #include #include diff --git a/arch/arm/mach-exynos/spl_boot.c b/arch/arm/mach-exynos/spl_boot.c index 553dac75b61..bd5a06447b9 100644 --- a/arch/arm/mach-exynos/spl_boot.c +++ b/arch/arm/mach-exynos/spl_boot.c @@ -3,7 +3,6 @@ * Copyright (C) 2012 Samsung Electronics */ -#include #include #include #include diff --git a/arch/arm/mach-exynos/system.c b/arch/arm/mach-exynos/system.c index 12d0d8fd34a..f5090613c0d 100644 --- a/arch/arm/mach-exynos/system.c +++ b/arch/arm/mach-exynos/system.c @@ -4,7 +4,7 @@ * Donghwa Lee */ -#include +#include #include #include diff --git a/arch/arm/mach-exynos/tzpc.c b/arch/arm/mach-exynos/tzpc.c index abe8e7f4589..320a0cf3513 100644 --- a/arch/arm/mach-exynos/tzpc.c +++ b/arch/arm/mach-exynos/tzpc.c @@ -5,7 +5,7 @@ * Copyright (C) 2012 Samsung Electronics */ -#include +#include #include #include diff --git a/arch/arm/mach-highbank/timer.c b/arch/arm/mach-highbank/timer.c index 2423a0e3785..32ec6f0ac0e 100644 --- a/arch/arm/mach-highbank/timer.c +++ b/arch/arm/mach-highbank/timer.c @@ -5,7 +5,6 @@ * Based on arm926ejs/mx27/timer.c */ -#include #include #include #include diff --git a/arch/arm/mach-histb/board_common.c b/arch/arm/mach-histb/board_common.c index a26c2066e02..84d02c9aca2 100644 --- a/arch/arm/mach-histb/board_common.c +++ b/arch/arm/mach-histb/board_common.c @@ -5,7 +5,6 @@ * (C) Copyright 2023 Yang Xiwen */ -#include #include #include #include diff --git a/arch/arm/mach-histb/sysmap-histb.c b/arch/arm/mach-histb/sysmap-histb.c index 83a2bb94179..76414558379 100644 --- a/arch/arm/mach-histb/sysmap-histb.c +++ b/arch/arm/mach-histb/sysmap-histb.c @@ -5,7 +5,6 @@ * (C) Copyright 2023 Yang Xiwen */ -#include #include static struct mm_region histb_mem_map[] = { diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c index ab9b621a2a6..b368db49fce 100644 --- a/arch/arm/mach-imx/cache.c +++ b/arch/arm/mach-imx/cache.c @@ -3,7 +3,7 @@ * Copyright 2015 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/cmd_bmode.c b/arch/arm/mach-imx/cmd_bmode.c index 5b2f4686230..c20e80725f8 100644 --- a/arch/arm/mach-imx/cmd_bmode.c +++ b/arch/arm/mach-imx/cmd_bmode.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2012 Boundary Devices Inc. */ -#include #include #include #include diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c index 2f389dbe8df..c7962ead2d5 100644 --- a/arch/arm/mach-imx/cmd_dek.c +++ b/arch/arm/mach-imx/cmd_dek.c @@ -6,7 +6,7 @@ * Command for encapsulating DEK blob */ -#include +#include #include #include #include @@ -17,6 +17,7 @@ #include #include #include +#include #ifdef CONFIG_IMX_SECO_DEK_ENCAP #include #include diff --git a/arch/arm/mach-imx/cmd_hdmidet.c b/arch/arm/mach-imx/cmd_hdmidet.c index e2571adfb00..8104ab26b08 100644 --- a/arch/arm/mach-imx/cmd_hdmidet.c +++ b/arch/arm/mach-imx/cmd_hdmidet.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2012 Boundary Devices Inc. */ -#include #include #include #include diff --git a/arch/arm/mach-imx/cmd_mfgprot.c b/arch/arm/mach-imx/cmd_mfgprot.c index 9576b48dde3..9925c992268 100644 --- a/arch/arm/mach-imx/cmd_mfgprot.c +++ b/arch/arm/mach-imx/cmd_mfgprot.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/cmd_nandbcb.c b/arch/arm/mach-imx/cmd_nandbcb.c index 70a213a49dd..c2e452b6927 100644 --- a/arch/arm/mach-imx/cmd_nandbcb.c +++ b/arch/arm/mach-imx/cmd_nandbcb.c @@ -11,7 +11,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include #include #include #include diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 488638c9058..ceee31eecd7 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -7,7 +7,6 @@ */ #include -#include #include #include #include diff --git a/arch/arm/mach-imx/ddrmc-vf610-calibration.c b/arch/arm/mach-imx/ddrmc-vf610-calibration.c index 7d787d04598..2cf684322ea 100644 --- a/arch/arm/mach-imx/ddrmc-vf610-calibration.c +++ b/arch/arm/mach-imx/ddrmc-vf610-calibration.c @@ -7,7 +7,6 @@ * */ /* #define DEBUG */ -#include #include #include #include diff --git a/arch/arm/mach-imx/ddrmc-vf610.c b/arch/arm/mach-imx/ddrmc-vf610.c index 7895ee66f8a..e449fa6f552 100644 --- a/arch/arm/mach-imx/ddrmc-vf610.c +++ b/arch/arm/mach-imx/ddrmc-vf610.c @@ -6,7 +6,6 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c index d02316ed6cb..c13d9f0e00e 100644 --- a/arch/arm/mach-imx/ele_ahab.c +++ b/arch/arm/mach-imx/ele_ahab.c @@ -3,7 +3,6 @@ * Copyright 2022 NXP */ -#include #include #include #include diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index 27e053ef701..85d90686f68 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -3,7 +3,6 @@ * Copyright (C) 2010-2015 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/arm/mach-imx/i2c-mxv7.c b/arch/arm/mach-imx/i2c-mxv7.c index a5866cf9f70..256db150818 100644 --- a/arch/arm/mach-imx/i2c-mxv7.c +++ b/arch/arm/mach-imx/i2c-mxv7.c @@ -2,8 +2,8 @@ /* * Copyright (C) 2012 Boundary Devices Inc. */ -#include #include +#include #include #include #include diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c index 35da0ae0425..e2388e3fef8 100644 --- a/arch/arm/mach-imx/image-container.c +++ b/arch/arm/mach-imx/image-container.c @@ -3,7 +3,7 @@ * Copyright 2019 NXP */ -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index 1c072f6af11..ed44df394b1 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -3,7 +3,6 @@ * Copyright 2018-2019, 2022 NXP */ -#include #include #include #include diff --git a/arch/arm/mach-imx/imx8/clock.c b/arch/arm/mach-imx/imx8/clock.c index 9941b57b4be..4e49b5bf375 100644 --- a/arch/arm/mach-imx/imx8/clock.c +++ b/arch/arm/mach-imx/imx8/clock.c @@ -3,7 +3,6 @@ * Copyright 2018 NXP */ -#include #include #include #include diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 6e643188f40..627baa1d83f 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -3,7 +3,6 @@ * Copyright 2018, 2021 NXP */ -#include #include #include #include diff --git a/arch/arm/mach-imx/imx8/fdt.c b/arch/arm/mach-imx/imx8/fdt.c index c2bed3e0c1f..6d0585f5cc6 100644 --- a/arch/arm/mach-imx/imx8/fdt.c +++ b/arch/arm/mach-imx/imx8/fdt.c @@ -3,7 +3,6 @@ * Copyright 2019 NXP */ -#include #include #include #include diff --git a/arch/arm/mach-imx/imx8/iomux.c b/arch/arm/mach-imx/imx8/iomux.c index e4f7651bd1d..3e27d75827a 100644 --- a/arch/arm/mach-imx/imx8/iomux.c +++ b/arch/arm/mach-imx/imx8/iomux.c @@ -3,7 +3,6 @@ * Copyright 2018 NXP */ -#include #include #include #include diff --git a/arch/arm/mach-imx/imx8/misc.c b/arch/arm/mach-imx/imx8/misc.c index 0ce3036818b..c77104d0338 100644 --- a/arch/arm/mach-imx/imx8/misc.c +++ b/arch/arm/mach-imx/imx8/misc.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc.c b/arch/arm/mach-imx/imx8/snvs_security_sc.c index 1eaa68f8d5f..f13dfc15516 100644 --- a/arch/arm/mach-imx/imx8/snvs_security_sc.c +++ b/arch/arm/mach-imx/imx8/snvs_security_sc.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 47219957b58..de630e940c9 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -5,7 +5,6 @@ * Peng Fan */ -#include #include #include #include diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c index 9db62b944e4..7e6c3748716 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -5,7 +5,6 @@ * Peng Fan */ -#include #include #include #include diff --git a/arch/arm/mach-imx/imx8m/clock_slice.c b/arch/arm/mach-imx/imx8m/clock_slice.c index b5ed27a923e..7cfdc46d349 100644 --- a/arch/arm/mach-imx/imx8m/clock_slice.c +++ b/arch/arm/mach-imx/imx8m/clock_slice.c @@ -5,7 +5,6 @@ * Peng Fan */ -#include #include #include #include diff --git a/arch/arm/mach-imx/imx8m/psci.c b/arch/arm/mach-imx/imx8m/psci.c index 62f0b768cfa..f5644c642bd 100644 --- a/arch/arm/mach-imx/imx8m/psci.c +++ b/arch/arm/mach-imx/imx8m/psci.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 0c49fb9cd48..be38ca52885 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -5,7 +5,7 @@ * Peng Fan */ -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c index d2fadb4877c..f9d8ed5b048 100644 --- a/arch/arm/mach-imx/imx8ulp/cgc.c +++ b/arch/arm/mach-imx/imx8ulp/cgc.c @@ -3,7 +3,6 @@ * Copyright 2021 NXP */ -#include #include #include #include diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index 36d12943a05..fadf165ece2 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -3,7 +3,6 @@ * Copyright 2020 NXP */ -#include #include #include #include diff --git a/arch/arm/mach-imx/imx8ulp/iomux.c b/arch/arm/mach-imx/imx8ulp/iomux.c index c6d20f54680..43f856bf732 100644 --- a/arch/arm/mach-imx/imx8ulp/iomux.c +++ b/arch/arm/mach-imx/imx8ulp/iomux.c @@ -3,7 +3,6 @@ * Copyright 2020-2021 NXP */ -#include #include #include #include diff --git a/arch/arm/mach-imx/imx8ulp/pcc.c b/arch/arm/mach-imx/imx8ulp/pcc.c index e3c6d6760be..449e496521f 100644 --- a/arch/arm/mach-imx/imx8ulp/pcc.c +++ b/arch/arm/mach-imx/imx8ulp/pcc.c @@ -3,7 +3,6 @@ * Copyright 2021 NXP */ -#include #include #include #include diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c index cfc09e79cbd..ca657748ed9 100644 --- a/arch/arm/mach-imx/imx8ulp/rdc.c +++ b/arch/arm/mach-imx/imx8ulp/rdc.c @@ -3,7 +3,8 @@ * Copyright 2021 NXP */ -#include +#include +#include #include #include #include diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 75d92af036a..0abf4579a1e 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -5,7 +5,6 @@ * Peng Fan */ -#include #include #include #include diff --git a/arch/arm/mach-imx/imx9/clock_root.c b/arch/arm/mach-imx/imx9/clock_root.c index 7d7ae865946..47106fffefb 100644 --- a/arch/arm/mach-imx/imx9/clock_root.c +++ b/arch/arm/mach-imx/imx9/clock_root.c @@ -5,7 +5,7 @@ * Peng Fan */ -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/imx9/imx_bootaux.c b/arch/arm/mach-imx/imx9/imx_bootaux.c index 6afb59e0515..73f2e72263d 100644 --- a/arch/arm/mach-imx/imx9/imx_bootaux.c +++ b/arch/arm/mach-imx/imx9/imx_bootaux.c @@ -3,11 +3,12 @@ * Copyright 2022 NXP */ -#include #include #include #include +#include #include +#include int arch_auxiliary_core_check_up(u32 core_id) { diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 2117489f232..32208220b20 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -5,7 +5,7 @@ * Peng Fan */ -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c index d0f855bb1bc..8cdb28459a3 100644 --- a/arch/arm/mach-imx/imx9/trdc.c +++ b/arch/arm/mach-imx/imx9/trdc.c @@ -3,8 +3,8 @@ * Copyright 2022 NXP */ -#include #include +#include #include #include #include diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index f7b14ca38d9..26374fdc33e 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -3,15 +3,18 @@ * Copyright (C) 2016 Freescale Semiconductor, Inc. */ -#include #include +#include #include #include #include #include #include +#include #include #include +#include +#include #include #ifndef CONFIG_IMX8 diff --git a/arch/arm/mach-imx/imxrt/soc.c b/arch/arm/mach-imx/imxrt/soc.c index 34162a3976f..3028957953b 100644 --- a/arch/arm/mach-imx/imxrt/soc.c +++ b/arch/arm/mach-imx/imxrt/soc.c @@ -4,7 +4,6 @@ * Author(s): Giulio Benetti */ -#include #include #include #include diff --git a/arch/arm/mach-imx/iomux-v3.c b/arch/arm/mach-imx/iomux-v3.c index 18131a20f43..c134e95ed78 100644 --- a/arch/arm/mach-imx/iomux-v3.c +++ b/arch/arm/mach-imx/iomux-v3.c @@ -7,7 +7,6 @@ * * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/arm/mach-imx/mac.c b/arch/arm/mach-imx/mac.c index 9bb63d25b48..e739fd14c89 100644 --- a/arch/arm/mach-imx/mac.c +++ b/arch/arm/mach-imx/mac.c @@ -5,7 +5,6 @@ * Peng Fan */ -#include #include #include #include diff --git a/arch/arm/mach-imx/misc.c b/arch/arm/mach-imx/misc.c index 09a758ff6e8..7452b82f110 100644 --- a/arch/arm/mach-imx/misc.c +++ b/arch/arm/mach-imx/misc.c @@ -3,7 +3,6 @@ * Copyright 2013 Stefan Roese */ -#include #include #include #include diff --git a/arch/arm/mach-imx/mmc_env.c b/arch/arm/mach-imx/mmc_env.c index 9c822f721c6..34a7d1706f3 100644 --- a/arch/arm/mach-imx/mmc_env.c +++ b/arch/arm/mach-imx/mmc_env.c @@ -3,7 +3,6 @@ * Copyright (C) 2017 NXP */ -#include #include #include #include diff --git a/arch/arm/mach-imx/mmdc_size.c b/arch/arm/mach-imx/mmdc_size.c index 41a5af6bd30..2b1d203f863 100644 --- a/arch/arm/mach-imx/mmdc_size.c +++ b/arch/arm/mach-imx/mmdc_size.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ -#include +#include #include #if defined(CONFIG_MX53) diff --git a/arch/arm/mach-imx/mx5/clock.c b/arch/arm/mach-imx/mx5/clock.c index bbaddd5a33f..0b8a10fd729 100644 --- a/arch/arm/mach-imx/mx5/clock.c +++ b/arch/arm/mach-imx/mx5/clock.c @@ -6,7 +6,6 @@ * (C) Copyright 2009 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/arm/mach-imx/mx5/mx53_dram.c b/arch/arm/mach-imx/mx5/mx53_dram.c index f7441441947..180a745d435 100644 --- a/arch/arm/mach-imx/mx5/mx53_dram.c +++ b/arch/arm/mach-imx/mx5/mx53_dram.c @@ -4,7 +4,6 @@ * Patrick Bruenn */ -#include #include #include diff --git a/arch/arm/mach-imx/mx5/soc.c b/arch/arm/mach-imx/mx5/soc.c index 47f531dc856..4df5f9c1641 100644 --- a/arch/arm/mach-imx/mx5/soc.c +++ b/arch/arm/mach-imx/mx5/soc.c @@ -6,7 +6,6 @@ * (C) Copyright 2009 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index e0da9c23958..fb9f56d2e63 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -3,10 +3,10 @@ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. */ -#include #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c index 3c87c577737..5a1258e002d 100644 --- a/arch/arm/mach-imx/mx6/ddr.c +++ b/arch/arm/mach-imx/mx6/ddr.c @@ -4,7 +4,6 @@ * Author: Tim Harvey */ -#include #include #include #include diff --git a/arch/arm/mach-imx/mx6/litesom.c b/arch/arm/mach-imx/mx6/litesom.c index 2ba3245e226..ab5de266577 100644 --- a/arch/arm/mach-imx/mx6/litesom.c +++ b/arch/arm/mach-imx/mx6/litesom.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/mx6/module_fuse.c b/arch/arm/mach-imx/mx6/module_fuse.c index b58f11c1e56..8b23d48a854 100644 --- a/arch/arm/mach-imx/mx6/module_fuse.c +++ b/arch/arm/mach-imx/mx6/module_fuse.c @@ -3,7 +3,6 @@ * Copyright 2019 NXP */ -#include #include #include #include diff --git a/arch/arm/mach-imx/mx6/mp.c b/arch/arm/mach-imx/mx6/mp.c index de9ace083ce..091a3723831 100644 --- a/arch/arm/mach-imx/mx6/mp.c +++ b/arch/arm/mach-imx/mx6/mp.c @@ -6,7 +6,6 @@ * (C) Copyright 2009 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/arm/mach-imx/mx6/opos6ul.c b/arch/arm/mach-imx/mx6/opos6ul.c index 38ead8ace20..340e6147b63 100644 --- a/arch/arm/mach-imx/mx6/opos6ul.c +++ b/arch/arm/mach-imx/mx6/opos6ul.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index c2875e727c9..3a3e01f3d0a 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -7,7 +7,6 @@ * Copyright 2021 NXP */ -#include #include #include #include diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c index 4e232385afc..a8606fa9b24 100644 --- a/arch/arm/mach-imx/mx7/clock.c +++ b/arch/arm/mach-imx/mx7/clock.c @@ -6,11 +6,12 @@ * Peng Fan */ -#include +#include #include #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-imx/mx7/clock_slice.c b/arch/arm/mach-imx/mx7/clock_slice.c index dd731d94962..2a1304fc112 100644 --- a/arch/arm/mach-imx/mx7/clock_slice.c +++ b/arch/arm/mach-imx/mx7/clock_slice.c @@ -6,7 +6,6 @@ * Peng Fan */ -#include #include #include #include diff --git a/arch/arm/mach-imx/mx7/ddr.c b/arch/arm/mach-imx/mx7/ddr.c index cf25569765e..c4a90be3945 100644 --- a/arch/arm/mach-imx/mx7/ddr.c +++ b/arch/arm/mach-imx/mx7/ddr.c @@ -12,7 +12,6 @@ #include #include #include -#include #include /* diff --git a/arch/arm/mach-imx/mx7/psci-mx7.c b/arch/arm/mach-imx/mx7/psci-mx7.c index 0b71fa40344..12d6a63b925 100644 --- a/arch/arm/mach-imx/mx7/psci-mx7.c +++ b/arch/arm/mach-imx/mx7/psci-mx7.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #define GPC_LPCR_A7_BSC 0x0 diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 689dbefe8ee..16c77cbf7be 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -4,7 +4,6 @@ * Copyright 2021 NXP */ -#include #include #include #include diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c index 37d8565c20f..fb19c62a520 100644 --- a/arch/arm/mach-imx/mx7ulp/clock.c +++ b/arch/arm/mach-imx/mx7ulp/clock.c @@ -3,7 +3,7 @@ * Copyright (C) 2016 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/mx7ulp/iomux.c b/arch/arm/mach-imx/mx7ulp/iomux.c index 05ddeed2a64..2c87a8c18b9 100644 --- a/arch/arm/mach-imx/mx7ulp/iomux.c +++ b/arch/arm/mach-imx/mx7ulp/iomux.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/arm/mach-imx/mx7ulp/pcc.c b/arch/arm/mach-imx/mx7ulp/pcc.c index aa7ea86a443..0bfd8f71815 100644 --- a/arch/arm/mach-imx/mx7ulp/pcc.c +++ b/arch/arm/mach-imx/mx7ulp/pcc.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c index 4c066557c1c..d4fb5389cac 100644 --- a/arch/arm/mach-imx/mx7ulp/scg.c +++ b/arch/arm/mach-imx/mx7ulp/scg.c @@ -3,7 +3,7 @@ * Copyright (C) 2016 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 217b7c45867..198ae2d919c 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -4,7 +4,7 @@ * Copyright 2021 NXP */ -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/priblob.c b/arch/arm/mach-imx/priblob.c index 5b022d5c820..65924483bc8 100644 --- a/arch/arm/mach-imx/priblob.c +++ b/arch/arm/mach-imx/priblob.c @@ -11,7 +11,6 @@ */ #include -#include #include #include diff --git a/arch/arm/mach-imx/rdc-sema.c b/arch/arm/mach-imx/rdc-sema.c index e683673753e..56725cc109f 100644 --- a/arch/arm/mach-imx/rdc-sema.c +++ b/arch/arm/mach-imx/rdc-sema.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/arm/mach-imx/speed.c b/arch/arm/mach-imx/speed.c index 0e81cc880a1..98a42b22f9c 100644 --- a/arch/arm/mach-imx/speed.c +++ b/arch/arm/mach-imx/speed.c @@ -7,7 +7,7 @@ * TsiChung Liew (Tsi-Chung.Liew@freescale.com) */ -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index b30cd962553..bc291dcd129 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -6,7 +6,7 @@ * Author: Tim Harvey */ -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c index b9ff9bb83b3..9a86f5c133f 100644 --- a/arch/arm/mach-imx/spl_imx_romapi.c +++ b/arch/arm/mach-imx/spl_imx_romapi.c @@ -3,7 +3,6 @@ * Copyright 2019 NXP */ -#include #include #include #include diff --git a/arch/arm/mach-imx/syscounter.c b/arch/arm/mach-imx/syscounter.c index 16df1186759..922f851c56b 100644 --- a/arch/arm/mach-imx/syscounter.c +++ b/arch/arm/mach-imx/syscounter.c @@ -5,7 +5,7 @@ * The file use ls102xa/timer.c as a reference. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/timer.c b/arch/arm/mach-imx/timer.c index fcd45f09f18..5ac8f28e670 100644 --- a/arch/arm/mach-imx/timer.c +++ b/arch/arm/mach-imx/timer.c @@ -6,7 +6,6 @@ * (C) Copyright 2009 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/arm/mach-imx/video.c b/arch/arm/mach-imx/video.c index 1bc9b7cc7e1..6cbb49da53c 100644 --- a/arch/arm/mach-imx/video.c +++ b/arch/arm/mach-imx/video.c @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ -#include +#include #include #include +#include #include #ifdef CONFIG_IMX_HDMI diff --git a/arch/arm/mach-k3/am64x/Makefile b/arch/arm/mach-k3/am64x/Makefile index 59ec43e7905..d0b286276c8 100644 --- a/arch/arm/mach-k3/am64x/Makefile +++ b/arch/arm/mach-k3/am64x/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ obj-$(CONFIG_SPL_BUILD) += am642_init.o +obj-y += boot.o diff --git a/arch/arm/mach-k3/am64x/am642_init.c b/arch/arm/mach-k3/am64x/am642_init.c index e5558201163..41812b7dbf7 100644 --- a/arch/arm/mach-k3/am64x/am642_init.c +++ b/arch/arm/mach-k3/am64x/am642_init.c @@ -286,97 +286,7 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) } } -static u32 __get_backup_bootmedia(u32 main_devstat) -{ - u32 bkup_bootmode = - (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >> - MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT; - u32 bkup_bootmode_cfg = - (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >> - MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT; - - switch (bkup_bootmode) { - case BACKUP_BOOT_DEVICE_UART: - return BOOT_DEVICE_UART; - - case BACKUP_BOOT_DEVICE_DFU: - if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK) - return BOOT_DEVICE_USB; - return BOOT_DEVICE_DFU; - - - case BACKUP_BOOT_DEVICE_ETHERNET: - return BOOT_DEVICE_ETHERNET; - - case BACKUP_BOOT_DEVICE_MMC: - if (bkup_bootmode_cfg) - return BOOT_DEVICE_MMC2; - return BOOT_DEVICE_MMC1; - - case BACKUP_BOOT_DEVICE_SPI: - return BOOT_DEVICE_SPI; - - case BACKUP_BOOT_DEVICE_I2C: - return BOOT_DEVICE_I2C; - }; - - return BOOT_DEVICE_RAM; -} - -static u32 __get_primary_bootmedia(u32 main_devstat) -{ - u32 bootmode = (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> - MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT; - u32 bootmode_cfg = - (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> - MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; - - switch (bootmode) { - case BOOT_DEVICE_OSPI: - fallthrough; - case BOOT_DEVICE_QSPI: - fallthrough; - case BOOT_DEVICE_XSPI: - fallthrough; - case BOOT_DEVICE_SPI: - return BOOT_DEVICE_SPI; - - case BOOT_DEVICE_ETHERNET_RGMII: - fallthrough; - case BOOT_DEVICE_ETHERNET_RMII: - return BOOT_DEVICE_ETHERNET; - - case BOOT_DEVICE_EMMC: - return BOOT_DEVICE_MMC1; - - case BOOT_DEVICE_NAND: - return BOOT_DEVICE_NAND; - - case BOOT_DEVICE_MMC: - if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >> - MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT) - return BOOT_DEVICE_MMC2; - return BOOT_DEVICE_MMC1; - - case BOOT_DEVICE_DFU: - if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >> - MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT) - return BOOT_DEVICE_USB; - return BOOT_DEVICE_DFU; - - case BOOT_DEVICE_NOBOOT: - return BOOT_DEVICE_RAM; - } - - return bootmode; -} - u32 spl_boot_device(void) { - u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); - - if (bootindex == K3_PRIMARY_BOOTMODE) - return __get_primary_bootmedia(devstat); - else - return __get_backup_bootmedia(devstat); + return get_boot_device(); } diff --git a/arch/arm/mach-k3/am64x/boot.c b/arch/arm/mach-k3/am64x/boot.c new file mode 100644 index 00000000000..ce8ae941be6 --- /dev/null +++ b/arch/arm/mach-k3/am64x/boot.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include +#include +#include + +static u32 __get_backup_bootmedia(u32 main_devstat) +{ + u32 bkup_bootmode = + (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >> + MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT; + u32 bkup_bootmode_cfg = + (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT; + + switch (bkup_bootmode) { + case BACKUP_BOOT_DEVICE_UART: + return BOOT_DEVICE_UART; + + case BACKUP_BOOT_DEVICE_DFU: + if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK) + return BOOT_DEVICE_USB; + return BOOT_DEVICE_DFU; + + case BACKUP_BOOT_DEVICE_ETHERNET: + return BOOT_DEVICE_ETHERNET; + + case BACKUP_BOOT_DEVICE_MMC: + if (bkup_bootmode_cfg) + return BOOT_DEVICE_MMC2; + return BOOT_DEVICE_MMC1; + + case BACKUP_BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + + case BACKUP_BOOT_DEVICE_I2C: + return BOOT_DEVICE_I2C; + }; + + return BOOT_DEVICE_RAM; +} + +static u32 __get_primary_bootmedia(u32 main_devstat) +{ + u32 bootmode = (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT; + u32 bootmode_cfg = + (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + + switch (bootmode) { + case BOOT_DEVICE_OSPI: + fallthrough; + case BOOT_DEVICE_QSPI: + fallthrough; + case BOOT_DEVICE_XSPI: + fallthrough; + case BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + + case BOOT_DEVICE_ETHERNET_RGMII: + fallthrough; + case BOOT_DEVICE_ETHERNET_RMII: + return BOOT_DEVICE_ETHERNET; + + case BOOT_DEVICE_EMMC: + return BOOT_DEVICE_MMC1; + + case BOOT_DEVICE_NAND: + return BOOT_DEVICE_NAND; + + case BOOT_DEVICE_MMC: + if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >> + MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT) + return BOOT_DEVICE_MMC2; + return BOOT_DEVICE_MMC1; + + case BOOT_DEVICE_DFU: + if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT) + return BOOT_DEVICE_USB; + return BOOT_DEVICE_DFU; + + case BOOT_DEVICE_NOBOOT: + return BOOT_DEVICE_RAM; + } + + return bootmode; +} + +u32 get_boot_device(void) +{ + u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); + u32 bootmode = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); + u32 bootmedia; + + if (bootmode == K3_PRIMARY_BOOTMODE) + bootmedia = __get_primary_bootmedia(devstat); + else + bootmedia = __get_backup_bootmedia(devstat); + + debug("%s: devstat = 0x%x bootmedia = 0x%x bootmode = %d\n", + __func__, devstat, bootmedia, bootmode); + + return bootmedia; +} diff --git a/arch/arm/mach-kirkwood/cache.c b/arch/arm/mach-kirkwood/cache.c index 009b7deeca6..acd2e8b1145 100644 --- a/arch/arm/mach-kirkwood/cache.c +++ b/arch/arm/mach-kirkwood/cache.c @@ -3,7 +3,6 @@ * Copyright (c) 2012 Michael Walle * Michael Walle */ -#include #include #include diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c index 2b493b36c20..a432abe615d 100644 --- a/arch/arm/mach-kirkwood/cpu.c +++ b/arch/arm/mach-kirkwood/cpu.c @@ -5,7 +5,6 @@ * Written-by: Prafulla Wadaskar */ -#include #include #include #include diff --git a/arch/arm/mach-kirkwood/include/mach/mpp.h b/arch/arm/mach-kirkwood/include/mach/mpp.h index 4d1f58c0cbd..e2757942590 100644 --- a/arch/arm/mach-kirkwood/include/mach/mpp.h +++ b/arch/arm/mach-kirkwood/include/mach/mpp.h @@ -8,6 +8,8 @@ #ifndef __KIRKWOOD_MPP_H #define __KIRKWOOD_MPP_H +#include + #define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \ /* MPP number */ ((_num) & 0xff) | \ /* MPP select value */ (((_sel) & 0xf) << 8) | \ diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c index 4fdad99cade..7938820e513 100644 --- a/arch/arm/mach-kirkwood/mpp.c +++ b/arch/arm/mach-kirkwood/mpp.c @@ -9,7 +9,6 @@ * warranty of any kind, whether express or implied. */ -#include #include #include #include diff --git a/arch/arm/mach-lpc32xx/clk.c b/arch/arm/mach-lpc32xx/clk.c index cb2344d79fe..2e11903e7e0 100644 --- a/arch/arm/mach-lpc32xx/clk.c +++ b/arch/arm/mach-lpc32xx/clk.c @@ -3,7 +3,6 @@ * Copyright (C) 2011 by Vladimir Zapolskiy */ -#include #include #include #include diff --git a/arch/arm/mach-lpc32xx/cpu.c b/arch/arm/mach-lpc32xx/cpu.c index a97f9a1958a..80f5e7c88eb 100644 --- a/arch/arm/mach-lpc32xx/cpu.c +++ b/arch/arm/mach-lpc32xx/cpu.c @@ -3,7 +3,6 @@ * Copyright (C) 2011-2015 by Vladimir Zapolskiy */ -#include #include #include #include diff --git a/arch/arm/mach-lpc32xx/devices.c b/arch/arm/mach-lpc32xx/devices.c index 6a67a3591aa..49308d6d4be 100644 --- a/arch/arm/mach-lpc32xx/devices.c +++ b/arch/arm/mach-lpc32xx/devices.c @@ -3,7 +3,7 @@ * Copyright (C) 2011 by Vladimir Zapolskiy */ -#include +#include #include #include diff --git a/arch/arm/mach-lpc32xx/dram.c b/arch/arm/mach-lpc32xx/dram.c index 16022379235..ab7c13512a5 100644 --- a/arch/arm/mach-lpc32xx/dram.c +++ b/arch/arm/mach-lpc32xx/dram.c @@ -10,7 +10,6 @@ * This code runs from SRAM. */ -#include #include #include #include diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c index 90183e3014e..523f9cfc8c4 100644 --- a/arch/arm/mach-lpc32xx/timer.c +++ b/arch/arm/mach-lpc32xx/timer.c @@ -3,7 +3,6 @@ * Copyright (C) 2011 Vladimir Zapolskiy */ -#include #include #include #include diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index 82018bd9d3e..ff1fdee5c8d 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -23,6 +23,7 @@ config TARGET_MT7622 config TARGET_MT7623 bool "MediaTek MT7623 SoC" select CPU_V7A + select MMC_SUPPORTS_TUNING help The MediaTek MT7623 is a ARM-based SoC with a quad-core Cortex-A7 including NEON and GPU, Mali-450 graphics, several DDR3 options, diff --git a/arch/arm/mach-mediatek/cpu.c b/arch/arm/mach-mediatek/cpu.c index c329e7cc98a..8e8bc4f9cea 100644 --- a/arch/arm/mach-mediatek/cpu.c +++ b/arch/arm/mach-mediatek/cpu.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 MediaTek Inc. */ -#include #include #include #include diff --git a/arch/arm/mach-mediatek/mt7622/init.c b/arch/arm/mach-mediatek/mt7622/init.c index 00d3eb9ce7a..6e970acf8b0 100644 --- a/arch/arm/mach-mediatek/mt7622/init.c +++ b/arch/arm/mach-mediatek/mt7622/init.c @@ -9,7 +9,6 @@ #include #include #include -#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-mediatek/mt7623/init.c b/arch/arm/mach-mediatek/mt7623/init.c index 988b057e598..3d6ba3f383c 100644 --- a/arch/arm/mach-mediatek/mt7623/init.c +++ b/arch/arm/mach-mediatek/mt7623/init.c @@ -3,7 +3,7 @@ * Copyright (C) 2018 MediaTek Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-mediatek/mt7629/init.c b/arch/arm/mach-mediatek/mt7629/init.c index 0130554ff35..7cb8b72c364 100644 --- a/arch/arm/mach-mediatek/mt7629/init.c +++ b/arch/arm/mach-mediatek/mt7629/init.c @@ -5,7 +5,7 @@ */ #include -#include +#include #include #include #include diff --git a/arch/arm/mach-mediatek/mt7981/init.c b/arch/arm/mach-mediatek/mt7981/init.c index 862f0ca4793..07da5897190 100644 --- a/arch/arm/mach-mediatek/mt7981/init.c +++ b/arch/arm/mach-mediatek/mt7981/init.c @@ -9,7 +9,6 @@ #include #include #include -#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-mediatek/mt7986/init.c b/arch/arm/mach-mediatek/mt7986/init.c index 905a3ab4e27..a521c95bd9d 100644 --- a/arch/arm/mach-mediatek/mt7986/init.c +++ b/arch/arm/mach-mediatek/mt7986/init.c @@ -9,7 +9,6 @@ #include #include #include -#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-mediatek/mt7988/init.c b/arch/arm/mach-mediatek/mt7988/init.c index 082f12bf65e..2efc8c6a88f 100644 --- a/arch/arm/mach-mediatek/mt7988/init.c +++ b/arch/arm/mach-mediatek/mt7988/init.c @@ -8,7 +8,6 @@ #include #include #include -#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-mediatek/mt8183/init.c b/arch/arm/mach-mediatek/mt8183/init.c index 7496029705f..37243547da8 100644 --- a/arch/arm/mach-mediatek/mt8183/init.c +++ b/arch/arm/mach-mediatek/mt8183/init.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/arch/arm/mach-mediatek/mt8512/init.c b/arch/arm/mach-mediatek/mt8512/init.c index 5a21e9a4485..3b48caf5196 100644 --- a/arch/arm/mach-mediatek/mt8512/init.c +++ b/arch/arm/mach-mediatek/mt8512/init.c @@ -7,7 +7,6 @@ */ #include -#include #include #include #include diff --git a/arch/arm/mach-mediatek/mt8516/init.c b/arch/arm/mach-mediatek/mt8516/init.c index 3460dcc2494..892bd441a33 100644 --- a/arch/arm/mach-mediatek/mt8516/init.c +++ b/arch/arm/mach-mediatek/mt8516/init.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/arch/arm/mach-mediatek/mt8518/init.c b/arch/arm/mach-mediatek/mt8518/init.c index f7e03de3650..c04bcb63517 100644 --- a/arch/arm/mach-mediatek/mt8518/init.c +++ b/arch/arm/mach-mediatek/mt8518/init.c @@ -7,7 +7,6 @@ */ #include -#include #include #include #include diff --git a/arch/arm/mach-mediatek/spl.c b/arch/arm/mach-mediatek/spl.c index d3cda94617e..247d7ee6f1d 100644 --- a/arch/arm/mach-mediatek/spl.c +++ b/arch/arm/mach-mediatek/spl.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/arch/arm/mach-meson/board-a1.c b/arch/arm/mach-meson/board-a1.c index 967bb671822..f848c0f068e 100644 --- a/arch/arm/mach-meson/board-a1.c +++ b/arch/arm/mach-meson/board-a1.c @@ -3,12 +3,12 @@ * (C) Copyright 2023 SberDevices, Inc. */ -#include #include #include #include #include #include +#include #include phys_size_t get_effective_memsize(void) diff --git a/arch/arm/mach-meson/board-axg.c b/arch/arm/mach-meson/board-axg.c index fdf18752cdd..6535539184c 100644 --- a/arch/arm/mach-meson/board-axg.c +++ b/arch/arm/mach-meson/board-axg.c @@ -4,7 +4,6 @@ * (C) Copyright 2018 Neil Armstrong */ -#include #include #include #include diff --git a/arch/arm/mach-meson/board-common.c b/arch/arm/mach-meson/board-common.c index 7ceba7cede8..39774c43049 100644 --- a/arch/arm/mach-meson/board-common.c +++ b/arch/arm/mach-meson/board-common.c @@ -3,7 +3,6 @@ * (C) Copyright 2016 Beniamino Galvani */ -#include #include #include #include diff --git a/arch/arm/mach-meson/board-g12a.c b/arch/arm/mach-meson/board-g12a.c index d5a830fb1db..dc4abe1e107 100644 --- a/arch/arm/mach-meson/board-g12a.c +++ b/arch/arm/mach-meson/board-g12a.c @@ -4,7 +4,6 @@ * (C) Copyright 2018 Neil Armstrong */ -#include #include #include #include diff --git a/arch/arm/mach-meson/board-gx.c b/arch/arm/mach-meson/board-gx.c index c3fbdfffeae..0370ed57e20 100644 --- a/arch/arm/mach-meson/board-gx.c +++ b/arch/arm/mach-meson/board-gx.c @@ -4,7 +4,6 @@ * (C) Copyright 2018 Neil Armstrong */ -#include #include #include #include diff --git a/arch/arm/mach-meson/board-info.c b/arch/arm/mach-meson/board-info.c index d51d9b8f064..b4058f59323 100644 --- a/arch/arm/mach-meson/board-info.c +++ b/arch/arm/mach-meson/board-info.c @@ -4,7 +4,6 @@ * (C) Copyright 2019 Neil Armstrong */ -#include #include #include #include diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c index 914fd11c989..4d9f83d3b38 100644 --- a/arch/arm/mach-meson/sm.c +++ b/arch/arm/mach-meson/sm.c @@ -5,7 +5,6 @@ * Secure monitor calls. */ -#include #include #include #include diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c b/arch/arm/mach-mvebu/alleycat5/cpu.c index 0f72ae1709b..be2d9a25bf9 100644 --- a/arch/arm/mach-mvebu/alleycat5/cpu.c +++ b/arch/arm/mach-mvebu/alleycat5/cpu.c @@ -3,7 +3,7 @@ * Copyright (C) 2018 Marvell International Ltd. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-mvebu/alleycat5/soc.c b/arch/arm/mach-mvebu/alleycat5/soc.c index 734b0a87dd4..98e66735eb9 100644 --- a/arch/arm/mach-mvebu/alleycat5/soc.c +++ b/arch/arm/mach-mvebu/alleycat5/soc.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Marvell International Ltd. */ -#include #include #include #include diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c index 4c67f1aba4d..63a12f7d774 100644 --- a/arch/arm/mach-mvebu/arm64-common.c +++ b/arch/arm/mach-mvebu/arm64-common.c @@ -3,7 +3,7 @@ * Copyright (C) 2016 Stefan Roese */ -#include +#include #include #include #include diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c b/arch/arm/mach-mvebu/armada3700/cpu.c index ab72b304e5d..17525691e68 100644 --- a/arch/arm/mach-mvebu/armada3700/cpu.c +++ b/arch/arm/mach-mvebu/armada3700/cpu.c @@ -4,7 +4,6 @@ * Copyright (C) 2020 Marek Behún */ -#include #include #include #include diff --git a/arch/arm/mach-mvebu/armada3700/efuse.c b/arch/arm/mach-mvebu/armada3700/efuse.c index 07d5f394354..84a1e388c11 100644 --- a/arch/arm/mach-mvebu/armada3700/efuse.c +++ b/arch/arm/mach-mvebu/armada3700/efuse.c @@ -5,9 +5,10 @@ */ #include -#include #include #include +#include +#include #include #include diff --git a/arch/arm/mach-mvebu/armada3700/mbox.c b/arch/arm/mach-mvebu/armada3700/mbox.c index 6555b8673ce..5ac543abce5 100644 --- a/arch/arm/mach-mvebu/armada3700/mbox.c +++ b/arch/arm/mach-mvebu/armada3700/mbox.c @@ -4,11 +4,11 @@ * Copyright (C) 2021 Pali Rohár */ -#include #include #include #include #include +#include #include #define RWTM_BASE (MVEBU_REGISTER(0xb0000)) diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c index 939abce000f..7908f75809c 100644 --- a/arch/arm/mach-mvebu/armada8k/cpu.c +++ b/arch/arm/mach-mvebu/armada8k/cpu.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Stefan Roese */ -#include #include #include #include diff --git a/arch/arm/mach-mvebu/armada8k/dram.c b/arch/arm/mach-mvebu/armada8k/dram.c index 6c801bfa1db..fd58551d0e3 100644 --- a/arch/arm/mach-mvebu/armada8k/dram.c +++ b/arch/arm/mach-mvebu/armada8k/dram.c @@ -3,7 +3,7 @@ * Copyright (C) 2016 Stefan Roese */ -#include +#include #include #include #include diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 7c62a5dbb6a..e603ab9ffb7 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -3,7 +3,7 @@ * Copyright (C) 2014-2016 Stefan Roese */ -#include +#include #include #include #include diff --git a/arch/arm/mach-mvebu/dram.c b/arch/arm/mach-mvebu/dram.c index d398d0f7676..c00c6b9b3fc 100644 --- a/arch/arm/mach-mvebu/dram.c +++ b/arch/arm/mach-mvebu/dram.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/arch/arm/mach-mvebu/efuse.c b/arch/arm/mach-mvebu/efuse.c index be5dc0e07d9..475687955e0 100644 --- a/arch/arm/mach-mvebu/efuse.c +++ b/arch/arm/mach-mvebu/efuse.c @@ -4,7 +4,6 @@ */ #include -#include #include #include #include diff --git a/arch/arm/mach-mvebu/gpio.c b/arch/arm/mach-mvebu/gpio.c index 1d1e3df8ba9..587cbb00e7f 100644 --- a/arch/arm/mach-mvebu/gpio.c +++ b/arch/arm/mach-mvebu/gpio.c @@ -5,7 +5,6 @@ * Written-by: Prafulla Wadaskar */ -#include #include #include #include diff --git a/arch/arm/mach-mvebu/mbus.c b/arch/arm/mach-mvebu/mbus.c index 959ca8e9260..9baeece3c85 100644 --- a/arch/arm/mach-mvebu/mbus.c +++ b/arch/arm/mach-mvebu/mbus.c @@ -46,7 +46,7 @@ * mvebu_mbus_del_window(). */ -#include +#include #include #include #include diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec-38x.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec-38x.c index 12596ec2d8b..4582871556d 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec-38x.c +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec-38x.c @@ -3,7 +3,6 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ -#include #include #include #include diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c index 3349f4eb549..efc31d5218a 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c @@ -3,7 +3,7 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ -#include +#include #include #include #include diff --git a/arch/arm/mach-mvebu/serdes/a38x/seq_exec.c b/arch/arm/mach-mvebu/serdes/a38x/seq_exec.c index 2a51b7113ce..9a1bbba7f2f 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/seq_exec.c +++ b/arch/arm/mach-mvebu/serdes/a38x/seq_exec.c @@ -3,7 +3,6 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ -#include #include #include #include diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c index fb8ec11dfb9..8290b861c07 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c @@ -3,7 +3,6 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ -#include #include #include #include diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c index 68f8eade272..61b7f168697 100644 --- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c @@ -3,7 +3,7 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ -#include +#include #include #include #include diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.c index 539d237623a..9b7bb2c3851 100644 --- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.c +++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.c @@ -3,7 +3,6 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ -#include #include #include #include diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index 79f8877745b..4f4f7e00e3c 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -3,7 +3,6 @@ * Copyright (C) 2014-2016 Stefan Roese */ -#include #include #include #include diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c index 682431ee11d..d94bde0777c 100644 --- a/arch/arm/mach-mvebu/system-controller.c +++ b/arch/arm/mach-mvebu/system-controller.c @@ -4,7 +4,6 @@ * Copyright (C) 2024 Marek Behún */ -#include #include #include #include diff --git a/arch/arm/mach-nexell/clock.c b/arch/arm/mach-nexell/clock.c index 59ffa26255f..3082f6077b7 100644 --- a/arch/arm/mach-nexell/clock.c +++ b/arch/arm/mach-nexell/clock.c @@ -4,8 +4,8 @@ * Hyunseok, Jung */ -#include #include +#include #include #include #include diff --git a/arch/arm/mach-nexell/include/mach/mipi_display.h b/arch/arm/mach-nexell/include/mach/mipi_display.h index f3fdec64647..9183ffdd9c3 100644 --- a/arch/arm/mach-nexell/include/mach/mipi_display.h +++ b/arch/arm/mach-nexell/include/mach/mipi_display.h @@ -11,6 +11,8 @@ #ifndef MIPI_DISPLAY_H #define MIPI_DISPLAY_H +#include + /* MIPI DSI Processor-to-Peripheral transaction types */ enum { MIPI_DSI_V_SYNC_START = 0x01, diff --git a/arch/arm/mach-nexell/include/mach/reset.h b/arch/arm/mach-nexell/include/mach/reset.h index e1301d4e53d..0c6a13043f9 100644 --- a/arch/arm/mach-nexell/include/mach/reset.h +++ b/arch/arm/mach-nexell/include/mach/reset.h @@ -7,6 +7,8 @@ #ifndef __NEXELL_RESET__ #define __NEXELL_RESET__ +#include + #define NUMBER_OF_RESET_MODULE_PIN 69 enum rstcon { diff --git a/arch/arm/mach-nexell/reset.c b/arch/arm/mach-nexell/reset.c index 1f732a3d373..627f568270b 100644 --- a/arch/arm/mach-nexell/reset.c +++ b/arch/arm/mach-nexell/reset.c @@ -8,7 +8,6 @@ *FIXME : Not support device tree & reset control driver. * will remove after support device tree & reset control driver. */ -#include #include #include #include diff --git a/arch/arm/mach-nexell/tieoff.c b/arch/arm/mach-nexell/tieoff.c index 5a4744c296a..51cca6744d6 100644 --- a/arch/arm/mach-nexell/tieoff.c +++ b/arch/arm/mach-nexell/tieoff.c @@ -4,7 +4,6 @@ * Youngbok, Park */ -#include #include #include #include diff --git a/arch/arm/mach-nexell/timer.c b/arch/arm/mach-nexell/timer.c index 3b311fd22a5..b35c7b1bb33 100644 --- a/arch/arm/mach-nexell/timer.c +++ b/arch/arm/mach-nexell/timer.c @@ -4,7 +4,6 @@ * Hyunseok, Jung */ -#include #include #include diff --git a/arch/arm/mach-npcm/npcm7xx/cpu.c b/arch/arm/mach-npcm/npcm7xx/cpu.c index dd74bb9e087..47d51cab5c7 100644 --- a/arch/arm/mach-npcm/npcm7xx/cpu.c +++ b/arch/arm/mach-npcm/npcm7xx/cpu.c @@ -3,7 +3,6 @@ * Copyright (c) 2021 Nuvoton Technology Corp. */ -#include #include #include #include diff --git a/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c b/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c index ed4b1ca5c98..df80687c857 100644 --- a/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c +++ b/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c @@ -3,7 +3,7 @@ * Copyright (c) 2021 Nuvoton Technology Corp. */ -#include +#include #include #include diff --git a/arch/arm/mach-npcm/npcm8xx/cpu.c b/arch/arm/mach-npcm/npcm8xx/cpu.c index af594526094..a1fb400b264 100644 --- a/arch/arm/mach-npcm/npcm8xx/cpu.c +++ b/arch/arm/mach-npcm/npcm8xx/cpu.c @@ -3,7 +3,6 @@ * Copyright (c) 2022 Nuvoton Technology Corp. */ -#include #include #include #include diff --git a/arch/arm/mach-npcm/npcm8xx/reset.c b/arch/arm/mach-npcm/npcm8xx/reset.c index 6954e6c6a17..e28b4ae7ae4 100644 --- a/arch/arm/mach-npcm/npcm8xx/reset.c +++ b/arch/arm/mach-npcm/npcm8xx/reset.c @@ -3,7 +3,6 @@ * Copyright (c) 2022 Nuvoton Technology Corp. */ -#include #include #include #include diff --git a/arch/arm/mach-octeontx/clock.c b/arch/arm/mach-octeontx/clock.c index 9da21077ecd..ffdee8799fb 100644 --- a/arch/arm/mach-octeontx/clock.c +++ b/arch/arm/mach-octeontx/clock.c @@ -5,7 +5,6 @@ * https://spdx.org/licenses */ -#include #include #include #include diff --git a/arch/arm/mach-octeontx/cpu.c b/arch/arm/mach-octeontx/cpu.c index aa5f4585c6f..90454edca25 100644 --- a/arch/arm/mach-octeontx/cpu.c +++ b/arch/arm/mach-octeontx/cpu.c @@ -5,7 +5,6 @@ * https://spdx.org/licenses */ -#include #include #include #include diff --git a/arch/arm/mach-octeontx2/clock.c b/arch/arm/mach-octeontx2/clock.c index 9da21077ecd..ffdee8799fb 100644 --- a/arch/arm/mach-octeontx2/clock.c +++ b/arch/arm/mach-octeontx2/clock.c @@ -5,7 +5,6 @@ * https://spdx.org/licenses */ -#include #include #include #include diff --git a/arch/arm/mach-octeontx2/cpu.c b/arch/arm/mach-octeontx2/cpu.c index 723deef719b..0a44af71a40 100644 --- a/arch/arm/mach-octeontx2/cpu.c +++ b/arch/arm/mach-octeontx2/cpu.c @@ -5,7 +5,6 @@ * https://spdx.org/licenses */ -#include #include #include #include diff --git a/arch/arm/mach-omap2/abb.c b/arch/arm/mach-omap2/abb.c index 722e6db0566..ce33d2fe129 100644 --- a/arch/arm/mach-omap2/abb.c +++ b/arch/arm/mach-omap2/abb.c @@ -8,7 +8,6 @@ * Andrii Tseglytskyi */ -#include #include #include #include diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 09659da5867..78c1e965c9f 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -7,7 +7,7 @@ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include +#include #include #include #include diff --git a/arch/arm/mach-omap2/am33xx/chilisom.c b/arch/arm/mach-omap2/am33xx/chilisom.c index d4f2abe17a9..4765ce0adee 100644 --- a/arch/arm/mach-omap2/am33xx/chilisom.c +++ b/arch/arm/mach-omap2/am33xx/chilisom.c @@ -4,7 +4,6 @@ * Copyright (C) 2017, Grinn - http://grinn-global.com/ */ -#include #include #include #include diff --git a/arch/arm/mach-omap2/am33xx/clk_synthesizer.c b/arch/arm/mach-omap2/am33xx/clk_synthesizer.c index 0969a404bf6..b75eb58ee82 100644 --- a/arch/arm/mach-omap2/am33xx/clk_synthesizer.c +++ b/arch/arm/mach-omap2/am33xx/clk_synthesizer.c @@ -7,8 +7,7 @@ * Copyright (C) 2016, Texas Instruments, Incorporated - https://www.ti.com/ */ - -#include +#include #include #include diff --git a/arch/arm/mach-omap2/am33xx/clock.c b/arch/arm/mach-omap2/am33xx/clock.c index 3273632c648..f07003c95bc 100644 --- a/arch/arm/mach-omap2/am33xx/clock.c +++ b/arch/arm/mach-omap2/am33xx/clock.c @@ -7,7 +7,6 @@ * * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include #include #include #include diff --git a/arch/arm/mach-omap2/am33xx/clock_am33xx.c b/arch/arm/mach-omap2/am33xx/clock_am33xx.c index d39e7e4fed1..c33d974dccd 100644 --- a/arch/arm/mach-omap2/am33xx/clock_am33xx.c +++ b/arch/arm/mach-omap2/am33xx/clock_am33xx.c @@ -7,7 +7,6 @@ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include #include #include #include diff --git a/arch/arm/mach-omap2/am33xx/clock_am43xx.c b/arch/arm/mach-omap2/am33xx/clock_am43xx.c index 8039bc2fe75..abd65ffd77f 100644 --- a/arch/arm/mach-omap2/am33xx/clock_am43xx.c +++ b/arch/arm/mach-omap2/am33xx/clock_am43xx.c @@ -8,7 +8,6 @@ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include #include #include #include diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c index 61b95c93733..41eec005cb1 100644 --- a/arch/arm/mach-omap2/am33xx/ddr.c +++ b/arch/arm/mach-omap2/am33xx/ddr.c @@ -5,7 +5,7 @@ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ -#include +#include #include #include #include diff --git a/arch/arm/mach-omap2/am33xx/emif4.c b/arch/arm/mach-omap2/am33xx/emif4.c index b29250b8d20..f19c66822d2 100644 --- a/arch/arm/mach-omap2/am33xx/emif4.c +++ b/arch/arm/mach-omap2/am33xx/emif4.c @@ -7,7 +7,6 @@ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include #include #include #include diff --git a/arch/arm/mach-omap2/am33xx/fdt.c b/arch/arm/mach-omap2/am33xx/fdt.c index 2ec30b1f9c3..3e81616cb74 100644 --- a/arch/arm/mach-omap2/am33xx/fdt.c +++ b/arch/arm/mach-omap2/am33xx/fdt.c @@ -3,7 +3,6 @@ * Copyright 2017 Texas Instruments, Inc. */ -#include #include #include #include diff --git a/arch/arm/mach-omap2/am33xx/mux.c b/arch/arm/mach-omap2/am33xx/mux.c index 49605593979..06b08e89e7f 100644 --- a/arch/arm/mach-omap2/am33xx/mux.c +++ b/arch/arm/mach-omap2/am33xx/mux.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/arch/arm/mach-omap2/am33xx/sys_info.c b/arch/arm/mach-omap2/am33xx/sys_info.c index 390d540e85a..87afc096602 100644 --- a/arch/arm/mach-omap2/am33xx/sys_info.c +++ b/arch/arm/mach-omap2/am33xx/sys_info.c @@ -11,7 +11,6 @@ * Syed Mohammed Khasim */ -#include #include #include #include diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index aa0ab13d5fb..e1ea3515ac1 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -7,7 +7,6 @@ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include #include #include #include diff --git a/arch/arm/mach-omap2/clocks-common.c b/arch/arm/mach-omap2/clocks-common.c index 390d1f2a649..2a0c22841d0 100644 --- a/arch/arm/mach-omap2/clocks-common.c +++ b/arch/arm/mach-omap2/clocks-common.c @@ -12,7 +12,6 @@ * Santosh Shilimkar * Rajendra Nayak */ -#include #include #include #include diff --git a/arch/arm/mach-omap2/emif-common.c b/arch/arm/mach-omap2/emif-common.c index 9daaeef7319..4d431e20779 100644 --- a/arch/arm/mach-omap2/emif-common.c +++ b/arch/arm/mach-omap2/emif-common.c @@ -8,7 +8,7 @@ * Aneesh V */ -#include +#include #include #include #include diff --git a/arch/arm/mach-omap2/fdt-common.c b/arch/arm/mach-omap2/fdt-common.c index e90d5776703..c6b4c03b508 100644 --- a/arch/arm/mach-omap2/fdt-common.c +++ b/arch/arm/mach-omap2/fdt-common.c @@ -3,7 +3,7 @@ * Copyright 2016-2017 Texas Instruments, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-omap2/hwinit-common.c b/arch/arm/mach-omap2/hwinit-common.c index 0e4572ca41a..138501602c3 100644 --- a/arch/arm/mach-omap2/hwinit-common.c +++ b/arch/arm/mach-omap2/hwinit-common.c @@ -10,7 +10,6 @@ * Aneesh V * Steve Sakoman */ -#include #include #include #include diff --git a/arch/arm/mach-omap2/mem-common.c b/arch/arm/mach-omap2/mem-common.c index 19197482aa4..00f144eb747 100644 --- a/arch/arm/mach-omap2/mem-common.c +++ b/arch/arm/mach-omap2/mem-common.c @@ -12,7 +12,7 @@ * Syed Mohammed Khasim */ -#include +#include #include #include #if IS_ENABLED(CONFIG_TARGET_AM335X_GUARDIAN) diff --git a/arch/arm/mach-omap2/omap-cache.c b/arch/arm/mach-omap2/omap-cache.c index 36db5882433..200a08fa5c8 100644 --- a/arch/arm/mach-omap2/omap-cache.c +++ b/arch/arm/mach-omap2/omap-cache.c @@ -11,9 +11,9 @@ * Steve Sakoman */ -#include #include #include +#include #include #include diff --git a/arch/arm/mach-omap2/omap3/am35x_musb.c b/arch/arm/mach-omap2/omap3/am35x_musb.c index 1121acc0058..d3807623bc6 100644 --- a/arch/arm/mach-omap2/omap3/am35x_musb.c +++ b/arch/arm/mach-omap2/omap3/am35x_musb.c @@ -8,8 +8,8 @@ * Hema HK */ -#include #include +#include #include #include #include diff --git a/arch/arm/mach-omap2/omap3/board.c b/arch/arm/mach-omap2/omap3/board.c index c76a95dd5d0..c5ada607f97 100644 --- a/arch/arm/mach-omap2/omap3/board.c +++ b/arch/arm/mach-omap2/omap3/board.c @@ -15,7 +15,6 @@ * Syed Mohammed Khasim * */ -#include #include #include #include diff --git a/arch/arm/mach-omap2/omap3/boot.c b/arch/arm/mach-omap2/omap3/boot.c index ea26115b711..2a36a25e279 100644 --- a/arch/arm/mach-omap2/omap3/boot.c +++ b/arch/arm/mach-omap2/omap3/boot.c @@ -5,7 +5,6 @@ * Copyright (C) 2015 Paul Kocialkowski */ -#include #include #include #include diff --git a/arch/arm/mach-omap2/omap3/clock.c b/arch/arm/mach-omap2/omap3/clock.c index 13685e0567a..417d1eb846f 100644 --- a/arch/arm/mach-omap2/omap3/clock.c +++ b/arch/arm/mach-omap2/omap3/clock.c @@ -11,11 +11,12 @@ * Syed Mohammed Khasim */ -#include +#include #include #include #include #include +#include #include #include diff --git a/arch/arm/mach-omap2/omap3/emac.c b/arch/arm/mach-omap2/omap3/emac.c index d0d0b7a75a6..7348e92cabd 100644 --- a/arch/arm/mach-omap2/omap3/emac.c +++ b/arch/arm/mach-omap2/omap3/emac.c @@ -6,7 +6,6 @@ * (C) Copyright 2011, Ilya Yanok, Emcraft Systems */ -#include #include #include #include diff --git a/arch/arm/mach-omap2/omap3/emif4.c b/arch/arm/mach-omap2/omap3/emif4.c index 4fbfb387ab0..049eedfeb65 100644 --- a/arch/arm/mach-omap2/omap3/emif4.c +++ b/arch/arm/mach-omap2/omap3/emif4.c @@ -9,7 +9,7 @@ * Texas Instruments Incorporated - https://www.ti.com/ */ -#include +#include #include #include #include diff --git a/arch/arm/mach-omap2/omap3/sdrc.c b/arch/arm/mach-omap2/omap3/sdrc.c index 4d27d82c788..404333689f6 100644 --- a/arch/arm/mach-omap2/omap3/sdrc.c +++ b/arch/arm/mach-omap2/omap3/sdrc.c @@ -21,7 +21,6 @@ * Manikandan Pillai */ -#include #include #include #include diff --git a/arch/arm/mach-omap2/omap3/spl_id_nand.c b/arch/arm/mach-omap2/omap3/spl_id_nand.c index 84a0b0ade93..d4712629d9d 100644 --- a/arch/arm/mach-omap2/omap3/spl_id_nand.c +++ b/arch/arm/mach-omap2/omap3/spl_id_nand.c @@ -11,7 +11,6 @@ * Jian Zhang */ -#include #include #include #include diff --git a/arch/arm/mach-omap2/omap3/sys_info.c b/arch/arm/mach-omap2/omap3/sys_info.c index 5f535e27827..1e3fcd59796 100644 --- a/arch/arm/mach-omap2/omap3/sys_info.c +++ b/arch/arm/mach-omap2/omap3/sys_info.c @@ -11,9 +11,10 @@ * Syed Mohammed Khasim */ -#include +#include #include #include /* get mem tables */ +#include #include #include #include diff --git a/arch/arm/mach-omap2/omap4/boot.c b/arch/arm/mach-omap2/omap4/boot.c index 90b5380ae39..a60249f7fd6 100644 --- a/arch/arm/mach-omap2/omap4/boot.c +++ b/arch/arm/mach-omap2/omap4/boot.c @@ -5,7 +5,6 @@ * Copyright (C) 2015 Paul Kocialkowski */ -#include #include #include #include diff --git a/arch/arm/mach-omap2/omap4/emif.c b/arch/arm/mach-omap2/omap4/emif.c index 35a51645be7..5b0d3b5c78a 100644 --- a/arch/arm/mach-omap2/omap4/emif.c +++ b/arch/arm/mach-omap2/omap4/emif.c @@ -8,7 +8,6 @@ * Aneesh V */ -#include #include #include #include diff --git a/arch/arm/mach-omap2/omap4/hw_data.c b/arch/arm/mach-omap2/omap4/hw_data.c index d587a4d4def..a81d7655494 100644 --- a/arch/arm/mach-omap2/omap4/hw_data.c +++ b/arch/arm/mach-omap2/omap4/hw_data.c @@ -8,7 +8,6 @@ * * Sricharan R */ -#include #include #include #include diff --git a/arch/arm/mach-omap2/omap4/hwinit.c b/arch/arm/mach-omap2/omap4/hwinit.c index 27dfa9142dc..e3e6cc8e578 100644 --- a/arch/arm/mach-omap2/omap4/hwinit.c +++ b/arch/arm/mach-omap2/omap4/hwinit.c @@ -10,7 +10,6 @@ * Aneesh V * Steve Sakoman */ -#include #include #include #include diff --git a/arch/arm/mach-omap2/omap4/sdram_elpida.c b/arch/arm/mach-omap2/omap4/sdram_elpida.c index 2a18cf0215d..a29a264016e 100644 --- a/arch/arm/mach-omap2/omap4/sdram_elpida.c +++ b/arch/arm/mach-omap2/omap4/sdram_elpida.c @@ -9,7 +9,6 @@ * Aneesh V */ -#include #include #include diff --git a/arch/arm/mach-omap2/omap5/abb.c b/arch/arm/mach-omap2/omap5/abb.c index 2f9f8e65d03..21da0b11661 100644 --- a/arch/arm/mach-omap2/omap5/abb.c +++ b/arch/arm/mach-omap2/omap5/abb.c @@ -8,7 +8,7 @@ * Andrii Tseglytskyi */ -#include +#include #include #include #include diff --git a/arch/arm/mach-omap2/omap5/boot.c b/arch/arm/mach-omap2/omap5/boot.c index 15d6836c6ea..5b479a87516 100644 --- a/arch/arm/mach-omap2/omap5/boot.c +++ b/arch/arm/mach-omap2/omap5/boot.c @@ -5,7 +5,6 @@ * Copyright (C) 2015 Paul Kocialkowski */ -#include #include #include #include diff --git a/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c b/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c index 8569eff31ab..d50452b5a30 100644 --- a/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c +++ b/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c @@ -6,7 +6,7 @@ * Lokesh Vutla */ -#include +#include #include #include #include diff --git a/arch/arm/mach-omap2/omap5/emif.c b/arch/arm/mach-omap2/omap5/emif.c index 2de36b6feca..d243ff3bd8f 100644 --- a/arch/arm/mach-omap2/omap5/emif.c +++ b/arch/arm/mach-omap2/omap5/emif.c @@ -8,7 +8,6 @@ * Aneesh V for OMAP4 */ -#include #include #include #include diff --git a/arch/arm/mach-omap2/omap5/fdt.c b/arch/arm/mach-omap2/omap5/fdt.c index 0ca02e664c4..f75ec47d821 100644 --- a/arch/arm/mach-omap2/omap5/fdt.c +++ b/arch/arm/mach-omap2/omap5/fdt.c @@ -3,7 +3,7 @@ * Copyright 2016 Texas Instruments, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c index b39132222ee..e65727026ef 100644 --- a/arch/arm/mach-omap2/omap5/hw_data.c +++ b/arch/arm/mach-omap2/omap5/hw_data.c @@ -8,7 +8,6 @@ * * Sricharan R */ -#include #include #include #include diff --git a/arch/arm/mach-omap2/omap5/hwinit.c b/arch/arm/mach-omap2/omap5/hwinit.c index edab9a92982..7f41e85c4a6 100644 --- a/arch/arm/mach-omap2/omap5/hwinit.c +++ b/arch/arm/mach-omap2/omap5/hwinit.c @@ -11,7 +11,6 @@ * Steve Sakoman * Sricharan */ -#include #include #include #include diff --git a/arch/arm/mach-omap2/omap5/sdram.c b/arch/arm/mach-omap2/omap5/sdram.c index 786da45fac8..6bf4cf4a758 100644 --- a/arch/arm/mach-omap2/omap5/sdram.c +++ b/arch/arm/mach-omap2/omap5/sdram.c @@ -10,7 +10,6 @@ * Sricharan R */ -#include #include #include diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c index 64560b21e3f..16bbc93f4a3 100644 --- a/arch/arm/mach-omap2/sec-common.c +++ b/arch/arm/mach-omap2/sec-common.c @@ -12,7 +12,7 @@ * Andrew F. Davis */ -#include +#include #include #include #include diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 71fdf5bf487..ed0620e7b63 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -15,7 +15,7 @@ * Gary Jennejohn, DENX Software Engineering, */ -#include +#include #include #include #include diff --git a/arch/arm/mach-omap2/utils.c b/arch/arm/mach-omap2/utils.c index 0623281a3c7..2326d153b12 100644 --- a/arch/arm/mach-omap2/utils.c +++ b/arch/arm/mach-omap2/utils.c @@ -3,9 +3,9 @@ * Copyright 2011 Linaro Limited * Aneesh V */ -#include #include #include +#include #include #include #include diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c index 054782efbdb..cb377aa1272 100644 --- a/arch/arm/mach-omap2/vc.c +++ b/arch/arm/mach-omap2/vc.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-orion5x/cpu.c b/arch/arm/mach-orion5x/cpu.c index ffae9a01e37..58ee67eca50 100644 --- a/arch/arm/mach-orion5x/cpu.c +++ b/arch/arm/mach-orion5x/cpu.c @@ -8,7 +8,6 @@ * Written-by: Prafulla Wadaskar */ -#include #include #include #include diff --git a/arch/arm/mach-orion5x/dram.c b/arch/arm/mach-orion5x/dram.c index 5647f847d78..228a3f7ad07 100644 --- a/arch/arm/mach-orion5x/dram.c +++ b/arch/arm/mach-orion5x/dram.c @@ -8,7 +8,6 @@ * Written-by: Prafulla Wadaskar */ -#include #include #include #include diff --git a/arch/arm/mach-orion5x/timer.c b/arch/arm/mach-orion5x/timer.c index b373e59e6fe..85736f04e67 100644 --- a/arch/arm/mach-orion5x/timer.c +++ b/arch/arm/mach-orion5x/timer.c @@ -7,7 +7,7 @@ * Written-by: Prafulla Wadaskar */ -#include +#include #include #include #include diff --git a/arch/arm/mach-owl/soc.c b/arch/arm/mach-owl/soc.c index f0f46f2dcb7..0130cad7678 100644 --- a/arch/arm/mach-owl/soc.c +++ b/arch/arm/mach-owl/soc.c @@ -5,13 +5,13 @@ * Copyright (C) 2018 Manivannan Sadhasivam */ +#include #include #include #include #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-owl/sysmap-owl.c b/arch/arm/mach-owl/sysmap-owl.c index 81f6ca2e491..6f0a220320e 100644 --- a/arch/arm/mach-owl/sysmap-owl.c +++ b/arch/arm/mach-owl/sysmap-owl.c @@ -6,7 +6,6 @@ * Copyright (C) 2018 Manivannan Sadhasivam */ -#include #include static struct mm_region owl_mem_map[] = { diff --git a/arch/arm/mach-renesas/memmap-gen3.c b/arch/arm/mach-renesas/memmap-gen3.c index 4dff9e07629..c50700df078 100644 --- a/arch/arm/mach-renesas/memmap-gen3.c +++ b/arch/arm/mach-renesas/memmap-gen3.c @@ -7,7 +7,6 @@ #include #include -#include #include #define GEN3_NR_REGIONS 16 diff --git a/arch/arm/mach-renesas/memmap-rzg2l.c b/arch/arm/mach-renesas/memmap-rzg2l.c index 9934a775220..3b3c6f7cde9 100644 --- a/arch/arm/mach-renesas/memmap-rzg2l.c +++ b/arch/arm/mach-renesas/memmap-rzg2l.c @@ -8,7 +8,6 @@ #include #include -#include #include #define RZG2L_NR_REGIONS 16 diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index cd226844b63..8a57b8217ff 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -8,7 +8,7 @@ * Based on puma-rk3399.c: * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH */ -#include +#include #include #include #include diff --git a/arch/arm/mach-rockchip/boot_mode.c b/arch/arm/mach-rockchip/boot_mode.c index f9be396aa55..55e9456668a 100644 --- a/arch/arm/mach-rockchip/boot_mode.c +++ b/arch/arm/mach-rockchip/boot_mode.c @@ -3,7 +3,6 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/bootrom.c b/arch/arm/mach-rockchip/bootrom.c index b36e559e871..82a0b3efef9 100644 --- a/arch/arm/mach-rockchip/bootrom.c +++ b/arch/arm/mach-rockchip/bootrom.c @@ -3,7 +3,6 @@ * Copyright (c) 2017 Google, Inc */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c index a62ff53c6a0..14c7331e1ab 100644 --- a/arch/arm/mach-rockchip/cpu-info.c +++ b/arch/arm/mach-rockchip/cpu-info.c @@ -4,7 +4,6 @@ * Author: Jagan Teki */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/px30-board-tpl.c b/arch/arm/mach-rockchip/px30-board-tpl.c index db368a7b8c2..f0b3c5f83f4 100644 --- a/arch/arm/mach-rockchip/px30-board-tpl.c +++ b/arch/arm/mach-rockchip/px30-board-tpl.c @@ -3,7 +3,6 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/px30/clk_px30.c b/arch/arm/mach-rockchip/px30/clk_px30.c index 7edf1321feb..410134769f8 100644 --- a/arch/arm/mach-rockchip/px30/clk_px30.c +++ b/arch/arm/mach-rockchip/px30/clk_px30.c @@ -3,7 +3,6 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd. */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index 2ec3289d75b..8b1509e55f2 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -2,7 +2,6 @@ /* * Copyright (c) 2017 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/px30/syscon_px30.c b/arch/arm/mach-rockchip/px30/syscon_px30.c index 37e88f5ccb9..c9de57493d8 100644 --- a/arch/arm/mach-rockchip/px30/syscon_px30.c +++ b/arch/arm/mach-rockchip/px30/syscon_px30.c @@ -3,7 +3,6 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c b/arch/arm/mach-rockchip/rk3036-board-spl.c index 73f6d241a1c..64e100172fa 100644 --- a/arch/arm/mach-rockchip/rk3036-board-spl.c +++ b/arch/arm/mach-rockchip/rk3036-board-spl.c @@ -3,7 +3,6 @@ * (C) Copyright 2015-2019 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3036/clk_rk3036.c b/arch/arm/mach-rockchip/rk3036/clk_rk3036.c index 116dccd7b87..9046601a75e 100644 --- a/arch/arm/mach-rockchip/rk3036/clk_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/clk_rk3036.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3036/rk3036.c b/arch/arm/mach-rockchip/rk3036/rk3036.c index e8130abdd77..6c92b31dc84 100644 --- a/arch/arm/mach-rockchip/rk3036/rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/rk3036.c @@ -3,7 +3,6 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c index 07cd29a33e6..308b9e6b8a8 100644 --- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c @@ -2,7 +2,7 @@ /* * (C) Copyright 2015 Rockchip Electronics Co., Ltd */ -#include +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c b/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c index c2fd1607990..23b75269d50 100644 --- a/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c @@ -3,7 +3,6 @@ * (C) Copyright 2015 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3066/clk_rk3066.c b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c index c47526dca5d..88057fad050 100644 --- a/arch/arm/mach-rockchip/rk3066/clk_rk3066.c +++ b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3066/rk3066.c b/arch/arm/mach-rockchip/rk3066/rk3066.c index 9a95ff85041..70b55ca8abf 100644 --- a/arch/arm/mach-rockchip/rk3066/rk3066.c +++ b/arch/arm/mach-rockchip/rk3066/rk3066.c @@ -3,7 +3,6 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c index a598f6400de..ff269b53b54 100644 --- a/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c +++ b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3128/clk_rk3128.c b/arch/arm/mach-rockchip/rk3128/clk_rk3128.c index a1b038c6486..ae552af3ff5 100644 --- a/arch/arm/mach-rockchip/rk3128/clk_rk3128.c +++ b/arch/arm/mach-rockchip/rk3128/clk_rk3128.c @@ -3,7 +3,6 @@ * Copyright (c) 2017 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c b/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c index 1406d5d0d32..f81c57a48be 100644 --- a/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c +++ b/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c @@ -3,7 +3,6 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3188/clk_rk3188.c b/arch/arm/mach-rockchip/rk3188/clk_rk3188.c index 94d1d23e1f4..c0e71c3fa90 100644 --- a/arch/arm/mach-rockchip/rk3188/clk_rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/clk_rk3188.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3188/rk3188.c b/arch/arm/mach-rockchip/rk3188/rk3188.c index ffdcaa49a1e..53b2eaa2d53 100644 --- a/arch/arm/mach-rockchip/rk3188/rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/rk3188.c @@ -2,7 +2,6 @@ /* * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c index 917ff37c0fc..6df054e5b27 100644 --- a/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk322x/clk_rk322x.c b/arch/arm/mach-rockchip/rk322x/clk_rk322x.c index 2e57672b246..4703125392e 100644 --- a/arch/arm/mach-rockchip/rk322x/clk_rk322x.c +++ b/arch/arm/mach-rockchip/rk322x/clk_rk322x.c @@ -3,7 +3,6 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd. */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c b/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c index 0d9dca8173c..c471a4c9fb7 100644 --- a/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c +++ b/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c @@ -3,7 +3,6 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c index fb4c0891d0d..af6c5d1f59b 100644 --- a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index 70cf5002912..d1170f7e23d 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -2,7 +2,6 @@ /* * Copyright (c) 2016 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c index 8b2c2f323a7..6413d0a88a1 100644 --- a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3308/clk_rk3308.c b/arch/arm/mach-rockchip/rk3308/clk_rk3308.c index 201bf661f9b..557e21f8199 100644 --- a/arch/arm/mach-rockchip/rk3308/clk_rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/clk_rk3308.c @@ -3,7 +3,6 @@ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c index a0915c72bfa..6f88638d156 100644 --- a/arch/arm/mach-rockchip/rk3308/rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/rk3308.c @@ -2,7 +2,6 @@ /* *Copyright (c) 2018 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3308/syscon_rk3308.c b/arch/arm/mach-rockchip/rk3308/syscon_rk3308.c index b380ff57233..2d7e9711015 100644 --- a/arch/arm/mach-rockchip/rk3308/syscon_rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/syscon_rk3308.c @@ -3,7 +3,6 @@ * (C) Copyright 2018 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3328/clk_rk3328.c b/arch/arm/mach-rockchip/rk3328/clk_rk3328.c index 70c0eb6f98e..b0c5af53da6 100644 --- a/arch/arm/mach-rockchip/rk3328/clk_rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/clk_rk3328.c @@ -3,7 +3,6 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c index ca3fa81e127..c86d11943d6 100644 --- a/arch/arm/mach-rockchip/rk3328/rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/rk3328.c @@ -3,7 +3,6 @@ * Copyright (c) 2016 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c index d2f267e6353..02ed366d8b6 100644 --- a/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c @@ -3,7 +3,6 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3368/clk_rk3368.c b/arch/arm/mach-rockchip/rk3368/clk_rk3368.c index b075319720d..c4d41e52af0 100644 --- a/arch/arm/mach-rockchip/rk3368/clk_rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/clk_rk3368.c @@ -4,7 +4,6 @@ * Author: Andy Yan */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c index 8f5ca1dfa7c..f589bf67328 100644 --- a/arch/arm/mach-rockchip/rk3368/rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c @@ -4,7 +4,6 @@ * Copyright (c) 2016 Andreas Färber */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c index dc2d831dd84..7389c028364 100644 --- a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c @@ -5,7 +5,6 @@ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c index 9d9a837fc74..de552b5903b 100644 --- a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 7fa1d7c7b7a..2d7d0f82a2f 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -3,7 +3,6 @@ * Copyright (c) 2016 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c index 2b5746cb31b..b92ad54ede5 100644 --- a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c @@ -3,7 +3,6 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3568/clk_rk3568.c b/arch/arm/mach-rockchip/rk3568/clk_rk3568.c index 8917edcbd30..1c6b2ece602 100644 --- a/arch/arm/mach-rockchip/rk3568/clk_rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/clk_rk3568.c @@ -3,7 +3,6 @@ * (C) Copyright 2021 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c index b30ea04f737..1b3e40074e3 100644 --- a/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -3,7 +3,6 @@ * (C) Copyright 2021 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c b/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c index 5407e7827f5..255259eabfd 100644 --- a/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c @@ -3,7 +3,6 @@ * (C) Copyright 2021 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3588/clk_rk3588.c b/arch/arm/mach-rockchip/rk3588/clk_rk3588.c index 3df0bf223e3..250ec423bd2 100644 --- a/arch/arm/mach-rockchip/rk3588/clk_rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/clk_rk3588.c @@ -3,7 +3,6 @@ * (C) Copyright 2020 Rockchip Electronics Co., Ltd. */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index eb65dafe3a2..d3162d3447e 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -4,7 +4,6 @@ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c b/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c index 7b2cf37d9da..f86567fcaf4 100644 --- a/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c @@ -3,7 +3,6 @@ * (C) Copyright 2021 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rv1108/clk_rv1108.c b/arch/arm/mach-rockchip/rv1108/clk_rv1108.c index 44b53c407a7..5659ae03d71 100644 --- a/arch/arm/mach-rockchip/rv1108/clk_rv1108.c +++ b/arch/arm/mach-rockchip/rv1108/clk_rv1108.c @@ -4,7 +4,6 @@ * Author: Andy Yan */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c b/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c index babdf5720b2..d68fbf1bd25 100644 --- a/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c +++ b/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c @@ -3,7 +3,6 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rv1126/clk_rv1126.c b/arch/arm/mach-rockchip/rv1126/clk_rv1126.c index bd8902718f2..3d64fcd4594 100644 --- a/arch/arm/mach-rockchip/rv1126/clk_rv1126.c +++ b/arch/arm/mach-rockchip/rv1126/clk_rv1126.c @@ -4,7 +4,6 @@ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rv1126/rv1126.c b/arch/arm/mach-rockchip/rv1126/rv1126.c index 40eb9eb7b19..1c10e9b9f23 100644 --- a/arch/arm/mach-rockchip/rv1126/rv1126.c +++ b/arch/arm/mach-rockchip/rv1126/rv1126.c @@ -4,7 +4,6 @@ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rv1126/syscon_rv1126.c b/arch/arm/mach-rockchip/rv1126/syscon_rv1126.c index 599ea66e3d6..67d2f18a8d0 100644 --- a/arch/arm/mach-rockchip/rv1126/syscon_rv1126.c +++ b/arch/arm/mach-rockchip/rv1126/syscon_rv1126.c @@ -4,7 +4,6 @@ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index f2a3d6b1400..1fb01e1c4b1 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -3,7 +3,7 @@ * Copyright (C) 2017 Rockchip Electronics Co., Ltd. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c index 3543267aa57..3dce9b30898 100644 --- a/arch/arm/mach-rockchip/spl-boot-order.c +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -3,7 +3,6 @@ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH */ -#include #include #include #include diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c index 2c3e9789cc8..50f04f9474a 100644 --- a/arch/arm/mach-rockchip/tpl.c +++ b/arch/arm/mach-rockchip/tpl.c @@ -3,7 +3,6 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/arch/arm/mach-s5pc1xx/cache.c b/arch/arm/mach-s5pc1xx/cache.c index b390bdf8278..f0aec7c0fe0 100644 --- a/arch/arm/mach-s5pc1xx/cache.c +++ b/arch/arm/mach-s5pc1xx/cache.c @@ -7,7 +7,6 @@ * based on arch/arm/cpu/armv7/omap3/cache.S */ -#include #include #include diff --git a/arch/arm/mach-s5pc1xx/clock.c b/arch/arm/mach-s5pc1xx/clock.c index c90c341b508..b92ce1152f6 100644 --- a/arch/arm/mach-s5pc1xx/clock.c +++ b/arch/arm/mach-s5pc1xx/clock.c @@ -5,7 +5,7 @@ * Heungjun Kim */ -#include +#include #include #include #include diff --git a/arch/arm/mach-s5pc1xx/pinmux.c b/arch/arm/mach-s5pc1xx/pinmux.c index 818d75164de..23b9252827a 100644 --- a/arch/arm/mach-s5pc1xx/pinmux.c +++ b/arch/arm/mach-s5pc1xx/pinmux.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include int exynos_pinmux_config(int peripheral, int flags) diff --git a/arch/arm/mach-sc5xx/Kconfig b/arch/arm/mach-sc5xx/Kconfig new file mode 100644 index 00000000000..3846b4fd5b6 --- /dev/null +++ b/arch/arm/mach-sc5xx/Kconfig @@ -0,0 +1,475 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# (C) Copyright 2022 - Analog Devices, Inc. +# +# Written and/or maintained by Timesys Corporation +# +# Contact: Nathan Barrett-Morrison +# Contact: Greg Malysa +# + +# All 32-bit platforms require SYS_ARM_CACHE_WRITETHROUGH +# But it is ignored if selected here, so it must be in the defconfig + +if ARCH_SC5XX + +config SC57X + bool + select SUPPORT_SPL + select CPU_V7A + select PANIC_HANG + select COMMON_CLK_ADI_SC57X + select TIMER + select ADI_SC5XX_TIMER + +config SC58X + bool + select SUPPORT_SPL + select CPU_V7A + select PANIC_HANG + select COMMON_CLK_ADI_SC58X + select TIMER + select ADI_SC5XX_TIMER + +config SC59X + bool + select SUPPORT_SPL + select CPU_V7A + select PANIC_HANG + select COMMON_CLK_ADI_SC594 + select TIMER + select ADI_SC5XX_TIMER + select NOP_PHY + +config SC59X_64 + bool + select SUPPORT_SPL + select PANIC_HANG + select MMC_SDHCI_ADMA_FORCE_32BIT + select ARM64 + select DM + select DM_SERIAL + select COMMON_CLK_ADI_SC598 + select GICV3 + select GIC_600_CLEAR_RDPD + select NOP_PHY + +config SC_BOOT_MODE + int "SC5XX boot mode select" + default 1 + range 0 7 + help + Mode 0: do nothing, just idle + Mode 1: boot ldr out of serial flash + Mode 7: boot ldr over uart + +config SC_BOOT_SPI_BUS + int "sc5xx spi boot bus" + default 2 + range 0 4 + help + This is the SPI peripheral number to use for booting, X in the + expression `sf probe X:Y` + +config SC_BOOT_SPI_SSEL + int "sc5xx spi boot chipselect" + default 1 + range 0 6 + help + This is the SPI chip select number to use for booting, Y in the + expression `sf probe X:Y` + +config SC_BOOT_OSPI_BUS + int "sc5xx ospi boot bus" + default 0 + help + This is the OSPI peripheral number to use for booting, X in the + expression `sf probe X:Y` + +config SC_BOOT_OSPI_SSEL + int "sc5xx ospi boot chipselect" + default 0 + help + This is the OSPI chip select number to use for booting, Y in the + expression `sf probe X:Y` + +config SYS_FLASH_BASE + hex + default 0x60000000 + +config UART_CONSOLE + int + default 0 + +config UART4_SERIAL + bool + depends on DM_SERIAL + default y + +config WDT_ADI + bool + default y + +config WATCHDOG_TIMEOUT_MSECS + int + default 30000 + +config DW_PORTS + int + default 1 + +config ADI_BUG_EZKHW21 + bool "SC584 EZKIT phy bug workaround" + depends on SC58X + help + This workaround affects the SC584 EZKIT and addresses bug EZKHW21. + It disables gigabit ethernet mode and limits the board to 100 Mbps + +config ADI_CARRIER_SOMCRR_EZKIT + bool "Support the EV-SOMCRR-EZKIT" + depends on (SC59X || SC59X_64) + help + Say y to include support for the EV-SOMCRR-EZKIT carrier board, + which is compatible with the SC594 and SC598 SOMs. The EZKIT is + mutually incompatible with the EZLITE. + +config ADI_CARRIER_SOMCRR_EZLITE + bool "Support the EV-SOMCRR-EZLITE" + depends on (SC59X || SC59X_64) + help + Say y to include support for the EV-SOMCRR-EZLITE carrier board, + which is compatible with the SC594 and SC598 SOMs. The EZLITE is + mutually incompatible with the EZKIT. + +config ADI_SPL_FORCE_BMODE + int "Force the SPL to use this BMODE device during next boot stage" + default 0 + range 0 9 + depends on SPL + help + Force the SPL to use this BMODE device during next boot stage. + For example, if booting via QSPI, we can force the second stage + Of the boot process to use other peripherals via: + 1 = QSPI -> QSPI + 5 = QSPI -> OSPI + 6 = QSPI -> eMMC + +config ADI_USE_DMC0 + bool "Configure DMC0" + default y + help + During hardware initialization, channel 0 of the DMC will be + initialized. Select this if you have DMC0 connected to external + DDR memory. This is expected to be true for every board using + an SC5xx SoC. + +config ADI_USE_DMC1 + bool "Configure DMC1" + help + During hardware initialization, channel 1 of the DMC will be + initialized. Not all processors have a DMC1. Select this if your + SoC has DMC1 and you have it connected to external DDR memory. + +config ADI_USE_DDR2 + bool "Configure DMC for DDR2 mode" + help + Configure the DMC in DDR2 mode. The default is DDR3 and not all + parts may actually support DDR2. Please consult the manual for + the SoC that you are using to determine if DDR2 mode is supported. + This also requires that DDR2 memory is present on the board or it + will probably cause strange failure. + +menu "Clock configuration" + +config CGU0_DF_DIV + int "CGU0_DF_DIV" + range 0 1 + help + Select 0 to pass CLKIN to PLL + Select 1 to pass CLKIN/2 to PLL + +config CGU0_VCO_MULT + int "CGU0_VCO_MULT" + range 0 127 + help + VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL + A value of 0 means 128 + +config CGU0_CCLK_DIV + int "CGU0_CCLK_DIV" + range 0 31 + help + CCLK_DIV controls the core clock divider + A value of 0 means 32 + CCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / CCLK_DIV + +config CGU0_SCLK_DIV + int "CGU0_SCLK_DIV" + range 0 31 + help + SCLK_DIV controls the system clock divider + A value of 0 means 32 + SCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / SYSCLK_DIV + +config CGU0_SCLK0_DIV + int "CGU0_SCLK0_DIV" + range 0 7 + help + A value of 0 means 8 + SCLK0 = SCLK / SCLK0_DIV + +config CGU0_SCLK1_DIV + int "CGU0_SCLK1_DIV" + depends on (SC57X || SC58X) + range 0 7 + help + A value of 0 means 8 + SCLK1 = SCLK / SCLK1_DIV + +config CGU0_DCLK_DIV + int "CGU0_DCLK_DIV" + range 0 31 + help + DCLK_DIV controls the DDR clock divider + A value of 0 means 32 + DCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / DCLK_DIV + +config CGU0_OCLK_DIV + int "CGU0_OCLK_DIV" + range 0 127 + help + OCLK_DIV controls the output clock divider + A value of 0 means 128 + OCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / OCLK_DIV + +config CGU0_DIV_S1SELEX + int "CGU0_DIV_S1SELEX" + depends on !SC57X && !SC58X + range 0 255 + help + CGU0 SCLK1 Extended divisor register. + A value of 0 means 256. + SCLK1 = ((CLKIN / (1 + DF)) * VCO_MULT) / DIV_S1SELEX + +config CGU0_CLKOUTSEL + int "CGU0_CLKOUTSEL" + default 0 + range 0 31 + help + Select signal driven through CLKOUT pin multiplexer. + This value varies on each SOC. Refer to + CGU_CLKOUTSEL.CLKOUTSEL in the Hardware Reference Manual + for values applicable to each SOC. + Commonly, values 0 and 1 select CLKIN0 or CLKIN1 respectively. + +config CGU1_PLL3_DDRCLK + bool "DDRCLK From 3rd PLL" + depends on SC59X_64 + help + 3rd PLL output is connected to DMC block when set. + When cleared, DDR clock is CLKO3 output of CDU. + +config CGU1_PLL3_VCO_MSEL + int "CGU0_PLL3_VCO_MSEL" + depends on CGU1_PLL3_DDRCLK + range 1 128 + help + PLL multiplier value for the 3rd PLL. + DCLK = (CLKIN * PLL3_VCO_MSEL) / PLL3_DCLK_DIV + +config CGU1_PLL3_DCLK_DIV + int "CGU0_PLL3_DCLK_DIV" + depends on CGU1_PLL3_DDRCLK + range 1 32 + help + PLL divider value for the 3rd PLL. + DCLK = (CLKIN * PLL3_VCO_MSEL) / PLL3_DCLK_DIV + +config CGU1_DF_DIV + int "CGU1_DF_DIV" + range 0 1 + help + Select 0 to pass CLKIN to PLL + Select 1 to pass CLKIN/2 to PLL + +config CGU1_VCO_MULT + int "CGU1_VCO_MULT" + range 0 127 + help + VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL + A value of 0 means 128 + +config CGU1_CCLK_DIV + int "CGU1_CCLK_DIV" + range 0 31 + help + CCLK_DIV controls the core clock divider + A value of 0 means 32 + CCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / CCLK_DIV + +config CGU1_SCLK_DIV + int "CGU1_SCLK_DIV" + range 0 31 + help + SCLK_DIV controls the system clock divider + A value of 0 means 32 + SCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / SYSCLK_DIV + +config CGU1_SCLK0_DIV + int "CGU1_SCLK0_DIV" + depends on (SC57X || SC58X || SC59X) + range 0 7 + help + A value of 0 means 8 + SCLK0 = SCLK / SCLK0_DIV + +config CGU1_SCLK1_DIV + int "CGU1_SCLK1_DIV" + depends on (SC57X || SC58X) + range 0 7 + help + A value of 0 means 8 + SCLK1 = SCLK / SCLK1_DIV + +config CGU1_DCLK_DIV + int "CGU1_DCLK_DIV" + range 0 31 + help + DCLK_DIV controls the DDR clock divider + A value of 0 means 32 + DCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / DCLK_DIV + +config CGU1_OCLK_DIV + int "CGU1_OCLK_DIV" + range 0 127 + help + OCLK_DIV controls the output clock divider + A value of 0 means 128 + OCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / OCLK_DIV + +config CGU1_DIV_S0SELEX + int "CGU1_DIV_S0SELEX" + depends on !SC57X && !SC58X && !SC59X + range 0 255 + help + CGU1 SCLK0 Extended divisor register. + A value of 0 means 256. + SCLK0 = ((CLKIN / (1 + DF)) * VCO_MULT) / DIV_S0SELEX + +config CGU1_DIV_S1SELEX + int "CGU1_DIV_S1SELEX" + depends on !SC57X && !SC58X + range 0 255 + help + CGU1 SCLK1 Extended divisor register. + A value of 0 means 256. + SCLK1 = ((CLKIN / (1 + DF)) * VCO_MULT) / DIV_S1SELEX + +config CDU0_CGU1_CLKIN + int "CDU0 CGU1 CLKINn Select" + default 0 + range 0 1 + help + Selects source clock for CGU1. + 0 for CLKIN0 + 1 for CLKIN1 + +config CDU0_CLKO0 + int "CDU0_CLKO0" + range 1 7 + help + Clock source select. Refer to SOC Hardware Reference Manual + +config CDU0_CLKO1 + int "CDU0_CLKO1" + range 1 7 + help + Clock source select. Refer to SOC Hardware Reference Manual + +config CDU0_CLKO2 + int "CDU0_CLKO2" + range 1 7 + help + Clock source select. Refer to SOC Hardware Reference Manual + +config CDU0_CLKO3 + int "CDU0_CLKO3" + range 1 7 + help + Clock source select. Refer to SOC Hardware Reference Manual + +config CDU0_CLKO4 + int "CDU0_CLKO4" + range 1 7 + help + Clock source select. Refer to SOC Hardware Reference Manual + +config CDU0_CLKO5 + int "CDU0_CLKO5" + range 1 7 + help + Clock source select. Refer to SOC Hardware Reference Manual + +config CDU0_CLKO6 + int "CDU0_CLKO6" + range 1 7 + help + Clock source select. Refer to SOC Hardware Reference Manual + +config CDU0_CLKO7 + int "CDU0_CLKO7" + range 1 7 + help + Clock source select. Refer to SOC Hardware Reference Manual + +config CDU0_CLKO8 + int "CDU0_CLKO8" + range 1 7 + help + Clock source select. Refer to SOC Hardware Reference Manual + +config CDU0_CLKO9 + int "CDU0_CLKO9" + range 1 7 + help + Clock source select. Refer to SOC Hardware Reference Manual + +config CDU0_CLKO10 + int "CDU0_CLKO10" + range 1 7 + depends on (SC59X || SC59X_64) + help + Clock source select. Refer to SOC Hardware Reference Manual + +config CDU0_CLKO12 + int "CDU0_CLKO12" + range 1 7 + depends on (SC59X || SC59X_64) + help + Clock source select. Refer to SOC Hardware Reference Manual + +config CDU0_CLKO13 + int "CDU0_CLKO13" + range 1 7 + depends on SC59X_64 + help + Clock source select. Refer to SOC Hardware Reference Manual + +config CDU0_CLKO14 + int "CDU0_CLKO14" + range 1 7 + depends on SC59X_64 + help + Clock source select. Refer to SOC Hardware Reference Manual + +endmenu + +config ADI_GPIO + bool + default y + +config PINCTRL_ADI + bool + default y + +endif diff --git a/arch/arm/mach-sc5xx/Makefile b/arch/arm/mach-sc5xx/Makefile new file mode 100644 index 00000000000..eeb56c078b3 --- /dev/null +++ b/arch/arm/mach-sc5xx/Makefile @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# (C) Copyright 2022 - Analog Devices, Inc. +# +# Written and/or maintained by Timesys Corporation +# +# Contact: Nathan Barrett-Morrison +# Contact: Greg Malysa +# + +obj-y += soc.o init/ + +obj-$(CONFIG_SC57X) += sc57x.o +obj-$(CONFIG_SC58X) += sc58x.o +obj-$(CONFIG_SC59X) += sc59x.o +obj-$(CONFIG_SC59X_64) += sc59x_64.o + +obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_SYSCON) += rcu.o diff --git a/arch/arm/mach-sc5xx/config.mk b/arch/arm/mach-sc5xx/config.mk new file mode 100644 index 00000000000..580964e559c --- /dev/null +++ b/arch/arm/mach-sc5xx/config.mk @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# (C) Copyright 2022 - Analog Devices, Inc. +# +# Written and/or maintained by Timesys Corporation +# +# Contact: Nathan Barrett-Morrison +# Contact: Greg Malysa +# + +ifdef CONFIG_SPL_BUILD +INPUTS-y += $(obj)/u-boot-spl.ldr +endif + +LDR_FLAGS += --bcode=$(CONFIG_SC_BOOT_MODE) +LDR_FLAGS += --use-vmas diff --git a/arch/arm/mach-sc5xx/init/Makefile b/arch/arm/mach-sc5xx/init/Makefile new file mode 100644 index 00000000000..9d4920fe076 --- /dev/null +++ b/arch/arm/mach-sc5xx/init/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# (C) Copyright 2022 - Analog Devices, Inc. +# +# Written and/or maintained by Timesys Corporation +# +# Contact: Nathan Barrett-Morrison +# Contact: Greg Malysa +# + +obj-y += dmcinit.o clkinit.o diff --git a/arch/arm/mach-sc5xx/init/clkinit.c b/arch/arm/mach-sc5xx/init/clkinit.c new file mode 100644 index 00000000000..ae53cd61efd --- /dev/null +++ b/arch/arm/mach-sc5xx/init/clkinit.c @@ -0,0 +1,558 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison + * Contact: Greg Malysa + */ + +#include +#include +#include +#include "clkinit.h" +#include "dmcinit.h" + +#ifdef CONFIG_CGU0_SCLK0_DIV + #define VAL_CGU0_SCLK0_DIV CONFIG_CGU0_SCLK0_DIV +#else + #define VAL_CGU0_SCLK0_DIV 1 +#endif +#ifdef CONFIG_CGU0_SCLK1_DIV + #define VAL_CGU0_SCLK1_DIV CONFIG_CGU0_SCLK1_DIV +#else + #define VAL_CGU0_SCLK1_DIV 1 +#endif +#ifdef CONFIG_CGU0_DIV_S0SELEX + #define VAL_CGU0_DIV_S0SELEX CONFIG_CGU0_DIV_S0SELEX +#else + #define VAL_CGU0_DIV_S0SELEX -1 +#endif +#ifdef CONFIG_CGU0_DIV_S1SELEX + #define VAL_CGU0_DIV_S1SELEX CONFIG_CGU0_DIV_S1SELEX +#else + #define VAL_CGU0_DIV_S1SELEX -1 +#endif +#ifdef CONFIG_CGU0_CLKOUTSEL + #define VAL_CGU0_CLKOUTSEL CONFIG_CGU0_CLKOUTSEL +#else + #define VAL_CGU0_CLKOUTSEL -1 +#endif +#ifdef CONFIG_CGU1_SCLK0_DIV + #define VAL_CGU1_SCLK0_DIV CONFIG_CGU1_SCLK0_DIV +#else + #define VAL_CGU1_SCLK0_DIV 1 +#endif +#ifdef CONFIG_CGU1_SCLK1_DIV + #define VAL_CGU1_SCLK1_DIV CONFIG_CGU1_SCLK1_DIV +#else + #define VAL_CGU1_SCLK1_DIV 1 +#endif +#ifdef CONFIG_CGU1_DIV_S0SELEX + #define VAL_CGU1_DIV_S0SELEX CONFIG_CGU1_DIV_S0SELEX +#else + #define VAL_CGU1_DIV_S0SELEX -1 +#endif +#ifdef CONFIG_CGU1_DIV_S1SELEX + #define VAL_CGU1_DIV_S1SELEX CONFIG_CGU1_DIV_S1SELEX +#else + #define VAL_CGU1_DIV_S1SELEX -1 +#endif +#ifdef CONFIG_CGU1_CLKOUTSEL + #define VAL_CGU1_CLKOUTSEL CONFIG_CGU1_CLKOUTSEL +#else + #define VAL_CGU1_CLKOUTSEL -1 +#endif + +#define REG_MISC_REG10_tst_addr 0x310A902C + +#define CGU0_REGBASE 0x3108D000 +#define CGU1_REGBASE 0x3108E000 + +#define CGU_CTL 0x00 // CGU0 Control Register +#define CGU_PLLCTL 0x04 // CGU0 PLL Control Register +#define CGU_STAT 0x08 // CGU0 Status Register +#define CGU_DIV 0x0C // CGU0 Clocks Divisor Register +#define CGU_CLKOUTSEL 0x10 // CGU0 CLKOUT Select Register +#define CGU_DIVEX 0x40 // CGU0 DIV Register Extension + +#define BITP_CGU_DIV_OSEL 22 // OUTCLK Divisor +#define BITP_CGU_DIV_DSEL 16 // DCLK Divisor +#define BITP_CGU_DIV_S1SEL 13 // SCLK 1 Divisor +#define BITP_CGU_DIV_SYSSEL 8 // SYSCLK Divisor +#define BITP_CGU_DIV_S0SEL 5 // SCLK 0 Divisor +#define BITP_CGU_DIV_CSEL 0 // CCLK Divisor + +#define BITP_CGU_CTL_MSEL 8 // Multiplier Select +#define BITP_CGU_CTL_DF 0 // Divide Frequency + +#define BITM_CGU_STAT_CLKSALGN 0x00000008 +#define BITM_CGU_STAT_PLOCK 0x00000004 +#define BITM_CGU_STAT_PLLBP 0x00000002 +#define BITM_CGU_STAT_PLLEN 0x00000001 + +/* PLL Multiplier and Divisor Selections (Required Value, Bit Position) */ +/* PLL Multiplier Select */ +#define MSEL(X) (((X) << BITP_CGU_CTL_MSEL) & \ + BITM_CGU_CTL_MSEL) +/* Divide frequency[true or false] */ +#define DF(X) (((X) << BITP_CGU_CTL_DF) & \ + BITM_CGU_CTL_DF) +/* Core Clock Divisor Select */ +#define CSEL(X) (((X) << BITP_CGU_DIV_CSEL) & \ + BITM_CGU_DIV_CSEL) +/* System Clock Divisor Select */ +#define SYSSEL(X) (((X) << BITP_CGU_DIV_SYSSEL) & \ + BITM_CGU_DIV_SYSSEL) +/* SCLK0 Divisor Select */ +#define S0SEL(X) (((X) << BITP_CGU_DIV_S0SEL) & \ + BITM_CGU_DIV_S0SEL) +/* SCLK1 Divisor Select */ +#define S1SEL(X) (((X) << BITP_CGU_DIV_S1SEL) & \ + BITM_CGU_DIV_S1SEL) +/* DDR Clock Divisor Select */ +#define DSEL(X) (((X) << BITP_CGU_DIV_DSEL) & \ + BITM_CGU_DIV_DSEL) +/* OUTCLK Divisor Select */ +#define OSEL(X) (((X) << BITP_CGU_DIV_OSEL) & \ + BITM_CGU_DIV_OSEL) +/* CLKOUT select */ +#define CLKOUTSEL(X) (((X) << BITP_CGU_CLKOUTSEL_CLKOUTSEL) & \ + BITM_CGU_CLKOUTSEL_CLKOUTSEL) +#define S0SELEX(X) (((X) << BITP_CGU_DIVEX_S0SELEX) & \ + BITM_CGU_DIVEX_S0SELEX) +#define S1SELEX(X) (((X) << BITP_CGU_DIVEX_S1SELEX) & \ + BITM_CGU_DIVEX_S1SELEX) + +struct CGU_Settings { + phys_addr_t rbase; + u32 ctl_MSEL:7; + u32 ctl_DF:1; + u32 div_CSEL:5; + u32 div_SYSSEL:5; + u32 div_S0SEL:3; + u32 div_S1SEL:3; + u32 div_DSEL:5; + u32 div_OSEL:7; + s16 divex_S0SELEX; + s16 divex_S1SELEX; + s8 clkoutsel; +}; + +/* CGU Registers */ +#define BITM_CGU_CTL_LOCK 0x80000000 /* Lock */ + +#define BITM_CGU_CTL_MSEL 0x00007F00 /* Multiplier Select */ +#define BITM_CGU_CTL_DF 0x00000001 /* Divide Frequency */ +#define BITM_CGU_CTL_S1SELEXEN 0x00020000 /* SCLK1 Extension Divider Enable */ +#define BITM_CGU_CTL_S0SELEXEN 0x00010000 /* SCLK0 Extension Divider Enable */ + +#define BITM_CGU_DIV_LOCK 0x80000000 /* Lock */ +#define BITM_CGU_DIV_UPDT 0x40000000 /* Update Clock Divisors */ +#define BITM_CGU_DIV_ALGN 0x20000000 /* Align */ +#define BITM_CGU_DIV_OSEL 0x1FC00000 /* OUTCLK Divisor */ +#define BITM_CGU_DIV_DSEL 0x001F0000 /* DCLK Divisor */ +#define BITM_CGU_DIV_S1SEL 0x0000E000 /* SCLK 1 Divisor */ +#define BITM_CGU_DIV_SYSSEL 0x00001F00 /* SYSCLK Divisor */ +#define BITM_CGU_DIV_S0SEL 0x000000E0 /* SCLK 0 Divisor */ +#define BITM_CGU_DIV_CSEL 0x0000001F /* CCLK Divisor */ + +#define BITP_CGU_DIVEX_S0SELEX 0 +#define BITM_CGU_DIVEX_S0SELEX 0x000000FF /* SCLK 0 Extension Divisor */ + +#define BITP_CGU_DIVEX_S1SELEX 16 +#define BITM_CGU_DIVEX_S1SELEX 0x00FF0000 /* SCLK 1 Extension Divisor */ + +#define BITM_CGU_PLLCTL_PLLEN 0x00000008 /* PLL Enable */ +#define BITM_CGU_PLLCTL_PLLBPCL 0x00000002 /* PLL Bypass Clear */ +#define BITM_CGU_PLLCTL_PLLBPST 0x00000001 /* PLL Bypass Set */ + +#define BITP_CGU_CLKOUTSEL_CLKOUTSEL 0 /* CLKOUT Select */ +#define BITM_CGU_CLKOUTSEL_CLKOUTSEL 0x0000001F /* CLKOUT Select */ + +#define CGU_STAT_MASK (BITM_CGU_STAT_PLLEN | BITM_CGU_STAT_PLOCK | \ + BITM_CGU_STAT_CLKSALGN) +#define CGU_STAT_ALGN_LOCK (BITM_CGU_STAT_PLLEN | BITM_CGU_STAT_PLOCK) + +/* Clock Distribution Unit Registers */ +#define REG_CDU0_CFG0 0x3108F000 +#define REG_CDU0_CFG1 0x3108F004 +#define REG_CDU0_CFG2 0x3108F008 +#define REG_CDU0_CFG3 0x3108F00C +#define REG_CDU0_CFG4 0x3108F010 +#define REG_CDU0_CFG5 0x3108F014 +#define REG_CDU0_CFG6 0x3108F018 +#define REG_CDU0_CFG7 0x3108F01C +#define REG_CDU0_CFG8 0x3108F020 +#define REG_CDU0_CFG9 0x3108F024 +#define REG_CDU0_CFG10 0x3108F028 +#define REG_CDU0_CFG11 0x3108F02C +#define REG_CDU0_CFG12 0x3108F030 +#define REG_CDU0_CFG13 0x3108F034 +#define REG_CDU0_CFG14 0x3108F038 +#define REG_CDU0_STAT 0x3108F040 +#define REG_CDU0_CLKINSEL 0x3108F044 +#define REG_CDU0_REVID 0x3108F048 + +#define BITM_REG10_MSEL3 0x000007F0 +#define BITP_REG10_MSEL3 4 + +#define BITM_REG10_DSEL3 0x0001F000 +#define BITP_REG10_DSEL3 12 + +/* Selected clock macros */ +#define CGUn_MULT(cgu) ((CONFIG_CGU##cgu##_VCO_MULT == 0) ? \ + 128 : CONFIG_CGU##cgu##_VCO_MULT) +#define CGUn_DIV(clkname, cgu) ((CONFIG_CGU##cgu##_##clkname##_DIV == 0) ? \ + 32 : CONFIG_CGU##cgu##_##clkname##_DIV) +#define CCLK1_n_RATIO(cgu) (((CGUn_MULT(cgu)) / \ + (1 + CONFIG_CGU##cgu##_DF_DIV)) / \ + CGUn_DIV(CCLK, cgu)) +#define CCLK2_n_RATIO(cgu) (((CGUn_MULT(cgu) * 2) / 3) / \ + (1 + CONFIG_CGU##cgu##_DF_DIV)) +#define DCLK_n_RATIO(cgu) (((CGUn_MULT(cgu)) / \ + (1 + CONFIG_CGU##cgu##_DF_DIV)) / \ + CGUn_DIV(DCLK, cgu)) +#define SYSCLK_n_RATIO(cgu) (((CGUn_MULT(cgu)) / \ + (1 + CONFIG_CGU##cgu##_DF_DIV)) / \ + CGUn_DIV(SCLK, cgu)) +#define PLL3_RATIO ((CONFIG_CGU1_PLL3_VCO_MSEL) / \ + (CONFIG_CGU1_PLL3_DCLK_DIV)) + +#if (1 == CONFIG_CDU0_CLKO2) + #define ARMCLK_IN 0 + #define ARMCLK_RATIO CCLK1_n_RATIO(0) +#elif (3 == CONFIG_CDU0_CLKO2) && \ + (defined(CONFIG_SC57X) || defined(CONFIG_SC58X)) + #define ARMCLK_IN 0 + #define ARMCLK_RATIO SYSCLK_n_RATIO(0) +#elif (5 == CONFIG_CDU0_CLKO2) && defined(CONFIG_SC59X_64) + #define ARMCLK_IN 0 + #define ARMCLK_RATIO CCLK2_n_RATIO(0) +#elif (7 == CONFIG_CDU0_CLKO2) && defined(CONFIG_SC59X_64) + #define ARMCLK_IN CDU0_CGU1_CLKIN + #define ARMCLK_RATIO CCLK2_n_RATIO(1) +#endif + +#ifdef CONFIG_CGU1_PLL3_DDRCLK + #define DDRCLK_IN CDU0_CGU1_CLKIN + #define DDRCLK_RATIO PLL3_RATIO +#elif (1 == CONFIG_CDU0_CLKO3) + #define DDRCLK_IN 0 + #define DDRCLK_RATIO DCLK_n_RATIO(0) +#elif (3 == CONFIG_CDU0_CLKO3) + #define DDRCLK_IN CDU0_CGU1_CLKIN + #define DDRCLK_RATIO DCLK_n_RATIO(1) +#endif + +#ifndef ARMCLK_RATIO + #error Invalid/unknown ARMCLK selection! +#endif +#ifndef DDRCLK_RATIO + #error Invalid/unknown DDRCLK selection! +#endif + +#define ARMDDR_CLK_RATIO_FPERCISION 1000 + +#if ARMCLK_IN != DDRCLK_IN + #ifndef CUSTOM_ARMDDR_CLK_RATIO + /** + * SYS_CLKINx are defined within the device tree, not configs. + * Thus, we can only determine cross-CGU clock ratios if they + * use the same SYS_CLKINx. + */ + #error Define CUSTOM_ARMDDR_CLK_RATIO for different SYS_CLKINs + #else + #define ARMDDR_CLK_RATIO CUSTOM_ARMDDR_CLK_RATIO + #endif +#else + #define ARMDDR_CLK_RATIO (ARMDDR_CLK_RATIO_FPERCISION *\ + ARMCLK_RATIO / DDRCLK_RATIO) +#endif + +void dmcdelay(uint32_t delay) +{ + /* There is no zero-overhead loop on ARM, so assume each iteration + * takes 4 processor cycles (based on examination of -O3 and -Ofast + * output). + */ + u32 i, remainder; + + /* Convert DDR cycles to core clock cycles */ + u32 f = delay * ARMDDR_CLK_RATIO; + + delay = f + 500; + delay /= ARMDDR_CLK_RATIO_FPERCISION; + + /* Round up to multiple of 4 */ + remainder = delay % 4; + if (remainder != 0u) + delay += (4u - remainder); + + for (i = 0; i < delay; i += 4) + asm("nop"); +} + +static void program_cgu(const struct CGU_Settings *cgu) +{ + const uintptr_t b = cgu->rbase; + const bool use_extension0 = cgu->divex_S0SELEX >= 0; + const bool use_extension1 = cgu->divex_S1SELEX >= 0; + u32 temp; + + temp = OSEL(cgu->div_OSEL); + temp |= SYSSEL(cgu->div_SYSSEL); + temp |= CSEL(cgu->div_CSEL); + temp |= DSEL(cgu->div_DSEL); + temp |= (S0SEL(cgu->div_S0SEL)); + temp |= (S1SEL(cgu->div_S1SEL)); + temp &= ~BITM_CGU_DIV_LOCK; + + //Put PLL in to Bypass Mode + writel(BITM_CGU_PLLCTL_PLLEN | BITM_CGU_PLLCTL_PLLBPST, + b + CGU_PLLCTL); + while (!(readl(b + CGU_STAT) & BITM_CGU_STAT_PLLBP)) + ; + + while (!((readl(b + CGU_STAT) & CGU_STAT_MASK) == CGU_STAT_ALGN_LOCK)) + ; + + dmcdelay(1000); + + writel(temp & (~BITM_CGU_DIV_ALGN) & (~BITM_CGU_DIV_UPDT), + b + CGU_DIV); + + dmcdelay(1000); + + temp = MSEL(cgu->ctl_MSEL) | DF(cgu->ctl_DF); + if (use_extension0) + temp |= BITM_CGU_CTL_S0SELEXEN; + if (use_extension1) + temp |= BITM_CGU_CTL_S1SELEXEN; + + writel(temp & (~BITM_CGU_CTL_LOCK), b + CGU_CTL); + + if (use_extension0 || use_extension1) { + u32 mask = BITM_CGU_CTL_S1SELEXEN | BITM_CGU_CTL_S0SELEXEN; + + while (!(readl(b + CGU_CTL) & mask)) + ; + + temp = readl(b + CGU_DIVEX); + + if (use_extension0) { + temp &= ~BITM_CGU_DIVEX_S0SELEX; + temp |= S0SELEX(cgu->divex_S0SELEX); + } + + if (use_extension1) { + temp &= ~BITM_CGU_DIVEX_S1SELEX; + temp |= S1SELEX(cgu->divex_S1SELEX); + } + + writel(temp, b + CGU_DIVEX); + } + + dmcdelay(1000); + + //Take PLL out of Bypass Mode + writel(BITM_CGU_PLLCTL_PLLEN | BITM_CGU_PLLCTL_PLLBPCL, + b + CGU_PLLCTL); + while ((readl(b + CGU_STAT) & + (BITM_CGU_STAT_PLLBP | BITM_CGU_STAT_CLKSALGN))) + ; + + dmcdelay(1000); + + if (cgu->clkoutsel >= 0) { + temp = readl(b + CGU_CLKOUTSEL); + temp &= ~BITM_CGU_CLKOUTSEL_CLKOUTSEL; + temp |= CLKOUTSEL(cgu->clkoutsel); + writel(temp, b + CGU_CLKOUTSEL); + } +} + +void adi_config_third_pll(void) +{ +#if defined(CONFIG_CGU1_PLL3_VCO_MSEL) && defined(CONFIG_CGU1_PLL3_DCLK_DIV) + u32 temp; + + u32 msel = CONFIG_CGU1_PLL3_VCO_MSEL - 1; + u32 dsel = CONFIG_CGU1_PLL3_DCLK_DIV - 1; + + temp = readl(REG_MISC_REG10_tst_addr); + temp &= 0xFFFE0000; + writel(temp, REG_MISC_REG10_tst_addr); + + dmcdelay(4000u); + + //update MSEL [10:4] + temp = readl(REG_MISC_REG10_tst_addr); + temp |= ((msel << BITP_REG10_MSEL3) & BITM_REG10_MSEL3); + writel(temp, REG_MISC_REG10_tst_addr); + + temp = readl(REG_MISC_REG10_tst_addr); + temp |= 0x2; + writel(temp, REG_MISC_REG10_tst_addr); + + dmcdelay(100000u); + + temp = readl(REG_MISC_REG10_tst_addr); + temp |= 0x1; + writel(temp, REG_MISC_REG10_tst_addr); + + temp = readl(REG_MISC_REG10_tst_addr); + temp |= 0x800; + writel(temp, REG_MISC_REG10_tst_addr); + + temp = readl(REG_MISC_REG10_tst_addr); + temp &= 0xFFFFF7F8; + writel(temp, REG_MISC_REG10_tst_addr); + + dmcdelay(4000u); + + temp = readl(REG_MISC_REG10_tst_addr); + temp |= ((dsel << BITP_REG10_DSEL3) & BITM_REG10_DSEL3); + writel(temp, REG_MISC_REG10_tst_addr); + + temp = readl(REG_MISC_REG10_tst_addr); + temp |= 0x4; + writel(temp, REG_MISC_REG10_tst_addr); + + dmcdelay(100000u); + + temp = readl(REG_MISC_REG10_tst_addr); + temp |= 0x1; + writel(temp, REG_MISC_REG10_tst_addr); + + temp = readl(REG_MISC_REG10_tst_addr); + temp |= 0x800; + writel(temp, REG_MISC_REG10_tst_addr); +#endif +} + +static void Active_To_Fullon(const struct CGU_Settings *pCGU) +{ + u32 tmp; + + while (1) { + tmp = readl(pCGU->rbase + CGU_STAT); + if ((tmp & BITM_CGU_STAT_PLLEN) && + (tmp & BITM_CGU_STAT_PLLBP)) + break; + } + + writel(BITM_CGU_PLLCTL_PLLBPCL, pCGU->rbase + CGU_PLLCTL); + + while (1) { + tmp = readl(pCGU->rbase + CGU_STAT); + if ((tmp & BITM_CGU_STAT_PLLEN) && + ~(tmp & BITM_CGU_STAT_PLLBP) && + ~(tmp & BITM_CGU_STAT_CLKSALGN)) + break; + } +} + +static void CGU_Init(const struct CGU_Settings *pCGU) +{ + const uintptr_t b = pCGU->rbase; + +#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) + if (readl(b + CGU_STAT) & BITM_CGU_STAT_PLLEN) + writel(BITM_CGU_PLLCTL_PLLEN, b + CGU_PLLCTL); + + dmcdelay(1000); +#endif + + /* Check if processor is in Active mode */ + if (readl(b + CGU_STAT) & BITM_CGU_STAT_PLLBP) + Active_To_Fullon(pCGU); + +#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) + dmcdelay(1000); +#endif + + program_cgu(pCGU); +} + +void cgu_init(void) +{ + const struct CGU_Settings dividers0 = { + .rbase = CGU0_REGBASE, + .ctl_MSEL = CONFIG_CGU0_VCO_MULT, + .ctl_DF = CONFIG_CGU0_DF_DIV, + .div_CSEL = CONFIG_CGU0_CCLK_DIV, + .div_SYSSEL = CONFIG_CGU0_SCLK_DIV, + .div_S0SEL = VAL_CGU0_SCLK0_DIV, + .div_S1SEL = VAL_CGU0_SCLK1_DIV, + .div_DSEL = CONFIG_CGU0_DCLK_DIV, + .div_OSEL = CONFIG_CGU0_OCLK_DIV, + .divex_S0SELEX = VAL_CGU0_DIV_S0SELEX, + .divex_S1SELEX = VAL_CGU0_DIV_S1SELEX, + .clkoutsel = VAL_CGU0_CLKOUTSEL, + }; + const struct CGU_Settings dividers1 = { + .rbase = CGU1_REGBASE, + .ctl_MSEL = CONFIG_CGU1_VCO_MULT, + .ctl_DF = CONFIG_CGU1_DF_DIV, + .div_CSEL = CONFIG_CGU1_CCLK_DIV, + .div_SYSSEL = CONFIG_CGU1_SCLK_DIV, + .div_S0SEL = VAL_CGU1_SCLK0_DIV, + .div_S1SEL = VAL_CGU1_SCLK1_DIV, + .div_DSEL = CONFIG_CGU1_DCLK_DIV, + .div_OSEL = CONFIG_CGU1_OCLK_DIV, + .divex_S0SELEX = VAL_CGU1_DIV_S0SELEX, + .divex_S1SELEX = VAL_CGU1_DIV_S1SELEX, + .clkoutsel = VAL_CGU1_CLKOUTSEL, + }; + + CGU_Init(÷rs0); + CGU_Init(÷rs1); +} + +#define CONFIGURE_CDU0(a, b, c) \ + writel(a, b); \ + while (readl(REG_CDU0_STAT) & (1 << (c))) + +void cdu_init(void) +{ + while (readl(REG_CDU0_STAT) & 0xffff) + ; + writel((CONFIG_CDU0_CGU1_CLKIN & 0x1), REG_CDU0_CLKINSEL); + + CONFIGURE_CDU0(CONFIG_CDU0_CLKO0, REG_CDU0_CFG0, 0); + CONFIGURE_CDU0(CONFIG_CDU0_CLKO1, REG_CDU0_CFG1, 1); + CONFIGURE_CDU0(CONFIG_CDU0_CLKO2, REG_CDU0_CFG2, 2); + CONFIGURE_CDU0(CONFIG_CDU0_CLKO3, REG_CDU0_CFG3, 3); + CONFIGURE_CDU0(CONFIG_CDU0_CLKO4, REG_CDU0_CFG4, 4); + CONFIGURE_CDU0(CONFIG_CDU0_CLKO5, REG_CDU0_CFG5, 5); + CONFIGURE_CDU0(CONFIG_CDU0_CLKO6, REG_CDU0_CFG6, 6); + CONFIGURE_CDU0(CONFIG_CDU0_CLKO7, REG_CDU0_CFG7, 7); + CONFIGURE_CDU0(CONFIG_CDU0_CLKO8, REG_CDU0_CFG8, 8); + CONFIGURE_CDU0(CONFIG_CDU0_CLKO9, REG_CDU0_CFG9, 9); +#ifdef CONFIG_CDU0_CLKO10 + CONFIGURE_CDU0(CONFIG_CDU0_CLKO10, REG_CDU0_CFG10, 10); +#endif +#ifdef CONFIG_CDU0_CLKO12 + CONFIGURE_CDU0(CONFIG_CDU0_CLKO12, REG_CDU0_CFG12, 12); +#endif +#ifdef CONFIG_CDU0_CLKO13 + CONFIGURE_CDU0(CONFIG_CDU0_CLKO13, REG_CDU0_CFG13, 13); +#endif +#ifdef CONFIG_CDU0_CLKO14 + CONFIGURE_CDU0(CONFIG_CDU0_CLKO14, REG_CDU0_CFG14, 14); +#endif +} + +void clks_init(void) +{ + adi_dmc_reset_lanes(true); + + cdu_init(); + cgu_init(); + + adi_config_third_pll(); + + adi_dmc_reset_lanes(false); +} diff --git a/arch/arm/mach-sc5xx/init/clkinit.h b/arch/arm/mach-sc5xx/init/clkinit.h new file mode 100644 index 00000000000..b05f4325bfc --- /dev/null +++ b/arch/arm/mach-sc5xx/init/clkinit.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison + * Contact: Greg Malysa + */ + +#ifndef CLKINIT_H_ +#define CLKINIT_H_ + +void clks_init(void); + +void dmcdelay(uint32_t delay); + +#endif diff --git a/arch/arm/mach-sc5xx/init/dmcinit.c b/arch/arm/mach-sc5xx/init/dmcinit.c new file mode 100644 index 00000000000..e375b5c9dfa --- /dev/null +++ b/arch/arm/mach-sc5xx/init/dmcinit.c @@ -0,0 +1,954 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison + * Contact: Greg Malysa + */ + +#include +#include +#include +#include "clkinit.h" +#include "dmcinit.h" + +#define REG_DMC0_BASE 0x31070000 +#define REG_DMC1_BASE 0x31073000 + +#define REG_DMC_CTL 0x0004 // Control Register +#define REG_DMC_STAT 0x0008 // Status Register +#define REG_DMC_CFG 0x0040 // Configuration Register +#define REG_DMC_TR0 0x0044 // Timing 0 Register +#define REG_DMC_TR1 0x0048 // Timing 1 Register +#define REG_DMC_TR2 0x004C // Timing 2 Register +#define REG_DMC_MR 0x0060 // Shadow MR Register (DDR3) +#define REG_DMC_EMR1 0x0064 // Shadow EMR1 Register +#define REG_DMC_EMR2 0x0068 // Shadow EMR2 Register +#define REG_DMC_EMR3 0x006C +#define REG_DMC_DLLCTL 0x0080 // DLL Control Register +#define REG_DMC_DT_CALIB_ADDR 0x0090 // Data Calibration Address Register +#define REG_DMC_CPHY_CTL 0x01C0 // Controller to PHY Interface Register + +/* SC57x && SC58x DMC REGs */ +#define REG_DMC_PHY_CTL0 0x1000 // PHY Control 0 Register +#define REG_DMC_PHY_CTL1 0x1004 // PHY Control 1 Register +#define REG_DMC_PHY_CTL2 0x1008 // PHY Control 2 Register +#define REG_DMC_PHY_CTL3 0x100c // PHY Control 3 Register +#define REG_DMC_PHY_CTL4 0x1010 // PHY Control 4 Register +#define REG_DMC_CAL_PADCTL0 0x1034 // CALIBRATION PAD CTL 0 Register +#define REG_DMC_CAL_PADCTL2 0x103C // CALIBRATION PAD CTL2 Register +/* END */ + +/* SC59x DMC REGs */ +#define REG_DMC_DDR_LANE0_CTL0 0x1000 // Data Lane 0 Control Register 0 +#define REG_DMC_DDR_LANE0_CTL1 0x1004 // Data Lane 0 Control Register 1 +#define REG_DMC_DDR_LANE1_CTL0 0x100C // Data Lane 1 Control Register 0 +#define REG_DMC_DDR_LANE1_CTL1 0x1010 // Data Lane 1 Control Register 1 +#define REG_DMC_DDR_ROOT_CTL 0x1018 // DDR ROOT Module Control Register +#define REG_DMC_DDR_ZQ_CTL0 0x1034 // DDR Calibration Control Register 0 +#define REG_DMC_DDR_ZQ_CTL1 0x1038 // DDR Calibration Control Register 1 +#define REG_DMC_DDR_ZQ_CTL2 0x103C // DDR Calibration Control Register 2 +#define REG_DMC_DDR_CA_CTL 0x1068 // DDR CA Lane Control Register +/* END */ + +#define REG_DMC_DDR_SCRATCH_2 0x1074 +#define REG_DMC_DDR_SCRATCH_3 0x1078 +#define REG_DMC_DDR_SCRATCH_6 0x1084 +#define REG_DMC_DDR_SCRATCH_7 0x1088 + +#define REG_DMC_DDR_SCRATCH_STAT0 0x107C +#define REG_DMC_DDR_SCRATCH_STAT1 0x1080 + +#define DMC0_DATA_CALIB_ADD 0x80000000 +#define DMC1_DATA_CALIB_ADD 0xC0000000 + +#define BITM_DMC_CFG_EXTBANK 0x0000F000 /* External Banks */ +#define ENUM_DMC_CFG_EXTBANK1 0x00000000 /* EXTBANK: 1 External Bank */ +#define BITM_DMC_CFG_SDRSIZE 0x00000F00 /* SDRAM Size */ +#define ENUM_DMC_CFG_SDRSIZE64 0x00000000 /* SDRSIZE: 64M Bit SDRAM (LPDDR Only) */ +#define ENUM_DMC_CFG_SDRSIZE128 0x00000100 /* SDRSIZE: 128M Bit SDRAM (LPDDR Only) */ +#define ENUM_DMC_CFG_SDRSIZE256 0x00000200 /* SDRSIZE: 256M Bit SDRAM */ +#define ENUM_DMC_CFG_SDRSIZE512 0x00000300 /* SDRSIZE: 512M Bit SDRAM */ +#define ENUM_DMC_CFG_SDRSIZE1G 0x00000400 /* SDRSIZE: 1G Bit SDRAM */ +#define ENUM_DMC_CFG_SDRSIZE2G 0x00000500 /* SDRSIZE: 2G Bit SDRAM */ +#define ENUM_DMC_CFG_SDRSIZE4G 0x00000600 /* SDRSIZE: 4G Bit SDRAM */ +#define ENUM_DMC_CFG_SDRSIZE8G 0x00000700 /* SDRSIZE: 8G Bit SDRAM */ +#define BITM_DMC_CFG_SDRWID 0x000000F0 /* SDRAM Width */ +#define ENUM_DMC_CFG_SDRWID16 0x00000020 /* SDRWID: 16-Bit Wide SDRAM */ +#define BITM_DMC_CFG_IFWID 0x0000000F /* Interface Width */ +#define ENUM_DMC_CFG_IFWID16 0x00000002 /* IFWID: 16-Bit Wide Interface */ + +#define BITM_DMC_CTL_DDR3EN 0x00000001 +#define BITM_DMC_CTL_INIT 0x00000004 +#define BITP_DMC_STAT_INITDONE 2 /* Initialization Done */ +#define BITM_DMC_STAT_INITDONE 0x00000004 + +#define BITP_DMC_CTL_AL_EN 27 +#define BITP_DMC_CTL_ZQCL 25 /* ZQ Calibration Long */ +#define BITP_DMC_CTL_ZQCS 24 /* ZQ Calibration Short */ +#define BITP_DMC_CTL_DLLCAL 13 /* DLL Calibration Start */ +#define BITP_DMC_CTL_PPREF 12 /* Postpone Refresh */ +#define BITP_DMC_CTL_RDTOWR 9 /* Read-to-Write Cycle */ +#define BITP_DMC_CTL_ADDRMODE 8 /* Addressing (Page/Bank) Mode */ +#define BITP_DMC_CTL_RESET 7 /* Reset SDRAM */ +#define BITP_DMC_CTL_PREC 6 /* Precharge */ +#define BITP_DMC_CTL_DPDREQ 5 /* Deep Power Down Request */ +#define BITP_DMC_CTL_PDREQ 4 /* Power Down Request */ +#define BITP_DMC_CTL_SRREQ 3 /* Self Refresh Request */ +#define BITP_DMC_CTL_INIT 2 /* Initialize DRAM Start */ +#define BITP_DMC_CTL_LPDDR 1 /* Low Power DDR Mode */ +#define BITP_DMC_CTL_DDR3EN 0 /* DDR3 Mode */ + +#ifdef CONFIG_TARGET_SC584_EZKIT + #define DMC_PADCTL2_VALUE 0x0078283C +#elif CONFIG_TARGET_SC573_EZKIT + #define DMC_PADCTL2_VALUE 0x00782828 +#elif CONFIG_TARGET_SC589_MINI || CONFIG_TARGET_SC589_EZKIT + #define DMC_PADCTL2_VALUE 0x00783C3C +#elif defined(CONFIG_SC57X) || defined(CONFIG_SC58X) + #error "PADCTL2 not specified for custom board!" +#else + //Newer DMC. Legacy calibration obsolete + #define DMC_PADCTL2_VALUE 0x0 +#endif + +#define DMC_CPHYCTL_VALUE 0x0000001A + +#define BITP_DMC_MR1_QOFF 12 /* Output Buffer Enable */ +#define BITP_DMC_MR1_TDQS 11 /* Termination Data Strobe */ +#define BITP_DMC_MR1_RTT2 9 /* Rtt_nom */ +#define BITP_DMC_MR1_WL 7 /* Write Leveling Enable. */ +#define BITP_DMC_MR1_RTT1 6 /* Rtt_nom */ +#define BITP_DMC_MR1_DIC1 5 /* Output Driver Impedance Control */ +#define BITP_DMC_MR1_AL 3 /* Additive Latency */ +#define BITP_DMC_MR1_RTT0 2 /* Rtt_nom */ +#define BITP_DMC_MR1_DIC0 1 /* Output Driver Impedance control */ +#define BITP_DMC_MR1_DLLEN 0 /* DLL Enable */ + +#define BITP_DMC_MR2_CWL 3 /* CAS write Latency */ + +#define BITP_DMC_TR0_TMRD 28 /* Timing Mode Register Delay */ +#define BITP_DMC_TR0_TRC 20 /* Timing Row Cycle */ +#define BITP_DMC_TR0_TRAS 12 /* Timing Row Active Time */ +#define BITP_DMC_TR0_TRP 8 /* Timing RAS Precharge. */ +#define BITP_DMC_TR0_TWTR 4 /* Timing Write to Read */ +#define BITP_DMC_TR0_TRCD 0 /* Timing RAS to CAS Delay */ + +#define BITP_DMC_TR1_TRRD 28 /* Timing Read-Read Delay */ +#define BITP_DMC_TR1_TRFC 16 /* Timing Refresh-to-Command */ +#define BITP_DMC_TR1_TREF 0 /* Timing Refresh Interval */ + +#define BITP_DMC_TR2_TCKE 20 /* Timing Clock Enable */ +#define BITP_DMC_TR2_TXP 16 /* Timing Exit Powerdown */ +#define BITP_DMC_TR2_TWR 12 /* Timing Write Recovery */ +#define BITP_DMC_TR2_TRTP 8 /* Timing Read-to-Precharge */ +#define BITP_DMC_TR2_TFAW 0 /* Timing Four-Activated-Window */ + +#define BITP_DMC_MR_PD 12 /* Active Powerdown Mode */ +#define BITP_DMC_MR_WRRECOV 9 /* Write Recovery */ +#define BITP_DMC_MR_DLLRST 8 /* DLL Reset */ +#define BITP_DMC_MR_CL 4 /* CAS Latency */ +#define BITP_DMC_MR_CL0 2 /* CAS Latency */ +#define BITP_DMC_MR_BLEN 0 /* Burst Length */ + +#define BITP_DMC_DLLCTL_DATACYC 8 /* Data Cycles */ +#define BITP_DMC_DLLCTL_DLLCALRDCNT 0 /* DLL Calibration RD Count */ + +#define BITM_DMC_DLLCTL_DATACYC 0x00000F00 /* Data Cycles */ +#define BITM_DMC_DLLCTL_DLLCALRDCNT 0x000000FF /* DLL Calib RD Count */ + +#define BITP_DMC_STAT_PHYRDPHASE 20 /* PHY Read Phase */ + +#define BITM_DMC_DDR_LANE0_CTL0_CB_RSTDAT 0x08000000 /* Rst Data Pads */ +#define BITM_DMC_DDR_LANE1_CTL0_CB_RSTDAT 0x08000000 /* Rst Data Pads */ +#define BITM_DMC_DDR_LANE0_CTL1_COMP_DCYCLE 0x00000002 /* Compute Dcycle */ +#define BITM_DMC_DDR_LANE1_CTL1_COMP_DCYCLE 0x00000002 /* Compute Dcycle */ +#define BITM_DMC_DDR_LANE1_CTL0_CB_RSTDLL 0x00000100 /* Rst Lane DLL */ +#define BITM_DMC_DDR_LANE0_CTL0_CB_RSTDLL 0x00000100 /* Rst Lane DLL */ +#define BITP_DMC_DDR_ROOT_CTL_PIPE_OFSTDCYCLE 10 /* Pipeline offset for PHYC_DATACYCLE */ +#define BITM_DMC_DDR_ROOT_CTL_SW_REFRESH 0x00002000 /* Refresh Lane DLL Code */ +#define BITM_DMC_DDR_CA_CTL_SW_REFRESH 0x00004000 /* Refresh Lane DLL Code */ + +#define BITP_DMC_CTL_RL_DQS 26 /* RL_DQS */ +#define BITM_DMC_CTL_RL_DQS 0x04000000 /* RL_DQS */ +#define BITP_DMC_EMR3_MPR 2 /* Multi Purpose Read Enable (Read Leveling)*/ +#define BITM_DMC_EMR3_MPR 0x00000004 /* Multi Purpose Read Enable (Read Leveling)*/ +#define BITM_DMC_MR1_WL 0x00000080 /* Write Leveling Enable.*/ +#define BITM_DMC_STAT_PHYRDPHASE 0x00F00000 /* PHY Read Phase */ + +#define BITP_DMC_DDR_LANE0_CTL1_BYPCODE 10 +#define BITM_DMC_DDR_LANE0_CTL1_BYPCODE 0x00007C00 +#define BITP_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN 15 +#define BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN 0x00008000 + +#define DMC_ZQCTL0_VALUE 0x00785A64 +#define DMC_ZQCTL1_VALUE 0 +#define DMC_ZQCTL2_VALUE 0x70000000 + +#define DMC_TRIG_CALIB 0 +#define DMC_OFSTDCYCLE 2 + +#define BITP_DMC_CAL_PADCTL0_RTTCALEN 31 /* RTT Calibration Enable */ +#define BITP_DMC_CAL_PADCTL0_PDCALEN 30 /* PULLDOWN Calib Enable */ +#define BITP_DMC_CAL_PADCTL0_PUCALEN 29 /* PULLUP Calib Enable */ +#define BITP_DMC_CAL_PADCTL0_CALSTRT 28 /* Start New Calib ( Hardware Cleared) */ +#define BITM_DMC_CAL_PADCTL0_RTTCALEN 0x80000000 /* RTT Calibration Enable */ +#define BITM_DMC_CAL_PADCTL0_PDCALEN 0x40000000 /* PULLDOWN Calib Enable */ +#define BITM_DMC_CAL_PADCTL0_PUCALEN 0x20000000 /* PULLUP Calib Enable */ +#define BITM_DMC_CAL_PADCTL0_CALSTRT 0x10000000 /* Start New Calib ( Hardware Cleared) */ +#define ENUM_DMC_PHY_CTL4_DDR3 0x00000000 /* DDRMODE: DDR3 Mode */ +#define ENUM_DMC_PHY_CTL4_DDR2 0x00000001 /* DDRMODE: DDR2 Mode */ +#define ENUM_DMC_PHY_CTL4_LPDDR 0x00000003 /* DDRMODE: LPDDR Mode */ + +#define BITP_DMC_DDR_ZQ_CTL0_IMPRTT 16 /* Data/DQS ODT */ +#define BITP_DMC_DDR_ZQ_CTL0_IMPWRDQ 8 /* Data/DQS/DM/CLK Drive Strength */ +#define BITP_DMC_DDR_ZQ_CTL0_IMPWRADD 0 /* Address/Command Drive Strength */ +#define BITM_DMC_DDR_ZQ_CTL0_IMPRTT 0x00FF0000 /* Data/DQS ODT */ +#define BITM_DMC_DDR_ZQ_CTL0_IMPWRDQ 0x0000FF00 /* Data/DQS/DM/CLK Drive Strength */ +#define BITM_DMC_DDR_ZQ_CTL0_IMPWRADD 0x000000FF /* Address/Command Drive Strength */ + +#define BITM_DMC_DDR_ROOT_CTL_TRIG_RD_XFER_ALL 0x00200000 /* All Lane Read Status */ + +#if defined(CONFIG_ADI_USE_DDR2) + #define DMC_MR0_VALUE \ + ((DMC_BL / 4 + 1) << BITP_DMC_MR_BLEN) | \ + (DMC_CL << BITP_DMC_MR_CL) | \ + (DMC_WRRECOV << BITP_DMC_MR_WRRECOV) + + #define DMC_MR1_VALUE \ + (DMC_MR1_AL << BITP_DMC_MR1_AL | 0x04) \ + + #define DMC_MR2_VALUE 0 + #define DMC_MR3_VALUE 0 + + #define DMC_CTL_VALUE \ + (DMC_RDTOWR << BITP_DMC_CTL_RDTOWR) | \ + (1 << BITP_DMC_CTL_DLLCAL) | \ + (BITM_DMC_CTL_INIT) +#else + #define DMC_MR0_VALUE \ + (0 << BITP_DMC_MR_BLEN) | \ + (DMC_CL0 << BITP_DMC_MR_CL0) | \ + (DMC_CL123 << BITP_DMC_MR_CL) | \ + (DMC_WRRECOV << BITP_DMC_MR_WRRECOV) | \ + (1 << BITP_DMC_MR_DLLRST) + + #define DMC_MR1_VALUE \ + (DMC_MR1_DLLEN << BITP_DMC_MR1_DLLEN) | \ + (DMC_MR1_DIC0 << BITP_DMC_MR1_DIC0) | \ + (DMC_MR1_RTT0 << BITP_DMC_MR1_RTT0) | \ + (DMC_MR1_AL << BITP_DMC_MR1_AL) | \ + (DMC_MR1_DIC1 << BITP_DMC_MR1_DIC1) | \ + (DMC_MR1_RTT1 << BITP_DMC_MR1_RTT1) | \ + (DMC_MR1_RTT2 << BITP_DMC_MR1_RTT2) | \ + (DMC_MR1_WL << BITP_DMC_MR1_WL) | \ + (DMC_MR1_TDQS << BITP_DMC_MR1_TDQS) | \ + (DMC_MR1_QOFF << BITP_DMC_MR1_QOFF) + + #define DMC_MR2_VALUE \ + ((DMC_WL) << BITP_DMC_MR2_CWL) + + #define DMC_MR3_VALUE \ + ((DMC_WL) << BITP_DMC_MR2_CWL) + + #define DMC_CTL_VALUE \ + (DMC_RDTOWR << BITP_DMC_CTL_RDTOWR) | \ + (BITM_DMC_CTL_INIT) | \ + (BITM_DMC_CTL_DDR3EN) | \ + (DMC_CTL_AL_EN << BITP_DMC_CTL_AL_EN) +#endif + +#define DMC_DLLCTL_VALUE \ + (DMC_DATACYC << BITP_DMC_DLLCTL_DATACYC) | \ + (DMC_DLLCALRDCNT << BITP_DMC_DLLCTL_DLLCALRDCNT) + +#define DMC_CFG_VALUE \ + ENUM_DMC_CFG_IFWID16 | \ + ENUM_DMC_CFG_SDRWID16 | \ + SDR_CHIP_SIZE | \ + ENUM_DMC_CFG_EXTBANK1 + +#define DMC_TR0_VALUE \ + (DMC_TRCD << BITP_DMC_TR0_TRCD) | \ + (DMC_TWTR << BITP_DMC_TR0_TWTR) | \ + (DMC_TRP << BITP_DMC_TR0_TRP) | \ + (DMC_TRAS << BITP_DMC_TR0_TRAS) | \ + (DMC_TRC << BITP_DMC_TR0_TRC) | \ + (DMC_TMRD << BITP_DMC_TR0_TMRD) + +#define DMC_TR1_VALUE \ + (DMC_TREF << BITP_DMC_TR1_TREF) | \ + (DMC_TRFC << BITP_DMC_TR1_TRFC) | \ + (DMC_TRRD << BITP_DMC_TR1_TRRD) + +#define DMC_TR2_VALUE \ + (DMC_TFAW << BITP_DMC_TR2_TFAW) | \ + (DMC_TRTP << BITP_DMC_TR2_TRTP) | \ + (DMC_TWR << BITP_DMC_TR2_TWR) | \ + (DMC_TXP << BITP_DMC_TR2_TXP) | \ + (DMC_TCKE << BITP_DMC_TR2_TCKE) + +enum DDR_MODE { + DDR3_MODE, + DDR2_MODE, + LPDDR_MODE, +}; + +enum CALIBRATION_MODE { + CALIBRATION_LEGACY, + CALIBRATION_METHOD1, + CALIBRATION_METHOD2, +}; + +static struct dmc_param { + phys_addr_t reg; + u32 ddr_mode; + u32 padctl2_value; + u32 dmc_cphyctl_value; + u32 dmc_cfg_value; + u32 dmc_dllctl_value; + u32 dmc_ctl_value; + u32 dmc_tr0_value; + u32 dmc_tr1_value; + u32 dmc_tr2_value; + u32 dmc_mr0_value; + u32 dmc_mr1_value; + u32 dmc_mr2_value; + u32 dmc_mr3_value; + u32 dmc_zqctl0_value; + u32 dmc_zqctl1_value; + u32 dmc_zqctl2_value; + u32 dmc_data_calib_add_value; + bool phy_init_required; + bool anomaly_20000037_applicable; + enum CALIBRATION_MODE calib_mode; +} dmc; + +#ifdef CONFIG_SC59X_64 +#define DQS_DEFAULT_DELAY 3ul + +#define DELAYTRIM 1 +#define LANE0_DQS_DELAY 1 +#define LANE1_DQS_DELAY 1 + +#define CLKDIR 0ul + +#define DQSTRIM 0 +#define DQSCODE 0ul + +#define CLKTRIM 0 +#define CLKCODE 0ul +#endif + +static inline void calibration_legacy(void) +{ + u32 temp; + + /* 1. Set DDR mode to DDR3/DDR2/LPDDR in DMCx_PHY_CTL4 register */ + if (dmc.ddr_mode == DDR3_MODE) + writel(ENUM_DMC_PHY_CTL4_DDR3, dmc.reg + REG_DMC_PHY_CTL4); + else if (dmc.ddr_mode == DDR2_MODE) + writel(ENUM_DMC_PHY_CTL4_DDR2, dmc.reg + REG_DMC_PHY_CTL4); + else if (dmc.ddr_mode == LPDDR_MODE) + writel(ENUM_DMC_PHY_CTL4_LPDDR, dmc.reg + REG_DMC_PHY_CTL4); + + /* + * 2. Make sure that the bits 6, 7, 25, and 27 of the DMC_PHY_ + * CTL3 register are set + */ + writel(0x0A0000C0, dmc.reg + REG_DMC_PHY_CTL3); + + /* + * 3. For DDR2/DDR3 mode, make sure that the bits 0, 1, 2, 3 of + * the DMC_PHY_CTL0 register and the bits 26, 27, 28, 29, 30, 31 + * of the DMC_PHY_CTL2 are set. + */ + if (dmc.ddr_mode == DDR3_MODE || + dmc.ddr_mode == DDR2_MODE) { + writel(0XFC000000, dmc.reg + REG_DMC_PHY_CTL2); + writel(0x0000000f, dmc.reg + REG_DMC_PHY_CTL0); + } + + writel(0x00000000, dmc.reg + REG_DMC_PHY_CTL1); + + /* 4. For DDR3 mode, set bit 1 and configure bits [5:2] of the + * DMC_CPHY_CTL register with WL=CWL+AL in DCLK cycles. + */ + if (dmc.ddr_mode == DDR3_MODE) + writel(dmc.dmc_cphyctl_value, dmc.reg + REG_DMC_CPHY_CTL); + /* 5. Perform On Die Termination(ODT) & Driver Impedance Calibration */ + if (dmc.ddr_mode == LPDDR_MODE) { + /* Bypass processor ODT */ + writel(0x80000, dmc.reg + REG_DMC_PHY_CTL1); + } else { + /* Set bits RTTCALEN, PDCALEN, PUCALEN of register */ + temp = BITM_DMC_CAL_PADCTL0_RTTCALEN | + BITM_DMC_CAL_PADCTL0_PDCALEN | + BITM_DMC_CAL_PADCTL0_PUCALEN; + writel(temp, dmc.reg + REG_DMC_CAL_PADCTL0); + /* Configure ODT and drive impedance values in the + * DMCx_CAL_PADCTL2 register + */ + writel(dmc.padctl2_value, dmc.reg + REG_DMC_CAL_PADCTL2); + /* start calibration */ + temp |= BITM_DMC_CAL_PADCTL0_CALSTRT; + writel(temp, dmc.reg + REG_DMC_CAL_PADCTL0); + /* Wait for PAD calibration to complete - 300 DCLK cycle. + * Worst case: CCLK=450 MHz, DCLK=125 MHz + */ + dmcdelay(300); + } +} + +static inline void calibration_method1(void) +{ +#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) + writel(dmc.dmc_zqctl0_value, dmc.reg + REG_DMC_DDR_ZQ_CTL0); + writel(dmc.dmc_zqctl1_value, dmc.reg + REG_DMC_DDR_ZQ_CTL1); + writel(dmc.dmc_zqctl2_value, dmc.reg + REG_DMC_DDR_ZQ_CTL2); + + /* Generate the trigger */ + writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL); + writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); + writel(0x00010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); + dmcdelay(8000u); + + /* The [31:26] bits may change if pad ring changes */ + writel(0x0C000001ul | DMC_TRIG_CALIB, dmc.reg + REG_DMC_DDR_CA_CTL); + dmcdelay(8000u); + writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL); + writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); +#endif +} + +static inline void calibration_method2(void) +{ +#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) + u32 stat_value = 0x0u; + u32 drv_pu, drv_pd, odt_pu, odt_pd; + u32 ro_dt, clk_dqs_drv_impedance; + u32 temp; + + /* Reset trigger */ + writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL); + writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); + writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_3); + writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_2); + + /* Writing internal registers in calib pad to zero. Calib mode set + * to 1 [26], trig M1 S1 write [16], this enables usage of scratch + * registers instead of ZQCTL registers + */ + writel(0x04010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); + dmcdelay(2500u); + + /* TRIGGER FOR M2-S2 WRITE -> slave id 31:26 trig m2,s2 write + * bit 1->1 slave1 address is 4 + */ + writel(0x10000002ul, dmc.reg + REG_DMC_DDR_CA_CTL); + dmcdelay(2500u); + + /* reset Trigger */ + writel(0x0u, dmc.reg + REG_DMC_DDR_CA_CTL); + writel(0x0u, dmc.reg + REG_DMC_DDR_ROOT_CTL); + + /* write to slave 1, make the power down bit high */ + writel(0x1ul << 12, dmc.reg + REG_DMC_DDR_SCRATCH_3); + writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_2); + dmcdelay(2500u); + + /* Calib mode set to 1 [26], trig M1 S1 write [16] */ + writel(0x04010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); + dmcdelay(2500u); + + writel(0x10000002ul, dmc.reg + REG_DMC_DDR_CA_CTL); + dmcdelay(2500u); + + writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL); + writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); + writel(0x0, dmc.reg + REG_DMC_DDR_SCRATCH_3); + + /* for slave 0 */ + writel(dmc.dmc_zqctl0_value, dmc.reg + REG_DMC_DDR_SCRATCH_2); + + /* Calib mode set to 1 [26], trig M1 S1 write [16] */ + writel(0x04010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); + dmcdelay(2500u); + + writel(0x0C000002ul, dmc.reg + REG_DMC_DDR_CA_CTL); + dmcdelay(2500u); + + writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL); + writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); + + /* writing to slave 1 + * calstrt is 0, but other programming is done + * + * make power down LOW again, to kickstart BIAS circuit + */ + writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_3); + writel(0x30000000ul, dmc.reg + REG_DMC_DDR_SCRATCH_2); + + /* write to ca_ctl lane, calib mode set to 1 [26], + * trig M1 S1 write [16] + */ + writel(0x04010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); + dmcdelay(2500u); + + /* copies data to lane controller slave + * TRIGGER FOR M2-S2 WRITE -> slave id 31:26 + * trig m2,s2 write bit 1->1 + * slave1 address is 4 + */ + writel(0x10000002ul, dmc.reg + REG_DMC_DDR_CA_CTL); + dmcdelay(2500u); + + /* reset Trigger */ + writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL); + writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); + writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_3); + writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_2); + writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_3); + writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_2); + writel(0x04010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); + dmcdelay(2500u); + writel(0x10000002ul, dmc.reg + REG_DMC_DDR_CA_CTL); + dmcdelay(2500u); + writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL); + writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); + writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_3); + writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_2); + writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_3); + writel(0x50000000ul, dmc.reg + REG_DMC_DDR_SCRATCH_2); + writel(0x04010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); + dmcdelay(2500u); + writel(0x10000002ul, dmc.reg + REG_DMC_DDR_CA_CTL); + dmcdelay(2500u); + writel(0u, dmc.reg + REG_DMC_DDR_CA_CTL); + writel(0u, dmc.reg + REG_DMC_DDR_ROOT_CTL); + writel(0x0C000004u, dmc.reg + REG_DMC_DDR_CA_CTL); + dmcdelay(2500u); + writel(BITM_DMC_DDR_ROOT_CTL_TRIG_RD_XFER_ALL, + dmc.reg + REG_DMC_DDR_ROOT_CTL); + dmcdelay(2500u); + writel(0u, dmc.reg + REG_DMC_DDR_CA_CTL); + writel(0u, dmc.reg + REG_DMC_DDR_ROOT_CTL); + // calculate ODT PU and PD values + stat_value = ((readl(dmc.reg + REG_DMC_DDR_SCRATCH_7) & 0x0000FFFFu) << + 16); + stat_value |= ((readl(dmc.reg + REG_DMC_DDR_SCRATCH_6) & 0xFFFF0000u) >> + 16); + clk_dqs_drv_impedance = ((dmc.dmc_zqctl0_value) & + BITM_DMC_DDR_ZQ_CTL0_IMPWRDQ) >> BITP_DMC_DDR_ZQ_CTL0_IMPWRDQ; + ro_dt = ((dmc.dmc_zqctl0_value) & BITM_DMC_DDR_ZQ_CTL0_IMPRTT) >> + BITP_DMC_DDR_ZQ_CTL0_IMPRTT; + drv_pu = stat_value & 0x0000003Fu; + drv_pd = (stat_value >> 12) & 0x0000003Fu; + odt_pu = (drv_pu * clk_dqs_drv_impedance) / ro_dt; + odt_pd = (drv_pd * clk_dqs_drv_impedance) / ro_dt; + temp = ((1uL << 24) | + ((drv_pd & 0x0000003Fu)) | + ((odt_pd & 0x0000003Fu) << 6) | + ((drv_pu & 0x0000003Fu) << 12) | + ((odt_pu & 0x0000003Fu) << 18)); + temp |= readl(dmc.reg + REG_DMC_DDR_SCRATCH_2); + writel(temp, dmc.reg + REG_DMC_DDR_SCRATCH_2); + writel(0x0C010000u, dmc.reg + REG_DMC_DDR_ROOT_CTL); + dmcdelay(2500u); + writel(0x08000002u, dmc.reg + REG_DMC_DDR_CA_CTL); + dmcdelay(2500u); + writel(0u, dmc.reg + REG_DMC_DDR_CA_CTL); + writel(0u, dmc.reg + REG_DMC_DDR_ROOT_CTL); + writel(0x04010000u, dmc.reg + REG_DMC_DDR_ROOT_CTL); + dmcdelay(2500u); + writel(0x80000002u, dmc.reg + REG_DMC_DDR_CA_CTL); + dmcdelay(2500u); + writel(0u, dmc.reg + REG_DMC_DDR_CA_CTL); + writel(0u, dmc.reg + REG_DMC_DDR_ROOT_CTL); +#endif +} + +static inline void adi_dmc_lane_reset(bool reset, uint32_t dmc_no) +{ +#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) + u32 temp; + phys_addr_t base = (dmc_no == 0) ? REG_DMC0_BASE : REG_DMC1_BASE; + phys_addr_t ln0 = base + REG_DMC_DDR_LANE0_CTL0; + phys_addr_t ln1 = base + REG_DMC_DDR_LANE1_CTL0; + + if (reset) { + temp = readl(ln0); + temp |= BITM_DMC_DDR_LANE0_CTL0_CB_RSTDLL; + writel(temp, ln0); + + temp = readl(ln1); + temp |= BITM_DMC_DDR_LANE1_CTL0_CB_RSTDLL; + writel(temp, ln1); + } else { + temp = readl(ln0); + temp &= ~BITM_DMC_DDR_LANE0_CTL0_CB_RSTDLL; + writel(temp, ln0); + + temp = readl(ln1); + temp &= ~BITM_DMC_DDR_LANE1_CTL0_CB_RSTDLL; + writel(temp, ln1); + } + dmcdelay(9000u); +#endif +} + +void adi_dmc_reset_lanes(bool reset) +{ + if (!IS_ENABLED(CONFIG_ADI_USE_DDR2)) { + if (IS_ENABLED(CONFIG_SC59X) || IS_ENABLED(CONFIG_SC59X_64)) { + if (IS_ENABLED(CONFIG_ADI_USE_DMC0)) + adi_dmc_lane_reset(reset, 0); + if (IS_ENABLED(CONFIG_ADI_USE_DMC1)) + adi_dmc_lane_reset(reset, 1); + } + else { + u32 temp = reset ? 0x800 : 0x0; + + if (IS_ENABLED(CONFIG_ADI_USE_DMC0)) + writel(temp, REG_DMC0_BASE + REG_DMC_PHY_CTL0); + if (IS_ENABLED(CONFIG_ADI_USE_DMC1)) + writel(temp, REG_DMC1_BASE + REG_DMC_PHY_CTL0); + } + } +} + +static inline void dmc_controller_init(void) +{ +#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) + u32 phyphase, rd_cnt, t_EMR1, t_EMR3, t_CTL, data_cyc, temp; +#endif + + /* 1. Program the DMC controller registers: DMCx_CFG, DMCx_TR0, + * DMCx_TR1, DMCx_TR2, DMCx_MR(DDR2/LPDDR)/DMCx_MR0(DDR3), + * DMCx_EMR1(DDR2)/DMCx_MR1(DDR3), + * DMCx_EMR2(DDR2)/DMCx_EMR(LPDDR)/DMCx_MR2(DDR3) + */ + writel(dmc.dmc_cfg_value, dmc.reg + REG_DMC_CFG); + writel(dmc.dmc_tr0_value, dmc.reg + REG_DMC_TR0); + writel(dmc.dmc_tr1_value, dmc.reg + REG_DMC_TR1); + writel(dmc.dmc_tr2_value, dmc.reg + REG_DMC_TR2); + writel(dmc.dmc_mr0_value, dmc.reg + REG_DMC_MR); + writel(dmc.dmc_mr1_value, dmc.reg + REG_DMC_EMR1); + writel(dmc.dmc_mr2_value, dmc.reg + REG_DMC_EMR2); + +#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) + writel(dmc.dmc_mr3_value, dmc.reg + REG_DMC_EMR3); + writel(dmc.dmc_dllctl_value, dmc.reg + REG_DMC_DLLCTL); + dmcdelay(2000u); + + temp = readl(dmc.reg + REG_DMC_DDR_CA_CTL); + temp |= BITM_DMC_DDR_CA_CTL_SW_REFRESH; + writel(temp, dmc.reg + REG_DMC_DDR_CA_CTL); + dmcdelay(5u); + + temp = readl(dmc.reg + REG_DMC_DDR_ROOT_CTL); + temp |= BITM_DMC_DDR_ROOT_CTL_SW_REFRESH | + (DMC_OFSTDCYCLE << BITP_DMC_DDR_ROOT_CTL_PIPE_OFSTDCYCLE); + writel(temp, dmc.reg + REG_DMC_DDR_ROOT_CTL); +#endif + + /* 2. Make sure that the REG_DMC_DT_CALIB_ADDR register is programmed + * to an unused DMC location corresponding to a burst of 16 bytes + * (by default it is the starting address of the DMC address range). + */ +#ifndef CONFIG_SC59X + writel(dmc.dmc_data_calib_add_value, dmc.reg + REG_DMC_DT_CALIB_ADDR); +#endif + /* 3. Program the DMCx_CTL register with INIT bit set to start + * the DMC initialization sequence + */ + writel(dmc.dmc_ctl_value, dmc.reg + REG_DMC_CTL); + /* 4. Wait for the DMC initialization to complete by polling + * DMCx_STAT.INITDONE bit. + */ + +#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) + dmcdelay(722000u); + + /* Add necessary delay depending on the configuration */ + t_EMR1 = (dmc.dmc_mr1_value & BITM_DMC_MR1_WL) >> BITP_DMC_MR1_WL; + + dmcdelay(600u); + if (t_EMR1 != 0u) + while ((readl(dmc.reg + REG_DMC_EMR1) & BITM_DMC_MR1_WL) != 0) + ; + + t_EMR3 = (dmc.dmc_mr3_value & BITM_DMC_EMR3_MPR) >> + BITP_DMC_EMR3_MPR; + dmcdelay(2000u); + if (t_EMR3 != 0u) + while ((readl(dmc.reg + REG_DMC_EMR3) & BITM_DMC_EMR3_MPR) != 0) + ; + + t_CTL = (dmc.dmc_ctl_value & BITM_DMC_CTL_RL_DQS) >> BITP_DMC_CTL_RL_DQS; + dmcdelay(600u); + if (t_CTL != 0u) + while ((readl(dmc.reg + REG_DMC_CTL) & BITM_DMC_CTL_RL_DQS) != 0) + ; +#endif + + /* check if DMC initialization finished*/ + while ((readl(dmc.reg + REG_DMC_STAT) & BITM_DMC_STAT_INITDONE) == 0) + ; + +#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) + /* toggle DCYCLE */ + temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL1); + temp |= BITM_DMC_DDR_LANE0_CTL1_COMP_DCYCLE; + writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL1); + + temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL1); + temp |= BITM_DMC_DDR_LANE1_CTL1_COMP_DCYCLE; + writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL1); + + dmcdelay(10u); + + temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL1); + temp &= (~BITM_DMC_DDR_LANE0_CTL1_COMP_DCYCLE); + writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL1); + + temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL1); + temp &= (~BITM_DMC_DDR_LANE1_CTL1_COMP_DCYCLE); + writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL1); + + /* toggle RSTDAT */ + temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL0); + temp |= BITM_DMC_DDR_LANE0_CTL0_CB_RSTDAT; + writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL0); + + temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL0); + temp &= (~BITM_DMC_DDR_LANE0_CTL0_CB_RSTDAT); + writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL0); + + temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL0); + temp |= BITM_DMC_DDR_LANE1_CTL0_CB_RSTDAT; + writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL0); + + temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL0); + temp &= (~BITM_DMC_DDR_LANE1_CTL0_CB_RSTDAT); + writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL0); + + dmcdelay(2500u); + + /* Program phyphase*/ + phyphase = (readl(dmc.reg + REG_DMC_STAT) & + BITM_DMC_STAT_PHYRDPHASE) >> BITP_DMC_STAT_PHYRDPHASE; + data_cyc = (phyphase << BITP_DMC_DLLCTL_DATACYC) & + BITM_DMC_DLLCTL_DATACYC; + rd_cnt = dmc.dmc_dllctl_value; + rd_cnt <<= BITP_DMC_DLLCTL_DLLCALRDCNT; + rd_cnt &= BITM_DMC_DLLCTL_DLLCALRDCNT; + writel(rd_cnt | data_cyc, dmc.reg + REG_DMC_DLLCTL); + writel((dmc.dmc_ctl_value & (~BITM_DMC_CTL_INIT) & + (~BITM_DMC_CTL_RL_DQS)), dmc.reg + REG_DMC_CTL); + +#if DELAYTRIM + /* DQS delay trim*/ + u32 stat_value, WL_code_LDQS, WL_code_UDQS; + + /* For LDQS */ + temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL1) | (0x000000D0); + writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL1); + dmcdelay(2500u); + writel(0x00400000, dmc.reg + REG_DMC_DDR_ROOT_CTL); + dmcdelay(2500u); + writel(0x0, dmc.reg + REG_DMC_DDR_ROOT_CTL); + stat_value = (readl(dmc.reg + REG_DMC_DDR_SCRATCH_STAT0) & + (0xFFFF0000)) >> 16; + WL_code_LDQS = (stat_value) & (0x0000001F); + + temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL1); + temp &= ~(BITM_DMC_DDR_LANE0_CTL1_BYPCODE | + BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN); + writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL1); + + /* If write leveling is enabled */ + if ((dmc.dmc_mr1_value & BITM_DMC_MR1_WL) >> BITP_DMC_MR1_WL) { + temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL1); + temp |= (((WL_code_LDQS + LANE0_DQS_DELAY) << + BITP_DMC_DDR_LANE0_CTL1_BYPCODE) & + BITM_DMC_DDR_LANE0_CTL1_BYPCODE) | + BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN; + writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL1); + } else { + temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL1); + temp |= (((DQS_DEFAULT_DELAY + LANE0_DQS_DELAY) << + BITP_DMC_DDR_LANE0_CTL1_BYPCODE) & + BITM_DMC_DDR_LANE0_CTL1_BYPCODE) | + BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN; + writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL1); + } + dmcdelay(2500u); + + /* For UDQS */ + temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL1) | (0x000000D0); + writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL1); + dmcdelay(2500u); + writel(0x00800000, dmc.reg + REG_DMC_DDR_ROOT_CTL); + dmcdelay(2500u); + writel(0x0, dmc.reg + REG_DMC_DDR_ROOT_CTL); + stat_value = (readl(dmc.reg + REG_DMC_DDR_SCRATCH_STAT1) & + (0xFFFF0000)) >> 16; + WL_code_UDQS = (stat_value) & (0x0000001F); + + temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL1); + temp &= ~(BITM_DMC_DDR_LANE0_CTL1_BYPCODE | + BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN); + writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL1); + + /* If write leveling is enabled */ + if ((dmc.dmc_mr1_value & BITM_DMC_MR1_WL) >> BITP_DMC_MR1_WL) { + temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL1); + temp |= (((WL_code_UDQS + LANE1_DQS_DELAY) << + BITP_DMC_DDR_LANE0_CTL1_BYPCODE) & + BITM_DMC_DDR_LANE0_CTL1_BYPCODE) | + BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN; + writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL1); + } else { + temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL1); + temp |= (((DQS_DEFAULT_DELAY + LANE1_DQS_DELAY) << + BITP_DMC_DDR_LANE0_CTL1_BYPCODE) & + BITM_DMC_DDR_LANE0_CTL1_BYPCODE) | + BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN; + writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL1); + } + dmcdelay(2500u); +#endif + +#else + /* 5. Program the DMCx_CTL.DLLCTL register with 0x948 value + * (DATACYC=9, DLLCALRDCNT=72). + */ + writel(0x00000948, dmc.reg + REG_DMC_DLLCTL); +#endif + + /* 6. Workaround for anomaly#20000037 */ + if (dmc.anomaly_20000037_applicable) { + /* Perform dummy read to any DMC location */ + readl(0x80000000); + + writel(readl(dmc.reg + REG_DMC_PHY_CTL0) | 0x1000, + dmc.reg + REG_DMC_PHY_CTL0); + /* Clear DMCx_PHY_CTL0.RESETDAT bit */ + writel(readl(dmc.reg + REG_DMC_PHY_CTL0) & (~0x1000), + dmc.reg + REG_DMC_PHY_CTL0); + } +} + +static inline void dmc_init(void) +{ + /* PHY Calibration+Initialization */ + if (!dmc.phy_init_required) + goto out; + + switch (dmc.calib_mode) { + case CALIBRATION_LEGACY: + calibration_legacy(); + break; + case CALIBRATION_METHOD1: + calibration_method1(); + break; + case CALIBRATION_METHOD2: + calibration_method2(); + break; + } + +#if DQSTRIM + /* DQS duty trim */ + temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL0); + temp |= ((DQSCODE) << BITP_DMC_DDR_LANE0_CTL0_BYPENB) & + (BITM_DMC_DDR_LANE1_CTL0_BYPENB | + BITM_DMC_DDR_LANE0_CTL0_BYPSELP | + BITM_DMC_DDR_LANE0_CTL0_BYPCODE); + writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL0); + + temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL0); + temp |= ((DQSCODE) << BITP_DMC_DDR_LANE1_CTL0_BYPENB) & + (BITM_DMC_DDR_LANE1_CTL1_BYPCODE | + BITM_DMC_DDR_LANE1_CTL0_BYPSELP | + BITM_DMC_DDR_LANE1_CTL0_BYPCODE); + writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL0); +#endif + +#if CLKTRIM + /* Clock duty trim */ + temp = readl(dmc.reg + REG_DMC_DDR_CA_CTL); + temp |= (((CLKCODE << BITP_DMC_DDR_CA_CTL_BYPCODE1) & + BITM_DMC_DDR_CA_CTL_BYPCODE1) | + BITM_DMC_DDR_CA_CTL_BYPENB | + ((CLKDIR << BITP_DMC_DDR_CA_CTL_BYPSELP) & + BITM_DMC_DDR_CA_CTL_BYPSELP)); + writel(temp, dmc.reg + REG_DMC_DDR_CA_CTL); +#endif + +out: + /* Controller Initialization */ + dmc_controller_init(); +} + +static inline void __dmc_config(uint32_t dmc_no) +{ + if (dmc_no == 0) { + dmc.reg = REG_DMC0_BASE; + dmc.dmc_data_calib_add_value = DMC0_DATA_CALIB_ADD; + } else if (dmc_no == 1) { + dmc.reg = REG_DMC1_BASE; + dmc.dmc_data_calib_add_value = DMC1_DATA_CALIB_ADD; + } else { + return; + } + + if (IS_ENABLED(CONFIG_ADI_USE_DDR2)) + dmc.ddr_mode = DDR2_MODE; + else + dmc.ddr_mode = DDR3_MODE; + + dmc.phy_init_required = true; + +#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) + dmc.anomaly_20000037_applicable = false; + dmc.dmc_dllctl_value = DMC_DLLCTL_VALUE; + dmc.calib_mode = CALIBRATION_METHOD2; +#else + dmc.anomaly_20000037_applicable = true; + dmc.calib_mode = CALIBRATION_LEGACY; +#endif + + dmc.dmc_ctl_value = DMC_CTL_VALUE; + dmc.dmc_cfg_value = DMC_CFG_VALUE; + dmc.dmc_tr0_value = DMC_TR0_VALUE; + dmc.dmc_tr1_value = DMC_TR1_VALUE; + dmc.dmc_tr2_value = DMC_TR2_VALUE; + dmc.dmc_mr0_value = DMC_MR0_VALUE; + dmc.dmc_mr1_value = DMC_MR1_VALUE; + dmc.dmc_mr2_value = DMC_MR2_VALUE; + +#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) + dmc.dmc_mr3_value = DMC_MR3_VALUE; + dmc.dmc_zqctl0_value = DMC_ZQCTL0_VALUE; + dmc.dmc_zqctl1_value = DMC_ZQCTL1_VALUE; + dmc.dmc_zqctl2_value = DMC_ZQCTL2_VALUE; +#endif + + dmc.padctl2_value = DMC_PADCTL2_VALUE; + dmc.dmc_cphyctl_value = DMC_CPHYCTL_VALUE; + + /* Initialize DMC now */ + dmc_init(); +} + +void DMC_Config(void) +{ + if (IS_ENABLED(CONFIG_ADI_USE_DMC0)) + __dmc_config(0); + + if (IS_ENABLED(CONFIG_ADI_USE_DMC1)) + __dmc_config(1); +} diff --git a/arch/arm/mach-sc5xx/init/dmcinit.h b/arch/arm/mach-sc5xx/init/dmcinit.h new file mode 100644 index 00000000000..46ff729282d --- /dev/null +++ b/arch/arm/mach-sc5xx/init/dmcinit.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison + * Contact: Greg Malysa + */ + +#ifndef DMCINIT_H_ +#define DMCINIT_H_ + +#include + +#ifdef MEM_MT41K512M16HA + #include "mem/mt41k512m16ha.h" +#elif defined(MEM_MT41K128M16JT) + #include "mem/mt41k128m16jt.h" +#elif defined(MEM_MT47H128M16RT) + #include "mem/mt47h128m16rt.h" +#elif defined(MEM_IS43TR16512BL) + #include "mem/is43tr16512bl.h" +#else + #error "No DDR part name is defined for this board." +#endif + +void DMC_Config(void); +void adi_dmc_reset_lanes(bool reset); + +#endif diff --git a/arch/arm/mach-sc5xx/init/mem/is43tr16512bl.h b/arch/arm/mach-sc5xx/init/mem/is43tr16512bl.h new file mode 100644 index 00000000000..a5838370555 --- /dev/null +++ b/arch/arm/mach-sc5xx/init/mem/is43tr16512bl.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison + * Contact: Greg Malysa + */ + +#ifndef IS43TR16512BL_H +#define IS43TR16512BL_H + +/* DMC0 setup for the EV-21593-SOM and EV-SC594-SOM : + * - uses a single 8GB IS43TR16512BL-125KBL DDR3 chip configured for + * 800 MHz DCLK. + * DMC0 setup for the EV-SC594-SOMS : + * - uses a single 4GB IS43TR16256BL-093NBL DDR3 chip configured for + * 800 MHz DCLK. + */ +#define DMC_DLLCALRDCNT 240 +#define DMC_DATACYC 12 +#define DMC_TRCD 11 +#define DMC_TWTR 6 +#define DMC_TRP 11 +#define DMC_TRAS 28 +#define DMC_TRC 39 +#define DMC_TMRD 4 +#define DMC_TREF 6240 +#define DMC_TRRD 6 +#define DMC_TFAW 32 +#define DMC_TRTP 6 +#define DMC_TWR 12 +#define DMC_TXP 5 +#define DMC_TCKE 4 +#define DMC_CL0 0 +#define DMC_CL123 7 +#define DMC_WRRECOV 6 +#define DMC_MR1_DLLEN 0 +#define DMC_MR1_DIC0 0 +#define DMC_MR1_RTT0 0 +#define DMC_MR1_AL 0 +#define DMC_MR1_DIC1 0 +#define DMC_MR1_RTT1 1 +#define DMC_MR1_WL 0 +#define DMC_MR1_RTT2 0 +#define DMC_MR1_TDQS 0 +#define DMC_MR1_QOFF 0 +#define DMC_WL 3 +#define DMC_RDTOWR 5 +#define DMC_CTL_AL_EN 1 +#if defined(MEM_ISSI_4Gb_DDR3_800MHZ) + #define SDR_CHIP_SIZE (ENUM_DMC_CFG_SDRSIZE4G) + #define DMC_TRFC 208ul +#elif defined(MEM_ISSI_8Gb_DDR3_800MHZ) + #define SDR_CHIP_SIZE (ENUM_DMC_CFG_SDRSIZE8G) + #define DMC_TRFC 280ul +#else + #error "Need to select MEM_ISSI_4Gb_DDR3_800MHZ or MEM_ISSI_8Gb_DDR3_800MHZ" +#endif + +#endif diff --git a/arch/arm/mach-sc5xx/init/mem/mt41k128m16jt.h b/arch/arm/mach-sc5xx/init/mem/mt41k128m16jt.h new file mode 100644 index 00000000000..882777521b8 --- /dev/null +++ b/arch/arm/mach-sc5xx/init/mem/mt41k128m16jt.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison + * Contact: Greg Malysa + */ + +#ifndef MT41K128M16JT_H +#define MT41K128M16JT_H + +/* Default DDR3 part assumed: MT41K128M16JT-125, 2Gb part */ +/* For DCLK= 450 MHz */ +#define DMC_DLLCALRDCNT 72 +#define DMC_DATACYC 9 +#define DMC_TRCD 6 +#define DMC_TWTR 4 +#define DMC_TRP 6 +#define DMC_TRAS 17 +#define DMC_TRC 23 +#define DMC_TMRD 4 +#define DMC_TREF 3510 +#define DMC_TRFC 72 +#define DMC_TRRD 4 +#define DMC_TFAW 17 +#define DMC_TRTP 4 +#define DMC_TWR 7 +#define DMC_TXP 4 +#define DMC_TCKE 3 +#define DMC_CL0 0 +#define DMC_CL123 3 +#define DMC_WRRECOV (DMC_TWR - 1) +#define DMC_MR1_DLLEN 0 +#define DMC_MR1_DIC0 1 +#define DMC_MR1_RTT0 1 +#define DMC_MR1_AL 0 +#define DMC_MR1_DIC1 0 +#define DMC_MR1_RTT1 0 +#define DMC_MR1_WL 0 +#define DMC_MR1_RTT2 0 +#define DMC_MR1_TDQS 0 +#define DMC_MR1_QOFF 0 +#define DMC_WL 1 +#define DMC_RDTOWR 2 +#define DMC_CTL_AL_EN 0 +#define SDR_CHIP_SIZE ENUM_DMC_CFG_SDRSIZE2G + +#endif diff --git a/arch/arm/mach-sc5xx/init/mem/mt41k512m16ha.h b/arch/arm/mach-sc5xx/init/mem/mt41k512m16ha.h new file mode 100644 index 00000000000..5735b87871c --- /dev/null +++ b/arch/arm/mach-sc5xx/init/mem/mt41k512m16ha.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison + * Contact: Greg Malysa + */ + +#ifndef MT41K512M16HA_H +#define MT41K512M16HA_H + +/* Default DDR3 part assumed: MT41K512M16HA-107, 8Gb part */ +/* For DCLK= 450 MHz */ +#define DMC_DLLCALRDCNT 72 +#define DMC_DATACYC 9 +#define DMC_TRCD 7 +#define DMC_TWTR 4 +#define DMC_TRP 7 +#define DMC_TRAS 10 +#define DMC_TRC 16 +#define DMC_TMRD 4 +#define DMC_TREF 3510 +#define DMC_TRFC 158 +#define DMC_TRRD 6 +#define DMC_TFAW 16 +#define DMC_TRTP 4 +#define DMC_TWR 7 +#define DMC_TXP 3 +#define DMC_TCKE 3 +#define DMC_CL0 0 +#define DMC_CL123 3 +#define DMC_WRRECOV (DMC_TWR - 1) +#define DMC_MR1_DLLEN 0 +#define DMC_MR1_DIC0 1 +#define DMC_MR1_RTT0 1 +#define DMC_MR1_AL 0 +#define DMC_MR1_DIC1 0 +#define DMC_MR1_RTT1 0 +#define DMC_MR1_WL 0 +#define DMC_MR1_RTT2 0 +#define DMC_MR1_TDQS 0 +#define DMC_MR1_QOFF 0 +#define DMC_WL 1 +#define DMC_RDTOWR 2 +#define DMC_CTL_AL_EN 0 +#define SDR_CHIP_SIZE ENUM_DMC_CFG_SDRSIZE8G + +#endif diff --git a/arch/arm/mach-sc5xx/init/mem/mt47h128m16rt.h b/arch/arm/mach-sc5xx/init/mem/mt47h128m16rt.h new file mode 100644 index 00000000000..5ada7f2985b --- /dev/null +++ b/arch/arm/mach-sc5xx/init/mem/mt47h128m16rt.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison + * Contact: Greg Malysa + */ + +#ifndef MT47H128M16RT_H +#define MT47H128M16RT_H + +/* Default DDR2 part: MT47H128M16RT-25E XIT:C, 2 Gb part */ +/* For DCLK= 400 MHz */ +#define DMC_DLLCALRDCNT 72 +#define DMC_DATACYC 9 +#define DMC_TRCD 5 +#define DMC_TWTR 3 +#define DMC_TRP 5 +#define DMC_TRAS 16 +#define DMC_TRC 22 +#define DMC_TMRD 2 +#define DMC_TREF 3120 +#define DMC_TRFC 78 +#define DMC_TRRD 4 +#define DMC_TFAW 18 +#define DMC_TRTP 3 +#define DMC_TWR 6 +#define DMC_TXP 2 +#define DMC_TCKE 3 +#define DMC_CL 5 +#define DMC_WRRECOV (DMC_TWR - 1) +#define DMC_MR1_DLLEN 0 +#define DMC_MR1_DIC0 1 +#define DMC_MR1_RTT0 1 +#define DMC_MR1_AL 4 +#define DMC_MR1_DIC1 0 +#define DMC_MR1_RTT1 0 +#define DMC_MR1_WL 0 +#define DMC_MR1_RTT2 0 +#define DMC_MR1_TDQS 0 +#define DMC_MR1_QOFF 0 +#define DMC_BL 4 +#define DMC_RDTOWR 2 +#define DMC_CTL_AL_EN 0 +#define SDR_CHIP_SIZE ENUM_DMC_CFG_SDRSIZE2G + +#endif diff --git a/arch/arm/mach-sc5xx/rcu.c b/arch/arm/mach-sc5xx/rcu.c new file mode 100644 index 00000000000..49357501a93 --- /dev/null +++ b/arch/arm/mach-sc5xx/rcu.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2024 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Ian Roberts + */ + +#include +#include + +static const struct udevice_id adi_syscon_ids[] = { + { .compatible = "adi,reset-controller" }, + { } +}; + +U_BOOT_DRIVER(syscon_sc5xx_rcu) = { + .name = "sc5xx_rcu", + .id = UCLASS_SYSCON, + .of_match = adi_syscon_ids, +}; diff --git a/arch/arm/mach-sc5xx/sc57x.c b/arch/arm/mach-sc5xx/sc57x.c new file mode 100644 index 00000000000..b0587686d73 --- /dev/null +++ b/arch/arm/mach-sc5xx/sc57x.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2024 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison + * Contact: Greg Malysa + */ + +#include +#include +#include + +#define REG_SPU0_SECUREC0 0x3108B980 +#define REG_PADS0_PCFG0 0x31004404 +#define REG_SPU0_SECUREP_START 0x3108BA00 +#define REG_SPU0_SECUREP_END 0x3108BD24 + +adi_rom_boot_fn adi_rom_boot = (adi_rom_boot_fn)0x000000e1; + +void sc5xx_enable_rgmii(void) +{ + writel((readl(REG_PADS0_PCFG0) | 0xc), REG_PADS0_PCFG0); +} + +void sc5xx_soc_init(void) +{ + sc5xx_enable_ns_sharc_access(REG_SPU0_SECUREC0); + sc5xx_disable_spu0(REG_SPU0_SECUREP_START, REG_SPU0_SECUREP_END); + sc5xx_enable_pmu(); +} diff --git a/arch/arm/mach-sc5xx/sc58x.c b/arch/arm/mach-sc5xx/sc58x.c new file mode 100644 index 00000000000..0f892774309 --- /dev/null +++ b/arch/arm/mach-sc5xx/sc58x.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2024 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison + * Contact: Greg Malysa + */ + +#include +#include +#include + +#define REG_SPU0_SECUREC0 0x3108C980 +#define REG_PADS0_PCFG0 0x31004404 +#define REG_SPU0_SECUREP_START 0x3108CA00 +#define REG_SPU0_SECUREP_END 0x3108CCF0 + +adi_rom_boot_fn adi_rom_boot = (adi_rom_boot_fn)0x000000e1; + +void sc5xx_enable_rgmii(void) +{ + writel((readl(REG_PADS0_PCFG0) | 0xc), REG_PADS0_PCFG0); +} + +void sc5xx_soc_init(void) +{ + sc5xx_enable_ns_sharc_access(REG_SPU0_SECUREC0); + sc5xx_disable_spu0(REG_SPU0_SECUREP_START, REG_SPU0_SECUREP_END); + sc5xx_enable_pmu(); +} diff --git a/arch/arm/mach-sc5xx/sc59x.c b/arch/arm/mach-sc5xx/sc59x.c new file mode 100644 index 00000000000..174c6f5c445 --- /dev/null +++ b/arch/arm/mach-sc5xx/sc59x.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2024 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison + * Contact: Greg Malysa + */ + +#include +#include +#include + +#define REG_SPU0_SECUREC0 0x3108B980 +#define REG_PADS0_PCFG0 0x31004604 +#define REG_SPU0_SECUREP_START 0x3108BA00 +#define REG_SPU0_SECUREP_END 0x3108BD24 + +#define REG_SCB5_SPI2_OSPI_REMAP 0x30400000 +#define BITM_SCB5_SPI2_OSPI_REMAP_REMAP 0x00000003 +#define ENUM_SCB5_SPI2_OSPI_REMAP_OSPI0 0x00000001 + +adi_rom_boot_fn adi_rom_boot = (adi_rom_boot_fn)0x000000e9; + +void sc5xx_enable_rgmii(void) +{ + writel((readl(REG_PADS0_PCFG0) | 0xc), REG_PADS0_PCFG0); +} + +void sc59x_remap_ospi(void) +{ + clrsetbits_le32(REG_SCB5_SPI2_OSPI_REMAP, + BITM_SCB5_SPI2_OSPI_REMAP_REMAP, + ENUM_SCB5_SPI2_OSPI_REMAP_OSPI0); +} + +void sc5xx_soc_init(void) +{ + sc5xx_enable_ns_sharc_access(REG_SPU0_SECUREC0); + sc5xx_disable_spu0(REG_SPU0_SECUREP_START, REG_SPU0_SECUREP_END); + sc5xx_enable_pmu(); +} diff --git a/arch/arm/mach-sc5xx/sc59x_64.c b/arch/arm/mach-sc5xx/sc59x_64.c new file mode 100644 index 00000000000..82537bf1965 --- /dev/null +++ b/arch/arm/mach-sc5xx/sc59x_64.c @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2024 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison + * Contact: Greg Malysa + */ + +#include +#include +#include + +#define REG_TSGENWR0_CNTCR 0x310AE000 +#define REG_PADS0_PCFG0 0x31004604 +#define REG_RCU0_BCODE 0x3108C028 + +#define REG_SPU0_SECUREP_START 0x3108BA00 +#define REG_SPU0_WP_START 0x3108B400 +#define REG_SPU0_SECUREC0 0x3108B980 + +#define REG_SCB5_SPI2_OSPI_REMAP 0x30400000 +#define BITM_SCB5_SPI2_OSPI_REMAP_REMAP 0x00000003 +#define ENUM_SCB5_SPI2_OSPI_REMAP_OSPI0 0x00000001 + +adi_rom_boot_fn adi_rom_boot = (adi_rom_boot_fn)0x000000e4; + +void sc5xx_enable_rgmii(void) +{ + writel((readl(REG_PADS0_PCFG0) | 0xc), REG_PADS0_PCFG0); + + // Set dw for little endian operation as well + writel(readl(REG_PADS0_PCFG0) & ~(1 << 19), REG_PADS0_PCFG0); + writel(readl(REG_PADS0_PCFG0) & ~(1 << 20), REG_PADS0_PCFG0); +} + +void sc59x_remap_ospi(void) +{ + clrsetbits_le32(REG_SCB5_SPI2_OSPI_REMAP, + BITM_SCB5_SPI2_OSPI_REMAP_REMAP, + ENUM_SCB5_SPI2_OSPI_REMAP_OSPI0); +} + +/** + * SPU/SMPU configuration is the default for permissive access from non-secure + * EL1. If TFA and OPTEE are configured, they run *after* this code, as the + * current boot flow is SPL -> TFA -> OPTEE -> Proper -> Linux, and will + * be expected to configure peripheral security correctly. If they are not + * configured, then this permissive setting will allow Linux (which always + * runs in NS EL1) to control all access to these peripherals. Without it, + * the peripherals would simply be unavailable in a non-security build, + * which is not OK. + */ +void sc5xx_soc_init(void) +{ + phys_addr_t smpus[] = { + 0x31007800, //SMPU0 + 0x31083800, //SMPU2 + 0x31084800, //SMPU3 + 0x31085800, //SMPU4 + 0x31086800, //SMPU5 + 0x31087800, //SMPU6 + 0x310A0800, //SMPU9 + 0x310A1800, //SMPU11 + 0x31012800, //SMPU12 + }; + size_t i; + + // Enable coresight timer + writel(1, REG_TSGENWR0_CNTCR); + + //Do not rerun preboot routine -- + // Without this, hardware resets triggered by RCU0_CTL:SYSRST + // lead to a deadlock somewhere in the boot ROM + writel(0x200, REG_RCU0_BCODE); + + /* Alter outstanding transactions property of A55*/ + writel(0x1, 0x30643108); /* SCB6 A55 M0 Ib.fn Mod */ + isb(); + + /* configure DDR prefetch behavior, per ADI */ + writel(0x1, 0x31076000); + + /* configure smart mode, per ADI */ + writel(0x1307, 0x31076004); + + // Disable SPU and SPU WP registers + sc5xx_disable_spu0(REG_SPU0_SECUREP_START, REG_SPU0_SECUREP_START + 4*213); + sc5xx_disable_spu0(REG_SPU0_WP_START, REG_SPU0_WP_START + 4*213); + + /* configure smpus permissively */ + for (i = 0; i < ARRAY_SIZE(smpus); ++i) + writel(0x500, smpus[i]); + + sc5xx_enable_ns_sharc_access(REG_SPU0_SECUREC0); +} diff --git a/arch/arm/mach-sc5xx/soc.c b/arch/arm/mach-sc5xx/soc.c new file mode 100644 index 00000000000..8f13127a660 --- /dev/null +++ b/arch/arm/mach-sc5xx/soc.c @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison + * Contact: Greg Malysa + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_SC58X + #define RCU0_CTL 0x3108B000 + #define RCU0_STAT 0x3108B004 + #define RCU0_CRCTL 0x3108B008 + #define RCU0_CRSTAT 0x3108B00C + #define RCU0_SIDIS 0x3108B010 + #define RCU0_MSG_SET 0x3108B064 +#elif defined(CONFIG_SC57X) || defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) + #define RCU0_CTL 0x3108C000 + #define RCU0_STAT 0x3108C004 + #define RCU0_CRCTL 0x3108C008 + #define RCU0_CRSTAT 0x3108C00C + #define RCU0_SIDIS 0x3108C01C + #define RCU0_MSG_SET 0x3108C070 +#else + #error "No SC5xx SoC CONFIG_ enabled" +#endif + +#define BITP_RCU_STAT_BMODE 8 +#define BITM_RCU_STAT_BMODE 0x00000F00 + +#define REG_ARMPMU0_PMCR 0x31121E04 +#define REG_ARMPMU0_PMUSERENR 0x31121E08 +#define REG_ARMPMU0_PMLAR 0x31121FB0 + +DECLARE_GLOBAL_DATA_PTR; + +void reset_cpu(void) +{ + u32 val = readl(RCU0_CTL); + writel(val | 1, RCU0_CTL); +} + +void enable_caches(void) +{ + if (!IS_ENABLED(CONFIG_SYS_DCACHE_OFF)) + dcache_enable(); +} + +void sc5xx_enable_ns_sharc_access(uintptr_t securec0_base) +{ + writel(0, securec0_base); + writel(0, securec0_base + 0x4); + writel(0, securec0_base + 0x8); +} + +void sc5xx_disable_spu0(uintptr_t spu0_start, uintptr_t spu0_end) +{ + for (uintptr_t i = spu0_start; i <= spu0_end; i += 4) + writel(0, i); +} + +/** + * PMU is only available on armv7 platforms and all share the same location + */ +void sc5xx_enable_pmu(void) +{ + if (!IS_ENABLED(CONFIG_SC59X_64)) { + writel(readl(REG_ARMPMU0_PMUSERENR) | 0x01, REG_ARMPMU0_PMUSERENR); + writel(0xc5acce55, REG_ARMPMU0_PMLAR); + writel(readl(REG_ARMPMU0_PMCR) | (1 << 1), REG_ARMPMU0_PMCR); + } +} + +const char *sc5xx_get_boot_mode(u32 *bmode) +{ + static const char * const bmodes[] = { + "JTAG/BOOTROM", + "QSPI Master", + "QSPI Slave", + "UART", + "LP0 Slave", + "OSPI", +#ifdef CONFIG_SC59X_64 + "eMMC" +#endif + }; + u32 local_mode; + + local_mode = (readl(RCU0_STAT) & BITM_RCU_STAT_BMODE) >> BITP_RCU_STAT_BMODE; + +#if CONFIG_ADI_SPL_FORCE_BMODE != 0 + /* + * In case we want to force boot sequences such as: + * QSPI -> OSPI + * QSPI -> eMMC + * If this is not set, then we will always try to use the BMODE setting + * for both stages... i.e. + * QSPI -> QSPI + */ + + // (Don't allow skipping JTAG/UART BMODE settings) + if (local_mode != 0 && local_mode != 3) + local_mode = CONFIG_ADI_SPL_FORCE_BMODE; +#endif + + *bmode = local_mode; + + if (local_mode >= 0 && local_mode <= ARRAY_SIZE(bmodes)) + return bmodes[local_mode]; + return "unknown"; +} + +void print_cpu_id(void) +{ + if (!IS_ENABLED(CONFIG_ARM64)) { + u32 cpuid = 0; + + __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0" : "=r"(cpuid)); + + printf("Detected Revision: %d.%d\n", cpuid & 0xf00000 >> 20, cpuid & 0xf); + } +} + +int print_cpuinfo(void) +{ + u32 bmode; + + printf("CPU: ADSP %s (%s boot)\n", CONFIG_LDR_CPU, sc5xx_get_boot_mode(&bmode)); + print_cpu_id(); + + return 0; +} + +void fixup_dp83867_phy(struct phy_device *phydev) +{ + int phy_data = 0; + + phy_data = phy_read(phydev, MDIO_DEVAD_NONE, 0x32); + phy_write(phydev, MDIO_DEVAD_NONE, 0x32, (1 << 7) | phy_data); + int cfg3 = 0; + #define MII_DP83867_CFG3 (0x1e) + /* + * Pin INT/PWDN on DP83867 should be configured as an Interrupt Output + * instead of a Power-Down Input on ADI SC5XX boards in order to + * prevent the signal interference from other peripherals during they + * are running at the same time. + */ + cfg3 = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG3); + cfg3 |= (1 << 7); + phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG3, cfg3); + + // Mystery second port fixup on ezkits with two PHYs + if (CONFIG_DW_PORTS & 2) + phy_write(phydev, MDIO_DEVAD_NONE, 0x11, 3); + + if (IS_ENABLED(CONFIG_ADI_BUG_EZKHW21)) { + phydev->advertising &= PHY_BASIC_FEATURES; + phydev->speed = SPEED_100; + } + + if (phydev->drv->config) + phydev->drv->config(phydev); + + if (IS_ENABLED(CONFIG_ADI_BUG_EZKHW21)) + phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x3100); +} + +int dram_init(void) +{ + gd->ram_size = CFG_SYS_SDRAM_SIZE; + return 0; +} diff --git a/arch/arm/mach-sc5xx/spl.c b/arch/arm/mach-sc5xx/spl.c new file mode 100644 index 00000000000..68e0310f5af --- /dev/null +++ b/arch/arm/mach-sc5xx/spl.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison + * Contact: Greg Malysa + */ + +#include +#include +#include +#include "init/clkinit.h" +#include "init/dmcinit.h" + +static bool adi_start_uboot_proper; + +static int adi_sf_default_bus = CONFIG_SF_DEFAULT_BUS; +static int adi_sf_default_cs = CONFIG_SF_DEFAULT_CS; +static int adi_sf_default_speed = CONFIG_SF_DEFAULT_SPEED; + +u32 bmode; + +int spl_start_uboot(void) +{ + return adi_start_uboot_proper; +} + +unsigned int spl_spi_get_default_speed(void) +{ + return adi_sf_default_speed; +} + +unsigned int spl_spi_get_default_bus(void) +{ + return adi_sf_default_bus; +} + +unsigned int spl_spi_get_default_cs(void) +{ + return adi_sf_default_cs; +} + +void board_boot_order(u32 *spl_boot_list) +{ + const char *bmodestring = sc5xx_get_boot_mode(&bmode); + + printf("ADI Boot Mode: 0x%x (%s)\n", bmode, bmodestring); + + /* + * By default everything goes back to the bootrom, where we'll read table + * parameters and ask for another image to be loaded + */ + spl_boot_list[0] = BOOT_DEVICE_BOOTROM; + + if (bmode == 0) { + printf("SPL execution has completed. Please load U-Boot Proper via JTAG"); + while (1) + ; + } +} + +int32_t __weak adi_rom_boot_hook(struct ADI_ROM_BOOT_CONFIG *config, int32_t cause) +{ + return 0; +} + +int board_return_to_bootrom(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) +{ +#if CONFIG_ADI_SPL_FORCE_BMODE != 0 + // see above + if (bmode != 0 && bmode != 3) + bmode = CONFIG_ADI_SPL_FORCE_BMODE; +#endif + + if (bmode >= (ARRAY_SIZE(adi_rom_boot_args))) + bmode = 0; + + adi_rom_boot((void *)adi_rom_boot_args[bmode].addr, + adi_rom_boot_args[bmode].flags, + 0, &adi_rom_boot_hook, + adi_rom_boot_args[bmode].cmd); + return 0; +}; + +void board_init_f(ulong dummy) +{ + int ret; + + clks_init(); + DMC_Config(); + sc5xx_soc_init(); + + ret = spl_early_init(); + if (ret) + panic("spl_early_init() failed\n"); + + preloader_console_init(); +} + diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 616e1afe5de..feaf5ce4596 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -5,7 +5,7 @@ * Copyright (C) 2015 Marek Vasut */ -#include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index 9e645a42531..160f6e73ca9 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -3,7 +3,6 @@ * Copyright (C) 2013-2017 Altera Corporation */ -#include #include #include #include diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c b/arch/arm/mach-socfpga/clock_manager_agilex.c index 28f593b60e6..9987d5bcee6 100644 --- a/arch/arm/mach-socfpga/clock_manager_agilex.c +++ b/arch/arm/mach-socfpga/clock_manager_agilex.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/arch/arm/mach-socfpga/clock_manager_agilex5.c b/arch/arm/mach-socfpga/clock_manager_agilex5.c index b92f0b3af80..7ec28d91ef3 100644 --- a/arch/arm/mach-socfpga/clock_manager_agilex5.c +++ b/arch/arm/mach-socfpga/clock_manager_agilex5.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c index 8ab18f6b725..58b9321131a 100644 --- a/arch/arm/mach-socfpga/clock_manager_arria10.c +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c @@ -3,7 +3,6 @@ * Copyright (C) 2016-2017 Intel Corporation */ -#include #include #include #include diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c b/arch/arm/mach-socfpga/clock_manager_gen5.c index 8fa2760798b..154ad2154ae 100644 --- a/arch/arm/mach-socfpga/clock_manager_gen5.c +++ b/arch/arm/mach-socfpga/clock_manager_gen5.c @@ -3,7 +3,6 @@ * Copyright (C) 2013-2017 Altera Corporation */ -#include #include #include #include diff --git a/arch/arm/mach-socfpga/clock_manager_n5x.c b/arch/arm/mach-socfpga/clock_manager_n5x.c index 0ed480de670..c4c071330fc 100644 --- a/arch/arm/mach-socfpga/clock_manager_n5x.c +++ b/arch/arm/mach-socfpga/clock_manager_n5x.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c index 45300336d52..1e148947a33 100644 --- a/arch/arm/mach-socfpga/clock_manager_s10.c +++ b/arch/arm/mach-socfpga/clock_manager_s10.c @@ -4,7 +4,7 @@ * */ -#include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/firewall.c b/arch/arm/mach-socfpga/firewall.c index 69229dc651e..4dec47b8e96 100644 --- a/arch/arm/mach-socfpga/firewall.c +++ b/arch/arm/mach-socfpga/firewall.c @@ -4,8 +4,8 @@ * */ +#include #include -#include #include #include diff --git a/arch/arm/mach-socfpga/fpga_manager.c b/arch/arm/mach-socfpga/fpga_manager.c index 18d692c6314..c946d4c38d9 100644 --- a/arch/arm/mach-socfpga/fpga_manager.c +++ b/arch/arm/mach-socfpga/fpga_manager.c @@ -7,7 +7,7 @@ * platform code, the real meat is located in drivers/fpga/socfpga.c . */ -#include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/freeze_controller.c b/arch/arm/mach-socfpga/freeze_controller.c index 561d3408cd8..7c86350d5ea 100644 --- a/arch/arm/mach-socfpga/freeze_controller.c +++ b/arch/arm/mach-socfpga/freeze_controller.c @@ -4,7 +4,7 @@ */ -#include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 6c9d32b9dd8..49f3fb2e705 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -6,6 +6,8 @@ #ifndef _CLOCK_MANAGER_H_ #define _CLOCK_MANAGER_H_ +#include + phys_addr_t socfpga_get_clkmgr_addr(void); #ifndef __ASSEMBLY__ diff --git a/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h index d5a11122c72..01335dc9310 100644 --- a/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h +++ b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h @@ -7,6 +7,8 @@ #ifndef _SECURE_REG_HELPER_H_ #define _SECURE_REG_HELPER_H_ +#include + #define SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC 1 #define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 2 #define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC1 3 diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index 101af238552..4c86f1e9917 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 80ad0870341..495ba2a0d41 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -3,7 +3,7 @@ * Copyright (C) 2012-2017 Altera Corporation */ -#include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index 93c9e8b0fb4..34c21317894 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -4,7 +4,7 @@ */ #include -#include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index e7500c16f72..b898b6f8f22 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -3,7 +3,7 @@ * Copyright (C) 2012-2017 Altera Corporation */ -#include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c index 2acdfad07b3..ad1ef0db186 100644 --- a/arch/arm/mach-socfpga/misc_soc64.c +++ b/arch/arm/mach-socfpga/misc_soc64.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c index 91c6d7c55f1..b8e40d9a788 100644 --- a/arch/arm/mach-socfpga/mmu-arm64_s10.c +++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c @@ -4,7 +4,6 @@ * */ -#include #include #include diff --git a/arch/arm/mach-socfpga/pinmux_arria10.c b/arch/arm/mach-socfpga/pinmux_arria10.c index f378fce7f02..c8074f47e76 100644 --- a/arch/arm/mach-socfpga/pinmux_arria10.c +++ b/arch/arm/mach-socfpga/pinmux_arria10.c @@ -4,9 +4,9 @@ */ #include +#include #include #include -#include #include static int do_pinctr_pin(const void *blob, int child, const char *node_name) diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c index 27c03080113..da335f4292c 100644 --- a/arch/arm/mach-socfpga/reset_manager_arria10.c +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c index a65860ef021..9395122dae1 100644 --- a/arch/arm/mach-socfpga/reset_manager_gen5.c +++ b/arch/arm/mach-socfpga/reset_manager_gen5.c @@ -4,7 +4,7 @@ */ -#include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index f47fec10a0c..dd0383c7c76 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/arch/arm/mach-socfpga/scan_manager.c b/arch/arm/mach-socfpga/scan_manager.c index 36d6880141e..f8811525da4 100644 --- a/arch/arm/mach-socfpga/scan_manager.c +++ b/arch/arm/mach-socfpga/scan_manager.c @@ -3,7 +3,7 @@ * Copyright (C) 2013 Altera Corporation */ -#include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/secure_reg_helper.c b/arch/arm/mach-socfpga/secure_reg_helper.c index 0d4f45f33da..802a966ce87 100644 --- a/arch/arm/mach-socfpga/secure_reg_helper.c +++ b/arch/arm/mach-socfpga/secure_reg_helper.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/arch/arm/mach-socfpga/secure_vab.c b/arch/arm/mach-socfpga/secure_vab.c index e2db5885064..4347bf6e792 100644 --- a/arch/arm/mach-socfpga/secure_vab.c +++ b/arch/arm/mach-socfpga/secure_vab.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c index 8ffc7a472b5..ebaa0b8fa17 100644 --- a/arch/arm/mach-socfpga/smc_api.c +++ b/arch/arm/mach-socfpga/smc_api.c @@ -4,10 +4,11 @@ * */ -#include #include #include +#include #include +#include int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len) { diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index 3981d2d4f14..c20376f7f8e 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -3,14 +3,13 @@ * Copyright (C) 2012-2021 Altera Corporation */ -#include +#include #include #include #include #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c index ee5a9dc1e2f..52617a39cca 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -8,9 +8,7 @@ #include #include #include -#include #include -#include #include #include #include diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 287fbd1713c..df79cfe0f7f 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -3,13 +3,11 @@ * Copyright (C) 2012 Altera Corporation */ -#include #include #include #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-socfpga/spl_n5x.c b/arch/arm/mach-socfpga/spl_n5x.c index d056871d292..5ff137e5c6f 100644 --- a/arch/arm/mach-socfpga/spl_n5x.c +++ b/arch/arm/mach-socfpga/spl_n5x.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include @@ -13,7 +12,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index c20e87cdbef..53852cb7443 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -9,9 +9,7 @@ #include #include #include -#include #include -#include #include #include #include diff --git a/arch/arm/mach-socfpga/spl_soc64.c b/arch/arm/mach-socfpga/spl_soc64.c index ba6efc1d864..4fe67ea0811 100644 --- a/arch/arm/mach-socfpga/spl_soc64.c +++ b/arch/arm/mach-socfpga/spl_soc64.c @@ -4,7 +4,6 @@ * */ -#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-socfpga/system_manager_gen5.c b/arch/arm/mach-socfpga/system_manager_gen5.c index 09caebb3c88..c377d1c32c7 100644 --- a/arch/arm/mach-socfpga/system_manager_gen5.c +++ b/arch/arm/mach-socfpga/system_manager_gen5.c @@ -3,7 +3,6 @@ * Copyright (C) 2013-2017 Altera Corporation */ -#include #include #include #include diff --git a/arch/arm/mach-socfpga/system_manager_soc64.c b/arch/arm/mach-socfpga/system_manager_soc64.c index 958bb5107b5..4b42158be9d 100644 --- a/arch/arm/mach-socfpga/system_manager_soc64.c +++ b/arch/arm/mach-socfpga/system_manager_soc64.c @@ -8,7 +8,6 @@ #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-socfpga/timer.c b/arch/arm/mach-socfpga/timer.c index d9e8c84bfcf..99de5744c48 100644 --- a/arch/arm/mach-socfpga/timer.c +++ b/arch/arm/mach-socfpga/timer.c @@ -3,7 +3,7 @@ * Copyright (C) 2012 Altera Corporation */ -#include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/timer_s10.c b/arch/arm/mach-socfpga/timer_s10.c index 84b13ce9d3a..80933586319 100644 --- a/arch/arm/mach-socfpga/timer_s10.c +++ b/arch/arm/mach-socfpga/timer_s10.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/arch/arm/mach-socfpga/vab.c b/arch/arm/mach-socfpga/vab.c index e146f2c5290..e74c71cfbb4 100644 --- a/arch/arm/mach-socfpga/vab.c +++ b/arch/arm/mach-socfpga/vab.c @@ -4,9 +4,9 @@ * */ +#include #include #include -#include #include static int do_vab(struct cmd_tbl *cmdtp, int flag, int argc, diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c index 6aa9bb26b4e..92051d19b73 100644 --- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c +++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c @@ -6,7 +6,6 @@ #include #include -#include #include #include "log.h" diff --git a/arch/arm/mach-socfpga/wrap_iocsr_config.c b/arch/arm/mach-socfpga/wrap_iocsr_config.c index ce86f04cad1..43ce329dd10 100644 --- a/arch/arm/mach-socfpga/wrap_iocsr_config.c +++ b/arch/arm/mach-socfpga/wrap_iocsr_config.c @@ -3,7 +3,7 @@ * Copyright (C) 2015 Marek Vasut */ -#include +#include #include #include diff --git a/arch/arm/mach-socfpga/wrap_pinmux_config.c b/arch/arm/mach-socfpga/wrap_pinmux_config.c index 33ca14c9dc7..e494d2eb3f9 100644 --- a/arch/arm/mach-socfpga/wrap_pinmux_config.c +++ b/arch/arm/mach-socfpga/wrap_pinmux_config.c @@ -3,8 +3,9 @@ * Copyright (C) 2015 Marek Vasut */ -#include #include +#include +#include /* Board-specific header. */ #include diff --git a/arch/arm/mach-socfpga/wrap_pll_config.c b/arch/arm/mach-socfpga/wrap_pll_config.c index 0c40ae98761..e0d0f8f81b7 100644 --- a/arch/arm/mach-socfpga/wrap_pll_config.c +++ b/arch/arm/mach-socfpga/wrap_pll_config.c @@ -3,7 +3,7 @@ * Copyright (C) 2015 Marek Vasut */ -#include +#include #include #include diff --git a/arch/arm/mach-socfpga/wrap_pll_config_soc64.c b/arch/arm/mach-socfpga/wrap_pll_config_soc64.c index 6a0d6b5ead7..f13581033e6 100644 --- a/arch/arm/mach-socfpga/wrap_pll_config_soc64.c +++ b/arch/arm/mach-socfpga/wrap_pll_config_soc64.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c b/arch/arm/mach-socfpga/wrap_sdram_config.c index cd3a0f66335..8f3fbaf80c8 100644 --- a/arch/arm/mach-socfpga/wrap_sdram_config.c +++ b/arch/arm/mach-socfpga/wrap_sdram_config.c @@ -3,8 +3,10 @@ * Copyright (C) 2015 Marek Vasut */ -#include +#include #include +#include +#include #include /* Board-specific header. */ diff --git a/arch/arm/mach-stm32/soc.c b/arch/arm/mach-stm32/soc.c index 0bd8d7b22c4..737e6809f8d 100644 --- a/arch/arm/mach-stm32/soc.c +++ b/arch/arm/mach-stm32/soc.c @@ -4,7 +4,6 @@ * Author(s): Patrice Chotard, for STMicroelectronics. */ -#include #include #include #include diff --git a/arch/arm/mach-stm32mp/boot_params.c b/arch/arm/mach-stm32mp/boot_params.c index 158bf40cb97..ebddf6a7dbc 100644 --- a/arch/arm/mach-stm32mp/boot_params.c +++ b/arch/arm/mach-stm32mp/boot_params.c @@ -5,7 +5,7 @@ #define LOG_CATEGORY LOGC_ARCH -#include +#include #include #include #include diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c index 5b869017ec1..9ba7a6c9a89 100644 --- a/arch/arm/mach-stm32mp/bsec.c +++ b/arch/arm/mach-stm32mp/bsec.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_MISC -#include #include #include #include diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c index c7fe232f86e..0cb3c7a9fa4 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32key.c +++ b/arch/arm/mach-stm32mp/cmd_stm32key.c @@ -3,7 +3,6 @@ * Copyright (C) 2019, STMicroelectronics - All Rights Reserved */ -#include #include #include #include diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c index adee6e05b63..967fa4e06c0 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c @@ -3,7 +3,6 @@ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved */ -#include #include #include #include diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c index 35bed319942..07c5e0456f8 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c @@ -3,12 +3,12 @@ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved */ -#include #include #include #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c index d18455bf36f..4b1ed50e9fe 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c @@ -3,7 +3,6 @@ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved */ -#include #include #include #include diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index fb1208fc5d5..78b12fcbb6a 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY LOGC_ARCH -#include #include #include #include diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index 524778f00c6..478c3efae73 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY LOGC_ARCH -#include #include #include #include diff --git a/arch/arm/mach-stm32mp/stm32mp1/fdt.c b/arch/arm/mach-stm32mp/stm32mp1/fdt.c index d0b6c3cc5a5..e1e4dc04e01 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/fdt.c +++ b/arch/arm/mach-stm32mp/stm32mp1/fdt.c @@ -5,11 +5,11 @@ #define LOG_CATEGORY LOGC_ARCH -#include #include #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c b/arch/arm/mach-stm32mp/stm32mp1/psci.c index 4f2379df45f..7772546b2fe 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/psci.c +++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c @@ -4,7 +4,6 @@ */ #include -#include #include #include #include @@ -13,6 +12,7 @@ #include #include #include +#include /* PWR */ #define PWR_CR3 0x0c diff --git a/arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c b/arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c index 846637ab162..79c44188cc5 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c +++ b/arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c @@ -5,10 +5,10 @@ #define LOG_CATEGORY UCLASS_REGULATOR -#include #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-stm32mp/stm32mp1/spl.c b/arch/arm/mach-stm32mp/stm32mp1/spl.c index 6c79259b2c8..7a8fd3178ad 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/spl.c +++ b/arch/arm/mach-stm32mp/stm32mp1/spl.c @@ -5,7 +5,7 @@ #define LOG_CATEGORY LOGC_ARCH -#include +#include #include #include #include diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c index 845d973ad1b..4a811065fc3 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c @@ -5,7 +5,7 @@ #define LOG_CATEGORY LOGC_ARCH -#include +#include #include #include #include diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c index d75ec99d6a1..f096fe538d8 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY LOGC_ARCH -#include #include #include #include diff --git a/arch/arm/mach-stm32mp/syscon.c b/arch/arm/mach-stm32mp/syscon.c index a2e351d74a7..8bcbd979340 100644 --- a/arch/arm/mach-stm32mp/syscon.c +++ b/arch/arm/mach-stm32mp/syscon.c @@ -3,7 +3,6 @@ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved */ -#include #include #include #include diff --git a/arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c b/arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c index 9077f86a8b4..3666dddca15 100644 --- a/arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c +++ b/arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c @@ -1,4 +1,3 @@ -#include #include #include diff --git a/arch/arm/mach-sunxi/dram_timings/ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/ddr3_1333.c index 0471e8a49e5..ceaafd6ec6f 100644 --- a/arch/arm/mach-sunxi/dram_timings/ddr3_1333.c +++ b/arch/arm/mach-sunxi/dram_timings/ddr3_1333.c @@ -1,4 +1,3 @@ -#include #include #include diff --git a/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c index 232b4fe2df7..3faf8d5bd97 100644 --- a/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c +++ b/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c @@ -11,7 +11,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include #include #include diff --git a/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c b/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c index b6d6a687468..ce2ffa7a020 100644 --- a/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c +++ b/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c @@ -11,7 +11,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include #include #include diff --git a/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c index c11cb8678f6..e6446b9180d 100644 --- a/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c +++ b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c @@ -9,7 +9,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include #include #include diff --git a/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c index 2136ca3a4cb..afe8e25c7f5 100644 --- a/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c +++ b/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c @@ -19,7 +19,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include #include #include diff --git a/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c b/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c index 10008601134..c243b574406 100644 --- a/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c +++ b/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c @@ -6,7 +6,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include #include #include diff --git a/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c b/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c index bd57e2f6aac..bc47a463853 100644 --- a/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c +++ b/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c @@ -1,4 +1,3 @@ -#include #include #include diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index 532730fe727..1ea620e4ab5 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -6,7 +6,7 @@ /* Tegra AP (Application Processor) code */ -#include +#include #include #include #include diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c index ea4eac392d9..4fbe47a91e1 100644 --- a/arch/arm/mach-tegra/arm64-mmu.c +++ b/arch/arm/mach-tegra/arm64-mmu.c @@ -7,7 +7,6 @@ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. */ -#include #include #include diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 327d70bd4cc..c382e042860 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -4,7 +4,7 @@ * NVIDIA Corporation */ -#include +#include #include #include #include diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index adea12c9b7f..479137e457c 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -4,7 +4,7 @@ * NVIDIA Corporation */ -#include +#include #include #include #include diff --git a/arch/arm/mach-tegra/cache.c b/arch/arm/mach-tegra/cache.c index d7063490e22..462364abf03 100644 --- a/arch/arm/mach-tegra/cache.c +++ b/arch/arm/mach-tegra/cache.c @@ -5,7 +5,6 @@ /* Tegra cache routines */ -#include #include #include #if IS_ENABLED(CONFIG_TEGRA_GP_PADCTRL) diff --git a/arch/arm/mach-tegra/cboot.c b/arch/arm/mach-tegra/cboot.c index 8f5bb2f261a..c12543d71ac 100644 --- a/arch/arm/mach-tegra/cboot.c +++ b/arch/arm/mach-tegra/cboot.c @@ -3,7 +3,6 @@ * Copyright (c) 2016-2018, NVIDIA CORPORATION. */ -#include #include #include #include diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 575da2bdb5a..157e6c4911a 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -5,7 +5,6 @@ /* Tegra SoC common clock control functions */ -#include #include #include #include diff --git a/arch/arm/mach-tegra/cmd_enterrcm.c b/arch/arm/mach-tegra/cmd_enterrcm.c index 92ff6cb1bf8..8fa1207e97a 100644 --- a/arch/arm/mach-tegra/cmd_enterrcm.c +++ b/arch/arm/mach-tegra/cmd_enterrcm.c @@ -24,7 +24,6 @@ * (C) Copyright 2004 Texas Insturments */ -#include #include #include #include diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c index 59ca8aeabac..5f2a5917102 100644 --- a/arch/arm/mach-tegra/cpu.c +++ b/arch/arm/mach-tegra/cpu.c @@ -3,7 +3,6 @@ * Copyright (c) 2010-2019, NVIDIA CORPORATION. All rights reserved. */ -#include #include #include #include diff --git a/arch/arm/mach-tegra/crypto.c b/arch/arm/mach-tegra/crypto.c index 893da35e0b9..49e6a45243a 100644 --- a/arch/arm/mach-tegra/crypto.c +++ b/arch/arm/mach-tegra/crypto.c @@ -4,7 +4,6 @@ * (C) Copyright 2010 - 2011 NVIDIA Corporation */ -#include #include #include #include diff --git a/arch/arm/mach-tegra/dt-setup.c b/arch/arm/mach-tegra/dt-setup.c index c11494722bc..f4ae602d523 100644 --- a/arch/arm/mach-tegra/dt-setup.c +++ b/arch/arm/mach-tegra/dt-setup.c @@ -3,7 +3,6 @@ * Copyright (c) 2010-2016, NVIDIA CORPORATION. */ -#include #include #include #include diff --git a/arch/arm/mach-tegra/emc.c b/arch/arm/mach-tegra/emc.c index 2eea14b5a74..83fad35d4dc 100644 --- a/arch/arm/mach-tegra/emc.c +++ b/arch/arm/mach-tegra/emc.c @@ -3,7 +3,6 @@ * Copyright (c) 2011 The Chromium OS Authors. */ -#include #include #include "emc.h" #include diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c index 83bd5055384..e9b5259ac70 100644 --- a/arch/arm/mach-tegra/fuse.c +++ b/arch/arm/mach-tegra/fuse.c @@ -7,7 +7,6 @@ * Svyatoslav Ryhel */ -#include #include #include diff --git a/arch/arm/mach-tegra/gpu.c b/arch/arm/mach-tegra/gpu.c index 36538e7f96a..23381759b79 100644 --- a/arch/arm/mach-tegra/gpu.c +++ b/arch/arm/mach-tegra/gpu.c @@ -5,7 +5,6 @@ /* Tegra vpr routines */ -#include #include #include #include diff --git a/arch/arm/mach-tegra/ivc.c b/arch/arm/mach-tegra/ivc.c index 66c1276f4b8..0445d5d48e5 100644 --- a/arch/arm/mach-tegra/ivc.c +++ b/arch/arm/mach-tegra/ivc.c @@ -3,11 +3,11 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ -#include #include #include #include #include +#include #include #define TEGRA_IVC_ALIGN 64 diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c index c4f5106750b..3f968d4aeae 100644 --- a/arch/arm/mach-tegra/pmc.c +++ b/arch/arm/mach-tegra/pmc.c @@ -3,7 +3,6 @@ * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */ -#include #include #include #include diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index 631bc04e950..2a2f8467216 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -3,8 +3,8 @@ * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved. */ -#include #include +#include #include #include diff --git a/arch/arm/mach-tegra/spl.c b/arch/arm/mach-tegra/spl.c index ed897efc5f0..5df0eb28c96 100644 --- a/arch/arm/mach-tegra/spl.c +++ b/arch/arm/mach-tegra/spl.c @@ -5,7 +5,6 @@ * * Allen Martin */ -#include #include #include #include diff --git a/arch/arm/mach-tegra/sys_info.c b/arch/arm/mach-tegra/sys_info.c index 5ad586ac17f..11b40480246 100644 --- a/arch/arm/mach-tegra/sys_info.c +++ b/arch/arm/mach-tegra/sys_info.c @@ -4,7 +4,6 @@ * NVIDIA Corporation */ -#include #include #include #if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA30) diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c index 2ee755bc649..d5cc8ac44dd 100644 --- a/arch/arm/mach-tegra/tegra114/clock.c +++ b/arch/arm/mach-tegra/tegra114/clock.c @@ -6,7 +6,6 @@ /* Tegra114 Clock control functions */ -#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra114/cpu.c b/arch/arm/mach-tegra/tegra114/cpu.c index 7d8f080c310..3fe2d2d7324 100644 --- a/arch/arm/mach-tegra/tegra114/cpu.c +++ b/arch/arm/mach-tegra/tegra114/cpu.c @@ -4,7 +4,6 @@ * NVIDIA Corporation */ -#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index ed8b6d96381..4ac0c10c597 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -6,7 +6,7 @@ /* Tegra124 Clock control functions */ -#include +#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra124/cpu.c b/arch/arm/mach-tegra/tegra124/cpu.c index b1bfe8fb5e1..07892aedd3c 100644 --- a/arch/arm/mach-tegra/tegra124/cpu.c +++ b/arch/arm/mach-tegra/tegra124/cpu.c @@ -4,7 +4,6 @@ * NVIDIA Corporation */ -#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra124/pmc.c b/arch/arm/mach-tegra/tegra124/pmc.c index 3921ffb52af..2294911501e 100644 --- a/arch/arm/mach-tegra/tegra124/pmc.c +++ b/arch/arm/mach-tegra/tegra124/pmc.c @@ -3,7 +3,6 @@ * Copyright (C) 2017 Google, Inc */ -#include #include #include diff --git a/arch/arm/mach-tegra/tegra124/psci.c b/arch/arm/mach-tegra/tegra124/psci.c index ab102a62261..a50b681935a 100644 --- a/arch/arm/mach-tegra/tegra124/psci.c +++ b/arch/arm/mach-tegra/tegra124/psci.c @@ -4,7 +4,6 @@ * Author: Jan Kiszka */ -#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra124/xusb-padctl.c b/arch/arm/mach-tegra/tegra124/xusb-padctl.c index 69736aa3925..1153444267d 100644 --- a/arch/arm/mach-tegra/tegra124/xusb-padctl.c +++ b/arch/arm/mach-tegra/tegra124/xusb-padctl.c @@ -5,9 +5,9 @@ #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt -#include #include #include +#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra20/bct.c b/arch/arm/mach-tegra/tegra20/bct.c index b2c44f3d237..e155b98cf65 100644 --- a/arch/arm/mach-tegra/tegra20/bct.c +++ b/arch/arm/mach-tegra/tegra20/bct.c @@ -4,7 +4,6 @@ * Copyright (c) 2022, Svyatoslav Ryhel */ -#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c index 109b73bfbe7..6af20e9c782 100644 --- a/arch/arm/mach-tegra/tegra20/clock.c +++ b/arch/arm/mach-tegra/tegra20/clock.c @@ -7,7 +7,6 @@ /* Tegra20 Clock control functions */ -#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra20/cpu.c b/arch/arm/mach-tegra/tegra20/cpu.c index e5b60598f7f..1ba3930b5e6 100644 --- a/arch/arm/mach-tegra/tegra20/cpu.c +++ b/arch/arm/mach-tegra/tegra20/cpu.c @@ -3,7 +3,6 @@ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. */ -#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra20/display.c b/arch/arm/mach-tegra/tegra20/display.c index 4ba3fb23fd6..207e50aac90 100644 --- a/arch/arm/mach-tegra/tegra20/display.c +++ b/arch/arm/mach-tegra/tegra20/display.c @@ -4,7 +4,6 @@ * NVIDIA Corporation */ -#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra20/emc.c b/arch/arm/mach-tegra/tegra20/emc.c index fb5e699c940..e2ee8f124ac 100644 --- a/arch/arm/mach-tegra/tegra20/emc.c +++ b/arch/arm/mach-tegra/tegra20/emc.c @@ -3,7 +3,7 @@ * Copyright (c) 2011 The Chromium OS Authors. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra20/pmu.c b/arch/arm/mach-tegra/tegra20/pmu.c index 05d0668cdba..f2fe5d0fa9d 100644 --- a/arch/arm/mach-tegra/tegra20/pmu.c +++ b/arch/arm/mach-tegra/tegra20/pmu.c @@ -4,7 +4,6 @@ * (C) Copyright 2010,2011 NVIDIA Corporation */ -#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c index 5e3a9ebaceb..18034c83a1c 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot.c +++ b/arch/arm/mach-tegra/tegra20/warmboot.c @@ -4,7 +4,6 @@ * NVIDIA Corporation */ -#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra20/warmboot_avp.c b/arch/arm/mach-tegra/tegra20/warmboot_avp.c index 94ce762e01f..65bbe182535 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot_avp.c +++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.c @@ -4,7 +4,7 @@ * NVIDIA Corporation */ -#include +#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index 74817e0440b..57ff0b2a19a 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -6,10 +6,10 @@ /* Tegra210 Clock control functions */ -#include #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c b/arch/arm/mach-tegra/tegra210/xusb-padctl.c index 30d0395bb0e..e409c2842e2 100644 --- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c +++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c @@ -5,9 +5,9 @@ #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt -#include #include #include +#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra30/bct.c b/arch/arm/mach-tegra/tegra30/bct.c index cff1a3e98d2..250009ea8d8 100644 --- a/arch/arm/mach-tegra/tegra30/bct.c +++ b/arch/arm/mach-tegra/tegra30/bct.c @@ -4,9 +4,9 @@ * Copyright (c) 2022, Svyatoslav Ryhel */ -#include #include #include +#include #include #include "bct.h" #include "uboot_aes.h" diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c index 0af8cde8c64..7d61127920b 100644 --- a/arch/arm/mach-tegra/tegra30/clock.c +++ b/arch/arm/mach-tegra/tegra30/clock.c @@ -6,7 +6,6 @@ /* Tegra30 Clock control functions */ -#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra30/cpu.c b/arch/arm/mach-tegra/tegra30/cpu.c index 60bbf13ea52..51a9deab1fd 100644 --- a/arch/arm/mach-tegra/tegra30/cpu.c +++ b/arch/arm/mach-tegra/tegra30/cpu.c @@ -3,7 +3,6 @@ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. */ -#include #include #include #include diff --git a/arch/arm/mach-tegra/xusb-padctl-common.c b/arch/arm/mach-tegra/xusb-padctl-common.c index 28fdebe50a3..a3515d903a6 100644 --- a/arch/arm/mach-tegra/xusb-padctl-common.c +++ b/arch/arm/mach-tegra/xusb-padctl-common.c @@ -5,7 +5,6 @@ #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt -#include #include #include #include diff --git a/arch/arm/mach-tegra/xusb-padctl-dummy.c b/arch/arm/mach-tegra/xusb-padctl-dummy.c index f2d90302f6d..1345b80747e 100644 --- a/arch/arm/mach-tegra/xusb-padctl-dummy.c +++ b/arch/arm/mach-tegra/xusb-padctl-dummy.c @@ -3,9 +3,9 @@ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. */ -#include #include +#include #include struct tegra_xusb_phy * __weak tegra_xusb_phy_get(unsigned int type) diff --git a/arch/arm/mach-u8500/cache.c b/arch/arm/mach-u8500/cache.c index 05a91346a89..7541b567d0f 100644 --- a/arch/arm/mach-u8500/cache.c +++ b/arch/arm/mach-u8500/cache.c @@ -3,7 +3,7 @@ * Copyright (C) 2019 Stephan Gerhold */ -#include +#include #include #include #include diff --git a/arch/arm/mach-u8500/cpuinfo.c b/arch/arm/mach-u8500/cpuinfo.c index ab05b8a51b2..6d4c6196c3d 100644 --- a/arch/arm/mach-u8500/cpuinfo.c +++ b/arch/arm/mach-u8500/cpuinfo.c @@ -3,7 +3,6 @@ * Copyright (C) 2019 Stephan Gerhold */ -#include #include #include diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index e6f1286e71f..0e1164a2680 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -12,7 +12,6 @@ #include #include #include -#include #include "init.h" #include "sg-regs.h" diff --git a/arch/arm/mach-versal-net/clk.c b/arch/arm/mach-versal-net/clk.c index d097de7afa6..61b8fe71b1a 100644 --- a/arch/arm/mach-versal-net/clk.c +++ b/arch/arm/mach-versal-net/clk.c @@ -6,7 +6,6 @@ * Michal Simek */ -#include #include #include #include diff --git a/arch/arm/mach-versal-net/cpu.c b/arch/arm/mach-versal-net/cpu.c index a82741e70fc..d088e440f63 100644 --- a/arch/arm/mach-versal-net/cpu.c +++ b/arch/arm/mach-versal-net/cpu.c @@ -6,7 +6,6 @@ * Michal Simek */ -#include #include #include #include diff --git a/arch/arm/mach-versal/clk.c b/arch/arm/mach-versal/clk.c index 5e3f44c7782..19943dfdd4c 100644 --- a/arch/arm/mach-versal/clk.c +++ b/arch/arm/mach-versal/clk.c @@ -4,7 +4,6 @@ * Michal Simek */ -#include #include #include #include diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index e4dc305d928..363ce3007fd 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -4,7 +4,6 @@ * Michal Simek */ -#include #include #include #include diff --git a/arch/arm/mach-versal/mp.c b/arch/arm/mach-versal/mp.c index 2487b482ddb..921ca49c359 100644 --- a/arch/arm/mach-versal/mp.c +++ b/arch/arm/mach-versal/mp.c @@ -4,7 +4,8 @@ * Siva Durga Prasad Paladugu */ -#include +#include +#include #include #include #include diff --git a/arch/arm/mach-versatile/Makefile b/arch/arm/mach-versatile/Makefile deleted file mode 100644 index 858ca9414c0..00000000000 --- a/arch/arm/mach-versatile/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y = timer.o -obj-y += reset.o diff --git a/arch/arm/mach-versatile/reset.S b/arch/arm/mach-versatile/reset.S deleted file mode 100644 index c7f1225fb29..00000000000 --- a/arch/arm/mach-versatile/reset.S +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * armboot - Startup Code for ARM926EJS CPU-core - * - * Copyright (c) 2003 Texas Instruments - * - * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ - * - * Copyright (c) 2001 Marius Gröger - * Copyright (c) 2002 Alex Züpke - * Copyright (c) 2002 Gary Jennejohn - * Copyright (c) 2003 Richard Woodruff - * Copyright (c) 2003 Kshitij - */ - - .align 5 -.globl reset_cpu -reset_cpu: - ldr r1, rstctl1 /* get clkm1 reset ctl */ - mov r3, #0x0 - strh r3, [r1] /* clear it */ - mov r3, #0x8 - strh r3, [r1] /* force dsp+arm reset */ -_loop_forever: - b _loop_forever - -rstctl1: - .word 0xfffece10 diff --git a/arch/arm/mach-versatile/timer.c b/arch/arm/mach-versatile/timer.c deleted file mode 100644 index b471412186d..00000000000 --- a/arch/arm/mach-versatile/timer.c +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2003 - * Texas Instruments - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * (C) Copyright 2002-2004 - * Gary Jennejohn, DENX Software Engineering, - * - * (C) Copyright 2004 - * Philippe Robin, ARM Ltd. - */ - -#include - -#define TIMER_ENABLE (1 << 7) -#define TIMER_MODE_MSK (1 << 6) -#define TIMER_MODE_FR (0 << 6) -#define TIMER_MODE_PD (1 << 6) - -#define TIMER_INT_EN (1 << 5) -#define TIMER_PRS_MSK (3 << 2) -#define TIMER_PRS_8S (1 << 3) -#define TIMER_SIZE_MSK (1 << 2) -#define TIMER_ONE_SHT (1 << 0) - -int timer_init (void) -{ - ulong tmr_ctrl_val; - - /* 1st disable the Timer */ - tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8); - tmr_ctrl_val &= ~TIMER_ENABLE; - *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val; - - /* - * The Timer Control Register has one Undefined/Shouldn't Use Bit - * So we should do read/modify/write Operation - */ - - /* - * Timer Mode : Free Running - * Interrupt : Disabled - * Prescale : 8 Stage, Clk/256 - * Tmr Siz : 16 Bit Counter - * Tmr in Wrapping Mode - */ - tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8); - tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT ); - tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S); - - *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val; - - return 0; -} diff --git a/arch/arm/mach-zynq/clk.c b/arch/arm/mach-zynq/clk.c index 5e1ba8d43ed..c1b018cf22e 100644 --- a/arch/arm/mach-zynq/clk.c +++ b/arch/arm/mach-zynq/clk.c @@ -4,7 +4,6 @@ * Copyright (C) 2013 Xilinx, Inc. All rights reserved. */ #include -#include #include #include #include diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index 3b6518c71c9..c75e453d573 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -3,10 +3,11 @@ * Copyright (C) 2012 Michal Simek * Copyright (C) 2012 Xilinx, Inc. All rights reserved. */ -#include +#include #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-zynq/ddrc.c b/arch/arm/mach-zynq/ddrc.c index 28988ef95b5..b9a2eef5a6f 100644 --- a/arch/arm/mach-zynq/ddrc.c +++ b/arch/arm/mach-zynq/ddrc.c @@ -4,7 +4,7 @@ * Copyright (C) 2012 - 2017 Xilinx, Inc. All rights reserved. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c index 5d9f4d23f34..ef877df0fe8 100644 --- a/arch/arm/mach-zynq/slcr.c +++ b/arch/arm/mach-zynq/slcr.c @@ -3,7 +3,6 @@ * Copyright (c) 2013 - 2017 Xilinx Inc. */ -#include #include #include #include diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c index fea1c9b12ad..8ef12ed65ce 100644 --- a/arch/arm/mach-zynq/spl.c +++ b/arch/arm/mach-zynq/spl.c @@ -2,7 +2,6 @@ /* * (C) Copyright 2014 - 2017 Xilinx, Inc. Michal Simek */ -#include #include #include #include diff --git a/arch/arm/mach-zynqmp-r5/cpu.c b/arch/arm/mach-zynqmp-r5/cpu.c index 0d368443d82..9a912dd5bd7 100644 --- a/arch/arm/mach-zynqmp-r5/cpu.c +++ b/arch/arm/mach-zynqmp-r5/cpu.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Xilinx, Inc. (Michal Simek) */ -#include #include #include #include diff --git a/arch/arm/mach-zynqmp/aes.c b/arch/arm/mach-zynqmp/aes.c index 8a2b7fdcbe9..9a05fbf9c11 100644 --- a/arch/arm/mach-zynqmp/aes.c +++ b/arch/arm/mach-zynqmp/aes.c @@ -7,9 +7,8 @@ * Christian Taedcke */ -#include #include - +#include #include #include #include diff --git a/arch/arm/mach-zynqmp/clk.c b/arch/arm/mach-zynqmp/clk.c index 3b05f8455bf..9b573b1746a 100644 --- a/arch/arm/mach-zynqmp/clk.c +++ b/arch/arm/mach-zynqmp/clk.c @@ -4,7 +4,6 @@ * Michal Simek */ -#include #include #include #include diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index 6ae27894ecd..07668c94689 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -4,9 +4,10 @@ * Michal Simek */ -#include #include #include +#include +#include #include #include #include diff --git a/arch/arm/mach-zynqmp/ecc_spl_init.c b/arch/arm/mach-zynqmp/ecc_spl_init.c index f547d8e3a5b..1eef1078951 100644 --- a/arch/arm/mach-zynqmp/ecc_spl_init.c +++ b/arch/arm/mach-zynqmp/ecc_spl_init.c @@ -5,7 +5,6 @@ * Jorge Ramirez-Ortiz */ -#include #include #include #include diff --git a/arch/arm/mach-zynqmp/handoff.c b/arch/arm/mach-zynqmp/handoff.c index dce92438926..b007307e1f3 100644 --- a/arch/arm/mach-zynqmp/handoff.c +++ b/arch/arm/mach-zynqmp/handoff.c @@ -5,7 +5,6 @@ * Michal Simek */ -#include #include #include #include diff --git a/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h b/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h index 2a9cffbd0f8..01a13d4c7c0 100644 --- a/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h +++ b/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h @@ -9,6 +9,8 @@ #ifndef ZYNQMP_AES_H #define ZYNQMP_AES_H +#include + struct zynqmp_aes { u64 srcaddr; u64 ivaddr; diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c index aff9054212c..9b46a25a1cb 100644 --- a/arch/arm/mach-zynqmp/mp.c +++ b/arch/arm/mach-zynqmp/mp.c @@ -4,14 +4,16 @@ * Michal Simek */ -#include +#include #include #include +#include #include #include #include #include #include +#include #define LOCK 0 #define SPLIT 1 diff --git a/arch/arm/mach-zynqmp/psu_spl_init.c b/arch/arm/mach-zynqmp/psu_spl_init.c index b4d7f44bbee..5b4d66359bf 100644 --- a/arch/arm/mach-zynqmp/psu_spl_init.c +++ b/arch/arm/mach-zynqmp/psu_spl_init.c @@ -4,7 +4,6 @@ * * Michal Simek */ -#include #include #include #include diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c index 979ff3aef6c..6b67245f348 100644 --- a/arch/arm/mach-zynqmp/spl.c +++ b/arch/arm/mach-zynqmp/spl.c @@ -5,7 +5,6 @@ * Michal Simek */ -#include #include #include #include diff --git a/arch/m68k/include/asm/global_data.h b/arch/m68k/include/asm/global_data.h index c2ef5770a3d..93efc722ba8 100644 --- a/arch/m68k/include/asm/global_data.h +++ b/arch/m68k/include/asm/global_data.h @@ -7,6 +7,8 @@ #ifndef __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H +#include + /* Architecture-specific global data */ struct arch_global_data { #ifdef CONFIG_SYS_I2C_FSL diff --git a/arch/m68k/lib/bdinfo.c b/arch/m68k/lib/bdinfo.c index 3719f11c03c..cf6ae5adddf 100644 --- a/arch/m68k/lib/bdinfo.c +++ b/arch/m68k/lib/bdinfo.c @@ -8,7 +8,6 @@ #include #include -#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c index cb224bd2542..52177670578 100644 --- a/arch/microblaze/cpu/spl.c +++ b/arch/microblaze/cpu/spl.c @@ -10,7 +10,6 @@ #include #include #include -#include #include void board_boot_order(u32 *spl_boot_list) diff --git a/arch/microblaze/include/asm/global_data.h b/arch/microblaze/include/asm/global_data.h index 93506dec894..bb4112f22a3 100644 --- a/arch/microblaze/include/asm/global_data.h +++ b/arch/microblaze/include/asm/global_data.h @@ -9,6 +9,7 @@ #define __ASM_GBL_DATA_H #include +#include /* Architecture-specific global data */ struct arch_global_data { diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h index 34b7e0bed94..147a95ecea8 100644 --- a/arch/mips/include/asm/global_data.h +++ b/arch/mips/include/asm/global_data.h @@ -9,6 +9,7 @@ #include #include +#include struct octeon_eeprom_mac_addr { u8 mac_addr_base[6]; diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c index 40469d1be09..89846c9723c 100644 --- a/arch/mips/lib/traps.c +++ b/arch/mips/lib/traps.c @@ -20,7 +20,6 @@ #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/mips/mach-mtmips/Kconfig b/arch/mips/mach-mtmips/Kconfig index 15b2792e619..3fcd0b8465b 100644 --- a/arch/mips/mach-mtmips/Kconfig +++ b/arch/mips/mach-mtmips/Kconfig @@ -80,6 +80,7 @@ config SOC_MT7621 bool "MT7621" select MIPS_CM select MIPS_L2_CACHE + select MMC_SUPPORTS_TUNING select SYS_CACHE_SHIFT_5 select SYS_MIPS_CACHE_INIT_RAM_LOAD select PINCTRL_MT7621 diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index de7bfa947f1..792fa01ab9e 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -4,7 +4,7 @@ * Scott McNutt */ -#include +#include #include #include #include diff --git a/arch/nios2/cpu/interrupts.c b/arch/nios2/cpu/interrupts.c index 90cabb67571..27093c4faa3 100644 --- a/arch/nios2/cpu/interrupts.c +++ b/arch/nios2/cpu/interrupts.c @@ -7,7 +7,6 @@ * Scott McNutt */ -#include #include #include #include diff --git a/arch/nios2/cpu/traps.c b/arch/nios2/cpu/traps.c index 087a05097d9..59690214f14 100644 --- a/arch/nios2/cpu/traps.c +++ b/arch/nios2/cpu/traps.c @@ -4,8 +4,8 @@ * Scott McNutt */ -#include #include +#include #include void trap_handler (struct pt_regs *regs) diff --git a/arch/nios2/include/asm/global_data.h b/arch/nios2/include/asm/global_data.h index b56e8a5078e..d9bbd54734e 100644 --- a/arch/nios2/include/asm/global_data.h +++ b/arch/nios2/include/asm/global_data.h @@ -7,6 +7,7 @@ #define __ASM_NIOS2_GLOBALDATA_H_ #include +#include /* Architecture-specific global data */ struct arch_global_data { diff --git a/arch/nios2/lib/bootm.c b/arch/nios2/lib/bootm.c index 657a17c7204..ce939ff5e15 100644 --- a/arch/nios2/lib/bootm.c +++ b/arch/nios2/lib/bootm.c @@ -4,7 +4,6 @@ * Scott McNutt */ -#include #include #include #include diff --git a/arch/nios2/lib/cache.c b/arch/nios2/lib/cache.c index 5864d8f0f47..8f543f2a2f2 100644 --- a/arch/nios2/lib/cache.c +++ b/arch/nios2/lib/cache.c @@ -5,7 +5,6 @@ * Implemented by fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com */ -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index f6ffe295b8e..e0be938ea98 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -9,7 +9,6 @@ * Derived from the MPC8260 and MPC85xx. */ -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc83xx/ecc.c b/arch/powerpc/cpu/mpc83xx/ecc.c index 3e24752e2f6..9ab5ea313d3 100644 --- a/arch/powerpc/cpu/mpc83xx/ecc.c +++ b/arch/powerpc/cpu/mpc83xx/ecc.c @@ -6,7 +6,6 @@ * based on the contribution of Marian Balakowicz */ -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c index 33b2151f878..1bd4f2b3449 100644 --- a/arch/powerpc/cpu/mpc83xx/fdt.c +++ b/arch/powerpc/cpu/mpc83xx/fdt.c @@ -6,7 +6,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc83xx/interrupts.c b/arch/powerpc/cpu/mpc83xx/interrupts.c index f9486678af3..d86c981811e 100644 --- a/arch/powerpc/cpu/mpc83xx/interrupts.c +++ b/arch/powerpc/cpu/mpc83xx/interrupts.c @@ -6,7 +6,6 @@ * Copyright 2004 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc83xx/law.c b/arch/powerpc/cpu/mpc83xx/law.c index 5e02f4094bb..ae60be9e877 100644 --- a/arch/powerpc/cpu/mpc83xx/law.c +++ b/arch/powerpc/cpu/mpc83xx/law.c @@ -3,7 +3,6 @@ * Copyright 2011 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc83xx/pci.c b/arch/powerpc/cpu/mpc83xx/pci.c index 65ef0497c2a..6f378c4e221 100644 --- a/arch/powerpc/cpu/mpc83xx/pci.c +++ b/arch/powerpc/cpu/mpc83xx/pci.c @@ -6,7 +6,6 @@ * with some bits from older board-specific PCI initialization. */ -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c index 47ca74c5c35..efa30c68338 100644 --- a/arch/powerpc/cpu/mpc83xx/pcie.c +++ b/arch/powerpc/cpu/mpc83xx/pcie.c @@ -7,7 +7,6 @@ * Anton Vorontsov */ -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc83xx/qe_io.c b/arch/powerpc/cpu/mpc83xx/qe_io.c index 52360703a7d..256dbfe8a4b 100644 --- a/arch/powerpc/cpu/mpc83xx/qe_io.c +++ b/arch/powerpc/cpu/mpc83xx/qe_io.c @@ -6,7 +6,6 @@ * based on source code of Shlomi Gridish */ -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc83xx/serdes.c b/arch/powerpc/cpu/mpc83xx/serdes.c index d4848b2ec4d..d3ca24422a5 100644 --- a/arch/powerpc/cpu/mpc83xx/serdes.c +++ b/arch/powerpc/cpu/mpc83xx/serdes.c @@ -9,7 +9,6 @@ */ #include -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index 6da8fc4381d..e847c03f378 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -12,7 +12,6 @@ #ifndef CONFIG_MPC83XX_SDRAM -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index b7a87fec2f5..72464962613 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -8,7 +8,6 @@ #ifndef CONFIG_CLK_MPC83XX -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c index b55bfaffcae..7036e3fae0c 100644 --- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c @@ -3,7 +3,7 @@ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc83xx/traps.c b/arch/powerpc/cpu/mpc83xx/traps.c index 94e6323d736..79ea1a9bb3c 100644 --- a/arch/powerpc/cpu/mpc83xx/traps.c +++ b/arch/powerpc/cpu/mpc83xx/traps.c @@ -11,7 +11,6 @@ * exceptions */ -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c index 013a171ed87..df2f0efe3ed 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c @@ -3,7 +3,8 @@ * Copyright 2012 Freescale Semiconductor, Inc. */ -#include +#include +#include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c index 8e18e12f634..25fdb4b0421 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c @@ -3,7 +3,6 @@ * Copyright 2012 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c index 79213348274..9ebb3d838fa 100644 --- a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c index e53dd43f31f..bbe4a0dd62b 100644 --- a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c @@ -4,7 +4,6 @@ */ #include -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index c7d473d4a1b..f91a4d441d3 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -3,7 +3,6 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index e8a3e82765f..6356b021638 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -9,7 +9,6 @@ */ #include -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index a67f37e3af9..574510fa088 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -3,8 +3,9 @@ * Copyright 2009-2012 Freescale Semiconductor, Inc */ -#include +#include #include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index e26436bf570..c56e98d4b49 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -6,7 +6,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index 9b6577e547e..945020f7ecb 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -3,7 +3,6 @@ * Copyright 2012 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 7c2de02c4c5..78316ea5ffe 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -3,7 +3,7 @@ * Copyright 2009-2011 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/interrupts.c b/arch/powerpc/cpu/mpc85xx/interrupts.c index bcbdfac0279..3c98768f22e 100644 --- a/arch/powerpc/cpu/mpc85xx/interrupts.c +++ b/arch/powerpc/cpu/mpc85xx/interrupts.c @@ -10,7 +10,7 @@ * Xianghua Xiao (X.Xiao@motorola.com) */ -#include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index 4b8844a4d96..af6731cbb3a 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -3,7 +3,7 @@ * Copyright 2008-2011 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index 7c47e415f05..b638f24ed14 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -3,7 +3,7 @@ * Copyright 2008-2011 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c index cbcb57fe3a5..bafff2083b3 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c index a48f3c15128..ad979caf6a7 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c @@ -4,7 +4,6 @@ */ #include -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c index 479ee085d3a..924afa096d1 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c @@ -4,7 +4,6 @@ */ #include -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c index 56e5ef6468c..d38041ef5c2 100644 --- a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c index 47f13e3c1cd..ec0f14ae6a7 100644 --- a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c @@ -4,7 +4,6 @@ */ #include -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c index 7a8f653727e..6d306d99c32 100644 --- a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c index 8c5d82ae8ad..49626fc1d1b 100644 --- a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c @@ -4,7 +4,6 @@ */ #include -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c index 540a6e6e191..ae5227a1eed 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c @@ -3,7 +3,8 @@ * Copyright 2011 Freescale Semiconductor, Inc. */ -#include +#include +#include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/p2041_serdes.c b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c index 3eca3a69326..3943859a518 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c @@ -3,7 +3,6 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c index 8f645258a5f..0675a59414b 100644 --- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c @@ -3,7 +3,8 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include +#include +#include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/p3041_serdes.c b/arch/powerpc/cpu/mpc85xx/p3041_serdes.c index ec8234c1c1e..b1586f110e8 100644 --- a/arch/powerpc/cpu/mpc85xx/p3041_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p3041_serdes.c @@ -3,7 +3,6 @@ * Copyright 2009-2011 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index db411162022..15ab4ac9385 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -3,7 +3,8 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include +#include +#include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/p4080_serdes.c b/arch/powerpc/cpu/mpc85xx/p4080_serdes.c index 463fa119c9b..438fd446be3 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_serdes.c @@ -3,7 +3,6 @@ * Copyright 2009-2010 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/p5040_ids.c b/arch/powerpc/cpu/mpc85xx/p5040_ids.c index bd05eae2551..0a34e066e94 100644 --- a/arch/powerpc/cpu/mpc85xx/p5040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5040_ids.c @@ -3,7 +3,8 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include +#include +#include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/p5040_serdes.c b/arch/powerpc/cpu/mpc85xx/p5040_serdes.c index 2327b2c2a41..409f2ac938d 100644 --- a/arch/powerpc/cpu/mpc85xx/p5040_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p5040_serdes.c @@ -3,7 +3,6 @@ * Copyright 2009-2011 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c index 6b4cbddcdfe..782874d79d7 100644 --- a/arch/powerpc/cpu/mpc85xx/portals.c +++ b/arch/powerpc/cpu/mpc85xx/portals.c @@ -3,7 +3,6 @@ * Copyright 2008-2011 Freescale Semiconductor, Inc. */ -#include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/qe_io.c b/arch/powerpc/cpu/mpc85xx/qe_io.c index 3cf41ca76d5..c3f7493efc7 100644 --- a/arch/powerpc/cpu/mpc85xx/qe_io.c +++ b/arch/powerpc/cpu/mpc85xx/qe_io.c @@ -6,7 +6,7 @@ * based on source code of Shlomi Gridish */ -#include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 9af40310b46..a7e1b3c98a9 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -9,7 +9,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c index ce2b9c21667..29318fad5f0 100644 --- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c @@ -3,7 +3,6 @@ * Copyright 2009 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/t1024_ids.c b/arch/powerpc/cpu/mpc85xx/t1024_ids.c index bab076b2b18..7239d28f936 100644 --- a/arch/powerpc/cpu/mpc85xx/t1024_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1024_ids.c @@ -3,7 +3,8 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include +#include +#include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/t1024_serdes.c b/arch/powerpc/cpu/mpc85xx/t1024_serdes.c index 16458e73be1..0d958fe131b 100644 --- a/arch/powerpc/cpu/mpc85xx/t1024_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t1024_serdes.c @@ -3,7 +3,6 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c b/arch/powerpc/cpu/mpc85xx/t1040_ids.c index 59f4f9c6692..bb92fc392cc 100644 --- a/arch/powerpc/cpu/mpc85xx/t1040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c @@ -3,7 +3,8 @@ * Copyright 2012 Freescale Semiconductor, Inc. */ -#include +#include +#include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c index 3a7fdef79c2..2033ebbaa5e 100644 --- a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c @@ -3,10 +3,11 @@ * Copyright 2012 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include +#include static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { diff --git a/arch/powerpc/cpu/mpc85xx/t2080_ids.c b/arch/powerpc/cpu/mpc85xx/t2080_ids.c index 390bb115375..26a2d745a86 100644 --- a/arch/powerpc/cpu/mpc85xx/t2080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t2080_ids.c @@ -3,7 +3,8 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ -#include +#include +#include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c index 5f34aab4531..6702acaf772 100644 --- a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c @@ -5,9 +5,10 @@ * Shengzhou Liu */ -#include +#include #include #include +#include #include "fsl_corenet2_serdes.h" struct serdes_config { diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c index 37ea7788ccf..c319bf5cff5 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c @@ -3,7 +3,8 @@ * Copyright 2012 Freescale Semiconductor, Inc. */ -#include +#include +#include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c index 61402e84ef6..36fe34f11ec 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c @@ -3,7 +3,6 @@ * Copyright 2012 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 2a78f0fe502..e0b36f869a9 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -6,7 +6,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c index 8f451b48624..db70f07500c 100644 --- a/arch/powerpc/cpu/mpc85xx/traps.c +++ b/arch/powerpc/cpu/mpc85xx/traps.c @@ -19,7 +19,7 @@ * This file handles the architecture-dependent parts of hardware exceptions */ -#include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 73d28f2a4e2..82f28749eb1 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -8,7 +8,6 @@ */ #include -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 30042902487..f1c1cbc1c3c 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -8,7 +8,6 @@ * cpu specific common code for 85xx/86xx processors. */ -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index 29489b46e6c..843dd191ccf 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -3,7 +3,6 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c index 8e1f6c964d3..29399bcd8b6 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c @@ -5,12 +5,14 @@ * Copyright 2012-2016 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include #include #include +#include +#include struct paace *ppaact; struct paace *sec; diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c index 35409dc8824..f16bc199663 100644 --- a/arch/powerpc/cpu/mpc8xxx/law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -6,7 +6,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c index b906279226a..831a11736cc 100644 --- a/arch/powerpc/cpu/mpc8xxx/pamu_table.c +++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c @@ -3,7 +3,6 @@ * Copyright 2012-2016 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index c0b4a1217d3..0c7288c7574 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -3,13 +3,13 @@ * Copyright 2011 Freescale Semiconductor, Inc. */ -#include #include #include #include #include #include #include +#include #include #include diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h index b94faa5408e..21dfce4c8c7 100644 --- a/arch/powerpc/include/asm/cache.h +++ b/arch/powerpc/include/asm/cache.h @@ -39,6 +39,8 @@ #endif #if defined(__KERNEL__) && !defined(__ASSEMBLY__) +#include + extern void flush_dcache_range(unsigned long start, unsigned long stop); extern void clean_dcache_range(unsigned long start, unsigned long stop); extern void invalidate_dcache_range(unsigned long start, unsigned long stop); diff --git a/arch/powerpc/include/asm/fsl_dma.h b/arch/powerpc/include/asm/fsl_dma.h index 1459db74bee..e69e7dbefe8 100644 --- a/arch/powerpc/include/asm/fsl_dma.h +++ b/arch/powerpc/include/asm/fsl_dma.h @@ -8,7 +8,7 @@ #ifndef _ASM_FSL_DMA_H_ #define _ASM_FSL_DMA_H_ -#include +#include #ifdef CONFIG_MPC83xx typedef struct fsl_dma { diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index 0af3d8902ac..4ce869b5c18 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -6,7 +6,9 @@ #ifndef _FSL_LIODN_H_ #define _FSL_LIODN_H_ -#include +#include +#include +#include #include struct srio_liodn_id_table { diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h index 54ef4fb6295..021eec72382 100644 --- a/arch/powerpc/include/asm/fsl_portals.h +++ b/arch/powerpc/include/asm/fsl_portals.h @@ -6,6 +6,8 @@ #ifndef _FSL_PORTALS_H_ #define _FSL_PORTALS_H_ +#include + /* entries must be in order and contiguous */ enum fsl_dpaa_dev { FSL_HW_PORTAL_SEC, diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index ddde4f80c63..fdf76115233 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -7,6 +7,7 @@ #define __FSL_SERDES_H #include +#include enum srds_prtcl { /* diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index f7860122a00..a9efbbdd3d4 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -93,4 +93,6 @@ struct arch_global_data { #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2") +#include + #endif /* __ASM_GBL_DATA_H */ diff --git a/arch/powerpc/include/asm/immap_8xx.h b/arch/powerpc/include/asm/immap_8xx.h index cf1300f6e29..e11300cab20 100644 --- a/arch/powerpc/include/asm/immap_8xx.h +++ b/arch/powerpc/include/asm/immap_8xx.h @@ -12,6 +12,8 @@ #ifndef __IMMAP_8XX__ #define __IMMAP_8XX__ +#include + /* System configuration registers. */ typedef struct sys_conf { diff --git a/arch/powerpc/lib/bdinfo.c b/arch/powerpc/lib/bdinfo.c index 55dcad5df8e..6491c210f4e 100644 --- a/arch/powerpc/lib/bdinfo.c +++ b/arch/powerpc/lib/bdinfo.c @@ -6,7 +6,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 75c6bfd2bf8..f55b5ff8320 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -7,7 +7,7 @@ */ -#include +#include #include #include #include diff --git a/arch/powerpc/lib/cache.c b/arch/powerpc/lib/cache.c index c4c5c2d4513..e480b269649 100644 --- a/arch/powerpc/lib/cache.c +++ b/arch/powerpc/lib/cache.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include diff --git a/arch/powerpc/lib/extable.c b/arch/powerpc/lib/extable.c index 7e9d4f22f39..fd45e8a790d 100644 --- a/arch/powerpc/lib/extable.c +++ b/arch/powerpc/lib/extable.c @@ -5,7 +5,6 @@ * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include /* diff --git a/arch/powerpc/lib/interrupts.c b/arch/powerpc/lib/interrupts.c index df312dfa28e..92b8a0bceac 100644 --- a/arch/powerpc/lib/interrupts.c +++ b/arch/powerpc/lib/interrupts.c @@ -7,7 +7,7 @@ * Gleb Natapov */ -#include +#include #include #include #include diff --git a/arch/powerpc/lib/kgdb.c b/arch/powerpc/lib/kgdb.c index 8727d18884c..20fcb7eef0e 100644 --- a/arch/powerpc/lib/kgdb.c +++ b/arch/powerpc/lib/kgdb.c @@ -1,4 +1,3 @@ -#include #include #include #include diff --git a/arch/powerpc/lib/spl.c b/arch/powerpc/lib/spl.c index b638ea7be61..3a24cbfff3b 100644 --- a/arch/powerpc/lib/spl.c +++ b/arch/powerpc/lib/spl.c @@ -2,7 +2,6 @@ /* * Copyright 2012 Stefan Roese */ -#include #include #include #include diff --git a/arch/powerpc/lib/stack.c b/arch/powerpc/lib/stack.c index 2e731aa8701..afd869e4ac3 100644 --- a/arch/powerpc/lib/stack.c +++ b/arch/powerpc/lib/stack.c @@ -10,7 +10,6 @@ * Sysgo Real-Time Solutions, GmbH * Marius Groeger */ -#include #include #include #include diff --git a/arch/powerpc/lib/time.c b/arch/powerpc/lib/time.c index 8d6babfb83d..0a0e75e726b 100644 --- a/arch/powerpc/lib/time.c +++ b/arch/powerpc/lib/time.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include diff --git a/arch/riscv/lib/boot.c b/arch/riscv/lib/boot.c index 03014c56dce..161335abee1 100644 --- a/arch/riscv/lib/boot.c +++ b/arch/riscv/lib/boot.c @@ -4,7 +4,8 @@ * Rick Chen, Andes Technology Corporation */ -#include +#include +#include unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc, char *const argv[]) diff --git a/arch/sandbox/include/asm/global_data.h b/arch/sandbox/include/asm/global_data.h index 001b2b53c1c..309422f75e3 100644 --- a/arch/sandbox/include/asm/global_data.h +++ b/arch/sandbox/include/asm/global_data.h @@ -10,6 +10,7 @@ #define __ASM_GBL_DATA_H #include +#include /* Architecture-specific global data */ struct arch_global_data { diff --git a/arch/sh/cpu/sh4/cache.c b/arch/sh/cpu/sh4/cache.c index 0f7dfdd3cf7..8c1839935ca 100644 --- a/arch/sh/cpu/sh4/cache.c +++ b/arch/sh/cpu/sh4/cache.c @@ -4,7 +4,6 @@ * (C) Copyright 2007 Nobuhiro Iwamatsu */ -#include #include #include #include diff --git a/arch/sh/cpu/sh4/cpu.c b/arch/sh/cpu/sh4/cpu.c index 1b2f50dbe6e..b0ad685a91b 100644 --- a/arch/sh/cpu/sh4/cpu.c +++ b/arch/sh/cpu/sh4/cpu.c @@ -4,7 +4,6 @@ * Nobuhiro Iwamatsu */ -#include #include #include #include diff --git a/arch/sh/cpu/sh4/interrupts.c b/arch/sh/cpu/sh4/interrupts.c index 278a3e32ac9..eace09aeabf 100644 --- a/arch/sh/cpu/sh4/interrupts.c +++ b/arch/sh/cpu/sh4/interrupts.c @@ -4,7 +4,6 @@ * Nobuhiro Iwamatsu */ -#include #include int interrupt_init(void) diff --git a/arch/sh/cpu/sh4/watchdog.c b/arch/sh/cpu/sh4/watchdog.c index bf403d3c520..c5974337465 100644 --- a/arch/sh/cpu/sh4/watchdog.c +++ b/arch/sh/cpu/sh4/watchdog.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/arch/sh/include/asm/global_data.h b/arch/sh/include/asm/global_data.h index bd946ffd8fd..933c302d68c 100644 --- a/arch/sh/include/asm/global_data.h +++ b/arch/sh/include/asm/global_data.h @@ -10,6 +10,8 @@ #ifndef __ASM_SH_GLOBALDATA_H_ #define __ASM_SH_GLOBALDATA_H_ +#include + /* Architecture-specific global data */ struct arch_global_data { }; diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c index b31fa6d7031..53b1c147c2e 100644 --- a/arch/sh/lib/board.c +++ b/arch/sh/lib/board.c @@ -3,7 +3,7 @@ * Copyright (C) 2016 Vladimir Zapolskiy */ -#include +#include #include #include diff --git a/arch/sh/lib/bootm.c b/arch/sh/lib/bootm.c index 05d586b1b6c..e298d766b52 100644 --- a/arch/sh/lib/bootm.c +++ b/arch/sh/lib/bootm.c @@ -7,7 +7,7 @@ * (c) Copyright 2008 Renesas Solutions Corp. */ -#include +#include #include #include #include diff --git a/arch/sh/lib/time.c b/arch/sh/lib/time.c index 19c8e3ca3e7..5feb1983556 100644 --- a/arch/sh/lib/time.c +++ b/arch/sh/lib/time.c @@ -10,7 +10,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include diff --git a/arch/sh/lib/time_sh2.c b/arch/sh/lib/time_sh2.c index 5484c543c6c..0ee7dc756ba 100644 --- a/arch/sh/lib/time_sh2.c +++ b/arch/sh/lib/time_sh2.c @@ -7,7 +7,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include diff --git a/arch/sh/lib/zimageboot.c b/arch/sh/lib/zimageboot.c index c2e285ff0f6..e731c6a7cb3 100644 --- a/arch/sh/lib/zimageboot.c +++ b/arch/sh/lib/zimageboot.c @@ -9,10 +9,10 @@ * Linux SuperH zImage loading and boot */ -#include #include #include #include +#include #include #include diff --git a/arch/x86/cpu/acpi_gpe.c b/arch/x86/cpu/acpi_gpe.c index da01e71335f..13fe695014b 100644 --- a/arch/x86/cpu/acpi_gpe.c +++ b/arch/x86/cpu/acpi_gpe.c @@ -6,10 +6,10 @@ #define LOG_CATEGORY UCLASS_IRQ -#include #include #include #include +#include #include #include #include diff --git a/arch/x86/cpu/apollolake/acpi.c b/arch/x86/cpu/apollolake/acpi.c index c610a7f4477..76230aea837 100644 --- a/arch/x86/cpu/apollolake/acpi.c +++ b/arch/x86/cpu/apollolake/acpi.c @@ -10,7 +10,6 @@ #define LOG_CATEGORY LOGC_ACPI -#include #include #include #include diff --git a/arch/x86/cpu/apollolake/cpu.c b/arch/x86/cpu/apollolake/cpu.c index 647c9df6a72..f480bb1d8c3 100644 --- a/arch/x86/cpu/apollolake/cpu.c +++ b/arch/x86/cpu/apollolake/cpu.c @@ -3,7 +3,6 @@ * Copyright 2019 Google LLC */ -#include #include #include #include diff --git a/arch/x86/cpu/apollolake/cpu_common.c b/arch/x86/cpu/apollolake/cpu_common.c index 9a5502617bf..498b306cd61 100644 --- a/arch/x86/cpu/apollolake/cpu_common.c +++ b/arch/x86/cpu/apollolake/cpu_common.c @@ -3,7 +3,6 @@ * Copyright 2019 Google LLC */ -#include #include #include #include diff --git a/arch/x86/cpu/apollolake/cpu_spl.c b/arch/x86/cpu/apollolake/cpu_spl.c index 8f48457ee22..8798fa79d4c 100644 --- a/arch/x86/cpu/apollolake/cpu_spl.c +++ b/arch/x86/cpu/apollolake/cpu_spl.c @@ -5,7 +5,6 @@ * Portions taken from coreboot */ -#include #include #include #include diff --git a/arch/x86/cpu/apollolake/fsp_bindings.c b/arch/x86/cpu/apollolake/fsp_bindings.c index fb75e1f7095..f6fbddce922 100644 --- a/arch/x86/cpu/apollolake/fsp_bindings.c +++ b/arch/x86/cpu/apollolake/fsp_bindings.c @@ -3,7 +3,6 @@ * Copyright 2020 B&R Industrial Automation GmbH - http://www.br-automation.com */ -#include #include #include #include diff --git a/arch/x86/cpu/apollolake/fsp_m.c b/arch/x86/cpu/apollolake/fsp_m.c index c6be707e4ea..19065e17ae0 100644 --- a/arch/x86/cpu/apollolake/fsp_m.c +++ b/arch/x86/cpu/apollolake/fsp_m.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c index a9b13c0c704..5fca19f90d3 100644 --- a/arch/x86/cpu/apollolake/fsp_s.c +++ b/arch/x86/cpu/apollolake/fsp_s.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/arch/x86/cpu/apollolake/hostbridge.c b/arch/x86/cpu/apollolake/hostbridge.c index 2405dec8525..9ee362239ef 100644 --- a/arch/x86/cpu/apollolake/hostbridge.c +++ b/arch/x86/cpu/apollolake/hostbridge.c @@ -11,7 +11,6 @@ #define LOG_CATEGORY UCLASS_NORTHBRIDGE -#include #include #include #include diff --git a/arch/x86/cpu/apollolake/lpc.c b/arch/x86/cpu/apollolake/lpc.c index 4be6366f043..531ff1cd91f 100644 --- a/arch/x86/cpu/apollolake/lpc.c +++ b/arch/x86/cpu/apollolake/lpc.c @@ -5,7 +5,6 @@ * From coreboot Apollo Lake support lpc.c */ -#include #include #include #include diff --git a/arch/x86/cpu/apollolake/pch.c b/arch/x86/cpu/apollolake/pch.c index a0f9b031dea..32190312ff8 100644 --- a/arch/x86/cpu/apollolake/pch.c +++ b/arch/x86/cpu/apollolake/pch.c @@ -3,7 +3,6 @@ * Copyright 2019 Google LLC */ -#include #include #include #include diff --git a/arch/x86/cpu/apollolake/pmc.c b/arch/x86/cpu/apollolake/pmc.c index 163119e2e9e..32fd0344861 100644 --- a/arch/x86/cpu/apollolake/pmc.c +++ b/arch/x86/cpu/apollolake/pmc.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_ACPI_PMC -#include #include #include #include diff --git a/arch/x86/cpu/apollolake/punit.c b/arch/x86/cpu/apollolake/punit.c index 5ed7963579e..b1503c25140 100644 --- a/arch/x86/cpu/apollolake/punit.c +++ b/arch/x86/cpu/apollolake/punit.c @@ -3,10 +3,10 @@ * Copyright 2019 Google LLC */ -#include #include #include #include +#include #include #include #include diff --git a/arch/x86/cpu/apollolake/spl.c b/arch/x86/cpu/apollolake/spl.c index 6078d5a200e..b351d73e7d8 100644 --- a/arch/x86/cpu/apollolake/spl.c +++ b/arch/x86/cpu/apollolake/spl.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY LOGC_BOOT -#include #include #include #include diff --git a/arch/x86/cpu/apollolake/systemagent.c b/arch/x86/cpu/apollolake/systemagent.c index b6bc2ba14f1..f966b9083fc 100644 --- a/arch/x86/cpu/apollolake/systemagent.c +++ b/arch/x86/cpu/apollolake/systemagent.c @@ -4,7 +4,6 @@ * Take from coreboot project file of the same name */ -#include #include #include #include diff --git a/arch/x86/cpu/apollolake/uart.c b/arch/x86/cpu/apollolake/uart.c index a9362436000..7e4c816dcef 100644 --- a/arch/x86/cpu/apollolake/uart.c +++ b/arch/x86/cpu/apollolake/uart.c @@ -7,7 +7,6 @@ * Some code from coreboot lpss.c */ -#include #include #include #include diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c index ccc4851b188..7821964f1fc 100644 --- a/arch/x86/cpu/baytrail/acpi.c +++ b/arch/x86/cpu/baytrail/acpi.c @@ -3,7 +3,6 @@ * Copyright (C) 2016, Bin Meng */ -#include #include #include #include diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c index c270426d820..7756a1a4a8e 100644 --- a/arch/x86/cpu/baytrail/cpu.c +++ b/arch/x86/cpu/baytrail/cpu.c @@ -5,7 +5,6 @@ * Based on code from coreboot */ -#include #include #include #include diff --git a/arch/x86/cpu/baytrail/early_uart.c b/arch/x86/cpu/baytrail/early_uart.c index 08dbd5538f7..3736127239e 100644 --- a/arch/x86/cpu/baytrail/early_uart.c +++ b/arch/x86/cpu/baytrail/early_uart.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Google, Inc */ -#include #include #include diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index fb3f946c45f..9eb456f90d1 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -5,7 +5,6 @@ * Copyright (C) 2015, Kodak Alaris, Inc */ -#include #include #include #include diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c index f73738ce5c0..839ff4d2bf2 100644 --- a/arch/x86/cpu/baytrail/valleyview.c +++ b/arch/x86/cpu/baytrail/valleyview.c @@ -3,7 +3,6 @@ * Copyright (C) 2014, Bin Meng */ -#include #include #include #include @@ -11,6 +10,7 @@ #include #include #include +#include #include /* GPIO SUS */ diff --git a/arch/x86/cpu/braswell/braswell.c b/arch/x86/cpu/braswell/braswell.c index 3345049993d..8cf4b628d41 100644 --- a/arch/x86/cpu/braswell/braswell.c +++ b/arch/x86/cpu/braswell/braswell.c @@ -3,10 +3,10 @@ * Copyright (C) 2017, Bin Meng */ -#include #include #include #include +#include int arch_cpu_init(void) { diff --git a/arch/x86/cpu/braswell/early_uart.c b/arch/x86/cpu/braswell/early_uart.c index d78c6b0feb6..8b28d28d136 100644 --- a/arch/x86/cpu/braswell/early_uart.c +++ b/arch/x86/cpu/braswell/early_uart.c @@ -3,7 +3,6 @@ * Copyright (C) 2017, Bin Meng */ -#include #include #define PCI_DEV_CONFIG(segbus, dev, fn) ( \ diff --git a/arch/x86/cpu/braswell/fsp_configs.c b/arch/x86/cpu/braswell/fsp_configs.c index 243298fd571..aaf3e67f81c 100644 --- a/arch/x86/cpu/braswell/fsp_configs.c +++ b/arch/x86/cpu/braswell/fsp_configs.c @@ -3,7 +3,6 @@ * Copyright (C) 2017, Bin Meng */ -#include #include #include #include diff --git a/arch/x86/cpu/broadwell/adsp.c b/arch/x86/cpu/broadwell/adsp.c index 1fa18237809..90b2449475e 100644 --- a/arch/x86/cpu/broadwell/adsp.c +++ b/arch/x86/cpu/broadwell/adsp.c @@ -9,7 +9,6 @@ #define LOG_CATEGORY UCLASS_SYSCON -#include #include #include #include diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c index cbd4a3b6797..dc6717eca40 100644 --- a/arch/x86/cpu/broadwell/cpu.c +++ b/arch/x86/cpu/broadwell/cpu.c @@ -5,7 +5,6 @@ * Based on code from coreboot src/soc/intel/broadwell/cpu.c */ -#include #include #include #include diff --git a/arch/x86/cpu/broadwell/cpu_from_spl.c b/arch/x86/cpu/broadwell/cpu_from_spl.c index df5a9675ee4..a48be295994 100644 --- a/arch/x86/cpu/broadwell/cpu_from_spl.c +++ b/arch/x86/cpu/broadwell/cpu_from_spl.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include @@ -13,6 +12,7 @@ #include #include #include +#include int misc_init_r(void) { diff --git a/arch/x86/cpu/broadwell/cpu_full.c b/arch/x86/cpu/broadwell/cpu_full.c index 2049dbfe24a..c43fb7a608b 100644 --- a/arch/x86/cpu/broadwell/cpu_full.c +++ b/arch/x86/cpu/broadwell/cpu_full.c @@ -5,7 +5,6 @@ * Based on code from coreboot src/soc/intel/broadwell/cpu.c */ -#include #include #include #include diff --git a/arch/x86/cpu/broadwell/iobp.c b/arch/x86/cpu/broadwell/iobp.c index cb5595c930e..f8b2a60d09f 100644 --- a/arch/x86/cpu/broadwell/iobp.c +++ b/arch/x86/cpu/broadwell/iobp.c @@ -5,7 +5,6 @@ * Modified from coreboot */ -#include #include #include #include diff --git a/arch/x86/cpu/broadwell/lpc.c b/arch/x86/cpu/broadwell/lpc.c index d2638a4e7a6..b945693f1cf 100644 --- a/arch/x86/cpu/broadwell/lpc.c +++ b/arch/x86/cpu/broadwell/lpc.c @@ -5,7 +5,6 @@ * From coreboot broadwell support */ -#include #include #include #include diff --git a/arch/x86/cpu/broadwell/me.c b/arch/x86/cpu/broadwell/me.c index ae16ce26499..3399d822e5b 100644 --- a/arch/x86/cpu/broadwell/me.c +++ b/arch/x86/cpu/broadwell/me.c @@ -5,7 +5,6 @@ * Based on code from coreboot src/soc/intel/broadwell/me_status.c */ -#include #include #include #include diff --git a/arch/x86/cpu/broadwell/northbridge.c b/arch/x86/cpu/broadwell/northbridge.c index 141babc51c3..d67ab03627d 100644 --- a/arch/x86/cpu/broadwell/northbridge.c +++ b/arch/x86/cpu/broadwell/northbridge.c @@ -3,7 +3,6 @@ * Copyright (C) 2011 The Chromium Authors */ -#include #include #include #include diff --git a/arch/x86/cpu/broadwell/pch.c b/arch/x86/cpu/broadwell/pch.c index 37fcddbb9b0..2c8b7380d96 100644 --- a/arch/x86/cpu/broadwell/pch.c +++ b/arch/x86/cpu/broadwell/pch.c @@ -3,7 +3,6 @@ * Copyright (c) 2016 Google, Inc */ -#include #include #include #include diff --git a/arch/x86/cpu/broadwell/pinctrl_broadwell.c b/arch/x86/cpu/broadwell/pinctrl_broadwell.c index 85bd37101ba..b6313c3466a 100644 --- a/arch/x86/cpu/broadwell/pinctrl_broadwell.c +++ b/arch/x86/cpu/broadwell/pinctrl_broadwell.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Google, Inc */ -#include #include #include #include diff --git a/arch/x86/cpu/broadwell/power_state.c b/arch/x86/cpu/broadwell/power_state.c index 62fd2e8d2c0..e1d60915f55 100644 --- a/arch/x86/cpu/broadwell/power_state.c +++ b/arch/x86/cpu/broadwell/power_state.c @@ -5,7 +5,6 @@ * Copyright (C) 2016 Google, Inc. */ -#include #include #include #include diff --git a/arch/x86/cpu/broadwell/refcode.c b/arch/x86/cpu/broadwell/refcode.c index df2df7972e9..653d31dd67c 100644 --- a/arch/x86/cpu/broadwell/refcode.c +++ b/arch/x86/cpu/broadwell/refcode.c @@ -6,7 +6,7 @@ * Copyright (c) 2016 Google, Inc */ -#include +#include #include #include #include diff --git a/arch/x86/cpu/broadwell/sata.c b/arch/x86/cpu/broadwell/sata.c index be3c9e764ef..0f67ba9666f 100644 --- a/arch/x86/cpu/broadwell/sata.c +++ b/arch/x86/cpu/broadwell/sata.c @@ -5,7 +5,6 @@ * From coreboot src/soc/intel/broadwell/sata.c */ -#include #include #include #include diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c index d30ebee021e..cd534a17cf1 100644 --- a/arch/x86/cpu/broadwell/sdram.c +++ b/arch/x86/cpu/broadwell/sdram.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY UCLASS_RAM -#include #include #include #include diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 82fe4c71cd2..d474c79e25e 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -5,7 +5,6 @@ * Graeme Russ, graeme.russ@gmail.com. */ -#include #include #include #include diff --git a/arch/x86/cpu/coreboot/coreboot_spl.c b/arch/x86/cpu/coreboot/coreboot_spl.c index 36661871e92..566c65a96ae 100644 --- a/arch/x86/cpu/coreboot/coreboot_spl.c +++ b/arch/x86/cpu/coreboot/coreboot_spl.c @@ -3,7 +3,6 @@ * Copyright 2020 Google LLC */ -#include #include int dram_init(void) diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c index 26352df421f..013225f129a 100644 --- a/arch/x86/cpu/coreboot/sdram.c +++ b/arch/x86/cpu/coreboot/sdram.c @@ -5,7 +5,6 @@ * Graeme Russ, */ -#include #include #include #include diff --git a/arch/x86/cpu/coreboot/timestamp.c b/arch/x86/cpu/coreboot/timestamp.c index 3ad611a530c..ec4003c4e77 100644 --- a/arch/x86/cpu/coreboot/timestamp.c +++ b/arch/x86/cpu/coreboot/timestamp.c @@ -5,10 +5,10 @@ * Modified from the coreboot version */ -#include #include #include #include +#include #include static struct timestamp_table *ts_table __section(".data"); diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index ce55efc454b..c8433360f28 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -20,7 +20,6 @@ #define LOG_CATEGORY UCLASS_CPU -#include #include #include #include diff --git a/arch/x86/cpu/cpu_x86.c b/arch/x86/cpu/cpu_x86.c index 59da41f3833..6c53f0ea821 100644 --- a/arch/x86/cpu/cpu_x86.c +++ b/arch/x86/cpu/cpu_x86.c @@ -3,7 +3,6 @@ * Copyright (C) 2015, Bin Meng */ -#include #include #include #include diff --git a/arch/x86/cpu/efi/app.c b/arch/x86/cpu/efi/app.c index f754489784a..218a68c4642 100644 --- a/arch/x86/cpu/efi/app.c +++ b/arch/x86/cpu/efi/app.c @@ -3,11 +3,11 @@ * Copyright (c) 2015 Google, Inc */ -#include #include #include #include #include +#include int arch_cpu_init(void) { diff --git a/arch/x86/cpu/efi/payload.c b/arch/x86/cpu/efi/payload.c index 708bfbe7ee4..642a87a37d8 100644 --- a/arch/x86/cpu/efi/payload.c +++ b/arch/x86/cpu/efi/payload.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include @@ -17,6 +16,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/cpu/efi/sdram.c b/arch/x86/cpu/efi/sdram.c index 56f3326146c..6fe40071140 100644 --- a/arch/x86/cpu/efi/sdram.c +++ b/arch/x86/cpu/efi/sdram.c @@ -3,7 +3,6 @@ * Copyright (c) 2015 Google, Inc */ -#include #include #include #include diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index 8882532ebf3..db2727d7485 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -18,7 +18,6 @@ * src/arch/x86/lib/cpu.c */ -#include #include #include #include @@ -32,6 +31,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c index f3f3527237f..b3f4214acdb 100644 --- a/arch/x86/cpu/i386/interrupt.c +++ b/arch/x86/cpu/i386/interrupt.c @@ -10,7 +10,6 @@ * Copyright (C) 1991, 1992 Linus Torvalds */ -#include #include #include #include diff --git a/arch/x86/cpu/intel_common/acpi.c b/arch/x86/cpu/intel_common/acpi.c index d94ec208f65..29676b4abfa 100644 --- a/arch/x86/cpu/intel_common/acpi.c +++ b/arch/x86/cpu/intel_common/acpi.c @@ -8,7 +8,6 @@ * Modified from coreboot src/soc/intel/common/block/acpi.c */ -#include #include #include #include diff --git a/arch/x86/cpu/intel_common/car.S b/arch/x86/cpu/intel_common/car.S index 00308dbdef9..46d9ede09cb 100644 --- a/arch/x86/cpu/intel_common/car.S +++ b/arch/x86/cpu/intel_common/car.S @@ -10,7 +10,6 @@ * Copyright (C) 2012 Kyösti Mälkki */ -#include #include #include #include diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c index 8f489e6c651..e7f41913042 100644 --- a/arch/x86/cpu/intel_common/cpu.c +++ b/arch/x86/cpu/intel_common/cpu.c @@ -7,7 +7,6 @@ * Some code taken from coreboot cpulib.c */ -#include #include #include #include diff --git a/arch/x86/cpu/intel_common/cpu_from_spl.c b/arch/x86/cpu/intel_common/cpu_from_spl.c index 1c0dcedb582..48b2ef253cb 100644 --- a/arch/x86/cpu/intel_common/cpu_from_spl.c +++ b/arch/x86/cpu/intel_common/cpu_from_spl.c @@ -3,7 +3,6 @@ * Copyright (c) 2016 Google, Inc */ -#include #include #include #include diff --git a/arch/x86/cpu/intel_common/fast_spi.c b/arch/x86/cpu/intel_common/fast_spi.c index 5d3944dee2c..e1d536be212 100644 --- a/arch/x86/cpu/intel_common/fast_spi.c +++ b/arch/x86/cpu/intel_common/fast_spi.c @@ -3,7 +3,6 @@ * Copyright 2019 Google LLC */ -#include #include #include #include diff --git a/arch/x86/cpu/intel_common/generic_wifi.c b/arch/x86/cpu/intel_common/generic_wifi.c index 61ec5391b09..75fa4e01d8a 100644 --- a/arch/x86/cpu/intel_common/generic_wifi.c +++ b/arch/x86/cpu/intel_common/generic_wifi.c @@ -6,7 +6,6 @@ * Modified from coreboot src/drivers/wifi/generic.c */ -#include #include #include #include diff --git a/arch/x86/cpu/intel_common/intel_opregion.c b/arch/x86/cpu/intel_common/intel_opregion.c index 1eed21d8cdf..78caff0dc12 100644 --- a/arch/x86/cpu/intel_common/intel_opregion.c +++ b/arch/x86/cpu/intel_common/intel_opregion.c @@ -6,7 +6,6 @@ * Modified from coreboot src/soc/intel/gma/opregion.c */ -#include #include #include #include diff --git a/arch/x86/cpu/intel_common/itss.c b/arch/x86/cpu/intel_common/itss.c index ec73b3d8931..6d3184f969f 100644 --- a/arch/x86/cpu/intel_common/itss.c +++ b/arch/x86/cpu/intel_common/itss.c @@ -9,7 +9,6 @@ * Taken from coreboot itss.c */ -#include #include #include #include diff --git a/arch/x86/cpu/intel_common/lpc.c b/arch/x86/cpu/intel_common/lpc.c index af68c0f079c..f2bdf8c1e87 100644 --- a/arch/x86/cpu/intel_common/lpc.c +++ b/arch/x86/cpu/intel_common/lpc.c @@ -3,7 +3,6 @@ * Copyright (c) 2016 Google, Inc */ -#include #include #include #include diff --git a/arch/x86/cpu/intel_common/lpss.c b/arch/x86/cpu/intel_common/lpss.c index 26a2d2d1e36..44cd3f0ca5f 100644 --- a/arch/x86/cpu/intel_common/lpss.c +++ b/arch/x86/cpu/intel_common/lpss.c @@ -7,7 +7,6 @@ * Some code from coreboot lpss.c */ -#include #include #include #include diff --git a/arch/x86/cpu/intel_common/me_status.c b/arch/x86/cpu/intel_common/me_status.c index abc5f6fbc77..a09bd5029eb 100644 --- a/arch/x86/cpu/intel_common/me_status.c +++ b/arch/x86/cpu/intel_common/me_status.c @@ -5,7 +5,6 @@ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. */ -#include #include #include diff --git a/arch/x86/cpu/intel_common/microcode.c b/arch/x86/cpu/intel_common/microcode.c index 4d8e1d21083..6cad2727075 100644 --- a/arch/x86/cpu/intel_common/microcode.c +++ b/arch/x86/cpu/intel_common/microcode.c @@ -6,7 +6,6 @@ * Microcode update for Intel PIII and later CPUs */ -#include #include #include #include diff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c index ff959d1bd8d..c834c05d130 100644 --- a/arch/x86/cpu/intel_common/mrc.c +++ b/arch/x86/cpu/intel_common/mrc.c @@ -5,17 +5,17 @@ #define LOG_CATEGORY UCLASS_RAM -#include +#include #include #include #include #include #include +#include #include #include #include #include -#include #include #include #include diff --git a/arch/x86/cpu/intel_common/p2sb.c b/arch/x86/cpu/intel_common/p2sb.c index e4e53f73c08..7aad8f8ca56 100644 --- a/arch/x86/cpu/intel_common/p2sb.c +++ b/arch/x86/cpu/intel_common/p2sb.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY UCLASS_P2SB -#include #include #include #include diff --git a/arch/x86/cpu/intel_common/pch.c b/arch/x86/cpu/intel_common/pch.c index af82b64a13c..c4cc478b306 100644 --- a/arch/x86/cpu/intel_common/pch.c +++ b/arch/x86/cpu/intel_common/pch.c @@ -3,7 +3,6 @@ * Copyright (c) 2016 Google, Inc */ -#include #include #include diff --git a/arch/x86/cpu/intel_common/report_platform.c b/arch/x86/cpu/intel_common/report_platform.c index a3612817c45..a7524435ba0 100644 --- a/arch/x86/cpu/intel_common/report_platform.c +++ b/arch/x86/cpu/intel_common/report_platform.c @@ -5,12 +5,12 @@ * Copyright (C) 2012 Google Inc. */ -#include #include #include #include #include #include +#include static void report_cpu_info(void) { diff --git a/arch/x86/cpu/ioapic.c b/arch/x86/cpu/ioapic.c index 4f99de6ece2..fa912bac57d 100644 --- a/arch/x86/cpu/ioapic.c +++ b/arch/x86/cpu/ioapic.c @@ -3,7 +3,6 @@ * Copyright (C) 2015, Bin Meng */ -#include #include #include #include diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c index 766b2451a2c..d4dd1816092 100644 --- a/arch/x86/cpu/irq.c +++ b/arch/x86/cpu/irq.c @@ -3,7 +3,6 @@ * Copyright (C) 2015, Bin Meng */ -#include #include #include #include diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 417290f559e..8ae4798f125 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2014 Google, Inc */ -#include #include #include #include diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index e71a10bfd44..d71ab0a6385 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -10,7 +10,6 @@ * Copyright (C) 2011 Google Inc. */ -#include #include #include #include diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c index bee1671baf8..ac868025f8e 100644 --- a/arch/x86/cpu/ivybridge/early_me.c +++ b/arch/x86/cpu/ivybridge/early_me.c @@ -5,7 +5,6 @@ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. */ -#include #include #include #include diff --git a/arch/x86/cpu/ivybridge/fsp_configs.c b/arch/x86/cpu/ivybridge/fsp_configs.c index 3c4ea6c267f..19b6ef283bc 100644 --- a/arch/x86/cpu/ivybridge/fsp_configs.c +++ b/arch/x86/cpu/ivybridge/fsp_configs.c @@ -3,7 +3,6 @@ * Copyright (C) 2016, Bin Meng */ -#include #include #include #include diff --git a/arch/x86/cpu/ivybridge/ivybridge.c b/arch/x86/cpu/ivybridge/ivybridge.c index eb3f362e4e9..81b54bb8dda 100644 --- a/arch/x86/cpu/ivybridge/ivybridge.c +++ b/arch/x86/cpu/ivybridge/ivybridge.c @@ -3,10 +3,10 @@ * Copyright (C) 2016, Bin Meng */ -#include #include #include #include +#include int arch_cpu_init(void) { diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index f931d2be1b5..17a47edadbb 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -5,7 +5,6 @@ * Copyright (C) 2008-2009 coresystems GmbH */ -#include #include #include #include diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index 3906a69796f..b72de96a277 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -6,7 +6,6 @@ * Copyright (C) 2011 The Chromium Authors */ -#include #include #include #include diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c index 994f8a4ff6a..76e52f38ad8 100644 --- a/arch/x86/cpu/ivybridge/northbridge.c +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -6,7 +6,6 @@ * Copyright (C) 2011 The Chromium Authors */ -#include #include #include #include diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c index f47ecdffae7..4e2484fa956 100644 --- a/arch/x86/cpu/ivybridge/sata.c +++ b/arch/x86/cpu/ivybridge/sata.c @@ -4,7 +4,6 @@ * Copyright (C) 2008-2009 coresystems GmbH */ -#include #include #include #include diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 95a826da713..bddec6c66b6 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -11,7 +11,6 @@ #define LOG_CATEGORY UCLASS_RAM -#include #include #include #include diff --git a/arch/x86/cpu/ivybridge/sdram_nop.c b/arch/x86/cpu/ivybridge/sdram_nop.c index 51dfe23f94d..d20c9a2a379 100644 --- a/arch/x86/cpu/ivybridge/sdram_nop.c +++ b/arch/x86/cpu/ivybridge/sdram_nop.c @@ -3,7 +3,6 @@ * Copyright (c) 2016 Google, Inc */ -#include #include #include diff --git a/arch/x86/cpu/lapic.c b/arch/x86/cpu/lapic.c index c0691454f12..55b1b1833ee 100644 --- a/arch/x86/cpu/lapic.c +++ b/arch/x86/cpu/lapic.c @@ -6,7 +6,6 @@ * Copyright (C) 2014 Google, Inc */ -#include #include #include #include diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c index a133a5d8116..aa1f47d7227 100644 --- a/arch/x86/cpu/mp_init.c +++ b/arch/x86/cpu/mp_init.c @@ -5,13 +5,13 @@ * Based on code from the coreboot file of the same name */ -#include #include #include #include #include #include #include +#include #include #include #include diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c index 9c24ae984e9..50cba5fb88d 100644 --- a/arch/x86/cpu/mtrr.c +++ b/arch/x86/cpu/mtrr.c @@ -16,7 +16,6 @@ * since the MTRR registers are sometimes in flux. */ -#include #include #include #include diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c index 8a992ed8233..a7ad57f6de0 100644 --- a/arch/x86/cpu/pci.c +++ b/arch/x86/cpu/pci.c @@ -8,7 +8,6 @@ * Daniel Engström, Omicron Ceti AB, */ -#include #include #include #include diff --git a/arch/x86/cpu/qemu/cpu.c b/arch/x86/cpu/qemu/cpu.c index 735b6560843..0708a380626 100644 --- a/arch/x86/cpu/qemu/cpu.c +++ b/arch/x86/cpu/qemu/cpu.c @@ -3,7 +3,6 @@ * Copyright (C) 2015, Miao Yan */ -#include #include #include #include diff --git a/arch/x86/cpu/qemu/dram.c b/arch/x86/cpu/qemu/dram.c index d83abf00527..62a301c0fd3 100644 --- a/arch/x86/cpu/qemu/dram.c +++ b/arch/x86/cpu/qemu/dram.c @@ -3,7 +3,6 @@ * Copyright (C) 2015, Bin Meng */ -#include #include #include #include diff --git a/arch/x86/cpu/qemu/e820.c b/arch/x86/cpu/qemu/e820.c index ebfe5956442..17a04f86479 100644 --- a/arch/x86/cpu/qemu/e820.c +++ b/arch/x86/cpu/qemu/e820.c @@ -6,7 +6,6 @@ * (C) Copyright 2019 Bin Meng */ -#include #include #include #include diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index 70414556086..262584d01f0 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -3,7 +3,6 @@ * Copyright (C) 2015, Bin Meng */ -#include #include #include #include @@ -14,6 +13,7 @@ #include #include #include +#include static bool i440fx; diff --git a/arch/x86/cpu/qfw_cpu.c b/arch/x86/cpu/qfw_cpu.c index ee00b8fe732..468df5a36e6 100644 --- a/arch/x86/cpu/qfw_cpu.c +++ b/arch/x86/cpu/qfw_cpu.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Google, Inc */ -#include #include #include #include diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c index 0e18ceab68d..80e94600fc5 100644 --- a/arch/x86/cpu/quark/acpi.c +++ b/arch/x86/cpu/quark/acpi.c @@ -3,13 +3,13 @@ * Copyright (C) 2016, Bin Meng */ -#include #include #include #include #include #include #include +#include static int quark_write_fadt(struct acpi_ctx *ctx, const struct acpi_writer *entry) diff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c index ad98f3e07ba..34e576940d4 100644 --- a/arch/x86/cpu/quark/dram.c +++ b/arch/x86/cpu/quark/dram.c @@ -3,7 +3,6 @@ * Copyright (C) 2015, Bin Meng */ -#include #include #include #include diff --git a/arch/x86/cpu/quark/hte.c b/arch/x86/cpu/quark/hte.c index df14779357d..3cca6bd4c22 100644 --- a/arch/x86/cpu/quark/hte.c +++ b/arch/x86/cpu/quark/hte.c @@ -7,7 +7,6 @@ * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei */ -#include #include #include #include "mrc_util.h" diff --git a/arch/x86/cpu/quark/mrc.c b/arch/x86/cpu/quark/mrc.c index ce3c2b8ab42..be9c36b96c4 100644 --- a/arch/x86/cpu/quark/mrc.c +++ b/arch/x86/cpu/quark/mrc.c @@ -32,9 +32,9 @@ * DRAM unit configuration based on Valleyview MRC. */ -#include #include #include +#include #include "mrc_util.h" #include "smc.h" diff --git a/arch/x86/cpu/quark/mrc_util.c b/arch/x86/cpu/quark/mrc_util.c index b0bc59b71ef..85408b3e335 100644 --- a/arch/x86/cpu/quark/mrc_util.c +++ b/arch/x86/cpu/quark/mrc_util.c @@ -7,12 +7,12 @@ * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei */ -#include #include #include #include #include #include +#include #include "mrc_util.h" #include "hte.h" #include "smc.h" diff --git a/arch/x86/cpu/quark/msg_port.c b/arch/x86/cpu/quark/msg_port.c index d4f8c082ffc..6261766cdf8 100644 --- a/arch/x86/cpu/quark/msg_port.c +++ b/arch/x86/cpu/quark/msg_port.c @@ -3,7 +3,6 @@ * Copyright (C) 2015, Bin Meng */ -#include #include #include #include diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index 62b83c228cf..fdf92b2c0c3 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -3,7 +3,6 @@ * Copyright (C) 2015, Bin Meng */ -#include #include #include #include @@ -19,6 +18,7 @@ #include #include #include +#include #include static void quark_setup_mtrr(void) diff --git a/arch/x86/cpu/quark/smc.c b/arch/x86/cpu/quark/smc.c index b4b3e1204bd..a7e92b3f5c1 100644 --- a/arch/x86/cpu/quark/smc.c +++ b/arch/x86/cpu/quark/smc.c @@ -7,11 +7,12 @@ * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei */ -#include #include #include #include #include +#include +#include #include "mrc_util.h" #include "hte.h" #include "smc.h" diff --git a/arch/x86/cpu/queensbay/fsp_configs.c b/arch/x86/cpu/queensbay/fsp_configs.c index 381edd07615..3b5cbdb44f1 100644 --- a/arch/x86/cpu/queensbay/fsp_configs.c +++ b/arch/x86/cpu/queensbay/fsp_configs.c @@ -4,7 +4,6 @@ * Copyright (C) 2014, Bin Meng */ -#include #include void fsp_update_configs(struct fsp_config_data *config, diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index 4a008622d19..7c7eb413f99 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -3,7 +3,6 @@ * Copyright (C) 2014, Bin Meng */ -#include #include #include #include diff --git a/arch/x86/cpu/slimbootloader/sdram.c b/arch/x86/cpu/slimbootloader/sdram.c index fbb33b246e5..75ca5273625 100644 --- a/arch/x86/cpu/slimbootloader/sdram.c +++ b/arch/x86/cpu/slimbootloader/sdram.c @@ -3,7 +3,6 @@ * Copyright (C) 2019 Intel Corporation */ -#include #include #include #include diff --git a/arch/x86/cpu/slimbootloader/serial.c b/arch/x86/cpu/slimbootloader/serial.c index d28b280890d..4c889dad6d2 100644 --- a/arch/x86/cpu/slimbootloader/serial.c +++ b/arch/x86/cpu/slimbootloader/serial.c @@ -3,7 +3,6 @@ * Copyright (C) 2019 Intel Corporation */ -#include #include #include #include diff --git a/arch/x86/cpu/slimbootloader/slimbootloader.c b/arch/x86/cpu/slimbootloader/slimbootloader.c index ec5b87cfd63..142c9341cf8 100644 --- a/arch/x86/cpu/slimbootloader/slimbootloader.c +++ b/arch/x86/cpu/slimbootloader/slimbootloader.c @@ -3,7 +3,6 @@ * Copyright (C) 2019 Intel Corporation */ -#include #include #include #include diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c index 1d37cc9e2b0..d4d0ef6f855 100644 --- a/arch/x86/cpu/tangier/acpi.c +++ b/arch/x86/cpu/tangier/acpi.c @@ -5,7 +5,6 @@ * Partially based on acpi.c for other x86 platforms */ -#include #include #include #include diff --git a/arch/x86/cpu/tangier/pinmux.c b/arch/x86/cpu/tangier/pinmux.c index 23bfa7c18d2..6afb8646a98 100644 --- a/arch/x86/cpu/tangier/pinmux.c +++ b/arch/x86/cpu/tangier/pinmux.c @@ -3,7 +3,6 @@ * Copyright (c) 2018 Emlid Limited */ -#include #include #include #include diff --git a/arch/x86/cpu/tangier/sdram.c b/arch/x86/cpu/tangier/sdram.c index 374b262b134..6192f2296b8 100644 --- a/arch/x86/cpu/tangier/sdram.c +++ b/arch/x86/cpu/tangier/sdram.c @@ -3,7 +3,6 @@ * Copyright (c) 2017 Intel Corporation */ -#include #include #include #include diff --git a/arch/x86/cpu/tangier/sysreset.c b/arch/x86/cpu/tangier/sysreset.c index b03bc28f935..f57423a611d 100644 --- a/arch/x86/cpu/tangier/sysreset.c +++ b/arch/x86/cpu/tangier/sysreset.c @@ -5,7 +5,6 @@ * Reset driver for tangier processor */ -#include #include #include #include diff --git a/arch/x86/cpu/tangier/tangier.c b/arch/x86/cpu/tangier/tangier.c index 1e2f6cc8b70..8a8f7d27a9d 100644 --- a/arch/x86/cpu/tangier/tangier.c +++ b/arch/x86/cpu/tangier/tangier.c @@ -3,7 +3,6 @@ * Copyright (c) 2017 Intel Corporation */ -#include #include #include #include diff --git a/arch/x86/cpu/turbo.c b/arch/x86/cpu/turbo.c index e2c84cddec8..c9b402c4dc7 100644 --- a/arch/x86/cpu/turbo.c +++ b/arch/x86/cpu/turbo.c @@ -5,7 +5,6 @@ * Copyright (C) 2011 The Chromium Authors. */ -#include #include #include #include diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c index 5ea746ecce4..80eab710315 100644 --- a/arch/x86/cpu/x86_64/cpu.c +++ b/arch/x86/cpu/x86_64/cpu.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/arch/x86/cpu/x86_64/interrupts.c b/arch/x86/cpu/x86_64/interrupts.c index 634f7660c03..b84ff798814 100644 --- a/arch/x86/cpu/x86_64/interrupts.c +++ b/arch/x86/cpu/x86_64/interrupts.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include diff --git a/arch/x86/cpu/x86_64/misc.c b/arch/x86/cpu/x86_64/misc.c index 691b67ff68a..294511e6eba 100644 --- a/arch/x86/cpu/x86_64/misc.c +++ b/arch/x86/cpu/x86_64/misc.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/include/asm/arch-quark/mrc.h b/arch/x86/include/asm/arch-quark/mrc.h index 2353426cd6d..40c92a549cd 100644 --- a/arch/x86/include/asm/arch-quark/mrc.h +++ b/arch/x86/include/asm/arch-quark/mrc.h @@ -10,6 +10,8 @@ #ifndef _MRC_H_ #define _MRC_H_ +#include + #define MRC_VERSION 0x0111 /* architectural definitions */ diff --git a/arch/x86/include/asm/arch-quark/msg_port.h b/arch/x86/include/asm/arch-quark/msg_port.h index 9527fdad3fd..98a9360d543 100644 --- a/arch/x86/include/asm/arch-quark/msg_port.h +++ b/arch/x86/include/asm/arch-quark/msg_port.h @@ -34,6 +34,8 @@ #ifndef __ASSEMBLY__ +#include + /** * msg_port_setup - set up the message port control register * diff --git a/arch/x86/include/asm/arch-quark/quark.h b/arch/x86/include/asm/arch-quark/quark.h index feca1983ba8..dec30e2b27f 100644 --- a/arch/x86/include/asm/arch-quark/quark.h +++ b/arch/x86/include/asm/arch-quark/quark.h @@ -71,6 +71,8 @@ #ifndef __ASSEMBLY__ +#include + /* variable range MTRR usage */ enum { MTRR_VAR_ROM, diff --git a/arch/x86/include/asm/cb_sysinfo.h b/arch/x86/include/asm/cb_sysinfo.h index 12fa395ffd2..5864b2700ce 100644 --- a/arch/x86/include/asm/cb_sysinfo.h +++ b/arch/x86/include/asm/cb_sysinfo.h @@ -9,6 +9,7 @@ #define _COREBOOT_SYSINFO_H #include +#include /* Maximum number of memory range definitions */ #define SYSINFO_MAX_MEM_RANGES 32 diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h index 0dfb64babb9..54aeffb9889 100644 --- a/arch/x86/include/asm/coreboot_tables.h +++ b/arch/x86/include/asm/coreboot_tables.h @@ -8,6 +8,9 @@ #ifndef _COREBOOT_TABLES_H #define _COREBOOT_TABLES_H +#include +#include + struct timestamp_entry { u32 entry_id; u64 entry_stamp; diff --git a/arch/x86/include/asm/early_cmos.h b/arch/x86/include/asm/early_cmos.h index 543a9e69f03..007aeb7c23e 100644 --- a/arch/x86/include/asm/early_cmos.h +++ b/arch/x86/include/asm/early_cmos.h @@ -6,6 +6,8 @@ #ifndef __EARLY_CMOS_H #define __EARLY_CMOS_H +#include + /* CMOS actually resides in the RTC SRAM */ #define CMOS_IO_PORT 0x70 diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 1ef7f1f0349..06bd80ccc13 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -12,6 +12,7 @@ #include #include #include +#include enum pei_boot_mode_t { PEI_BOOT_NONE = 0, diff --git a/arch/x86/include/asm/handoff.h b/arch/x86/include/asm/handoff.h index aec49b9b815..5f6691939eb 100644 --- a/arch/x86/include/asm/handoff.h +++ b/arch/x86/include/asm/handoff.h @@ -9,6 +9,8 @@ #ifndef __x86_asm_handoff_h #define __x86_asm_handoff_h +#include + /** * struct arch_spl_handoff - architecture-specific handoff info * diff --git a/arch/x86/include/asm/me_common.h b/arch/x86/include/asm/me_common.h index 85703683149..aa478594ec9 100644 --- a/arch/x86/include/asm/me_common.h +++ b/arch/x86/include/asm/me_common.h @@ -13,6 +13,7 @@ #define __ASM_ME_COMMON_H #include +#include #include #include diff --git a/arch/x86/include/asm/mp.h b/arch/x86/include/asm/mp.h index f4c4d6c257c..7c08f7a1d5c 100644 --- a/arch/x86/include/asm/mp.h +++ b/arch/x86/include/asm/mp.h @@ -11,6 +11,7 @@ #include #include #include +#include struct udevice; diff --git a/arch/x86/lib/acpi.c b/arch/x86/lib/acpi.c index 155fffabf08..a73a2539ad3 100644 --- a/arch/x86/lib/acpi.c +++ b/arch/x86/lib/acpi.c @@ -3,7 +3,6 @@ * Copyright (C) 2018, Bin Meng */ -#include #include #include #include diff --git a/arch/x86/lib/acpi_nhlt.c b/arch/x86/lib/acpi_nhlt.c index 08e13fdea67..880ef31df7d 100644 --- a/arch/x86/lib/acpi_nhlt.c +++ b/arch/x86/lib/acpi_nhlt.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY LOGC_ACPI -#include #include #include #include diff --git a/arch/x86/lib/acpi_s3.c b/arch/x86/lib/acpi_s3.c index 2c70acbe7b0..3a1e3318a15 100644 --- a/arch/x86/lib/acpi_s3.c +++ b/arch/x86/lib/acpi_s3.c @@ -3,7 +3,6 @@ * Copyright (C) 2017, Bin Meng */ -#include #include #include #include diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index a5683132b01..a42a7e6bbd6 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY LOGC_ACPI -#include #include #include #include diff --git a/arch/x86/lib/acpigen.c b/arch/x86/lib/acpigen.c index ea2ec2a9083..b486f8fb37d 100644 --- a/arch/x86/lib/acpigen.c +++ b/arch/x86/lib/acpigen.c @@ -3,7 +3,6 @@ * Copyright (C) 2020 Google LLC */ -#include #include #include #include diff --git a/arch/x86/lib/asm-offsets.c b/arch/x86/lib/asm-offsets.c index 8df67db65c3..7b2905dda56 100644 --- a/arch/x86/lib/asm-offsets.c +++ b/arch/x86/lib/asm-offsets.c @@ -11,7 +11,6 @@ * #defines from the assembly-language output. */ -#include #include #include diff --git a/arch/x86/lib/bdinfo.c b/arch/x86/lib/bdinfo.c index 124058442c5..165e8ab944f 100644 --- a/arch/x86/lib/bdinfo.c +++ b/arch/x86/lib/bdinfo.c @@ -5,7 +5,6 @@ * Copyright 2021 Google LLC */ -#include #include #include #include diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c index f146bbd5422..03f7360032c 100644 --- a/arch/x86/lib/bios.c +++ b/arch/x86/lib/bios.c @@ -5,7 +5,6 @@ * Copyright (C) 2007 Advanced Micro Devices, Inc. * Copyright (C) 2009-2010 coresystems GmbH */ -#include #include #include #include diff --git a/arch/x86/lib/bios_interrupts.c b/arch/x86/lib/bios_interrupts.c index d6b4da7e250..b2cf1527b1c 100644 --- a/arch/x86/lib/bios_interrupts.c +++ b/arch/x86/lib/bios_interrupts.c @@ -7,7 +7,6 @@ * Copyright (C) 2007-2009 coresystems GmbH */ -#include #include #include #include "bios_emul.h" diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index 050c420e86b..2c889bcd33c 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -7,7 +7,6 @@ * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) */ -#include #include #include #include diff --git a/arch/x86/lib/cmd_boot.c b/arch/x86/lib/cmd_boot.c index 4facbe5f32f..0444a5f89d3 100644 --- a/arch/x86/lib/cmd_boot.c +++ b/arch/x86/lib/cmd_boot.c @@ -14,7 +14,6 @@ * Marius Groeger */ -#include #include #include #include diff --git a/arch/x86/lib/coreboot/cb_support.c b/arch/x86/lib/coreboot/cb_support.c index ebb45cdfb5b..b4d5fa4af32 100644 --- a/arch/x86/lib/coreboot/cb_support.c +++ b/arch/x86/lib/coreboot/cb_support.c @@ -5,9 +5,9 @@ * Copyright 2021 Google LLC */ -#include #include #include +#include unsigned int cb_install_e820_map(unsigned int max_entries, struct e820_entry *entries) diff --git a/arch/x86/lib/coreboot/cb_sysinfo.c b/arch/x86/lib/coreboot/cb_sysinfo.c index f7fd9ea5bcb..ec997fa49cf 100644 --- a/arch/x86/lib/coreboot/cb_sysinfo.c +++ b/arch/x86/lib/coreboot/cb_sysinfo.c @@ -6,12 +6,12 @@ * Copyright (C) 2009 coresystems GmbH */ -#include #include #include #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/lib/coreboot_table.c b/arch/x86/lib/coreboot_table.c index 05519d851a9..33fce5d0a5e 100644 --- a/arch/x86/lib/coreboot_table.c +++ b/arch/x86/lib/coreboot_table.c @@ -3,7 +3,6 @@ * Copyright (C) 2016, Bin Meng */ -#include #include #include #include diff --git a/arch/x86/lib/div64.c b/arch/x86/lib/div64.c index 2bea205f60f..57da889ef49 100644 --- a/arch/x86/lib/div64.c +++ b/arch/x86/lib/div64.c @@ -6,7 +6,7 @@ * Copyright 2014 Google Inc. */ -#include +#include union overlay64 { u64 longw; diff --git a/arch/x86/lib/e820.c b/arch/x86/lib/e820.c index 12fcff12380..122b4f7ca01 100644 --- a/arch/x86/lib/e820.c +++ b/arch/x86/lib/e820.c @@ -3,7 +3,6 @@ * Copyright (C) 2015, Bin Meng */ -#include #include #include #include diff --git a/arch/x86/lib/early_cmos.c b/arch/x86/lib/early_cmos.c index f7b3bb2a8e1..5635d08718f 100644 --- a/arch/x86/lib/early_cmos.c +++ b/arch/x86/lib/early_cmos.c @@ -10,7 +10,6 @@ * uclass write ops, that data is stored in little-endian mode. */ -#include #include #include diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index 8f2977a8070..c47e6ca4738 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -3,7 +3,6 @@ * Copyright (C) 2014, Bin Meng */ -#include #include #include #include diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index cc889a688d8..730721dc176 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -3,7 +3,6 @@ * Copyright (C) 2014, Bin Meng */ -#include #include #include #include diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c index 09d5da8c841..5f7701265a9 100644 --- a/arch/x86/lib/fsp/fsp_graphics.c +++ b/arch/x86/lib/fsp/fsp_graphics.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_VIDEO -#include #include #include #include diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c index fd4d98ef627..19f9f65b2e4 100644 --- a/arch/x86/lib/fsp/fsp_support.c +++ b/arch/x86/lib/fsp/fsp_support.c @@ -4,7 +4,6 @@ * Copyright (C) 2014, Bin Meng */ -#include #include #include #include diff --git a/arch/x86/lib/fsp1/fsp_common.c b/arch/x86/lib/fsp1/fsp_common.c index df18f476756..ebf655a1143 100644 --- a/arch/x86/lib/fsp1/fsp_common.c +++ b/arch/x86/lib/fsp1/fsp_common.c @@ -3,7 +3,6 @@ * Copyright (C) 2014, Bin Meng */ -#include #include #include #include diff --git a/arch/x86/lib/fsp1/fsp_dram.c b/arch/x86/lib/fsp1/fsp_dram.c index eee9ce54b1c..f3a8134a3f2 100644 --- a/arch/x86/lib/fsp1/fsp_dram.c +++ b/arch/x86/lib/fsp1/fsp_dram.c @@ -3,7 +3,6 @@ * Copyright (C) 2014, Bin Meng */ -#include #include #include #include diff --git a/arch/x86/lib/fsp1/fsp_support.c b/arch/x86/lib/fsp1/fsp_support.c index d84c632f140..6e311a12d20 100644 --- a/arch/x86/lib/fsp1/fsp_support.c +++ b/arch/x86/lib/fsp1/fsp_support.c @@ -4,7 +4,6 @@ * Copyright (C) 2014, Bin Meng */ -#include #include #include #include diff --git a/arch/x86/lib/fsp2/fsp_common.c b/arch/x86/lib/fsp2/fsp_common.c index d802a86967d..45a274c0512 100644 --- a/arch/x86/lib/fsp2/fsp_common.c +++ b/arch/x86/lib/fsp2/fsp_common.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include diff --git a/arch/x86/lib/fsp2/fsp_dram.c b/arch/x86/lib/fsp2/fsp_dram.c index a1432239cfc..83c6d7bcc93 100644 --- a/arch/x86/lib/fsp2/fsp_dram.c +++ b/arch/x86/lib/fsp2/fsp_dram.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY LOGC_ARCH -#include #include #include #include diff --git a/arch/x86/lib/fsp2/fsp_init.c b/arch/x86/lib/fsp2/fsp_init.c index aadc08cf3c4..ecbadaae75c 100644 --- a/arch/x86/lib/fsp2/fsp_init.c +++ b/arch/x86/lib/fsp2/fsp_init.c @@ -3,7 +3,6 @@ * Copyright 2019 Google LLC */ -#include #include #include #include diff --git a/arch/x86/lib/fsp2/fsp_meminit.c b/arch/x86/lib/fsp2/fsp_meminit.c index 022e2cb64e5..f4817830cc2 100644 --- a/arch/x86/lib/fsp2/fsp_meminit.c +++ b/arch/x86/lib/fsp2/fsp_meminit.c @@ -6,7 +6,6 @@ * Mostly taken from coreboot fsp2_0/memory_init.c */ -#include #include #include #include diff --git a/arch/x86/lib/fsp2/fsp_silicon_init.c b/arch/x86/lib/fsp2/fsp_silicon_init.c index a96d2b183f6..16d30c25a57 100644 --- a/arch/x86/lib/fsp2/fsp_silicon_init.c +++ b/arch/x86/lib/fsp2/fsp_silicon_init.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_NORTHBRIDGE -#include #include #include #include diff --git a/arch/x86/lib/fsp2/fsp_support.c b/arch/x86/lib/fsp2/fsp_support.c index b2c76582453..808f0eb9d29 100644 --- a/arch/x86/lib/fsp2/fsp_support.c +++ b/arch/x86/lib/fsp2/fsp_support.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/arch/x86/lib/hob.c b/arch/x86/lib/hob.c index b35248e5fde..46e83aa395a 100644 --- a/arch/x86/lib/hob.c +++ b/arch/x86/lib/hob.c @@ -4,7 +4,6 @@ * Copyright (C) 2014, Bin Meng */ -#include #include /** diff --git a/arch/x86/lib/i8254.c b/arch/x86/lib/i8254.c index a8d1db188ec..8a590c6191f 100644 --- a/arch/x86/lib/i8254.c +++ b/arch/x86/lib/i8254.c @@ -4,10 +4,10 @@ * Daniel Engström, Omicron Ceti AB, */ -#include #include #include #include +#include #define TIMER1_VALUE 18 /* 15.6us */ #define BEEP_FREQUENCY_HZ 440 diff --git a/arch/x86/lib/i8259.c b/arch/x86/lib/i8259.c index a0e3c092573..465ff70146f 100644 --- a/arch/x86/lib/i8259.c +++ b/arch/x86/lib/i8259.c @@ -13,7 +13,6 @@ * Programmable Interrupt Controllers. */ -#include #include #include #include diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index bf0c921577d..bd0efde00c1 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -4,11 +4,11 @@ * Graeme Russ, */ -#include #include #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/lib/interrupts.c b/arch/x86/lib/interrupts.c index ff52959ed28..f96b2bfd70e 100644 --- a/arch/x86/lib/interrupts.c +++ b/arch/x86/lib/interrupts.c @@ -29,7 +29,6 @@ * Daniel Engström */ -#include #include #include #include diff --git a/arch/x86/lib/lpc-uclass.c b/arch/x86/lib/lpc-uclass.c index 67b931d3b28..4f89db4e538 100644 --- a/arch/x86/lib/lpc-uclass.c +++ b/arch/x86/lib/lpc-uclass.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include UCLASS_DRIVER(lpc) = { diff --git a/arch/x86/lib/mpspec.c b/arch/x86/lib/mpspec.c index 8e97d9ff36d..5abd9288c2a 100644 --- a/arch/x86/lib/mpspec.c +++ b/arch/x86/lib/mpspec.c @@ -5,7 +5,6 @@ * Adapted from coreboot src/arch/x86/boot/mpspec.c */ -#include #include #include #include diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c index 6494b8d2634..970704a8dd6 100644 --- a/arch/x86/lib/mrccache.c +++ b/arch/x86/lib/mrccache.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_RAM -#include #include #include #include diff --git a/arch/x86/lib/northbridge-uclass.c b/arch/x86/lib/northbridge-uclass.c index 38388872484..1d1780535a2 100644 --- a/arch/x86/lib/northbridge-uclass.c +++ b/arch/x86/lib/northbridge-uclass.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include diff --git a/arch/x86/lib/physmem.c b/arch/x86/lib/physmem.c index 382f768149f..48cd1073c15 100644 --- a/arch/x86/lib/physmem.c +++ b/arch/x86/lib/physmem.c @@ -8,7 +8,6 @@ * Software Foundation. */ -#include #include #include #include diff --git a/arch/x86/lib/pinctrl_ich6.c b/arch/x86/lib/pinctrl_ich6.c index c93f245845d..d4f71c562f8 100644 --- a/arch/x86/lib/pinctrl_ich6.c +++ b/arch/x86/lib/pinctrl_ich6.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Google, Inc */ -#include #include #include #include diff --git a/arch/x86/lib/pirq_routing.c b/arch/x86/lib/pirq_routing.c index caeaec9287f..5178940901c 100644 --- a/arch/x86/lib/pirq_routing.c +++ b/arch/x86/lib/pirq_routing.c @@ -5,7 +5,6 @@ * Part of this file is ported from coreboot src/arch/x86/boot/pirq_routing.c */ -#include #include #include #include diff --git a/arch/x86/lib/pmu.c b/arch/x86/lib/pmu.c index 083aec8d8dd..2127257cd43 100644 --- a/arch/x86/lib/pmu.c +++ b/arch/x86/lib/pmu.c @@ -2,7 +2,6 @@ /* * Copyright (c) 2017 Intel Corporation */ -#include #include #include #include diff --git a/arch/x86/lib/ramtest.c b/arch/x86/lib/ramtest.c index 03385396325..16cd6e49437 100644 --- a/arch/x86/lib/ramtest.c +++ b/arch/x86/lib/ramtest.c @@ -5,9 +5,9 @@ * From Coreboot src/lib/ramtest.c */ -#include #include #include +#include static void write_phys(unsigned long addr, u32 value) { diff --git a/arch/x86/lib/reloc_ia32_efi.c b/arch/x86/lib/reloc_ia32_efi.c index d56cd50bd93..17ab54dc246 100644 --- a/arch/x86/lib/reloc_ia32_efi.c +++ b/arch/x86/lib/reloc_ia32_efi.c @@ -7,7 +7,6 @@ * All rights reserved. */ -#include #include #include diff --git a/arch/x86/lib/reloc_x86_64_efi.c b/arch/x86/lib/reloc_x86_64_efi.c index 2694de71104..c7a21d9393d 100644 --- a/arch/x86/lib/reloc_x86_64_efi.c +++ b/arch/x86/lib/reloc_x86_64_efi.c @@ -9,7 +9,6 @@ * All rights reserved. */ -#include #include #include diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c index da819b9bdd2..9ce56062d24 100644 --- a/arch/x86/lib/relocate.c +++ b/arch/x86/lib/relocate.c @@ -14,7 +14,6 @@ * Marius Groeger */ -#include #include #include #include diff --git a/arch/x86/lib/scu.c b/arch/x86/lib/scu.c index 90ef239bcd3..02fed601fb6 100644 --- a/arch/x86/lib/scu.c +++ b/arch/x86/lib/scu.c @@ -9,7 +9,6 @@ * * This driver enables IPC channel to SCU. */ -#include #include #include #include diff --git a/arch/x86/lib/sfi.c b/arch/x86/lib/sfi.c index 85e963b634b..04d97327a4d 100644 --- a/arch/x86/lib/sfi.c +++ b/arch/x86/lib/sfi.c @@ -12,7 +12,6 @@ * See https://simplefirmware.org/ for details */ -#include #include #include #include diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index c15f11f8cdf..f761fbc8bc3 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY LOGC_BOOT -#include #include #include #include @@ -29,6 +28,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index 1095dc92c5a..45a70e92763 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY LOGC_ACPI -#include #include #include #include diff --git a/arch/x86/lib/tpl.c b/arch/x86/lib/tpl.c index 273e9c8e1ca..7c03dea0711 100644 --- a/arch/x86/lib/tpl.c +++ b/arch/x86/lib/tpl.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY LOGC_BOOT -#include #include #include #include diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index d7403876c13..73a21bc8f03 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -14,7 +14,6 @@ #define LOG_CATEGORY LOGC_BOOT -#include #include #include #include diff --git a/arch/xtensa/cpu/cpu.c b/arch/xtensa/cpu/cpu.c index 98d9753b7e3..abcd8f7984f 100644 --- a/arch/xtensa/cpu/cpu.c +++ b/arch/xtensa/cpu/cpu.c @@ -8,7 +8,7 @@ * CPU specific code */ -#include +#include #include #include #include diff --git a/arch/xtensa/cpu/exceptions.c b/arch/xtensa/cpu/exceptions.c index cf9af4326a2..206767094e9 100644 --- a/arch/xtensa/cpu/exceptions.c +++ b/arch/xtensa/cpu/exceptions.c @@ -10,12 +10,12 @@ * (Note that alloca is a special case and handled in start.S) */ -#include #include #include #include #include #include +#include typedef void (*handler_t)(struct pt_regs *); diff --git a/arch/xtensa/include/asm/global_data.h b/arch/xtensa/include/asm/global_data.h index 1157978ab68..40c129db4ac 100644 --- a/arch/xtensa/include/asm/global_data.h +++ b/arch/xtensa/include/asm/global_data.h @@ -6,6 +6,8 @@ #ifndef _XTENSA_GBL_DATA_H #define _XTENSA_GBL_DATA_H +#include + /* Architecture-specific global data */ struct arch_global_data { diff --git a/arch/xtensa/lib/bootm.c b/arch/xtensa/lib/bootm.c index 9780d46e9b8..1de06b7fb53 100644 --- a/arch/xtensa/lib/bootm.c +++ b/arch/xtensa/lib/bootm.c @@ -4,7 +4,6 @@ * (C) Copyright 2014 Cadence Design Systems Inc. */ -#include #include #include #include diff --git a/arch/xtensa/lib/cache.c b/arch/xtensa/lib/cache.c index 4e0c0acc3bb..e6a7f6827fc 100644 --- a/arch/xtensa/lib/cache.c +++ b/arch/xtensa/lib/cache.c @@ -4,7 +4,6 @@ * (C) Copyright 2014 - 2016 Cadence Design Systems Inc. */ -#include #include #include diff --git a/arch/xtensa/lib/time.c b/arch/xtensa/lib/time.c index 1c927d2a6a3..c6739584bbf 100644 --- a/arch/xtensa/lib/time.c +++ b/arch/xtensa/lib/time.c @@ -3,7 +3,6 @@ * (C) Copyright 2008 - 2013 Tensilica Inc. */ -#include #include #include #include diff --git a/board/BuR/brppt1/board.c b/board/BuR/brppt1/board.c index 36945bbdccf..192a2fa6327 100644 --- a/board/BuR/brppt1/board.c +++ b/board/BuR/brppt1/board.c @@ -9,7 +9,7 @@ * */ -#include +#include #include #include #include diff --git a/board/BuR/brppt1/mux.c b/board/BuR/brppt1/mux.c index 5d2c7a201ea..8932b9ab3b1 100644 --- a/board/BuR/brppt1/mux.c +++ b/board/BuR/brppt1/mux.c @@ -8,7 +8,6 @@ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com */ -#include #include #include #include diff --git a/board/BuR/brppt2/board.c b/board/BuR/brppt2/board.c index ee006f0196c..105fac8912d 100644 --- a/board/BuR/brppt2/board.c +++ b/board/BuR/brppt2/board.c @@ -6,7 +6,6 @@ * B&R Industrial Automation GmbH - http://www.br-automation.com/ * */ -#include #include #include #include diff --git a/board/BuR/brsmarc1/board.c b/board/BuR/brsmarc1/board.c index 738a5d2ff94..2d3f593d0ab 100644 --- a/board/BuR/brsmarc1/board.c +++ b/board/BuR/brsmarc1/board.c @@ -8,7 +8,6 @@ * B&R Industrial Automation GmbH - http://www.br-automation.com * */ -#include #include #include #include diff --git a/board/BuR/brsmarc1/mux.c b/board/BuR/brsmarc1/mux.c index 33c214d6b2a..b59d64f93ef 100644 --- a/board/BuR/brsmarc1/mux.c +++ b/board/BuR/brsmarc1/mux.c @@ -9,7 +9,6 @@ * */ -#include #include #include #include diff --git a/board/BuR/brxre1/board.c b/board/BuR/brxre1/board.c index a909104df4a..b9b595cb156 100644 --- a/board/BuR/brxre1/board.c +++ b/board/BuR/brxre1/board.c @@ -8,7 +8,6 @@ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com * */ -#include #include #include #include diff --git a/board/BuR/brxre1/mux.c b/board/BuR/brxre1/mux.c index 6c5ad891ba9..e2e8ec57678 100644 --- a/board/BuR/brxre1/mux.c +++ b/board/BuR/brxre1/mux.c @@ -8,7 +8,6 @@ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com */ -#include #include #include #include diff --git a/board/BuR/common/br_resetc.c b/board/BuR/common/br_resetc.c index 32f32b65e9d..f5d09fef3d3 100644 --- a/board/BuR/common/br_resetc.c +++ b/board/BuR/common/br_resetc.c @@ -5,7 +5,6 @@ * Copyright (C) 2019 Hannes Schmelzer * B&R Industrial Automation GmbH - http://www.br-automation.com/ * */ -#include #include #include #include diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index 3c78020bf93..8aff821cfe8 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -10,7 +10,6 @@ */ #include #include -#include #include #include #include diff --git a/board/BuS/eb_cpu5282/eb_cpu5282.c b/board/BuS/eb_cpu5282/eb_cpu5282.c index ea49c7a99c0..cf5610861b5 100644 --- a/board/BuS/eb_cpu5282/eb_cpu5282.c +++ b/board/BuS/eb_cpu5282/eb_cpu5282.c @@ -7,7 +7,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include "asm/m5282.h" diff --git a/board/CZ.NIC/turris_mox/mox_sp.c b/board/CZ.NIC/turris_mox/mox_sp.c index 11d87564717..1591b40deee 100644 --- a/board/CZ.NIC/turris_mox/mox_sp.c +++ b/board/CZ.NIC/turris_mox/mox_sp.c @@ -3,7 +3,7 @@ * Copyright (C) 2018 Marek Behún */ -#include +#include #include #include #include diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index 00114e6d915..e4ed7f25810 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -3,7 +3,7 @@ * Copyright (C) 2018 Marek Behún */ -#include +#include #include #include #include diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index 3b7a71bdad2..4ee1a394b02 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -7,7 +7,7 @@ * Marvell/db-88f6820-gp by Stefan Roese */ -#include +#include #include #include #include diff --git a/board/LaCie/common/common.c b/board/LaCie/common/common.c index 52880a16fad..e8a7830fc05 100644 --- a/board/LaCie/common/common.c +++ b/board/LaCie/common/common.c @@ -3,7 +3,6 @@ * Copyright (C) 2011 Simon Guinot */ -#include #include #include diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c index 91709134000..083d91b696a 100644 --- a/board/LaCie/net2big_v2/net2big_v2.c +++ b/board/LaCie/net2big_v2/net2big_v2.c @@ -8,7 +8,7 @@ * Written-by: Prafulla Wadaskar */ -#include +#include #include #include #include diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c index 22bb008745e..3a2fdb5c154 100644 --- a/board/LaCie/netspace_v2/netspace_v2.c +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -8,7 +8,6 @@ * Written-by: Prafulla Wadaskar */ -#include #include #include #include diff --git a/board/Marvell/db-88f6720/db-88f6720.c b/board/Marvell/db-88f6720/db-88f6720.c index 26c30647fbb..920421366f1 100644 --- a/board/Marvell/db-88f6720/db-88f6720.c +++ b/board/Marvell/db-88f6720/db-88f6720.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Stefan Roese */ -#include #include #include #include diff --git a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c index 122c63d11f9..0f92cc385bc 100644 --- a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c +++ b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c @@ -3,7 +3,7 @@ * Copyright (C) 2015 Stefan Roese */ -#include +#include #include #include #include diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c index 1edc1cb6515..8f8b2720107 100644 --- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c +++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c @@ -3,7 +3,7 @@ * Copyright (C) 2015 Stefan Roese */ -#include +#include #include #include #include diff --git a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c index 9e1fdecfca4..6bca1f91a0a 100644 --- a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c +++ b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c @@ -3,7 +3,6 @@ * Copyright (C) 2014 Stefan Roese */ -#include #include #include #include diff --git a/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c b/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c index 0abdca1cd21..a7a84798a53 100644 --- a/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c +++ b/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Stefan Roese */ -#include #include #include #include diff --git a/board/Marvell/dreamplug/dreamplug.c b/board/Marvell/dreamplug/dreamplug.c index d15faa1cb7f..38127506131 100644 --- a/board/Marvell/dreamplug/dreamplug.c +++ b/board/Marvell/dreamplug/dreamplug.c @@ -8,7 +8,6 @@ * Written-by: Siddarth Gore */ -#include #include #include #include diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c index ea87ded222e..7c3cea22b93 100644 --- a/board/Marvell/guruplug/guruplug.c +++ b/board/Marvell/guruplug/guruplug.c @@ -5,7 +5,6 @@ * Written-by: Siddarth Gore */ -#include #include #include #include diff --git a/board/Marvell/mvebu_alleycat-5/board.c b/board/Marvell/mvebu_alleycat-5/board.c index 0c4f8e03b85..c1b7cc3b613 100644 --- a/board/Marvell/mvebu_alleycat-5/board.c +++ b/board/Marvell/mvebu_alleycat-5/board.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ -#include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c index 1685b12b847..df3fb6d2164 100644 --- a/board/Marvell/mvebu_armada-37xx/board.c +++ b/board/Marvell/mvebu_armada-37xx/board.c @@ -3,7 +3,7 @@ * Copyright (C) 2016 Stefan Roese */ -#include +#include #include #include #include diff --git a/board/Marvell/mvebu_armada-8k/board.c b/board/Marvell/mvebu_armada-8k/board.c index a8899af6e5a..6d704211742 100644 --- a/board/Marvell/mvebu_armada-8k/board.c +++ b/board/Marvell/mvebu_armada-8k/board.c @@ -3,7 +3,7 @@ * Copyright (C) 2016 Stefan Roese */ -#include +#include #include #include #include diff --git a/board/Marvell/octeontx2/soc-utils.c b/board/Marvell/octeontx2/soc-utils.c index 43a19a90717..64eb95f3b40 100644 --- a/board/Marvell/octeontx2/soc-utils.c +++ b/board/Marvell/octeontx2/soc-utils.c @@ -5,7 +5,6 @@ * https://spdx.org/licenses */ -#include #include #include #include diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c index 581e2e084d6..dda56a582b3 100644 --- a/board/Marvell/openrd/openrd.c +++ b/board/Marvell/openrd/openrd.c @@ -10,7 +10,6 @@ * Written-by: Prafulla Wadaskar */ -#include #include #include #include diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c index 26ee39ef77f..23e761d5feb 100644 --- a/board/Marvell/sheevaplug/sheevaplug.c +++ b/board/Marvell/sheevaplug/sheevaplug.c @@ -6,7 +6,6 @@ * Written-by: Prafulla Wadaskar */ -#include #include #include #include diff --git a/board/Seagate/dockstar/dockstar.c b/board/Seagate/dockstar/dockstar.c index d72e3ef24ee..e6ec00a9c6c 100644 --- a/board/Seagate/dockstar/dockstar.c +++ b/board/Seagate/dockstar/dockstar.c @@ -9,7 +9,6 @@ * Marvell Semiconductor */ -#include #include #include #include diff --git a/board/Seagate/goflexhome/goflexhome.c b/board/Seagate/goflexhome/goflexhome.c index caea89c10e0..b2d0ad8c3f2 100644 --- a/board/Seagate/goflexhome/goflexhome.c +++ b/board/Seagate/goflexhome/goflexhome.c @@ -12,7 +12,6 @@ * Marvell Semiconductor */ -#include #include #include #include diff --git a/board/Seagate/nas220/nas220.c b/board/Seagate/nas220/nas220.c index cd2bbdad1cd..fa7553250d1 100644 --- a/board/Seagate/nas220/nas220.c +++ b/board/Seagate/nas220/nas220.c @@ -8,7 +8,6 @@ * Marvell Semiconductor */ -#include #include #include #include diff --git a/board/Synology/ds109/ds109.c b/board/Synology/ds109/ds109.c index 5c3f46e23f4..4f397578182 100644 --- a/board/Synology/ds109/ds109.c +++ b/board/Synology/ds109/ds109.c @@ -5,7 +5,7 @@ * Luka Perkov */ -#include +#include #include #include #include diff --git a/board/Synology/ds414/cmd_syno.c b/board/Synology/ds414/cmd_syno.c index a62658a2eb6..29ea35e5e91 100644 --- a/board/Synology/ds414/cmd_syno.c +++ b/board/Synology/ds414/cmd_syno.c @@ -5,7 +5,6 @@ * Copyright (C) 2015 Phil Sutter */ -#include #include #include #include diff --git a/board/Synology/ds414/ds414.c b/board/Synology/ds414/ds414.c index abe6f9eb5e2..8db810ad3eb 100644 --- a/board/Synology/ds414/ds414.c +++ b/board/Synology/ds414/ds414.c @@ -4,7 +4,6 @@ * Copyright (C) 2015 Phil Sutter */ -#include #include #include #include diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c index d87fe3606f6..070933fb54b 100644 --- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c +++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c @@ -4,7 +4,6 @@ * Copyright 2022 Linaro */ -#include #include #include #include diff --git a/board/advantech/imx8mp_rsb3720a1/spl.c b/board/advantech/imx8mp_rsb3720a1/spl.c index f4257bc993d..1f7c1f25adc 100644 --- a/board/advantech/imx8mp_rsb3720a1/spl.c +++ b/board/advantech/imx8mp_rsb3720a1/spl.c @@ -4,7 +4,7 @@ * Copyright 2022 Linaro */ -#include +#include #include #include #include diff --git a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c index 56b7bdb57c9..50b35db5f6c 100644 --- a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c +++ b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c @@ -4,7 +4,6 @@ * Copyright 2019-2023 Kococonnector GmbH */ -#include #include #include #include diff --git a/board/advantech/imx8qm_dmsse20_a1/spl.c b/board/advantech/imx8qm_dmsse20_a1/spl.c index e8959ede51d..93cf0744002 100644 --- a/board/advantech/imx8qm_dmsse20_a1/spl.c +++ b/board/advantech/imx8qm_dmsse20_a1/spl.c @@ -3,7 +3,7 @@ * Copyright 2017-2018 NXP * Copyright 2019-2023 Kococonnector GmbH */ -#include +#include #include #include #include diff --git a/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c b/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c index 7f766a688bb..3def182f296 100644 --- a/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c +++ b/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c @@ -4,7 +4,6 @@ * Copyright (C) 2019 Oliver Graute */ -#include #include #include #include diff --git a/board/advantech/imx8qm_rom7720_a1/spl.c b/board/advantech/imx8qm_rom7720_a1/spl.c index d32400101fc..5863e335a8b 100644 --- a/board/advantech/imx8qm_rom7720_a1/spl.c +++ b/board/advantech/imx8qm_rom7720_a1/spl.c @@ -2,7 +2,7 @@ /* * Copyright 2017-2018 NXP */ -#include +#include #include #include #include diff --git a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c index 8499fc541fa..9bbd5fd291a 100644 --- a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c +++ b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c @@ -4,7 +4,6 @@ * Copyright (C) 2016 George McCollister */ -#include #include #include diff --git a/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c b/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c index e0a7f3fa89f..5e6d6c6234f 100644 --- a/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c +++ b/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c @@ -4,7 +4,6 @@ * Allied Telesis */ -#include #include #include #include diff --git a/board/alliedtelesis/SBx81LIFXCAT/sbx81lifxcat.c b/board/alliedtelesis/SBx81LIFXCAT/sbx81lifxcat.c index 52b8eba92fc..f30821c1796 100644 --- a/board/alliedtelesis/SBx81LIFXCAT/sbx81lifxcat.c +++ b/board/alliedtelesis/SBx81LIFXCAT/sbx81lifxcat.c @@ -4,7 +4,6 @@ * Allied Telesis */ -#include #include #include #include diff --git a/board/alliedtelesis/common/gpio_hog.c b/board/alliedtelesis/common/gpio_hog.c index 4aecf7e2cef..7da70fb4f7d 100644 --- a/board/alliedtelesis/common/gpio_hog.c +++ b/board/alliedtelesis/common/gpio_hog.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Allied Telesis Labs */ -#include #include #include #include diff --git a/board/alliedtelesis/x240/x240.c b/board/alliedtelesis/x240/x240.c index 0c4f8e03b85..c1b7cc3b613 100644 --- a/board/alliedtelesis/x240/x240.c +++ b/board/alliedtelesis/x240/x240.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ -#include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c index 80ad62c2c66..65e6d48db0a 100644 --- a/board/alliedtelesis/x530/x530.c +++ b/board/alliedtelesis/x530/x530.c @@ -3,7 +3,7 @@ * Copyright (C) 2017 Allied Telesis Labs */ -#include +#include #include #include #include diff --git a/board/amarula/vyasa-rk3288/vyasa-rk3288.c b/board/amarula/vyasa-rk3288/vyasa-rk3288.c index 92e0698c534..b220256c67f 100644 --- a/board/amarula/vyasa-rk3288/vyasa-rk3288.c +++ b/board/amarula/vyasa-rk3288/vyasa-rk3288.c @@ -3,7 +3,6 @@ * Copyright (C) 2017 Amarula Solutions */ -#include #include #ifndef CONFIG_TPL_BUILD diff --git a/board/amlogic/beelink-s922x/beelink-s922x.c b/board/amlogic/beelink-s922x/beelink-s922x.c index c2776310a3d..ccb2f7d1bb1 100644 --- a/board/amlogic/beelink-s922x/beelink-s922x.c +++ b/board/amlogic/beelink-s922x/beelink-s922x.c @@ -4,7 +4,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/board/amlogic/jethub-j100/jethub-j100.c b/board/amlogic/jethub-j100/jethub-j100.c index 010fc0df7d1..b770a1f8c53 100644 --- a/board/amlogic/jethub-j100/jethub-j100.c +++ b/board/amlogic/jethub-j100/jethub-j100.c @@ -4,7 +4,6 @@ * Author: Vyacheslav Bocharov */ -#include #include #include #include diff --git a/board/amlogic/jethub-j80/jethub-j80.c b/board/amlogic/jethub-j80/jethub-j80.c index 0b781666e98..07a08dcd170 100644 --- a/board/amlogic/jethub-j80/jethub-j80.c +++ b/board/amlogic/jethub-j80/jethub-j80.c @@ -6,7 +6,6 @@ * */ -#include #include #include #include diff --git a/board/amlogic/odroid-go-ultra/odroid-go-ultra.c b/board/amlogic/odroid-go-ultra/odroid-go-ultra.c index bbd23e20fcd..8f3f2045d74 100644 --- a/board/amlogic/odroid-go-ultra/odroid-go-ultra.c +++ b/board/amlogic/odroid-go-ultra/odroid-go-ultra.c @@ -3,7 +3,7 @@ * Copyright (C) 2023 Neil Armstrong */ -#include +#include #include #include diff --git a/board/amlogic/odroid-n2/odroid-n2.c b/board/amlogic/odroid-n2/odroid-n2.c index a4bcc62174a..ae953d0e4ba 100644 --- a/board/amlogic/odroid-n2/odroid-n2.c +++ b/board/amlogic/odroid-n2/odroid-n2.c @@ -4,7 +4,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/board/amlogic/p200/p200.c b/board/amlogic/p200/p200.c index 754242e4a9f..3bede46b324 100644 --- a/board/amlogic/p200/p200.c +++ b/board/amlogic/p200/p200.c @@ -3,7 +3,6 @@ * (C) Copyright 2016 Beniamino Galvani */ -#include #include #include #include diff --git a/board/amlogic/p201/p201.c b/board/amlogic/p201/p201.c index 769e2735d27..d44ebae07dd 100644 --- a/board/amlogic/p201/p201.c +++ b/board/amlogic/p201/p201.c @@ -3,7 +3,6 @@ * (C) Copyright 2016 Beniamino Galvani */ -#include #include #include #include diff --git a/board/amlogic/p212/p212.c b/board/amlogic/p212/p212.c index f6e60ae3af1..ae9834c0bf8 100644 --- a/board/amlogic/p212/p212.c +++ b/board/amlogic/p212/p212.c @@ -4,7 +4,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/board/amlogic/q200/q200.c b/board/amlogic/q200/q200.c index 47f1566a9d3..0c0afccb38c 100644 --- a/board/amlogic/q200/q200.c +++ b/board/amlogic/q200/q200.c @@ -4,7 +4,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/board/amlogic/s400/s400.c b/board/amlogic/s400/s400.c index 06a9044fd80..96244c9ccb1 100644 --- a/board/amlogic/s400/s400.c +++ b/board/amlogic/s400/s400.c @@ -4,7 +4,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/board/amlogic/sei510/sei510.c b/board/amlogic/sei510/sei510.c index bb188c21f75..1a978d1290a 100644 --- a/board/amlogic/sei510/sei510.c +++ b/board/amlogic/sei510/sei510.c @@ -4,7 +4,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/board/amlogic/sei610/sei610.c b/board/amlogic/sei610/sei610.c index 6490bac9eb5..8a096b15bfb 100644 --- a/board/amlogic/sei610/sei610.c +++ b/board/amlogic/sei610/sei610.c @@ -4,7 +4,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/board/amlogic/u200/u200.c b/board/amlogic/u200/u200.c index 06a9044fd80..96244c9ccb1 100644 --- a/board/amlogic/u200/u200.c +++ b/board/amlogic/u200/u200.c @@ -4,7 +4,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/board/amlogic/vim3/vim3.c b/board/amlogic/vim3/vim3.c index a4850364f41..bbc2d826e05 100644 --- a/board/amlogic/vim3/vim3.c +++ b/board/amlogic/vim3/vim3.c @@ -4,7 +4,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/board/amlogic/w400/w400.c b/board/amlogic/w400/w400.c index 4199198496b..b84366aaeb1 100644 --- a/board/amlogic/w400/w400.c +++ b/board/amlogic/w400/w400.c @@ -4,7 +4,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 17f37badd74..8cfac9fbb34 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -9,7 +9,6 @@ * Author: Fabio Estevam */ -#include #include #include #include diff --git a/board/armadeus/opos6uldev/board.c b/board/armadeus/opos6uldev/board.c index 365fdca1b76..5b25545cdb8 100644 --- a/board/armadeus/opos6uldev/board.c +++ b/board/armadeus/opos6uldev/board.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Armadeus Systems */ -#include #include #include #include diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c index 01c80aaf9d7..3ad77f51949 100644 --- a/board/armltd/corstone1000/corstone1000.c +++ b/board/armltd/corstone1000/corstone1000.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index ad02cf16da5..eaf87e3bfe3 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -16,7 +16,7 @@ * Philippe Robin, */ -#include +#include #include #include #include diff --git a/board/armltd/integrator/timer.c b/board/armltd/integrator/timer.c index 9db5135a8ff..f4101b649e3 100644 --- a/board/armltd/integrator/timer.c +++ b/board/armltd/integrator/timer.c @@ -16,7 +16,7 @@ * Philippe Robin, */ -#include +#include #include #include #include diff --git a/board/armltd/total_compute/total_compute.c b/board/armltd/total_compute/total_compute.c index 53941b5f5f2..e1b4f49d044 100644 --- a/board/armltd/total_compute/total_compute.c +++ b/board/armltd/total_compute/total_compute.c @@ -4,7 +4,7 @@ * Usama Arif */ -#include +#include #include #include #include diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c index 763131c217e..6c374e25e32 100644 --- a/board/armltd/vexpress/vexpress_common.c +++ b/board/armltd/vexpress/vexpress_common.c @@ -15,7 +15,7 @@ * ARM Ltd. * Philippe Robin, */ -#include +#include #include #include #include diff --git a/board/armltd/vexpress64/pcie.c b/board/armltd/vexpress64/pcie.c index e553da86e0e..1045c905f73 100644 --- a/board/armltd/vexpress64/pcie.c +++ b/board/armltd/vexpress64/pcie.c @@ -5,7 +5,6 @@ * Author: Liviu Dudau */ -#include #include #include #include diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index ee65a596838..0119f54f0df 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -4,7 +4,7 @@ * David Feng * Sharma Bhupesh */ -#include +#include #include #include #include diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c index f85737432b3..6e505c630d1 100644 --- a/board/astro/mcf5373l/fpga.c +++ b/board/astro/mcf5373l/fpga.c @@ -13,7 +13,6 @@ /* Altera/Xilinx FPGA configuration support for the ASTRO "URMEL" board */ -#include #include #include #include diff --git a/board/astro/mcf5373l/mcf5373l.c b/board/astro/mcf5373l/mcf5373l.c index 43563c41279..43fcbc65513 100644 --- a/board/astro/mcf5373l/mcf5373l.c +++ b/board/astro/mcf5373l/mcf5373l.c @@ -5,9 +5,10 @@ * modified by Wolfgang Wegner for ASTRO 5373l */ -#include +#include #include #include +#include #include #include #include diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index b8e02f45903..48aec652c4a 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -5,7 +5,7 @@ * Lead Tech Design */ -#include +#include #include #include #include diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index eab3a130819..5d7a18379fa 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -5,7 +5,7 @@ * Lead Tech Design */ -#include +#include #include #include #include diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 15f20b62f67..2b0b01798ea 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -5,7 +5,7 @@ * Lead Tech Design */ -#include +#include #include #include #include diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index f53c1cf612d..3bd94d0889d 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -5,7 +5,7 @@ * Lead Tech Design */ -#include +#include #include #include #include diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index a3e294c88fc..afc0c0520e1 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -4,7 +4,7 @@ * Josh Wu */ -#include +#include #include #include #include diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index 11725f778b7..214e917381e 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -5,7 +5,7 @@ * Lead Tech Design */ -#include +#include #include #include #include diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index ab666b6be34..e5688c6cf13 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -3,7 +3,7 @@ * Copyright (C) 2012 Atmel Corporation */ -#include +#include #include #include #include diff --git a/board/atmel/common/board.c b/board/atmel/common/board.c index c93c0e52e30..55afd43d4f3 100644 --- a/board/atmel/common/board.c +++ b/board/atmel/common/board.c @@ -4,7 +4,6 @@ * Wenyou Yang */ -#include #include #include #include diff --git a/board/atmel/common/mac-spi-nor.c b/board/atmel/common/mac-spi-nor.c index ced27b65e63..628f7958129 100644 --- a/board/atmel/common/mac-spi-nor.c +++ b/board/atmel/common/mac-spi-nor.c @@ -5,7 +5,6 @@ * Author: Tudor Ambarus */ -#include #include #include #include diff --git a/board/atmel/common/mac_eeprom.c b/board/atmel/common/mac_eeprom.c index 4606008c697..97edb7a549d 100644 --- a/board/atmel/common/mac_eeprom.c +++ b/board/atmel/common/mac_eeprom.c @@ -4,9 +4,7 @@ * Wenyou Yang */ -#include #include -#include #include #include #include diff --git a/board/atmel/common/video_display.c b/board/atmel/common/video_display.c index a5049f4aad4..77188820581 100644 --- a/board/atmel/common/video_display.c +++ b/board/atmel/common/video_display.c @@ -4,7 +4,6 @@ * Wenyou Yang */ -#include #include #include #include diff --git a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c index f53d359404e..e75043ec00f 100644 --- a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c +++ b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c @@ -5,7 +5,6 @@ * Author: Durai Manickam KR */ -#include #include #include #include diff --git a/board/atmel/sam9x60ek/sam9x60ek.c b/board/atmel/sam9x60ek/sam9x60ek.c index 3fbfca4acc9..2e5073f02b3 100644 --- a/board/atmel/sam9x60ek/sam9x60ek.c +++ b/board/atmel/sam9x60ek/sam9x60ek.c @@ -5,7 +5,7 @@ * Author: Sandeep Sheriker M */ -#include +#include #include #include #include diff --git a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c index 329eac7223a..36995a927cf 100644 --- a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c +++ b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c @@ -4,7 +4,6 @@ * Wenyou.Yang */ -#include #include #include #include diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c index 6e41017af17..c775d593e58 100644 --- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c +++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c @@ -5,7 +5,7 @@ * Author: Nicolas Ferre */ -#include +#include #include #include #include diff --git a/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c b/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c index d0679317fb2..8759ff6f01a 100644 --- a/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c +++ b/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c @@ -6,7 +6,6 @@ * */ -#include #include #include #include diff --git a/board/atmel/sama5d2_icp/sama5d2_icp.c b/board/atmel/sama5d2_icp/sama5d2_icp.c index fabe492715a..986da01639f 100644 --- a/board/atmel/sama5d2_icp/sama5d2_icp.c +++ b/board/atmel/sama5d2_icp/sama5d2_icp.c @@ -4,7 +4,7 @@ * Eugen Hristev */ -#include +#include #include #include #include diff --git a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c index 854715ea226..438829df82d 100644 --- a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c +++ b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c @@ -4,7 +4,7 @@ * Wenyou Yang */ -#include +#include #include #include #include diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index aa522075691..c8a8eb49826 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -4,7 +4,6 @@ * Wenyou.Yang */ -#include #include #include #include diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c index ce73a801e50..54cc3c4d900 100644 --- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c +++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c @@ -4,7 +4,7 @@ * Bo Shen */ -#include +#include #include #include #include diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index 660a6b9d583..f2e1242fcb0 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -4,7 +4,7 @@ * Bo Shen */ -#include +#include #include #include #include diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c index 780aba15ab1..09ca16ca88c 100644 --- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -4,7 +4,7 @@ * Bo Shen */ -#include +#include #include #include #include diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c index 2226906a3b3..1f8b85f0614 100644 --- a/board/atmel/sama5d4ek/sama5d4ek.c +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -4,7 +4,7 @@ * Bo Shen */ -#include +#include #include #include #include diff --git a/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c b/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c index 33cd0903d25..b05c9754c96 100644 --- a/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c +++ b/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c @@ -6,7 +6,6 @@ * */ -#include #include #include #include diff --git a/board/atmel/sama7g5ek/sama7g5ek.c b/board/atmel/sama7g5ek/sama7g5ek.c index 295fd079dcf..c07115a2119 100644 --- a/board/atmel/sama7g5ek/sama7g5ek.c +++ b/board/atmel/sama7g5ek/sama7g5ek.c @@ -4,7 +4,7 @@ * Eugen Hristev */ -#include +#include #include #include #include diff --git a/board/avionic-design/common/tamonten-ng.c b/board/avionic-design/common/tamonten-ng.c index 29bde60228f..e35bda81468 100644 --- a/board/avionic-design/common/tamonten-ng.c +++ b/board/avionic-design/common/tamonten-ng.c @@ -4,7 +4,6 @@ * Avionic Design GmbH */ -#include #include #include #include diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c index 988f057a281..4d7477237d4 100644 --- a/board/avionic-design/common/tamonten.c +++ b/board/avionic-design/common/tamonten.c @@ -6,7 +6,6 @@ * Avionic Design GmbH */ -#include #include #include #include diff --git a/board/avionic-design/tec-ng/tec-ng-spl.c b/board/avionic-design/tec-ng/tec-ng-spl.c index 6e544641833..25049452495 100644 --- a/board/avionic-design/tec-ng/tec-ng-spl.c +++ b/board/avionic-design/tec-ng/tec-ng-spl.c @@ -7,7 +7,6 @@ * Svyatoslav Ryhel */ -#include #include #include diff --git a/board/beacon/beacon-rzg2m/beacon-rzg2m.c b/board/beacon/beacon-rzg2m/beacon-rzg2m.c index 99fe1edfb33..099053235de 100644 --- a/board/beacon/beacon-rzg2m/beacon-rzg2m.c +++ b/board/beacon/beacon-rzg2m/beacon-rzg2m.c @@ -3,7 +3,6 @@ * Copyright 2020 Compass Electronics Group, LLC */ -#include #include #include diff --git a/board/beacon/imx8mm/lpddr4_timing.c b/board/beacon/imx8mm/lpddr4_timing.c index 8e48b9d81b7..c1498dd5eaf 100644 --- a/board/beacon/imx8mm/lpddr4_timing.c +++ b/board/beacon/imx8mm/lpddr4_timing.c @@ -4,7 +4,6 @@ */ #include -#include #include #include diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c index 1632238bf5d..12013aa5a4d 100644 --- a/board/beacon/imx8mm/spl.c +++ b/board/beacon/imx8mm/spl.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c index b4d46f11f98..f03841e5a01 100644 --- a/board/beacon/imx8mn/spl.c +++ b/board/beacon/imx8mn/spl.c @@ -3,7 +3,6 @@ * Copyright 2020 Compass Electronics Group, LLC */ -#include #include #include #include diff --git a/board/beacon/imx8mp/imx8mp_beacon.c b/board/beacon/imx8mp/imx8mp_beacon.c index 8963a51fbba..dd74e7c0f75 100644 --- a/board/beacon/imx8mp/imx8mp_beacon.c +++ b/board/beacon/imx8mp/imx8mp_beacon.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* Copyright 2023 Logic PD, Inc dba Beacon EmbeddedWorks */ -#include #include #include #include diff --git a/board/beacon/imx8mp/spl.c b/board/beacon/imx8mp/spl.c index 591e8ca9ab5..30d577f7e0e 100644 --- a/board/beacon/imx8mp/spl.c +++ b/board/beacon/imx8mp/spl.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/board/beagle/beagle/beagle.c b/board/beagle/beagle/beagle.c index 847d596646e..ac2f89cf213 100644 --- a/board/beagle/beagle/beagle.c +++ b/board/beagle/beagle/beagle.c @@ -12,7 +12,7 @@ * Syed Mohammed Khasim * */ -#include +#include #include #include #include diff --git a/board/beagle/beagle/led.c b/board/beagle/beagle/led.c index e21c0169db7..efbd7c1e0e3 100644 --- a/board/beagle/beagle/led.c +++ b/board/beagle/beagle/led.c @@ -3,7 +3,6 @@ * Copyright (c) 2010 Texas Instruments, Inc. * Jason Kridner */ -#include #include #include #include diff --git a/board/beckhoff/mx53cx9020/mx53cx9020.c b/board/beckhoff/mx53cx9020/mx53cx9020.c index e7b131836b6..3a766728a6f 100644 --- a/board/beckhoff/mx53cx9020/mx53cx9020.c +++ b/board/beckhoff/mx53cx9020/mx53cx9020.c @@ -7,7 +7,6 @@ * Copyright (C) 2011 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/board/beckhoff/mx53cx9020/mx53cx9020_video.c b/board/beckhoff/mx53cx9020/mx53cx9020_video.c index bf472902562..fd28a70f4d7 100644 --- a/board/beckhoff/mx53cx9020/mx53cx9020_video.c +++ b/board/beckhoff/mx53cx9020/mx53cx9020_video.c @@ -7,7 +7,6 @@ * Copyright (C) 2012 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/board/bluewater/gurnard/gurnard.c b/board/bluewater/gurnard/gurnard.c index 9b42299b080..3275803226a 100644 --- a/board/bluewater/gurnard/gurnard.c +++ b/board/bluewater/gurnard/gurnard.c @@ -7,7 +7,7 @@ * Author: Ryan Mallon */ -#include +#include #include #include #include diff --git a/board/bosch/acc/acc.c b/board/bosch/acc/acc.c index 65c2f356713..a1a00e7ffc4 100644 --- a/board/bosch/acc/acc.c +++ b/board/bosch/acc/acc.c @@ -5,7 +5,7 @@ * Copyright (c) 2022 DENX Software Engineering GmbH, Philip Oberfichtner */ -#include +#include #include #include #include diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c index ee9e6d632ed..41d7567ad21 100644 --- a/board/bosch/guardian/board.c +++ b/board/bosch/guardian/board.c @@ -8,7 +8,7 @@ * Copyright (C) 2018 Robert Bosch Power Tools GmbH */ -#include +#include #include #include #include diff --git a/board/bosch/guardian/mux.c b/board/bosch/guardian/mux.c index 53850ffb8f7..eab3398c4ae 100644 --- a/board/bosch/guardian/mux.c +++ b/board/bosch/guardian/mux.c @@ -6,7 +6,6 @@ * Copyright (C) 2018 Robert Bosch Power Tools GmbH */ -#include #include #include #include diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c index aebdfd4dfec..ab688745938 100644 --- a/board/bosch/shc/board.c +++ b/board/bosch/shc/board.c @@ -11,7 +11,7 @@ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include +#include #include #include #include diff --git a/board/bosch/shc/mux.c b/board/bosch/shc/mux.c index f19d1866c72..a2a8947a3bd 100644 --- a/board/bosch/shc/mux.c +++ b/board/bosch/shc/mux.c @@ -9,7 +9,6 @@ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ -#include #include #include #include diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 382c01ddf4e..2b0cb2361c4 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -4,7 +4,6 @@ * Copyright (C) 2013, Boundary Devices */ -#include #include #include #include diff --git a/board/broadcom/bcmbca/board.c b/board/broadcom/bcmbca/board.c index bcecb4d7839..a6ced92565f 100644 --- a/board/broadcom/bcmbca/board.c +++ b/board/broadcom/bcmbca/board.c @@ -3,7 +3,6 @@ * (C) Copyright 2022 Broadcom Ltd. */ -#include #include int board_init(void) diff --git a/board/broadcom/bcmns/ns.c b/board/broadcom/bcmns/ns.c index 1249e45af03..45cc62936ce 100644 --- a/board/broadcom/bcmns/ns.c +++ b/board/broadcom/bcmns/ns.c @@ -4,7 +4,6 @@ * Copyright (C) 2023 Linus Walleij */ -#include #include #include #include diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c index 7ae6742c4be..bb2f1e4f62a 100644 --- a/board/broadcom/bcmns3/ns3.c +++ b/board/broadcom/bcmns3/ns3.c @@ -4,8 +4,8 @@ * */ -#include #include +#include #include #include #include diff --git a/board/broadcom/bcmstb/bcmstb.c b/board/broadcom/bcmstb/bcmstb.c index aead6f099e8..bc05aecc446 100644 --- a/board/broadcom/bcmstb/bcmstb.c +++ b/board/broadcom/bcmstb/bcmstb.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include diff --git a/board/bsh/imx6ulz_smm_m2/imx6ulz_smm_m2.c b/board/bsh/imx6ulz_smm_m2/imx6ulz_smm_m2.c index c82eabbfbea..c03e390762a 100644 --- a/board/bsh/imx6ulz_smm_m2/imx6ulz_smm_m2.c +++ b/board/bsh/imx6ulz_smm_m2/imx6ulz_smm_m2.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include diff --git a/board/bsh/imx6ulz_smm_m2/spl.c b/board/bsh/imx6ulz_smm_m2/spl.c index 5b4812e129e..724841b5745 100644 --- a/board/bsh/imx6ulz_smm_m2/spl.c +++ b/board/bsh/imx6ulz_smm_m2/spl.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c b/board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c index 0ebf208be82..c9989687399 100644 --- a/board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c +++ b/board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c @@ -3,7 +3,6 @@ * Copyright 2021 Collabora Ltd. */ -#include #include #include diff --git a/board/bticino/mamoj/mamoj.c b/board/bticino/mamoj/mamoj.c index c9da42b43bf..71497b8ab1e 100644 --- a/board/bticino/mamoj/mamoj.c +++ b/board/bticino/mamoj/mamoj.c @@ -5,7 +5,6 @@ * Copyright (C) 2018 Jagan Teki */ -#include #include #include #include diff --git a/board/bticino/mamoj/spl.c b/board/bticino/mamoj/spl.c index 883b7f4133b..59b7c24ccc9 100644 --- a/board/bticino/mamoj/spl.c +++ b/board/bticino/mamoj/spl.c @@ -5,7 +5,6 @@ * Copyright (C) 2018 Jagan Teki */ -#include #include #include #include diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c index 6a866b5470d..1e501a09813 100644 --- a/board/buffalo/lsxl/lsxl.c +++ b/board/buffalo/lsxl/lsxl.c @@ -7,7 +7,6 @@ * Marvell Semiconductor */ -#include #include #include #include diff --git a/board/cadence/xtfpga/xtfpga.c b/board/cadence/xtfpga/xtfpga.c index 8e4081b4c6d..5110fed3119 100644 --- a/board/cadence/xtfpga/xtfpga.c +++ b/board/cadence/xtfpga/xtfpga.c @@ -4,7 +4,7 @@ * (C) Copyright 2014 - 2016 Cadence Design Systems Inc. */ -#include +#include #include #include #include diff --git a/board/calao/usb_a9263/usb_a9263.c b/board/calao/usb_a9263/usb_a9263.c index 3d31776d484..8e39a157ea3 100644 --- a/board/calao/usb_a9263/usb_a9263.c +++ b/board/calao/usb_a9263/usb_a9263.c @@ -7,7 +7,7 @@ * Mateusz Kulikowski */ -#include +#include #include #include #include diff --git a/board/cavium/thunderx/atf.c b/board/cavium/thunderx/atf.c index 37340fe9700..ce7afb78ed5 100644 --- a/board/cavium/thunderx/atf.c +++ b/board/cavium/thunderx/atf.c @@ -3,8 +3,9 @@ * (C) Copyright 2014, Cavium Inc. **/ -#include +#include #include +#include #include #include #include diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c index ab20825ed36..b1a805c1360 100644 --- a/board/cavium/thunderx/thunderx.c +++ b/board/cavium/thunderx/thunderx.c @@ -3,7 +3,7 @@ * (C) Copyright 2014, Cavium Inc. **/ -#include +#include #include #include #include diff --git a/board/cei/cei-tk1-som/cei-tk1-som.c b/board/cei/cei-tk1-som/cei-tk1-som.c index 95ee7bbfe29..15b200454da 100644 --- a/board/cei/cei-tk1-som/cei-tk1-som.c +++ b/board/cei/cei-tk1-som/cei-tk1-som.c @@ -4,7 +4,7 @@ * NVIDIA Corporation */ -#include +#include #include #include diff --git a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c index e6909b3b1c5..dd7551170d2 100644 --- a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c +++ b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c @@ -3,7 +3,6 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ -#include #include #include diff --git a/board/cloos/imx8mm_phg/imx8mm_phg.c b/board/cloos/imx8mm_phg/imx8mm_phg.c index bc4e984d505..091c9a59a52 100644 --- a/board/cloos/imx8mm_phg/imx8mm_phg.c +++ b/board/cloos/imx8mm_phg/imx8mm_phg.c @@ -3,7 +3,6 @@ * Copyright 2018 NXP */ -#include #include #include #include diff --git a/board/cloos/imx8mm_phg/spl.c b/board/cloos/imx8mm_phg/spl.c index 0c3a0135a86..b8892ed2fcc 100644 --- a/board/cloos/imx8mm_phg/spl.c +++ b/board/cloos/imx8mm_phg/spl.c @@ -3,7 +3,6 @@ * Copyright 2019 NXP */ -#include #include #include #include diff --git a/board/cloudengines/pogo_e02/pogo_e02.c b/board/cloudengines/pogo_e02/pogo_e02.c index 59e1218b411..48eee67129f 100644 --- a/board/cloudengines/pogo_e02/pogo_e02.c +++ b/board/cloudengines/pogo_e02/pogo_e02.c @@ -10,7 +10,6 @@ * Written-by: Prafulla Wadaskar */ -#include #include #include #include diff --git a/board/cloudengines/pogo_v4/pogo_v4.c b/board/cloudengines/pogo_v4/pogo_v4.c index 61ce0d59c77..c8ad563f721 100644 --- a/board/cloudengines/pogo_v4/pogo_v4.c +++ b/board/cloudengines/pogo_v4/pogo_v4.c @@ -11,7 +11,6 @@ * Written-by: Prafulla Wadaskar */ -#include #include #include #include diff --git a/board/cobra5272/cobra5272.c b/board/cobra5272/cobra5272.c index 69a9df94231..774aa82b57f 100644 --- a/board/cobra5272/cobra5272.c +++ b/board/cobra5272/cobra5272.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include diff --git a/board/cobra5272/flash.c b/board/cobra5272/flash.c index 8416af163ad..157b71da85e 100644 --- a/board/cobra5272/flash.c +++ b/board/cobra5272/flash.c @@ -4,13 +4,17 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include #include +#include +#include #include +#include #include +#include #define PHYS_FLASH_1 CFG_SYS_FLASH_BASE #define FLASH_BANK_SIZE 0x200000 diff --git a/board/compulab/cl-som-imx7/cl-som-imx7.c b/board/compulab/cl-som-imx7/cl-som-imx7.c index af19a658b54..7853c4d024a 100644 --- a/board/compulab/cl-som-imx7/cl-som-imx7.c +++ b/board/compulab/cl-som-imx7/cl-som-imx7.c @@ -7,7 +7,7 @@ * Author: Uri Mashiach */ -#include +#include #include #include #include diff --git a/board/compulab/cl-som-imx7/common.c b/board/compulab/cl-som-imx7/common.c index 40ba0f7a960..ae8e8346620 100644 --- a/board/compulab/cl-som-imx7/common.c +++ b/board/compulab/cl-som-imx7/common.c @@ -7,7 +7,6 @@ * Author: Uri Mashiach */ -#include #include #include #include "common.h" diff --git a/board/compulab/cl-som-imx7/mux.c b/board/compulab/cl-som-imx7/mux.c index 18f16a48738..25123ee145a 100644 --- a/board/compulab/cl-som-imx7/mux.c +++ b/board/compulab/cl-som-imx7/mux.c @@ -7,7 +7,7 @@ * Author: Uri Mashiach */ -#include +#include #include #include diff --git a/board/compulab/cl-som-imx7/spl.c b/board/compulab/cl-som-imx7/spl.c index 98c3b831f1e..9b6bbb974da 100644 --- a/board/compulab/cl-som-imx7/spl.c +++ b/board/compulab/cl-som-imx7/spl.c @@ -7,7 +7,6 @@ * Author: Uri Mashiach */ -#include #include #include #include diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index 7bce09e432c..4a6cc3e5630 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -7,7 +7,7 @@ * Author: Nikita Kiryanov */ -#include +#include #include #include #include diff --git a/board/compulab/cm_fx6/common.c b/board/compulab/cm_fx6/common.c index ed8c7a3bf5f..a71861b1731 100644 --- a/board/compulab/cm_fx6/common.c +++ b/board/compulab/cm_fx6/common.c @@ -7,7 +7,6 @@ * Author: Nikita Kiryanov */ -#include #include #include #include diff --git a/board/compulab/cm_fx6/spl.c b/board/compulab/cm_fx6/spl.c index 079f196200e..b11bf2d28c6 100644 --- a/board/compulab/cm_fx6/spl.c +++ b/board/compulab/cm_fx6/spl.c @@ -7,7 +7,6 @@ * Author: Nikita Kiryanov */ -#include #include #include #include diff --git a/board/compulab/cm_t43/cm_t43.c b/board/compulab/cm_t43/cm_t43.c index 5df378a62e3..181581926c3 100644 --- a/board/compulab/cm_t43/cm_t43.c +++ b/board/compulab/cm_t43/cm_t43.c @@ -3,7 +3,7 @@ * Copyright (C) 2015 Compulab, Ltd. */ -#include +#include #include #include #include diff --git a/board/compulab/cm_t43/mux.c b/board/compulab/cm_t43/mux.c index 778ea05e84c..f10910565d5 100644 --- a/board/compulab/cm_t43/mux.c +++ b/board/compulab/cm_t43/mux.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Compulab, Ltd. */ -#include #include #include #include "board.h" diff --git a/board/compulab/cm_t43/spl.c b/board/compulab/cm_t43/spl.c index a6223a477fe..212bfeb5c30 100644 --- a/board/compulab/cm_t43/spl.c +++ b/board/compulab/cm_t43/spl.c @@ -3,7 +3,7 @@ * Copyright (C) 2016 Compulab, Ltd. */ -#include +#include #include #include #include diff --git a/board/compulab/common/common.c b/board/compulab/common/common.c index 528c97df19a..6ffebe6bdb4 100644 --- a/board/compulab/common/common.c +++ b/board/compulab/common/common.c @@ -5,7 +5,6 @@ * Authors: Igor Grinberg */ -#include #include #include #include diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c index c4b257f851d..efdaf342d5c 100644 --- a/board/compulab/common/eeprom.c +++ b/board/compulab/common/eeprom.c @@ -6,13 +6,13 @@ * Igor Grinberg */ -#include -#include #include +#include #include #include #include #include +#include #include "eeprom.h" #define EEPROM_LAYOUT_VER_OFFSET 44 diff --git a/board/compulab/common/omap3_smc911x.c b/board/compulab/common/omap3_smc911x.c index f0d365272c1..411fc4943ba 100644 --- a/board/compulab/common/omap3_smc911x.c +++ b/board/compulab/common/omap3_smc911x.c @@ -5,7 +5,6 @@ * Authors: Igor Grinberg */ -#include #include #include diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c index b230478b611..99d3bf3af3b 100644 --- a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c @@ -5,7 +5,6 @@ * */ -#include #include #include #include diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c b/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c index 9019a1f2035..efcc95c739f 100644 --- a/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c @@ -7,7 +7,6 @@ */ #include -#include #include #include diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.c b/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.c index 5141c04f12d..67f59ed9407 100644 --- a/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.c +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.c @@ -7,7 +7,6 @@ */ #include -#include #include #include diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff000110.c b/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff000110.c index 2334722497d..273ee89c0bc 100644 --- a/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff000110.c +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff000110.c @@ -7,7 +7,6 @@ */ #include -#include #include #include diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff020008.c b/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff020008.c index e65445e0155..1243800b324 100644 --- a/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff020008.c +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff020008.c @@ -7,7 +7,6 @@ */ #include -#include #include #include diff --git a/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c b/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c index 90cc33a6e46..1256848f9a9 100644 --- a/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c +++ b/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* (C) Copyright 2019 CompuLab, Ltd. */ -#include +#include #include #include #include diff --git a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c index af070ec315c..ba158734142 100644 --- a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c +++ b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c @@ -4,7 +4,6 @@ * Copyright 2020 Linaro */ -#include #include #include #include diff --git a/board/compulab/imx8mm-cl-iot-gate/spl.c b/board/compulab/imx8mm-cl-iot-gate/spl.c index 19c1acd8a52..6d9af2538b6 100644 --- a/board/compulab/imx8mm-cl-iot-gate/spl.c +++ b/board/compulab/imx8mm-cl-iot-gate/spl.c @@ -4,7 +4,6 @@ * Copyright 2020 Linaro */ -#include #include #include #include diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c index 21ff0cda7f7..af05c0c0f05 100644 --- a/board/compulab/trimslice/trimslice.c +++ b/board/compulab/trimslice/trimslice.c @@ -4,7 +4,6 @@ * NVIDIA Corporation */ -#include #include #include #include diff --git a/board/conclusive/kstr-sama5d27/kstr-sama5d27.c b/board/conclusive/kstr-sama5d27/kstr-sama5d27.c index 1b765b11374..64282ae9dc7 100644 --- a/board/conclusive/kstr-sama5d27/kstr-sama5d27.c +++ b/board/conclusive/kstr-sama5d27/kstr-sama5d27.c @@ -4,7 +4,7 @@ * Copyright (C) 2021-2023 Conclusive Engineering Sp. z o. o. */ -#include +#include #include #include #include diff --git a/board/congatec/cgtqmx8/cgtqmx8.c b/board/congatec/cgtqmx8/cgtqmx8.c index d8e5b1d6963..99c33a1943e 100644 --- a/board/congatec/cgtqmx8/cgtqmx8.c +++ b/board/congatec/cgtqmx8/cgtqmx8.c @@ -3,7 +3,7 @@ * Copyright 2018 congatec AG * Copyright (C) 2019 Oliver Graute */ -#include +#include #include #include #include diff --git a/board/congatec/cgtqmx8/spl.c b/board/congatec/cgtqmx8/spl.c index b432ce27459..242e794981b 100644 --- a/board/congatec/cgtqmx8/spl.c +++ b/board/congatec/cgtqmx8/spl.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/board/congatec/common/mmc.c b/board/congatec/common/mmc.c index bb7a3d4a9aa..74a189ab4d7 100644 --- a/board/congatec/common/mmc.c +++ b/board/congatec/common/mmc.c @@ -4,7 +4,8 @@ * Copyright 2018 NXP * */ -#include + +#include #include #include #include diff --git a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c index 315b6dc5429..4197e88fb6f 100644 --- a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c +++ b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Stefan Roese */ -#include #include #include #include diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c index e58dce37477..f2ca1076768 100644 --- a/board/coreboot/coreboot/coreboot.c +++ b/board/coreboot/coreboot/coreboot.c @@ -3,7 +3,6 @@ * Copyright (C) 2018, Bin Meng */ -#include #include #include #include diff --git a/board/cortina/presidio-asic/presidio.c b/board/cortina/presidio-asic/presidio.c index fdfa3affc3b..c07e0eae4e9 100644 --- a/board/cortina/presidio-asic/presidio.c +++ b/board/cortina/presidio-asic/presidio.c @@ -3,7 +3,7 @@ * (C) Copyright 2020 - Cortina Access Inc. * */ -#include +#include #include #include #include diff --git a/board/cssi/cmpcpro/cmpcpro.c b/board/cssi/cmpcpro/cmpcpro.c index ef304124564..ec13d9a7ed7 100644 --- a/board/cssi/cmpcpro/cmpcpro.c +++ b/board/cssi/cmpcpro/cmpcpro.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/board/d-link/dns325/dns325.c b/board/d-link/dns325/dns325.c index 8ebfe4c6018..3bbde9808d2 100644 --- a/board/d-link/dns325/dns325.c +++ b/board/d-link/dns325/dns325.c @@ -9,7 +9,6 @@ * Written-by: Prafulla Wadaskar */ -#include #include #include #include diff --git a/board/data_modul/common/common.c b/board/data_modul/common/common.c index 4ece82c7303..b4d74a8fd8b 100644 --- a/board/data_modul/common/common.c +++ b/board/data_modul/common/common.c @@ -3,7 +3,6 @@ * Copyright 2022 Marek Vasut */ -#include #include #include #include diff --git a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c index bfb2bddc1d1..339702e8392 100644 --- a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c +++ b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c @@ -3,7 +3,6 @@ * Copyright 2022 Marek Vasut */ -#include #include #include #include diff --git a/board/data_modul/imx8mm_edm_sbc/spl.c b/board/data_modul/imx8mm_edm_sbc/spl.c index 4a9c62fb86f..17aafd719c9 100644 --- a/board/data_modul/imx8mm_edm_sbc/spl.c +++ b/board/data_modul/imx8mm_edm_sbc/spl.c @@ -3,7 +3,6 @@ * Copyright 2022 Marek Vasut */ -#include #include #include #include diff --git a/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c b/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c index f0f373aa280..138acd36ad2 100644 --- a/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c +++ b/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c @@ -3,7 +3,6 @@ * Copyright 2022 Marek Vasut */ -#include #include #include #include diff --git a/board/data_modul/imx8mp_edm_sbc/spl.c b/board/data_modul/imx8mp_edm_sbc/spl.c index cc2d253e391..c1935898533 100644 --- a/board/data_modul/imx8mp_edm_sbc/spl.c +++ b/board/data_modul/imx8mp_edm_sbc/spl.c @@ -3,7 +3,6 @@ * Copyright 2022 Marek Vasut */ -#include #include #include #include diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 05053a87a5a..0011c828523 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -8,7 +8,7 @@ * Copyright (C) 2007 Sergey Kubushyn */ -#include +#include #include #include #include diff --git a/board/davinci/da8xxevm/omapl138_lcdk.c b/board/davinci/da8xxevm/omapl138_lcdk.c index 9738e2bd9c7..607e05ad9ae 100644 --- a/board/davinci/da8xxevm/omapl138_lcdk.c +++ b/board/davinci/da8xxevm/omapl138_lcdk.c @@ -8,7 +8,7 @@ * Copyright (C) 2007 Sergey Kubushyn */ -#include +#include #include #include #include diff --git a/board/dfi/dfi-bt700/dfi-bt700.c b/board/dfi/dfi-bt700/dfi-bt700.c index 87506a77a17..907cc985d7a 100644 --- a/board/dfi/dfi-bt700/dfi-bt700.c +++ b/board/dfi/dfi-bt700/dfi-bt700.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Stefan Roese */ -#include #include #include #include diff --git a/board/dhelectronics/common/dh_common.c b/board/dhelectronics/common/dh_common.c index 34094a020b0..32c50b4f0f5 100644 --- a/board/dhelectronics/common/dh_common.c +++ b/board/dhelectronics/common/dh_common.c @@ -4,7 +4,6 @@ * Copyright 2022 DENX Software Engineering GmbH, Philip Oberfichtner */ -#include #include #include #include diff --git a/board/dhelectronics/common/dh_imx.c b/board/dhelectronics/common/dh_imx.c index 7f451bad59c..3d6487dd0d8 100644 --- a/board/dhelectronics/common/dh_imx.c +++ b/board/dhelectronics/common/dh_imx.c @@ -4,9 +4,9 @@ * Copyright 2022 DENX Software Engineering GmbH, Philip Oberfichtner */ +#include #include #include -#include #include #include "dh_imx.h" diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c b/board/dhelectronics/dh_imx6/dh_imx6.c index 0676587c38a..c8dd30dfeaf 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6.c +++ b/board/dhelectronics/dh_imx6/dh_imx6.c @@ -5,9 +5,7 @@ * Copyright (C) 2017 Marek Vasut */ -#include #include -#include #include #include #include diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c index e6d5657c62d..3a5495ea18e 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c @@ -5,7 +5,6 @@ * Copyright (C) 2017 Marek Vasut */ -#include #include #include #include diff --git a/board/dhelectronics/dh_imx8mp/common.c b/board/dhelectronics/dh_imx8mp/common.c index 44456da681c..f6db9f67804 100644 --- a/board/dhelectronics/dh_imx8mp/common.c +++ b/board/dhelectronics/dh_imx8mp/common.c @@ -3,7 +3,6 @@ * Copyright 2022 Marek Vasut */ -#include #include #include diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c index ff2c0e87215..c635735d89c 100644 --- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c +++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c @@ -3,7 +3,6 @@ * Copyright 2022 Marek Vasut */ -#include #include #include #include diff --git a/board/dhelectronics/dh_imx8mp/spl.c b/board/dhelectronics/dh_imx8mp/spl.c index 7d228da8e5b..714f846521e 100644 --- a/board/dhelectronics/dh_imx8mp/spl.c +++ b/board/dhelectronics/dh_imx8mp/spl.c @@ -3,7 +3,6 @@ * Copyright 2022 Marek Vasut */ -#include #include #include #include diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index 22af423536d..20c9d70737e 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -3,7 +3,6 @@ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved */ -#include #include #include #include diff --git a/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c b/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c index 2b03e4891d9..222e5facf43 100644 --- a/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c +++ b/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c @@ -5,7 +5,7 @@ */ #include -#include +#include #include #include diff --git a/board/ea/mx7ulp_com/mx7ulp_com.c b/board/ea/mx7ulp_com/mx7ulp_com.c index cd9591a9e32..8f78937e097 100644 --- a/board/ea/mx7ulp_com/mx7ulp_com.c +++ b/board/ea/mx7ulp_com/mx7ulp_com.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/board/eets/pdu001/board.c b/board/eets/pdu001/board.c index 3a52e4ae675..2ad256f8635 100644 --- a/board/eets/pdu001/board.c +++ b/board/eets/pdu001/board.c @@ -9,7 +9,7 @@ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include +#include #include #include #include diff --git a/board/eets/pdu001/mux.c b/board/eets/pdu001/mux.c index c97927e5cfe..f306a134031 100644 --- a/board/eets/pdu001/mux.c +++ b/board/eets/pdu001/mux.c @@ -7,7 +7,7 @@ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ -#include +#include #include #include #include diff --git a/board/efi/efi-x86_payload/payload.c b/board/efi/efi-x86_payload/payload.c index 5d4492cdc77..d7d1e53e911 100644 --- a/board/efi/efi-x86_payload/payload.c +++ b/board/efi/efi-x86_payload/payload.c @@ -3,7 +3,6 @@ * Copyright (C) 2018, Bin Meng */ -#include #include #include diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c index 9953df017e1..64e341c3779 100644 --- a/board/egnite/ethernut5/ethernut5.c +++ b/board/egnite/ethernut5/ethernut5.c @@ -52,7 +52,7 @@ * http://www.ethernut.de/ */ -#include +#include #include #include #include diff --git a/board/egnite/ethernut5/ethernut5_pwrman.c b/board/egnite/ethernut5/ethernut5_pwrman.c index 81f1abf2fad..42e1914a875 100644 --- a/board/egnite/ethernut5/ethernut5_pwrman.c +++ b/board/egnite/ethernut5/ethernut5_pwrman.c @@ -31,8 +31,8 @@ * For additional information visit the project home page at * http://www.ethernut.de/ */ -#include #include +#include #include #include #include diff --git a/board/elgin/elgin_rv1108/elgin_rv1108.c b/board/elgin/elgin_rv1108/elgin_rv1108.c index 10398e7f712..9fea4f86d5a 100644 --- a/board/elgin/elgin_rv1108/elgin_rv1108.c +++ b/board/elgin/elgin_rv1108/elgin_rv1108.c @@ -4,7 +4,6 @@ * Authors: Andy Yan */ -#include #include #include #include diff --git a/board/embest/mx6boards/mx6boards.c b/board/embest/mx6boards/mx6boards.c index a3c23bdfb64..896350140d6 100644 --- a/board/embest/mx6boards/mx6boards.c +++ b/board/embest/mx6boards/mx6boards.c @@ -12,7 +12,6 @@ * Copyright (C) 2013 Jon Nettleton . */ -#include #include #include #include diff --git a/board/emulation/common/qemu_dfu.c b/board/emulation/common/qemu_dfu.c index 7e7d84f6c00..393fcaeb742 100644 --- a/board/emulation/common/qemu_dfu.c +++ b/board/emulation/common/qemu_dfu.c @@ -3,7 +3,6 @@ * Copyright (c) 2020 Linaro Limited */ -#include #include #include #include diff --git a/board/emulation/common/qemu_mtdparts.c b/board/emulation/common/qemu_mtdparts.c index 60212e97acf..c1501276789 100644 --- a/board/emulation/common/qemu_mtdparts.c +++ b/board/emulation/common/qemu_mtdparts.c @@ -3,7 +3,6 @@ * Copyright (c) 2020 Linaro Limited */ -#include #include #include diff --git a/board/emulation/qemu-arm/qemu-arm.c b/board/emulation/qemu-arm/qemu-arm.c index ecfd19f1a7e..6095cb02b23 100644 --- a/board/emulation/qemu-arm/qemu-arm.c +++ b/board/emulation/qemu-arm/qemu-arm.c @@ -3,7 +3,7 @@ * Copyright (c) 2017 Tuomas Tynkkynen */ -#include +#include #include #include #include diff --git a/board/emulation/qemu-ppce500/qemu-ppce500.c b/board/emulation/qemu-ppce500/qemu-ppce500.c index 221361691c1..58e5d5eb942 100644 --- a/board/emulation/qemu-ppce500/qemu-ppce500.c +++ b/board/emulation/qemu-ppce500/qemu-ppce500.c @@ -4,7 +4,7 @@ * Copyright (C) 2021, Bin Meng */ -#include +#include #include #include #include diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c index 173245b40e3..e5193e31e37 100644 --- a/board/emulation/qemu-riscv/qemu-riscv.c +++ b/board/emulation/qemu-riscv/qemu-riscv.c @@ -3,7 +3,6 @@ * Copyright (C) 2018, Bin Meng */ -#include #include #include #include diff --git a/board/engicam/common/board.c b/board/engicam/common/board.c index df9149e0d6d..8e0477c7a6e 100644 --- a/board/engicam/common/board.c +++ b/board/engicam/common/board.c @@ -5,7 +5,6 @@ * Author: Jagan Teki */ -#include #include #include #include diff --git a/board/engicam/common/spl.c b/board/engicam/common/spl.c index f1ccdc33436..8bc80ee6baa 100644 --- a/board/engicam/common/spl.c +++ b/board/engicam/common/spl.c @@ -5,7 +5,6 @@ * Author: Jagan Teki */ -#include #include #include #include diff --git a/board/engicam/imx6q/imx6q.c b/board/engicam/imx6q/imx6q.c index e6c888fcfde..d799fe6526a 100644 --- a/board/engicam/imx6q/imx6q.c +++ b/board/engicam/imx6q/imx6q.c @@ -5,7 +5,6 @@ * Author: Jagan Teki */ -#include #include #include diff --git a/board/engicam/imx6ul/imx6ul.c b/board/engicam/imx6ul/imx6ul.c index 412d6c302e8..24d654445db 100644 --- a/board/engicam/imx6ul/imx6ul.c +++ b/board/engicam/imx6ul/imx6ul.c @@ -5,7 +5,6 @@ * Author: Jagan Teki */ -#include #include #include diff --git a/board/engicam/imx8mm/icore_mx8mm.c b/board/engicam/imx8mm/icore_mx8mm.c index 320388faae3..236337546ae 100644 --- a/board/engicam/imx8mm/icore_mx8mm.c +++ b/board/engicam/imx8mm/icore_mx8mm.c @@ -5,7 +5,6 @@ * Author: Jagan Teki */ -#include #include #include diff --git a/board/engicam/imx8mm/lpddr4_timing.c b/board/engicam/imx8mm/lpddr4_timing.c index 821212740bc..fcd45c158f2 100644 --- a/board/engicam/imx8mm/lpddr4_timing.c +++ b/board/engicam/imx8mm/lpddr4_timing.c @@ -6,7 +6,6 @@ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga */ -#include #include #include diff --git a/board/engicam/imx8mm/spl.c b/board/engicam/imx8mm/spl.c index af9044a3c2b..d51ae241e85 100644 --- a/board/engicam/imx8mm/spl.c +++ b/board/engicam/imx8mm/spl.c @@ -5,7 +5,6 @@ * Author: Jagan Teki */ -#include #include #include #include diff --git a/board/engicam/imx8mp/icore_mx8mp.c b/board/engicam/imx8mp/icore_mx8mp.c index 5f820cc8dd7..e2ed70caa43 100644 --- a/board/engicam/imx8mp/icore_mx8mp.c +++ b/board/engicam/imx8mp/icore_mx8mp.c @@ -8,7 +8,6 @@ * Jagan Teki */ -#include #include #include #include diff --git a/board/engicam/imx8mp/spl.c b/board/engicam/imx8mp/spl.c index 36b83aace39..cd31aa6041d 100644 --- a/board/engicam/imx8mp/spl.c +++ b/board/engicam/imx8mp/spl.c @@ -8,7 +8,6 @@ * Jagan Teki */ -#include #include #include #include diff --git a/board/engicam/stm32mp1/spl.c b/board/engicam/stm32mp1/spl.c index 2b7779cc01d..bb2bd446aa8 100644 --- a/board/engicam/stm32mp1/spl.c +++ b/board/engicam/stm32mp1/spl.c @@ -5,7 +5,7 @@ * Copyright (C) 2020 Amarula Solutions(India) */ -#include +#include /* board early initialisation in board_f: need to use global variable */ static u32 opp_voltage_mv __section(".data"); diff --git a/board/engicam/stm32mp1/stm32mp1.c b/board/engicam/stm32mp1/stm32mp1.c index 5223e9bae8d..bc2af66d8e9 100644 --- a/board/engicam/stm32mp1/stm32mp1.c +++ b/board/engicam/stm32mp1/stm32mp1.c @@ -6,7 +6,6 @@ * Author: Jagan Teki */ -#include #include #include #include diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index 9e362104224..dce69abdfd1 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -9,7 +9,7 @@ * esd electronic system design gmbh */ -#include +#include #include #include #include diff --git a/board/firefly/firefly-rk3288/firefly-rk3288.c b/board/firefly/firefly-rk3288/firefly-rk3288.c index 95d8b00924d..8e67ab4b132 100644 --- a/board/firefly/firefly-rk3288/firefly-rk3288.c +++ b/board/firefly/firefly-rk3288/firefly-rk3288.c @@ -3,7 +3,6 @@ * (C) Copyright 2015 Google, Inc */ -#include #include #include #include diff --git a/board/firefly/firefly-rk3308/roc_cc_rk3308.c b/board/firefly/firefly-rk3308/roc_cc_rk3308.c index af00250e118..404bdc632bb 100644 --- a/board/firefly/firefly-rk3308/roc_cc_rk3308.c +++ b/board/firefly/firefly-rk3308/roc_cc_rk3308.c @@ -3,7 +3,6 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c index 590519b32af..a149e4fe822 100644 --- a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c +++ b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c @@ -3,7 +3,6 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/board/freescale/common/cadmus.c b/board/freescale/common/cadmus.c index e7e07fff86c..6f66ed6851d 100644 --- a/board/freescale/common/cadmus.c +++ b/board/freescale/common/cadmus.c @@ -4,8 +4,9 @@ */ -#include +#include #include +#include /* * CADMUS Board System Registers diff --git a/board/freescale/common/cds_pci_ft.c b/board/freescale/common/cds_pci_ft.c index dc2d62850d1..56b01e3f51f 100644 --- a/board/freescale/common/cds_pci_ft.c +++ b/board/freescale/common/cds_pci_ft.c @@ -3,7 +3,6 @@ * Copyright 2004 Freescale Semiconductor. */ -#include #include #include #include "cadmus.h" diff --git a/board/freescale/common/cds_via.c b/board/freescale/common/cds_via.c index 6184472b165..6fc3a21780f 100644 --- a/board/freescale/common/cds_via.c +++ b/board/freescale/common/cds_via.c @@ -3,7 +3,6 @@ * Copyright 2006 Freescale Semiconductor. */ -#include #include /* Config the VIA chip */ diff --git a/board/freescale/common/cmd_esbc_validate.c b/board/freescale/common/cmd_esbc_validate.c index 6c096266b48..d4192e5ab52 100644 --- a/board/freescale/common/cmd_esbc_validate.c +++ b/board/freescale/common/cmd_esbc_validate.c @@ -3,10 +3,10 @@ * Copyright 2015 Freescale Semiconductor, Inc. */ -#include #include #include #include +#include int do_esbc_halt(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/board/freescale/common/emc2305.c b/board/freescale/common/emc2305.c index 9a75c5a09dd..50252bb5007 100644 --- a/board/freescale/common/emc2305.c +++ b/board/freescale/common/emc2305.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/board/freescale/common/fman.c b/board/freescale/common/fman.c index 358303108d8..650ecc7b440 100644 --- a/board/freescale/common/fman.c +++ b/board/freescale/common/fman.c @@ -3,7 +3,6 @@ * Copyright 2011-2015 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index 87ed814d6a2..27a33924c84 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -4,7 +4,7 @@ * Copyright 2022 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index bfe6357b0d6..e03434dcdfe 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -4,7 +4,7 @@ * Copyright 2021-2022 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/common/i2c_common.c b/board/freescale/common/i2c_common.c index 119ed3c6171..20705ecc8e4 100644 --- a/board/freescale/common/i2c_common.c +++ b/board/freescale/common/i2c_common.c @@ -5,7 +5,7 @@ * Copyright 2021 Microsoft Corporation */ -#include +#include #include #include "i2c_common.h" diff --git a/board/freescale/common/i2c_mux.c b/board/freescale/common/i2c_mux.c index d40b34f1039..89151ccaf06 100644 --- a/board/freescale/common/i2c_mux.c +++ b/board/freescale/common/i2c_mux.c @@ -5,8 +5,9 @@ * Copyright 2021 Microsoft Corporation */ -#include +#include #include +#include #include "i2c_common.h" #include "i2c_mux.h" diff --git a/board/freescale/common/ics307_clk.c b/board/freescale/common/ics307_clk.c index 5f95571d24c..af30faa0c5f 100644 --- a/board/freescale/common/ics307_clk.c +++ b/board/freescale/common/ics307_clk.c @@ -3,7 +3,7 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/common/ls102xa_stream_id.c b/board/freescale/common/ls102xa_stream_id.c index f754cf42fd3..bf76274c43c 100644 --- a/board/freescale/common/ls102xa_stream_id.c +++ b/board/freescale/common/ls102xa_stream_id.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor */ -#include +#include #include #include diff --git a/board/freescale/common/mc34vr500.c b/board/freescale/common/mc34vr500.c index d6b4c65a3c0..cf14b29a3ec 100644 --- a/board/freescale/common/mc34vr500.c +++ b/board/freescale/common/mc34vr500.c @@ -4,7 +4,6 @@ * Hou Zhiqiang */ -#include #include #include #include diff --git a/board/freescale/common/mmc.c b/board/freescale/common/mmc.c index 8cd5079f962..00e4f3675fe 100644 --- a/board/freescale/common/mmc.c +++ b/board/freescale/common/mmc.c @@ -4,8 +4,8 @@ * Copyright 2018-2022 NXP */ -#include #include +#include #include #include #include diff --git a/board/freescale/common/ngpixis.c b/board/freescale/common/ngpixis.c index 7be1ccee638..74c345807e6 100644 --- a/board/freescale/common/ngpixis.c +++ b/board/freescale/common/ngpixis.c @@ -29,7 +29,6 @@ * boot from the alternate bank. */ -#include #include #include diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c index a95d15c1ef3..c46e87f4cce 100644 --- a/board/freescale/common/ns_access.c +++ b/board/freescale/common/ns_access.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor */ -#include +#include #include #include #include diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c index 1a1e9343d23..83818d6d847 100644 --- a/board/freescale/common/p_corenet/law.c +++ b/board/freescale/common/p_corenet/law.c @@ -6,7 +6,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index 1a2d9cbfc0c..cebdedfa4a7 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -6,8 +6,9 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include +#include struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ diff --git a/board/freescale/common/pfuze.c b/board/freescale/common/pfuze.c index a9288820b2e..0d7a94fd232 100644 --- a/board/freescale/common/pfuze.c +++ b/board/freescale/common/pfuze.c @@ -3,7 +3,6 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index da2c1de078b..6400ac05245 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -7,7 +7,7 @@ * This file provides support for the QIXIS of some Freescale reference boards. */ -#include +#include #include #include #include diff --git a/board/freescale/common/sdhc_boot.c b/board/freescale/common/sdhc_boot.c index a1c7a94a90e..5ee730cefd0 100644 --- a/board/freescale/common/sdhc_boot.c +++ b/board/freescale/common/sdhc_boot.c @@ -3,7 +3,6 @@ * Copyright 2011 Freescale Semiconductor, Inc. */ -#include #include #include diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 64139d4659f..ec3c9e37222 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -6,7 +6,6 @@ * Timur Tabi (timur@freescale.com) */ -#include #include #include #include diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index fc5d400cfe1..84cb43fad56 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -5,12 +5,13 @@ * Copyright 2020 Stephen Carlson */ -#include +#include #include #include #include #include #include +#include #include #ifdef CONFIG_FSL_LSCH2 #include diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c b/board/freescale/imx8mm_evk/imx8mm_evk.c index e0975fcda70..4c4436af3b1 100644 --- a/board/freescale/imx8mm_evk/imx8mm_evk.c +++ b/board/freescale/imx8mm_evk/imx8mm_evk.c @@ -3,7 +3,6 @@ * Copyright 2018 NXP */ -#include #include #include #include diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c index 35437811d9d..cd251d274ff 100644 --- a/board/freescale/imx8mm_evk/spl.c +++ b/board/freescale/imx8mm_evk/spl.c @@ -3,7 +3,6 @@ * Copyright 2019, 2021 NXP */ -#include #include #include #include diff --git a/board/freescale/imx8mn_evk/imx8mn_evk.c b/board/freescale/imx8mn_evk/imx8mn_evk.c index e35d505aea9..6b6fb0a7dd2 100644 --- a/board/freescale/imx8mn_evk/imx8mn_evk.c +++ b/board/freescale/imx8mn_evk/imx8mn_evk.c @@ -3,7 +3,6 @@ * Copyright 2019 NXP */ -#include #include #include #include diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c index dd54fa9b608..231b9289eea 100644 --- a/board/freescale/imx8mn_evk/spl.c +++ b/board/freescale/imx8mn_evk/spl.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c index 9dd2cbc799c..12da1b2abfb 100644 --- a/board/freescale/imx8mp_evk/spl.c +++ b/board/freescale/imx8mp_evk/spl.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c index e577e4d9cca..ab920a4539c 100644 --- a/board/freescale/imx8mq_evk/imx8mq_evk.c +++ b/board/freescale/imx8mq_evk/imx8mq_evk.c @@ -3,7 +3,6 @@ * Copyright 2018 NXP */ -#include #include #include #include diff --git a/board/freescale/imx8mq_evk/lpddr4_timing.c b/board/freescale/imx8mq_evk/lpddr4_timing.c index 46bc7f8591c..e9559e3d843 100644 --- a/board/freescale/imx8mq_evk/lpddr4_timing.c +++ b/board/freescale/imx8mq_evk/lpddr4_timing.c @@ -4,7 +4,6 @@ */ #include -#include #include #include diff --git a/board/freescale/imx8mq_evk/lpddr4_timing_b0.c b/board/freescale/imx8mq_evk/lpddr4_timing_b0.c index ec68edaf690..5d8f2803be6 100644 --- a/board/freescale/imx8mq_evk/lpddr4_timing_b0.c +++ b/board/freescale/imx8mq_evk/lpddr4_timing_b0.c @@ -4,7 +4,6 @@ */ #include -#include #include #include diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c index 818cdd615eb..a346305c863 100644 --- a/board/freescale/imx8mq_evk/spl.c +++ b/board/freescale/imx8mq_evk/spl.c @@ -4,7 +4,7 @@ * */ -#include +#include #include #include #include diff --git a/board/freescale/imx8qm_mek/imx8qm_mek.c b/board/freescale/imx8qm_mek/imx8qm_mek.c index 2b209c8886f..72527f774ca 100644 --- a/board/freescale/imx8qm_mek/imx8qm_mek.c +++ b/board/freescale/imx8qm_mek/imx8qm_mek.c @@ -3,7 +3,6 @@ * Copyright 2018 NXP */ -#include #include #include #include diff --git a/board/freescale/imx8qm_mek/spl.c b/board/freescale/imx8qm_mek/spl.c index 17fd437116d..ad786833309 100644 --- a/board/freescale/imx8qm_mek/spl.c +++ b/board/freescale/imx8qm_mek/spl.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/board/freescale/imx8qxp_mek/imx8qxp_mek.c index 833bee55462..adb9556a021 100644 --- a/board/freescale/imx8qxp_mek/imx8qxp_mek.c +++ b/board/freescale/imx8qxp_mek/imx8qxp_mek.c @@ -3,7 +3,6 @@ * Copyright 2018 NXP */ -#include #include #include #include diff --git a/board/freescale/imx8qxp_mek/spl.c b/board/freescale/imx8qxp_mek/spl.c index 462c43ceebc..05e3c0a2ff2 100644 --- a/board/freescale/imx8qxp_mek/spl.c +++ b/board/freescale/imx8qxp_mek/spl.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.c b/board/freescale/imx8ulp_evk/imx8ulp_evk.c index dd04d5925a0..0af61067263 100644 --- a/board/freescale/imx8ulp_evk/imx8ulp_evk.c +++ b/board/freescale/imx8ulp_evk/imx8ulp_evk.c @@ -3,7 +3,6 @@ * Copyright 2020 NXP */ -#include #include #include #include diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c index c49b5be4762..d123b21b722 100644 --- a/board/freescale/imx8ulp_evk/spl.c +++ b/board/freescale/imx8ulp_evk/spl.c @@ -3,7 +3,6 @@ * Copyright 2021 NXP */ -#include #include #include #include diff --git a/board/freescale/imx93_evk/imx93_evk.c b/board/freescale/imx93_evk/imx93_evk.c index c54dc9d05c5..341831a7d30 100644 --- a/board/freescale/imx93_evk/imx93_evk.c +++ b/board/freescale/imx93_evk/imx93_evk.c @@ -3,7 +3,6 @@ * Copyright 2022 NXP */ -#include #include #include #include diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c index 6d5e110b277..e5807134bb2 100644 --- a/board/freescale/imx93_evk/spl.c +++ b/board/freescale/imx93_evk/spl.c @@ -3,7 +3,6 @@ * Copyright 2022 NXP */ -#include #include #include #include diff --git a/board/freescale/imxrt1020-evk/imxrt1020-evk.c b/board/freescale/imxrt1020-evk/imxrt1020-evk.c index 785da604b96..42a0a67ae93 100644 --- a/board/freescale/imxrt1020-evk/imxrt1020-evk.c +++ b/board/freescale/imxrt1020-evk/imxrt1020-evk.c @@ -4,7 +4,6 @@ * Author(s): Giulio Benetti */ -#include #include #include #include diff --git a/board/freescale/imxrt1050-evk/imxrt1050-evk.c b/board/freescale/imxrt1050-evk/imxrt1050-evk.c index 4cc3defc882..46a644908e9 100644 --- a/board/freescale/imxrt1050-evk/imxrt1050-evk.c +++ b/board/freescale/imxrt1050-evk/imxrt1050-evk.c @@ -4,7 +4,6 @@ * Author(s): Giulio Benetti */ -#include #include #include #include diff --git a/board/freescale/imxrt1170-evk/imxrt1170-evk.c b/board/freescale/imxrt1170-evk/imxrt1170-evk.c index 4b82ee5e9ce..e10b8830ec6 100644 --- a/board/freescale/imxrt1170-evk/imxrt1170-evk.c +++ b/board/freescale/imxrt1170-evk/imxrt1170-evk.c @@ -4,7 +4,6 @@ * Author(s): Giulio Benetti */ -#include #include #include #include diff --git a/board/freescale/ls1012afrdm/eth.c b/board/freescale/ls1012afrdm/eth.c index d2df9351eac..c431e5e611b 100644 --- a/board/freescale/ls1012afrdm/eth.c +++ b/board/freescale/ls1012afrdm/eth.c @@ -4,7 +4,6 @@ * Copyright 2017 NXP */ -#include #include #include #include diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c index 271072bf7a1..dae2cf097bc 100644 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -3,7 +3,7 @@ * Copyright 2017-2018, 2021 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c index 38267acedde..d5e87c5393b 100644 --- a/board/freescale/ls1012aqds/eth.c +++ b/board/freescale/ls1012aqds/eth.c @@ -4,7 +4,7 @@ * Copyright 2017 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index a5ea8d634ed..7d56eb0117d 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -4,7 +4,7 @@ * Copyright 2021 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c index 5c661274987..71cb2988a56 100644 --- a/board/freescale/ls1012ardb/eth.c +++ b/board/freescale/ls1012ardb/eth.c @@ -4,7 +4,7 @@ * Copyright 2017 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index 18f92089cae..7f8001b4981 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -4,7 +4,7 @@ * Copyright 2021 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c index d6f22bd6a2a..7abc4126933 100644 --- a/board/freescale/ls1021aiot/ls1021aiot.c +++ b/board/freescale/ls1021aiot/ls1021aiot.c @@ -4,7 +4,7 @@ * Copyright 2021 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c index 4e70acc5a0c..5b0f23688f0 100644 --- a/board/freescale/ls1021aqds/ddr.c +++ b/board/freescale/ls1021aqds/ddr.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/ls1028a/ddr.c b/board/freescale/ls1028a/ddr.c index 3e976da6b30..c406f2436d1 100644 --- a/board/freescale/ls1028a/ddr.c +++ b/board/freescale/ls1028a/ddr.c @@ -3,7 +3,6 @@ * Copyright 2019 NXP */ -#include #include #include #include diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c index 7f181ab3dfb..e01b5a8c2eb 100644 --- a/board/freescale/ls1028a/ls1028a.c +++ b/board/freescale/ls1028a/ls1028a.c @@ -3,7 +3,7 @@ * Copyright 2019-2022 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c index 23947bdb84c..2a9717df616 100644 --- a/board/freescale/ls1043aqds/ddr.c +++ b/board/freescale/ls1043aqds/ddr.c @@ -3,7 +3,6 @@ * Copyright 2015 Freescale Semiconductor, Inc. */ -#include #include #include #ifdef CONFIG_FSL_DEEP_SLEEP diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c index cd1f83e3d06..5a8ca27b327 100644 --- a/board/freescale/ls1043aqds/eth.c +++ b/board/freescale/ls1043aqds/eth.c @@ -4,7 +4,7 @@ * Copyright 2019 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index b87da41e408..fdf011efc5b 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -4,7 +4,7 @@ * Copyright 2019-2020 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c index 9db3aa58605..bda2f3ac3a6 100644 --- a/board/freescale/ls1043ardb/cpld.c +++ b/board/freescale/ls1043ardb/cpld.c @@ -5,7 +5,7 @@ * Freescale LS1043ARDB board-specific CPLD controlling supports. */ -#include +#include #include #include #include "cpld.h" diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c index 4d2fce38412..187925e981a 100644 --- a/board/freescale/ls1043ardb/ddr.c +++ b/board/freescale/ls1043ardb/ddr.c @@ -3,7 +3,6 @@ * Copyright 2015 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/board/freescale/ls1043ardb/eth.c b/board/freescale/ls1043ardb/eth.c index cc95214c4e3..cacc49c0584 100644 --- a/board/freescale/ls1043ardb/eth.c +++ b/board/freescale/ls1043ardb/eth.c @@ -2,7 +2,7 @@ /* * Copyright 2015 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/ls1046afrwy/ddr.c b/board/freescale/ls1046afrwy/ddr.c index 256397b52b6..b08caee1d97 100644 --- a/board/freescale/ls1046afrwy/ddr.c +++ b/board/freescale/ls1046afrwy/ddr.c @@ -3,7 +3,6 @@ * Copyright 2019 NXP */ -#include #include #include diff --git a/board/freescale/ls1046afrwy/eth.c b/board/freescale/ls1046afrwy/eth.c index d1a2bfe1885..8efc7f68424 100644 --- a/board/freescale/ls1046afrwy/eth.c +++ b/board/freescale/ls1046afrwy/eth.c @@ -2,7 +2,7 @@ /* * Copyright 2019 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c index 899c22a367e..8889c24f1f0 100644 --- a/board/freescale/ls1046afrwy/ls1046afrwy.c +++ b/board/freescale/ls1046afrwy/ls1046afrwy.c @@ -3,7 +3,7 @@ * Copyright 2019, 2021 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1046aqds/ddr.c b/board/freescale/ls1046aqds/ddr.c index 9a96de27178..ac1b6049721 100644 --- a/board/freescale/ls1046aqds/ddr.c +++ b/board/freescale/ls1046aqds/ddr.c @@ -3,7 +3,6 @@ * Copyright 2016 Freescale Semiconductor, Inc. */ -#include #include #include #ifdef CONFIG_FSL_DEEP_SLEEP diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c index bbf8b8c2bee..cd3500c2e96 100644 --- a/board/freescale/ls1046aqds/eth.c +++ b/board/freescale/ls1046aqds/eth.c @@ -4,7 +4,7 @@ * Copyright 2018-2020 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index 2faac54a0e2..a83b2170651 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -4,7 +4,7 @@ * Copyright 2019-2021 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1046ardb/cpld.c b/board/freescale/ls1046ardb/cpld.c index ee19d4ff8aa..7f8ca2e857f 100644 --- a/board/freescale/ls1046ardb/cpld.c +++ b/board/freescale/ls1046ardb/cpld.c @@ -5,7 +5,7 @@ * Freescale LS1046ARDB board-specific CPLD controlling supports. */ -#include +#include #include #include #include "cpld.h" diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c index befb556bd30..68353022e7d 100644 --- a/board/freescale/ls1046ardb/ddr.c +++ b/board/freescale/ls1046ardb/ddr.c @@ -3,7 +3,6 @@ * Copyright 2016 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/board/freescale/ls1046ardb/eth.c b/board/freescale/ls1046ardb/eth.c index bbc22a3cdf4..fee8e0e21d4 100644 --- a/board/freescale/ls1046ardb/eth.c +++ b/board/freescale/ls1046ardb/eth.c @@ -2,7 +2,7 @@ /* * Copyright 2016 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c index 26e69db55f7..0492f0a8c0a 100644 --- a/board/freescale/ls1046ardb/ls1046ardb.c +++ b/board/freescale/ls1046ardb/ls1046ardb.c @@ -4,7 +4,7 @@ * Copyright 2021 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1088a/ddr.c b/board/freescale/ls1088a/ddr.c index 9e0941cc9d6..d2e239c4d61 100644 --- a/board/freescale/ls1088a/ddr.c +++ b/board/freescale/ls1088a/ddr.c @@ -3,7 +3,6 @@ * Copyright 2017 NXP */ -#include #include #include #include diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index 98a91c48adb..58951f2bb2a 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -2,7 +2,7 @@ /* * Copyright 2017-2022 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls2080aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c index 2767d058cc9..2986ffb7a82 100644 --- a/board/freescale/ls2080aqds/ddr.c +++ b/board/freescale/ls2080aqds/ddr.c @@ -3,7 +3,6 @@ * Copyright 2015 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 5c94c83121b..4c8d0706688 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -3,7 +3,7 @@ * Copyright 2015 Freescale Semiconductor * Copyright 2021 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls2080ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c index 07fa8473332..ec34b42e619 100644 --- a/board/freescale/ls2080ardb/ddr.c +++ b/board/freescale/ls2080ardb/ddr.c @@ -3,7 +3,6 @@ * Copyright 2015 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 5c30de83d84..6f824f57c47 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -3,7 +3,7 @@ * Copyright 2015 Freescale Semiconductor * Copyright 2017, 2021 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/lx2160a/ddr.c b/board/freescale/lx2160a/ddr.c index 7ab7a9e6ca8..637e43a22be 100644 --- a/board/freescale/lx2160a/ddr.c +++ b/board/freescale/lx2160a/ddr.c @@ -3,7 +3,6 @@ * Copyright 2018 NXP */ -#include #include #include #include diff --git a/board/freescale/lx2160a/eth_lx2160ardb.c b/board/freescale/lx2160a/eth_lx2160ardb.c index c5dfefe1f34..90e7c9100e1 100644 --- a/board/freescale/lx2160a/eth_lx2160ardb.c +++ b/board/freescale/lx2160a/eth_lx2160ardb.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index b3187a14214..3aa984dab8e 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -3,7 +3,7 @@ * Copyright 2018-2021 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/m5208evbe/m5208evbe.c b/board/freescale/m5208evbe/m5208evbe.c index 6125c9e13aa..b202b8094d9 100644 --- a/board/freescale/m5208evbe/m5208evbe.c +++ b/board/freescale/m5208evbe/m5208evbe.c @@ -8,7 +8,6 @@ */ #include -#include #include #include #include diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c index 44161a0b0a1..65cde56fb2d 100644 --- a/board/freescale/m5235evb/m5235evb.c +++ b/board/freescale/m5235evb/m5235evb.c @@ -8,7 +8,6 @@ */ #include -#include #include #include #include diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c index d67db24d588..717dc087e02 100644 --- a/board/freescale/m5249evb/m5249evb.c +++ b/board/freescale/m5249evb/m5249evb.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include diff --git a/board/freescale/m5253demo/flash.c b/board/freescale/m5253demo/flash.c index eeb9cfd3125..334518a4bc9 100644 --- a/board/freescale/m5253demo/flash.c +++ b/board/freescale/m5253demo/flash.c @@ -7,10 +7,11 @@ * TsiChung Liew (Tsi-Chung.Liew@freescale.com) */ -#include +#include #include #include #include +#include #include diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c index c1cff52fb3d..d0b01f81745 100644 --- a/board/freescale/m5253demo/m5253demo.c +++ b/board/freescale/m5253demo/m5253demo.c @@ -7,7 +7,7 @@ * Hayden Fraser (Hayden.Fraser@freescale.com) */ -#include +#include #include #include #include diff --git a/board/freescale/m5272c3/m5272c3.c b/board/freescale/m5272c3/m5272c3.c index 3c20a23385c..d1286badc61 100644 --- a/board/freescale/m5272c3/m5272c3.c +++ b/board/freescale/m5272c3/m5272c3.c @@ -6,7 +6,7 @@ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. */ -#include +#include #include #include #include diff --git a/board/freescale/m5275evb/m5275evb.c b/board/freescale/m5275evb/m5275evb.c index 00fa35ca5f7..e1d94fc9a3e 100644 --- a/board/freescale/m5275evb/m5275evb.c +++ b/board/freescale/m5275evb/m5275evb.c @@ -8,7 +8,7 @@ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. */ -#include +#include #include #include #include diff --git a/board/freescale/m5282evb/m5282evb.c b/board/freescale/m5282evb/m5282evb.c index 53e0f202101..81da6e2abd4 100644 --- a/board/freescale/m5282evb/m5282evb.c +++ b/board/freescale/m5282evb/m5282evb.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include diff --git a/board/freescale/m53017evb/m53017evb.c b/board/freescale/m53017evb/m53017evb.c index 76ebc0ab8dc..196d56dc17d 100644 --- a/board/freescale/m53017evb/m53017evb.c +++ b/board/freescale/m53017evb/m53017evb.c @@ -8,7 +8,6 @@ */ #include -#include #include #include #include diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c index b278dbfb485..26d5f3bf58c 100644 --- a/board/freescale/m5329evb/m5329evb.c +++ b/board/freescale/m5329evb/m5329evb.c @@ -8,7 +8,6 @@ */ #include -#include #include #include #include diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c index d921eef8b67..a250d61ef36 100644 --- a/board/freescale/m5329evb/nand.c +++ b/board/freescale/m5329evb/nand.c @@ -8,7 +8,6 @@ */ #include -#include #include #include diff --git a/board/freescale/m5373evb/m5373evb.c b/board/freescale/m5373evb/m5373evb.c index 0e9eec316c2..d6fdf41bab4 100644 --- a/board/freescale/m5373evb/m5373evb.c +++ b/board/freescale/m5373evb/m5373evb.c @@ -8,7 +8,6 @@ */ #include -#include #include #include #include diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c index 6d825a66e33..e7c08d22e6b 100644 --- a/board/freescale/m5373evb/nand.c +++ b/board/freescale/m5373evb/nand.c @@ -8,7 +8,6 @@ */ #include -#include #include #include diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index 97884a39796..55299745a3c 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -5,7 +5,7 @@ * Joe D'Abbraccio */ -#include +#include #include #include #include diff --git a/board/freescale/mpc8548cds/ddr.c b/board/freescale/mpc8548cds/ddr.c index b6c1847b141..14202cd5a78 100644 --- a/board/freescale/mpc8548cds/ddr.c +++ b/board/freescale/mpc8548cds/ddr.c @@ -3,7 +3,6 @@ * Copyright 2008 Freescale Semiconductor, Inc. */ -#include #include #include diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c index 7b6ef5b11c9..2334870fda0 100644 --- a/board/freescale/mpc8548cds/law.c +++ b/board/freescale/mpc8548cds/law.c @@ -6,7 +6,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index ec6e3a2d0ab..7810010fd04 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -5,7 +5,7 @@ * (C) Copyright 2002 Scott McNutt */ -#include +#include #include #include #include diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c index 994a32dd92a..0b2afa8054d 100644 --- a/board/freescale/mpc8548cds/tlb.c +++ b/board/freescale/mpc8548cds/tlb.c @@ -6,8 +6,9 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include +#include struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ diff --git a/board/freescale/mx23evk/mx23evk.c b/board/freescale/mx23evk/mx23evk.c index df4fb391255..fbc8fbdbf59 100644 --- a/board/freescale/mx23evk/mx23evk.c +++ b/board/freescale/mx23evk/mx23evk.c @@ -11,7 +11,6 @@ * on behalf of DENX Software Engineering GmbH */ -#include #include #include #include diff --git a/board/freescale/mx23evk/spl_boot.c b/board/freescale/mx23evk/spl_boot.c index 14e9b4a8634..a4c39a35221 100644 --- a/board/freescale/mx23evk/spl_boot.c +++ b/board/freescale/mx23evk/spl_boot.c @@ -6,7 +6,6 @@ * on behalf of DENX Software Engineering GmbH */ -#include #include #include #include diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c index cc0c8588544..b84b045bd1f 100644 --- a/board/freescale/mx28evk/iomux.c +++ b/board/freescale/mx28evk/iomux.c @@ -6,7 +6,6 @@ * on behalf of DENX Software Engineering GmbH */ -#include #include #include #include diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c index 88c3bf36089..ada572912da 100644 --- a/board/freescale/mx28evk/mx28evk.c +++ b/board/freescale/mx28evk/mx28evk.c @@ -11,7 +11,6 @@ * on behalf of DENX Software Engineering GmbH */ -#include #include #include #include diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 95edb359944..69456842302 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -3,7 +3,7 @@ * (C) Copyright 2009 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index d418cd8f4c0..2d8f5da9906 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -4,7 +4,7 @@ * Jason Liu */ -#include +#include #include #include #include diff --git a/board/freescale/mx6memcal/mx6memcal.c b/board/freescale/mx6memcal/mx6memcal.c index 0dfd7dec9ef..17095c34e92 100644 --- a/board/freescale/mx6memcal/mx6memcal.c +++ b/board/freescale/mx6memcal/mx6memcal.c @@ -7,7 +7,6 @@ * Author: Eric Nelson */ -#include #include #include #include diff --git a/board/freescale/mx6memcal/spl.c b/board/freescale/mx6memcal/spl.c index 61d0ca3408f..bc9c4259f07 100644 --- a/board/freescale/mx6memcal/spl.c +++ b/board/freescale/mx6memcal/spl.c @@ -4,7 +4,6 @@ * Author: Eric Nelson */ -#include #include #include #include diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c index 77e92006131..e782543c0fa 100644 --- a/board/freescale/mx6sabreauto/mx6sabreauto.c +++ b/board/freescale/mx6sabreauto/mx6sabreauto.c @@ -5,7 +5,6 @@ * Author: Fabio Estevam */ -#include #include #include #include diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index e9ac57118b0..d37d8a4136f 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/board/freescale/mx6sllevk/mx6sllevk.c b/board/freescale/mx6sllevk/mx6sllevk.c index 10a00095aff..7114444fc3e 100644 --- a/board/freescale/mx6sllevk/mx6sllevk.c +++ b/board/freescale/mx6sllevk/mx6sllevk.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c index 84cc51e9cac..6176f738238 100644 --- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c +++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index e7958df4024..e3353feec68 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index 534b16cec7a..6b0665a1067 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c index de45f8b1d24..189eddefea3 100644 --- a/board/freescale/mx6ullevk/mx6ullevk.c +++ b/board/freescale/mx6ullevk/mx6ullevk.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index 4fe23b51cd1..3db167c0dad 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include diff --git a/board/freescale/mx7ulp_evk/mx7ulp_evk.c b/board/freescale/mx7ulp_evk/mx7ulp_evk.c index 01e32136532..af68e57854e 100644 --- a/board/freescale/mx7ulp_evk/mx7ulp_evk.c +++ b/board/freescale/mx7ulp_evk/mx7ulp_evk.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c index b423ec8e218..43a0936bc9a 100644 --- a/board/freescale/p1010rdb/ddr.c +++ b/board/freescale/p1010rdb/ddr.c @@ -3,7 +3,6 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/board/freescale/p1010rdb/law.c b/board/freescale/p1010rdb/law.c index 13fc2fa2e38..a7d80f28521 100644 --- a/board/freescale/p1010rdb/law.c +++ b/board/freescale/p1010rdb/law.c @@ -3,7 +3,7 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include +#include #include #include diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index d32274b2481..ab0031440ae 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -4,7 +4,7 @@ * Copyright 2020 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c index e450f626e0a..fc26cef2cc8 100644 --- a/board/freescale/p1010rdb/spl.c +++ b/board/freescale/p1010rdb/spl.c @@ -2,7 +2,7 @@ /* Copyright 2013 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c index 8f0dec4c0ab..8cd79c6fb5f 100644 --- a/board/freescale/p1010rdb/spl_minimal.c +++ b/board/freescale/p1010rdb/spl_minimal.c @@ -2,7 +2,7 @@ /* * Copyright 2011 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c index 265cde81a3c..44acebaa2bb 100644 --- a/board/freescale/p1010rdb/tlb.c +++ b/board/freescale/p1010rdb/tlb.c @@ -3,8 +3,9 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include +#include #include +#include struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index 5f16779abaa..8622a5a610a 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -3,11 +3,12 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include +#include #include +#include #include #include -#include +#include #include #include #include diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c index 6085984eab4..49594070b83 100644 --- a/board/freescale/p1_p2_rdb_pc/law.c +++ b/board/freescale/p1_p2_rdb_pc/law.c @@ -3,7 +3,7 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include +#include #include #include diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 602b7f0156b..399ff720722 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -4,7 +4,7 @@ * Copyright 2020 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index 6c3f82849e3..b07f481fbf9 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -3,7 +3,7 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c index f9e0b5b25ab..511bcf5506b 100644 --- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c +++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c @@ -3,7 +3,7 @@ * Copyright 2011 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 94773969e9d..ae0b7adbe54 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -3,8 +3,9 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include +#include #include +#include struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ diff --git a/board/freescale/p2041rdb/cpld.c b/board/freescale/p2041rdb/cpld.c index a1908b8a571..915a8b994d5 100644 --- a/board/freescale/p2041rdb/cpld.c +++ b/board/freescale/p2041rdb/cpld.c @@ -11,7 +11,6 @@ * CPLD_BASE - The virtual address of the base of the CPLD register map */ -#include #include #include diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c index 910058cefe1..b8b765a85ef 100644 --- a/board/freescale/p2041rdb/ddr.c +++ b/board/freescale/p2041rdb/ddr.c @@ -3,7 +3,6 @@ * Copyright 2011 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c index c0d05539c5c..65850866777 100644 --- a/board/freescale/p2041rdb/eth.c +++ b/board/freescale/p2041rdb/eth.c @@ -12,7 +12,7 @@ * and serdes protocol selection. */ -#include +#include #include #include #include diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index 575259b19c0..d5b71f78430 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -3,7 +3,7 @@ * Copyright 2011,2012 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/t102xrdb/cpld.c b/board/freescale/t102xrdb/cpld.c index 17a6226cafc..cc933ccd544 100644 --- a/board/freescale/t102xrdb/cpld.c +++ b/board/freescale/t102xrdb/cpld.c @@ -7,7 +7,7 @@ * The following macros need to be defined: */ -#include +#include #include #include #include "cpld.h" diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c index 1b417398992..f8d504fb3c7 100644 --- a/board/freescale/t102xrdb/ddr.c +++ b/board/freescale/t102xrdb/ddr.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c index ad78f72f98c..7185a0abd52 100644 --- a/board/freescale/t102xrdb/eth_t102xrdb.c +++ b/board/freescale/t102xrdb/eth_t102xrdb.c @@ -5,7 +5,7 @@ * Shengzhou Liu */ -#include +#include #include #include #include diff --git a/board/freescale/t102xrdb/law.c b/board/freescale/t102xrdb/law.c index d636bef325f..81caa961897 100644 --- a/board/freescale/t102xrdb/law.c +++ b/board/freescale/t102xrdb/law.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include +#include #include #include diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c index 9faf259af74..de6cdda194e 100644 --- a/board/freescale/t102xrdb/spl.c +++ b/board/freescale/t102xrdb/spl.c @@ -2,7 +2,7 @@ /* Copyright 2014 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index 73f9d3ac72e..0a29e27b42c 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -4,7 +4,7 @@ * Copyright 2020-2023 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/t102xrdb/tlb.c b/board/freescale/t102xrdb/tlb.c index 2519a9e4dbe..008bd6e72b7 100644 --- a/board/freescale/t102xrdb/tlb.c +++ b/board/freescale/t102xrdb/tlb.c @@ -3,8 +3,9 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include +#include #include +#include struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c index 9ac57bbd830..c2d526ae15a 100644 --- a/board/freescale/t104xrdb/cpld.c +++ b/board/freescale/t104xrdb/cpld.c @@ -10,7 +10,7 @@ * CFG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map */ -#include +#include #include #include diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c index 02ddb661415..bab684860da 100644 --- a/board/freescale/t104xrdb/ddr.c +++ b/board/freescale/t104xrdb/ddr.c @@ -4,7 +4,7 @@ * Copyright 2021 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index 5eca9386f6e..d5c084e319d 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/t104xrdb/law.c b/board/freescale/t104xrdb/law.c index a0d6eb5b270..d34641c2397 100644 --- a/board/freescale/t104xrdb/law.c +++ b/board/freescale/t104xrdb/law.c @@ -3,7 +3,7 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ -#include +#include #include #include diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c index dd8283f3c60..e02a1f95d4c 100644 --- a/board/freescale/t104xrdb/spl.c +++ b/board/freescale/t104xrdb/spl.c @@ -2,7 +2,7 @@ /* Copyright 2013 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index b3080492716..ef4dfef4965 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -4,7 +4,7 @@ * Copyright 2023 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c index 10be580b813..24bc83f756b 100644 --- a/board/freescale/t104xrdb/tlb.c +++ b/board/freescale/t104xrdb/tlb.c @@ -3,8 +3,9 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ -#include +#include #include +#include struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c index 56471b3988b..9076fbba10a 100644 --- a/board/freescale/t208xqds/ddr.c +++ b/board/freescale/t208xqds/ddr.c @@ -3,7 +3,6 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index 569b193eab7..9f299227e29 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -6,7 +6,7 @@ * Shengzhou Liu */ -#include +#include #include #include #include diff --git a/board/freescale/t208xqds/law.c b/board/freescale/t208xqds/law.c index 3cdd4937684..287f4650e05 100644 --- a/board/freescale/t208xqds/law.c +++ b/board/freescale/t208xqds/law.c @@ -6,7 +6,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c index 8866be54a66..44ad4e68d9f 100644 --- a/board/freescale/t208xqds/spl.c +++ b/board/freescale/t208xqds/spl.c @@ -2,7 +2,7 @@ /* Copyright 2013 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c index 8be55e52e5f..5e71da0e163 100644 --- a/board/freescale/t208xqds/t208xqds.c +++ b/board/freescale/t208xqds/t208xqds.c @@ -4,7 +4,7 @@ * Copyright 2020 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c index 3d220afc16e..f99d51c8cd7 100644 --- a/board/freescale/t208xqds/tlb.c +++ b/board/freescale/t208xqds/tlb.c @@ -6,8 +6,9 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include +#include struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ diff --git a/board/freescale/t208xrdb/cpld.c b/board/freescale/t208xrdb/cpld.c index 933fa0decc3..d2226af6278 100644 --- a/board/freescale/t208xrdb/cpld.c +++ b/board/freescale/t208xrdb/cpld.c @@ -5,8 +5,9 @@ * Freescale T2080RDB board-specific CPLD controlling supports. */ -#include +#include #include +#include #include "cpld.h" u8 cpld_read(unsigned int reg) diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c index 1fbab36e1a2..fe98f62668a 100644 --- a/board/freescale/t208xrdb/ddr.c +++ b/board/freescale/t208xrdb/ddr.c @@ -3,7 +3,6 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/board/freescale/t208xrdb/eth_t208xrdb.c b/board/freescale/t208xrdb/eth_t208xrdb.c index e4592eac153..5223eccb280 100644 --- a/board/freescale/t208xrdb/eth_t208xrdb.c +++ b/board/freescale/t208xrdb/eth_t208xrdb.c @@ -6,7 +6,6 @@ * Shengzhou Liu */ -#include #include #include #include diff --git a/board/freescale/t208xrdb/law.c b/board/freescale/t208xrdb/law.c index 53a13694506..e1f570a8935 100644 --- a/board/freescale/t208xrdb/law.c +++ b/board/freescale/t208xrdb/law.c @@ -6,7 +6,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c index 130cb8847c0..df3b9c6fe40 100644 --- a/board/freescale/t208xrdb/spl.c +++ b/board/freescale/t208xrdb/spl.c @@ -2,7 +2,7 @@ /* Copyright 2013 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c index e33e5d082d8..d93edf007ad 100644 --- a/board/freescale/t208xrdb/t208xrdb.c +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -4,7 +4,7 @@ * Copyright 2021-2023 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c index 688a208c621..df5831541f3 100644 --- a/board/freescale/t208xrdb/tlb.c +++ b/board/freescale/t208xrdb/tlb.c @@ -6,8 +6,9 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include +#include struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c index 8b1012086ec..cd14d5895f5 100644 --- a/board/freescale/t4rdb/cpld.c +++ b/board/freescale/t4rdb/cpld.c @@ -14,7 +14,7 @@ * */ -#include +#include #include #include diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c index 57cbde154f0..5b60b50c672 100644 --- a/board/freescale/t4rdb/ddr.c +++ b/board/freescale/t4rdb/ddr.c @@ -3,7 +3,6 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c index 2e52543847b..e7646365d7d 100644 --- a/board/freescale/t4rdb/eth.c +++ b/board/freescale/t4rdb/eth.c @@ -5,7 +5,7 @@ * Chunhe Lan */ -#include +#include #include #include #include diff --git a/board/freescale/t4rdb/law.c b/board/freescale/t4rdb/law.c index 43eeb884e2f..c43ac0f30d7 100644 --- a/board/freescale/t4rdb/law.c +++ b/board/freescale/t4rdb/law.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include +#include #include #include diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c index 779457d2964..9d2472dec25 100644 --- a/board/freescale/t4rdb/spl.c +++ b/board/freescale/t4rdb/spl.c @@ -5,7 +5,7 @@ * Author: Chunhe Lan */ -#include +#include #include #include #include diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c index ab717769ed5..5cacfd27380 100644 --- a/board/freescale/t4rdb/t4240rdb.c +++ b/board/freescale/t4rdb/t4240rdb.c @@ -4,7 +4,7 @@ * Copyright 2023 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c index f5af893c2d9..1fb9d41d52b 100644 --- a/board/freescale/t4rdb/tlb.c +++ b/board/freescale/t4rdb/tlb.c @@ -3,8 +3,9 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include +#include #include +#include struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c index 98cb0140ad0..80a798af9cb 100644 --- a/board/freescale/vf610twr/vf610twr.c +++ b/board/freescale/vf610twr/vf610twr.c @@ -3,7 +3,6 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/board/friendlyarm/nanopi2/board.c b/board/friendlyarm/nanopi2/board.c index 393c5a447d6..c8cbc5a15fa 100644 --- a/board/friendlyarm/nanopi2/board.c +++ b/board/friendlyarm/nanopi2/board.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/board/friendlyarm/nanopi2/hwrev.c b/board/friendlyarm/nanopi2/hwrev.c index 585e08c944f..cd9c2414a32 100644 --- a/board/friendlyarm/nanopi2/hwrev.c +++ b/board/friendlyarm/nanopi2/hwrev.c @@ -5,7 +5,6 @@ */ #include -#include #include #include diff --git a/board/friendlyarm/nanopi2/lcds.c b/board/friendlyarm/nanopi2/lcds.c index 7303e53af92..b37367300cf 100644 --- a/board/friendlyarm/nanopi2/lcds.c +++ b/board/friendlyarm/nanopi2/lcds.c @@ -4,7 +4,6 @@ */ #include -#include #include #include #include diff --git a/board/friendlyarm/nanopi2/onewire.c b/board/friendlyarm/nanopi2/onewire.c index 4f0b1e33c2d..31cc871330c 100644 --- a/board/friendlyarm/nanopi2/onewire.c +++ b/board/friendlyarm/nanopi2/onewire.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/board/gardena/smart-gateway-at91sam/board.c b/board/gardena/smart-gateway-at91sam/board.c index d9dfb256b32..2b5b2844fbd 100644 --- a/board/gardena/smart-gateway-at91sam/board.c +++ b/board/gardena/smart-gateway-at91sam/board.c @@ -4,7 +4,7 @@ * Copyright (C) 2019 Stefan Roese */ -#include +#include #include #include #include diff --git a/board/gardena/smart-gateway-at91sam/spl.c b/board/gardena/smart-gateway-at91sam/spl.c index 2807c4e3114..fb3ec48f9c5 100644 --- a/board/gardena/smart-gateway-at91sam/spl.c +++ b/board/gardena/smart-gateway-at91sam/spl.c @@ -4,7 +4,7 @@ * Copyright (C) 2019 Stefan Roese */ -#include +#include #include #include #include diff --git a/board/gardena/smart-gateway-mt7688/board.c b/board/gardena/smart-gateway-mt7688/board.c index 0cfde91c94c..c6b14bed41f 100644 --- a/board/gardena/smart-gateway-mt7688/board.c +++ b/board/gardena/smart-gateway-mt7688/board.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Stefan Roese */ -#include #include #include #include diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c index 74328b2e1b3..891d1b5ddca 100644 --- a/board/gateworks/gw_ventana/common.c +++ b/board/gateworks/gw_ventana/common.c @@ -5,7 +5,6 @@ * Author: Tim Harvey */ -#include #include #include #include diff --git a/board/gateworks/gw_ventana/eeprom.c b/board/gateworks/gw_ventana/eeprom.c index e622a9ba9e4..b37f1972249 100644 --- a/board/gateworks/gw_ventana/eeprom.c +++ b/board/gateworks/gw_ventana/eeprom.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 683def7e9f7..21a908c20dd 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 2f046c9c0b3..3de4727b2ed 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -4,7 +4,7 @@ * Author: Tim Harvey */ -#include +#include #include #include #include diff --git a/board/gateworks/venice/eeprom.c b/board/gateworks/venice/eeprom.c index 241be4ee630..afaabf34879 100644 --- a/board/gateworks/venice/eeprom.c +++ b/board/gateworks/venice/eeprom.c @@ -3,7 +3,6 @@ * Copyright 2021 Gateworks Corporation */ -#include #include #include #include diff --git a/board/gateworks/venice/lpddr4_timing_imx8mm.c b/board/gateworks/venice/lpddr4_timing_imx8mm.c index 78b431dc284..3f2c090a94f 100644 --- a/board/gateworks/venice/lpddr4_timing_imx8mm.c +++ b/board/gateworks/venice/lpddr4_timing_imx8mm.c @@ -6,7 +6,6 @@ */ #include -#include #include #include diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index b0a315ba953..f10d310a46d 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -3,7 +3,6 @@ * Copyright 2021 Gateworks Corporation */ -#include #include #include #include diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c index 0f620c2d917..4abb3e45128 100644 --- a/board/gdsys/a38x/controlcenterdc.c +++ b/board/gdsys/a38x/controlcenterdc.c @@ -4,7 +4,7 @@ * Copyright (C) 2016 Mario Six */ -#include +#include #include #include #include diff --git a/board/gdsys/a38x/dt_helpers.c b/board/gdsys/a38x/dt_helpers.c index 61d30c2e637..a12e115c72c 100644 --- a/board/gdsys/a38x/dt_helpers.c +++ b/board/gdsys/a38x/dt_helpers.c @@ -4,7 +4,6 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ -#include #include #include #include diff --git a/board/gdsys/a38x/hre.c b/board/gdsys/a38x/hre.c index d16233ed78e..f303793b63b 100644 --- a/board/gdsys/a38x/hre.c +++ b/board/gdsys/a38x/hre.c @@ -4,7 +4,6 @@ * Reinhard Pfau, Guntermann & Drunck GmbH, reinhard.pfau@gdsys.cc */ -#include #include #include #include diff --git a/board/gdsys/a38x/hydra.c b/board/gdsys/a38x/hydra.c index 495a9769188..970d508ff32 100644 --- a/board/gdsys/a38x/hydra.c +++ b/board/gdsys/a38x/hydra.c @@ -1,8 +1,8 @@ -#include #include #include /* ctrlc */ #include #include +#include #include "hydra.h" diff --git a/board/gdsys/a38x/ihs_phys.c b/board/gdsys/a38x/ihs_phys.c index 60a5c37aeff..690a29690b9 100644 --- a/board/gdsys/a38x/ihs_phys.c +++ b/board/gdsys/a38x/ihs_phys.c @@ -1,4 +1,3 @@ -#include #include #include #include diff --git a/board/gdsys/a38x/keyprogram.c b/board/gdsys/a38x/keyprogram.c index 7020fae1894..15c36e22684 100644 --- a/board/gdsys/a38x/keyprogram.c +++ b/board/gdsys/a38x/keyprogram.c @@ -4,7 +4,6 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ -#include #include #include #include diff --git a/board/gdsys/common/cmd_ioloop.c b/board/gdsys/common/cmd_ioloop.c index 1412421a021..fb6313f0197 100644 --- a/board/gdsys/common/cmd_ioloop.c +++ b/board/gdsys/common/cmd_ioloop.c @@ -4,7 +4,6 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */ -#include #include #include #include diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c index 9ca69ebcbbe..7698e76b524 100644 --- a/board/gdsys/common/dp501.c +++ b/board/gdsys/common/dp501.c @@ -8,7 +8,6 @@ #ifdef CONFIG_GDSYS_LEGACY_DRIVERS -#include #include #include #include diff --git a/board/gdsys/common/ihs_mdio.c b/board/gdsys/common/ihs_mdio.c index 5f1215e9e8a..a814566beaf 100644 --- a/board/gdsys/common/ihs_mdio.c +++ b/board/gdsys/common/ihs_mdio.c @@ -4,7 +4,6 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */ -#include #include #include diff --git a/board/gdsys/common/ioep-fpga.c b/board/gdsys/common/ioep-fpga.c index 7292d7ab5a4..f01b48b5c8e 100644 --- a/board/gdsys/common/ioep-fpga.c +++ b/board/gdsys/common/ioep-fpga.c @@ -6,7 +6,6 @@ #ifdef CONFIG_GDSYS_LEGACY_DRIVERS -#include #include #include diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c index dc548efbc7a..bd9c5ca9969 100644 --- a/board/gdsys/common/osd.c +++ b/board/gdsys/common/osd.c @@ -6,7 +6,6 @@ #ifdef CONFIG_GDSYS_LEGACY_DRIVERS -#include #include #include #include diff --git a/board/gdsys/common/osd_cmd.c b/board/gdsys/common/osd_cmd.c index 6a9c0b4c24f..39e64f5f2eb 100644 --- a/board/gdsys/common/osd_cmd.c +++ b/board/gdsys/common/osd_cmd.c @@ -9,7 +9,6 @@ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de */ -#include #include #include #include diff --git a/board/gdsys/mpc8308/gazerbeam.c b/board/gdsys/mpc8308/gazerbeam.c index cc608c4ac43..05e4d84460a 100644 --- a/board/gdsys/mpc8308/gazerbeam.c +++ b/board/gdsys/mpc8308/gazerbeam.c @@ -5,7 +5,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include #include #include #include diff --git a/board/gdsys/mpc8308/mpc8308.c b/board/gdsys/mpc8308/mpc8308.c index 0f90f8ad327..42c45ecedce 100644 --- a/board/gdsys/mpc8308/mpc8308.c +++ b/board/gdsys/mpc8308/mpc8308.c @@ -4,7 +4,6 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */ -#include #include #include #include diff --git a/board/gdsys/mpc8308/sdram.c b/board/gdsys/mpc8308/sdram.c index 4fac146353d..2933de0f304 100644 --- a/board/gdsys/mpc8308/sdram.c +++ b/board/gdsys/mpc8308/sdram.c @@ -13,7 +13,7 @@ #ifndef CONFIG_MPC83XX_SDRAM -#include +#include #include #include #include diff --git a/board/ge/b1x5v2/b1x5v2.c b/board/ge/b1x5v2/b1x5v2.c index a2cbd1512e9..031773bc5ef 100644 --- a/board/ge/b1x5v2/b1x5v2.c +++ b/board/ge/b1x5v2/b1x5v2.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/board/ge/common/ge_rtc.c b/board/ge/common/ge_rtc.c index 6437afc7bd0..5c62ecca8c8 100644 --- a/board/ge/common/ge_rtc.c +++ b/board/ge/common/ge_rtc.c @@ -3,7 +3,6 @@ * Copyright 2017 General Electric Company */ -#include #include #include #include diff --git a/board/ge/common/vpd_reader.h b/board/ge/common/vpd_reader.h index 0c51dc57e90..d32c18da351 100644 --- a/board/ge/common/vpd_reader.h +++ b/board/ge/common/vpd_reader.h @@ -3,7 +3,7 @@ * Copyright 2016 General Electric Company */ -#include "common.h" +#include struct vpd_cache; diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c index cc462d53da6..9396d43f8ad 100644 --- a/board/ge/mx53ppd/mx53ppd.c +++ b/board/ge/mx53ppd/mx53ppd.c @@ -8,7 +8,6 @@ * Jason Liu */ -#include #include #include #include diff --git a/board/ge/mx53ppd/mx53ppd_video.c b/board/ge/mx53ppd/mx53ppd_video.c index 4e2c6ebde73..eb4dd758b3b 100644 --- a/board/ge/mx53ppd/mx53ppd_video.c +++ b/board/ge/mx53ppd/mx53ppd_video.c @@ -8,7 +8,6 @@ * Fabio Estevam */ -#include #include #include #include diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c index 9d9168d608a..7b2724c01d0 100644 --- a/board/google/chromebook_coral/coral.c +++ b/board/google/chromebook_coral/coral.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_SYSINFO -#include #include #include #include diff --git a/board/google/imx8mq_phanbell/imx8mq_phanbell.c b/board/google/imx8mq_phanbell/imx8mq_phanbell.c index d0a740dd3f4..9544d6dd19a 100644 --- a/board/google/imx8mq_phanbell/imx8mq_phanbell.c +++ b/board/google/imx8mq_phanbell/imx8mq_phanbell.c @@ -3,7 +3,6 @@ * Copyright 2020 NXP */ -#include #include #include #include diff --git a/board/google/imx8mq_phanbell/spl.c b/board/google/imx8mq_phanbell/spl.c index 83de5bfd75f..cfba9300dcb 100644 --- a/board/google/imx8mq_phanbell/spl.c +++ b/board/google/imx8mq_phanbell/spl.c @@ -4,7 +4,7 @@ * */ -#include +#include #include #include #include diff --git a/board/google/veyron/veyron.c b/board/google/veyron/veyron.c index 32dbcdc4d10..53c3435c92f 100644 --- a/board/google/veyron/veyron.c +++ b/board/google/veyron/veyron.c @@ -4,7 +4,6 @@ */ #include -#include #include #include #include diff --git a/board/grinn/chiliboard/board.c b/board/grinn/chiliboard/board.c index 64b32ca96df..8313b37655f 100644 --- a/board/grinn/chiliboard/board.c +++ b/board/grinn/chiliboard/board.c @@ -4,7 +4,7 @@ * Copyright (C) 2017, Grinn - http://grinn-global.com/ */ -#include +#include #include #include #include diff --git a/board/grinn/liteboard/board.c b/board/grinn/liteboard/board.c index cf1d7cee925..07bb5b7d797 100644 --- a/board/grinn/liteboard/board.c +++ b/board/grinn/liteboard/board.c @@ -4,7 +4,6 @@ * Copyright (C) 2016 Grinn */ -#include #include #include #include diff --git a/board/highbank/ahci.c b/board/highbank/ahci.c index 9c057278ace..899c502dfbc 100644 --- a/board/highbank/ahci.c +++ b/board/highbank/ahci.c @@ -3,7 +3,6 @@ * Copyright 2012 Calxeda, Inc. */ -#include #include #include #include diff --git a/board/highbank/hb_sregs.c b/board/highbank/hb_sregs.c index d9dd2c2bf67..94052f7a3f9 100644 --- a/board/highbank/hb_sregs.c +++ b/board/highbank/hb_sregs.c @@ -10,7 +10,6 @@ * Copyright (C) 2019 Arm Ltd. */ -#include #include #include diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index 7f67d1e4530..f3df83ed6c9 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -3,7 +3,6 @@ * Copyright 2010-2011 Calxeda, Inc. */ -#include #include #include #include diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c index c9a2d60ee56..95a831efcaf 100644 --- a/board/hisilicon/hikey/hikey.c +++ b/board/hisilicon/hikey/hikey.c @@ -3,7 +3,6 @@ * (C) Copyright 2015 Linaro * Peter Griffin */ -#include #include #include #include diff --git a/board/hisilicon/hikey960/hikey960.c b/board/hisilicon/hikey960/hikey960.c index f41fabbad09..5029f4edb2a 100644 --- a/board/hisilicon/hikey960/hikey960.c +++ b/board/hisilicon/hikey960/hikey960.c @@ -4,7 +4,6 @@ * Author: Manivannan Sadhasivam */ -#include #include #include #include diff --git a/board/hisilicon/poplar/poplar.c b/board/hisilicon/poplar/poplar.c index b89e7e86976..c3ea080ff75 100644 --- a/board/hisilicon/poplar/poplar.c +++ b/board/hisilicon/poplar/poplar.c @@ -4,7 +4,6 @@ * Jorge Ramirez-Ortiz */ -#include #include #include #include diff --git a/board/hoperun/hihope-rzg2/hihope-rzg2.c b/board/hoperun/hihope-rzg2/hihope-rzg2.c index 68d3d300dc4..0966e257464 100644 --- a/board/hoperun/hihope-rzg2/hihope-rzg2.c +++ b/board/hoperun/hihope-rzg2/hihope-rzg2.c @@ -6,7 +6,6 @@ * Copyright (C) 2021 Renesas Electronics Corporation */ -#include #include #include #include diff --git a/board/imgtec/boston/checkboard.c b/board/imgtec/boston/checkboard.c index c246a7b9d45..b0f7d3243c5 100644 --- a/board/imgtec/boston/checkboard.c +++ b/board/imgtec/boston/checkboard.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Imagination Technologies */ -#include #include #include diff --git a/board/imgtec/boston/ddr.c b/board/imgtec/boston/ddr.c index cecf454011c..55356d1175d 100644 --- a/board/imgtec/boston/ddr.c +++ b/board/imgtec/boston/ddr.c @@ -3,7 +3,7 @@ * Copyright (C) 2016 Imagination Technologies */ -#include +#include #include #include diff --git a/board/imgtec/boston/dt.c b/board/imgtec/boston/dt.c index bf772ff5dec..874a21cec61 100644 --- a/board/imgtec/boston/dt.c +++ b/board/imgtec/boston/dt.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Imagination Technologies */ -#include #include #include diff --git a/board/imgtec/ci20/ci20.c b/board/imgtec/ci20/ci20.c index 89f5e7ad792..4e268381d3c 100644 --- a/board/imgtec/ci20/ci20.c +++ b/board/imgtec/ci20/ci20.c @@ -6,7 +6,6 @@ * Author: Paul Burton */ -#include #include #include #include diff --git a/board/imgtec/malta/superio.c b/board/imgtec/malta/superio.c index aba11e25be3..edd5c203b16 100644 --- a/board/imgtec/malta/superio.c +++ b/board/imgtec/malta/superio.c @@ -6,7 +6,6 @@ * Setup code for the FDC37M817 super I/O controller */ -#include #include #define SIO_CONF_PORT 0x3f0 diff --git a/board/imgtec/xilfpga/xilfpga.c b/board/imgtec/xilfpga/xilfpga.c index 71226927211..e50ee8efe55 100644 --- a/board/imgtec/xilfpga/xilfpga.c +++ b/board/imgtec/xilfpga/xilfpga.c @@ -8,7 +8,7 @@ * */ -#include +#include #include #include diff --git a/board/intel/cherryhill/cherryhill.c b/board/intel/cherryhill/cherryhill.c index c037d5b14cd..b4378afee15 100644 --- a/board/intel/cherryhill/cherryhill.c +++ b/board/intel/cherryhill/cherryhill.c @@ -3,7 +3,6 @@ * Copyright (C) 2017, Bin Meng */ -#include #include #include diff --git a/board/intel/cougarcanyon2/cougarcanyon2.c b/board/intel/cougarcanyon2/cougarcanyon2.c index 7f61ef8b366..e5cda068e17 100644 --- a/board/intel/cougarcanyon2/cougarcanyon2.c +++ b/board/intel/cougarcanyon2/cougarcanyon2.c @@ -3,7 +3,6 @@ * Copyright (C) 2016, Bin Meng */ -#include #include #include #include diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c index 55095deeadd..036beb1146d 100644 --- a/board/intel/crownbay/crownbay.c +++ b/board/intel/crownbay/crownbay.c @@ -3,7 +3,6 @@ * Copyright (C) 2014, Bin Meng */ -#include #include #include #include diff --git a/board/intel/edison/edison.c b/board/intel/edison/edison.c index 11e7f74e47c..911ffda2fc7 100644 --- a/board/intel/edison/edison.c +++ b/board/intel/edison/edison.c @@ -2,7 +2,6 @@ /* * Copyright (c) 2017 Intel Corporation */ -#include #include #include #include diff --git a/board/intel/galileo/galileo.c b/board/intel/galileo/galileo.c index 341b627a65f..19e5d0952fb 100644 --- a/board/intel/galileo/galileo.c +++ b/board/intel/galileo/galileo.c @@ -3,7 +3,6 @@ * Copyright (C) 2015, Bin Meng */ -#include #include #include #include diff --git a/board/intel/minnowmax/minnowmax.c b/board/intel/minnowmax/minnowmax.c index b02e3f0d4e5..cdc2e0b75d8 100644 --- a/board/intel/minnowmax/minnowmax.c +++ b/board/intel/minnowmax/minnowmax.c @@ -3,7 +3,6 @@ * Copyright (C) 2015, Google, Inc */ -#include #include #include #include diff --git a/board/intel/slimbootloader/slimbootloader.c b/board/intel/slimbootloader/slimbootloader.c index b20ddf0c682..f92c0b5112f 100644 --- a/board/intel/slimbootloader/slimbootloader.c +++ b/board/intel/slimbootloader/slimbootloader.c @@ -3,7 +3,6 @@ * Copyright (C) 2019 Intel Corporation */ -#include #include int board_early_init_r(void) diff --git a/board/inversepath/usbarmory/usbarmory.c b/board/inversepath/usbarmory/usbarmory.c index f3a0de3967b..fbed8abcecf 100644 --- a/board/inversepath/usbarmory/usbarmory.c +++ b/board/inversepath/usbarmory/usbarmory.c @@ -7,7 +7,7 @@ * Andrej Rosano */ -#include +#include #include #include #include diff --git a/board/iomega/iconnect/iconnect.c b/board/iomega/iconnect/iconnect.c index 03871602001..00b08987e9e 100644 --- a/board/iomega/iconnect/iconnect.c +++ b/board/iomega/iconnect/iconnect.c @@ -6,7 +6,6 @@ * Luka Perkov */ -#include #include #include #include diff --git a/board/isee/igep003x/board.c b/board/isee/igep003x/board.c index 7dbb0800892..7cd26ce3c34 100644 --- a/board/isee/igep003x/board.c +++ b/board/isee/igep003x/board.c @@ -5,7 +5,7 @@ * Copyright (C) 2013-2017, ISEE 2007 SL - http://www.isee.biz/ */ -#include +#include #include #include #include diff --git a/board/isee/igep003x/mux.c b/board/isee/igep003x/mux.c index 550e3b3197d..1a40c007762 100644 --- a/board/isee/igep003x/mux.c +++ b/board/isee/igep003x/mux.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/board/isee/igep00x0/common.c b/board/isee/igep00x0/common.c index 3fdf83e845c..2584d2e5ddf 100644 --- a/board/isee/igep00x0/common.c +++ b/board/isee/igep00x0/common.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 0f0a9c592fc..8a3f290f678 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -3,7 +3,7 @@ * (C) Copyright 2010 * ISEE 2007 SL, */ -#include +#include #include #include #include diff --git a/board/k+p/kp_imx53/kp_id_rev.c b/board/k+p/kp_imx53/kp_id_rev.c index 9f93cf008ce..cbfe94e25a2 100644 --- a/board/k+p/kp_imx53/kp_id_rev.c +++ b/board/k+p/kp_imx53/kp_id_rev.c @@ -9,11 +9,11 @@ * Daniel Gericke */ -#include #include #include #include "kp_id_rev.h" #include +#include static int eeprom_has_been_read; static struct id_eeprom eeprom; diff --git a/board/k+p/kp_imx53/kp_imx53.c b/board/k+p/kp_imx53/kp_imx53.c index 7c3a695cb25..efb7b49cbe0 100644 --- a/board/k+p/kp_imx53/kp_imx53.c +++ b/board/k+p/kp_imx53/kp_imx53.c @@ -4,7 +4,6 @@ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de */ -#include #include #include #include diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c index e6877e4c070..e0895194300 100644 --- a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c +++ b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c @@ -5,7 +5,6 @@ * Copyright (C) 2018 Lukasz Majewski */ -#include #include #include #include diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c index 54902437940..6a5e252751d 100644 --- a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c +++ b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c @@ -5,7 +5,6 @@ * Copyright (C) 2018 Lukasz Majewski */ -#include #include #include #include diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index 991022ac833..9358c25dcb0 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -7,7 +7,7 @@ * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com */ -#include +#include #include #include #include diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c index 67db0c50f47..f01fe44303c 100644 --- a/board/keymile/common/ivm.c +++ b/board/keymile/common/ivm.c @@ -4,10 +4,11 @@ * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com */ -#include #include #include #include +#include +#include #include "common.h" #define MAC_STR_SZ 20 diff --git a/board/keymile/common/qrio.c b/board/keymile/common/qrio.c index b433f69675a..c8299483299 100644 --- a/board/keymile/common/qrio.c +++ b/board/keymile/common/qrio.c @@ -4,7 +4,7 @@ * Valentin Longchamp */ -#include +#include #include #include diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index acd13105dd5..40718aa58a7 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -13,7 +13,7 @@ * Heiko Schocher, DENX Software Engineering, hs@denx.de. */ -#include +#include #include #include #include diff --git a/board/keymile/kmcent2/tlb.c b/board/keymile/kmcent2/tlb.c index 41b24e39433..77e11e9bc1e 100644 --- a/board/keymile/kmcent2/tlb.c +++ b/board/keymile/kmcent2/tlb.c @@ -7,7 +7,7 @@ */ #include -#include +#include struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ diff --git a/board/keymile/pg-wcom-ls102xa/ddr.c b/board/keymile/pg-wcom-ls102xa/ddr.c index 556d39d4d4e..51938a1b4d8 100644 --- a/board/keymile/pg-wcom-ls102xa/ddr.c +++ b/board/keymile/pg-wcom-ls102xa/ddr.c @@ -4,7 +4,7 @@ * Copyright 2020 Hitachi Power Grids. All rights reserved. */ -#include +#include #include #include #include diff --git a/board/keymile/secu1/socfpga.c b/board/keymile/secu1/socfpga.c index 6a4cb21786a..1a626c52068 100644 --- a/board/keymile/secu1/socfpga.c +++ b/board/keymile/secu1/socfpga.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2017-2020 Hitachi Power Grids */ -#include #include #include diff --git a/board/kobol/helios4/helios4.c b/board/kobol/helios4/helios4.c index 9c5b687b3e8..4c8407bb676 100644 --- a/board/kobol/helios4/helios4.c +++ b/board/kobol/helios4/helios4.c @@ -4,7 +4,7 @@ * based on board/solidrun/clearfog/clearfog.c */ -#include +#include #include #include #include diff --git a/board/kontron/pitx_imx8m/pitx_imx8m.c b/board/kontron/pitx_imx8m/pitx_imx8m.c index 4548e7c1dff..a908aee9ecc 100644 --- a/board/kontron/pitx_imx8m/pitx_imx8m.c +++ b/board/kontron/pitx_imx8m/pitx_imx8m.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ #include "pitx_misc.h" -#include #include #include #include diff --git a/board/kontron/pitx_imx8m/spl.c b/board/kontron/pitx_imx8m/spl.c index a247803a4b4..475e52f6231 100644 --- a/board/kontron/pitx_imx8m/spl.c +++ b/board/kontron/pitx_imx8m/spl.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ -#include +#include #include #include #include diff --git a/board/kontron/sl-mx8mm/lpddr4_timing.c b/board/kontron/sl-mx8mm/lpddr4_timing.c index 74b79c7a009..851aeef8f8c 100644 --- a/board/kontron/sl-mx8mm/lpddr4_timing.c +++ b/board/kontron/sl-mx8mm/lpddr4_timing.c @@ -4,7 +4,6 @@ */ #include -#include #include #include diff --git a/board/kontron/sl28/cmds.c b/board/kontron/sl28/cmds.c index 08a22b5d01e..7851361c48c 100644 --- a/board/kontron/sl28/cmds.c +++ b/board/kontron/sl28/cmds.c @@ -5,10 +5,11 @@ * Copyright (c) 2020 Kontron Europe GmbH */ -#include #include #include +#include #include +#include #define CPLD_I2C_ADDR 0x4a #define REG_UFM_CTRL 0x02 diff --git a/board/kontron/sl28/common.c b/board/kontron/sl28/common.c index 331de29baee..d8d0172a21b 100644 --- a/board/kontron/sl28/common.c +++ b/board/kontron/sl28/common.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ -#include +#include #include #include diff --git a/board/kontron/sl28/ddr.c b/board/kontron/sl28/ddr.c index 315d9f99c71..9b881fdc265 100644 --- a/board/kontron/sl28/ddr.c +++ b/board/kontron/sl28/ddr.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ -#include +#include #include #include #include diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c index 4ab221c12bf..adfec8ba237 100644 --- a/board/kontron/sl28/sl28.c +++ b/board/kontron/sl28/sl28.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/board/kontron/sl28/spl.c b/board/kontron/sl28/spl.c index 80acde74956..45a4fc65120 100644 --- a/board/kontron/sl28/spl.c +++ b/board/kontron/sl28/spl.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ -#include +#include #include #include #include diff --git a/board/kontron/sl28/spl_atf.c b/board/kontron/sl28/spl_atf.c index a9cd6850e98..0710316a48b 100644 --- a/board/kontron/sl28/spl_atf.c +++ b/board/kontron/sl28/spl_atf.c @@ -5,7 +5,7 @@ * Copyright (c) 2020 Michael Walle */ -#include +#include #include #include #include diff --git a/board/kosagi/novena/novena.c b/board/kosagi/novena/novena.c index f009a8afd48..3220727f236 100644 --- a/board/kosagi/novena/novena.c +++ b/board/kosagi/novena/novena.c @@ -5,7 +5,6 @@ * Copyright (C) 2014 Marek Vasut */ -#include #include #include #include diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c index 24c0fb22268..008418b0184 100644 --- a/board/kosagi/novena/novena_spl.c +++ b/board/kosagi/novena/novena_spl.c @@ -5,7 +5,7 @@ * Copyright (C) 2014 Marek Vasut */ -#include +#include #include #include #include diff --git a/board/kosagi/novena/video.c b/board/kosagi/novena/video.c index a96a877f5f2..be5a737a31d 100644 --- a/board/kosagi/novena/video.c +++ b/board/kosagi/novena/video.c @@ -9,7 +9,6 @@ * Copyright (C) 2014 Marek Vasut */ -#include #include #include #include diff --git a/board/l+g/vinco/vinco.c b/board/l+g/vinco/vinco.c index b3c176dd59a..066d315baa2 100644 --- a/board/l+g/vinco/vinco.c +++ b/board/l+g/vinco/vinco.c @@ -9,7 +9,7 @@ * Gregory CLEMENT */ -#include +#include #include #include #include diff --git a/board/lego/ev3/legoev3.c b/board/lego/ev3/legoev3.c index 43afe593c78..1a153668a43 100644 --- a/board/lego/ev3/legoev3.c +++ b/board/lego/ev3/legoev3.c @@ -12,7 +12,7 @@ * Copyright (C) 2007 Sergey Kubushyn */ -#include +#include #include #include #include diff --git a/board/lg/sniper/sniper.c b/board/lg/sniper/sniper.c index 86032d7fcdf..88d5d088143 100644 --- a/board/lg/sniper/sniper.c +++ b/board/lg/sniper/sniper.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/board/liebherr/display5/display5.c b/board/liebherr/display5/display5.c index e3a59dbec00..a0bbd03e8d1 100644 --- a/board/liebherr/display5/display5.c +++ b/board/liebherr/display5/display5.c @@ -4,7 +4,6 @@ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de */ -#include #include #include #include diff --git a/board/liebherr/display5/spl.c b/board/liebherr/display5/spl.c index 97928e92215..819d3acbe56 100644 --- a/board/liebherr/display5/spl.c +++ b/board/liebherr/display5/spl.c @@ -4,7 +4,6 @@ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de */ -#include #include #include #include diff --git a/board/liebherr/mccmon6/mccmon6.c b/board/liebherr/mccmon6/mccmon6.c index 1b49526fba4..fef915b2aca 100644 --- a/board/liebherr/mccmon6/mccmon6.c +++ b/board/liebherr/mccmon6/mccmon6.c @@ -4,7 +4,6 @@ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de */ -#include #include #include #include diff --git a/board/liebherr/xea/spl_xea.c b/board/liebherr/xea/spl_xea.c index 6cf8f8390e8..88c157eca45 100644 --- a/board/liebherr/xea/spl_xea.c +++ b/board/liebherr/xea/spl_xea.c @@ -12,7 +12,6 @@ * on behalf of DENX Software Engineering GmbH */ -#include #include #include #include diff --git a/board/liebherr/xea/xea.c b/board/liebherr/xea/xea.c index 0a6fd7f1437..9ade3563b25 100644 --- a/board/liebherr/xea/xea.c +++ b/board/liebherr/xea/xea.c @@ -13,7 +13,6 @@ * */ -#include #include #include #include diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index e69a73f2af6..e6ca31016b7 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -10,7 +10,6 @@ * Texas Instruments Incorporated - https://www.ti.com/ */ -#include #include #include #include diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c index 0d53548dcb4..589136fd64a 100644 --- a/board/logicpd/imx6/imx6logic.c +++ b/board/logicpd/imx6/imx6logic.c @@ -8,7 +8,6 @@ * and updates by Jagan Teki */ -#include #include #include #include diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index 86992829caf..a9fe61918b6 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -10,7 +10,7 @@ * Richard Woodruff * Syed Mohammed Khasim */ -#include +#include #include #include #include diff --git a/board/maxbcm/maxbcm.c b/board/maxbcm/maxbcm.c index aad3dc86429..e011520f2ec 100644 --- a/board/maxbcm/maxbcm.c +++ b/board/maxbcm/maxbcm.c @@ -3,7 +3,6 @@ * Copyright (C) 2014 Stefan Roese */ -#include #include #include #include diff --git a/board/mediatek/mt7622/mt7622_rfb.c b/board/mediatek/mt7622/mt7622_rfb.c index 2cc73bc35dc..e7f492a13bc 100644 --- a/board/mediatek/mt7622/mt7622_rfb.c +++ b/board/mediatek/mt7622/mt7622_rfb.c @@ -4,7 +4,6 @@ * Author: Sam Shih */ -#include #include #include #include diff --git a/board/mediatek/mt7623/mt7623_rfb.c b/board/mediatek/mt7623/mt7623_rfb.c index ec10f77c51e..c78eaa07243 100644 --- a/board/mediatek/mt7623/mt7623_rfb.c +++ b/board/mediatek/mt7623/mt7623_rfb.c @@ -3,7 +3,7 @@ * Copyright (C) 2018 MediaTek Inc. */ -#include +#include #include #include diff --git a/board/mediatek/mt7629/mt7629_rfb.c b/board/mediatek/mt7629/mt7629_rfb.c index 55f7696c510..02719181624 100644 --- a/board/mediatek/mt7629/mt7629_rfb.c +++ b/board/mediatek/mt7629/mt7629_rfb.c @@ -3,7 +3,7 @@ * Copyright (C) 2018 MediaTek Inc. */ -#include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/mediatek/mt8183/mt8183_pumpkin.c b/board/mediatek/mt8183/mt8183_pumpkin.c index db613ebdc4f..1b8736966f6 100644 --- a/board/mediatek/mt8183/mt8183_pumpkin.c +++ b/board/mediatek/mt8183/mt8183_pumpkin.c @@ -4,7 +4,6 @@ * Author: Fabien Parent */ -#include #include #include diff --git a/board/mediatek/mt8512/mt8512.c b/board/mediatek/mt8512/mt8512.c index ac3adb80122..d2f557ffee5 100644 --- a/board/mediatek/mt8512/mt8512.c +++ b/board/mediatek/mt8512/mt8512.c @@ -3,7 +3,6 @@ * Copyright (C) 2019 MediaTek Inc. */ -#include #include #include #include diff --git a/board/mediatek/mt8516/mt8516_pumpkin.c b/board/mediatek/mt8516/mt8516_pumpkin.c index 42f3863b92c..930bfec3483 100644 --- a/board/mediatek/mt8516/mt8516_pumpkin.c +++ b/board/mediatek/mt8516/mt8516_pumpkin.c @@ -3,7 +3,6 @@ * Copyright (C) 2019 BayLibre SAS */ -#include #include #include diff --git a/board/mediatek/mt8518/mt8518_ap1.c b/board/mediatek/mt8518/mt8518_ap1.c index e03da63b1d9..745cfda2ddf 100644 --- a/board/mediatek/mt8518/mt8518_ap1.c +++ b/board/mediatek/mt8518/mt8518_ap1.c @@ -3,7 +3,7 @@ * Copyright (C) 2019 MediaTek Inc. */ -#include +#include #include #include #include diff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c index b8dffb0e485..79351f47273 100644 --- a/board/menlo/m53menlo/m53menlo.c +++ b/board/menlo/m53menlo/m53menlo.c @@ -6,7 +6,6 @@ * Copyright (C) 2014-2017 Olaf Mandel */ -#include #include #include #include diff --git a/board/menlo/mx8menlo/mx8menlo.c b/board/menlo/mx8menlo/mx8menlo.c index 18f5fd5c5ee..f47b45c1d56 100644 --- a/board/menlo/mx8menlo/mx8menlo.c +++ b/board/menlo/mx8menlo/mx8menlo.c @@ -3,7 +3,6 @@ * Copyright 2021-2022 Marek Vasut */ -#include #include #include #include diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c b/board/microchip/mpfs_icicle/mpfs_icicle.c index 0f5f82924e7..7beac33cfbd 100644 --- a/board/microchip/mpfs_icicle/mpfs_icicle.c +++ b/board/microchip/mpfs_icicle/mpfs_icicle.c @@ -4,7 +4,6 @@ * Padmarao Begari */ -#include #include #include #include diff --git a/board/microchip/pic32mzda/pic32mzda.c b/board/microchip/pic32mzda/pic32mzda.c index 3c2203d2202..848a1aee400 100644 --- a/board/microchip/pic32mzda/pic32mzda.c +++ b/board/microchip/pic32mzda/pic32mzda.c @@ -7,7 +7,6 @@ * */ -#include #include #include #include diff --git a/board/mikrotik/crs3xx-98dx3236/crs3xx-98dx3236.c b/board/mikrotik/crs3xx-98dx3236/crs3xx-98dx3236.c index 315169ba661..ae1c586277f 100644 --- a/board/mikrotik/crs3xx-98dx3236/crs3xx-98dx3236.c +++ b/board/mikrotik/crs3xx-98dx3236/crs3xx-98dx3236.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Stefan Roese */ -#include #include #include #include diff --git a/board/mntre/imx8mq_reform2/imx8mq_reform2.c b/board/mntre/imx8mq_reform2/imx8mq_reform2.c index be5c5060a2a..ebc490e24b1 100644 --- a/board/mntre/imx8mq_reform2/imx8mq_reform2.c +++ b/board/mntre/imx8mq_reform2/imx8mq_reform2.c @@ -4,7 +4,6 @@ * Copyright (C) 2018, Boundary Devices */ -#include #include #include #include diff --git a/board/mntre/imx8mq_reform2/spl.c b/board/mntre/imx8mq_reform2/spl.c index 5120c628b91..48a783593b6 100644 --- a/board/mntre/imx8mq_reform2/spl.c +++ b/board/mntre/imx8mq_reform2/spl.c @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include +#include #include #include #include diff --git a/board/msc/sm2s_imx8mp/sm2s_imx8mp.c b/board/msc/sm2s_imx8mp/sm2s_imx8mp.c index 6ccbf02db06..b1ce014bd55 100644 --- a/board/msc/sm2s_imx8mp/sm2s_imx8mp.c +++ b/board/msc/sm2s_imx8mp/sm2s_imx8mp.c @@ -7,7 +7,6 @@ * Copyright 2021 Collabora Ltd. */ -#include #include #include #include diff --git a/board/msc/sm2s_imx8mp/spl.c b/board/msc/sm2s_imx8mp/spl.c index ed7a1b7d3d0..b1b5561838d 100644 --- a/board/msc/sm2s_imx8mp/spl.c +++ b/board/msc/sm2s_imx8mp/spl.c @@ -7,7 +7,7 @@ * Copyright 2021 Collabora Ltd. */ -#include +#include #include #include #include diff --git a/board/mscc/common/spi.c b/board/mscc/common/spi.c index 45b9649336d..cb43ad6811e 100644 --- a/board/mscc/common/spi.c +++ b/board/mscc/common/spi.c @@ -3,7 +3,6 @@ * Copyright (c) 2018 Microsemi Coprporation */ -#include #include #include #include diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c index 84b95be648d..acaeb468022 100644 --- a/board/mscc/jr2/jr2.c +++ b/board/mscc/jr2/jr2.c @@ -3,7 +3,7 @@ * Copyright (c) 2018 Microsemi Corporation */ -#include +#include #include #include #include diff --git a/board/mscc/luton/luton.c b/board/mscc/luton/luton.c index 48170b3aa12..f9ea26ebc5c 100644 --- a/board/mscc/luton/luton.c +++ b/board/mscc/luton/luton.c @@ -3,7 +3,7 @@ * Copyright (c) 2018 Microsemi Corporation */ -#include +#include #include #include #include diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c index d69db04de66..4cec25b3976 100644 --- a/board/mscc/ocelot/ocelot.c +++ b/board/mscc/ocelot/ocelot.c @@ -3,7 +3,7 @@ * Copyright (c) 2018 Microsemi Corporation */ -#include +#include #include #include #include diff --git a/board/mscc/serval/serval.c b/board/mscc/serval/serval.c index 99d5f5be657..951c24dd286 100644 --- a/board/mscc/serval/serval.c +++ b/board/mscc/serval/serval.c @@ -3,7 +3,7 @@ * Copyright (c) 2018 Microsemi Corporation */ -#include +#include #include #include #include diff --git a/board/mscc/servalt/servalt.c b/board/mscc/servalt/servalt.c index 49993168c23..9055b73ada2 100644 --- a/board/mscc/servalt/servalt.c +++ b/board/mscc/servalt/servalt.c @@ -3,7 +3,7 @@ * Copyright (c) 2018 Microsemi Corporation */ -#include +#include #include #include #include diff --git a/board/myir/mys_6ulx/spl.c b/board/myir/mys_6ulx/spl.c index 3cf14e2bc66..4414487eff2 100644 --- a/board/myir/mys_6ulx/spl.c +++ b/board/myir/mys_6ulx/spl.c @@ -4,7 +4,7 @@ * Author: Parthiban Nallathambi */ -#include +#include #include #include #include diff --git a/board/netgear/dgnd3700v2/dgnd3700v2.c b/board/netgear/dgnd3700v2/dgnd3700v2.c index cfc3529c348..9cf3a2fe60a 100644 --- a/board/netgear/dgnd3700v2/dgnd3700v2.c +++ b/board/netgear/dgnd3700v2/dgnd3700v2.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Álvaro Fernández Rojas */ -#include #include #include #include diff --git a/board/novtech/meerkat96/meerkat96.c b/board/novtech/meerkat96/meerkat96.c index 1edebe5db9b..ca3b0698f5a 100644 --- a/board/novtech/meerkat96/meerkat96.c +++ b/board/novtech/meerkat96/meerkat96.c @@ -12,7 +12,6 @@ #include #include #include -#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/nuvoton/arbel_evb/arbel_evb.c b/board/nuvoton/arbel_evb/arbel_evb.c index 53c931c3c24..1f519219e7e 100644 --- a/board/nuvoton/arbel_evb/arbel_evb.c +++ b/board/nuvoton/arbel_evb/arbel_evb.c @@ -3,7 +3,6 @@ * Copyright (c) 2022 Nuvoton Technology Corp. */ -#include #include #include #include diff --git a/board/nuvoton/poleg_evb/poleg_evb.c b/board/nuvoton/poleg_evb/poleg_evb.c index e69bca95031..3c4e5aaf294 100644 --- a/board/nuvoton/poleg_evb/poleg_evb.c +++ b/board/nuvoton/poleg_evb/poleg_evb.c @@ -4,7 +4,6 @@ * Copyright (c) 2021 Nuvoton Technology Corp. */ -#include #include #include #include diff --git a/board/nvidia/beaver/beaver-spl.c b/board/nvidia/beaver/beaver-spl.c index b5d0c14854d..c6956ff9f58 100644 --- a/board/nvidia/beaver/beaver-spl.c +++ b/board/nvidia/beaver/beaver-spl.c @@ -7,7 +7,6 @@ * Svyatoslav Ryhel */ -#include #include #include diff --git a/board/nvidia/cardhu/cardhu-spl.c b/board/nvidia/cardhu/cardhu-spl.c index de2fa300f1c..80912a65a19 100644 --- a/board/nvidia/cardhu/cardhu-spl.c +++ b/board/nvidia/cardhu/cardhu-spl.c @@ -7,7 +7,6 @@ * Svyatoslav Ryhel */ -#include #include #include diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c index 6848e340046..ab0dc61ebe5 100644 --- a/board/nvidia/cardhu/cardhu.c +++ b/board/nvidia/cardhu/cardhu.c @@ -4,7 +4,6 @@ * NVIDIA Corporation */ -#include #include #include #include diff --git a/board/nvidia/dalmore/dalmore.c b/board/nvidia/dalmore/dalmore.c index 72511e401e3..c00c6343eaa 100644 --- a/board/nvidia/dalmore/dalmore.c +++ b/board/nvidia/dalmore/dalmore.c @@ -3,7 +3,6 @@ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. */ -#include #include #include #include diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c index 52236792e24..da14e09c40c 100644 --- a/board/nvidia/harmony/harmony.c +++ b/board/nvidia/harmony/harmony.c @@ -4,7 +4,6 @@ * NVIDIA Corporation */ -#include #include #include #include diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c index 7f3cdd70fe7..da6edb42c1e 100644 --- a/board/nvidia/jetson-tk1/jetson-tk1.c +++ b/board/nvidia/jetson-tk1/jetson-tk1.c @@ -4,7 +4,6 @@ * NVIDIA Corporation */ -#include #include #include #include diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c index 06a36f8ed38..e15f31dcfd7 100644 --- a/board/nvidia/nyan-big/nyan-big.c +++ b/board/nvidia/nyan-big/nyan-big.c @@ -4,7 +4,6 @@ * NVIDIA Corporation */ -#include #include #include #include diff --git a/board/nvidia/p2371-0000/p2371-0000.c b/board/nvidia/p2371-0000/p2371-0000.c index b819b049f4b..edf2b1adb7c 100644 --- a/board/nvidia/p2371-0000/p2371-0000.c +++ b/board/nvidia/p2371-0000/p2371-0000.c @@ -4,7 +4,6 @@ * NVIDIA Corporation */ -#include #include #include #include diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c index 816c7bec6ae..5f203d8ffaa 100644 --- a/board/nvidia/p2371-2180/p2371-2180.c +++ b/board/nvidia/p2371-2180/p2371-2180.c @@ -4,7 +4,6 @@ * NVIDIA Corporation */ -#include #include #include #include diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c index a4c4259eeae..4056f986483 100644 --- a/board/nvidia/p2571/p2571.c +++ b/board/nvidia/p2571/p2571.c @@ -4,7 +4,6 @@ * NVIDIA Corporation */ -#include #include #include #include diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c index 5ff89c45423..12eaa7a1e53 100644 --- a/board/nvidia/p2771-0000/p2771-0000.c +++ b/board/nvidia/p2771-0000/p2771-0000.c @@ -3,7 +3,6 @@ * Copyright (c) 2016, NVIDIA CORPORATION */ -#include #include #include #include diff --git a/board/nvidia/p3450-0000/p3450-0000.c b/board/nvidia/p3450-0000/p3450-0000.c index fb1a224daa7..530c438a2e3 100644 --- a/board/nvidia/p3450-0000/p3450-0000.c +++ b/board/nvidia/p3450-0000/p3450-0000.c @@ -5,7 +5,6 @@ * */ -#include #include #include #include diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 829751112f1..a646dcc96b5 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -4,7 +4,6 @@ * NVIDIA Corporation */ -#include #include #include #include diff --git a/board/nvidia/venice2/as3722_init.c b/board/nvidia/venice2/as3722_init.c index 395bdd99c78..b89e03703b2 100644 --- a/board/nvidia/venice2/as3722_init.c +++ b/board/nvidia/venice2/as3722_init.c @@ -4,7 +4,6 @@ * NVIDIA Corporation */ -#include #include #include #include diff --git a/board/nvidia/venice2/venice2.c b/board/nvidia/venice2/venice2.c index d89bbe5ecce..fa10cda4870 100644 --- a/board/nvidia/venice2/venice2.c +++ b/board/nvidia/venice2/venice2.c @@ -4,7 +4,7 @@ * NVIDIA Corporation */ -#include +#include #include #include #include "pinmux-config-venice2.h" diff --git a/board/olimex/mx23_olinuxino/mx23_olinuxino.c b/board/olimex/mx23_olinuxino/mx23_olinuxino.c index bdd5fcd76ae..b2bb6678c23 100644 --- a/board/olimex/mx23_olinuxino/mx23_olinuxino.c +++ b/board/olimex/mx23_olinuxino/mx23_olinuxino.c @@ -5,7 +5,6 @@ * Copyright (C) 2013 Marek Vasut */ -#include #include #include #include diff --git a/board/olimex/mx23_olinuxino/spl_boot.c b/board/olimex/mx23_olinuxino/spl_boot.c index 248176c23cd..eb85ce9643d 100644 --- a/board/olimex/mx23_olinuxino/spl_boot.c +++ b/board/olimex/mx23_olinuxino/spl_boot.c @@ -5,7 +5,6 @@ * Copyright (C) 2013 Marek Vasut */ -#include #include #include #include diff --git a/board/openpiton/riscv64/openpiton-riscv64.c b/board/openpiton/riscv64/openpiton-riscv64.c index f2282d15488..4c957e88992 100644 --- a/board/openpiton/riscv64/openpiton-riscv64.c +++ b/board/openpiton/riscv64/openpiton-riscv64.c @@ -8,7 +8,6 @@ * Pragnesh Patel * Tianrui Wei */ -#include #include #include #include diff --git a/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c b/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c index edb200e9e55..10469aecd0b 100644 --- a/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c +++ b/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c @@ -5,7 +5,6 @@ #include #include #include -#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile index 3feb00fd1ec..c34fc503059 100644 --- a/board/phytec/common/Makefile +++ b/board/phytec/common/Makefile @@ -5,6 +5,8 @@ ifdef CONFIG_SPL_BUILD # necessary to create built-in.o obj- := __dummy__.o +else +obj-$(CONFIG_ARCH_K3) += k3/ endif obj-y += phytec_som_detection.o diff --git a/board/phytec/common/imx8m_som_detection.c b/board/phytec/common/imx8m_som_detection.c index ee34a5b9579..bfd60ffb777 100644 --- a/board/phytec/common/imx8m_som_detection.c +++ b/board/phytec/common/imx8m_som_detection.c @@ -4,7 +4,6 @@ * Author: Teresa Remmet */ -#include #include #include #include diff --git a/board/phytec/common/k3/Makefile b/board/phytec/common/k3/Makefile new file mode 100644 index 00000000000..bcca1a9f846 --- /dev/null +++ b/board/phytec/common/k3/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0+ +obj-y += board.o diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c new file mode 100644 index 00000000000..9cb168c36cb --- /dev/null +++ b/board/phytec/common/k3/board.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov + */ + +#include +#include +#include + +#if IS_ENABLED(CONFIG_ENV_IS_IN_FAT) || IS_ENABLED(CONFIG_ENV_IS_IN_MMC) +int mmc_get_env_dev(void) +{ + u32 boot_device = get_boot_device(); + + switch (boot_device) { + case BOOT_DEVICE_MMC1: + return 0; + case BOOT_DEVICE_MMC2: + return 1; + }; + + return CONFIG_SYS_MMC_ENV_DEV; +} +#endif + +enum env_location env_get_location(enum env_operation op, int prio) +{ + u32 boot_device = get_boot_device(); + + if (prio) + return ENVL_UNKNOWN; + + switch (boot_device) { + case BOOT_DEVICE_MMC1: + case BOOT_DEVICE_MMC2: + if (CONFIG_IS_ENABLED(ENV_IS_IN_FAT)) + return ENVL_FAT; + if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC)) + return ENVL_MMC; + case BOOT_DEVICE_SPI: + if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH)) + return ENVL_SPI_FLASH; + default: + return ENVL_NOWHERE; + }; +} + +#if IS_ENABLED(CONFIG_BOARD_LATE_INIT) +int board_late_init(void) +{ + u32 boot_device = get_boot_device(); + + switch (boot_device) { + case BOOT_DEVICE_MMC1: + env_set_ulong("mmcdev", 0); + env_set("boot", "mmc"); + break; + case BOOT_DEVICE_MMC2: + env_set_ulong("mmcdev", 1); + env_set("boot", "mmc"); + break; + case BOOT_DEVICE_SPI: + env_set("boot", "spi"); + break; + case BOOT_DEVICE_ETHERNET: + env_set("boot", "net"); + break; + }; + + return 0; +} +#endif diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c index 78c173df20d..b14bb3dbb7f 100644 --- a/board/phytec/common/phytec_som_detection.c +++ b/board/phytec/common/phytec_som_detection.c @@ -4,7 +4,6 @@ * Author: Teresa Remmet */ -#include #include #include #include diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c index b6d459fdfce..b98c46dbcbd 100644 --- a/board/phytec/pcl063/spl.c +++ b/board/phytec/pcl063/spl.c @@ -6,7 +6,7 @@ * Copyright (C) 2015-2016 Stefan Roese */ -#include +#include #include #include #include diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c index 0f7235979b0..20f2aac332d 100644 --- a/board/phytec/pcm052/pcm052.c +++ b/board/phytec/pcm052/pcm052.c @@ -6,7 +6,6 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/board/phytec/pcm058/pcm058.c b/board/phytec/pcm058/pcm058.c index b37c6fe218d..ecc5b75d8d4 100644 --- a/board/phytec/pcm058/pcm058.c +++ b/board/phytec/pcm058/pcm058.c @@ -9,7 +9,6 @@ * Both NAND and eMMC cannot be set because they share the * same pins (SD4) */ -#include #include #include #include diff --git a/board/phytec/phycore_am335x_r2/board.c b/board/phytec/phycore_am335x_r2/board.c index 5700effbd3f..2022525651d 100644 --- a/board/phytec/phycore_am335x_r2/board.c +++ b/board/phytec/phycore_am335x_r2/board.c @@ -10,7 +10,7 @@ * Copyright (C) 2019 DENX Software Engineering GmbH */ -#include +#include #include #include #include diff --git a/board/phytec/phycore_am335x_r2/mux.c b/board/phytec/phycore_am335x_r2/mux.c index 7091c985ba1..bb1c48da0fe 100644 --- a/board/phytec/phycore_am335x_r2/mux.c +++ b/board/phytec/phycore_am335x_r2/mux.c @@ -6,7 +6,6 @@ * Copyright (C) 2019 DENX Software Engineering GmbH */ -#include #include #include #include diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c index 618b4c370d1..a082b886bda 100644 --- a/board/phytec/phycore_am62x/phycore-am62x.c +++ b/board/phytec/phycore_am62x/phycore-am62x.c @@ -5,11 +5,8 @@ */ #include -#include -#include #include #include -#include DECLARE_GLOBAL_DATA_PTR; @@ -57,67 +54,3 @@ void spl_board_init(void) MCU_CTRL_DEVICE_CLKOUT_32K_CTRL); } #endif - -#if IS_ENABLED(CONFIG_ENV_IS_IN_FAT) || IS_ENABLED(CONFIG_ENV_IS_IN_MMC) -int mmc_get_env_dev(void) -{ - u32 boot_device = get_boot_device(); - - switch (boot_device) { - case BOOT_DEVICE_MMC1: - return 0; - case BOOT_DEVICE_MMC2: - return 1; - }; - - return CONFIG_SYS_MMC_ENV_DEV; -} -#endif - -enum env_location env_get_location(enum env_operation op, int prio) -{ - u32 boot_device = get_boot_device(); - - if (prio) - return ENVL_UNKNOWN; - - switch (boot_device) { - case BOOT_DEVICE_MMC1: - case BOOT_DEVICE_MMC2: - if (CONFIG_IS_ENABLED(ENV_IS_IN_FAT)) - return ENVL_FAT; - if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC)) - return ENVL_MMC; - case BOOT_DEVICE_SPI: - if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH)) - return ENVL_SPI_FLASH; - default: - return ENVL_NOWHERE; - }; -} - -#if IS_ENABLED(CONFIG_BOARD_LATE_INIT) -int board_late_init(void) -{ - u32 boot_device = get_boot_device(); - - switch (boot_device) { - case BOOT_DEVICE_MMC1: - env_set_ulong("mmcdev", 0); - env_set("boot", "mmc"); - break; - case BOOT_DEVICE_MMC2: - env_set_ulong("mmcdev", 1); - env_set("boot", "mmc"); - break; - case BOOT_DEVICE_SPI: - env_set("boot", "spi"); - break; - case BOOT_DEVICE_ETHERNET: - env_set("boot", "net"); - break; - }; - - return 0; -} -#endif diff --git a/board/phytec/phycore_imx8mm/phycore-imx8mm.c b/board/phytec/phycore_imx8mm/phycore-imx8mm.c index ef647291690..06cffbca3a6 100644 --- a/board/phytec/phycore_imx8mm/phycore-imx8mm.c +++ b/board/phytec/phycore_imx8mm/phycore-imx8mm.c @@ -4,7 +4,6 @@ * Author: Teresa Remmet */ -#include #include #include #include diff --git a/board/phytec/phycore_imx8mm/spl.c b/board/phytec/phycore_imx8mm/spl.c index 690a51f7a72..8d858590a39 100644 --- a/board/phytec/phycore_imx8mm/spl.c +++ b/board/phytec/phycore_imx8mm/spl.c @@ -4,7 +4,6 @@ * Author: Teresa Remmet */ -#include #include #include #include diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c b/board/phytec/phycore_imx8mp/phycore-imx8mp.c index dbdd6bb7937..35683591433 100644 --- a/board/phytec/phycore_imx8mp/phycore-imx8mp.c +++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c @@ -4,7 +4,6 @@ * Author: Teresa Remmet */ -#include #include #include #include diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index df158024654..352f803e454 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -4,7 +4,6 @@ * Author: Teresa Remmet */ -#include #include #include #include diff --git a/board/phytec/phycore_rk3288/phycore-rk3288.c b/board/phytec/phycore_rk3288/phycore-rk3288.c index 3f49f39e3d5..a970634b4c3 100644 --- a/board/phytec/phycore_rk3288/phycore-rk3288.c +++ b/board/phytec/phycore_rk3288/phycore-rk3288.c @@ -4,13 +4,11 @@ * Author: Wadim Egorov */ -#include #include #include #include #include #include -#include #include #include #include diff --git a/board/phytium/durian/durian.c b/board/phytium/durian/durian.c index 0a4048d4982..01e210fcdd1 100644 --- a/board/phytium/durian/durian.c +++ b/board/phytium/durian/durian.c @@ -5,7 +5,6 @@ * liuhao */ -#include #include #include #include diff --git a/board/phytium/pe2201/pe2201.c b/board/phytium/pe2201/pe2201.c index 0e837b0f50f..fbbf6789b50 100644 --- a/board/phytium/pe2201/pe2201.c +++ b/board/phytium/pe2201/pe2201.c @@ -12,7 +12,6 @@ #include #include #include -#include #include "cpu.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/phytium/pomelo/pomelo.c b/board/phytium/pomelo/pomelo.c index 960e491c768..0ea335e7486 100644 --- a/board/phytium/pomelo/pomelo.c +++ b/board/phytium/pomelo/pomelo.c @@ -14,7 +14,6 @@ #include #include #include -#include #include "cpu.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c b/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c index 14b94c9e33c..112770ba493 100644 --- a/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c +++ b/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include diff --git a/board/polyhex/imx8mp_debix_model_a/spl.c b/board/polyhex/imx8mp_debix_model_a/spl.c index eb904e116b1..6cbd1815cad 100644 --- a/board/polyhex/imx8mp_debix_model_a/spl.c +++ b/board/polyhex/imx8mp_debix_model_a/spl.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include diff --git a/board/purism/librem5/librem5.c b/board/purism/librem5/librem5.c index d0249e71f09..a3c421572af 100644 --- a/board/purism/librem5/librem5.c +++ b/board/purism/librem5/librem5.c @@ -4,7 +4,6 @@ * Copyright 2021 Purism */ -#include #include #include #include diff --git a/board/purism/librem5/lpddr4_timing.c b/board/purism/librem5/lpddr4_timing.c index 46bc7f8591c..e9559e3d843 100644 --- a/board/purism/librem5/lpddr4_timing.c +++ b/board/purism/librem5/lpddr4_timing.c @@ -4,7 +4,6 @@ */ #include -#include #include #include diff --git a/board/purism/librem5/lpddr4_timing_b0.c b/board/purism/librem5/lpddr4_timing_b0.c index ec68edaf690..5d8f2803be6 100644 --- a/board/purism/librem5/lpddr4_timing_b0.c +++ b/board/purism/librem5/lpddr4_timing_b0.c @@ -4,7 +4,6 @@ */ #include -#include #include #include diff --git a/board/purism/librem5/spl.c b/board/purism/librem5/spl.c index 9aadc553302..ed57554a2bc 100644 --- a/board/purism/librem5/spl.c +++ b/board/purism/librem5/spl.c @@ -4,7 +4,7 @@ * Copyright 2021 Purism */ -#include +#include #include #include #include diff --git a/board/qca/ap121/ap121.c b/board/qca/ap121/ap121.c index 60a2e19143d..6bb12602193 100644 --- a/board/qca/ap121/ap121.c +++ b/board/qca/ap121/ap121.c @@ -3,7 +3,6 @@ * Copyright (C) 2015-2016 Wills Wang */ -#include #include #include #include diff --git a/board/qca/ap143/ap143.c b/board/qca/ap143/ap143.c index ac65054136c..b88de9c4ec8 100644 --- a/board/qca/ap143/ap143.c +++ b/board/qca/ap143/ap143.c @@ -3,7 +3,6 @@ * Copyright (C) 2015-2016 Wills Wang */ -#include #include #include #include diff --git a/board/qca/ap152/ap152.c b/board/qca/ap152/ap152.c index 82458c3af42..53587288c93 100644 --- a/board/qca/ap152/ap152.c +++ b/board/qca/ap152/ap152.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Rosy Song */ -#include #include #include #include diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c index fbbfc0e65e2..bd2e213b3bc 100644 --- a/board/qualcomm/dragonboard410c/dragonboard410c.c +++ b/board/qualcomm/dragonboard410c/dragonboard410c.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/board/qualcomm/dragonboard820c/dragonboard820c.c b/board/qualcomm/dragonboard820c/dragonboard820c.c index ac7de711c58..d3333a59db0 100644 --- a/board/qualcomm/dragonboard820c/dragonboard820c.c +++ b/board/qualcomm/dragonboard820c/dragonboard820c.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include diff --git a/board/raidsonic/ib62x0/ib62x0.c b/board/raidsonic/ib62x0/ib62x0.c index f9bc07649e0..8d1d549a217 100644 --- a/board/raidsonic/ib62x0/ib62x0.c +++ b/board/raidsonic/ib62x0/ib62x0.c @@ -6,7 +6,6 @@ * Simon Baatz */ -#include #include #include #include diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 2851ebc9853..d996eb0cf69 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -3,7 +3,6 @@ * (C) Copyright 2012-2016 Stephen Warren */ -#include #include #include #include diff --git a/board/renesas/falcon/falcon.c b/board/renesas/falcon/falcon.c index 27fccacf6f8..c88257d9677 100644 --- a/board/renesas/falcon/falcon.c +++ b/board/renesas/falcon/falcon.c @@ -14,7 +14,6 @@ #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/renesas/grpeach/grpeach.c b/board/renesas/grpeach/grpeach.c index c475c3f50ab..88f65c3b6a0 100644 --- a/board/renesas/grpeach/grpeach.c +++ b/board/renesas/grpeach/grpeach.c @@ -10,7 +10,6 @@ #include #include #include -#include #define RZA1_WDT_BASE 0xfcfe0000 #define WTCSR 0x00 diff --git a/board/rockchip/evb_rk3036/evb_rk3036.c b/board/rockchip/evb_rk3036/evb_rk3036.c index 8c606463e45..a0805030ea4 100644 --- a/board/rockchip/evb_rk3036/evb_rk3036.c +++ b/board/rockchip/evb_rk3036/evb_rk3036.c @@ -3,7 +3,6 @@ * (C) Copyright 2015 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/board/rockchip/evb_rk3308/evb_rk3308.c b/board/rockchip/evb_rk3308/evb_rk3308.c index e0c96fd70a2..c895da934a9 100644 --- a/board/rockchip/evb_rk3308/evb_rk3308.c +++ b/board/rockchip/evb_rk3308/evb_rk3308.c @@ -3,7 +3,6 @@ * (C) Copyright 2018 Rockchip Electronics Co., Ltd */ -#include #include #include diff --git a/board/rockchip/evb_rv1108/evb_rv1108.c b/board/rockchip/evb_rv1108/evb_rv1108.c index 0d7a486bed7..48b9d8f80c4 100644 --- a/board/rockchip/evb_rv1108/evb_rv1108.c +++ b/board/rockchip/evb_rv1108/evb_rv1108.c @@ -4,7 +4,6 @@ * Authors: Andy Yan */ -#include #include #include #include diff --git a/board/rockchip/kylin_rk3036/kylin_rk3036.c b/board/rockchip/kylin_rk3036/kylin_rk3036.c index 0ca91cdeb01..c452b131208 100644 --- a/board/rockchip/kylin_rk3036/kylin_rk3036.c +++ b/board/rockchip/kylin_rk3036/kylin_rk3036.c @@ -3,7 +3,6 @@ * (C) Copyright 2015 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/board/rockchip/tinker_rk3288/tinker-rk3288.c b/board/rockchip/tinker_rk3288/tinker-rk3288.c index eff3a00c30a..e966e9f201a 100644 --- a/board/rockchip/tinker_rk3288/tinker-rk3288.c +++ b/board/rockchip/tinker_rk3288/tinker-rk3288.c @@ -3,9 +3,7 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ -#include #include -#include #include #include #include diff --git a/board/ronetix/imx7-cm/imx7-cm.c b/board/ronetix/imx7-cm/imx7-cm.c index c23097f0476..a1f3f3cd797 100644 --- a/board/ronetix/imx7-cm/imx7-cm.c +++ b/board/ronetix/imx7-cm/imx7-cm.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include diff --git a/board/ronetix/imx7-cm/spl.c b/board/ronetix/imx7-cm/spl.c index b94cfd6ffc6..136de3cf3ef 100644 --- a/board/ronetix/imx7-cm/spl.c +++ b/board/ronetix/imx7-cm/spl.c @@ -5,7 +5,6 @@ * Author: Ilko Iliev */ -#include #include #include #include diff --git a/board/ronetix/imx8mq-cm/imx8mq_cm.c b/board/ronetix/imx8mq-cm/imx8mq_cm.c index 9805a3a7da8..fbee2c39771 100644 --- a/board/ronetix/imx8mq-cm/imx8mq_cm.c +++ b/board/ronetix/imx8mq-cm/imx8mq_cm.c @@ -3,7 +3,6 @@ * Copyright 2018 NXP */ -#include #include #include #include diff --git a/board/ronetix/imx8mq-cm/lpddr4_timing.c b/board/ronetix/imx8mq-cm/lpddr4_timing.c index 685600ee62f..a7ad9375ce3 100644 --- a/board/ronetix/imx8mq-cm/lpddr4_timing.c +++ b/board/ronetix/imx8mq-cm/lpddr4_timing.c @@ -4,7 +4,6 @@ */ #include -#include #include #include diff --git a/board/ronetix/imx8mq-cm/spl.c b/board/ronetix/imx8mq-cm/spl.c index 1c675bcab25..ee0ad20ced4 100644 --- a/board/ronetix/imx8mq-cm/spl.c +++ b/board/ronetix/imx8mq-cm/spl.c @@ -4,7 +4,7 @@ * */ -#include +#include #include #include #include diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index 07febe69dc7..ee578749bce 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -7,7 +7,7 @@ * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD */ -#include +#include #include #include #include diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index 76f62ddde91..1de1bd68701 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -7,7 +7,7 @@ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD */ -#include +#include #include #include #include diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index aa5c80ac641..5d5edd9f253 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -10,7 +10,7 @@ * Lead Tech Design */ -#include +#include #include #include #include diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c index 3ebf600e1d7..e70b4a82687 100644 --- a/board/samsung/arndale/arndale.c +++ b/board/samsung/arndale/arndale.c @@ -3,7 +3,7 @@ * Copyright (C) 2013 Samsung Electronics */ -#include +#include #include #include #include diff --git a/board/samsung/arndale/arndale_spl.c b/board/samsung/arndale/arndale_spl.c index 6ad0273e049..c40ca7fa749 100644 --- a/board/samsung/arndale/arndale_spl.c +++ b/board/samsung/arndale/arndale_spl.c @@ -3,7 +3,6 @@ * Copyright (c) 2012 The Chromium OS Authors. */ -#include #include #define SIGNATURE 0xdeadbeef diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 5a71982775d..eed1c2450fa 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -4,7 +4,7 @@ * Rajeshwari Shinde */ -#include +#include #include #include #include diff --git a/board/samsung/common/exynos5-dt-types.c b/board/samsung/common/exynos5-dt-types.c index 9294d36ba35..8328bf427cc 100644 --- a/board/samsung/common/exynos5-dt-types.c +++ b/board/samsung/common/exynos5-dt-types.c @@ -4,7 +4,7 @@ * Przemyslaw Marczak */ -#include +#include #include #include #include diff --git a/board/samsung/common/exynos5-dt.c b/board/samsung/common/exynos5-dt.c index b3e87c93751..56862bcb34d 100644 --- a/board/samsung/common/exynos5-dt.c +++ b/board/samsung/common/exynos5-dt.c @@ -3,7 +3,7 @@ * Copyright (C) 2012 Samsung Electronics */ -#include +#include #include #include #include diff --git a/board/samsung/common/gadget.c b/board/samsung/common/gadget.c index 9487f9ec4e0..c1b4342f4e2 100644 --- a/board/samsung/common/gadget.c +++ b/board/samsung/common/gadget.c @@ -4,7 +4,7 @@ * Lukasz Majewski */ -#include +#include #include #define EXYNOS_G_DNL_THOR_VENDOR_NUM 0x04E8 diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index cc114aaaa6d..c134a9d70e2 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -4,7 +4,7 @@ * Przemyslaw Marczak */ -#include +#include #include #include #include diff --git a/board/samsung/common/sromc.c b/board/samsung/common/sromc.c index 76e37dfe262..689ac8f8c6f 100644 --- a/board/samsung/common/sromc.c +++ b/board/samsung/common/sromc.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_ETH -#include #include #include #include diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index c8f5a153bb4..a1047f3fd2a 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -5,7 +5,6 @@ * Kyungmin Park */ -#include #include #include #include diff --git a/board/samsung/goni/onenand.c b/board/samsung/goni/onenand.c index c67c107b16c..6c7a03624b0 100644 --- a/board/samsung/goni/onenand.c +++ b/board/samsung/goni/onenand.c @@ -4,7 +4,7 @@ * Kyungmin Park */ -#include +#include #include #include #include diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index 99e5613ced9..84d6d919f07 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -4,7 +4,7 @@ * Przemyslaw Marczak */ -#include +#include #include #include #include diff --git a/board/samsung/origen/origen.c b/board/samsung/origen/origen.c index ddf6a2b72fa..c474a7e54fa 100644 --- a/board/samsung/origen/origen.c +++ b/board/samsung/origen/origen.c @@ -3,7 +3,6 @@ * Copyright (C) 2011 Samsung Electronics */ -#include #include #include #include diff --git a/board/samsung/smdk5250/smdk5250_spl.c b/board/samsung/smdk5250/smdk5250_spl.c index b0ef34dd6aa..1c78cb6dda4 100644 --- a/board/samsung/smdk5250/smdk5250_spl.c +++ b/board/samsung/smdk5250/smdk5250_spl.c @@ -3,7 +3,6 @@ * Copyright (c) 2012 The Chromium OS Authors. */ -#include #include #include #include diff --git a/board/samsung/smdk5420/smdk5420_spl.c b/board/samsung/smdk5420/smdk5420_spl.c index 84126f5608c..ccf8b257ec2 100644 --- a/board/samsung/smdk5420/smdk5420_spl.c +++ b/board/samsung/smdk5420/smdk5420_spl.c @@ -3,7 +3,6 @@ * Copyright (C) 2013 The Chromium OS Authors. */ -#include #include #include #include diff --git a/board/samsung/smdkc100/onenand.c b/board/samsung/smdkc100/onenand.c index 04dc04a1a4a..86ec550aaca 100644 --- a/board/samsung/smdkc100/onenand.c +++ b/board/samsung/smdkc100/onenand.c @@ -4,7 +4,6 @@ * Kyungmin Park */ -#include #include #include #include diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index 4f46911b0b4..7d0b0fcb0ae 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -5,7 +5,7 @@ * Kyungmin Park */ -#include +#include #include #include #include diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c index 47483a26a62..5a4874b29cd 100644 --- a/board/samsung/smdkv310/smdkv310.c +++ b/board/samsung/smdkv310/smdkv310.c @@ -3,7 +3,7 @@ * Copyright (C) 2011 Samsung Electronics */ -#include +#include #include #include #include diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index 6a3e5b29b98..6efc6f3831d 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -6,7 +6,6 @@ * Donghwa Lee */ -#include #include #include #include diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index 81ccc124c80..612575a5094 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -5,7 +5,6 @@ * Piotr Wilczek */ -#include #include #include #include diff --git a/board/samsung/universal_c210/onenand.c b/board/samsung/universal_c210/onenand.c index 265a2cde4b4..ba56e86df46 100644 --- a/board/samsung/universal_c210/onenand.c +++ b/board/samsung/universal_c210/onenand.c @@ -4,7 +4,7 @@ * Kyungmin Park */ -#include +#include #include #include #include diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 2d61dff89c2..6bed724153e 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -5,7 +5,6 @@ * Kyungmin Park */ -#include #include #include #include diff --git a/board/schneider/rzn1-snarc/rzn1.c b/board/schneider/rzn1-snarc/rzn1.c index 09241c3a954..e1d5b5b0497 100644 --- a/board/schneider/rzn1-snarc/rzn1.c +++ b/board/schneider/rzn1-snarc/rzn1.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/board/seeed/linkit-smart-7688/board.c b/board/seeed/linkit-smart-7688/board.c index bf7c69ea838..91fa08fd9ec 100644 --- a/board/seeed/linkit-smart-7688/board.c +++ b/board/seeed/linkit-smart-7688/board.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Stefan Roese */ -#include #include #include #include diff --git a/board/seeed/npi_imx6ull/spl.c b/board/seeed/npi_imx6ull/spl.c index b29da2c1fc1..2312d8fac69 100644 --- a/board/seeed/npi_imx6ull/spl.c +++ b/board/seeed/npi_imx6ull/spl.c @@ -4,7 +4,7 @@ * Author: Navin Sankar Velliangiri */ -#include +#include #include #include #include diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c index b1d7e3b1c05..53dac8bfe1b 100644 --- a/board/siemens/capricorn/board.c +++ b/board/siemens/capricorn/board.c @@ -5,7 +5,6 @@ * Copyright 2019 Siemens AG * */ -#include #include #include #include diff --git a/board/siemens/capricorn/spl.c b/board/siemens/capricorn/spl.c index e160c611a96..696b5ebd340 100644 --- a/board/siemens/capricorn/spl.c +++ b/board/siemens/capricorn/spl.c @@ -5,7 +5,6 @@ * Copyright 2019 Siemens AG * */ -#include #include #include #include diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c index 569b86db00a..7d73d1f2b36 100644 --- a/board/siemens/corvus/board.c +++ b/board/siemens/corvus/board.c @@ -10,7 +10,7 @@ * Lead Tech Design */ -#include +#include #include #include #include diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c index 0b0686e2628..ed292c364a5 100644 --- a/board/siemens/iot2050/board.c +++ b/board/siemens/iot2050/board.c @@ -8,7 +8,7 @@ * Jan Kiszka */ -#include +#include #include #include #include diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c index 15044c7d0ed..946fbc3f229 100644 --- a/board/siemens/smartweb/smartweb.c +++ b/board/siemens/smartweb/smartweb.c @@ -15,7 +15,7 @@ * DENX Software Engineering GmbH */ -#include +#include #include #include #include diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c index ad44a7c0d28..bda12a97708 100644 --- a/board/siemens/taurus/taurus.c +++ b/board/siemens/taurus/taurus.c @@ -12,7 +12,7 @@ */ #include -#include +#include #include #include #include diff --git a/board/silinux/ek874/ek874.c b/board/silinux/ek874/ek874.c index 6dc804a0c06..a3fe6f96d09 100644 --- a/board/silinux/ek874/ek874.c +++ b/board/silinux/ek874/ek874.c @@ -6,8 +6,8 @@ * Copyright (C) 2021 Renesas Electronics Corporation */ -#include #include +#include #include #define RST_BASE 0xE6160000 diff --git a/board/sipeed/maix/maix.c b/board/sipeed/maix/maix.c index 06653b5a876..08077a1f9e1 100644 --- a/board/sipeed/maix/maix.c +++ b/board/sipeed/maix/maix.c @@ -3,7 +3,7 @@ * Copyright (C) 2019-20 Sean Anderson */ -#include +#include #include #include #include diff --git a/board/skyworth/hc2910-2aghd05/hc2910-2aghd05.c b/board/skyworth/hc2910-2aghd05/hc2910-2aghd05.c index abad5efdafb..22be10d70a7 100644 --- a/board/skyworth/hc2910-2aghd05/hc2910-2aghd05.c +++ b/board/skyworth/hc2910-2aghd05/hc2910-2aghd05.c @@ -3,7 +3,6 @@ * Board init file for Skyworth HC2910 2AGHD05 */ -#include #include #include #include diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c index 062e4a7b79f..556a9ed527e 100644 --- a/board/socionext/developerbox/developerbox.c +++ b/board/socionext/developerbox/developerbox.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/socrates/ddr.c b/board/socrates/ddr.c index 3a94f7beccd..bf4894eff67 100644 --- a/board/socrates/ddr.c +++ b/board/socrates/ddr.c @@ -3,7 +3,6 @@ * Copyright 2008 Freescale Semiconductor, Inc. */ -#include #include #include diff --git a/board/socrates/law.c b/board/socrates/law.c index e4427ecff1b..446fdbcaba3 100644 --- a/board/socrates/law.c +++ b/board/socrates/law.c @@ -9,7 +9,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include diff --git a/board/socrates/nand.c b/board/socrates/nand.c index b1e38c511e5..517a4a0af6a 100644 --- a/board/socrates/nand.c +++ b/board/socrates/nand.c @@ -4,7 +4,7 @@ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. */ -#include +#include #if defined(CFG_SYS_NAND_BASE) #include diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c index 61402a554b7..d0415d26ce7 100644 --- a/board/socrates/sdram.c +++ b/board/socrates/sdram.c @@ -4,7 +4,7 @@ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. */ -#include +#include #include #include #include diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index 1d63c81a9c8..6e6e276cc74 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -10,7 +10,7 @@ * (C) Copyright 2002 Scott McNutt */ -#include +#include #include #include #include diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c index 631f6c34075..0cc675781d1 100644 --- a/board/socrates/tlb.c +++ b/board/socrates/tlb.c @@ -9,8 +9,9 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include +#include struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ diff --git a/board/softing/vining_2000/vining_2000.c b/board/softing/vining_2000/vining_2000.c index 4483bd7f7a3..a0dbf97524b 100644 --- a/board/softing/vining_2000/vining_2000.c +++ b/board/softing/vining_2000/vining_2000.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/softing/vining_fpga/socfpga.c b/board/softing/vining_fpga/socfpga.c index b3f9550742e..2483fbcf263 100644 --- a/board/softing/vining_fpga/socfpga.c +++ b/board/softing/vining_fpga/socfpga.c @@ -3,7 +3,7 @@ * Copyright (C) 2012 Altera Corporation */ -#include +#include #include #include #include diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c index 6977db0a9e2..2dbd071abd9 100644 --- a/board/solidrun/clearfog/clearfog.c +++ b/board/solidrun/clearfog/clearfog.c @@ -3,7 +3,7 @@ * Copyright (C) 2015 Stefan Roese */ -#include +#include #include #include #include diff --git a/board/solidrun/common/tlv_data.c b/board/solidrun/common/tlv_data.c index cf5824886c3..b8086605c3a 100644 --- a/board/solidrun/common/tlv_data.c +++ b/board/solidrun/common/tlv_data.c @@ -3,9 +3,9 @@ * Copyright 2020 SolidRun */ -#include #include #include +#include #include "tlv_data.h" #define SR_TLV_CODE_RAM_SIZE 0x81 diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index 7f4811d8879..3406ba8616e 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -15,7 +15,7 @@ * Ported to SolidRun microSOM by Rabeeh Khoury */ -#include +#include #include #include #include diff --git a/board/somlabs/visionsom-6ull/visionsom-6ull.c b/board/somlabs/visionsom-6ull/visionsom-6ull.c index 38d14f6bc26..0ecb5c3b493 100644 --- a/board/somlabs/visionsom-6ull/visionsom-6ull.c +++ b/board/somlabs/visionsom-6ull/visionsom-6ull.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/board/sr1500/socfpga.c b/board/sr1500/socfpga.c index d9125a76bf7..5603ef24da8 100644 --- a/board/sr1500/socfpga.c +++ b/board/sr1500/socfpga.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Stefan Roese */ -#include #include #include #include diff --git a/board/st/common/cmd_stboard.c b/board/st/common/cmd_stboard.c index c8c0bad5da1..50da063051b 100644 --- a/board/st/common/cmd_stboard.c +++ b/board/st/common/cmd_stboard.c @@ -30,7 +30,6 @@ */ #ifndef CONFIG_SPL_BUILD -#include #include #include #include diff --git a/board/st/common/stm32mp_dfu.c b/board/st/common/stm32mp_dfu.c index 77edb86e78c..1db8e45480e 100644 --- a/board/st/common/stm32mp_dfu.c +++ b/board/st/common/stm32mp_dfu.c @@ -3,7 +3,6 @@ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved */ -#include #include #include #include diff --git a/board/st/common/stm32mp_dfu_virt.c b/board/st/common/stm32mp_dfu_virt.c index f0f99605796..4049d72bf9d 100644 --- a/board/st/common/stm32mp_dfu_virt.c +++ b/board/st/common/stm32mp_dfu_virt.c @@ -3,7 +3,6 @@ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved */ -#include #include #include #include diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c index 969ad484864..45c2bb5bcea 100644 --- a/board/st/common/stpmic1.c +++ b/board/st/common/stpmic1.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY LOGC_BOARD -#include #include #include #include diff --git a/board/st/common/stusb160x.c b/board/st/common/stusb160x.c index f0385e5e383..e1ad8b00717 100644 --- a/board/st/common/stusb160x.c +++ b/board/st/common/stusb160x.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_I2C_GENERIC -#include #include #include diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c index 82817571ae3..a912712c9dd 100644 --- a/board/st/stih410-b2260/board.c +++ b/board/st/stih410-b2260/board.c @@ -4,7 +4,6 @@ * Author(s): Patrice Chotard, for STMicroelectronics. */ -#include #include #include #include diff --git a/board/st/stm32f429-discovery/led.c b/board/st/stm32f429-discovery/led.c index 8dda6a97bd1..4b8038341b9 100644 --- a/board/st/stm32f429-discovery/led.c +++ b/board/st/stm32f429-discovery/led.c @@ -4,7 +4,6 @@ * Kamil Lulko, */ -#include #include #include diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c index 55e464cc7cf..22d751b44d3 100644 --- a/board/st/stm32f429-discovery/stm32f429-discovery.c +++ b/board/st/stm32f429-discovery/stm32f429-discovery.c @@ -10,7 +10,6 @@ * Kamil Lulko, */ -#include #include #include #include diff --git a/board/st/stm32f429-evaluation/stm32f429-evaluation.c b/board/st/stm32f429-evaluation/stm32f429-evaluation.c index 25472f041fe..db59ebb838e 100644 --- a/board/st/stm32f429-evaluation/stm32f429-evaluation.c +++ b/board/st/stm32f429-evaluation/stm32f429-evaluation.c @@ -4,7 +4,6 @@ * Author(s): Patrice Chotard, for STMicroelectronics. */ -#include #include #include #include diff --git a/board/st/stm32f469-discovery/stm32f469-discovery.c b/board/st/stm32f469-discovery/stm32f469-discovery.c index 9ed6c1e6768..134d207d95d 100644 --- a/board/st/stm32f469-discovery/stm32f469-discovery.c +++ b/board/st/stm32f469-discovery/stm32f469-discovery.c @@ -4,7 +4,6 @@ * Author(s): Patrice CHOTARD, for STMicroelectronics. */ -#include #include #include #include diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index 0f966600843..6d86e4fe7aa 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -4,7 +4,7 @@ * Author(s): Vikas Manocha, for STMicroelectronics. */ -#include +#include #include #include #include diff --git a/board/st/stm32h743-disco/stm32h743-disco.c b/board/st/stm32h743-disco/stm32h743-disco.c index 4ca5e847212..35ef9ff9e28 100644 --- a/board/st/stm32h743-disco/stm32h743-disco.c +++ b/board/st/stm32h743-disco/stm32h743-disco.c @@ -4,7 +4,6 @@ * Author(s): Patrice Chotard, for STMicroelectronics. */ -#include #include #include #include diff --git a/board/st/stm32h743-eval/stm32h743-eval.c b/board/st/stm32h743-eval/stm32h743-eval.c index 4ca5e847212..35ef9ff9e28 100644 --- a/board/st/stm32h743-eval/stm32h743-eval.c +++ b/board/st/stm32h743-eval/stm32h743-eval.c @@ -4,7 +4,6 @@ * Author(s): Patrice Chotard, for STMicroelectronics. */ -#include #include #include #include diff --git a/board/st/stm32h750-art-pi/stm32h750-art-pi.c b/board/st/stm32h750-art-pi/stm32h750-art-pi.c index 0d39ce849a6..75aa4d139fb 100644 --- a/board/st/stm32h750-art-pi/stm32h750-art-pi.c +++ b/board/st/stm32h750-art-pi/stm32h750-art-pi.c @@ -4,7 +4,6 @@ * Author(s): Dillon Min */ -#include #include #include #include diff --git a/board/st/stm32mp1/spl.c b/board/st/stm32mp1/spl.c index 8b4a529f759..d63dffd97e8 100644 --- a/board/st/stm32mp1/spl.c +++ b/board/st/stm32mp1/spl.c @@ -4,7 +4,6 @@ */ #include -#include #include #include #include diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index db15d78237e..97532a8156f 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY LOGC_BOARD -#include #include #include #include diff --git a/board/ste/stemmy/stemmy.c b/board/ste/stemmy/stemmy.c index 060d562cbc9..826c002907d 100644 --- a/board/ste/stemmy/stemmy.c +++ b/board/ste/stemmy/stemmy.c @@ -2,12 +2,12 @@ /* * Copyright (C) 2019 Stephan Gerhold */ -#include #include #include #include #include #include +#include #include #include #include diff --git a/board/storopack/smegw01/smegw01.c b/board/storopack/smegw01/smegw01.c index 345191b31c2..910feeda31f 100644 --- a/board/storopack/smegw01/smegw01.c +++ b/board/storopack/smegw01/smegw01.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 1313b01dcea..ed86f1df5dc 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -10,7 +10,6 @@ * Some board init for the Allwinner A10-evb board. */ -#include #include #include #include diff --git a/board/sunxi/chip.c b/board/sunxi/chip.c index eeee6319e79..270af2506d2 100644 --- a/board/sunxi/chip.c +++ b/board/sunxi/chip.c @@ -5,7 +5,6 @@ * Based on initial code from Maxime Ripard */ -#include #include #include #include diff --git a/board/sunxi/dram_sun4i_auto.c b/board/sunxi/dram_sun4i_auto.c index 547d1c0cb4d..4b78919a5ba 100644 --- a/board/sunxi/dram_sun4i_auto.c +++ b/board/sunxi/dram_sun4i_auto.c @@ -1,4 +1,3 @@ -#include #include #include diff --git a/board/sunxi/dram_sun5i_auto.c b/board/sunxi/dram_sun5i_auto.c index 517506ccc4f..8976e3b16d6 100644 --- a/board/sunxi/dram_sun5i_auto.c +++ b/board/sunxi/dram_sun5i_auto.c @@ -1,6 +1,5 @@ /* DRAM parameters for auto dram configuration on sun5i and sun7i */ -#include #include #include diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c index 2a885305ebe..710e821e3fc 100644 --- a/board/sunxi/gmac.c +++ b/board/sunxi/gmac.c @@ -1,4 +1,3 @@ -#include #include #include #include diff --git a/board/sysam/amcore/amcore.c b/board/sysam/amcore/amcore.c index 086421d9265..d5aa1f0776f 100644 --- a/board/sysam/amcore/amcore.c +++ b/board/sysam/amcore/amcore.c @@ -7,7 +7,7 @@ * This file copies memory testdram() from sandburst/common/sb_common.c */ -#include +#include #include #include #include diff --git a/board/sysam/stmark2/stmark2.c b/board/sysam/stmark2/stmark2.c index 475e3edfa62..7818f2671d5 100644 --- a/board/sysam/stmark2/stmark2.c +++ b/board/sysam/stmark2/stmark2.c @@ -5,7 +5,7 @@ * (C) Copyright 2017 Angelo Dureghello */ -#include +#include #include #include #include diff --git a/board/tcl/sl50/board.c b/board/tcl/sl50/board.c index 3f7d42f3eb8..2e54ede62d6 100644 --- a/board/tcl/sl50/board.c +++ b/board/tcl/sl50/board.c @@ -7,7 +7,7 @@ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include +#include #include #include #include diff --git a/board/tcl/sl50/mux.c b/board/tcl/sl50/mux.c index ab9088145ab..6d89c4a3998 100644 --- a/board/tcl/sl50/mux.c +++ b/board/tcl/sl50/mux.c @@ -5,7 +5,6 @@ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include #include #include #include diff --git a/board/technexion/pico-imx6/pico-imx6.c b/board/technexion/pico-imx6/pico-imx6.c index 6b9c4f4373c..03170b148c5 100644 --- a/board/technexion/pico-imx6/pico-imx6.c +++ b/board/technexion/pico-imx6/pico-imx6.c @@ -6,7 +6,6 @@ * Author: Fabio Estevam */ -#include #include #include #include diff --git a/board/technexion/pico-imx6/spl.c b/board/technexion/pico-imx6/spl.c index 3b36bb8df13..50f51774264 100644 --- a/board/technexion/pico-imx6/spl.c +++ b/board/technexion/pico-imx6/spl.c @@ -6,7 +6,6 @@ * Fabio Estevam */ -#include #include #include #include diff --git a/board/technexion/pico-imx6ul/pico-imx6ul.c b/board/technexion/pico-imx6ul/pico-imx6ul.c index 682c88dee78..10dcf8077e2 100644 --- a/board/technexion/pico-imx6ul/pico-imx6ul.c +++ b/board/technexion/pico-imx6ul/pico-imx6ul.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/board/technexion/pico-imx6ul/spl.c b/board/technexion/pico-imx6ul/spl.c index ff56fd88d68..67484e62dad 100644 --- a/board/technexion/pico-imx6ul/spl.c +++ b/board/technexion/pico-imx6ul/spl.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c index b12941ccf82..d0f739c624a 100644 --- a/board/technexion/pico-imx7d/pico-imx7d.c +++ b/board/technexion/pico-imx7d/pico-imx7d.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include diff --git a/board/technexion/pico-imx7d/spl.c b/board/technexion/pico-imx7d/spl.c index 0192eafbaa1..8f219f76c60 100644 --- a/board/technexion/pico-imx7d/spl.c +++ b/board/technexion/pico-imx7d/spl.c @@ -5,7 +5,7 @@ * Author: Richard Hu */ -#include +#include #include #include #include diff --git a/board/technexion/pico-imx8mq/lpddr4_timing_1gb.c b/board/technexion/pico-imx8mq/lpddr4_timing_1gb.c index 97b9ee27527..cd8ba59f645 100644 --- a/board/technexion/pico-imx8mq/lpddr4_timing_1gb.c +++ b/board/technexion/pico-imx8mq/lpddr4_timing_1gb.c @@ -7,7 +7,6 @@ */ #include -#include #include #include diff --git a/board/technexion/pico-imx8mq/lpddr4_timing_2gb.c b/board/technexion/pico-imx8mq/lpddr4_timing_2gb.c index 1572a50a05f..3f66238a504 100644 --- a/board/technexion/pico-imx8mq/lpddr4_timing_2gb.c +++ b/board/technexion/pico-imx8mq/lpddr4_timing_2gb.c @@ -7,7 +7,6 @@ */ #include -#include #include #include diff --git a/board/technexion/pico-imx8mq/lpddr4_timing_3gb.c b/board/technexion/pico-imx8mq/lpddr4_timing_3gb.c index 3fc60a3eeb9..2f037abc97d 100644 --- a/board/technexion/pico-imx8mq/lpddr4_timing_3gb.c +++ b/board/technexion/pico-imx8mq/lpddr4_timing_3gb.c @@ -7,7 +7,6 @@ */ #include -#include #include #include diff --git a/board/technexion/pico-imx8mq/lpddr4_timing_4gb.c b/board/technexion/pico-imx8mq/lpddr4_timing_4gb.c index 93b34235162..336ac4c2f54 100644 --- a/board/technexion/pico-imx8mq/lpddr4_timing_4gb.c +++ b/board/technexion/pico-imx8mq/lpddr4_timing_4gb.c @@ -7,7 +7,6 @@ */ #include -#include #include #include diff --git a/board/technexion/pico-imx8mq/pico-imx8mq.c b/board/technexion/pico-imx8mq/pico-imx8mq.c index 2be3206f78a..1659db112fa 100644 --- a/board/technexion/pico-imx8mq/pico-imx8mq.c +++ b/board/technexion/pico-imx8mq/pico-imx8mq.c @@ -3,7 +3,6 @@ * Copyright 2018 NXP */ -#include #include #include #include diff --git a/board/technexion/pico-imx8mq/spl.c b/board/technexion/pico-imx8mq/spl.c index 1a9c7996cb2..c9d68b402ae 100644 --- a/board/technexion/pico-imx8mq/spl.c +++ b/board/technexion/pico-imx8mq/spl.c @@ -3,7 +3,6 @@ * Copyright 2018 NXP */ -#include #include #include #include diff --git a/board/terasic/de1-soc/socfpga.c b/board/terasic/de1-soc/socfpga.c index 22fbee40aba..8d17f44fd37 100644 --- a/board/terasic/de1-soc/socfpga.c +++ b/board/terasic/de1-soc/socfpga.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2012 Altera Corporation */ -#include #include void board_boot_order(u32 *spl_boot_list) diff --git a/board/thead/th1520_lpi4a/board.c b/board/thead/th1520_lpi4a/board.c index 16c3e456b3e..bb83e7561f4 100644 --- a/board/thead/th1520_lpi4a/board.c +++ b/board/thead/th1520_lpi4a/board.c @@ -4,7 +4,6 @@ * */ -#include #include int board_init(void) diff --git a/board/theadorable/fpga.c b/board/theadorable/fpga.c index bc8379cccf6..56d3647227b 100644 --- a/board/theadorable/fpga.c +++ b/board/theadorable/fpga.c @@ -3,10 +3,10 @@ * Copyright (C) 2016 Stefan Roese */ -#include #include #include #include +#include #include #include #include diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c index 144f122bb20..cca5c3d33b5 100644 --- a/board/theadorable/theadorable.c +++ b/board/theadorable/theadorable.c @@ -3,7 +3,6 @@ * Copyright (C) 2015-2019 Stefan Roese */ -#include #include #include #include diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 34f987c2b72..34f4a919656 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -7,7 +7,7 @@ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include +#include #include #include #include diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h index 1284c160d81..b0a3842423f 100644 --- a/board/ti/am335x/board.h +++ b/board/ti/am335x/board.h @@ -10,6 +10,8 @@ #ifndef _BOARD_H_ #define _BOARD_H_ +#include + /** * AM335X (EMIF_4D) EMIF REG_COS_COUNT_1, REG_COS_COUNT_2, and * REG_PR_OLD_COUNT values to avoid LCDC DMA FIFO underflows and Frame diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 0bad154f86e..960de15398f 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index a4679a2e294..40b7fcfc387 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -7,8 +7,7 @@ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include -#include +#include #include #include #include diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h index 37a169aaf75..b1025bdda1e 100644 --- a/board/ti/am43xx/board.h +++ b/board/ti/am43xx/board.h @@ -11,6 +11,7 @@ #ifndef _BOARD_H_ #define _BOARD_H_ +#include #include #define DEV_ATTR_MAX_OFFSET 5 diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index 463f1cc7178..2fcccbd1f04 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -5,7 +5,6 @@ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ */ -#include #include #include #include "../common/board_detect.h" diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index b004a89bb32..48668884bdd 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -7,7 +7,7 @@ * Based on board/ti/dra7xx/evm.c */ -#include +#include #include #include #include diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c index 38e23ccbb67..ea21d48bbc0 100644 --- a/board/ti/common/board_detect.c +++ b/board/ti/common/board_detect.c @@ -7,10 +7,9 @@ * Steve Kipisz */ -#include -#include #include #include +#include #include #include #include diff --git a/board/ti/common/cape_detect.c b/board/ti/common/cape_detect.c index 2e6105cfbf1..da805befabc 100644 --- a/board/ti/common/cape_detect.c +++ b/board/ti/common/cape_detect.c @@ -4,10 +4,11 @@ * Köry Maincent, Bootlin, */ -#include +#include #include #include #include +#include #include "cape_detect.h" diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index a8a216d034a..2b1db2541b0 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -9,7 +9,7 @@ * Aneesh V * Steve Sakoman */ -#include +#include #include #include #include diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 5dcda12105b..c6735d37dda 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -6,7 +6,7 @@ * Texas Instruments Incorporated, */ -#include +#include #include #include "board.h" #include diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c index 39abb24e156..4385be4221b 100644 --- a/board/ti/ks2_evm/board_k2e.c +++ b/board/ti/ks2_evm/board_k2e.c @@ -6,7 +6,6 @@ * Texas Instruments Incorporated, */ -#include #include #include #include diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index 5229afad63b..d07b77d23e2 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -5,8 +5,7 @@ * (C) Copyright 2015 * Texas Instruments Incorporated, */ -#include -#include +#include #include #include #include diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c index 12c4649c3c4..2b5d2d75664 100644 --- a/board/ti/ks2_evm/board_k2hk.c +++ b/board/ti/ks2_evm/board_k2hk.c @@ -6,7 +6,6 @@ * Texas Instruments Incorporated, */ -#include #include #include #include diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c index f759ee36466..1971bc94f7d 100644 --- a/board/ti/ks2_evm/board_k2l.c +++ b/board/ti/ks2_evm/board_k2l.c @@ -6,7 +6,6 @@ * Texas Instruments Incorporated, */ -#include #include #include #include diff --git a/board/ti/ks2_evm/ddr3_cfg.c b/board/ti/ks2_evm/ddr3_cfg.c index 0ade75263f8..fe350fee795 100644 --- a/board/ti/ks2_evm/ddr3_cfg.c +++ b/board/ti/ks2_evm/ddr3_cfg.c @@ -6,7 +6,6 @@ * Texas Instruments Incorporated, */ -#include #include #include "ddr3_cfg.h" diff --git a/board/ti/ks2_evm/ddr3_k2e.c b/board/ti/ks2_evm/ddr3_k2e.c index 95fe3a9021e..28305326e6a 100644 --- a/board/ti/ks2_evm/ddr3_k2e.c +++ b/board/ti/ks2_evm/ddr3_k2e.c @@ -6,7 +6,6 @@ * Texas Instruments Incorporated, */ -#include #include "ddr3_cfg.h" #include diff --git a/board/ti/ks2_evm/ddr3_k2g.c b/board/ti/ks2_evm/ddr3_k2g.c index 3000d7245eb..ef39e078152 100644 --- a/board/ti/ks2_evm/ddr3_k2g.c +++ b/board/ti/ks2_evm/ddr3_k2g.c @@ -6,7 +6,6 @@ * Texas Instruments Incorporated, */ -#include #include "ddr3_cfg.h" #include #include diff --git a/board/ti/ks2_evm/ddr3_k2hk.c b/board/ti/ks2_evm/ddr3_k2hk.c index 198c5da0e62..05c050cee44 100644 --- a/board/ti/ks2_evm/ddr3_k2hk.c +++ b/board/ti/ks2_evm/ddr3_k2hk.c @@ -6,7 +6,6 @@ * Texas Instruments Incorporated, */ -#include #include "ddr3_cfg.h" #include #include diff --git a/board/ti/ks2_evm/ddr3_k2l.c b/board/ti/ks2_evm/ddr3_k2l.c index 805bf81f6bd..aa6d45f0f8a 100644 --- a/board/ti/ks2_evm/ddr3_k2l.c +++ b/board/ti/ks2_evm/ddr3_k2l.c @@ -6,7 +6,6 @@ * Texas Instruments Incorporated, */ -#include #include "ddr3_cfg.h" #include diff --git a/board/ti/omap3evm/evm.c b/board/ti/omap3evm/evm.c index a4d6a0138d9..4eb08add256 100644 --- a/board/ti/omap3evm/evm.c +++ b/board/ti/omap3evm/evm.c @@ -10,7 +10,7 @@ * Richard Woodruff * Syed Mohammed Khasim */ -#include +#include #include #include #include diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index 22093186019..e47d3a952d5 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -4,7 +4,6 @@ * Texas Instruments Incorporated, * Steve Sakoman */ -#include #include #include #include diff --git a/board/ti/sdp4430/cmd_bat.c b/board/ti/sdp4430/cmd_bat.c index 6c1e6ca393c..6bf44d92655 100644 --- a/board/ti/sdp4430/cmd_bat.c +++ b/board/ti/sdp4430/cmd_bat.c @@ -3,7 +3,6 @@ * Copyright (C) 2010 Texas Instruments */ -#include #include #ifdef CONFIG_CMD_BAT diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c index 2c9ae794fd4..1a71390f543 100644 --- a/board/ti/sdp4430/sdp.c +++ b/board/ti/sdp4430/sdp.c @@ -5,7 +5,6 @@ * Aneesh V * Steve Sakoman */ -#include #include #include #include diff --git a/board/timll/devkit3250/devkit3250.c b/board/timll/devkit3250/devkit3250.c index efef855b3d0..f0c0f03deeb 100644 --- a/board/timll/devkit3250/devkit3250.c +++ b/board/timll/devkit3250/devkit3250.c @@ -5,7 +5,7 @@ * Copyright (C) 2011-2015 Vladimir Zapolskiy */ -#include +#include #include #include #include diff --git a/board/timll/devkit3250/devkit3250_spl.c b/board/timll/devkit3250/devkit3250_spl.c index 12e8ae9c39c..07a367c3ad1 100644 --- a/board/timll/devkit3250/devkit3250_spl.c +++ b/board/timll/devkit3250/devkit3250_spl.c @@ -5,7 +5,6 @@ * (C) Copyright 2015 Vladimir Zapolskiy */ -#include #include #include #include diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index 06009d8ad54..ad404f7e9c4 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -15,7 +15,7 @@ * Syed Mohammed Khasim * */ -#include +#include #include #include #include diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c index 0f993e644d7..72d67d90d41 100644 --- a/board/toradex/apalis-imx8/apalis-imx8.c +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -3,7 +3,6 @@ * Copyright 2019 Toradex */ -#include #include #include #include diff --git a/board/toradex/apalis-tk1/apalis-tk1.c b/board/toradex/apalis-tk1/apalis-tk1.c index ee87d9f4145..4557ed1f1f2 100644 --- a/board/toradex/apalis-tk1/apalis-tk1.c +++ b/board/toradex/apalis-tk1/apalis-tk1.c @@ -3,7 +3,6 @@ * Copyright (c) 2016-2018 Toradex, Inc. */ -#include #include #include #include diff --git a/board/toradex/apalis-tk1/as3722_init.c b/board/toradex/apalis-tk1/as3722_init.c index e9bd1028bed..8971f7aa16a 100644 --- a/board/toradex/apalis-tk1/as3722_init.c +++ b/board/toradex/apalis-tk1/as3722_init.c @@ -3,7 +3,6 @@ * Copyright (c) 2012-2016 Toradex, Inc. */ -#include #include #include #include diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index 0da245374a0..2dcc042ab26 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -6,7 +6,7 @@ * copied from nitrogen6x */ -#include +#include #include #include #include diff --git a/board/toradex/apalis_imx6/do_fuse.c b/board/toradex/apalis_imx6/do_fuse.c index 6991b1bc136..b404b01e032 100644 --- a/board/toradex/apalis_imx6/do_fuse.c +++ b/board/toradex/apalis_imx6/do_fuse.c @@ -7,7 +7,6 @@ * Helpers for i.MX OTP fusing during module production */ -#include #ifndef CONFIG_SPL_BUILD #include #include diff --git a/board/toradex/apalis_imx6/pf0100.c b/board/toradex/apalis_imx6/pf0100.c index c89052ff5da..157aaec6fe0 100644 --- a/board/toradex/apalis_imx6/pf0100.c +++ b/board/toradex/apalis_imx6/pf0100.c @@ -7,7 +7,6 @@ * Helpers for Freescale PMIC PF0100 */ -#include #include #include #include diff --git a/board/toradex/apalis_t30/apalis_t30-spl.c b/board/toradex/apalis_t30/apalis_t30-spl.c index 6e544641833..25049452495 100644 --- a/board/toradex/apalis_t30/apalis_t30-spl.c +++ b/board/toradex/apalis_t30/apalis_t30-spl.c @@ -7,7 +7,6 @@ * Svyatoslav Ryhel */ -#include #include #include diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c index b10beb44796..02e8f8eb1fe 100644 --- a/board/toradex/apalis_t30/apalis_t30.c +++ b/board/toradex/apalis_t30/apalis_t30.c @@ -4,7 +4,6 @@ * Marcel Ziswiler */ -#include #include #include #include diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c index 9b9fb342c9d..7bfe200d6e4 100644 --- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c +++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c @@ -2,7 +2,7 @@ /* * Copyright (C) 2018-2019 Toradex AG */ -#include +#include #include #include #include diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c index 35657852595..2a71e7b92de 100644 --- a/board/toradex/colibri-imx8x/colibri-imx8x.c +++ b/board/toradex/colibri-imx8x/colibri-imx8x.c @@ -3,7 +3,6 @@ * Copyright 2019 Toradex */ -#include #include #include #include diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index ce19a9c7975..34e82c2b078 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -6,7 +6,7 @@ * copied from nitrogen6x */ -#include +#include #include #include #include diff --git a/board/toradex/colibri_imx6/do_fuse.c b/board/toradex/colibri_imx6/do_fuse.c index 6991b1bc136..b404b01e032 100644 --- a/board/toradex/colibri_imx6/do_fuse.c +++ b/board/toradex/colibri_imx6/do_fuse.c @@ -7,7 +7,6 @@ * Helpers for i.MX OTP fusing during module production */ -#include #ifndef CONFIG_SPL_BUILD #include #include diff --git a/board/toradex/colibri_imx6/pf0100.c b/board/toradex/colibri_imx6/pf0100.c index 8f08d8c7337..58b7bc3bb9a 100644 --- a/board/toradex/colibri_imx6/pf0100.c +++ b/board/toradex/colibri_imx6/pf0100.c @@ -7,7 +7,6 @@ * Helpers for Freescale PMIC PF0100 */ -#include #include #include #include diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index c37c5e0af6d..e966ffbf781 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -3,7 +3,6 @@ * Copyright (C) 2016-2018 Toradex AG */ -#include #include #include #include diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index 97e33d00f0d..6425fa881ea 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -3,7 +3,6 @@ * Copyright (C) 2012 Lucas Stach */ -#include #include #include #include diff --git a/board/toradex/colibri_t30/colibri_t30-spl.c b/board/toradex/colibri_t30/colibri_t30-spl.c index 6e544641833..25049452495 100644 --- a/board/toradex/colibri_t30/colibri_t30-spl.c +++ b/board/toradex/colibri_t30/colibri_t30-spl.c @@ -7,7 +7,6 @@ * Svyatoslav Ryhel */ -#include #include #include diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c index 0da247de98f..342673ac506 100644 --- a/board/toradex/colibri_t30/colibri_t30.c +++ b/board/toradex/colibri_t30/colibri_t30.c @@ -4,7 +4,6 @@ * Stefan Agner */ -#include #include #include #include diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index 35920008805..87f82396d63 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -6,7 +6,6 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ -#include #include #include diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index dcf00d2b632..2225cefec16 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -3,7 +3,7 @@ * Copyright (c) 2016-2020 Toradex */ -#include +#include #include #include "tdx-cfg-block.h" #include "tdx-eeprom.h" diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c index 9f09788137d..a6b45cdab81 100644 --- a/board/toradex/common/tdx-common.c +++ b/board/toradex/common/tdx-common.c @@ -4,7 +4,7 @@ */ #include -#include +#include #include #include #include diff --git a/board/toradex/verdin-imx8mm/spl.c b/board/toradex/verdin-imx8mm/spl.c index afa3686083a..1020078afea 100644 --- a/board/toradex/verdin-imx8mm/spl.c +++ b/board/toradex/verdin-imx8mm/spl.c @@ -3,7 +3,6 @@ * Copyright 2020 Toradex */ -#include #include #include #include diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index 55c02653da6..020ee677480 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -3,7 +3,7 @@ * Copyright 2020-2021 Toradex */ -#include +#include #include #include #include diff --git a/board/toradex/verdin-imx8mp/spl.c b/board/toradex/verdin-imx8mp/spl.c index 73729a42b45..8628112a782 100644 --- a/board/toradex/verdin-imx8mp/spl.c +++ b/board/toradex/verdin-imx8mp/spl.c @@ -3,7 +3,6 @@ * Copyright 2022 Toradex */ -#include #include #include #include diff --git a/board/toradex/verdin-imx8mp/verdin-imx8mp.c b/board/toradex/verdin-imx8mp/verdin-imx8mp.c index e16a771e3ec..e57ec3b6896 100644 --- a/board/toradex/verdin-imx8mp/verdin-imx8mp.c +++ b/board/toradex/verdin-imx8mp/verdin-imx8mp.c @@ -3,7 +3,7 @@ * Copyright 2022 Toradex */ -#include +#include #include #include #include diff --git a/board/tplink/wdr4300/wdr4300.c b/board/tplink/wdr4300/wdr4300.c index f2de039b6b4..3ae0dc4ecd7 100644 --- a/board/tplink/wdr4300/wdr4300.c +++ b/board/tplink/wdr4300/wdr4300.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Marek Vasut */ -#include #include #include #include diff --git a/board/tq/tqma6/tqma6.c b/board/tq/tqma6/tqma6.c index 1c2228c77ad..92142c10ae5 100644 --- a/board/tq/tqma6/tqma6.c +++ b/board/tq/tqma6/tqma6.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/board/tq/tqma6/tqma6_mba6.c b/board/tq/tqma6/tqma6_mba6.c index 52851dd5b55..877539e359e 100644 --- a/board/tq/tqma6/tqma6_mba6.c +++ b/board/tq/tqma6/tqma6_mba6.c @@ -20,7 +20,6 @@ #include #include -#include #include #include #include diff --git a/board/tq/tqma6/tqma6_wru4.c b/board/tq/tqma6/tqma6_wru4.c index 5d239913fc5..21c710188e0 100644 --- a/board/tq/tqma6/tqma6_wru4.c +++ b/board/tq/tqma6/tqma6_wru4.c @@ -23,7 +23,6 @@ #include #include -#include #include #include #include diff --git a/board/traverse/common/ten64_controller.c b/board/traverse/common/ten64_controller.c index d6ef8a8d0df..63b72c4df7b 100644 --- a/board/traverse/common/ten64_controller.c +++ b/board/traverse/common/ten64_controller.c @@ -5,7 +5,6 @@ * */ -#include #include #include #include diff --git a/board/traverse/ten64/eth_ten64.c b/board/traverse/ten64/eth_ten64.c index 3f96e572b75..c5f7acecc14 100644 --- a/board/traverse/ten64/eth_ten64.c +++ b/board/traverse/ten64/eth_ten64.c @@ -3,7 +3,6 @@ * Copyright 2017 NXP * Copyright 2019-2021 Traverse Technologies Australia */ -#include #include #include #include diff --git a/board/traverse/ten64/ten64.c b/board/traverse/ten64/ten64.c index 6ff5312d6d7..d41bd2e9dee 100644 --- a/board/traverse/ten64/ten64.c +++ b/board/traverse/ten64/ten64.c @@ -4,7 +4,7 @@ * Copyright 2017-2018 NXP * Copyright 2019-2021 Traverse Technologies */ -#include +#include #include #include #include diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c index d99d93b44ae..b435b721e53 100644 --- a/board/udoo/neo/neo.c +++ b/board/udoo/neo/neo.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/board/udoo/udoo_spl.c b/board/udoo/udoo_spl.c index 647380e1db6..6c477530055 100644 --- a/board/udoo/udoo_spl.c +++ b/board/udoo/udoo_spl.c @@ -6,7 +6,6 @@ * Based on board/wandboard/spl.c */ -#include #include #include #include diff --git a/board/variscite/dart_6ul/spl.c b/board/variscite/dart_6ul/spl.c index 1dff69c8277..6d17563d32c 100644 --- a/board/variscite/dart_6ul/spl.c +++ b/board/variscite/dart_6ul/spl.c @@ -4,7 +4,7 @@ * Copyright (C) 2019 Parthiban Nallathambi */ -#include +#include #include #include #include diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c b/board/variscite/imx8mn_var_som/imx8mn_var_som.c index 994fd4f7058..532d8d60a76 100644 --- a/board/variscite/imx8mn_var_som/imx8mn_var_som.c +++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c @@ -5,7 +5,6 @@ * Copyright 2023 DimOnOff Inc. */ -#include #include #include #include diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c index bc7dc5888f2..2c91e9fac43 100644 --- a/board/vscom/baltos/board.c +++ b/board/vscom/baltos/board.c @@ -7,7 +7,7 @@ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include +#include #include #include #include diff --git a/board/vscom/baltos/mux.c b/board/vscom/baltos/mux.c index 7b99cf0e182..77b142f08f0 100644 --- a/board/vscom/baltos/mux.c +++ b/board/vscom/baltos/mux.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c index 717e02a039b..9ce2785a4f0 100644 --- a/board/wandboard/spl.c +++ b/board/wandboard/spl.c @@ -5,7 +5,7 @@ * Richard Hu */ -#include +#include #include #include #include diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 8be62c86695..a48ef33ffde 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -6,7 +6,6 @@ * Author: Fabio Estevam */ -#include #include #include #include diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c index ead52d5a490..4cd3ff0051b 100644 --- a/board/warp7/warp7.c +++ b/board/warp7/warp7.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include diff --git a/board/work-microwave/work_92105/work_92105.c b/board/work-microwave/work_92105/work_92105.c index c8e791a4da8..9a236880e3c 100644 --- a/board/work-microwave/work_92105/work_92105.c +++ b/board/work-microwave/work_92105/work_92105.c @@ -6,7 +6,7 @@ * Written-by: Albert ARIBAUD */ -#include +#include #include #include #include diff --git a/board/work-microwave/work_92105/work_92105_display.c b/board/work-microwave/work_92105/work_92105_display.c index 64dd5d4072a..d4ab2299895 100644 --- a/board/work-microwave/work_92105/work_92105_display.c +++ b/board/work-microwave/work_92105/work_92105_display.c @@ -10,7 +10,6 @@ * MAX518 I2C DACs and native LPC32xx GPO 15. */ -#include #include #include #include diff --git a/board/work-microwave/work_92105/work_92105_spl.c b/board/work-microwave/work_92105/work_92105_spl.c index d9401145f27..3f91221ce8b 100644 --- a/board/work-microwave/work_92105/work_92105_spl.c +++ b/board/work-microwave/work_92105/work_92105_spl.c @@ -6,7 +6,6 @@ * Written-by: Albert ARIBAUD */ -#include #include #include #include diff --git a/board/xen/xenguest_arm64/xenguest_arm64.c b/board/xen/xenguest_arm64/xenguest_arm64.c index 1d2946f4fde..4c3b9c9e278 100644 --- a/board/xen/xenguest_arm64/xenguest_arm64.c +++ b/board/xen/xenguest_arm64/xenguest_arm64.c @@ -7,7 +7,6 @@ * (C) 2020 EPAM Systems Inc */ -#include #include #include #include diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index b47d2d23f91..30a81376ac4 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -6,7 +6,6 @@ * Michal Simek */ -#include #include #include #include diff --git a/board/xilinx/common/cpu-info.c b/board/xilinx/common/cpu-info.c index bfe7f5b7e38..765bb24d937 100644 --- a/board/xilinx/common/cpu-info.c +++ b/board/xilinx/common/cpu-info.c @@ -4,7 +4,6 @@ * Michal Simek */ -#include #include #include diff --git a/board/xilinx/common/fru.c b/board/xilinx/common/fru.c index 12b21317496..8cf307e33f2 100644 --- a/board/xilinx/common/fru.c +++ b/board/xilinx/common/fru.c @@ -3,7 +3,6 @@ * (C) Copyright 2019 - 2020 Xilinx, Inc. */ -#include #include #include #include diff --git a/board/xilinx/common/fru_ops.c b/board/xilinx/common/fru_ops.c index 167252c240c..610293bccf7 100644 --- a/board/xilinx/common/fru_ops.c +++ b/board/xilinx/common/fru_ops.c @@ -4,13 +4,13 @@ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. */ -#include #include #include #include #include #include #include +#include #include #include diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c index da03024e162..88e10fa7a7f 100644 --- a/board/xilinx/versal-net/board.c +++ b/board/xilinx/versal-net/board.c @@ -6,7 +6,6 @@ * Michal Simek */ -#include #include #include #include diff --git a/board/xilinx/versal-net/cmds.c b/board/xilinx/versal-net/cmds.c index b18a71fe52c..4d52084846b 100644 --- a/board/xilinx/versal-net/cmds.c +++ b/board/xilinx/versal-net/cmds.c @@ -7,10 +7,10 @@ #include #include -#include #include #include #include +#include #include /** diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 4f6d56119db..77ba783501e 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/board/xilinx/versal/cmds.c b/board/xilinx/versal/cmds.c index 2a74e49aede..c78793573e8 100644 --- a/board/xilinx/versal/cmds.c +++ b/board/xilinx/versal/cmds.c @@ -6,10 +6,10 @@ #include #include -#include #include #include #include +#include #include static int do_versal_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc, diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 6c365910011..b9a91110ff7 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -4,7 +4,7 @@ * (C) Copyright 2013 - 2018 Xilinx, Inc. */ -#include +#include #include #include #include diff --git a/board/xilinx/zynq/bootimg.c b/board/xilinx/zynq/bootimg.c index 2f55078dd76..79bec3a4cfb 100644 --- a/board/xilinx/zynq/bootimg.c +++ b/board/xilinx/zynq/bootimg.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Xilinx, Inc. */ -#include #include #include #include diff --git a/board/xilinx/zynq/cmds.c b/board/xilinx/zynq/cmds.c index d7c7b2f2295..05ecb75406b 100644 --- a/board/xilinx/zynq/cmds.c +++ b/board/xilinx/zynq/cmds.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Xilinx, Inc. */ -#include #include #include #include diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c index 9524688f27d..bf39c5472ea 100644 --- a/board/xilinx/zynqmp/cmds.c +++ b/board/xilinx/zynqmp/cmds.c @@ -4,13 +4,14 @@ * Siva Durga Prasad Paladugu > */ -#include #include #include #include #include #include +#include #include +#include #include #include #include diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index f370fb7347a..c4050af2a5a 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -4,7 +4,7 @@ * Michal Simek */ -#include +#include #include #include #include diff --git a/board/xilinx/zynqmp_r5/board.c b/board/xilinx/zynqmp_r5/board.c index 5c5a2e93863..0c62b0013c4 100644 --- a/board/xilinx/zynqmp_r5/board.c +++ b/board/xilinx/zynqmp_r5/board.c @@ -3,9 +3,9 @@ * (C) Copyright 2018 Xilinx, Inc. (Michal Simek) */ -#include #include #include +#include int board_init(void) { diff --git a/board/zyxel/nsa310s/nsa310s.c b/board/zyxel/nsa310s/nsa310s.c index b3ea6608914..d018b573824 100644 --- a/board/zyxel/nsa310s/nsa310s.c +++ b/board/zyxel/nsa310s/nsa310s.c @@ -4,7 +4,6 @@ * Copyright (C) 2015 Gerald Kerma */ -#include #include #include #include diff --git a/board/zyxel/nsa325/nsa325.c b/board/zyxel/nsa325/nsa325.c index f5f63ee5d3b..38340b33c8b 100644 --- a/board/zyxel/nsa325/nsa325.c +++ b/board/zyxel/nsa325/nsa325.c @@ -14,7 +14,6 @@ * Marvell Semiconductor */ -#include #include #include #include diff --git a/boot/android_ab.c b/boot/android_ab.c index 1e5aa81b750..143f373aae9 100644 --- a/boot/android_ab.c +++ b/boot/android_ab.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2017 The Android Open Source Project */ -#include #include #include #include diff --git a/boot/boot_fit.c b/boot/boot_fit.c index 9d394126563..4dcaf95c6ae 100644 --- a/boot/boot_fit.c +++ b/boot/boot_fit.c @@ -7,7 +7,6 @@ */ #include -#include #include #include #include diff --git a/boot/bootdev-uclass.c b/boot/bootdev-uclass.c index 46815ea2fdb..7c7bba088c9 100644 --- a/boot/bootdev-uclass.c +++ b/boot/bootdev-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_BOOTSTD -#include #include #include #include diff --git a/boot/bootflow.c b/boot/bootflow.c index 68bf99329ab..9aa3179c388 100644 --- a/boot/bootflow.c +++ b/boot/bootflow.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_BOOTSTD -#include #include #include #include diff --git a/boot/bootflow_menu.c b/boot/bootflow_menu.c index 16f9cd8f8ca..143ef841332 100644 --- a/boot/bootflow_menu.c +++ b/boot/bootflow_menu.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_BOOTSTD -#include #include #include #include diff --git a/boot/bootm.c b/boot/bootm.c index 032f5a4a160..6fa8edab021 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -5,7 +5,6 @@ */ #ifndef USE_HOSTCC -#include #include #include #include diff --git a/boot/bootm_os.c b/boot/bootm_os.c index ccde72d22c1..15297ddb530 100644 --- a/boot/bootm_os.c +++ b/boot/bootm_os.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include diff --git a/boot/bootmeth-uclass.c b/boot/bootmeth-uclass.c index 1d157d54dbd..c0abadef97c 100644 --- a/boot/bootmeth-uclass.c +++ b/boot/bootmeth-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_BOOTSTD -#include #include #include #include diff --git a/boot/bootmeth_cros.c b/boot/bootmeth_cros.c index f015f2e1c75..645b8bed102 100644 --- a/boot/bootmeth_cros.c +++ b/boot/bootmeth_cros.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_BOOTSTD -#include #include #include #include diff --git a/boot/bootmeth_efi.c b/boot/bootmeth_efi.c index aebc5207fc0..c7035c0d0c4 100644 --- a/boot/bootmeth_efi.c +++ b/boot/bootmeth_efi.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_BOOTSTD -#include #include #include #include diff --git a/boot/bootmeth_efi_mgr.c b/boot/bootmeth_efi_mgr.c index b7d429f2c3d..23ae1e610ac 100644 --- a/boot/bootmeth_efi_mgr.c +++ b/boot/bootmeth_efi_mgr.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_BOOTSTD -#include #include #include #include diff --git a/boot/bootmeth_extlinux.c b/boot/bootmeth_extlinux.c index ae0ad1d53e3..9b55686948f 100644 --- a/boot/bootmeth_extlinux.c +++ b/boot/bootmeth_extlinux.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_BOOTSTD -#include #include #include #include diff --git a/boot/bootmeth_pxe.c b/boot/bootmeth_pxe.c index 70f693aa239..03d2589c264 100644 --- a/boot/bootmeth_pxe.c +++ b/boot/bootmeth_pxe.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_BOOTSTD -#include #include #include #include diff --git a/boot/bootmeth_qfw.c b/boot/bootmeth_qfw.c index 8ebbc3ebcd5..dfaa944594e 100644 --- a/boot/bootmeth_qfw.c +++ b/boot/bootmeth_qfw.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_BOOTSTD -#include #include #include #include diff --git a/boot/bootmeth_sandbox.c b/boot/bootmeth_sandbox.c index aabc57e635a..0bc8f688e30 100644 --- a/boot/bootmeth_sandbox.c +++ b/boot/bootmeth_sandbox.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_BOOTSTD -#include #include #include #include diff --git a/boot/bootmeth_script.c b/boot/bootmeth_script.c index 06340e43d2d..0e05d28d4d9 100644 --- a/boot/bootmeth_script.c +++ b/boot/bootmeth_script.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_BOOTSTD -#include #include #include #include diff --git a/boot/bootretry.c b/boot/bootretry.c index 8d850df9d48..587b2de7d6b 100644 --- a/boot/bootretry.c +++ b/boot/bootretry.c @@ -4,12 +4,13 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include #include #include +#include #include static uint64_t endtime; /* must be set, default is instant timeout */ diff --git a/boot/bootstd-uclass.c b/boot/bootstd-uclass.c index 81555d341e3..5de8efce19a 100644 --- a/boot/bootstd-uclass.c +++ b/boot/bootstd-uclass.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/boot/cedit.c b/boot/cedit.c index 8c654dba6dc..c29a2be14ce 100644 --- a/boot/cedit.c +++ b/boot/cedit.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY LOGC_EXPO -#include #include #include #include diff --git a/boot/common_fit.c b/boot/common_fit.c index cde2dc45e90..a2f9b8d83c3 100644 --- a/boot/common_fit.c +++ b/boot/common_fit.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/boot/expo.c b/boot/expo.c index cadb6a0ad6e..ed01483f1d3 100644 --- a/boot/expo.c +++ b/boot/expo.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY LOGC_EXPO -#include #include #include #include diff --git a/boot/expo_build.c b/boot/expo_build.c index 04d88a2c308..a4df798adeb 100644 --- a/boot/expo_build.c +++ b/boot/expo_build.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY LOGC_EXPO -#include #include #include #include diff --git a/boot/fdt_simplefb.c b/boot/fdt_simplefb.c index 837920bd3a3..53415548459 100644 --- a/boot/fdt_simplefb.c +++ b/boot/fdt_simplefb.c @@ -6,7 +6,6 @@ * Stephen Warren */ -#include #include #include #include diff --git a/boot/fdt_support.c b/boot/fdt_support.c index 2bd80a9dfb1..874ca4d6f5a 100644 --- a/boot/fdt_support.c +++ b/boot/fdt_support.c @@ -6,7 +6,6 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/boot/image-android-dt.c b/boot/image-android-dt.c index fb014190d44..3b25018c2e7 100644 --- a/boot/image-android-dt.c +++ b/boot/image-android-dt.c @@ -6,7 +6,6 @@ #include #include -#include #include #include diff --git a/boot/image-android.c b/boot/image-android.c index 88e40bc7ec6..ddd8ffd5e54 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -3,7 +3,6 @@ * Copyright (c) 2011 Sebastian Andrzej Siewior */ -#include #include #include #include diff --git a/boot/image-board.c b/boot/image-board.c index 09b6e4e0bdc..b7884b8c5dc 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -8,7 +8,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include diff --git a/boot/image-cipher.c b/boot/image-cipher.c index b9061489396..9d389f26cea 100644 --- a/boot/image-cipher.c +++ b/boot/image-cipher.c @@ -7,7 +7,6 @@ #include "mkimage.h" #include #else -#include #include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/boot/image-fdt.c b/boot/image-fdt.c index f09716cba30..56dd7687f51 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -8,7 +8,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include diff --git a/boot/image-fit-sig.c b/boot/image-fit-sig.c index 12369896fe3..fe328df4a85 100644 --- a/boot/image-fit-sig.c +++ b/boot/image-fit-sig.c @@ -7,7 +7,6 @@ #include "mkimage.h" #include #else -#include #include #include #include diff --git a/boot/image-fit.c b/boot/image-fit.c index 89e377563ce..fb03cab831b 100644 --- a/boot/image-fit.c +++ b/boot/image-fit.c @@ -19,7 +19,6 @@ #else #include #include -#include #include #include #include diff --git a/boot/image-pre-load.c b/boot/image-pre-load.c index b504ab42a54..cc19017404c 100644 --- a/boot/image-pre-load.c +++ b/boot/image-pre-load.c @@ -3,7 +3,6 @@ * Copyright (C) 2021 Philippe Reynes */ -#include #include DECLARE_GLOBAL_DATA_PTR; #include diff --git a/boot/image-sig.c b/boot/image-sig.c index 0421a61b040..6bc74866eae 100644 --- a/boot/image-sig.c +++ b/boot/image-sig.c @@ -3,7 +3,6 @@ * Copyright (c) 2013, Google Inc. */ -#include #include #include #include diff --git a/boot/image.c b/boot/image.c index 073931cd7a3..eb12e4be04a 100644 --- a/boot/image.c +++ b/boot/image.c @@ -7,7 +7,6 @@ */ #ifndef USE_HOSTCC -#include #include #include #include diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c index 5c1c962ff4c..4b22bb6f525 100644 --- a/boot/pxe_utils.c +++ b/boot/pxe_utils.c @@ -4,7 +4,6 @@ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. */ -#include #include #include #include diff --git a/boot/scene.c b/boot/scene.c index d4dfb49ada1..ac976aa26bb 100644 --- a/boot/scene.c +++ b/boot/scene.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY LOGC_EXPO -#include #include #include #include diff --git a/boot/scene_menu.c b/boot/scene_menu.c index 63994165efb..80bd7457cb1 100644 --- a/boot/scene_menu.c +++ b/boot/scene_menu.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY LOGC_EXPO -#include #include #include #include diff --git a/boot/scene_textline.c b/boot/scene_textline.c index 6ea072a1c26..bba8663b98d 100644 --- a/boot/scene_textline.c +++ b/boot/scene_textline.c @@ -8,10 +8,12 @@ #define LOG_CATEGORY LOGC_EXPO -#include #include #include +#include #include +#include +#include #include "scene_internal.h" int scene_textline(struct scene *scn, const char *name, uint id, uint max_chars, diff --git a/boot/vbe.c b/boot/vbe.c index 52b32830037..00673de7ee2 100644 --- a/boot/vbe.c +++ b/boot/vbe.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/boot/vbe_request.c b/boot/vbe_request.c index 0293ac6c869..a1350c1a706 100644 --- a/boot/vbe_request.c +++ b/boot/vbe_request.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY LOGC_BOOT -#include #include #include #include diff --git a/boot/vbe_simple.c b/boot/vbe_simple.c index 12682abd399..189e86d2a22 100644 --- a/boot/vbe_simple.c +++ b/boot/vbe_simple.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY LOGC_BOOT -#include #include #include #include diff --git a/boot/vbe_simple_fw.c b/boot/vbe_simple_fw.c index d59a704ddba..4d6da9490a7 100644 --- a/boot/vbe_simple_fw.c +++ b/boot/vbe_simple_fw.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY LOGC_BOOT -#include #include #include #include diff --git a/boot/vbe_simple_os.c b/boot/vbe_simple_os.c index 84626cdeaf2..b4126d8d2d0 100644 --- a/boot/vbe_simple_os.c +++ b/boot/vbe_simple_os.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY LOGC_BOOT -#include #include #include #include diff --git a/cmd/2048.c b/cmd/2048.c index fa60aa94aad..42cd171b0e4 100644 --- a/cmd/2048.c +++ b/cmd/2048.c @@ -3,10 +3,10 @@ /* Console version of the game "2048" for GNU/Linux */ -#include #include #include #include +#include #include #define SIZE 4 diff --git a/cmd/Kconfig b/cmd/Kconfig index b026439c773..c06fec35275 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -539,6 +539,7 @@ config CMD_IMI config CMD_IMLS bool "imls" + depends on MTD_NOR_FLASH || FLASH_CFI_DRIVER help List all images found in flash @@ -831,7 +832,7 @@ config SYS_EEPROM_SIZE config SYS_EEPROM_PAGE_WRITE_BITS int "Number of bits used to address bytes in a single page" - depends on CMD_EEPROM + depends on CMD_EEPROM || ENV_IS_IN_EEPROM default 8 help The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. @@ -1023,8 +1024,8 @@ config CMD_ARMFFA - Displaying the arm_ffa device info config CMD_ARMFLASH - #depends on FLASH_CFI_DRIVER bool "armflash" + depends on FLASH_CFI_DRIVER help ARM Ltd reference designs flash partition access @@ -1167,6 +1168,7 @@ config CMD_FPGA_LOAD_SECURE config CMD_FPGAD bool "fpgad - dump FPGA registers" + depends on GDSYS_LEGACY_DRIVERS help (legacy, needs conversion to driver model) Provides a way to dump FPGA registers by calling the board-specific @@ -1602,6 +1604,7 @@ config CMD_TEMPERATURE config CMD_TSI148 bool "tsi148 - Command to access tsi148 device" + depends on DM_PCI_COMPAT help This provides various sub-commands to initialise and configure the Turndra tsi148 device. See the command help for full details. @@ -1615,6 +1618,7 @@ config CMD_UFS config CMD_UNIVERSE bool "universe - Command to set up the Turndra Universe controller" + depends on DM_PCI_COMPAT help This allows setting up the VMEbus provided by this controller. See the command help for full details. diff --git a/cmd/ab_select.c b/cmd/ab_select.c index bfb67b8236b..faeb83816e5 100644 --- a/cmd/ab_select.c +++ b/cmd/ab_select.c @@ -3,7 +3,6 @@ * Copyright (C) 2017 The Android Open Source Project */ -#include #include #include #include diff --git a/cmd/abootimg.c b/cmd/abootimg.c index 2653b555b10..88c77d99929 100644 --- a/cmd/abootimg.c +++ b/cmd/abootimg.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/cmd/acpi.c b/cmd/acpi.c index 928e5dc525e..094d9d4e858 100644 --- a/cmd/acpi.c +++ b/cmd/acpi.c @@ -3,7 +3,6 @@ * Copyright 2019 Google LLC * Written by Simon Glass */ -#include #include #include #include @@ -11,6 +10,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/cmd/adc.c b/cmd/adc.c index 4cb18b66d4a..f87f9785a11 100644 --- a/cmd/adc.c +++ b/cmd/adc.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 BayLibre, SAS * Author: Neil Armstrong */ -#include #include #include #include diff --git a/cmd/addrmap.c b/cmd/addrmap.c index bd23549f3a5..f7e4d9206de 100644 --- a/cmd/addrmap.c +++ b/cmd/addrmap.c @@ -3,7 +3,6 @@ * Copyright (C) 2021, Bin Meng */ -#include #include #include diff --git a/cmd/adtimg.c b/cmd/adtimg.c index f4b5cbf35b9..53f33764fbe 100644 --- a/cmd/adtimg.c +++ b/cmd/adtimg.c @@ -7,8 +7,8 @@ #include #include +#include #include -#include #define OPT_INDEX "--index" diff --git a/cmd/aes.c b/cmd/aes.c index 1264675aa01..87ad1ab82b9 100644 --- a/cmd/aes.c +++ b/cmd/aes.c @@ -5,13 +5,13 @@ * Command for en/de-crypting block of memory with AES-[128/192/256]-CBC cipher. */ -#include #include #include #include #include #include #include +#include u32 aes_get_key_len(char *command) { diff --git a/cmd/arm/exception64.c b/cmd/arm/exception64.c index 589a23115b0..73d6c20ccac 100644 --- a/cmd/arm/exception64.c +++ b/cmd/arm/exception64.c @@ -5,7 +5,6 @@ * Copyright (c) 2018, Heinrich Schuchardt */ -#include #include #include diff --git a/cmd/armffa.c b/cmd/armffa.c index 9585150b962..181e31bc49a 100644 --- a/cmd/armffa.c +++ b/cmd/armffa.c @@ -5,7 +5,6 @@ * Authors: * Abdellatif El Khlifi */ -#include #include #include #include diff --git a/cmd/armflash.c b/cmd/armflash.c index fdaea5ad811..e292cf85c45 100644 --- a/cmd/armflash.c +++ b/cmd/armflash.c @@ -5,10 +5,10 @@ * * Support for ARM Flash Partitions */ -#include #include #include #include +#include #include #define MAX_REGIONS 4 diff --git a/cmd/axi.c b/cmd/axi.c index 5620891db28..3dbea0499de 100644 --- a/cmd/axi.c +++ b/cmd/axi.c @@ -9,7 +9,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include #include #include #include diff --git a/cmd/bcb.c b/cmd/bcb.c index f3b92564d10..fe6d6cb2c38 100644 --- a/cmd/bcb.c +++ b/cmd/bcb.c @@ -8,12 +8,12 @@ #include #include #include -#include #include #include #include #include #include +#include #include enum bcb_cmd { diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index 79106caeec2..437ac4e8630 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -6,7 +6,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include diff --git a/cmd/bind.c b/cmd/bind.c index be0d4d2a711..3a59eefd5c5 100644 --- a/cmd/bind.c +++ b/cmd/bind.c @@ -3,7 +3,6 @@ * Copyright (c) 2018 JJ Hiblot */ -#include #include #include #include diff --git a/cmd/binop.c b/cmd/binop.c index 592e9146901..10d91b5dbf2 100644 --- a/cmd/binop.c +++ b/cmd/binop.c @@ -1,11 +1,11 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include #include #include +#include #include enum { diff --git a/cmd/blk_common.c b/cmd/blk_common.c index 02ac92837b6..4c05a4e0610 100644 --- a/cmd/blk_common.c +++ b/cmd/blk_common.c @@ -8,10 +8,10 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include +#include int blk_common_cmd(int argc, char *const argv[], enum uclass_id uclass_id, int *cur_devnump) diff --git a/cmd/blkcache.c b/cmd/blkcache.c index 1456654df6f..dbd03df14dc 100644 --- a/cmd/blkcache.c +++ b/cmd/blkcache.c @@ -6,9 +6,9 @@ */ #include #include -#include #include #include +#include static int blkc_show(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/blkmap.c b/cmd/blkmap.c index ef74ebc0036..164f80f1387 100644 --- a/cmd/blkmap.c +++ b/cmd/blkmap.c @@ -6,7 +6,6 @@ #include #include -#include #include #include #include diff --git a/cmd/blob.c b/cmd/blob.c index 7c77c410d52..a3c1dc49224 100644 --- a/cmd/blob.c +++ b/cmd/blob.c @@ -4,9 +4,9 @@ * Command for encapsulating/decapsulating blob of memory. */ -#include #include #include +#include #include #include #if defined(CONFIG_ARCH_MX6) || defined(CONFIG_ARCH_MX7) || \ diff --git a/cmd/bloblist.c b/cmd/bloblist.c index 26548ecf847..333ae558142 100644 --- a/cmd/bloblist.c +++ b/cmd/bloblist.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/cmd/bmp.c b/cmd/bmp.c index 8f43a40dafd..3b618448624 100644 --- a/cmd/bmp.c +++ b/cmd/bmp.c @@ -8,7 +8,6 @@ * BMP handling routines */ -#include #include #include #include diff --git a/cmd/boot.c b/cmd/boot.c index 14839c1cedc..23496cafdf5 100644 --- a/cmd/boot.c +++ b/cmd/boot.c @@ -7,9 +7,9 @@ /* * Misc boot support */ -#include #include #include +#include #ifdef CONFIG_CMD_GO diff --git a/cmd/bootcount.c b/cmd/bootcount.c index 30ce5dba30d..5e3b66e676b 100644 --- a/cmd/bootcount.c +++ b/cmd/bootcount.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include diff --git a/cmd/bootdev.c b/cmd/bootdev.c index 471189cda48..fa7285ba25e 100644 --- a/cmd/bootdev.c +++ b/cmd/bootdev.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/cmd/bootflow.c b/cmd/bootflow.c index be5d7d8e743..1588f277a4a 100644 --- a/cmd/bootflow.c +++ b/cmd/bootflow.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/cmd/booti.c b/cmd/booti.c index b9637b3ec3d..62b19e83436 100644 --- a/cmd/booti.c +++ b/cmd/booti.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include diff --git a/cmd/bootm.c b/cmd/bootm.c index 9737a2d28c0..545b0c3d823 100644 --- a/cmd/bootm.c +++ b/cmd/bootm.c @@ -7,7 +7,6 @@ /* * Boot support */ -#include #include #include #include diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c index 78184fccab2..977a04b7d76 100644 --- a/cmd/bootmenu.c +++ b/cmd/bootmenu.c @@ -5,7 +5,6 @@ #include #include -#include #include #include #include diff --git a/cmd/bootmeth.c b/cmd/bootmeth.c index f5b01343c48..ebf8b7e2530 100644 --- a/cmd/bootmeth.c +++ b/cmd/bootmeth.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/cmd/bootstage.c b/cmd/bootstage.c index 77a4bc66ff4..5246924f39a 100644 --- a/cmd/bootstage.c +++ b/cmd/bootstage.c @@ -3,9 +3,9 @@ * Copyright (c) 2012, Google Inc. All rights reserved. */ -#include #include #include +#include static int do_bootstage_report(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/bootz.c b/cmd/bootz.c index b6bb4aae72d..55837a7599b 100644 --- a/cmd/bootz.c +++ b/cmd/bootz.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include diff --git a/cmd/broadcom/chimp_boot.c b/cmd/broadcom/chimp_boot.c index 16f2b612c4d..ae0a81179d0 100644 --- a/cmd/broadcom/chimp_boot.c +++ b/cmd/broadcom/chimp_boot.c @@ -3,7 +3,6 @@ * Copyright 2020 Broadcom */ -#include #include #include diff --git a/cmd/broadcom/chimp_handshake.c b/cmd/broadcom/chimp_handshake.c index a90a73a6d74..e2742671963 100644 --- a/cmd/broadcom/chimp_handshake.c +++ b/cmd/broadcom/chimp_handshake.c @@ -3,7 +3,6 @@ * Copyright 2020 Broadcom */ -#include #include #include diff --git a/cmd/broadcom/nitro_image_load.c b/cmd/broadcom/nitro_image_load.c index 93b5cb4cebe..289b184e9af 100644 --- a/cmd/broadcom/nitro_image_load.c +++ b/cmd/broadcom/nitro_image_load.c @@ -3,8 +3,8 @@ * Copyright 2020 Broadcom */ -#include #include +#include #define FW_IMAGE_SIG 0xff123456 #define CFG_IMAGE_SIG 0xcf54321a diff --git a/cmd/btrfs.c b/cmd/btrfs.c index 2843835d08b..69d1b1f830d 100644 --- a/cmd/btrfs.c +++ b/cmd/btrfs.c @@ -3,7 +3,6 @@ * 2017 by Marek Behún */ -#include #include #include #include diff --git a/cmd/button.c b/cmd/button.c index 1b45d0a2a03..3e6db3f5b8e 100644 --- a/cmd/button.c +++ b/cmd/button.c @@ -5,7 +5,6 @@ * Based on led.c */ -#include #include #include #include diff --git a/cmd/cache.c b/cmd/cache.c index b68d45b98bf..0254ff17f9b 100644 --- a/cmd/cache.c +++ b/cmd/cache.c @@ -7,7 +7,6 @@ /* * Cache support: switch on or off, get status */ -#include #include #include #include diff --git a/cmd/cat.c b/cmd/cat.c index 18aa6ca7aa6..6828b7b364e 100644 --- a/cmd/cat.c +++ b/cmd/cat.c @@ -4,7 +4,6 @@ * Roger Knecht */ -#include #include #include #include diff --git a/cmd/cbfs.c b/cmd/cbfs.c index 3cfc9eb2727..c1035461df1 100644 --- a/cmd/cbfs.c +++ b/cmd/cbfs.c @@ -6,10 +6,10 @@ /* * CBFS commands */ -#include #include #include #include +#include static int do_cbfs_init(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/cedit.c b/cmd/cedit.c index 6352e6369d1..fec67a8e334 100644 --- a/cmd/cedit.c +++ b/cmd/cedit.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/cmd/clk.c b/cmd/clk.c index 7bbcbfeda33..6fda6efb1ce 100644 --- a/cmd/clk.c +++ b/cmd/clk.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2013 Xilinx, Inc. */ -#include #include #include #if defined(CONFIG_DM) && defined(CONFIG_CLK) diff --git a/cmd/clone.c b/cmd/clone.c index a9062077571..1f3cff1836d 100644 --- a/cmd/clone.c +++ b/cmd/clone.c @@ -4,11 +4,11 @@ * */ -#include #include #include #include #include +#include #include #define BUFSIZE (1 * 1024 * 1024) diff --git a/cmd/cls.c b/cmd/cls.c index 80d0558d467..4bee8a18305 100644 --- a/cmd/cls.c +++ b/cmd/cls.c @@ -5,7 +5,6 @@ * * cls - clear screen command */ -#include #include #include #include diff --git a/cmd/config.c b/cmd/config.c index cf30841a359..f0d2033c61f 100644 --- a/cmd/config.c +++ b/cmd/config.c @@ -3,7 +3,6 @@ * Copyright (C) 2017 Masahiro Yamada */ -#include #include #include #include diff --git a/cmd/conitrace.c b/cmd/conitrace.c index 9a1bc351848..6cc113328eb 100644 --- a/cmd/conitrace.c +++ b/cmd/conitrace.c @@ -5,7 +5,6 @@ * * Copyright (c) 2018, Heinrich Schuchardt */ -#include #include #include diff --git a/cmd/console.c b/cmd/console.c index 58c2cf1c894..12fc92061a1 100644 --- a/cmd/console.c +++ b/cmd/console.c @@ -7,7 +7,6 @@ /* * Boot support */ -#include #include #include #include diff --git a/cmd/cpu.c b/cmd/cpu.c index 245a82fa3eb..9e323069b9e 100644 --- a/cmd/cpu.c +++ b/cmd/cpu.c @@ -5,7 +5,6 @@ * Copyright (c) 2017 Álvaro Fernández Rojas */ -#include #include #include #include diff --git a/cmd/cramfs.c b/cmd/cramfs.c index 57e2afa2472..b57e2815926 100644 --- a/cmd/cramfs.c +++ b/cmd/cramfs.c @@ -10,7 +10,6 @@ /* * CRAMFS support */ -#include #include #include #include diff --git a/cmd/cros_ec.c b/cmd/cros_ec.c index 90921cecf60..7b60e415b6c 100644 --- a/cmd/cros_ec.c +++ b/cmd/cros_ec.c @@ -6,7 +6,6 @@ * Copyright (c) 2016 National Instruments Corp */ -#include #include #include #include diff --git a/cmd/cyclic.c b/cmd/cyclic.c index ad7fc3b975e..40e966de9aa 100644 --- a/cmd/cyclic.c +++ b/cmd/cyclic.c @@ -8,11 +8,12 @@ * Copyright (C) 2022 Stefan Roese */ -#include #include #include #include #include +#include +#include #include struct cyclic_demo_info { diff --git a/cmd/date.c b/cmd/date.c index 4f98b470ca2..755adec1e71 100644 --- a/cmd/date.c +++ b/cmd/date.c @@ -7,7 +7,6 @@ /* * RTC, Date & Time support: get and set date & time */ -#include #include #include #include diff --git a/cmd/demo.c b/cmd/demo.c index ebd5a241c36..5c422ac165b 100644 --- a/cmd/demo.c +++ b/cmd/demo.c @@ -6,7 +6,6 @@ * Pavel Herrmann */ -#include #include #include #include diff --git a/cmd/dfu.c b/cmd/dfu.c index d7bfb535dc6..46f0190588e 100644 --- a/cmd/dfu.c +++ b/cmd/dfu.c @@ -10,7 +10,6 @@ * Lukasz Majewski */ -#include #include #include #include diff --git a/cmd/diag.c b/cmd/diag.c index f51536dbfaa..c6da5aae3fc 100644 --- a/cmd/diag.c +++ b/cmd/diag.c @@ -7,7 +7,6 @@ /* * Diagnostics support */ -#include #include #include diff --git a/cmd/disk.c b/cmd/disk.c index 92eaa02f4a1..2efc3ca4b1a 100644 --- a/cmd/disk.c +++ b/cmd/disk.c @@ -3,7 +3,6 @@ * (C) Copyright 2000-2011 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include diff --git a/cmd/dm.c b/cmd/dm.c index fb605c2da1a..ec9cfd85376 100644 --- a/cmd/dm.c +++ b/cmd/dm.c @@ -6,7 +6,6 @@ * Marek Vasut */ -#include #include #include #include diff --git a/cmd/echo.c b/cmd/echo.c index fda844ee9d3..973213a03a6 100644 --- a/cmd/echo.c +++ b/cmd/echo.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include static int do_echo(struct cmd_tbl *cmdtp, int flag, int argc, diff --git a/cmd/eeprom.c b/cmd/eeprom.c index 322765ad02a..26f3750a80a 100644 --- a/cmd/eeprom.c +++ b/cmd/eeprom.c @@ -19,12 +19,12 @@ * */ -#include #include #include #include #include #include +#include #include #ifndef I2C_RXTX_LEN diff --git a/cmd/efi.c b/cmd/efi.c index 6cd5361aca5..6bed2d743ba 100644 --- a/cmd/efi.c +++ b/cmd/efi.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/cmd/efi_common.c b/cmd/efi_common.c index 1aa2351fcdf..c46764e6eea 100644 --- a/cmd/efi_common.c +++ b/cmd/efi_common.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/cmd/eficonfig.c b/cmd/eficonfig.c index 0ba92c60e03..4164cb4f9b8 100644 --- a/cmd/eficonfig.c +++ b/cmd/eficonfig.c @@ -7,7 +7,6 @@ #include #include -#include #include #include #include diff --git a/cmd/eficonfig_sbkey.c b/cmd/eficonfig_sbkey.c index caca27495e0..b3325a540f9 100644 --- a/cmd/eficonfig_sbkey.c +++ b/cmd/eficonfig_sbkey.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/cmd/efidebug.c b/cmd/efidebug.c index c2c525f2351..e978e74aad9 100644 --- a/cmd/efidebug.c +++ b/cmd/efidebug.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/cmd/elf.c b/cmd/elf.c index df4354d3742..a02361f9f51 100644 --- a/cmd/elf.c +++ b/cmd/elf.c @@ -4,7 +4,6 @@ * All rights reserved. */ -#include #include #include #include diff --git a/cmd/ethsw.c b/cmd/ethsw.c index f8b8a798bf6..4bf49ac598f 100644 --- a/cmd/ethsw.c +++ b/cmd/ethsw.c @@ -5,13 +5,13 @@ * Ethernet Switch commands */ -#include #include #include #include #include #include #include +#include static const char *ethsw_name; diff --git a/cmd/event.c b/cmd/event.c index f6cdb55fc91..00c828757ca 100644 --- a/cmd/event.c +++ b/cmd/event.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include diff --git a/cmd/exit.c b/cmd/exit.c index 7bf241ec732..d125ec1e31f 100644 --- a/cmd/exit.c +++ b/cmd/exit.c @@ -4,8 +4,8 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include +#include static int do_exit(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/ext2.c b/cmd/ext2.c index a0ce0cf5796..45c8b353b58 100644 --- a/cmd/ext2.c +++ b/cmd/ext2.c @@ -19,7 +19,6 @@ /* * Ext2fs support */ -#include #include #include diff --git a/cmd/ext4.c b/cmd/ext4.c index 4791b69fd96..40d1fe30d5e 100644 --- a/cmd/ext4.c +++ b/cmd/ext4.c @@ -25,7 +25,6 @@ * file in uboot. Added ext4fs ls load and write support. */ -#include #include #include #include diff --git a/cmd/extension_board.c b/cmd/extension_board.c index 2b672d888c6..f43bf680858 100644 --- a/cmd/extension_board.c +++ b/cmd/extension_board.c @@ -4,7 +4,6 @@ * Köry Maincent, Bootlin, */ -#include #include #include #include diff --git a/cmd/fastboot.c b/cmd/fastboot.c index c3c19231c98..d4cfc0c7a28 100644 --- a/cmd/fastboot.c +++ b/cmd/fastboot.c @@ -6,7 +6,6 @@ * (C) Copyright 2014 Linaro, Ltd. * Rob Herring */ -#include #include #include #include diff --git a/cmd/fat.c b/cmd/fat.c index 69ce1fa5300..ad0e5ed7d60 100644 --- a/cmd/fat.c +++ b/cmd/fat.c @@ -7,7 +7,6 @@ /* * Boot support */ -#include #include #include #include diff --git a/cmd/fdt.c b/cmd/fdt.c index 331564c13be..d16b141ce32 100644 --- a/cmd/fdt.c +++ b/cmd/fdt.c @@ -7,7 +7,6 @@ * Matthew McClintock */ -#include #include #include #include diff --git a/cmd/flash.c b/cmd/flash.c index f4f85ecc7a8..de0e04f09cf 100644 --- a/cmd/flash.c +++ b/cmd/flash.c @@ -7,9 +7,9 @@ /* * FLASH support */ -#include #include #include +#include #include #if defined(CONFIG_CMD_MTDPARTS) diff --git a/cmd/font.c b/cmd/font.c index cb39c88063f..ebde094b0a5 100644 --- a/cmd/font.c +++ b/cmd/font.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/cmd/fpga.c b/cmd/fpga.c index 8c64e957db0..93f14098ccb 100644 --- a/cmd/fpga.c +++ b/cmd/fpga.c @@ -7,7 +7,6 @@ /* * FPGA support */ -#include #include #include #include diff --git a/cmd/fpgad.c b/cmd/fpgad.c index dfc6220b5e0..b4bfaa12165 100644 --- a/cmd/fpgad.c +++ b/cmd/fpgad.c @@ -8,10 +8,10 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include +#include #include diff --git a/cmd/fs.c b/cmd/fs.c index 46cb43dcdb5..3d7e06d6f1e 100644 --- a/cmd/fs.c +++ b/cmd/fs.c @@ -5,7 +5,6 @@ * Inspired by cmd_ext_common.c, cmd_fat.c. */ -#include #include #include diff --git a/cmd/fs_uuid.c b/cmd/fs_uuid.c index 5dc94aa6408..5f7770d09ac 100644 --- a/cmd/fs_uuid.c +++ b/cmd/fs_uuid.c @@ -5,7 +5,6 @@ * Copyright (C) 2014, Bachmann electronic GmbH */ -#include #include #include diff --git a/cmd/fuse.c b/cmd/fuse.c index f884c894fb0..598ef496a43 100644 --- a/cmd/fuse.c +++ b/cmd/fuse.c @@ -8,11 +8,11 @@ * Martha Marx */ -#include #include #include #include #include +#include #include static int strtou32(const char *str, unsigned int base, u32 *result) diff --git a/cmd/gettime.c b/cmd/gettime.c index 2e74e02b499..fc307efce8c 100644 --- a/cmd/gettime.c +++ b/cmd/gettime.c @@ -11,8 +11,8 @@ /* * Get Timer overflows after 2^32 / CONFIG_SYS_HZ (32Khz) = 131072 sec */ -#include #include +#include static int do_gettime(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/gpio.c b/cmd/gpio.c index dab6f7097ae..7a43dc6ab18 100644 --- a/cmd/gpio.c +++ b/cmd/gpio.c @@ -6,7 +6,6 @@ * Licensed under the GPL-2 or later. */ -#include #include #include #include diff --git a/cmd/gpt.c b/cmd/gpt.c index 7aaf1889a5a..36b112d5978 100644 --- a/cmd/gpt.c +++ b/cmd/gpt.c @@ -10,7 +10,6 @@ * author: Piotr Wilczek */ -#include #include #include #include diff --git a/cmd/hash.c b/cmd/hash.c index 5534a735fa7..60d482b7f87 100644 --- a/cmd/hash.c +++ b/cmd/hash.c @@ -9,7 +9,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include diff --git a/cmd/help.c b/cmd/help.c index 9f8393eefd8..56579e28d31 100644 --- a/cmd/help.c +++ b/cmd/help.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include static int do_help(struct cmd_tbl *cmdtp, int flag, int argc, diff --git a/cmd/history.c b/cmd/history.c index b6bf4670b1c..8972986ca9d 100644 --- a/cmd/history.c +++ b/cmd/history.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include diff --git a/cmd/host.c b/cmd/host.c index c33c2a9787e..e03576b4d2d 100644 --- a/cmd/host.c +++ b/cmd/host.c @@ -3,7 +3,6 @@ * Copyright (c) 2012, Google Inc. */ -#include #include #include #include diff --git a/cmd/i2c.c b/cmd/i2c.c index 80831561c67..7dac0a9fb6c 100644 --- a/cmd/i2c.c +++ b/cmd/i2c.c @@ -64,7 +64,6 @@ * Adapted from cmd_mem.c which is copyright Wolfgang Denk (wd@denx.de). */ -#include #include #include #include diff --git a/cmd/ide.c b/cmd/ide.c index ddc87d3a0bb..036489fda97 100644 --- a/cmd/ide.c +++ b/cmd/ide.c @@ -8,7 +8,6 @@ * IDE support */ -#include #include #include #include diff --git a/cmd/ini.c b/cmd/ini.c index 35de2373e60..96399017691 100644 --- a/cmd/ini.c +++ b/cmd/ini.c @@ -11,9 +11,9 @@ * http://code.google.com/p/inih/ */ -#include #include #include +#include #include #include diff --git a/cmd/io.c b/cmd/io.c index 2de1111998f..617373d3cb7 100644 --- a/cmd/io.c +++ b/cmd/io.c @@ -7,9 +7,9 @@ * IO space access commands. */ -#include #include #include +#include #include /* Display values from last command */ diff --git a/cmd/iotrace.c b/cmd/iotrace.c index f28359e2875..0a041ed8652 100644 --- a/cmd/iotrace.c +++ b/cmd/iotrace.c @@ -3,9 +3,9 @@ * Copyright (c) 2014 Google, Inc */ -#include #include #include +#include static void do_print_stats(void) { diff --git a/cmd/irq.c b/cmd/irq.c index 1d3e28cb3ce..655aba576a8 100644 --- a/cmd/irq.c +++ b/cmd/irq.c @@ -3,7 +3,6 @@ * Copyright 2008 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/cmd/itest.c b/cmd/itest.c index 74414cbdc4c..b79512a505d 100644 --- a/cmd/itest.c +++ b/cmd/itest.c @@ -11,11 +11,11 @@ * A few parts were lifted from bash 'test' command */ -#include #include #include #include #include +#include #include diff --git a/cmd/jffs2.c b/cmd/jffs2.c index e00fcc20226..89d336f5958 100644 --- a/cmd/jffs2.c +++ b/cmd/jffs2.c @@ -70,7 +70,6 @@ /* * JFFS2/CRAMFS support */ -#include #include #include #if defined(CONFIG_CMD_FLASH) diff --git a/cmd/kaslrseed.c b/cmd/kaslrseed.c index 9acb8e16386..e0d3c7fe748 100644 --- a/cmd/kaslrseed.c +++ b/cmd/kaslrseed.c @@ -6,7 +6,6 @@ * Copyright (c) 2021, Chris Morgan */ -#include #include #include #include diff --git a/cmd/led.c b/cmd/led.c index 48a02baf509..4256b3429c2 100644 --- a/cmd/led.c +++ b/cmd/led.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/cmd/legacy-mtd-utils.c b/cmd/legacy-mtd-utils.c index 5903a90fe53..1a5271000bf 100644 --- a/cmd/legacy-mtd-utils.c +++ b/cmd/legacy-mtd-utils.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/cmd/legacy_led.c b/cmd/legacy_led.c index 5256255f052..50de7e89d8f 100644 --- a/cmd/legacy_led.c +++ b/cmd/legacy_led.c @@ -9,10 +9,9 @@ * Ulf Samuelsson */ -#include -#include #include #include +#include struct led_tbl_s { char *string; /* String for use in the command */ diff --git a/cmd/license.c b/cmd/license.c index 15411b5a92d..161663ff29c 100644 --- a/cmd/license.c +++ b/cmd/license.c @@ -4,7 +4,6 @@ * Author: Harald Welte */ -#include #include #include #include diff --git a/cmd/load.c b/cmd/load.c index 540361b43f0..ace1c52f90a 100644 --- a/cmd/load.c +++ b/cmd/load.c @@ -7,7 +7,6 @@ /* * Serial up- and download support */ -#include #include #include #include diff --git a/cmd/log.c b/cmd/log.c index c9a23e4ae0d..519ec76f3b5 100644 --- a/cmd/log.c +++ b/cmd/log.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/cmd/lsblk.c b/cmd/lsblk.c index d214dafc3be..7c00bfdc7a0 100644 --- a/cmd/lsblk.c +++ b/cmd/lsblk.c @@ -4,7 +4,6 @@ * Niel Fourie, DENX Software Engineering, lusus@denx.de. */ -#include #include #include #include diff --git a/cmd/lzmadec.c b/cmd/lzmadec.c index 81924da4618..c40b96941b4 100644 --- a/cmd/lzmadec.c +++ b/cmd/lzmadec.c @@ -9,10 +9,10 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include +#include #include #include diff --git a/cmd/mbr.c b/cmd/mbr.c index ec99b662834..7e1f92a13bb 100644 --- a/cmd/mbr.c +++ b/cmd/mbr.c @@ -8,11 +8,11 @@ * based on the gpt command. */ -#include #include #include #include #include +#include /** * extract_val() - Extract a value from the key=value pair list diff --git a/cmd/mdio.c b/cmd/mdio.c index 3c74326161e..c0a87087d31 100644 --- a/cmd/mdio.c +++ b/cmd/mdio.c @@ -8,7 +8,6 @@ * MDIO Commands */ -#include #include #include #include diff --git a/cmd/mem.c b/cmd/mem.c index 768057e4d3f..4989d27f2ab 100644 --- a/cmd/mem.c +++ b/cmd/mem.c @@ -10,7 +10,6 @@ * Copied from FADS ROM, Dan Malek (dmalek@jlc.net) */ -#include #include #include #include @@ -24,6 +23,7 @@ #include #include #include +#include #include #include #include diff --git a/cmd/meson/sm.c b/cmd/meson/sm.c index de9a242e17f..b69f8123ee2 100644 --- a/cmd/meson/sm.c +++ b/cmd/meson/sm.c @@ -9,11 +9,11 @@ */ #include -#include #include #include #include #include +#include static int do_sm_serial(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/mii.c b/cmd/mii.c index fab420ee29e..ce372489692 100644 --- a/cmd/mii.c +++ b/cmd/mii.c @@ -8,7 +8,6 @@ * MII Utilities */ -#include #include #include #include diff --git a/cmd/misc.c b/cmd/misc.c index ec32b41ed1e..792d9723c75 100644 --- a/cmd/misc.c +++ b/cmd/misc.c @@ -8,7 +8,6 @@ * A command interface to access misc devices with MISC uclass driver APIs. */ -#include #include #include #include diff --git a/cmd/mmc.c b/cmd/mmc.c index 2d5430a5307..7244a90f4dc 100644 --- a/cmd/mmc.c +++ b/cmd/mmc.c @@ -4,7 +4,6 @@ * Kyle Harris, kharris@nexus-tech.net */ -#include #include #include #include @@ -14,6 +13,7 @@ #include #include #include +#include static int curr_device = -1; diff --git a/cmd/mp.c b/cmd/mp.c index 1b4373f2587..b9b5e016246 100644 --- a/cmd/mp.c +++ b/cmd/mp.c @@ -3,9 +3,9 @@ * Copyright 2008-2009 Freescale Semiconductor, Inc. */ -#include #include #include +#include static int cpu_status_all(void) { diff --git a/cmd/mtd.c b/cmd/mtd.c index 9189f45cabd..795aaa2b37d 100644 --- a/cmd/mtd.c +++ b/cmd/mtd.c @@ -9,7 +9,6 @@ */ #include -#include #include #if CONFIG_IS_ENABLED(CMD_MTD_OTP) #include diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c index b31db73ebfc..f57d84dbb3a 100644 --- a/cmd/mtdparts.c +++ b/cmd/mtdparts.c @@ -70,7 +70,6 @@ * */ -#include #include #include #include diff --git a/cmd/mux.c b/cmd/mux.c index 388fb0878a8..2f6c08b8b07 100644 --- a/cmd/mux.c +++ b/cmd/mux.c @@ -6,7 +6,6 @@ * Author: Pratyush Yadav */ -#include #include #include #include diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c index 744b1c20aa8..e3f21dd0d81 100644 --- a/cmd/mvebu/bubt.c +++ b/cmd/mvebu/bubt.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/cmd/mvebu/comphy_rx_training.c b/cmd/mvebu/comphy_rx_training.c index 4ee8f54ea9c..5653877cd4a 100644 --- a/cmd/mvebu/comphy_rx_training.c +++ b/cmd/mvebu/comphy_rx_training.c @@ -5,7 +5,6 @@ * SPDX-License-Identifier: GPL-2.0 */ -#include #include #include #include diff --git a/cmd/nand.c b/cmd/nand.c index fe834c4ac5c..5a328e0acdd 100644 --- a/cmd/nand.c +++ b/cmd/nand.c @@ -23,7 +23,6 @@ * only */ -#include #include #include #include diff --git a/cmd/net.c b/cmd/net.c index d407d8320a3..b206ff58e68 100644 --- a/cmd/net.c +++ b/cmd/net.c @@ -9,7 +9,6 @@ /* * Boot support */ -#include #include #include #include diff --git a/cmd/nvedit.c b/cmd/nvedit.c index e77338f8139..98a687bcabb 100644 --- a/cmd/nvedit.c +++ b/cmd/nvedit.c @@ -23,7 +23,7 @@ * environment. After that, we use a hash table. */ -#include +#include #include #include #include diff --git a/cmd/nvedit_efi.c b/cmd/nvedit_efi.c index 7a30b5cc8f8..64ae2ad2ce2 100644 --- a/cmd/nvedit_efi.c +++ b/cmd/nvedit_efi.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/cmd/nvme.c b/cmd/nvme.c index 09d5f438fb1..f2c9acba5c3 100644 --- a/cmd/nvme.c +++ b/cmd/nvme.c @@ -4,7 +4,6 @@ * Copyright (C) 2017 Bin Meng */ -#include #include #include #include diff --git a/cmd/onenand.c b/cmd/onenand.c index fad781583a3..6e808ce3fce 100644 --- a/cmd/onenand.c +++ b/cmd/onenand.c @@ -9,7 +9,6 @@ * published by the Free Software Foundation. */ -#include #include #include #include diff --git a/cmd/optee_rpmb.c b/cmd/optee_rpmb.c index b3cafd92410..b155278ee2a 100644 --- a/cmd/optee_rpmb.c +++ b/cmd/optee_rpmb.c @@ -4,7 +4,6 @@ */ #include -#include #include #include #include diff --git a/cmd/osd.c b/cmd/osd.c index 210bc5d4c23..5671338d9e7 100644 --- a/cmd/osd.c +++ b/cmd/osd.c @@ -9,7 +9,6 @@ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de */ -#include #include #include #include diff --git a/cmd/panic.c b/cmd/panic.c index f13b3f094fa..7c0affa5eb5 100644 --- a/cmd/panic.c +++ b/cmd/panic.c @@ -3,7 +3,7 @@ * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH */ -#include +#include #include static int do_panic(struct cmd_tbl *cmdtp, int flag, int argc, diff --git a/cmd/part.c b/cmd/part.c index c75f85acd52..d140a1eddb9 100644 --- a/cmd/part.c +++ b/cmd/part.c @@ -15,7 +15,6 @@ * Pavel Bartusek */ -#include #include #include #include diff --git a/cmd/pcap.c b/cmd/pcap.c index a0149203fad..8d610966c13 100644 --- a/cmd/pcap.c +++ b/cmd/pcap.c @@ -4,8 +4,8 @@ * Ramon Fried */ -#include #include +#include #include #include diff --git a/cmd/pci.c b/cmd/pci.c index d89e71c16a0..3c0aed50cae 100644 --- a/cmd/pci.c +++ b/cmd/pci.c @@ -12,7 +12,6 @@ * PCI routines */ -#include #include #include #include diff --git a/cmd/pci_mps.c b/cmd/pci_mps.c index 98161da93a0..19e71db8cbd 100644 --- a/cmd/pci_mps.c +++ b/cmd/pci_mps.c @@ -6,7 +6,6 @@ * PCI Express Maximum Packet Size (MPS) configuration */ -#include #include #include #include diff --git a/cmd/pinmux.c b/cmd/pinmux.c index 105f01eaaff..01f3e4af6ce 100644 --- a/cmd/pinmux.c +++ b/cmd/pinmux.c @@ -3,7 +3,6 @@ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved */ -#include #include #include #include diff --git a/cmd/pmc.c b/cmd/pmc.c index 9a3ba2bffc5..1a3416fb2a9 100644 --- a/cmd/pmc.c +++ b/cmd/pmc.c @@ -5,7 +5,6 @@ * Copyright 2019 Google LLC */ -#include #include #include #include diff --git a/cmd/pmic.c b/cmd/pmic.c index c9e9730adf9..3ad1b8aa375 100644 --- a/cmd/pmic.c +++ b/cmd/pmic.c @@ -3,7 +3,6 @@ * Copyright (C) 2014-2015 Samsung Electronics * Przemyslaw Marczak */ -#include #include #include #include diff --git a/cmd/printf.c b/cmd/printf.c index 0c6887e0d6e..a1727ac15a2 100644 --- a/cmd/printf.c +++ b/cmd/printf.c @@ -84,12 +84,12 @@ * We try to be compatible. */ -#include #include #include #include #include #include +#include #define WANT_HEX_ESCAPES 0 #define PRINT_CONVERSION_ERROR 1 diff --git a/cmd/pvblock.c b/cmd/pvblock.c index 1b604c37373..3a83ac9cd92 100644 --- a/cmd/pvblock.c +++ b/cmd/pvblock.c @@ -6,7 +6,6 @@ */ #include -#include #include /* Current I/O Device */ diff --git a/cmd/pxe.c b/cmd/pxe.c index 21134eb7a30..ae02c28c075 100644 --- a/cmd/pxe.c +++ b/cmd/pxe.c @@ -4,12 +4,12 @@ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. */ -#include #include #include #include #include #include +#include #include "pxe_utils.h" diff --git a/cmd/qfw.c b/cmd/qfw.c index 1b8c775ebf5..1b108118658 100644 --- a/cmd/qfw.c +++ b/cmd/qfw.c @@ -3,7 +3,6 @@ * (C) Copyright 2015 Miao Yan */ -#include #include #include #include diff --git a/cmd/read.c b/cmd/read.c index 1218e7acfd0..af54bd17654 100644 --- a/cmd/read.c +++ b/cmd/read.c @@ -8,10 +8,10 @@ * Software Foundation. */ -#include #include #include #include +#include static int do_rw(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/reginfo.c b/cmd/reginfo.c index c8a04b1754e..53b8bc41bfe 100644 --- a/cmd/reginfo.c +++ b/cmd/reginfo.c @@ -4,7 +4,6 @@ * Subodh Nijsure, SkyStream Networks, snijsure@skystream.com */ -#include #include #include diff --git a/cmd/regulator.c b/cmd/regulator.c index 635a9add585..da298090bb7 100644 --- a/cmd/regulator.c +++ b/cmd/regulator.c @@ -3,7 +3,6 @@ * Copyright (C) 2014-2015 Samsung Electronics * Przemyslaw Marczak */ -#include #include #include #include diff --git a/cmd/remoteproc.c b/cmd/remoteproc.c index ea8724a187d..3c5b6a05b1a 100644 --- a/cmd/remoteproc.c +++ b/cmd/remoteproc.c @@ -3,7 +3,6 @@ * (C) Copyright 2015 * Texas Instruments Incorporated - https://www.ti.com/ */ -#include #include #include #include diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c index 2d8ee7e5bbb..a231604e492 100644 --- a/cmd/riscv/sbi.c +++ b/cmd/riscv/sbi.c @@ -5,7 +5,6 @@ * Copyright (c) 2020, Heinrich Schuchardt */ -#include #include #include diff --git a/cmd/rkmtd.c b/cmd/rkmtd.c index 5b80427cb94..a870c119110 100644 --- a/cmd/rkmtd.c +++ b/cmd/rkmtd.c @@ -8,7 +8,6 @@ * Copyright (C) 2023 Johan Jonker */ -#include #include #include #include diff --git a/cmd/rng.c b/cmd/rng.c index e5ab8681122..2fb7202303a 100644 --- a/cmd/rng.c +++ b/cmd/rng.c @@ -4,7 +4,6 @@ * * Copyright (c) 2019, Heinrich Schuchardt */ -#include #include #include #include diff --git a/cmd/rockusb.c b/cmd/rockusb.c index 07088564a10..48497aa8764 100644 --- a/cmd/rockusb.c +++ b/cmd/rockusb.c @@ -3,7 +3,6 @@ * Copyright (C) 2017 Eddie Cai */ -#include #include #include #include diff --git a/cmd/rtc.c b/cmd/rtc.c index a344cfa76b1..a931fd9d54f 100644 --- a/cmd/rtc.c +++ b/cmd/rtc.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/cmd/sata.c b/cmd/sata.c index 9c9fe111d12..8b923f9378b 100644 --- a/cmd/sata.c +++ b/cmd/sata.c @@ -9,7 +9,6 @@ * Dave Liu */ -#include #include #include #include diff --git a/cmd/sb.c b/cmd/sb.c index 0d55818e3c6..1aa5921f03e 100644 --- a/cmd/sb.c +++ b/cmd/sb.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/cmd/scp03.c b/cmd/scp03.c index 2b8d5aecf34..9c749d19af8 100644 --- a/cmd/scp03.c +++ b/cmd/scp03.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/cmd/scsi.c b/cmd/scsi.c index c501d7f456d..c286bdc0726 100644 --- a/cmd/scsi.c +++ b/cmd/scsi.c @@ -7,7 +7,6 @@ /* * SCSI support. */ -#include #include #include #include diff --git a/cmd/seama.c b/cmd/seama.c index 3aafb43c48a..3c8e8199234 100644 --- a/cmd/seama.c +++ b/cmd/seama.c @@ -4,7 +4,6 @@ * Support for the "SEAttle iMAge" SEAMA NAND image format */ -#include #include #include diff --git a/cmd/setexpr.c b/cmd/setexpr.c index ab76824a32b..e111b8ba98a 100644 --- a/cmd/setexpr.c +++ b/cmd/setexpr.c @@ -8,7 +8,6 @@ * This file provides a shell like 'expr' function to return. */ -#include #include #include #include @@ -16,6 +15,8 @@ #include #include #include +#include +#include #include #include "printf.h" diff --git a/cmd/sf.c b/cmd/sf.c index e3866899f6c..f43a2e08b31 100644 --- a/cmd/sf.c +++ b/cmd/sf.c @@ -5,7 +5,6 @@ * Copyright (C) 2008 Atmel Corporation */ -#include #include #include #include @@ -14,6 +13,7 @@ #include #include #include +#include #include #include #include diff --git a/cmd/sha1sum.c b/cmd/sha1sum.c index bcc665a5a6c..52aa26c78d2 100644 --- a/cmd/sha1sum.c +++ b/cmd/sha1sum.c @@ -7,7 +7,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include diff --git a/cmd/sleep.c b/cmd/sleep.c index c741b4aa029..7616fed7556 100644 --- a/cmd/sleep.c +++ b/cmd/sleep.c @@ -4,9 +4,10 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include +#include +#include #include static int do_sleep(struct cmd_tbl *cmdtp, int flag, int argc, diff --git a/cmd/smccc.c b/cmd/smccc.c index fb80431ad1d..3a4d885e37e 100644 --- a/cmd/smccc.c +++ b/cmd/smccc.c @@ -4,8 +4,8 @@ * Michalis Pappas */ #include -#include #include +#include #include #include #include diff --git a/cmd/sound.c b/cmd/sound.c index 0b7f9599716..08bf74112f1 100644 --- a/cmd/sound.c +++ b/cmd/sound.c @@ -4,7 +4,6 @@ * Rajeshwari Shinde */ -#include #include #include #include diff --git a/cmd/source.c b/cmd/source.c index 0ba9736b1ab..c9b5f8e400a 100644 --- a/cmd/source.c +++ b/cmd/source.c @@ -14,7 +14,6 @@ /* #define DEBUG */ -#include #include #include #include diff --git a/cmd/spi.c b/cmd/spi.c index f30018f33be..ea30c854c21 100644 --- a/cmd/spi.c +++ b/cmd/spi.c @@ -8,7 +8,6 @@ * SPI Read/Write Utilities */ -#include #include #include #include diff --git a/cmd/spl.c b/cmd/spl.c index 8a2ded72be9..d1f47c7316b 100644 --- a/cmd/spl.c +++ b/cmd/spl.c @@ -4,7 +4,6 @@ * Corscience GmbH & Co. KG - Simon Schwarz */ -#include #include #include #include diff --git a/cmd/stackprot_test.c b/cmd/stackprot_test.c index f3470288fac..e7ff4a06158 100644 --- a/cmd/stackprot_test.c +++ b/cmd/stackprot_test.c @@ -3,7 +3,6 @@ * Copyright 2021 Broadcom */ -#include #include static int do_test_stackprot_fail(struct cmd_tbl *cmdtp, int flag, int argc, diff --git a/cmd/strings.c b/cmd/strings.c index bf348afce81..5bcb0f2b567 100644 --- a/cmd/strings.c +++ b/cmd/strings.c @@ -7,8 +7,8 @@ */ #include -#include #include +#include static char *start_addr, *last_addr; diff --git a/cmd/sysboot.c b/cmd/sysboot.c index d14c570d96a..0ea08fd7b53 100644 --- a/cmd/sysboot.c +++ b/cmd/sysboot.c @@ -1,10 +1,10 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include #include +#include /** * struct sysboot_info - useful information for sysboot helpers diff --git a/cmd/temperature.c b/cmd/temperature.c index 420965de143..41e422fc937 100644 --- a/cmd/temperature.c +++ b/cmd/temperature.c @@ -5,7 +5,6 @@ * Written by Robert Marko */ -#include #include #include #include diff --git a/cmd/terminal.c b/cmd/terminal.c index 9e32a4191e1..369a755e0f5 100644 --- a/cmd/terminal.c +++ b/cmd/terminal.c @@ -7,7 +7,6 @@ /* * Boot support */ -#include #include #include #include diff --git a/cmd/test.c b/cmd/test.c index fa7c48fb9f1..b4c3eabf9f6 100644 --- a/cmd/test.c +++ b/cmd/test.c @@ -4,10 +4,10 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include +#include #define OP_INVALID 0 #define OP_NOT 1 diff --git a/cmd/thordown.c b/cmd/thordown.c index 48e22b31d02..70061bf8d4c 100644 --- a/cmd/thordown.c +++ b/cmd/thordown.c @@ -6,7 +6,6 @@ * All rights reserved. */ -#include #include #include #include diff --git a/cmd/ti/ddr3.c b/cmd/ti/ddr3.c index bbd406fc66e..70ce53d01e8 100644 --- a/cmd/ti/ddr3.c +++ b/cmd/ti/ddr3.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include diff --git a/cmd/ti/pd.c b/cmd/ti/pd.c index a0492a5fdee..305023af1e7 100644 --- a/cmd/ti/pd.c +++ b/cmd/ti/pd.c @@ -5,7 +5,6 @@ * Copyright (C) 2020 Texas Instruments Incorporated, */ -#include #include #include #include diff --git a/cmd/time.c b/cmd/time.c index db8c1892df4..eee6084e968 100644 --- a/cmd/time.c +++ b/cmd/time.c @@ -3,7 +3,6 @@ * Copyright (c) 2011 The Chromium OS Authors. */ -#include #include static void report_time(ulong cycles) diff --git a/cmd/timer.c b/cmd/timer.c index 551be5dd54e..04fcd84ac6a 100644 --- a/cmd/timer.c +++ b/cmd/timer.c @@ -4,8 +4,8 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include +#include static int do_timer(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c index 57cfd355df1..0aec7521770 100644 --- a/cmd/tlv_eeprom.c +++ b/cmd/tlv_eeprom.c @@ -9,7 +9,6 @@ * Copyright (C) 2014,2016 david_yang */ -#include #include #include #include diff --git a/cmd/tpm-common.c b/cmd/tpm-common.c index a7dc23d85d5..1cd57f901b6 100644 --- a/cmd/tpm-common.c +++ b/cmd/tpm-common.c @@ -3,7 +3,6 @@ * Copyright (c) 2013 The Chromium OS Authors. */ -#include #include #include #include diff --git a/cmd/tpm-v1.c b/cmd/tpm-v1.c index 1b1efcd204d..6e019d1c729 100644 --- a/cmd/tpm-v1.c +++ b/cmd/tpm-v1.c @@ -3,10 +3,10 @@ * Copyright (c) 2013 The Chromium OS Authors. */ -#include #include #include #include +#include #include #include #include diff --git a/cmd/tpm-v2.c b/cmd/tpm-v2.c index 7e479b9dfe3..99c540b26de 100644 --- a/cmd/tpm-v2.c +++ b/cmd/tpm-v2.c @@ -4,7 +4,6 @@ * Author: Miquel Raynal */ -#include #include #include #include diff --git a/cmd/tpm_test.c b/cmd/tpm_test.c index c7fa6e775f5..9c8b1c74384 100644 --- a/cmd/tpm_test.c +++ b/cmd/tpm_test.c @@ -3,10 +3,10 @@ * Copyright (c) 2015 Google, Inc */ -#include #include #include #include +#include #include #include #include "tpm-user-utils.h" diff --git a/cmd/trace.c b/cmd/trace.c index 2e3ee1d3ba2..937e6a682ad 100644 --- a/cmd/trace.c +++ b/cmd/trace.c @@ -3,11 +3,11 @@ * Copyright (c) 2011 The Chromium OS Authors. */ -#include #include #include #include #include +#include #include static int get_args(int argc, char *const argv[], char **buff, diff --git a/cmd/tsi148.c b/cmd/tsi148.c index 0d849d9979e..113b4e67330 100644 --- a/cmd/tsi148.c +++ b/cmd/tsi148.c @@ -7,10 +7,10 @@ * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com */ -#include #include #include #include +#include #include #include diff --git a/cmd/ubi.c b/cmd/ubi.c index 0a6a80bdd10..8c1b5df0572 100644 --- a/cmd/ubi.c +++ b/cmd/ubi.c @@ -11,7 +11,6 @@ * published by the Free Software Foundation. */ -#include #include #include #include diff --git a/cmd/ubifs.c b/cmd/ubifs.c index 2a035bc7ae6..8fd39032ecc 100644 --- a/cmd/ubifs.c +++ b/cmd/ubifs.c @@ -11,11 +11,11 @@ #undef DEBUG -#include #include #include #include #include +#include static int ubifs_initialized; static int ubifs_mounted; diff --git a/cmd/ufs.c b/cmd/ufs.c index 536bd85b75d..6e21fbb1685 100644 --- a/cmd/ufs.c +++ b/cmd/ufs.c @@ -5,9 +5,9 @@ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com * */ -#include #include #include +#include static int do_ufs(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { diff --git a/cmd/universe.c b/cmd/universe.c index fb3a32d4d5a..d1a712829d0 100644 --- a/cmd/universe.c +++ b/cmd/universe.c @@ -3,9 +3,9 @@ * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com */ -#include #include #include +#include #include #include diff --git a/cmd/unlz4.c b/cmd/unlz4.c index 5f20838e899..fc5200117ad 100644 --- a/cmd/unlz4.c +++ b/cmd/unlz4.c @@ -4,9 +4,9 @@ * FUJITSU COMPUTERTECHNOLOGIES LIMITED. All rights reserved. */ -#include #include #include +#include #include static int do_unlz4(struct cmd_tbl *cmdtp, int flag, int argc, diff --git a/cmd/unzip.c b/cmd/unzip.c index bc6cee06043..e7a3f9808b2 100644 --- a/cmd/unzip.c +++ b/cmd/unzip.c @@ -4,12 +4,12 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include #include #include +#include static int do_unzip(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/usb.c b/cmd/usb.c index 23253f22231..3a3764a5b86 100644 --- a/cmd/usb.c +++ b/cmd/usb.c @@ -10,7 +10,6 @@ * project. */ -#include #include #include #include diff --git a/cmd/usb_gadget_sdp.c b/cmd/usb_gadget_sdp.c index cbdda733533..39259a3b092 100644 --- a/cmd/usb_gadget_sdp.c +++ b/cmd/usb_gadget_sdp.c @@ -6,7 +6,6 @@ * Author: Stefan Agner */ -#include #include #include #include diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c index 751701fe73a..47e8b70cd10 100644 --- a/cmd/usb_mass_storage.c +++ b/cmd/usb_mass_storage.c @@ -6,7 +6,6 @@ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. */ -#include #include #include #include diff --git a/cmd/vbe.c b/cmd/vbe.c index 0e84b0e97aa..423d9e5f8f0 100644 --- a/cmd/vbe.c +++ b/cmd/vbe.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/cmd/version.c b/cmd/version.c index d99a44f19fb..53db1a0b6bd 100644 --- a/cmd/version.c +++ b/cmd/version.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include diff --git a/cmd/video.c b/cmd/video.c index 942f81c1633..91bd6de14dc 100644 --- a/cmd/video.c +++ b/cmd/video.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/cmd/virtio.c b/cmd/virtio.c index 019e317e755..a42a563ab72 100644 --- a/cmd/virtio.c +++ b/cmd/virtio.c @@ -4,7 +4,6 @@ * Copyright (C) 2018, Bin Meng */ -#include #include #include #include diff --git a/cmd/w1.c b/cmd/w1.c index 3209e65f377..e462e786a96 100644 --- a/cmd/w1.c +++ b/cmd/w1.c @@ -4,7 +4,6 @@ * Microchip Technology, Inc. * Eugen Hristev */ -#include #include #include #include diff --git a/cmd/wdt.c b/cmd/wdt.c index b9fdf7ad155..c7a06cca181 100644 --- a/cmd/wdt.c +++ b/cmd/wdt.c @@ -5,7 +5,6 @@ * Copyright (c) 2019 Michael Walle */ -#include #include #include #include diff --git a/cmd/wol.c b/cmd/wol.c index f0d63432272..45d4ae3f719 100644 --- a/cmd/wol.c +++ b/cmd/wol.c @@ -7,9 +7,9 @@ /* * Wake-on-LAN support */ -#include #include #include +#include #if defined(CONFIG_CMD_WOL) void wol_set_timeout(ulong); diff --git a/cmd/x86/cbsysinfo.c b/cmd/x86/cbsysinfo.c index 84822a3e321..7ca2e13ae2f 100644 --- a/cmd/x86/cbsysinfo.c +++ b/cmd/x86/cbsysinfo.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/cmd/x86/fsp.c b/cmd/x86/fsp.c index 82e4415b16e..2620ab8ee02 100644 --- a/cmd/x86/fsp.c +++ b/cmd/x86/fsp.c @@ -3,7 +3,6 @@ * Copyright (C) 2014-2015, Bin Meng */ -#include #include #include #include diff --git a/cmd/x86/hob.c b/cmd/x86/hob.c index 04d092dbe7e..2dd30808bd1 100644 --- a/cmd/x86/hob.c +++ b/cmd/x86/hob.c @@ -3,7 +3,6 @@ * Copyright (C) 2014-2015, Bin Meng */ -#include #include #include #include diff --git a/cmd/x86/mtrr.c b/cmd/x86/mtrr.c index 6ad7a123a44..b2afb598c73 100644 --- a/cmd/x86/mtrr.c +++ b/cmd/x86/mtrr.c @@ -3,9 +3,9 @@ * (C) Copyright 2014 Google, Inc */ -#include #include #include +#include #include #include #include diff --git a/cmd/ximg.c b/cmd/ximg.c index 0e7eead8d19..1467484df8d 100644 --- a/cmd/ximg.c +++ b/cmd/ximg.c @@ -11,7 +11,6 @@ /* * Multi Image extract */ -#include #include #include #include diff --git a/cmd/xxd.c b/cmd/xxd.c index 446ac1915ef..8ae05f910cb 100644 --- a/cmd/xxd.c +++ b/cmd/xxd.c @@ -4,7 +4,6 @@ * Roger Knecht */ -#include #include #include #include diff --git a/cmd/yaffs2.c b/cmd/yaffs2.c index 27fbd1be8f7..d0724d9bea8 100644 --- a/cmd/yaffs2.c +++ b/cmd/yaffs2.c @@ -13,7 +13,6 @@ * ... */ -#include #include #include diff --git a/cmd/zfs.c b/cmd/zfs.c index 6ef1b56ab10..2f831532c2e 100644 --- a/cmd/zfs.c +++ b/cmd/zfs.c @@ -8,7 +8,6 @@ * made from existing GRUB Sources by Sun, GNU and others. */ -#include #include #include #include diff --git a/cmd/zip.c b/cmd/zip.c index 08afd62b973..2d255428822 100644 --- a/cmd/zip.c +++ b/cmd/zip.c @@ -4,10 +4,10 @@ * Lei Wen , Marvell Inc. */ -#include #include #include #include +#include static int do_zip(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { diff --git a/common/autoboot.c b/common/autoboot.c index 6f0aeae6bf3..898a57bc92b 100644 --- a/common/autoboot.c +++ b/common/autoboot.c @@ -4,13 +4,14 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include #include #include #include +#include #include #include #include diff --git a/common/bloblist.c b/common/bloblist.c index ad06d7a1795..11d6422b695 100644 --- a/common/bloblist.c +++ b/common/bloblist.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY LOGC_BLOBLIST -#include #include #include #include diff --git a/common/board_f.c b/common/board_f.c index 039d6d712d0..212ffb3090b 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -9,7 +9,7 @@ * Marius Groeger */ -#include +#include #include #include #include diff --git a/common/board_info.c b/common/board_info.c index f4c385add90..33c260b404e 100644 --- a/common/board_info.c +++ b/common/board_info.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/common/board_r.c b/common/board_r.c index da0b80f24ff..c823cd262f1 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -9,7 +9,7 @@ * Marius Groeger */ -#include +#include #include #include #include diff --git a/common/bootstage.c b/common/bootstage.c index 0e6d80718fd..fb6befcbc4a 100644 --- a/common/bootstage.c +++ b/common/bootstage.c @@ -11,7 +11,6 @@ #define LOG_CATEGORY LOGC_BOOT -#include #include #include #include diff --git a/common/bouncebuf.c b/common/bouncebuf.c index 934b83f7ec3..b2f87e4d939 100644 --- a/common/bouncebuf.c +++ b/common/bouncebuf.c @@ -5,7 +5,6 @@ * Copyright (C) 2012 Marek Vasut */ -#include #include #include #include diff --git a/common/cli.c b/common/cli.c index 1c33daf1149..4694a35cd0e 100644 --- a/common/cli.c +++ b/common/cli.c @@ -10,7 +10,6 @@ #define pr_fmt(fmt) "cli: %s: " fmt, __func__ -#include #include #include #include diff --git a/common/cli_getch.c b/common/cli_getch.c index 0ee79087774..a5ed6eb6fcf 100644 --- a/common/cli_getch.c +++ b/common/cli_getch.c @@ -6,8 +6,10 @@ * Copyright 2022 Google LLC */ -#include #include +#include +#include +#include /** * enum cli_esc_state_t - indicates what to do with an escape character diff --git a/common/cli_hush.c b/common/cli_hush.c index 9cda97f30e3..96a98209b9d 100644 --- a/common/cli_hush.c +++ b/common/cli_hush.c @@ -75,7 +75,6 @@ #define __U_BOOT__ #ifdef __U_BOOT__ -#include /* readline */ #include #include /* malloc, free, realloc*/ #include /* isalpha, isdigit */ diff --git a/common/cli_readline.c b/common/cli_readline.c index cf4339d0e50..4cb82b40149 100644 --- a/common/cli_readline.c +++ b/common/cli_readline.c @@ -8,7 +8,6 @@ * JinHua Luo, GuangDong Linux Center, */ -#include #include #include #include @@ -16,6 +15,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/common/cli_simple.c b/common/cli_simple.c index f89ba92d1b0..266c444334e 100644 --- a/common/cli_simple.c +++ b/common/cli_simple.c @@ -8,7 +8,6 @@ * JinHua Luo, GuangDong Linux Center, */ -#include #include #include #include diff --git a/common/command.c b/common/command.c index af8ffdba8f8..3f691399cbe 100644 --- a/common/command.c +++ b/common/command.c @@ -8,7 +8,7 @@ * Command Processor Table */ -#include +#include #include #include #include @@ -16,6 +16,7 @@ #include #include #include +#include #include #include diff --git a/common/console.c b/common/console.c index aa3053bc441..63f78004fdb 100644 --- a/common/console.c +++ b/common/console.c @@ -4,7 +4,6 @@ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it */ -#include #include #include #include diff --git a/common/cros_ec.c b/common/cros_ec.c index 249d1f19411..9ccc8fa16cd 100644 --- a/common/cros_ec.c +++ b/common/cros_ec.c @@ -8,7 +8,6 @@ * Software Foundation. */ -#include #include #include #include diff --git a/common/ddr_spd.c b/common/ddr_spd.c index 58dc9b3781b..2f6eb99bf0c 100644 --- a/common/ddr_spd.c +++ b/common/ddr_spd.c @@ -3,8 +3,8 @@ * Copyright 2008-2014 Freescale Semiconductor, Inc. */ -#include #include +#include /* used for ddr1 and ddr2 spd */ static int diff --git a/common/dfu.c b/common/dfu.c index 0d154e8d4c4..1af8194139c 100644 --- a/common/dfu.c +++ b/common/dfu.c @@ -10,7 +10,6 @@ * Lukasz Majewski */ -#include #include #include #include diff --git a/common/dlmalloc.c b/common/dlmalloc.c index a0616217d49..9549c59f358 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -12,7 +12,6 @@ #define DEBUG #endif -#include #include #include diff --git a/common/edid.c b/common/edid.c index 556c4e3434b..865ba9daa78 100644 --- a/common/edid.c +++ b/common/edid.c @@ -9,7 +9,6 @@ * Copyright (C) Nalin Dahyabhai */ -#include #include #include #include diff --git a/common/eeprom/eeprom_field.c b/common/eeprom/eeprom_field.c index f56eebe679f..3bacb1ae7eb 100644 --- a/common/eeprom/eeprom_field.c +++ b/common/eeprom/eeprom_field.c @@ -6,7 +6,8 @@ * Igor Grinberg */ -#include +#include +#include #include #include diff --git a/common/eeprom/eeprom_layout.c b/common/eeprom/eeprom_layout.c index 5a9be1da061..1a425c1754d 100644 --- a/common/eeprom/eeprom_layout.c +++ b/common/eeprom/eeprom_layout.c @@ -6,8 +6,8 @@ * Igor Grinberg */ -#include #include +#include #include #include diff --git a/common/event.c b/common/event.c index 16c2ba6cc92..dda569d4478 100644 --- a/common/event.c +++ b/common/event.c @@ -9,13 +9,13 @@ #define LOG_CATEGORY LOGC_EVENT -#include #include #include #include #include #include #include +#include #include #include diff --git a/common/exports.c b/common/exports.c index 20d8b759bc2..48b084c3861 100644 --- a/common/exports.c +++ b/common/exports.c @@ -1,4 +1,3 @@ -#include #include #include #include diff --git a/common/flash.c b/common/flash.c index 848f44e59df..24ddc8bee72 100644 --- a/common/flash.c +++ b/common/flash.c @@ -6,10 +6,10 @@ /* #define DEBUG */ -#include #include #include #include +#include #include diff --git a/common/hash.c b/common/hash.c index 3d6b84de473..ac63803fed9 100644 --- a/common/hash.c +++ b/common/hash.c @@ -10,7 +10,6 @@ */ #ifndef USE_HOSTCC -#include #include #include #include diff --git a/common/hwconfig.c b/common/hwconfig.c index cac0b6348f4..afaa6cb37ab 100644 --- a/common/hwconfig.c +++ b/common/hwconfig.c @@ -10,7 +10,6 @@ #ifndef HWCONFIG_TEST #include -#include #include #include #include diff --git a/common/init/board_init.c b/common/init/board_init.c index ed2365daa35..a06ec1caa2c 100644 --- a/common/init/board_init.c +++ b/common/init/board_init.c @@ -6,7 +6,7 @@ * Written by Simon Glass */ -#include +#include #include #include #include diff --git a/common/init/handoff.c b/common/init/handoff.c index d0be1bb17a2..a7cd065fb38 100644 --- a/common/init/handoff.c +++ b/common/init/handoff.c @@ -5,7 +5,6 @@ * Copyright 2018 Google, Inc */ -#include #include #include diff --git a/common/iomux.c b/common/iomux.c index c428f7110a7..1224c15eb71 100644 --- a/common/iomux.c +++ b/common/iomux.c @@ -4,7 +4,6 @@ * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de. */ -#include #include #include #include diff --git a/common/iotrace.c b/common/iotrace.c index 63d0cca3a00..a0a5613bd9b 100644 --- a/common/iotrace.c +++ b/common/iotrace.c @@ -5,7 +5,6 @@ #define IOTRACE_IMPL -#include #include #include #include diff --git a/common/kallsyms.c b/common/kallsyms.c index 13344e634b9..49b3897078a 100644 --- a/common/kallsyms.c +++ b/common/kallsyms.c @@ -5,7 +5,6 @@ * Licensed under the GPL-2 or later. */ -#include /* We need the weak marking as this symbol is provided specially */ extern const char system_map[] __attribute__((weak)); diff --git a/common/kgdb.c b/common/kgdb.c index 29b09fcfe56..01a09f17628 100644 --- a/common/kgdb.c +++ b/common/kgdb.c @@ -87,7 +87,6 @@ * ****************************************************************************/ -#include #include #include diff --git a/common/kgdb_stubs.c b/common/kgdb_stubs.c index 66aed7cea1c..256d88697d7 100644 --- a/common/kgdb_stubs.c +++ b/common/kgdb_stubs.c @@ -7,7 +7,6 @@ * Licensed under the GPL-2 or later. */ -#include #include #include #include diff --git a/common/log.c b/common/log.c index 42d35f04b68..dfee250b158 100644 --- a/common/log.c +++ b/common/log.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/common/log_console.c b/common/log_console.c index bb091ce21a4..c27101b8fe2 100644 --- a/common/log_console.c +++ b/common/log_console.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include diff --git a/common/log_syslog.c b/common/log_syslog.c index 53c4def5d1c..d01bb749c22 100644 --- a/common/log_syslog.c +++ b/common/log_syslog.c @@ -5,7 +5,6 @@ * Copyright (c) 2020, Heinrich Schuchardt */ -#include #include #include #include diff --git a/common/main.c b/common/main.c index 82d3aafa53c..b0b6e74f5d3 100644 --- a/common/main.c +++ b/common/main.c @@ -6,7 +6,6 @@ /* #define DEBUG */ -#include #include #include #include diff --git a/common/malloc_simple.c b/common/malloc_simple.c index 0a004d40e1e..4e6d7952b3c 100644 --- a/common/malloc_simple.c +++ b/common/malloc_simple.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY LOGC_ALLOC -#include #include #include #include diff --git a/common/memsize.c b/common/memsize.c index d646df8b04c..86109579c95 100644 --- a/common/memsize.c +++ b/common/memsize.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include diff --git a/common/menu.c b/common/menu.c index b55cf7b9996..e48424995b6 100644 --- a/common/menu.c +++ b/common/menu.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/common/miiphyutil.c b/common/miiphyutil.c index 194c84e7e89..9b8744e5d8b 100644 --- a/common/miiphyutil.c +++ b/common/miiphyutil.c @@ -9,7 +9,6 @@ * channel. */ -#include #include #include #include diff --git a/common/s_record.c b/common/s_record.c index 2b7651fcffc..486dd93abd4 100644 --- a/common/s_record.c +++ b/common/s_record.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include static int hex1_bin (char c); diff --git a/common/scp03.c b/common/scp03.c index 09ef7b5ba3d..54b1bd54b60 100644 --- a/common/scp03.c +++ b/common/scp03.c @@ -4,10 +4,11 @@ * */ -#include #include #include #include +#include +#include static int scp03_enable(bool provision) { diff --git a/common/spl/spl.c b/common/spl/spl.c index e06bc75d36b..9a879e9fb10 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -6,7 +6,7 @@ * Aneesh V */ -#include +#include #include #include #include @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include diff --git a/common/spl/spl_atf.c b/common/spl/spl_atf.c index 3bdd013a35f..0b1c981a105 100644 --- a/common/spl/spl_atf.c +++ b/common/spl/spl_atf.c @@ -9,7 +9,6 @@ * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH */ -#include #include #include #include diff --git a/common/spl/spl_blk_fs.c b/common/spl/spl_blk_fs.c index 04eac6f306b..bc551c5c074 100644 --- a/common/spl/spl_blk_fs.c +++ b/common/spl/spl_blk_fs.c @@ -5,7 +5,6 @@ * */ -#include #include #include #include diff --git a/common/spl/spl_bootrom.c b/common/spl/spl_bootrom.c index 0eefd39a519..e172a2d7b83 100644 --- a/common/spl/spl_bootrom.c +++ b/common/spl/spl_bootrom.c @@ -3,7 +3,6 @@ * Copyright (C) 2017 Theobroma Systems Design und Consulting GmH */ -#include #include __weak int board_return_to_bootrom(struct spl_image_info *spl_image, diff --git a/common/spl/spl_dfu.c b/common/spl/spl_dfu.c index 8a779da8fa1..e9f381c392c 100644 --- a/common/spl/spl_dfu.c +++ b/common/spl/spl_dfu.c @@ -5,7 +5,6 @@ * * Ravi B */ -#include #include #include #include diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c index 2be6f04b02c..76f49a5a8a6 100644 --- a/common/spl/spl_ext.c +++ b/common/spl/spl_ext.c @@ -1,11 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include #include -#include #include #include #include diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c index a52f9e178e6..bd8aab253a9 100644 --- a/common/spl/spl_fat.c +++ b/common/spl/spl_fat.c @@ -8,12 +8,10 @@ * FAT Image Functions copied from spl_mmc.c */ -#include #include #include #include #include -#include #include #include #include diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index e5195d460c4..988125be008 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/common/spl/spl_imx_container.c b/common/spl/spl_imx_container.c index b4ea9241d68..2c31777fcd3 100644 --- a/common/spl/spl_imx_container.c +++ b/common/spl/spl_imx_container.c @@ -4,7 +4,6 @@ */ #define LOG_CATEGORY LOGC_ARCH -#include #include #include #include diff --git a/common/spl/spl_legacy.c b/common/spl/spl_legacy.c index 08687ca8f6c..a77893455f2 100644 --- a/common/spl/spl_legacy.c +++ b/common/spl/spl_legacy.c @@ -3,7 +3,6 @@ * Copyright (C) 2020 Stefan Roese */ -#include #include #include #include diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 3d032bb27ce..ccab0be4be2 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -5,7 +5,6 @@ * * Aneesh V */ -#include #include #include #include @@ -13,7 +12,6 @@ #include #include #include -#include #include #include #include diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index 3b0a1524238..5631fa6d563 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -3,7 +3,6 @@ * Copyright (C) 2011 * Corscience GmbH & Co. KG - Simon Schwarz */ -#include #include #include #include diff --git a/common/spl/spl_net.c b/common/spl/spl_net.c index 898f9df705a..be7278bb933 100644 --- a/common/spl/spl_net.c +++ b/common/spl/spl_net.c @@ -6,7 +6,6 @@ * (C) Copyright 2012 * Ilya Yanok */ -#include #include #include #include diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c index 70745114efe..ed76b5e1293 100644 --- a/common/spl/spl_nor.c +++ b/common/spl/spl_nor.c @@ -3,7 +3,7 @@ * Copyright (C) 2012 Stefan Roese */ -#include +#include #include #include #include diff --git a/common/spl/spl_nvme.c b/common/spl/spl_nvme.c index c8774d67ecf..0e15a3c7545 100644 --- a/common/spl/spl_nvme.c +++ b/common/spl/spl_nvme.c @@ -5,7 +5,6 @@ * */ -#include #include #include diff --git a/common/spl/spl_onenand.c b/common/spl/spl_onenand.c index 53a8c6de89e..f6f65286c21 100644 --- a/common/spl/spl_onenand.c +++ b/common/spl/spl_onenand.c @@ -7,7 +7,6 @@ * Copyright (C) 2011 * Corscience GmbH & Co. KG - Simon Schwarz */ -#include #include #include #include diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c index ec62aab929b..5a26d7c31a4 100644 --- a/common/spl/spl_opensbi.c +++ b/common/spl/spl_opensbi.c @@ -5,7 +5,6 @@ * * Based on common/spl/spl_atf.c */ -#include #include #include #include diff --git a/common/spl/spl_ram.c b/common/spl/spl_ram.c index 8aeda237be1..5a23841f698 100644 --- a/common/spl/spl_ram.c +++ b/common/spl/spl_ram.c @@ -9,7 +9,6 @@ * Michal Simek * Stefan Agner */ -#include #include #include #include diff --git a/common/spl/spl_sata.c b/common/spl/spl_sata.c index 32746ce9f3c..67fc620d9be 100644 --- a/common/spl/spl_sata.c +++ b/common/spl/spl_sata.c @@ -8,9 +8,7 @@ * Derived work from spl_usb.c */ -#include #include -#include #include #include #include diff --git a/common/spl/spl_sdp.c b/common/spl/spl_sdp.c index 9143c27bbf1..9ca80bd534f 100644 --- a/common/spl/spl_sdp.c +++ b/common/spl/spl_sdp.c @@ -4,7 +4,6 @@ * Author: Stefan Agner */ -#include #include #include #include diff --git a/common/spl/spl_semihosting.c b/common/spl/spl_semihosting.c index 941fa911040..2047248f39b 100644 --- a/common/spl/spl_semihosting.c +++ b/common/spl/spl_semihosting.c @@ -3,7 +3,6 @@ * Copyright (C) 2022 Sean Anderson */ -#include #include #include #include diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c index 89de73c726c..8ab4803f7c4 100644 --- a/common/spl/spl_spi.c +++ b/common/spl/spl_spi.c @@ -8,7 +8,7 @@ * Heiko Schocher, DENX Software Engineering, hs@denx.de. */ -#include +#include #include #include #include diff --git a/common/spl/spl_ubi.c b/common/spl/spl_ubi.c index d7ab9efd110..a8d3f43b452 100644 --- a/common/spl/spl_ubi.c +++ b/common/spl/spl_ubi.c @@ -4,7 +4,6 @@ * Ladislav Michl */ -#include #include #include #include diff --git a/common/spl/spl_usb.c b/common/spl/spl_usb.c index 479e2dc1826..932da56ab6d 100644 --- a/common/spl/spl_usb.c +++ b/common/spl/spl_usb.c @@ -8,10 +8,8 @@ * Derived work from spl_mmc.c */ -#include #include #include -#include #include #include #include diff --git a/common/spl/spl_xip.c b/common/spl/spl_xip.c index 959915ffa61..1465c3e46b9 100644 --- a/common/spl/spl_xip.c +++ b/common/spl/spl_xip.c @@ -4,7 +4,7 @@ * Author(s): Vikas Manocha, for STMicroelectronics. */ -#include +#include #include #include #include diff --git a/common/spl/spl_ymodem.c b/common/spl/spl_ymodem.c index 1faaa2c938d..4c7222af612 100644 --- a/common/spl/spl_ymodem.c +++ b/common/spl/spl_ymodem.c @@ -8,13 +8,11 @@ * * Matt Porter */ -#include #include #include #include #include #include -#include #include #define BUF_SIZE 1024 diff --git a/common/splash.c b/common/splash.c index 6820db683bd..c5591293634 100644 --- a/common/splash.c +++ b/common/splash.c @@ -20,11 +20,12 @@ * */ -#include #include #include #include #include +#include +#include static struct splash_location default_splash_locations[] = { { diff --git a/common/splash_source.c b/common/splash_source.c index 2ce0768833d..5b271160449 100644 --- a/common/splash_source.c +++ b/common/splash_source.c @@ -5,7 +5,6 @@ * Authors: Igor Grinberg */ -#include #include #include #include diff --git a/common/stackprot.c b/common/stackprot.c index 6495951a773..4e3297b7d00 100644 --- a/common/stackprot.c +++ b/common/stackprot.c @@ -3,7 +3,6 @@ * Copyright 2021 Broadcom */ -#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/common/stdio.c b/common/stdio.c index e3354f092dc..a61220ce4b9 100644 --- a/common/stdio.c +++ b/common/stdio.c @@ -9,7 +9,6 @@ */ #include -#include #include #include #include diff --git a/common/update.c b/common/update.c index ec302ca68fb..eb0b60a2ce4 100644 --- a/common/update.c +++ b/common/update.c @@ -6,7 +6,6 @@ * Bartlomiej Sieka */ -#include #include #include #include diff --git a/common/usb.c b/common/usb.c index 99e6b857c74..84b10f5c7d8 100644 --- a/common/usb.c +++ b/common/usb.c @@ -25,7 +25,6 @@ * * For each transfer (except "Interrupt") we wait for completion. */ -#include #include #include #include diff --git a/common/usb_hub.c b/common/usb_hub.c index 2e054eb9353..807f490bb60 100644 --- a/common/usb_hub.c +++ b/common/usb_hub.c @@ -21,7 +21,6 @@ * Probes device for being a hub and configurate it */ -#include #include #include #include @@ -29,6 +28,7 @@ #include #include #include +#include #include #include #include diff --git a/common/usb_kbd.c b/common/usb_kbd.c index 820f591fc5b..f3b4a3c94e6 100644 --- a/common/usb_kbd.c +++ b/common/usb_kbd.c @@ -6,7 +6,6 @@ * Part of this source has been derived from the Linux USB * project. */ -#include #include #include #include @@ -15,6 +14,7 @@ #include #include #include +#include #include #include #ifdef CONFIG_SANDBOX diff --git a/common/usb_onboard_hub.c b/common/usb_onboard_hub.c index 89e18a2ddad..68a04ac0412 100644 --- a/common/usb_onboard_hub.c +++ b/common/usb_onboard_hub.c @@ -7,7 +7,6 @@ * Mostly inspired by Linux kernel v6.1 onboard_usb_hub driver */ -#include #include #include #include diff --git a/common/usb_storage.c b/common/usb_storage.c index 774d5bdf54b..a79ed2e23a4 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -32,7 +32,6 @@ */ -#include #include #include #include diff --git a/common/xyzModem.c b/common/xyzModem.c index fb319f71190..9feb240de28 100644 --- a/common/xyzModem.c +++ b/common/xyzModem.c @@ -21,12 +21,13 @@ * *========================================================================== */ -#include #include #include +#include #include #include #include +#include /* Assumption - run xyzModem protocol over the console port */ diff --git a/configs/phycore_am64x_a53_defconfig b/configs/phycore_am64x_a53_defconfig index 9b52f8ad064..76bb0e53e51 100644 --- a/configs/phycore_am64x_a53_defconfig +++ b/configs/phycore_am64x_a53_defconfig @@ -38,6 +38,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTSTD_FULL=y CONFIG_BOOTCOMMAND="run mmcboot; bootflow scan -lb" CONFIG_DEFAULT_FDT_FILE="oftree" +CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x180000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/disk/disk-uclass.c b/disk/disk-uclass.c index efe4bf1f949..ee3cc4407d7 100644 --- a/disk/disk-uclass.c +++ b/disk/disk-uclass.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_PARTITION -#include #include #include #include diff --git a/disk/part.c b/disk/part.c index 2bee6695828..bc932526f90 100644 --- a/disk/part.c +++ b/disk/part.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include diff --git a/disk/part_amiga.c b/disk/part_amiga.c index 65e30fea558..9b0f2fe7498 100644 --- a/disk/part_amiga.c +++ b/disk/part_amiga.c @@ -4,12 +4,12 @@ * Hans-Joerg Frieden, Hyperion Entertainment * Hans-JoergF@hyperion-entertainment.com */ -#include #include #include #include #include "part_amiga.h" #include +#include #undef AMIGA_DEBUG diff --git a/disk/part_dos.c b/disk/part_dos.c index 567ead7511d..e6b5295e0ec 100644 --- a/disk/part_dos.c +++ b/disk/part_dos.c @@ -13,11 +13,11 @@ * http://developer.apple.com/techpubs/mac/Devices/Devices-126.html#MARKER-14-92 */ -#include #include #include #include #include +#include #include #include #include "part_dos.h" diff --git a/disk/part_efi.c b/disk/part_efi.c index 4ce9243ef25..b1a03bd165e 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -12,7 +12,6 @@ #define LOG_CATEGORY LOGC_FS -#include #include #include #include diff --git a/disk/part_iso.c b/disk/part_iso.c index 6ac6d95be92..6e05b2feffb 100644 --- a/disk/part_iso.c +++ b/disk/part_iso.c @@ -4,7 +4,6 @@ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch. */ -#include #include #include #include diff --git a/disk/part_mac.c b/disk/part_mac.c index db5e203be59..81a65823be9 100644 --- a/disk/part_mac.c +++ b/disk/part_mac.c @@ -12,7 +12,6 @@ * http://developer.apple.com/techpubs/mac/Devices/Devices-126.html#MARKER-14-92 */ -#include #include #include #include diff --git a/doc/develop/codingstyle.rst b/doc/develop/codingstyle.rst index f6248cdcb1e..fa3cd6aec82 100644 --- a/doc/develop/codingstyle.rst +++ b/doc/develop/codingstyle.rst @@ -110,9 +110,8 @@ Include files You should follow this ordering in U-Boot. In all cases, they should be listed in alphabetical order. First comes headers which are located directly in our -top-level include diretory. This excludes the common.h header file which is to -be removed. Second are headers within subdirectories, Finally directory-local -includes should be listed. See this example: +top-level include diretory. Second are headers within subdirectories, Finally +directory-local includes should be listed. See this example: .. code-block:: C @@ -129,9 +128,6 @@ For files that need to be compiled for the host (e.g. tools), you need to use ``#ifndef USE_HOSTCC`` to avoid including U-Boot specific include files. See common/image.c for an example. -If you encounter code which still uses a patch to remove that and -replace it with any required include files directly is much appreciated. - If your file uses driver model, include in the C file. Do not include dm.h in a header file. Try to use forward declarations (e.g. ``struct udevice``) instead. diff --git a/doc/develop/tests_writing.rst b/doc/develop/tests_writing.rst index bb1145da268..44b544fa78b 100644 --- a/doc/develop/tests_writing.rst +++ b/doc/develop/tests_writing.rst @@ -281,7 +281,6 @@ new one of those, you should add a new suite. Create a new file in test/ or a subdirectory and define a macro to register the suite. For example:: - #include #include #include #include diff --git a/drivers/adc/adc-uclass.c b/drivers/adc/adc-uclass.c index 1b35bf22014..16600be821c 100644 --- a/drivers/adc/adc-uclass.c +++ b/drivers/adc/adc-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_ADC -#include #include #include #include diff --git a/drivers/adc/exynos-adc.c b/drivers/adc/exynos-adc.c index 2bda733af90..ecc564cd219 100644 --- a/drivers/adc/exynos-adc.c +++ b/drivers/adc/exynos-adc.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Samsung Electronics * Przemyslaw Marczak */ -#include #include #include #include diff --git a/drivers/adc/imx93-adc.c b/drivers/adc/imx93-adc.c index 41d04e0426c..f593fb6447b 100644 --- a/drivers/adc/imx93-adc.c +++ b/drivers/adc/imx93-adc.c @@ -6,7 +6,6 @@ * Originally based on NXP linux-imx kernel v5.15 drivers/iio/adc/imx93_adc.c */ -#include #include #include #include diff --git a/drivers/adc/meson-saradc.c b/drivers/adc/meson-saradc.c index c15c7fea47f..60e348968fb 100644 --- a/drivers/adc/meson-saradc.c +++ b/drivers/adc/meson-saradc.c @@ -7,7 +7,6 @@ * Amlogic Meson Successive Approximation Register (SAR) A/D Converter */ -#include #include #include #include diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c index 10ded1b088f..f6832ab3073 100644 --- a/drivers/adc/rockchip-saradc.c +++ b/drivers/adc/rockchip-saradc.c @@ -5,7 +5,6 @@ * Rockchip SARADC driver for U-Boot */ -#include #include #include #include diff --git a/drivers/adc/sandbox.c b/drivers/adc/sandbox.c index 43cad34ffeb..24d4af63bd9 100644 --- a/drivers/adc/sandbox.c +++ b/drivers/adc/sandbox.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Samsung Electronics * Przemyslaw Marczak */ -#include #include #include #include diff --git a/drivers/adc/stm32-adc-core.c b/drivers/adc/stm32-adc-core.c index 6c176961f17..af340b8b273 100644 --- a/drivers/adc/stm32-adc-core.c +++ b/drivers/adc/stm32-adc-core.c @@ -6,7 +6,6 @@ * Originally based on the Linux kernel v4.18 drivers/iio/adc/stm32-adc-core.c. */ -#include #include #include #include diff --git a/drivers/adc/stm32-adc.c b/drivers/adc/stm32-adc.c index 1fba707c6f7..d50f00f1233 100644 --- a/drivers/adc/stm32-adc.c +++ b/drivers/adc/stm32-adc.c @@ -6,7 +6,6 @@ * Originally based on the Linux kernel v4.18 drivers/iio/adc/stm32-adc.c. */ -#include #include #include #include diff --git a/drivers/ata/ahci-pci.c b/drivers/ata/ahci-pci.c index 5356b9d83d3..f2102aaa635 100644 --- a/drivers/ata/ahci-pci.c +++ b/drivers/ata/ahci-pci.c @@ -3,7 +3,6 @@ * Copyright (C) 2017, Bin Meng */ -#include #include #include #include diff --git a/drivers/ata/ahci-uclass.c b/drivers/ata/ahci-uclass.c index d398b50b9a1..7affb3f1ec7 100644 --- a/drivers/ata/ahci-uclass.c +++ b/drivers/ata/ahci-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_AHCI -#include #include #include diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index 04ddc339464..ac869296d52 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -8,10 +8,10 @@ * * This driver provides a SCSI interface to SATA. */ -#include #include #include #include +#include #include #include diff --git a/drivers/ata/ahci_mvebu.c b/drivers/ata/ahci_mvebu.c index f05150d61dd..f6e2d6bee45 100644 --- a/drivers/ata/ahci_mvebu.c +++ b/drivers/ata/ahci_mvebu.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Stefan Roese */ -#include #include #include #include diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c index 9064774e661..6cf5cee055e 100644 --- a/drivers/ata/ahci_sunxi.c +++ b/drivers/ata/ahci_sunxi.c @@ -1,4 +1,3 @@ -#include #include #include #include diff --git a/drivers/ata/dwc_ahci.c b/drivers/ata/dwc_ahci.c index 15fd3e365b2..b480cde4465 100644 --- a/drivers/ata/dwc_ahci.c +++ b/drivers/ata/dwc_ahci.c @@ -8,7 +8,6 @@ * Author: Mugunthan V N */ -#include #include #include #include diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c index b4d4e39c9b3..a29d641343e 100644 --- a/drivers/ata/dwc_ahsata.c +++ b/drivers/ata/dwc_ahsata.c @@ -4,7 +4,6 @@ * Terry Lv */ -#include #include #include #include diff --git a/drivers/ata/fsl_sata.c b/drivers/ata/fsl_sata.c index 969bc191f8e..4990148388b 100644 --- a/drivers/ata/fsl_sata.c +++ b/drivers/ata/fsl_sata.c @@ -5,7 +5,6 @@ * Author: Dave Liu */ -#include #include #include #include diff --git a/drivers/ata/libata.c b/drivers/ata/libata.c index 47e2c5c1cc4..ef659cb1728 100644 --- a/drivers/ata/libata.c +++ b/drivers/ata/libata.c @@ -5,9 +5,9 @@ * port from the libata of linux kernel */ -#include #include #include +#include u64 ata_id_n_sectors(u16 *id) { diff --git a/drivers/ata/mtk_ahci.c b/drivers/ata/mtk_ahci.c index 2c5227df306..53aabee0a5e 100644 --- a/drivers/ata/mtk_ahci.c +++ b/drivers/ata/mtk_ahci.c @@ -8,7 +8,6 @@ * Author: Frank Wunderlich */ -#include #include #include #include diff --git a/drivers/ata/sata.c b/drivers/ata/sata.c index 784d9bbeacb..84437d3d346 100644 --- a/drivers/ata/sata.c +++ b/drivers/ata/sata.c @@ -9,7 +9,6 @@ * Dave Liu */ -#include #include #include #include diff --git a/drivers/ata/sata_bootdev.c b/drivers/ata/sata_bootdev.c index f638493ce04..a5ca6f6fd5b 100644 --- a/drivers/ata/sata_bootdev.c +++ b/drivers/ata/sata_bootdev.c @@ -5,7 +5,6 @@ * Copyright 2023 Tony Dinh */ -#include #include #include #include diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c index 7769d4f99ef..a81b3165992 100644 --- a/drivers/ata/sata_ceva.c +++ b/drivers/ata/sata_ceva.c @@ -3,7 +3,6 @@ * (C) Copyright 2015 - 2016 Xilinx, Inc. * Michal Simek */ -#include #include #include #include diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index 94d7369351a..ac78760a33e 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c @@ -31,7 +31,6 @@ * No port multiplier support */ -#include #include #include #include @@ -46,6 +45,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/ata/sata_sil.c b/drivers/ata/sata_sil.c index 43a91a79120..5b80f6249d7 100644 --- a/drivers/ata/sata_sil.c +++ b/drivers/ata/sata_sil.c @@ -5,7 +5,6 @@ * Author: Tang Yuantian */ -#include #include #include #include diff --git a/drivers/axi/axi-emul-uclass.c b/drivers/axi/axi-emul-uclass.c index e6f3ef07200..bea0b040738 100644 --- a/drivers/axi/axi-emul-uclass.c +++ b/drivers/axi/axi-emul-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_AXI_EMUL -#include #include #include #include diff --git a/drivers/axi/axi-uclass.c b/drivers/axi/axi-uclass.c index 41551ae85c9..fa2475cbaf4 100644 --- a/drivers/axi/axi-uclass.c +++ b/drivers/axi/axi-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_AXI -#include #include #include diff --git a/drivers/axi/axi_sandbox.c b/drivers/axi/axi_sandbox.c index b91c91f6b3b..6f698a405f9 100644 --- a/drivers/axi/axi_sandbox.c +++ b/drivers/axi/axi_sandbox.c @@ -4,7 +4,6 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ -#include #include #include #include diff --git a/drivers/axi/ihs_axi.c b/drivers/axi/ihs_axi.c index a7e9761fbfc..a37dd1e1786 100644 --- a/drivers/axi/ihs_axi.c +++ b/drivers/axi/ihs_axi.c @@ -7,7 +7,6 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ -#include #include #include #include diff --git a/drivers/axi/sandbox_store.c b/drivers/axi/sandbox_store.c index ef349a50b79..b9413c758f7 100644 --- a/drivers/axi/sandbox_store.c +++ b/drivers/axi/sandbox_store.c @@ -4,7 +4,6 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ -#include #include #include #include diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c index 7ebead6bfad..d544ffb5ffb 100644 --- a/drivers/bios_emulator/atibios.c +++ b/drivers/bios_emulator/atibios.c @@ -45,7 +45,6 @@ * Jason ported this file to u-boot to run the ATI video card * BIOS in u-boot. ****************************************************************************/ -#include #include #include #include diff --git a/drivers/bios_emulator/besys.c b/drivers/bios_emulator/besys.c index 02c4286a854..690fb5a4d7b 100644 --- a/drivers/bios_emulator/besys.c +++ b/drivers/bios_emulator/besys.c @@ -48,7 +48,6 @@ ****************************************************************************/ #define __io -#include #include #include "biosemui.h" diff --git a/drivers/bios_emulator/bios.c b/drivers/bios_emulator/bios.c index 9596a1fdd3e..7f883daf8f0 100644 --- a/drivers/bios_emulator/bios.c +++ b/drivers/bios_emulator/bios.c @@ -42,7 +42,6 @@ ****************************************************************************/ #define __io -#include #include #include "biosemui.h" diff --git a/drivers/bios_emulator/biosemu.c b/drivers/bios_emulator/biosemu.c index 82befbae66f..ba4328474ce 100644 --- a/drivers/bios_emulator/biosemu.c +++ b/drivers/bios_emulator/biosemu.c @@ -46,7 +46,6 @@ ****************************************************************************/ #include -#include #include "biosemui.h" BE_sysEnv _BE_env = {{0}}; diff --git a/drivers/bios_emulator/x86emu/debug.c b/drivers/bios_emulator/x86emu/debug.c index 95f3cc09aad..b426dc3bc45 100644 --- a/drivers/bios_emulator/x86emu/debug.c +++ b/drivers/bios_emulator/x86emu/debug.c @@ -38,7 +38,6 @@ ****************************************************************************/ #include -#include #include #include #include "x86emu/x86emui.h" diff --git a/drivers/bios_emulator/x86emu/decode.c b/drivers/bios_emulator/x86emu/decode.c index e2028eaf083..7e188d58a52 100644 --- a/drivers/bios_emulator/x86emu/decode.c +++ b/drivers/bios_emulator/x86emu/decode.c @@ -36,7 +36,6 @@ * instruction decoding and accessess of immediate data via IP. etc. * ****************************************************************************/ -#include #include #include "x86emu/x86emui.h" diff --git a/drivers/bios_emulator/x86emu/ops.c b/drivers/bios_emulator/x86emu/ops.c index 8c1a146165c..57422ec3d47 100644 --- a/drivers/bios_emulator/x86emu/ops.c +++ b/drivers/bios_emulator/x86emu/ops.c @@ -72,7 +72,6 @@ * ****************************************************************************/ -#include #include #include "x86emu/x86emui.h" diff --git a/drivers/bios_emulator/x86emu/ops2.c b/drivers/bios_emulator/x86emu/ops2.c index 6cd1ac39825..32fecb34791 100644 --- a/drivers/bios_emulator/x86emu/ops2.c +++ b/drivers/bios_emulator/x86emu/ops2.c @@ -41,7 +41,6 @@ * ****************************************************************************/ -#include #include #include #include "x86emu/x86emui.h" diff --git a/drivers/bios_emulator/x86emu/prim_ops.c b/drivers/bios_emulator/x86emu/prim_ops.c index 5f6c795fb7f..b3cccb17f20 100644 --- a/drivers/bios_emulator/x86emu/prim_ops.c +++ b/drivers/bios_emulator/x86emu/prim_ops.c @@ -97,7 +97,6 @@ * ****************************************************************************/ -#include #define PRIM_OPS_NO_REDEFINE_ASM #include "x86emu/x86emui.h" diff --git a/drivers/bios_emulator/x86emu/sys.c b/drivers/bios_emulator/x86emu/sys.c index f96652415cd..483ecd52efe 100644 --- a/drivers/bios_emulator/x86emu/sys.c +++ b/drivers/bios_emulator/x86emu/sys.c @@ -39,7 +39,6 @@ * ****************************************************************************/ -#include #include #include "x86emu/x86emui.h" diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c index 77066da352a..512c952f4d7 100644 --- a/drivers/block/blk-uclass.c +++ b/drivers/block/blk-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_BLK -#include #include #include #include diff --git a/drivers/block/blk_legacy.c b/drivers/block/blk_legacy.c index 5bf1d047152..f36932183d1 100644 --- a/drivers/block/blk_legacy.c +++ b/drivers/block/blk_legacy.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/block/blkcache.c b/drivers/block/blkcache.c index 26bcbea4353..0e69160249c 100644 --- a/drivers/block/blkcache.c +++ b/drivers/block/blkcache.c @@ -4,7 +4,6 @@ * Author: Eric Nelson * */ -#include #include #include #include diff --git a/drivers/block/blkmap.c b/drivers/block/blkmap.c index 21201409ed4..34eed1380dc 100644 --- a/drivers/block/blkmap.c +++ b/drivers/block/blkmap.c @@ -4,7 +4,6 @@ * Author: Tobias Waldekranz */ -#include #include #include #include diff --git a/drivers/block/efi-media-uclass.c b/drivers/block/efi-media-uclass.c index e012f6f2f4c..dc5e4f59b7f 100644 --- a/drivers/block/efi-media-uclass.c +++ b/drivers/block/efi-media-uclass.c @@ -5,7 +5,6 @@ * Copyright 2021 Google LLC */ -#include #include UCLASS_DRIVER(efi_media) = { diff --git a/drivers/block/efi_blk.c b/drivers/block/efi_blk.c index 917a19f6025..9766cd6f832 100644 --- a/drivers/block/efi_blk.c +++ b/drivers/block/efi_blk.c @@ -8,7 +8,6 @@ * Copyright 2021 Google LLC */ -#include #include #include #include diff --git a/drivers/block/host-uclass.c b/drivers/block/host-uclass.c index b3647e3ce33..cf42bd1e07a 100644 --- a/drivers/block/host-uclass.c +++ b/drivers/block/host-uclass.c @@ -9,7 +9,6 @@ #define LOG_CATEGORY UCLASS_HOST -#include #include #include #include diff --git a/drivers/block/host_dev.c b/drivers/block/host_dev.c index 52313435a0c..b3ff3cd1fab 100644 --- a/drivers/block/host_dev.c +++ b/drivers/block/host_dev.c @@ -9,7 +9,6 @@ #define LOG_CATEGORY UCLASS_HOST -#include #include #include #include diff --git a/drivers/block/ide.c b/drivers/block/ide.c index c698f9cbd55..b16623d7a3a 100644 --- a/drivers/block/ide.c +++ b/drivers/block/ide.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_IDE -#include #include #include #include diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c index be4e02cb601..ec34f1ad8c2 100644 --- a/drivers/block/sandbox.c +++ b/drivers/block/sandbox.c @@ -3,7 +3,6 @@ * Copyright (C) 2013 Henrik Nordstrom */ -#include #include #include #include diff --git a/drivers/block/sb_efi_media.c b/drivers/block/sb_efi_media.c index 52af155a600..3255db06496 100644 --- a/drivers/block/sb_efi_media.c +++ b/drivers/block/sb_efi_media.c @@ -5,7 +5,6 @@ * Copyright 2021 Google LLC */ -#include #include static const struct udevice_id sandbox_efi_media_ids[] = { diff --git a/drivers/bootcount/bootcount-uclass.c b/drivers/bootcount/bootcount-uclass.c index 5a369c82f1c..0178c1818e5 100644 --- a/drivers/bootcount/bootcount-uclass.c +++ b/drivers/bootcount/bootcount-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_BOOTCOUNT -#include #include #include #include diff --git a/drivers/bootcount/bootcount_at91.c b/drivers/bootcount/bootcount_at91.c index c4ab5ceafab..1a06db1fb74 100644 --- a/drivers/bootcount/bootcount_at91.c +++ b/drivers/bootcount/bootcount_at91.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/drivers/bootcount/bootcount_env.c b/drivers/bootcount/bootcount_env.c index b75c9002b2c..960cd71b9d5 100644 --- a/drivers/bootcount/bootcount_env.c +++ b/drivers/bootcount/bootcount_env.c @@ -4,7 +4,6 @@ * Heiko Schocher, DENX Software Engineering, hs@denx.de. */ -#include #include void bootcount_store(ulong a) diff --git a/drivers/bootcount/bootcount_ram.c b/drivers/bootcount/bootcount_ram.c index 8cc30cf40ef..33e157b865a 100644 --- a/drivers/bootcount/bootcount_ram.c +++ b/drivers/bootcount/bootcount_ram.c @@ -4,7 +4,6 @@ * Heiko Schocher, DENX Software Engineering, hs@denx.de. */ -#include #include #include #include diff --git a/drivers/bootcount/bootcount_syscon.c b/drivers/bootcount/bootcount_syscon.c index f80d87071d9..5dbc13cd545 100644 --- a/drivers/bootcount/bootcount_syscon.c +++ b/drivers/bootcount/bootcount_syscon.c @@ -3,7 +3,6 @@ * Copyright (c) Vaisala Oyj. All rights reserved. */ -#include #include #include #include diff --git a/drivers/bootcount/i2c-eeprom.c b/drivers/bootcount/i2c-eeprom.c index 709be094b11..12c430465c9 100644 --- a/drivers/bootcount/i2c-eeprom.c +++ b/drivers/bootcount/i2c-eeprom.c @@ -4,7 +4,6 @@ * (C) Copyright 2019 GE */ -#include #include #include #include diff --git a/drivers/bootcount/pmic_pfuze100.c b/drivers/bootcount/pmic_pfuze100.c index df046f1b0ab..8c529f5592b 100644 --- a/drivers/bootcount/pmic_pfuze100.c +++ b/drivers/bootcount/pmic_pfuze100.c @@ -8,7 +8,6 @@ * This works only, if the PMIC is not connected to a battery. */ -#include #include #include #include diff --git a/drivers/bootcount/rtc.c b/drivers/bootcount/rtc.c index 483caaa80df..b131946aa9d 100644 --- a/drivers/bootcount/rtc.c +++ b/drivers/bootcount/rtc.c @@ -3,7 +3,6 @@ * (C) Copyright 2018 Theobroma Systems Design und Consulting GmbH */ -#include #include #include #include diff --git a/drivers/bootcount/spi-flash.c b/drivers/bootcount/spi-flash.c index 03050e66613..155d0323ee7 100644 --- a/drivers/bootcount/spi-flash.c +++ b/drivers/bootcount/spi-flash.c @@ -4,7 +4,6 @@ * (C) Copyright 2019 GE */ -#include #include #include #include diff --git a/drivers/bus/ti-pwmss.c b/drivers/bus/ti-pwmss.c index 265b4cf83b5..d1f6f3bab00 100644 --- a/drivers/bus/ti-pwmss.c +++ b/drivers/bus/ti-pwmss.c @@ -5,7 +5,6 @@ * Copyright (C) 2020 Dario Binacchi */ -#include #include static const struct udevice_id ti_pwmss_ids[] = { diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 778c0654f6a..5f9f0a0d0b7 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -5,7 +5,6 @@ * Copyright (C) 2020 Dario Binacchi */ -#include #include #include #include diff --git a/drivers/button/button-adc.c b/drivers/button/button-adc.c index 9c24c960e6f..da7ddf2a857 100644 --- a/drivers/button/button-adc.c +++ b/drivers/button/button-adc.c @@ -5,7 +5,6 @@ * Author: Marek Szyprowski */ -#include #include #include #include diff --git a/drivers/button/button-gpio.c b/drivers/button/button-gpio.c index 7b5b3affe2d..43b82d98aeb 100644 --- a/drivers/button/button-gpio.c +++ b/drivers/button/button-gpio.c @@ -3,7 +3,6 @@ * Copyright (C) 2020 Philippe Reynes */ -#include #include #include #include diff --git a/drivers/button/button-uclass.c b/drivers/button/button-uclass.c index 032191d61ab..cda243389df 100644 --- a/drivers/button/button-uclass.c +++ b/drivers/button/button-uclass.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY UCLASS_BUTTON -#include #include #include #include diff --git a/drivers/cache/cache-andes-l2.c b/drivers/cache/cache-andes-l2.c index 45d29f2fbd9..7de8f16852d 100644 --- a/drivers/cache/cache-andes-l2.c +++ b/drivers/cache/cache-andes-l2.c @@ -4,7 +4,6 @@ * Rick Chen, Andes Technology Corporation */ -#include #include #include #include diff --git a/drivers/cache/cache-l2x0.c b/drivers/cache/cache-l2x0.c index 560f4c94f1e..c7bdd9d064a 100644 --- a/drivers/cache/cache-l2x0.c +++ b/drivers/cache/cache-l2x0.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2019 Intel Corporation */ -#include #include #include diff --git a/drivers/cache/cache-sifive-ccache.c b/drivers/cache/cache-sifive-ccache.c index 521df40466f..cc00b80f60b 100644 --- a/drivers/cache/cache-sifive-ccache.c +++ b/drivers/cache/cache-sifive-ccache.c @@ -3,7 +3,6 @@ * Copyright (C) 2021 SiFive */ -#include #include #include #include diff --git a/drivers/cache/cache-uclass.c b/drivers/cache/cache-uclass.c index 0c13dbdb75c..300e7bc86e1 100644 --- a/drivers/cache/cache-uclass.c +++ b/drivers/cache/cache-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_CACHE -#include #include #include diff --git a/drivers/cache/sandbox_cache.c b/drivers/cache/sandbox_cache.c index 955dfc8a0f8..2e20b83ab80 100644 --- a/drivers/cache/sandbox_cache.c +++ b/drivers/cache/sandbox_cache.c @@ -3,7 +3,6 @@ * Copyright (C) 2019 Intel Corporation */ -#include #include #include #include diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index bda6873be33..9acbc47fe8e 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -246,6 +246,7 @@ config CLK_ZYNQMP This clock driver adds support for clock realted settings for ZynqMP platform. +source "drivers/clk/adi/Kconfig" source "drivers/clk/analogbits/Kconfig" source "drivers/clk/at91/Kconfig" source "drivers/clk/exynos/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 638ad04baeb..847b9b29110 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-fixed-factor.o obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o obj-$(CONFIG_$(SPL_TPL_)CLK_GPIO) += clk-gpio.o +obj-y += adi/ obj-y += analogbits/ obj-y += imx/ obj-$(CONFIG_CLK_JH7110) += starfive/ diff --git a/drivers/clk/adi/Kconfig b/drivers/clk/adi/Kconfig new file mode 100644 index 00000000000..5745bedf88c --- /dev/null +++ b/drivers/clk/adi/Kconfig @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# (C) Copyright 2022 - Analog Devices, Inc. +# +# Written and/or maintained by Timesys Corporation +# +# Contact: Nathan Barrett-Morrison +# Contact: Greg Malysa +# + +config COMMON_CLK_ADI_SHARED + bool "Enable shared ADI clock framework code" + help + Required for shared code between SoC clock drivers. Automatically + selected by an appropriate SoC-specific clock driver version. + +config COMMON_CLK_ADI_SC598 + bool "Clock driver for ADI SC598 SoCs" + select DM + select CLK + select CLK_CCF + select OF_CONTROL + select CMD_CLK + select SPL_DM if SPL + select SPL_CLK if SPL + select SPL_CLK_CCF if SPL + select SPL_OF_CONTROL if SPL + select COMMON_CLK_ADI_SHARED + depends on SC59X_64 + help + This driver supports the system clocks on Analog Devices SC598-series + SoCs. It includes CGU and CDU clocks and supports gating unused clocks. + Modifying PLL configuration is not supported; that must be done prior + to booting the kernel. Clock dividers after the PLLs may be configured. + +config COMMON_CLK_ADI_SC594 + bool "Clock driver for ADI SC594 SoCs" + select DM + select CLK + select CLK_CCF + select OF_CONTROL + select CMD_CLK + select SPL_DM if SPL + select SPL_CLK if SPL + select SPL_CLK_CCF if SPL + select SPL_OF_CONTROL if SPL + select COMMON_CLK_ADI_SHARED + depends on SC59X + help + This driver supports the system clocks on Analog Devices SC594-series + SoCs. It includes CGU and CDU clocks and supports gating unused clocks. + Modifying PLL configuration is not supported; that must be done prior + to booting the kernel. Clock dividers after the PLLs may be configured. + +config COMMON_CLK_ADI_SC58X + bool "Clock driver for ADI SC58X SoCs" + select DM + select CLK + select CLK_CCF + select OF_CONTROL + select CMD_CLK + select COMMON_CLK_ADI_SHARED + depends on SC58X + help + This driver supports the system clocks on Analog Devices SC58x-series + SoCs. It includes CGU and CDU clocks and supports gating unused clocks. + Modifying PLL configuration is not supported; that must be done prior + to booting the kernel. Clock dividers after the PLLs may be configured. + +config COMMON_CLK_ADI_SC57X + bool "Clock driver for ADI SC57X SoCs" + select DM + select CLK + select CLK_CCF + select OF_CONTROL + select CMD_CLK + select COMMON_CLK_ADI_SHARED + depends on SC57X + help + This driver supports the system clocks on Analog Devices SC57x-series + SoCs. It includes CGU and CDU clocks and supports gating unused clocks. + Modifying PLL configuration is not supported; that must be done prior + to booting the kernel. Clock dividers after the PLLs may be configured. diff --git a/drivers/clk/adi/Makefile b/drivers/clk/adi/Makefile new file mode 100644 index 00000000000..f3f1fd92e5f --- /dev/null +++ b/drivers/clk/adi/Makefile @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# (C) Copyright 2022 - Analog Devices, Inc. +# +# Written and/or maintained by Timesys Corporation +# +# Contact: Nathan Barrett-Morrison +# Contact: Greg Malysa +# + +obj-$(CONFIG_COMMON_CLK_ADI_SHARED) += clk-shared.o clk-adi-pll.o + +obj-$(CONFIG_COMMON_CLK_ADI_SC594) += clk-adi-sc594.o +obj-$(CONFIG_COMMON_CLK_ADI_SC598) += clk-adi-sc598.o +obj-$(CONFIG_COMMON_CLK_ADI_SC58X) += clk-adi-sc58x.o +obj-$(CONFIG_COMMON_CLK_ADI_SC57X) += clk-adi-sc57x.o diff --git a/drivers/clk/adi/clk-adi-pll.c b/drivers/clk/adi/clk-adi-pll.c new file mode 100644 index 00000000000..372baa9c11b --- /dev/null +++ b/drivers/clk/adi/clk-adi-pll.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Author: Greg Malysa + * + * Ported from Linux: Nathan Barrett-Morrison + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#define ADI_CLK_PLL_GENERIC "adi_clk_pll_generic" + +struct clk_sc5xx_cgu_pll { + struct clk clk; + void __iomem *base; + u32 mask; + u32 max; + u32 m_offset; + u8 shift; + bool half_m; +}; + +#define to_clk_sc5xx_cgu_pll(_clk) container_of(_clk, struct clk_sc5xx_cgu_pll, clk) + +static unsigned long sc5xx_cgu_pll_get_rate(struct clk *clk) +{ + struct clk_sc5xx_cgu_pll *pll = to_clk_sc5xx_cgu_pll(dev_get_clk_ptr(clk->dev)); + unsigned long parent_rate = clk_get_parent_rate(clk); + + u32 reg = readl(pll->base); + u32 m = ((reg & pll->mask) >> pll->shift) + pll->m_offset; + + if (m == 0) + m = pll->max; + + if (pll->half_m) + return parent_rate * m * 2; + return parent_rate * m; +} + +static const struct clk_ops clk_sc5xx_cgu_pll_ops = { + .get_rate = sc5xx_cgu_pll_get_rate, +}; + +struct clk *sc5xx_cgu_pll(const char *name, const char *parent_name, + void __iomem *base, u8 shift, u8 width, u32 m_offset, + bool half_m) +{ + struct clk_sc5xx_cgu_pll *pll; + struct clk *clk; + int ret; + char *drv_name = ADI_CLK_PLL_GENERIC; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pll->base = base; + pll->shift = shift; + pll->mask = GENMASK(width - 1, 0) << shift; + pll->max = pll->mask + 1; + pll->m_offset = m_offset; + pll->half_m = half_m; + + clk = &pll->clk; + + ret = clk_register(clk, drv_name, name, parent_name); + if (ret) { + pr_err("Failed to register %s in %s: %d\n", name, __func__, ret); + kfree(pll); + return ERR_PTR(ret); + } + + return clk; +} + +U_BOOT_DRIVER(clk_adi_pll_generic) = { + .name = ADI_CLK_PLL_GENERIC, + .id = UCLASS_CLK, + .ops = &clk_sc5xx_cgu_pll_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/adi/clk-adi-sc57x.c b/drivers/clk/adi/clk-adi-sc57x.c new file mode 100644 index 00000000000..b17563f0444 --- /dev/null +++ b/drivers/clk/adi/clk-adi-sc57x.c @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Author: Greg Malysa + * + * Ported from Linux: Nathan Barrett-Morrison + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +static const char * const cgu1_in_sels[] = {"sys_clkin0", "sys_clkin1"}; +static const char * const sharc0_sels[] = {"cclk0_0", "sysclk_0", "dummy", "dummy"}; +static const char * const sharc1_sels[] = {"cclk0_0", "sysclk_0", "dummy", "dummy"}; +static const char * const arm_sels[] = {"cclk1_0", "sysclk_0", "dummy", "dummy"}; +static const char * const cdu_ddr_sels[] = {"dclk_0", "dclk_1", "dummy", "dummy"}; +static const char * const can_sels[] = {"oclk_0", "oclk_1", "dclk_1", "oclk_0_half"}; +static const char * const spdif_sels[] = {"oclk_0", "oclk_1", "dclk_1", "dclk_0"}; +static const char * const gige_sels[] = {"sclk1_0", "sclk1_1", "cclk0_1", "oclk_0"}; +static const char * const sdio_sels[] = {"oclk_0_half", "cclk1_1_half", "cclk1_1", + "dclk_1"}; + +static int sc57x_clock_probe(struct udevice *dev) +{ + void __iomem *cgu0; + void __iomem *cgu1; + void __iomem *cdu; + int ret; + struct resource res; + + struct clk *clks[ADSP_SC57X_CLK_END]; + struct clk dummy, clkin0, clkin1; + + ret = dev_read_resource_byname(dev, "cgu0", &res); + if (ret) + return ret; + cgu0 = devm_ioremap(dev, res.start, resource_size(&res)); + + ret = dev_read_resource_byname(dev, "cgu1", &res); + if (ret) + return ret; + cgu1 = devm_ioremap(dev, res.start, resource_size(&res)); + + ret = dev_read_resource_byname(dev, "cdu", &res); + if (ret) + return ret; + cdu = devm_ioremap(dev, res.start, resource_size(&res)); + + // Input clock configuration + clk_get_by_name(dev, "dummy", &dummy); + clk_get_by_name(dev, "sys_clkin0", &clkin0); + clk_get_by_name(dev, "sys_clkin1", &clkin1); + + clks[ADSP_SC57X_CLK_DUMMY] = &dummy; + clks[ADSP_SC57X_CLK_SYS_CLKIN0] = &clkin0; + clks[ADSP_SC57X_CLK_SYS_CLKIN1] = &clkin1; + + clks[ADSP_SC57X_CLK_CGU1_IN] = clk_register_mux(NULL, "cgu1_in_sel", cgu1_in_sels, + 2, CLK_SET_RATE_PARENT, + cdu + CDU_CLKINSEL, 0, 1, 0); + + // CGU configuration and internal clocks + clks[ADSP_SC57X_CLK_CGU0_PLL_IN] = clk_register_divider(NULL, "cgu0_df", + "sys_clkin0", + CLK_SET_RATE_PARENT, + cgu0 + CGU_CTL, 0, 1, 0); + clks[ADSP_SC57X_CLK_CGU1_PLL_IN] = clk_register_divider(NULL, "cgu1_df", + "cgu1_in_sel", + CLK_SET_RATE_PARENT, + cgu1 + CGU_CTL, 0, 1, 0); + + // VCO output == PLL output + clks[ADSP_SC57X_CLK_CGU0_PLLCLK] = sc5xx_cgu_pll("cgu0_pllclk", "cgu0_df", + cgu0 + CGU_CTL, CGU_MSEL_SHIFT, + CGU_MSEL_WIDTH, 0, false); + clks[ADSP_SC57X_CLK_CGU1_PLLCLK] = sc5xx_cgu_pll("cgu1_pllclk", "cgu1_df", + cgu1 + CGU_CTL, CGU_MSEL_SHIFT, + CGU_MSEL_WIDTH, 0, false); + + // Dividers from pll output + clks[ADSP_SC57X_CLK_CGU0_CDIV] = cgu_divider("cgu0_cdiv", "cgu0_pllclk", + cgu0 + CGU_DIV, 0, 5, 0); + clks[ADSP_SC57X_CLK_CGU0_SYSCLK] = cgu_divider("sysclk_0", "cgu0_pllclk", + cgu0 + CGU_DIV, 8, 5, 0); + clks[ADSP_SC57X_CLK_CGU0_DDIV] = cgu_divider("cgu0_ddiv", "cgu0_pllclk", + cgu0 + CGU_DIV, 16, 5, 0); + clks[ADSP_SC57X_CLK_CGU0_ODIV] = cgu_divider("cgu0_odiv", "cgu0_pllclk", + cgu0 + CGU_DIV, 22, 7, 0); + clks[ADSP_SC57X_CLK_CGU0_S0SELDIV] = cgu_divider("cgu0_s0seldiv", "sysclk_0", + cgu0 + CGU_DIV, 5, 3, 0); + clks[ADSP_SC57X_CLK_CGU0_S1SELDIV] = cgu_divider("cgu0_s1seldiv", "sysclk_0", + cgu0 + CGU_DIV, 13, 3, 0); + + clks[ADSP_SC57X_CLK_CGU1_CDIV] = cgu_divider("cgu1_cdiv", "cgu1_pllclk", + cgu1 + CGU_DIV, 0, 5, 0); + clks[ADSP_SC57X_CLK_CGU1_SYSCLK] = cgu_divider("sysclk_1", "cgu1_pllclk", + cgu1 + CGU_DIV, 8, 5, 0); + clks[ADSP_SC57X_CLK_CGU1_DDIV] = cgu_divider("cgu1_ddiv", "cgu1_pllclk", + cgu1 + CGU_DIV, 16, 5, 0); + clks[ADSP_SC57X_CLK_CGU1_ODIV] = cgu_divider("cgu1_odiv", "cgu1_pllclk", + cgu1 + CGU_DIV, 22, 7, 0); + clks[ADSP_SC57X_CLK_CGU1_S0SELDIV] = cgu_divider("cgu1_s0seldiv", + "sysclk_1", cgu1 + CGU_DIV, 5, + 3, 0); + clks[ADSP_SC57X_CLK_CGU1_S1SELDIV] = cgu_divider("cgu1_s1seldiv", + "sysclk_1", cgu1 + CGU_DIV, 13, + 3, 0); + + // Gates to enable CGU outputs + clks[ADSP_SC57X_CLK_CGU0_CCLK0] = cgu_gate("cclk0_0", "cgu0_cdiv", + cgu0 + CGU_CCBF_DIS, 0); + clks[ADSP_SC57X_CLK_CGU0_CCLK1] = cgu_gate("cclk1_0", "cgu0_cdiv", + cgu1 + CGU_CCBF_DIS, 1); + clks[ADSP_SC57X_CLK_CGU0_OCLK] = cgu_gate("oclk_0", "cgu0_odiv", + cgu0 + CGU_SCBF_DIS, 3); + clks[ADSP_SC57X_CLK_CGU0_DCLK] = cgu_gate("dclk_0", "cgu0_ddiv", + cgu0 + CGU_SCBF_DIS, 2); + clks[ADSP_SC57X_CLK_CGU0_SCLK1] = cgu_gate("sclk1_0", "cgu0_s1seldiv", + cgu0 + CGU_SCBF_DIS, 1); + clks[ADSP_SC57X_CLK_CGU0_SCLK0] = cgu_gate("sclk0_0", "cgu0_s0seldiv", + cgu0 + CGU_SCBF_DIS, 0); + + clks[ADSP_SC57X_CLK_CGU1_CCLK0] = cgu_gate("cclk0_1", "cgu1_cdiv", + cgu1 + CGU_CCBF_DIS, 0); + clks[ADSP_SC57X_CLK_CGU1_CCLK1] = cgu_gate("cclk1_1", "cgu1_cdiv", + cgu1 + CGU_CCBF_DIS, 1); + clks[ADSP_SC57X_CLK_CGU1_OCLK] = cgu_gate("oclk_1", "cgu1_odiv", + cgu1 + CGU_SCBF_DIS, 3); + clks[ADSP_SC57X_CLK_CGU1_DCLK] = cgu_gate("dclk_1", "cgu1_ddiv", + cgu1 + CGU_SCBF_DIS, 2); + clks[ADSP_SC57X_CLK_CGU1_SCLK1] = cgu_gate("sclk1_1", "cgu1_s1seldiv", + cgu1 + CGU_SCBF_DIS, 1); + clks[ADSP_SC57X_CLK_CGU1_SCLK0] = cgu_gate("sclk0_1", "cgu1_s0seldiv", + cgu1 + CGU_SCBF_DIS, 0); + + // Extra half rate clocks generated in the CDU + clks[ADSP_SC57X_CLK_OCLK0_HALF] = clk_register_fixed_factor(NULL, "oclk_0_half", + "oclk_0", + CLK_SET_RATE_PARENT, + 1, 2); + clks[ADSP_SC57X_CLK_CCLK1_1_HALF] = clk_register_fixed_factor(NULL, + "cclk1_1_half", + "cclk1_1", + CLK_SET_RATE_PARENT, + 1, 2); + + // CDU output muxes + clks[ADSP_SC57X_CLK_SHARC0_SEL] = cdu_mux("sharc0_sel", cdu + CDU_CFG0, + sharc0_sels); + clks[ADSP_SC57X_CLK_SHARC1_SEL] = cdu_mux("sharc1_sel", cdu + CDU_CFG1, + sharc1_sels); + clks[ADSP_SC57X_CLK_ARM_SEL] = cdu_mux("arm_sel", cdu + CDU_CFG2, arm_sels); + clks[ADSP_SC57X_CLK_CDU_DDR_SEL] = cdu_mux("cdu_ddr_sel", cdu + CDU_CFG3, + cdu_ddr_sels); + clks[ADSP_SC57X_CLK_CAN_SEL] = cdu_mux("can_sel", cdu + CDU_CFG4, can_sels); + clks[ADSP_SC57X_CLK_SPDIF_SEL] = cdu_mux("spdif_sel", cdu + CDU_CFG5, spdif_sels); + clks[ADSP_SC57X_CLK_GIGE_SEL] = cdu_mux("gige_sel", cdu + CDU_CFG7, gige_sels); + clks[ADSP_SC57X_CLK_SDIO_SEL] = cdu_mux("sdio_sel", cdu + CDU_CFG9, sdio_sels); + + // CDU output enable gates + clks[ADSP_SC57X_CLK_SHARC0] = cdu_gate("sharc0", "sharc0_sel", cdu + CDU_CFG0, + CLK_IS_CRITICAL); + clks[ADSP_SC57X_CLK_SHARC1] = cdu_gate("sharc1", "sharc1_sel", cdu + CDU_CFG1, + CLK_IS_CRITICAL); + clks[ADSP_SC57X_CLK_ARM] = cdu_gate("arm", "arm_sel", cdu + CDU_CFG2, + CLK_IS_CRITICAL); + clks[ADSP_SC57X_CLK_CDU_DDR] = cdu_gate("cdu_ddr", "cdu_ddr_sel", cdu + CDU_CFG3, + CLK_IS_CRITICAL); + clks[ADSP_SC57X_CLK_CAN] = cdu_gate("can", "can_sel", cdu + CDU_CFG4, 0); + clks[ADSP_SC57X_CLK_SPDIF] = cdu_gate("spdif", "spdif_sel", cdu + CDU_CFG5, 0); + clks[ADSP_SC57X_CLK_GIGE] = cdu_gate("gige", "gige_sel", cdu + CDU_CFG7, 0); + clks[ADSP_SC57X_CLK_SDIO] = cdu_gate("sdio", "sdio_sel", cdu + CDU_CFG9, 0); + + ret = cdu_check_clocks(clks, ARRAY_SIZE(clks)); + if (ret) + pr_err("CDU error detected\n"); + + return ret; +} + +static const struct udevice_id adi_sc57x_clk_ids[] = { + { .compatible = "adi,sc57x-clocks" }, + { }, +}; + +U_BOOT_DRIVER(adi_sc57x_clk) = { + .name = "clk_adi_sc57x", + .id = UCLASS_CLK, + .of_match = adi_sc57x_clk_ids, + .ops = &adi_clk_ops, + .probe = sc57x_clock_probe, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/adi/clk-adi-sc58x.c b/drivers/clk/adi/clk-adi-sc58x.c new file mode 100644 index 00000000000..05a0feddec7 --- /dev/null +++ b/drivers/clk/adi/clk-adi-sc58x.c @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Author: Greg Malysa + * + * Ported from Linux: Nathan Barrett-Morrison + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +static const char * const cgu1_in_sels[] = {"sys_clkin0", "sys_clkin1"}; +static const char * const sharc0_sels[] = {"cclk0_0", "sysclk_0", "dummy", "dummy"}; +static const char * const sharc1_sels[] = {"cclk0_0", "sysclk_0", "dummy", "dummy"}; +static const char * const arm_sels[] = {"cclk1_0", "sysclk_0", "dummy", "dummy"}; +static const char * const cdu_ddr_sels[] = {"dclk_0", "dclk_1", "dummy", "dummy"}; +static const char * const can_sels[] = {"oclk_0", "oclk_1", "dclk_1", "dummy"}; +static const char * const spdif_sels[] = {"oclk_0", "oclk_1", "dclk_1", "dclk_0"}; +static const char * const reserved_sels[] = {"sclk0_0", "oclk_0", "dummy", "dummy"}; +static const char * const gige_sels[] = {"sclk0_0", "sclk1_1", "cclk0_1", "oclk_0"}; +static const char * const lp_sels[] = {"sclk0_0", "sclk0_1", "cclk1_1", "dclk_1"}; +static const char * const sdio_sels[] = {"oclk_0_half", "cclk1_1_half", "cclk1_1", + "dclk_1"}; + +static int sc58x_clock_probe(struct udevice *dev) +{ + void __iomem *cgu0; + void __iomem *cgu1; + void __iomem *cdu; + int ret; + struct resource res; + + struct clk *clks[ADSP_SC58X_CLK_END]; + struct clk dummy, clkin0, clkin1; + + ret = dev_read_resource_byname(dev, "cgu0", &res); + if (ret) + return ret; + cgu0 = devm_ioremap(dev, res.start, resource_size(&res)); + + ret = dev_read_resource_byname(dev, "cgu1", &res); + if (ret) + return ret; + cgu1 = devm_ioremap(dev, res.start, resource_size(&res)); + + ret = dev_read_resource_byname(dev, "cdu", &res); + if (ret) + return ret; + cdu = devm_ioremap(dev, res.start, resource_size(&res)); + + // Input clock configuration + clk_get_by_name(dev, "dummy", &dummy); + clk_get_by_name(dev, "sys_clkin0", &clkin0); + clk_get_by_name(dev, "sys_clkin1", &clkin1); + + clks[ADSP_SC58X_CLK_DUMMY] = &dummy; + clks[ADSP_SC58X_CLK_SYS_CLKIN0] = &clkin0; + clks[ADSP_SC58X_CLK_SYS_CLKIN1] = &clkin1; + + clks[ADSP_SC58X_CLK_CGU1_IN] = clk_register_mux(NULL, "cgu1_in_sel", cgu1_in_sels, + 2, CLK_SET_RATE_PARENT, + cdu + CDU_CLKINSEL, 0, 1, 0); + + // CGU configuration and internal clocks + clks[ADSP_SC58X_CLK_CGU0_PLL_IN] = clk_register_divider(NULL, "cgu0_df", + "sys_clkin0", + CLK_SET_RATE_PARENT, + cgu0 + CGU_CTL, 0, 1, 0); + clks[ADSP_SC58X_CLK_CGU1_PLL_IN] = clk_register_divider(NULL, "cgu1_df", + "cgu1_in_sel", + CLK_SET_RATE_PARENT, + cgu1 + CGU_CTL, 0, 1, 0); + + // VCO output inside PLL + clks[ADSP_SC58X_CLK_CGU0_VCO_OUT] = sc5xx_cgu_pll("cgu0_vco", "cgu0_df", + cgu0 + CGU_CTL, CGU_MSEL_SHIFT, + CGU_MSEL_WIDTH, 0, false); + clks[ADSP_SC58X_CLK_CGU1_VCO_OUT] = sc5xx_cgu_pll("cgu1_vco", "cgu1_df", + cgu1 + CGU_CTL, CGU_MSEL_SHIFT, + CGU_MSEL_WIDTH, 0, false); + + // Final PLL output + clks[ADSP_SC58X_CLK_CGU0_PLLCLK] = clk_register_fixed_factor(NULL, "cgu0_pllclk", + "cgu0_vco", + CLK_SET_RATE_PARENT, + 1, 1); + clks[ADSP_SC58X_CLK_CGU1_PLLCLK] = clk_register_fixed_factor(NULL, "cgu1_pllclk", + "cgu1_vco", + CLK_SET_RATE_PARENT, + 1, 1); + + // Dividers from pll output + clks[ADSP_SC58X_CLK_CGU0_CDIV] = cgu_divider("cgu0_cdiv", "cgu0_pllclk", + cgu0 + CGU_DIV, 0, 5, 0); + clks[ADSP_SC58X_CLK_CGU0_SYSCLK] = cgu_divider("sysclk_0", "cgu0_pllclk", + cgu0 + CGU_DIV, 8, 5, 0); + clks[ADSP_SC58X_CLK_CGU0_DDIV] = cgu_divider("cgu0_ddiv", "cgu0_pllclk", + cgu0 + CGU_DIV, 16, 5, 0); + clks[ADSP_SC58X_CLK_CGU0_ODIV] = cgu_divider("cgu0_odiv", "cgu0_pllclk", + cgu0 + CGU_DIV, 22, 7, 0); + clks[ADSP_SC58X_CLK_CGU0_S0SELDIV] = cgu_divider("cgu0_s0seldiv", "sysclk_0", + cgu0 + CGU_DIV, 5, 3, 0); + clks[ADSP_SC58X_CLK_CGU0_S1SELDIV] = cgu_divider("cgu0_s1seldiv", "sysclk_0", + cgu0 + CGU_DIV, 13, 3, 0); + + clks[ADSP_SC58X_CLK_CGU1_CDIV] = cgu_divider("cgu1_cdiv", "cgu1_pllclk", + cgu1 + CGU_DIV, 0, 5, 0); + clks[ADSP_SC58X_CLK_CGU1_SYSCLK] = cgu_divider("sysclk_1", "cgu1_pllclk", + cgu1 + CGU_DIV, 8, 5, 0); + clks[ADSP_SC58X_CLK_CGU1_DDIV] = cgu_divider("cgu1_ddiv", "cgu1_pllclk", + cgu1 + CGU_DIV, 16, 5, 0); + clks[ADSP_SC58X_CLK_CGU1_ODIV] = cgu_divider("cgu1_odiv", "cgu1_pllclk", + cgu1 + CGU_DIV, 22, 7, 0); + clks[ADSP_SC58X_CLK_CGU1_S0SELDIV] = cgu_divider("cgu1_s0seldiv", "sysclk_1", + cgu1 + CGU_DIV, 5, 3, 0); + clks[ADSP_SC58X_CLK_CGU1_S1SELDIV] = cgu_divider("cgu1_s1seldiv", "sysclk_1", + cgu1 + CGU_DIV, 13, 3, 0); + + // Gates to enable CGU outputs + clks[ADSP_SC58X_CLK_CGU0_CCLK0] = cgu_gate("cclk0_0", "cgu0_cdiv", + cgu0 + CGU_CCBF_DIS, 0); + clks[ADSP_SC58X_CLK_CGU0_CCLK1] = cgu_gate("cclk1_0", "cgu0_cdiv", + cgu1 + CGU_CCBF_DIS, 1); + clks[ADSP_SC58X_CLK_CGU0_OCLK] = cgu_gate("oclk_0", "cgu0_odiv", + cgu0 + CGU_SCBF_DIS, 3); + clks[ADSP_SC58X_CLK_CGU0_DCLK] = cgu_gate("dclk_0", "cgu0_ddiv", + cgu0 + CGU_SCBF_DIS, 2); + clks[ADSP_SC58X_CLK_CGU0_SCLK1] = cgu_gate("sclk1_0", "cgu0_s1seldiv", + cgu0 + CGU_SCBF_DIS, 1); + clks[ADSP_SC58X_CLK_CGU0_SCLK0] = cgu_gate("sclk0_0", "cgu0_s0seldiv", + cgu0 + CGU_SCBF_DIS, 0); + + clks[ADSP_SC58X_CLK_CGU1_CCLK0] = cgu_gate("cclk0_1", "cgu1_cdiv", + cgu1 + CGU_CCBF_DIS, 0); + clks[ADSP_SC58X_CLK_CGU1_CCLK1] = cgu_gate("cclk1_1", "cgu1_cdiv", + cgu1 + CGU_CCBF_DIS, 1); + clks[ADSP_SC58X_CLK_CGU1_OCLK] = cgu_gate("oclk_1", "cgu1_odiv", + cgu1 + CGU_SCBF_DIS, 3); + clks[ADSP_SC58X_CLK_CGU1_DCLK] = cgu_gate("dclk_1", "cgu1_ddiv", + cgu1 + CGU_SCBF_DIS, 2); + clks[ADSP_SC58X_CLK_CGU1_SCLK1] = cgu_gate("sclk1_1", "cgu1_s1seldiv", + cgu1 + CGU_SCBF_DIS, 1); + clks[ADSP_SC58X_CLK_CGU1_SCLK0] = cgu_gate("sclk0_1", "cgu1_s0seldiv", + cgu1 + CGU_SCBF_DIS, 0); + + // Extra half rate clocks generated in the CDU + clks[ADSP_SC58X_CLK_OCLK0_HALF] = clk_register_fixed_factor(NULL, "oclk_0_half", + "oclk_0", + CLK_SET_RATE_PARENT, + 1, 2); + clks[ADSP_SC58X_CLK_CCLK1_1_HALF] = clk_register_fixed_factor(NULL, + "cclk1_1_half", + "cclk1_1", + CLK_SET_RATE_PARENT, + 1, 2); + + // CDU output muxes + clks[ADSP_SC58X_CLK_SHARC0_SEL] = cdu_mux("sharc0_sel", cdu + CDU_CFG0, + sharc0_sels); + clks[ADSP_SC58X_CLK_SHARC1_SEL] = cdu_mux("sharc1_sel", cdu + CDU_CFG1, + sharc1_sels); + clks[ADSP_SC58X_CLK_ARM_SEL] = cdu_mux("arm_sel", cdu + CDU_CFG2, arm_sels); + clks[ADSP_SC58X_CLK_CDU_DDR_SEL] = cdu_mux("cdu_ddr_sel", cdu + CDU_CFG3, + cdu_ddr_sels); + clks[ADSP_SC58X_CLK_CAN_SEL] = cdu_mux("can_sel", cdu + CDU_CFG4, can_sels); + clks[ADSP_SC58X_CLK_SPDIF_SEL] = cdu_mux("spdif_sel", cdu + CDU_CFG5, spdif_sels); + clks[ADSP_SC58X_CLK_RESERVED_SEL] = cdu_mux("reserved_sel", cdu + CDU_CFG6, + reserved_sels); + clks[ADSP_SC58X_CLK_GIGE_SEL] = cdu_mux("gige_sel", cdu + CDU_CFG7, gige_sels); + clks[ADSP_SC58X_CLK_LP_SEL] = cdu_mux("lp_sel", cdu + CDU_CFG8, lp_sels); + clks[ADSP_SC58X_CLK_SDIO_SEL] = cdu_mux("sdio_sel", cdu + CDU_CFG9, sdio_sels); + + // CDU output enable gates + clks[ADSP_SC58X_CLK_SHARC0] = cdu_gate("sharc0", "sharc0_sel", cdu + CDU_CFG0, + CLK_IS_CRITICAL); + clks[ADSP_SC58X_CLK_SHARC1] = cdu_gate("sharc1", "sharc1_sel", cdu + CDU_CFG1, + CLK_IS_CRITICAL); + clks[ADSP_SC58X_CLK_ARM] = cdu_gate("arm", "arm_sel", cdu + CDU_CFG2, + CLK_IS_CRITICAL); + clks[ADSP_SC58X_CLK_CDU_DDR] = cdu_gate("cdu_ddr", "cdu_ddr_sel", cdu + CDU_CFG3, + CLK_IS_CRITICAL); + clks[ADSP_SC58X_CLK_CAN] = cdu_gate("can", "can_sel", cdu + CDU_CFG4, 0); + clks[ADSP_SC58X_CLK_SPDIF] = cdu_gate("spdif", "spdif_sel", cdu + CDU_CFG5, 0); + clks[ADSP_SC58X_CLK_RESERVED] = cdu_gate("reserved", "reserved_sel", + cdu + CDU_CFG6, 0); + clks[ADSP_SC58X_CLK_GIGE] = cdu_gate("gige", "gige_sel", cdu + CDU_CFG7, 0); + clks[ADSP_SC58X_CLK_LP] = cdu_gate("lp", "lp_sel", cdu + CDU_CFG8, 0); + clks[ADSP_SC58X_CLK_SDIO] = cdu_gate("sdio", "sdio_sel", cdu + CDU_CFG9, 0); + + ret = cdu_check_clocks(clks, ARRAY_SIZE(clks)); + if (ret) + pr_err("CDU error detected\n"); + + return ret; +} + +static const struct udevice_id adi_sc58x_clk_ids[] = { + { .compatible = "adi,sc58x-clocks" }, + { }, +}; + +U_BOOT_DRIVER(adi_sc58x_clk) = { + .name = "clk_adi_sc58x", + .id = UCLASS_CLK, + .of_match = adi_sc58x_clk_ids, + .ops = &adi_clk_ops, + .probe = sc58x_clock_probe, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/adi/clk-adi-sc594.c b/drivers/clk/adi/clk-adi-sc594.c new file mode 100644 index 00000000000..c80bbf9728d --- /dev/null +++ b/drivers/clk/adi/clk-adi-sc594.c @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Author: Greg Malysa + * + * Ported from Linux: Nathan Barrett-Morrison + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +static const char * const cgu1_in_sels[] = {"sys_clkin0", "sys_clkin1"}; +static const char * const cgu0_s1sels[] = {"cgu0_s1seldiv", "cgu0_s1selexdiv"}; +static const char * const cgu1_s1sels[] = {"cgu1_s1seldiv", "cgu1_s1selexdiv"}; +static const char * const sharc0_sels[] = {"cclk0_0", "dummy", "dummy", "dummy"}; +static const char * const sharc1_sels[] = {"cclk0_0", "dummy", "dummy", "dummy"}; +static const char * const arm_sels[] = {"cclk1_0", "dummy", "dummy", "dummy"}; +static const char * const cdu_ddr_sels[] = {"dclk_0", "dclk_1", "dummy", "dummy"}; +static const char * const can_sels[] = {"oclk_0", "oclk_1", "dummy", "dummy"}; +static const char * const spdif_sels[] = {"sclk1_0", "dummy", "dummy", "dummy"}; +static const char * const spi_sels[] = {"sclk0_0", "oclk_0", "dummy", "dummy"}; +static const char * const gige_sels[] = {"sclk0_0", "sclk0_1", "cclk0_1", "dummy"}; +static const char * const lp_sels[] = {"oclk_0", "sclk0_0", "cclk0_1", "dummy"}; +static const char * const lpddr_sels[] = {"oclk_0", "dclk_0", "sysclkin_1", "dummy"}; +static const char * const ospi_sels[] = {"sysclk_0", "sclk0_0", "sclk1_1", "dummy"}; +static const char * const trace_sels[] = {"sclk0_0", "dummy", "dummy", "dummy"}; + +static int sc594_clock_probe(struct udevice *dev) +{ + void __iomem *cgu0; + void __iomem *cgu1; + void __iomem *cdu; + int ret; + struct resource res; + + struct clk *clks[ADSP_SC594_CLK_END]; + struct clk dummy, clkin0, clkin1; + + ret = dev_read_resource_byname(dev, "cgu0", &res); + if (ret) + return ret; + cgu0 = devm_ioremap(dev, res.start, resource_size(&res)); + + ret = dev_read_resource_byname(dev, "cgu1", &res); + if (ret) + return ret; + cgu1 = devm_ioremap(dev, res.start, resource_size(&res)); + + ret = dev_read_resource_byname(dev, "cdu", &res); + if (ret) + return ret; + cdu = devm_ioremap(dev, res.start, resource_size(&res)); + + // Input clock configuration + clk_get_by_name(dev, "dummy", &dummy); + clk_get_by_name(dev, "sys_clkin0", &clkin0); + clk_get_by_name(dev, "sys_clkin1", &clkin1); + + clks[ADSP_SC594_CLK_DUMMY] = &dummy; + clks[ADSP_SC594_CLK_SYS_CLKIN0] = &clkin0; + clks[ADSP_SC594_CLK_SYS_CLKIN1] = &clkin1; + clks[ADSP_SC594_CLK_CGU1_IN] = clk_register_mux(NULL, "cgu1_in_sel", cgu1_in_sels, + 2, CLK_SET_RATE_PARENT, + cdu + CDU_CLKINSEL, 0, 1, 0); + + // CGU configuration and internal clocks + clks[ADSP_SC594_CLK_CGU0_PLL_IN] = clk_register_divider(NULL, "cgu0_df", + "sys_clkin0", + CLK_SET_RATE_PARENT, + cgu0 + CGU_CTL, 0, 1, 0); + clks[ADSP_SC594_CLK_CGU1_PLL_IN] = clk_register_divider(NULL, "cgu1_df", + "cgu1_in_sel", + CLK_SET_RATE_PARENT, + cgu1 + CGU_CTL, 0, 1, 0); + + // VCO output inside PLL + clks[ADSP_SC594_CLK_CGU0_VCO_OUT] = sc5xx_cgu_pll("cgu0_vco", "cgu0_df", + cgu0 + CGU_CTL, CGU_MSEL_SHIFT, + CGU_MSEL_WIDTH, 0, false); + clks[ADSP_SC594_CLK_CGU1_VCO_OUT] = sc5xx_cgu_pll("cgu1_vco", "cgu1_df", + cgu1 + CGU_CTL, CGU_MSEL_SHIFT, + CGU_MSEL_WIDTH, 0, false); + + // Final PLL output + clks[ADSP_SC594_CLK_CGU0_PLLCLK] = clk_register_fixed_factor(NULL, "cgu0_pllclk", + "cgu0_vco", + CLK_SET_RATE_PARENT, + 1, 1); + clks[ADSP_SC594_CLK_CGU1_PLLCLK] = clk_register_fixed_factor(NULL, "cgu1_pllclk", + "cgu1_vco", + CLK_SET_RATE_PARENT, + 1, 1); + + // Dividers from pll output + clks[ADSP_SC594_CLK_CGU0_CDIV] = cgu_divider("cgu0_cdiv", "cgu0_pllclk", + cgu0 + CGU_DIV, 0, 5, 0); + clks[ADSP_SC594_CLK_CGU0_SYSCLK] = cgu_divider("sysclk_0", "cgu0_pllclk", + cgu0 + CGU_DIV, 8, 5, 0); + clks[ADSP_SC594_CLK_CGU0_DDIV] = cgu_divider("cgu0_ddiv", "cgu0_pllclk", + cgu0 + CGU_DIV, 16, 5, 0); + clks[ADSP_SC594_CLK_CGU0_ODIV] = cgu_divider("cgu0_odiv", "cgu0_pllclk", + cgu0 + CGU_DIV, 22, 7, 0); + clks[ADSP_SC594_CLK_CGU0_S0SELDIV] = cgu_divider("cgu0_s0seldiv", "sysclk_0", + cgu0 + CGU_DIV, 5, 3, 0); + clks[ADSP_SC594_CLK_CGU0_S1SELDIV] = cgu_divider("cgu0_s1seldiv", "sysclk_0", + cgu0 + CGU_DIV, 13, 3, 0); + clks[ADSP_SC594_CLK_CGU0_S1SELEXDIV] = cgu_divider("cgu0_s1selexdiv", + "cgu0_pllclk", + cgu0 + CGU_DIVEX, 16, 8, 0); + clks[ADSP_SC594_CLK_CGU0_S1SEL] = clk_register_mux(NULL, "cgu0_sclk1sel", + cgu0_s1sels, 2, + CLK_SET_RATE_PARENT, + cgu0 + CGU_CTL, 17, 1, 0); + + clks[ADSP_SC594_CLK_CGU1_CDIV] = cgu_divider("cgu1_cdiv", "cgu1_pllclk", + cgu1 + CGU_DIV, 0, 5, 0); + clks[ADSP_SC594_CLK_CGU1_SYSCLK] = cgu_divider("sysclk_1", "cgu1_pllclk", + cgu1 + CGU_DIV, 8, 5, 0); + clks[ADSP_SC594_CLK_CGU1_DDIV] = cgu_divider("cgu1_ddiv", "cgu1_pllclk", + cgu1 + CGU_DIV, 16, 5, 0); + clks[ADSP_SC594_CLK_CGU1_ODIV] = cgu_divider("cgu1_odiv", "cgu1_pllclk", + cgu1 + CGU_DIV, 22, 7, 0); + clks[ADSP_SC594_CLK_CGU1_S0SELDIV] = cgu_divider("cgu1_s0seldiv", "sysclk_1", + cgu1 + CGU_DIV, 5, 3, 0); + clks[ADSP_SC594_CLK_CGU1_S1SELDIV] = cgu_divider("cgu1_s1seldiv", "sysclk_1", + cgu1 + CGU_DIV, 13, 3, 0); + clks[ADSP_SC594_CLK_CGU1_S1SELEXDIV] = cgu_divider("cgu1_s1selexdiv", + "cgu1_pllclk", + cgu1 + CGU_DIVEX, 16, 8, 0); + clks[ADSP_SC594_CLK_CGU1_S1SEL] = clk_register_mux(NULL, "cgu1_sclk1sel", + cgu1_s1sels, 2, + CLK_SET_RATE_PARENT, + cgu1 + CGU_CTL, 17, 1, 0); + + // Gates to enable CGU outputs + clks[ADSP_SC594_CLK_CGU0_CCLK0] = cgu_gate("cclk0_0", "cgu0_cdiv", + cgu0 + CGU_CCBF_DIS, 0); + clks[ADSP_SC594_CLK_CGU0_CCLK1] = cgu_gate("cclk1_0", "cgu0_cdiv", + cgu1 + CGU_CCBF_DIS, 1); + clks[ADSP_SC594_CLK_CGU0_OCLK] = cgu_gate("oclk_0", "cgu0_odiv", + cgu0 + CGU_SCBF_DIS, 3); + clks[ADSP_SC594_CLK_CGU0_DCLK] = cgu_gate("dclk_0", "cgu0_ddiv", + cgu0 + CGU_SCBF_DIS, 2); + clks[ADSP_SC594_CLK_CGU0_SCLK1] = cgu_gate("sclk1_0", "cgu0_sclk1sel", + cgu0 + CGU_SCBF_DIS, 1); + clks[ADSP_SC594_CLK_CGU0_SCLK0] = cgu_gate("sclk0_0", "cgu0_s0seldiv", + cgu0 + CGU_SCBF_DIS, 0); + + clks[ADSP_SC594_CLK_CGU1_CCLK0] = cgu_gate("cclk0_1", "cgu1_cdiv", + cgu1 + CGU_CCBF_DIS, 0); + clks[ADSP_SC594_CLK_CGU1_CCLK1] = cgu_gate("cclk1_1", "cgu1_cdiv", + cgu1 + CGU_CCBF_DIS, 1); + clks[ADSP_SC594_CLK_CGU1_OCLK] = cgu_gate("oclk_1", "cgu1_odiv", + cgu1 + CGU_SCBF_DIS, 3); + clks[ADSP_SC594_CLK_CGU1_DCLK] = cgu_gate("dclk_1", "cgu1_ddiv", + cgu1 + CGU_SCBF_DIS, 2); + clks[ADSP_SC594_CLK_CGU1_SCLK1] = cgu_gate("sclk1_1", "cgu1_sclk1sel", + cgu1 + CGU_SCBF_DIS, 1); + clks[ADSP_SC594_CLK_CGU1_SCLK0] = cgu_gate("sclk0_1", "cgu1_s0seldiv", + cgu1 + CGU_SCBF_DIS, 0); + + // CDU output muxes + clks[ADSP_SC594_CLK_SHARC0_SEL] = cdu_mux("sharc0_sel", cdu + CDU_CFG0, + sharc0_sels); + clks[ADSP_SC594_CLK_SHARC1_SEL] = cdu_mux("sharc1_sel", cdu + CDU_CFG1, + sharc1_sels); + clks[ADSP_SC594_CLK_ARM_SEL] = cdu_mux("arm_sel", cdu + CDU_CFG2, arm_sels); + clks[ADSP_SC594_CLK_CDU_DDR_SEL] = cdu_mux("cdu_ddr_sel", cdu + CDU_CFG3, + cdu_ddr_sels); + clks[ADSP_SC594_CLK_CAN_SEL] = cdu_mux("can_sel", cdu + CDU_CFG4, can_sels); + clks[ADSP_SC594_CLK_SPDIF_SEL] = cdu_mux("spdif_sel", cdu + CDU_CFG5, spdif_sels); + clks[ADSP_SC594_CLK_RESERVED_SEL] = cdu_mux("spi_sel", cdu + CDU_CFG6, spi_sels); + clks[ADSP_SC594_CLK_GIGE_SEL] = cdu_mux("gige_sel", cdu + CDU_CFG7, gige_sels); + clks[ADSP_SC594_CLK_LP_SEL] = cdu_mux("lp_sel", cdu + CDU_CFG8, lp_sels); + clks[ADSP_SC594_CLK_LPDDR_SEL] = cdu_mux("lpddr_sel", cdu + CDU_CFG9, lpddr_sels); + clks[ADSP_SC594_CLK_OSPI_SEL] = cdu_mux("ospi_sel", cdu + CDU_CFG10, + ospi_sels); + clks[ADSP_SC594_CLK_TRACE_SEL] = cdu_mux("trace_sel", cdu + CDU_CFG12, + trace_sels); + + // CDU output enable gates + clks[ADSP_SC594_CLK_SHARC0] = cdu_gate("sharc0", "sharc0_sel", + cdu + CDU_CFG0, CLK_IS_CRITICAL); + clks[ADSP_SC594_CLK_SHARC1] = cdu_gate("sharc1", "sharc1_sel", + cdu + CDU_CFG1, CLK_IS_CRITICAL); + clks[ADSP_SC594_CLK_ARM] = cdu_gate("arm", "arm_sel", cdu + CDU_CFG2, + CLK_IS_CRITICAL); + clks[ADSP_SC594_CLK_CDU_DDR] = cdu_gate("cdu_ddr", "cdu_ddr_sel", + cdu + CDU_CFG3, CLK_IS_CRITICAL); + clks[ADSP_SC594_CLK_CAN] = cdu_gate("can", "can_sel", cdu + CDU_CFG4, 0); + clks[ADSP_SC594_CLK_SPDIF] = cdu_gate("spdif", "spdif_sel", cdu + CDU_CFG5, 0); + clks[ADSP_SC594_CLK_SPI] = cdu_gate("spi", "spi_sel", cdu + CDU_CFG6, 0); + clks[ADSP_SC594_CLK_GIGE] = cdu_gate("gige", "gige_sel", cdu + CDU_CFG7, 0); + clks[ADSP_SC594_CLK_LP] = cdu_gate("lp", "lp_sel", cdu + CDU_CFG8, 0); + clks[ADSP_SC594_CLK_LPDDR] = cdu_gate("lpddr", "lpddr_sel", cdu + CDU_CFG9, 0); + clks[ADSP_SC594_CLK_OSPI] = cdu_gate("ospi", "ospi_sel", cdu + CDU_CFG10, 0); + clks[ADSP_SC594_CLK_TRACE] = cdu_gate("trace", "trace_sel", cdu + CDU_CFG12, 0); + + ret = cdu_check_clocks(clks, ARRAY_SIZE(clks)); + if (ret) + pr_err("CDU error detected\n"); + + return ret; +} + +static const struct udevice_id adi_sc594_clk_ids[] = { + { .compatible = "adi,sc594-clocks" }, + { }, +}; + +U_BOOT_DRIVER(adi_sc594_clk) = { + .name = "clk_adi_sc594", + .id = UCLASS_CLK, + .of_match = adi_sc594_clk_ids, + .ops = &adi_clk_ops, + .probe = sc594_clock_probe, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/adi/clk-adi-sc598.c b/drivers/clk/adi/clk-adi-sc598.c new file mode 100644 index 00000000000..d4a16ac9603 --- /dev/null +++ b/drivers/clk/adi/clk-adi-sc598.c @@ -0,0 +1,308 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Author: Greg Malysa + * + * Ported from Linux: Nathan Barrett-Morrison + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +static const char * const cgu1_in_sels[] = {"sys_clkin0", "sys_clkin1"}; +static const char * const cgu0_s1sels[] = {"cgu0_s1seldiv", "cgu0_s1selexdiv"}; +static const char * const cgu1_s0sels[] = {"cgu1_s0seldiv", "cgu1_s0selexdiv"}; +static const char * const cgu1_s1sels[] = {"cgu1_s1seldiv", "cgu1_s1selexdiv"}; +static const char * const sharc0_sels[] = {"cclk0_0", "dummy", "dummy", "dummy"}; +static const char * const sharc1_sels[] = {"cclk0_0", "dummy", "dummy", "dummy"}; +static const char * const arm_sels[] = {"dummy", "dummy", "cclk2_0", "cclk2_1"}; +static const char * const cdu_ddr_sels[] = {"dclk_0", "dclk_1", "dummy", "dummy"}; +static const char * const can_sels[] = {"dummy", "oclk_1", "dummy", "dummy"}; +static const char * const spdif_sels[] = {"sclk1_0", "dummy", "dummy", "dummy"}; +static const char * const spi_sels[] = {"sclk0_0", "oclk_0", "dummy", "dummy"}; +static const char * const gige_sels[] = {"sclk0_0", "sclk0_1", "dummy", "dummy"}; +static const char * const lp_sels[] = {"oclk_0", "sclk0_0", "cclk0_1", "dummy"}; +static const char * const lp_ddr_sels[] = {"oclk_0", "dclk_0", "sysclk_1", "dummy"}; +static const char * const ospi_refclk_sels[] = {"sysclk_0", "sclk0_0", "sclk1_1", + "dummy"}; +static const char * const trace_sels[] = {"sclk0_0", "dummy", "dummy", "dummy"}; +static const char * const emmc_sels[] = {"oclk_0", "sclk0_1", "dclk_0_half", + "dclk_1_half"}; +static const char * const emmc_timer_sels[] = {"dummy", "sclk1_1_half", "dummy", + "dummy"}; +static const char * const ddr_sels[] = {"cdu_ddr", "3pll_ddiv"}; + +static int sc598_clock_probe(struct udevice *dev) +{ + void __iomem *cgu0; + void __iomem *cgu1; + void __iomem *cdu; + void __iomem *pll3; + int ret; + struct resource res; + + struct clk *clks[ADSP_SC598_CLK_END]; + struct clk dummy, clkin0, clkin1; + + ret = dev_read_resource_byname(dev, "cgu0", &res); + if (ret) + return ret; + cgu0 = devm_ioremap(dev, res.start, resource_size(&res)); + + ret = dev_read_resource_byname(dev, "cgu1", &res); + if (ret) + return ret; + cgu1 = devm_ioremap(dev, res.start, resource_size(&res)); + + ret = dev_read_resource_byname(dev, "cdu", &res); + if (ret) + return ret; + cdu = devm_ioremap(dev, res.start, resource_size(&res)); + + ret = dev_read_resource_byname(dev, "pll3", &res); + if (ret) + return ret; + pll3 = devm_ioremap(dev, res.start, resource_size(&res)); + + // We only access this one register for pll3 + pll3 = pll3 + PLL3_OFFSET; + + // Input clock configuration + clk_get_by_name(dev, "dummy", &dummy); + clk_get_by_name(dev, "sys_clkin0", &clkin0); + clk_get_by_name(dev, "sys_clkin1", &clkin1); + + clks[ADSP_SC598_CLK_DUMMY] = &dummy; + clks[ADSP_SC598_CLK_SYS_CLKIN0] = &clkin0; + clks[ADSP_SC598_CLK_SYS_CLKIN1] = &clkin1; + + clks[ADSP_SC598_CLK_CGU1_IN] = clk_register_mux(NULL, "cgu1_in_sel", cgu1_in_sels, + 2, CLK_SET_RATE_PARENT, + cdu + CDU_CLKINSEL, 0, 1, 0); + + // 3rd pll reuses cgu1 clk in selection, feeds directly into 3pll df + // changing the cgu1 in sel mux will affect 3pll so reuse the same clocks + + // CGU configuration and internal clocks + clks[ADSP_SC598_CLK_CGU0_PLL_IN] = clk_register_divider(NULL, "cgu0_df", + "sys_clkin0", + CLK_SET_RATE_PARENT, + cgu0 + CGU_CTL, 0, 1, 0); + clks[ADSP_SC598_CLK_CGU1_PLL_IN] = clk_register_divider(NULL, "cgu1_df", + "cgu1_in_sel", + CLK_SET_RATE_PARENT, + cgu1 + CGU_CTL, 0, 1, 0); + clks[ADSP_SC598_CLK_3PLL_PLL_IN] = clk_register_divider(NULL, "3pll_df", + "cgu1_in_sel", + CLK_SET_RATE_PARENT, + pll3, 3, 1, 0); + + // VCO output inside PLL + clks[ADSP_SC598_CLK_CGU0_VCO_OUT] = sc5xx_cgu_pll("cgu0_vco", "cgu0_df", + cgu0 + CGU_CTL, CGU_MSEL_SHIFT, + CGU_MSEL_WIDTH, 0, true); + clks[ADSP_SC598_CLK_CGU1_VCO_OUT] = sc5xx_cgu_pll("cgu1_vco", "cgu1_df", + cgu1 + CGU_CTL, CGU_MSEL_SHIFT, + CGU_MSEL_WIDTH, 0, true); + clks[ADSP_SC598_CLK_3PLL_VCO_OUT] = sc5xx_cgu_pll("3pll_vco", "3pll_df", + pll3, PLL3_MSEL_SHIFT, + PLL3_MSEL_WIDTH, 1, true); + + // Final PLL output + clks[ADSP_SC598_CLK_CGU0_PLLCLK] = clk_register_fixed_factor(NULL, "cgu0_pllclk", + "cgu0_vco", + CLK_SET_RATE_PARENT, + 1, 2); + clks[ADSP_SC598_CLK_CGU1_PLLCLK] = clk_register_fixed_factor(NULL, "cgu1_pllclk", + "cgu1_vco", + CLK_SET_RATE_PARENT, + 1, 2); + clks[ADSP_SC598_CLK_3PLL_PLLCLK] = clk_register_fixed_factor(NULL, "3pll_pllclk", + "3pll_vco", + CLK_SET_RATE_PARENT, + 1, 2); + + // Dividers from pll output + clks[ADSP_SC598_CLK_CGU0_CDIV] = cgu_divider("cgu0_cdiv", "cgu0_pllclk", + cgu0 + CGU_DIV, 0, 5, 0); + clks[ADSP_SC598_CLK_CGU0_SYSCLK] = cgu_divider("sysclk_0", "cgu0_pllclk", + cgu0 + CGU_DIV, 8, 5, 0); + clks[ADSP_SC598_CLK_CGU0_DDIV] = cgu_divider("cgu0_ddiv", "cgu0_pllclk", + cgu0 + CGU_DIV, 16, 5, 0); + clks[ADSP_SC598_CLK_CGU0_ODIV] = cgu_divider("cgu0_odiv", "cgu0_pllclk", + cgu0 + CGU_DIV, 22, 7, 0); + clks[ADSP_SC598_CLK_CGU0_S0SELDIV] = cgu_divider("cgu0_s0seldiv", "sysclk_0", + cgu0 + CGU_DIV, 5, 3, 0); + clks[ADSP_SC598_CLK_CGU0_S1SELDIV] = cgu_divider("cgu0_s1seldiv", "sysclk_0", + cgu0 + CGU_DIV, 13, 3, 0); + clks[ADSP_SC598_CLK_CGU0_S1SELEXDIV] = cgu_divider("cgu0_s1selexdiv", + "cgu0_pllclk", + cgu0 + CGU_DIVEX, 16, 8, 0); + clks[ADSP_SC598_CLK_CGU0_S1SEL] = clk_register_mux(NULL, "cgu0_sclk1sel", + cgu0_s1sels, 2, + CLK_SET_RATE_PARENT, + cgu0 + CGU_CTL, 17, 1, 0); + clks[ADSP_SC598_CLK_CGU0_CCLK2] = clk_register_fixed_factor(NULL, "cclk2_0", + "cgu0_vco", + CLK_SET_RATE_PARENT, + 1, 3); + + clks[ADSP_SC598_CLK_CGU1_CDIV] = cgu_divider("cgu1_cdiv", "cgu1_pllclk", + cgu1 + CGU_DIV, 0, 5, 0); + clks[ADSP_SC598_CLK_CGU1_SYSCLK] = cgu_divider("sysclk_1", "cgu1_pllclk", + cgu1 + CGU_DIV, 8, 5, 0); + clks[ADSP_SC598_CLK_CGU1_DDIV] = cgu_divider("cgu1_ddiv", "cgu1_pllclk", + cgu1 + CGU_DIV, 16, 5, 0); + clks[ADSP_SC598_CLK_CGU1_ODIV] = cgu_divider("cgu1_odiv", "cgu1_pllclk", + cgu1 + CGU_DIV, 22, 7, 0); + clks[ADSP_SC598_CLK_CGU1_S0SELDIV] = cgu_divider("cgu1_s0seldiv", "sysclk_1", + cgu1 + CGU_DIV, 5, 3, 0); + clks[ADSP_SC598_CLK_CGU1_S1SELDIV] = cgu_divider("cgu1_s1seldiv", "sysclk_1", + cgu1 + CGU_DIV, 13, 3, 0); + clks[ADSP_SC598_CLK_CGU1_S0SELEXDIV] = cgu_divider("cgu1_s0selexdiv", + "cgu1_pllclk", + cgu1 + CGU_DIVEX, 0, 8, 0); + clks[ADSP_SC598_CLK_CGU1_S1SELEXDIV] = cgu_divider("cgu1_s1selexdiv", + "cgu1_pllclk", + cgu1 + CGU_DIVEX, 16, 8, 0); + clks[ADSP_SC598_CLK_CGU1_S0SEL] = clk_register_mux(NULL, "cgu1_sclk0sel", + cgu1_s0sels, 2, + CLK_SET_RATE_PARENT, + cgu1 + CGU_CTL, 16, 1, 0); + clks[ADSP_SC598_CLK_CGU1_S1SEL] = clk_register_mux(NULL, "cgu1_sclk1sel", + cgu1_s1sels, 2, + CLK_SET_RATE_PARENT, + cgu1 + CGU_CTL, 17, 1, 0); + clks[ADSP_SC598_CLK_CGU1_CCLK2] = clk_register_fixed_factor(NULL, "cclk2_1", + "cgu1_vco", + CLK_SET_RATE_PARENT, + 1, 3); + + clks[ADSP_SC598_CLK_3PLL_DDIV] = clk_register_divider(NULL, "3pll_ddiv", + "3pll_pllclk", + CLK_SET_RATE_PARENT, pll3, + 12, 5, 0); + + // Gates to enable CGU outputs + clks[ADSP_SC598_CLK_CGU0_CCLK0] = cgu_gate("cclk0_0", "cgu0_cdiv", + cgu0 + CGU_CCBF_DIS, 0); + clks[ADSP_SC598_CLK_CGU0_OCLK] = cgu_gate("oclk_0", "cgu0_odiv", + cgu0 + CGU_SCBF_DIS, 3); + clks[ADSP_SC598_CLK_CGU0_DCLK] = cgu_gate("dclk_0", "cgu0_ddiv", + cgu0 + CGU_SCBF_DIS, 2); + clks[ADSP_SC598_CLK_CGU0_SCLK1] = cgu_gate("sclk1_0", "cgu0_sclk1sel", + cgu0 + CGU_SCBF_DIS, 1); + clks[ADSP_SC598_CLK_CGU0_SCLK0] = cgu_gate("sclk0_0", "cgu0_s0seldiv", + cgu0 + CGU_SCBF_DIS, 0); + + clks[ADSP_SC598_CLK_CGU1_CCLK0] = cgu_gate("cclk0_1", "cgu1_cdiv", + cgu1 + CGU_CCBF_DIS, 0); + clks[ADSP_SC598_CLK_CGU1_OCLK] = cgu_gate("oclk_1", "cgu1_odiv", + cgu1 + CGU_SCBF_DIS, 3); + clks[ADSP_SC598_CLK_CGU1_DCLK] = cgu_gate("dclk_1", "cgu1_ddiv", + cgu1 + CGU_SCBF_DIS, 2); + clks[ADSP_SC598_CLK_CGU1_SCLK1] = cgu_gate("sclk1_1", "cgu1_sclk1sel", + cgu1 + CGU_SCBF_DIS, 1); + clks[ADSP_SC598_CLK_CGU1_SCLK0] = cgu_gate("sclk0_1", "cgu1_sclk0sel", + cgu1 + CGU_SCBF_DIS, 0); + + // Extra half rate clocks generated in the CDU + clks[ADSP_SC598_CLK_DCLK0_HALF] = clk_register_fixed_factor(NULL, "dclk_0_half", + "dclk_0", + CLK_SET_RATE_PARENT, + 1, 2); + clks[ADSP_SC598_CLK_DCLK1_HALF] = clk_register_fixed_factor(NULL, "dclk_1_half", + "dclk_1", + CLK_SET_RATE_PARENT, + 1, 2); + clks[ADSP_SC598_CLK_CGU1_SCLK1_HALF] = clk_register_fixed_factor(NULL, + "sclk1_1_half", + "sclk1_1", + CLK_SET_RATE_PARENT, + 1, 2); + + // CDU output muxes + clks[ADSP_SC598_CLK_SHARC0_SEL] = cdu_mux("sharc0_sel", cdu + CDU_CFG0, + sharc0_sels); + clks[ADSP_SC598_CLK_SHARC1_SEL] = cdu_mux("sharc1_sel", cdu + CDU_CFG1, + sharc1_sels); + clks[ADSP_SC598_CLK_ARM_SEL] = cdu_mux("arm_sel", cdu + CDU_CFG2, arm_sels); + clks[ADSP_SC598_CLK_CDU_DDR_SEL] = cdu_mux("cdu_ddr_sel", cdu + CDU_CFG3, + cdu_ddr_sels); + clks[ADSP_SC598_CLK_CAN_SEL] = cdu_mux("can_sel", cdu + CDU_CFG4, can_sels); + clks[ADSP_SC598_CLK_SPDIF_SEL] = cdu_mux("spdif_sel", cdu + CDU_CFG5, spdif_sels); + clks[ADSP_SC598_CLK_SPI_SEL] = cdu_mux("spi_sel", cdu + CDU_CFG6, spi_sels); + clks[ADSP_SC598_CLK_GIGE_SEL] = cdu_mux("gige_sel", cdu + CDU_CFG7, gige_sels); + clks[ADSP_SC598_CLK_LP_SEL] = cdu_mux("lp_sel", cdu + CDU_CFG8, lp_sels); + clks[ADSP_SC598_CLK_LP_DDR_SEL] = cdu_mux("lp_ddr_sel", cdu + CDU_CFG9, + lp_ddr_sels); + clks[ADSP_SC598_CLK_OSPI_REFCLK_SEL] = cdu_mux("ospi_refclk_sel", cdu + CDU_CFG10, + ospi_refclk_sels); + clks[ADSP_SC598_CLK_TRACE_SEL] = cdu_mux("trace_sel", cdu + CDU_CFG12, + trace_sels); + clks[ADSP_SC598_CLK_EMMC_SEL] = cdu_mux("emmc_sel", cdu + CDU_CFG13, emmc_sels); + clks[ADSP_SC598_CLK_EMMC_TIMER_QMC_SEL] = cdu_mux("emmc_timer_qmc_sel", + cdu + CDU_CFG14, + emmc_timer_sels); + + // CDU output enable gates + clks[ADSP_SC598_CLK_SHARC0] = cdu_gate("sharc0", "sharc0_sel", cdu + CDU_CFG0, + CLK_IS_CRITICAL); + clks[ADSP_SC598_CLK_SHARC1] = cdu_gate("sharc1", "sharc1_sel", cdu + CDU_CFG1, + CLK_IS_CRITICAL); + clks[ADSP_SC598_CLK_ARM] = cdu_gate("arm", "arm_sel", cdu + CDU_CFG2, + CLK_IS_CRITICAL); + clks[ADSP_SC598_CLK_CDU_DDR] = cdu_gate("cdu_ddr", "cdu_ddr_sel", cdu + CDU_CFG3, + 0); + clks[ADSP_SC598_CLK_CAN] = cdu_gate("can", "can_sel", cdu + CDU_CFG4, 0); + clks[ADSP_SC598_CLK_SPDIF] = cdu_gate("spdif", "spdif_sel", cdu + CDU_CFG5, 0); + clks[ADSP_SC598_CLK_SPI] = cdu_gate("spi", "spi_sel", cdu + CDU_CFG6, 0); + clks[ADSP_SC598_CLK_GIGE] = cdu_gate("gige", "gige_sel", cdu + CDU_CFG7, 0); + clks[ADSP_SC598_CLK_LP] = cdu_gate("lp", "lp_sel", cdu + CDU_CFG8, 0); + clks[ADSP_SC598_CLK_LP_DDR] = cdu_gate("lp_ddr", "lp_ddr_sel", cdu + CDU_CFG9, 0); + clks[ADSP_SC598_CLK_OSPI_REFCLK] = cdu_gate("ospi_refclk", "ospi_refclk_sel", + cdu + CDU_CFG10, 0); + clks[ADSP_SC598_CLK_TRACE] = cdu_gate("trace", "trace_sel", cdu + CDU_CFG12, 0); + clks[ADSP_SC598_CLK_EMMC] = cdu_gate("emmc", "emmc_sel", cdu + CDU_CFG13, 0); + clks[ADSP_SC598_CLK_EMMC_TIMER_QMC] = cdu_gate("emmc_timer_qmc", + "emmc_timer_qmc_sel", + cdu + CDU_CFG14, 0); + + // Dedicated DDR output mux + clks[ADSP_SC598_CLK_DDR] = clk_register_mux(NULL, "ddr", ddr_sels, 2, + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + pll3, 11, 1, 0); + + ret = cdu_check_clocks(clks, ARRAY_SIZE(clks)); + if (ret) + pr_err("CDU error detected\n"); + + return ret; +} + +static const struct udevice_id adi_sc598_clk_ids[] = { + { .compatible = "adi,sc598-clocks" }, + { }, +}; + +U_BOOT_DRIVER(adi_sc598_clk) = { + .name = "clk_adi_sc598", + .id = UCLASS_CLK, + .of_match = adi_sc598_clk_ids, + .ops = &adi_clk_ops, + .probe = sc598_clock_probe, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/adi/clk-shared.c b/drivers/clk/adi/clk-shared.c new file mode 100644 index 00000000000..dcadcafa9d2 --- /dev/null +++ b/drivers/clk/adi/clk-shared.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Author: Greg Malysa + */ + +#include "clk.h" + +static ulong adi_get_rate(struct clk *clk) +{ + struct clk *c; + int ret; + + ret = clk_get_by_id(clk->id, &c); + if (ret) + return ret; + + return clk_get_rate(c); +} + +static ulong adi_set_rate(struct clk *clk, ulong rate) +{ + //Not yet implemented + return 0; +} + +static int adi_enable(struct clk *clk) +{ + //Not yet implemented + return 0; +} + +static int adi_disable(struct clk *clk) +{ + //Not yet implemented + return 0; +} + +const struct clk_ops adi_clk_ops = { + .set_rate = adi_set_rate, + .get_rate = adi_get_rate, + .enable = adi_enable, + .disable = adi_disable, +}; + diff --git a/drivers/clk/adi/clk.h b/drivers/clk/adi/clk.h new file mode 100644 index 00000000000..f230205c311 --- /dev/null +++ b/drivers/clk/adi/clk.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Author: Greg Malysa + * + * Ported from Linux: Nathan Barrett-Morrison + */ + +#ifndef CLK_ADI_CLK_H +#define CLK_ADI_CLK_H + +#include +#include +#include + +#define CGU_CTL 0x00 +#define CGU_PLLCTL 0x04 +#define CGU_STAT 0x08 +#define CGU_DIV 0x0C +#define CGU_CLKOUTSEL 0x10 +#define CGU_OSCWDCTL 0x14 +#define CGU_TSCTL 0x18 +#define CGU_TSVALUE0 0x1C +#define CGU_TSVALUE1 0x20 +#define CGU_TSCOUNT0 0x24 +#define CGU_TSCOUNT1 0x28 +#define CGU_CCBF_DIS 0x2C +#define CGU_CCBF_STAT 0x30 +#define CGU_SCBF_DIS 0x38 +#define CGU_SCBF_STAT 0x3C +#define CGU_DIVEX 0x40 +#define CGU_REVID 0x48 + +#define CDU_CFG0 0x00 +#define CDU_CFG1 0x04 +#define CDU_CFG2 0x08 +#define CDU_CFG3 0x0C +#define CDU_CFG4 0x10 +#define CDU_CFG5 0x14 +#define CDU_CFG6 0x18 +#define CDU_CFG7 0x1C +#define CDU_CFG8 0x20 +#define CDU_CFG9 0x24 +#define CDU_CFG10 0x28 +#define CDU_CFG11 0x2C +#define CDU_CFG12 0x30 +#define CDU_CFG13 0x34 +#define CDU_CFG14 0x38 + +#define PLL3_OFFSET 0x2c + +#define CDU_CLKINSEL 0x44 + +#define CGU_MSEL_SHIFT 8 +#define CGU_MSEL_WIDTH 7 + +#define PLL3_MSEL_SHIFT 4 +#define PLL3_MSEL_WIDTH 7 + +#define CDU_MUX_SIZE 4 +#define CDU_MUX_SHIFT 1 +#define CDU_MUX_WIDTH 2 +#define CDU_EN_BIT 0 + +extern const struct clk_ops adi_clk_ops; + +struct clk *sc5xx_cgu_pll(const char *name, const char *parent_name, + void __iomem *base, u8 shift, u8 width, u32 m_offset, bool half_m); + +/** + * All CDU clock muxes are the same size + */ +static inline struct clk *cdu_mux(const char *name, void __iomem *reg, + const char * const *parents) +{ + return clk_register_mux(NULL, name, parents, CDU_MUX_SIZE, + CLK_SET_RATE_PARENT, reg, CDU_MUX_SHIFT, CDU_MUX_WIDTH, 0); +} + +static inline struct clk *cgu_divider(const char *name, const char *parent, + void __iomem *reg, u8 shift, u8 width, u8 extra_flags) +{ + return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, + reg, shift, width, CLK_DIVIDER_MAX_AT_ZERO | extra_flags); +} + +static inline struct clk *cdu_gate(const char *name, const char *parent, + void __iomem *reg, u32 flags) +{ + return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT | flags, + reg, CDU_EN_BIT, 0, NULL); +} + +static inline struct clk *cgu_gate(const char *name, const char *parent, + void __iomem *reg, u8 bit) +{ + return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, bit, + CLK_GATE_SET_TO_DISABLE, NULL); +} + +static inline int cdu_check_clocks(struct clk *clks[], size_t count) +{ + size_t i; + + for (i = 0; i < count; ++i) { + if (clks[i]) { + if (IS_ERR(clks[i])) { + pr_err("Clock %zu failed to register: %ld\n", i, PTR_ERR(clks[i])); + return PTR_ERR(clks[i]); + } + clks[i]->id = i; + } else { + pr_err("ADI Clock framework: Null pointer detected on clock %zu\n", i); + } + } + + return 0; +} + +#endif diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index cca6d674122..bdc7be0fb5d 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -3,7 +3,6 @@ * Copyright (C) 2019 Intel Corporation */ -#include #include #include #include diff --git a/drivers/clk/altera/clk-agilex5.c b/drivers/clk/altera/clk-agilex5.c index 92f2abdaf93..72b923465df 100644 --- a/drivers/clk/altera/clk-agilex5.c +++ b/drivers/clk/altera/clk-agilex5.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/clk/altera/clk-arria10.c b/drivers/clk/altera/clk-arria10.c index 578597a16e8..1840f73beee 100644 --- a/drivers/clk/altera/clk-arria10.c +++ b/drivers/clk/altera/clk-arria10.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Marek Vasut */ -#include #include #include #include diff --git a/drivers/clk/altera/clk-mem-n5x.c b/drivers/clk/altera/clk-mem-n5x.c index 9bbe2cd0ca7..b75f52d203b 100644 --- a/drivers/clk/altera/clk-mem-n5x.c +++ b/drivers/clk/altera/clk-mem-n5x.c @@ -3,7 +3,6 @@ * Copyright (C) 2020-2022 Intel Corporation */ -#include #include #include #include diff --git a/drivers/clk/altera/clk-n5x.c b/drivers/clk/altera/clk-n5x.c index 3fa19e05c47..3e256101a94 100644 --- a/drivers/clk/altera/clk-n5x.c +++ b/drivers/clk/altera/clk-n5x.c @@ -3,7 +3,6 @@ * Copyright (C) 2020-2022 Intel Corporation */ -#include #include #include #include diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c index dc446ce9fb7..a330dcda4dc 100644 --- a/drivers/clk/aspeed/clk_ast2500.c +++ b/drivers/clk/aspeed/clk_ast2500.c @@ -3,7 +3,6 @@ * (C) Copyright 2016 Google, Inc */ -#include #include #include #include diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c index a15909329bb..535010b7941 100644 --- a/drivers/clk/aspeed/clk_ast2600.c +++ b/drivers/clk/aspeed/clk_ast2600.c @@ -3,7 +3,6 @@ * Copyright (C) ASPEED Technology Inc. */ -#include #include #include #include diff --git a/drivers/clk/at91/clk-generic.c b/drivers/clk/at91/clk-generic.c index 87738b7b5bf..c410cd2b505 100644 --- a/drivers/clk/at91/clk-generic.c +++ b/drivers/clk/at91/clk-generic.c @@ -8,7 +8,6 @@ * * Based on drivers/clk/at91/clk-generated.c from Linux. */ -#include #include #include #include diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c index 025c7a7aa26..09daae97676 100644 --- a/drivers/clk/at91/clk-main.c +++ b/drivers/clk/at91/clk-main.c @@ -10,7 +10,6 @@ */ #include -#include #include #include #include diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index aec0bca7b3c..d28775d64d3 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -11,7 +11,6 @@ #include #include -#include #include #include #include diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c index 52cbc520cef..08d7e7dddc9 100644 --- a/drivers/clk/at91/clk-peripheral.c +++ b/drivers/clk/at91/clk-peripheral.c @@ -8,7 +8,6 @@ * * Based on drivers/clk/at91/clk-peripheral.c from Linux. */ -#include #include #include #include diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c index 868de4b1774..d0b14656c4d 100644 --- a/drivers/clk/at91/clk-programmable.c +++ b/drivers/clk/at91/clk-programmable.c @@ -8,7 +8,6 @@ * * Based on drivers/clk/at91/clk-programmable.c from Linux. */ -#include #include #include #include diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c index 383f79cfbaf..a30035eb8ce 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -11,7 +11,6 @@ */ #include -#include #include #include #include diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c index 82f79e74a19..3545b0b24bd 100644 --- a/drivers/clk/at91/clk-system.c +++ b/drivers/clk/at91/clk-system.c @@ -9,7 +9,6 @@ * Based on drivers/clk/at91/clk-system.c from Linux. */ #include -#include #include #include #include diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c index 7c8bcfb51db..84784ae41ce 100644 --- a/drivers/clk/at91/clk-utmi.c +++ b/drivers/clk/at91/clk-utmi.c @@ -9,7 +9,6 @@ * Based on drivers/clk/at91/clk-utmi.c from Linux. */ #include -#include #include #include #include diff --git a/drivers/clk/at91/compat.c b/drivers/clk/at91/compat.c index ee67093c607..1d738f160b6 100644 --- a/drivers/clk/at91/compat.c +++ b/drivers/clk/at91/compat.c @@ -6,7 +6,7 @@ * * Author: Claudiu Beznea */ -#include +#include #include #include #include diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c index 87d2069d89c..aa4bc8fa47a 100644 --- a/drivers/clk/at91/pmc.c +++ b/drivers/clk/at91/pmc.c @@ -4,7 +4,6 @@ * Wenyou.Yang */ -#include #include #include #include diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index d858c860f69..b7d64bdbb3d 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -7,7 +7,6 @@ * Based on sam9x60.c on Linux. */ -#include #include #include #include diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 3e62fb1f58d..63b2c647467 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -9,7 +9,6 @@ * Based on drivers/clk/at91/sama7g5.c from Linux. */ -#include #include #include #include diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c index 43136ab2e34..6d6f12578db 100644 --- a/drivers/clk/at91/sckc.c +++ b/drivers/clk/at91/sckc.c @@ -7,7 +7,6 @@ * Author: Claudiu Beznea */ -#include #include #include #include diff --git a/drivers/clk/clk-cdce9xx.c b/drivers/clk/clk-cdce9xx.c index b8700f517fc..e5f74e714d5 100644 --- a/drivers/clk/clk-cdce9xx.c +++ b/drivers/clk/clk-cdce9xx.c @@ -8,7 +8,6 @@ * Based on Linux kernel clk-cdce925.c. */ -#include #include #include #include diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index d2e5a1ae401..199ca6eaa37 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_CLK -#include #include #include #include diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 2ad682b8fe2..aa210e3d15f 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -11,7 +11,6 @@ #define LOG_CATEGORY UCLASS_CLK -#include #include #include #include diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index 2a446788e19..068798cf9b0 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_CLK -#include #include #include #include diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index cfd90b717e7..bf1c6a93b46 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -9,7 +9,6 @@ #define LOG_CATEGORY UCLASS_CLK -#include #include #include #include diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c index 85074f1b86e..53655059279 100644 --- a/drivers/clk/clk-hsdk-cgu.c +++ b/drivers/clk/clk-hsdk-cgu.c @@ -9,7 +9,6 @@ * warranty of any kind, whether express or implied. */ -#include #include #include #include diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index f410518461e..39e01c3fbc6 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -23,7 +23,6 @@ #define LOG_CATEGORY UCLASS_CLK -#include #include #include #include diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index ed6e60bc484..4c832f1a530 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_CLK -#include #include #include #include diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c index a10a843f11f..4a3f50c638b 100644 --- a/drivers/clk/clk-xlnx-clock-wizard.c +++ b/drivers/clk/clk-xlnx-clock-wizard.c @@ -7,7 +7,6 @@ * Author: Zhengxun Li */ -#include #include #include #include diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 6ede1b4d4dc..b8c2e8d531b 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_CLK -#include #include #include #include diff --git a/drivers/clk/clk_bcm6345.c b/drivers/clk/clk_bcm6345.c index 8c22ed2f43d..0b41872b719 100644 --- a/drivers/clk/clk_bcm6345.c +++ b/drivers/clk/clk_bcm6345.c @@ -6,7 +6,6 @@ * Copyright (C) 2008 Maxime Bizon */ -#include #include #include #include diff --git a/drivers/clk/clk_boston.c b/drivers/clk/clk_boston.c index 4bcf9117551..030ff7cc58e 100644 --- a/drivers/clk/clk_boston.c +++ b/drivers/clk/clk_boston.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Imagination Technologies */ -#include #include #include #include diff --git a/drivers/clk/clk_fixed_factor.c b/drivers/clk/clk_fixed_factor.c index 6c1139e5c51..1d740cf49f6 100644 --- a/drivers/clk/clk_fixed_factor.c +++ b/drivers/clk/clk_fixed_factor.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY UCLASS_CLK -#include #include #include #include diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c index b5e78c70559..d1da05cc18a 100644 --- a/drivers/clk/clk_fixed_rate.c +++ b/drivers/clk/clk_fixed_rate.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_CLK -#include #include #include #include diff --git a/drivers/clk/clk_k210.c b/drivers/clk/clk_k210.c index 7432ae8f064..d1a6cde8f0f 100644 --- a/drivers/clk/clk_k210.c +++ b/drivers/clk/clk_k210.c @@ -4,7 +4,6 @@ */ #define LOG_CATEGORY UCLASS_CLK -#include #include #include #include diff --git a/drivers/clk/clk_pic32.c b/drivers/clk/clk_pic32.c index a77d0e7419c..885aa834516 100644 --- a/drivers/clk/clk_pic32.c +++ b/drivers/clk/clk_pic32.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/drivers/clk/clk_sandbox.c b/drivers/clk/clk_sandbox.c index 73d943f9e09..8dd77f18d90 100644 --- a/drivers/clk/clk_sandbox.c +++ b/drivers/clk/clk_sandbox.c @@ -3,7 +3,6 @@ * (C) Copyright 2015 Google, Inc */ -#include #include #include #include diff --git a/drivers/clk/clk_sandbox_ccf.c b/drivers/clk/clk_sandbox_ccf.c index 38184e27aa4..f96a15c30b3 100644 --- a/drivers/clk/clk_sandbox_ccf.c +++ b/drivers/clk/clk_sandbox_ccf.c @@ -6,7 +6,6 @@ * Common Clock Framework [CCF] driver for Sandbox */ -#include #include #include #include diff --git a/drivers/clk/clk_sandbox_test.c b/drivers/clk/clk_sandbox_test.c index c224dc1d2cb..87350212775 100644 --- a/drivers/clk/clk_sandbox_test.c +++ b/drivers/clk/clk_sandbox_test.c @@ -3,7 +3,6 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ -#include #include #include #include diff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c index 34a49363a51..e42d2032d45 100644 --- a/drivers/clk/clk_scmi.c +++ b/drivers/clk/clk_scmi.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_CLK -#include #include #include #include diff --git a/drivers/clk/clk_versaclock.c b/drivers/clk/clk_versaclock.c index bbe72256032..9ccaf13d242 100644 --- a/drivers/clk/clk_versaclock.c +++ b/drivers/clk/clk_versaclock.c @@ -5,7 +5,6 @@ * Derived from code Copyright (C) 2017 Marek Vasut */ -#include #include #include #include diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index 42ab032bf7e..35ee56d0693 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -4,7 +4,6 @@ * Siva Durga Prasad Paladugu > */ -#include #include #include #include diff --git a/drivers/clk/clk_vexpress_osc.c b/drivers/clk/clk_vexpress_osc.c index 3b1e0208d47..2e0e7bbe68f 100644 --- a/drivers/clk/clk_vexpress_osc.c +++ b/drivers/clk/clk_vexpress_osc.c @@ -5,7 +5,6 @@ * */ #define DEBUG -#include #include #include #include diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c index e3cefe2e0c7..b62b4646f4e 100644 --- a/drivers/clk/clk_zynq.c +++ b/drivers/clk/clk_zynq.c @@ -7,7 +7,6 @@ * Copyright (C) 2013 Xilinx, Inc. All rights reserved. */ -#include #include #include #include diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index e23f7da3f92..59999266148 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -5,7 +5,6 @@ * Copyright (C) 2016 Xilinx, Inc. */ -#include #include #include #include diff --git a/drivers/clk/exynos/clk-exynos7420.c b/drivers/clk/exynos/clk-exynos7420.c index 9caa932e12f..3aa751bf4e4 100644 --- a/drivers/clk/exynos/clk-exynos7420.c +++ b/drivers/clk/exynos/clk-exynos7420.c @@ -5,7 +5,6 @@ * Thomas Abraham */ -#include #include #include #include diff --git a/drivers/clk/ics8n3qv01.c b/drivers/clk/ics8n3qv01.c index 33fb6ed0c7a..9c61a84ea61 100644 --- a/drivers/clk/ics8n3qv01.c +++ b/drivers/clk/ics8n3qv01.c @@ -9,7 +9,6 @@ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de */ -#include #include #include #include diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index 494156751da..45f1bcaea28 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -3,7 +3,6 @@ * Copyright 2019 NXP */ -#include #include #include #include diff --git a/drivers/clk/imx/clk-composite-93.c b/drivers/clk/imx/clk-composite-93.c index 6d71c0c03ff..2cf20be2cca 100644 --- a/drivers/clk/imx/clk-composite-93.c +++ b/drivers/clk/imx/clk-composite-93.c @@ -4,7 +4,6 @@ * * Peng Fan */ -#include #include #include #include diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c index 9228f279e27..8f42a5cb1b7 100644 --- a/drivers/clk/imx/clk-fracn-gppll.c +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -3,7 +3,6 @@ * Copyright 2021 NXP */ -#include #include #include #include diff --git a/drivers/clk/imx/clk-gate-93.c b/drivers/clk/imx/clk-gate-93.c index bc857413713..d7f2640fbb7 100644 --- a/drivers/clk/imx/clk-gate-93.c +++ b/drivers/clk/imx/clk-gate-93.c @@ -5,7 +5,6 @@ * Peng Fan */ -#include #include #include #include diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c index da272302377..65fa6b5b139 100644 --- a/drivers/clk/imx/clk-gate2.c +++ b/drivers/clk/imx/clk-gate2.c @@ -14,7 +14,6 @@ * */ -#include #include #include #include diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index 67825af89b8..ba9923d8f6f 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -4,7 +4,6 @@ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de */ -#include #include #include #include diff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c index d39b87b2e24..96cf5fece75 100644 --- a/drivers/clk/imx/clk-imx8.c +++ b/drivers/clk/imx/clk-imx8.c @@ -4,7 +4,6 @@ * Peng Fan */ -#include #include #include #include diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 1a00dd1d287..70e2e53bdea 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -4,7 +4,6 @@ * Peng Fan */ -#include #include #include #include diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 457acb8a401..ed9e16d7c18 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -4,7 +4,6 @@ * Peng Fan */ -#include #include #include #include diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 7dfc829df2c..1f498b6ba4e 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -4,7 +4,6 @@ * Peng Fan */ -#include #include #include #include diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index cf197df96db..ed4acd79ef7 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -5,7 +5,6 @@ * Peng Fan */ -#include #include #include #include diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c index 01e33de9d63..62fed7e3e32 100644 --- a/drivers/clk/imx/clk-imx8qm.c +++ b/drivers/clk/imx/clk-imx8qm.c @@ -4,7 +4,6 @@ * Peng Fan */ -#include #include #include #include diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index d900d4cd528..18bdc08971b 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -4,7 +4,6 @@ * Peng Fan */ -#include #include #include #include diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c index f0cb797d975..ede36c412bf 100644 --- a/drivers/clk/imx/clk-imx93.c +++ b/drivers/clk/imx/clk-imx93.c @@ -3,7 +3,6 @@ * Copyright 2021 NXP. */ -#include #include #include #include diff --git a/drivers/clk/imx/clk-imxrt1020.c b/drivers/clk/imx/clk-imxrt1020.c index dc91ac5adbf..c80b02975aa 100644 --- a/drivers/clk/imx/clk-imxrt1020.c +++ b/drivers/clk/imx/clk-imxrt1020.c @@ -4,7 +4,6 @@ * Author(s): Giulio Benetti */ -#include #include #include #include diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c index d40635d17a4..754f3948427 100644 --- a/drivers/clk/imx/clk-imxrt1050.c +++ b/drivers/clk/imx/clk-imxrt1050.c @@ -4,7 +4,6 @@ * Author(s): Giulio Benetti */ -#include #include #include #include diff --git a/drivers/clk/imx/clk-imxrt1170.c b/drivers/clk/imx/clk-imxrt1170.c index 077dd1bf02d..20b9dc31500 100644 --- a/drivers/clk/imx/clk-imxrt1170.c +++ b/drivers/clk/imx/clk-imxrt1170.c @@ -4,7 +4,6 @@ * Author(s): Jesse Taube */ -#include #include #include #include diff --git a/drivers/clk/imx/clk-pfd.c b/drivers/clk/imx/clk-pfd.c index b8be3167c4c..378cdff072f 100644 --- a/drivers/clk/imx/clk-pfd.c +++ b/drivers/clk/imx/clk-pfd.c @@ -14,7 +14,6 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include #include #include #include diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 1cb685ee9ab..3911e033905 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -5,7 +5,6 @@ * Peng Fan */ -#include #include #include #include diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index fad306aeed2..c6692f2f9f5 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -4,7 +4,6 @@ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de */ -#include #include #include #include diff --git a/drivers/clk/intel/clk_intel.c b/drivers/clk/intel/clk_intel.c index 46ccbb1d834..a677a7caac7 100644 --- a/drivers/clk/intel/clk_intel.c +++ b/drivers/clk/intel/clk_intel.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 259ea335959..2beb63030f2 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -6,7 +6,6 @@ * Author: Ryder Lee */ -#include #include #include #include diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c index 0c7411ee814..5072c9983c1 100644 --- a/drivers/clk/mediatek/clk-mt7623.c +++ b/drivers/clk/mediatek/clk-mt7623.c @@ -6,7 +6,6 @@ * Author: Ryder Lee */ -#include #include #include #include diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index 31b6fa02251..0c796a1788a 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -6,7 +6,6 @@ * Author: Ryder Lee */ -#include #include #include #include diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 17e653a1f00..9612a62e56a 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -8,7 +8,6 @@ * Author: Weiyi Lu */ -#include #include #include #include diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c index 193e069cb05..ab270673442 100644 --- a/drivers/clk/mediatek/clk-mt8512.c +++ b/drivers/clk/mediatek/clk-mt8512.c @@ -6,7 +6,6 @@ * Author: Chen Zhong */ -#include #include #include #include diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c index 29f70620e09..623f88499f1 100644 --- a/drivers/clk/mediatek/clk-mt8516.c +++ b/drivers/clk/mediatek/clk-mt8516.c @@ -6,7 +6,6 @@ * Author: Fabien Parent */ -#include #include #include #include diff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c index 23865148372..ba8cc584d46 100644 --- a/drivers/clk/mediatek/clk-mt8518.c +++ b/drivers/clk/mediatek/clk-mt8518.c @@ -6,7 +6,6 @@ * Author: Chen Zhong */ -#include #include #include #include diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 4303300d3a8..d2c45be30de 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -6,7 +6,6 @@ * Author: Ryder Lee */ -#include #include #include #include diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c index 5220a337a8b..a1b8d791491 100644 --- a/drivers/clk/meson/a1.c +++ b/drivers/clk/meson/a1.c @@ -4,7 +4,6 @@ * Author: Igor Prusov */ -#include #include #include #include diff --git a/drivers/clk/meson/axg-ao.c b/drivers/clk/meson/axg-ao.c index 311ffc1cca9..6ccf52127b0 100644 --- a/drivers/clk/meson/axg-ao.c +++ b/drivers/clk/meson/axg-ao.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index d6da59d269b..c421a622a58 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -5,7 +5,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/drivers/clk/meson/g12a-ao.c b/drivers/clk/meson/g12a-ao.c index 1a855a68966..61d489c6e1c 100644 --- a/drivers/clk/meson/g12a-ao.c +++ b/drivers/clk/meson/g12a-ao.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index e4fed8ddfb2..5d7faaa3eab 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -5,7 +5,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index e379540deee..72ad4fd0e85 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -5,7 +5,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/drivers/clk/microchip/mpfs_clk.c b/drivers/clk/microchip/mpfs_clk.c index 08f8bfcecbe..0a82777ff74 100644 --- a/drivers/clk/microchip/mpfs_clk.c +++ b/drivers/clk/microchip/mpfs_clk.c @@ -3,7 +3,6 @@ * Copyright (C) 2020 Microchip Technology Inc. * Padmarao Begari */ -#include #include #include #include diff --git a/drivers/clk/microchip/mpfs_clk_cfg.c b/drivers/clk/microchip/mpfs_clk_cfg.c index 5739fd66e8d..5e8fb995289 100644 --- a/drivers/clk/microchip/mpfs_clk_cfg.c +++ b/drivers/clk/microchip/mpfs_clk_cfg.c @@ -3,7 +3,6 @@ * Copyright (C) 2020 Microchip Technology Inc. * Padmarao Begari */ -#include #include #include #include diff --git a/drivers/clk/microchip/mpfs_clk_msspll.c b/drivers/clk/microchip/mpfs_clk_msspll.c index f37c0d86047..d0e7b1ff844 100644 --- a/drivers/clk/microchip/mpfs_clk_msspll.c +++ b/drivers/clk/microchip/mpfs_clk_msspll.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2022 Microchip Technology Inc. */ -#include #include #include #include diff --git a/drivers/clk/microchip/mpfs_clk_periph.c b/drivers/clk/microchip/mpfs_clk_periph.c index ddeccb91457..41c6df4fb97 100644 --- a/drivers/clk/microchip/mpfs_clk_periph.c +++ b/drivers/clk/microchip/mpfs_clk_periph.c @@ -3,7 +3,6 @@ * Copyright (C) 2020 Microchip Technology Inc. * Padmarao Begari */ -#include #include #include #include diff --git a/drivers/clk/mpc83xx_clk.c b/drivers/clk/mpc83xx_clk.c index cc734450ef0..a29ad0d7a68 100644 --- a/drivers/clk/mpc83xx_clk.c +++ b/drivers/clk/mpc83xx_clk.c @@ -4,7 +4,6 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ -#include #include #include #include diff --git a/drivers/clk/mtmips/clk-mt7628.c b/drivers/clk/mtmips/clk-mt7628.c index 4d3ac847d1d..2e263fb2cd2 100644 --- a/drivers/clk/mtmips/clk-mt7628.c +++ b/drivers/clk/mtmips/clk-mt7628.c @@ -5,7 +5,6 @@ * Author: Weijie Gao */ -#include #include #include #include diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c index f5c9bd735c1..30330393f76 100644 --- a/drivers/clk/mvebu/armada-37xx-periph.c +++ b/drivers/clk/mvebu/armada-37xx-periph.c @@ -8,7 +8,6 @@ * Gregory CLEMENT */ -#include #include #include #include diff --git a/drivers/clk/mvebu/armada-37xx-tbg.c b/drivers/clk/mvebu/armada-37xx-tbg.c index 846a73cd6b3..c1bab84c070 100644 --- a/drivers/clk/mvebu/armada-37xx-tbg.c +++ b/drivers/clk/mvebu/armada-37xx-tbg.c @@ -8,7 +8,6 @@ * Gregory CLEMENT */ -#include #include #include #include diff --git a/drivers/clk/owl/clk_owl.c b/drivers/clk/owl/clk_owl.c index 678fdd5a454..513112c1146 100644 --- a/drivers/clk/owl/clk_owl.c +++ b/drivers/clk/owl/clk_owl.c @@ -6,7 +6,6 @@ * Copyright (C) 2018 Manivannan Sadhasivam */ -#include #include #include "clk_owl.h" #include diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index d3b63b9c1ac..41fe4d896a7 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -7,7 +7,6 @@ * Based on Little Kernel driver, simplified */ -#include #include #include #include diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c index 479f9771a46..c77d69128b0 100644 --- a/drivers/clk/qcom/clock-apq8096.c +++ b/drivers/clk/qcom/clock-apq8096.c @@ -7,7 +7,6 @@ * Based on Little Kernel driver, simplified */ -#include #include #include #include diff --git a/drivers/clk/qcom/clock-ipq4019.c b/drivers/clk/qcom/clock-ipq4019.c index 72f235eab21..0e6d93b3d7c 100644 --- a/drivers/clk/qcom/clock-ipq4019.c +++ b/drivers/clk/qcom/clock-ipq4019.c @@ -9,7 +9,6 @@ */ #include -#include #include #include #include diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 05e5ab7d094..3a9cf2a231f 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -12,7 +12,6 @@ * Based on Little Kernel driver, simplified */ -#include #include #include #include diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c index 8a897a52bc0..70a1f648e58 100644 --- a/drivers/clk/qcom/clock-qcs404.c +++ b/drivers/clk/qcom/clock-qcs404.c @@ -5,7 +5,6 @@ * (C) Copyright 2022 Sumit Garg */ -#include #include #include #include diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index 782df7da844..f41f8c9e8de 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -8,7 +8,6 @@ * Based on Little Kernel driver, simplified */ -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c index 66f8bb16695..44c6f14618d 100644 --- a/drivers/clk/rockchip/clk_pll.c +++ b/drivers/clk/rockchip/clk_pll.c @@ -2,7 +2,6 @@ /* * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd */ - #include #include #include #include diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c index 2875c152b20..d7825c66493 100644 --- a/drivers/clk/rockchip/clk_px30.c +++ b/drivers/clk/rockchip/clk_px30.c @@ -3,7 +3,6 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c index 6238b14c29e..274428f2b4b 100644 --- a/drivers/clk/rockchip/clk_rk3036.c +++ b/drivers/clk/rockchip/clk_rk3036.c @@ -3,7 +3,6 @@ * (C) Copyright 2015 Google, Inc */ -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3066.c b/drivers/clk/rockchip/clk_rk3066.c index f83335df6db..f7dea7859f7 100644 --- a/drivers/clk/rockchip/clk_rk3066.c +++ b/drivers/clk/rockchip/clk_rk3066.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3128.c b/drivers/clk/rockchip/clk_rk3128.c index 182754e7052..a07285593b5 100644 --- a/drivers/clk/rockchip/clk_rk3128.c +++ b/drivers/clk/rockchip/clk_rk3128.c @@ -3,7 +3,6 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c index f98b46a0f73..f569a100f22 100644 --- a/drivers/clk/rockchip/clk_rk3188.c +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -4,7 +4,6 @@ * (C) Copyright 2016 Heiko Stuebner */ -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index 9371c4f63a4..9b71fd863ba 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -3,7 +3,6 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 0b7eefad15f..432a79291c8 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -3,7 +3,6 @@ * (C) Copyright 2015 Google, Inc */ -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c index 861648321d4..e73bb6790af 100644 --- a/drivers/clk/rockchip/clk_rk3308.c +++ b/drivers/clk/rockchip/clk_rk3308.c @@ -2,7 +2,6 @@ /* * (C) Copyright 2017-2019 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index 314b903eaa0..a4f6dd5a0f5 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -3,7 +3,6 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c index 1c5dfaa3800..d8943980521 100644 --- a/drivers/clk/rockchip/clk_rk3368.c +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -5,7 +5,6 @@ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH */ -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 67b2c05ec9e..24cefebd1b2 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -4,7 +4,6 @@ * (C) 2017 Theobroma Systems Design und Consulting GmbH */ -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 24eeca8bf26..35563509d61 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -4,7 +4,6 @@ * Author: Elaine Zhang */ -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index 4c611a39049..ceae08a19aa 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -4,7 +4,6 @@ * Author: Elaine Zhang */ -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c index fc442f7eebe..75202a66aa6 100644 --- a/drivers/clk/rockchip/clk_rv1108.c +++ b/drivers/clk/rockchip/clk_rv1108.c @@ -4,7 +4,6 @@ * Author: Andy Yan */ -#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rv1126.c b/drivers/clk/rockchip/clk_rv1126.c index cfdfcbdb0f4..aeeea956914 100644 --- a/drivers/clk/rockchip/clk_rv1126.c +++ b/drivers/clk/rockchip/clk_rv1126.c @@ -5,7 +5,6 @@ * Author: Finley Xiao */ -#include #include #include #include diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index c8fb6002907..5ea86062800 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -22,7 +22,6 @@ * https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60 */ -#include #include #include #include diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c index 1568a1f4cd9..581035842fc 100644 --- a/drivers/clk/starfive/clk-jh7110-pll.c +++ b/drivers/clk/starfive/clk-jh7110-pll.c @@ -6,7 +6,6 @@ * Xingyu Wu */ -#include #include #include #include diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c index a38694809a0..191da75d7ba 100644 --- a/drivers/clk/starfive/clk-jh7110.c +++ b/drivers/clk/starfive/clk-jh7110.c @@ -6,7 +6,6 @@ * Xingyu Wu */ -#include #include #include #include diff --git a/drivers/clk/stm32/clk-stm32-core.c b/drivers/clk/stm32/clk-stm32-core.c index 37e996e78f9..cad07cc952e 100644 --- a/drivers/clk/stm32/clk-stm32-core.c +++ b/drivers/clk/stm32/clk-stm32-core.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_CLK -#include #include #include #include diff --git a/drivers/clk/stm32/clk-stm32f.c b/drivers/clk/stm32/clk-stm32f.c index d68c75ed201..fceb3c44b94 100644 --- a/drivers/clk/stm32/clk-stm32f.c +++ b/drivers/clk/stm32/clk-stm32f.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_CLK -#include #include #include #include diff --git a/drivers/clk/stm32/clk-stm32h7.c b/drivers/clk/stm32/clk-stm32h7.c index d440c28eb48..a554eda504d 100644 --- a/drivers/clk/stm32/clk-stm32h7.c +++ b/drivers/clk/stm32/clk-stm32h7.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_CLK -#include #include #include #include diff --git a/drivers/clk/stm32/clk-stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c index 6f000c8e444..204ac170531 100644 --- a/drivers/clk/stm32/clk-stm32mp1.c +++ b/drivers/clk/stm32/clk-stm32mp1.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_CLK -#include #include #include #include diff --git a/drivers/clk/stm32/clk-stm32mp13.c b/drivers/clk/stm32/clk-stm32mp13.c index 5174ae53a1a..362dba10252 100644 --- a/drivers/clk/stm32/clk-stm32mp13.c +++ b/drivers/clk/stm32/clk-stm32mp13.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY UCLASS_CLK #include -#include #include #include #include diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c index f27306fe33b..19fe248044b 100644 --- a/drivers/clk/sunxi/clk_a10.c +++ b/drivers/clk/sunxi/clk_a10.c @@ -4,7 +4,6 @@ * Author: Jagan Teki */ -#include #include #include #include diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c index 16ac589bb2b..f771369c942 100644 --- a/drivers/clk/sunxi/clk_a10s.c +++ b/drivers/clk/sunxi/clk_a10s.c @@ -4,7 +4,6 @@ * Author: Jagan Teki */ -#include #include #include #include diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c index 45d5ba75bf5..fdee4347e99 100644 --- a/drivers/clk/sunxi/clk_a23.c +++ b/drivers/clk/sunxi/clk_a23.c @@ -4,7 +4,6 @@ * Author: Jagan Teki */ -#include #include #include #include diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c index 6ca800050ed..04f76a7c2a3 100644 --- a/drivers/clk/sunxi/clk_a31.c +++ b/drivers/clk/sunxi/clk_a31.c @@ -4,7 +4,6 @@ * Author: Jagan Teki */ -#include #include #include #include diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index fd26cd4f5d6..f1b01d25ddd 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -4,7 +4,6 @@ * Author: Jagan Teki */ -#include #include #include #include diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c index c5834f44103..6751af8a803 100644 --- a/drivers/clk/sunxi/clk_a80.c +++ b/drivers/clk/sunxi/clk_a80.c @@ -4,7 +4,6 @@ * Author: Jagan Teki */ -#include #include #include #include diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c index 760d98cd620..d8621a3e64c 100644 --- a/drivers/clk/sunxi/clk_a83t.c +++ b/drivers/clk/sunxi/clk_a83t.c @@ -4,7 +4,6 @@ * Author: Jagan Teki */ -#include #include #include #include diff --git a/drivers/clk/sunxi/clk_d1.c b/drivers/clk/sunxi/clk_d1.c index 9dae761de83..b990a118594 100644 --- a/drivers/clk/sunxi/clk_d1.c +++ b/drivers/clk/sunxi/clk_d1.c @@ -3,7 +3,6 @@ * Copyright (C) 2021 Samuel Holland */ -#include #include #include #include diff --git a/drivers/clk/sunxi/clk_f1c100s.c b/drivers/clk/sunxi/clk_f1c100s.c index 7b4c3ce5176..e2295699201 100644 --- a/drivers/clk/sunxi/clk_f1c100s.c +++ b/drivers/clk/sunxi/clk_f1c100s.c @@ -3,7 +3,6 @@ * Copyright (C) 2019 George Hilliard . */ -#include #include #include #include diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index 32bc95fccca..ce55caeb157 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -4,7 +4,6 @@ * Author: Jagan Teki */ -#include #include #include #include diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c index 071fd581003..1b7bd9dea2f 100644 --- a/drivers/clk/sunxi/clk_h6.c +++ b/drivers/clk/sunxi/clk_h6.c @@ -4,7 +4,6 @@ * Author: Jagan Teki */ -#include #include #include #include diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c index 113dcff2851..b1e999e18c1 100644 --- a/drivers/clk/sunxi/clk_h616.c +++ b/drivers/clk/sunxi/clk_h616.c @@ -3,7 +3,6 @@ * Copyright (C) 2021 Jernej Skrabec */ -#include #include #include #include diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c index 0fef6f3566d..721debdae23 100644 --- a/drivers/clk/sunxi/clk_r40.c +++ b/drivers/clk/sunxi/clk_r40.c @@ -4,7 +4,6 @@ * Author: Jagan Teki */ -#include #include #include #include diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c index 1782cffc404..2ef4f45dacf 100644 --- a/drivers/clk/sunxi/clk_sunxi.c +++ b/drivers/clk/sunxi/clk_sunxi.c @@ -4,7 +4,6 @@ * Author: Jagan Teki */ -#include #include #include #include diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index 6524c13540e..85410e282e8 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b/drivers/clk/sunxi/clk_v3s.c @@ -4,7 +4,6 @@ * Author: Jagan Teki */ -#include #include #include #include diff --git a/drivers/clk/tegra/tegra-car-clk.c b/drivers/clk/tegra/tegra-car-clk.c index c5214b9b3e2..1d61f8dc378 100644 --- a/drivers/clk/tegra/tegra-car-clk.c +++ b/drivers/clk/tegra/tegra-car-clk.c @@ -3,7 +3,6 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ -#include #include #include #include diff --git a/drivers/clk/tegra/tegra186-clk.c b/drivers/clk/tegra/tegra186-clk.c index 5a98a3f3f0e..ec52326c3b3 100644 --- a/drivers/clk/tegra/tegra186-clk.c +++ b/drivers/clk/tegra/tegra186-clk.c @@ -3,7 +3,6 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ -#include #include #include #include diff --git a/drivers/clk/ti/clk-am3-dpll-x2.c b/drivers/clk/ti/clk-am3-dpll-x2.c index 3cf279d6a3a..1b0b9818cdd 100644 --- a/drivers/clk/ti/clk-am3-dpll-x2.c +++ b/drivers/clk/ti/clk-am3-dpll-x2.c @@ -7,7 +7,6 @@ * Loosely based on Linux kernel drivers/clk/ti/dpll.c */ -#include #include #include #include diff --git a/drivers/clk/ti/clk-am3-dpll.c b/drivers/clk/ti/clk-am3-dpll.c index 398a011a5ce..21ec01f8dd9 100644 --- a/drivers/clk/ti/clk-am3-dpll.c +++ b/drivers/clk/ti/clk-am3-dpll.c @@ -7,7 +7,6 @@ * Loosely based on Linux kernel drivers/clk/ti/dpll.c */ -#include #include #include #include diff --git a/drivers/clk/ti/clk-ctrl.c b/drivers/clk/ti/clk-ctrl.c index 8926e57ebc8..c5c97dc35c4 100644 --- a/drivers/clk/ti/clk-ctrl.c +++ b/drivers/clk/ti/clk-ctrl.c @@ -5,7 +5,6 @@ * Copyright (C) 2020 Dario Binacchi */ -#include #include #include #include diff --git a/drivers/clk/ti/clk-divider.c b/drivers/clk/ti/clk-divider.c index 15941f17811..40a742d7fdc 100644 --- a/drivers/clk/ti/clk-divider.c +++ b/drivers/clk/ti/clk-divider.c @@ -7,7 +7,6 @@ * Loosely based on Linux kernel drivers/clk/ti/divider.c */ -#include #include #include #include diff --git a/drivers/clk/ti/clk-gate.c b/drivers/clk/ti/clk-gate.c index eb15f6243f2..873ceb8a2ab 100644 --- a/drivers/clk/ti/clk-gate.c +++ b/drivers/clk/ti/clk-gate.c @@ -7,7 +7,6 @@ * Loosely based on Linux kernel drivers/clk/ti/gate.c */ -#include #include #include #include diff --git a/drivers/clk/ti/clk-k3-pll.c b/drivers/clk/ti/clk-k3-pll.c index 8323e6e6919..b3a1b4cedb7 100644 --- a/drivers/clk/ti/clk-k3-pll.c +++ b/drivers/clk/ti/clk-k3-pll.c @@ -6,7 +6,6 @@ * Tero Kristo */ -#include #include #include #include diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c index 7aa162c2f70..41e5022ea0c 100644 --- a/drivers/clk/ti/clk-k3.c +++ b/drivers/clk/ti/clk-k3.c @@ -6,7 +6,6 @@ * Tero Kristo */ -#include #include #include #include diff --git a/drivers/clk/ti/clk-mux.c b/drivers/clk/ti/clk-mux.c index 215241b1613..db539341431 100644 --- a/drivers/clk/ti/clk-mux.c +++ b/drivers/clk/ti/clk-mux.c @@ -7,7 +7,6 @@ * Based on Linux kernel drivers/clk/ti/mux.c */ -#include #include #include #include diff --git a/drivers/clk/ti/clk-sci.c b/drivers/clk/ti/clk-sci.c index 9e5760d3354..e374bd3bcc2 100644 --- a/drivers/clk/ti/clk-sci.c +++ b/drivers/clk/ti/clk-sci.c @@ -8,7 +8,6 @@ * Loosely based on Linux kernel sci-clk.c... */ -#include #include #include #include diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c index 6e5cc90f0f8..28cd1512881 100644 --- a/drivers/clk/ti/clk.c +++ b/drivers/clk/ti/clk.c @@ -5,7 +5,6 @@ * Copyright (C) 2020 Dario Binacchi */ -#include #include #include #include diff --git a/drivers/clk/ti/omap4-cm.c b/drivers/clk/ti/omap4-cm.c index 3cdc9b28887..a30ce9d09d2 100644 --- a/drivers/clk/ti/omap4-cm.c +++ b/drivers/clk/ti/omap4-cm.c @@ -5,7 +5,6 @@ * Copyright (C) 2020 Dario Binacchi */ -#include #include #include diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c index c31e59641d9..33369c93916 100644 --- a/drivers/clk/uniphier/clk-uniphier-core.c +++ b/drivers/clk/uniphier/clk-uniphier-core.c @@ -4,7 +4,6 @@ * Author: Masahiro Yamada */ -#include #include #include #include diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c index 0ebd288ab42..9f784228921 100644 --- a/drivers/core/acpi.c +++ b/drivers/core/acpi.c @@ -8,7 +8,6 @@ #define LOG_CATEOGRY LOGC_ACPI -#include #include #include #include diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c index a86b9325dd8..437080ed778 100644 --- a/drivers/core/device-remove.c +++ b/drivers/core/device-remove.c @@ -10,7 +10,6 @@ #define LOG_CATEGORY LOGC_DM -#include #include #include #include diff --git a/drivers/core/device.c b/drivers/core/device.c index bf7f261cbce..18e2bd02dd5 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -8,8 +8,8 @@ * Pavel Herrmann */ -#include #include +#include #include #include #include diff --git a/drivers/core/devres.c b/drivers/core/devres.c index 78914bdf7f2..8df08b91021 100644 --- a/drivers/core/devres.c +++ b/drivers/core/devres.c @@ -9,7 +9,6 @@ #define LOG_CATEGORY LOGC_DEVRES -#include #include #include #include diff --git a/drivers/core/dump.c b/drivers/core/dump.c index 841124830ee..5ec30d5b3c1 100644 --- a/drivers/core/dump.c +++ b/drivers/core/dump.c @@ -3,7 +3,6 @@ * Copyright (c) 2015 Google, Inc */ -#include #include #include #include diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c index 5f27d251148..6be8ea0c0a9 100644 --- a/drivers/core/fdtaddr.c +++ b/drivers/core/fdtaddr.c @@ -8,7 +8,6 @@ * Pavel Herrmann */ -#include #include #include #include diff --git a/drivers/core/lists.c b/drivers/core/lists.c index 8034a8f48d9..2839a9b7371 100644 --- a/drivers/core/lists.c +++ b/drivers/core/lists.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY LOGC_DM -#include #include #include #include diff --git a/drivers/core/of_access.c b/drivers/core/of_access.c index c8db743f529..41f2e09b9c2 100644 --- a/drivers/core/of_access.c +++ b/drivers/core/of_access.c @@ -19,7 +19,6 @@ * Linux version. */ -#include #include #include #include diff --git a/drivers/core/of_addr.c b/drivers/core/of_addr.c index b3b3d7ccdd5..d7913ab3d2f 100644 --- a/drivers/core/of_addr.c +++ b/drivers/core/of_addr.c @@ -6,7 +6,6 @@ * Copyright (c) 2017 Google, Inc */ -#include #include #include #include diff --git a/drivers/core/of_extra.c b/drivers/core/of_extra.c index 59ce9174ad0..a3ebe9e9c24 100644 --- a/drivers/core/of_extra.c +++ b/drivers/core/of_extra.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 21a233f90f0..9a5eaaa4d13 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY LOGC_DT -#include #include #include #include diff --git a/drivers/core/read.c b/drivers/core/read.c index 1a4a95cddea..55c19f335ae 100644 --- a/drivers/core/read.c +++ b/drivers/core/read.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/core/read_extra.c b/drivers/core/read_extra.c index 51383488278..5a0153a4661 100644 --- a/drivers/core/read_extra.c +++ b/drivers/core/read_extra.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c index dd32328098c..7ff7834bdf0 100644 --- a/drivers/core/regmap.c +++ b/drivers/core/regmap.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY LOGC_DM -#include #include #include #include diff --git a/drivers/core/root.c b/drivers/core/root.c index d4ae652bcfb..4bfd08f4813 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_ROOT -#include #include #include #include diff --git a/drivers/core/simple-bus.c b/drivers/core/simple-bus.c index 6022e7514e0..f402bb5d674 100644 --- a/drivers/core/simple-bus.c +++ b/drivers/core/simple-bus.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_SIMPLE_BUS -#include #include #include #include diff --git a/drivers/core/simple-pm-bus.c b/drivers/core/simple-pm-bus.c index 1bb0d86e289..f38372ec60b 100644 --- a/drivers/core/simple-pm-bus.c +++ b/drivers/core/simple-pm-bus.c @@ -3,7 +3,6 @@ * Copyright (C) 2020 Sean Anderson */ -#include #include #include diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c index a47b8bd3c01..f0e69d7216b 100644 --- a/drivers/core/syscon-uclass.c +++ b/drivers/core/syscon-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_SYSCON -#include #include #include #include diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index e46d5717aa6..762536eebc6 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY LOGC_DM -#include #include #include #include diff --git a/drivers/core/util.c b/drivers/core/util.c index 81497df85ff..108a3bc4dac 100644 --- a/drivers/core/util.c +++ b/drivers/core/util.c @@ -3,7 +3,6 @@ * Copyright (c) 2013 Google, Inc */ -#include #include #include #include diff --git a/drivers/cpu/at91_cpu.c b/drivers/cpu/at91_cpu.c index 34a3f61c7e9..b45cc6ca1a9 100644 --- a/drivers/cpu/at91_cpu.c +++ b/drivers/cpu/at91_cpu.c @@ -5,7 +5,6 @@ * Author: Claudiu Beznea */ -#include #include #include #include diff --git a/drivers/cpu/bmips_cpu.c b/drivers/cpu/bmips_cpu.c index 3dd04fa8858..db624ee47fb 100644 --- a/drivers/cpu/bmips_cpu.c +++ b/drivers/cpu/bmips_cpu.c @@ -7,7 +7,6 @@ * Copyright (C) 2009 Florian Fainelli */ -#include #include #include #include diff --git a/drivers/cpu/cpu-uclass.c b/drivers/cpu/cpu-uclass.c index 9772578968b..16f8f2e5219 100644 --- a/drivers/cpu/cpu-uclass.c +++ b/drivers/cpu/cpu-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_CPU -#include #include #include #include diff --git a/drivers/cpu/cpu_sandbox.c b/drivers/cpu/cpu_sandbox.c index 2e871fe313c..e65e1bdc51b 100644 --- a/drivers/cpu/cpu_sandbox.c +++ b/drivers/cpu/cpu_sandbox.c @@ -4,7 +4,6 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ -#include #include #include diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 98ff95f5ff5..4781a565547 100644 --- a/drivers/cpu/imx8_cpu.c +++ b/drivers/cpu/imx8_cpu.c @@ -3,7 +3,6 @@ * Copyright 2019 NXP */ -#include #include #include #include diff --git a/drivers/cpu/microblaze_cpu.c b/drivers/cpu/microblaze_cpu.c index a229f6913b0..4e24ada4002 100644 --- a/drivers/cpu/microblaze_cpu.c +++ b/drivers/cpu/microblaze_cpu.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2022, Ovidiu Panait */ -#include #include #include #include diff --git a/drivers/cpu/mpc83xx_cpu.c b/drivers/cpu/mpc83xx_cpu.c index e451c11116a..9a7b5fd7c42 100644 --- a/drivers/cpu/mpc83xx_cpu.c +++ b/drivers/cpu/mpc83xx_cpu.c @@ -4,7 +4,6 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ -#include #include #include #include diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c index d39a943cb84..4fff4658b5f 100644 --- a/drivers/cpu/riscv_cpu.c +++ b/drivers/cpu/riscv_cpu.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/drivers/crypto/ace_sha.c b/drivers/crypto/ace_sha.c index 261d3efe84e..0e43e82fc5f 100644 --- a/drivers/crypto/ace_sha.c +++ b/drivers/crypto/ace_sha.c @@ -3,10 +3,12 @@ * Advanced Crypto Engine - SHA Firmware * Copyright (c) 2012 Samsung Electronics */ -#include + +#include #include "ace_sha.h" #include #include +#include #ifdef CONFIG_SHA_HW_ACCEL #include diff --git a/drivers/crypto/ace_sha.h b/drivers/crypto/ace_sha.h index ad9e81a586c..efc791a4def 100644 --- a/drivers/crypto/ace_sha.h +++ b/drivers/crypto/ace_sha.h @@ -8,6 +8,8 @@ #ifndef __ACE_SHA_H #define __ACE_SHA_H +#include + struct exynos_ace_sfr { unsigned int fc_intstat; /* base + 0 */ unsigned int fc_intenset; diff --git a/drivers/crypto/aspeed/aspeed_acry.c b/drivers/crypto/aspeed/aspeed_acry.c index 47a007f633a..e3f81ebd5c7 100644 --- a/drivers/crypto/aspeed/aspeed_acry.c +++ b/drivers/crypto/aspeed/aspeed_acry.c @@ -3,7 +3,6 @@ * Copyright 2021 ASPEED Technology Inc. */ #include -#include #include #include #include diff --git a/drivers/crypto/aspeed/aspeed_hace.c b/drivers/crypto/aspeed/aspeed_hace.c index 6b6c8fa6588..17cc30a7b54 100644 --- a/drivers/crypto/aspeed/aspeed_hace.c +++ b/drivers/crypto/aspeed/aspeed_hace.c @@ -3,7 +3,6 @@ * Copyright 2021 ASPEED Technology Inc. */ #include -#include #include #include #include diff --git a/drivers/crypto/fsl/dcp_rng.c b/drivers/crypto/fsl/dcp_rng.c index 31706960157..6b19c171fcd 100644 --- a/drivers/crypto/fsl/dcp_rng.c +++ b/drivers/crypto/fsl/dcp_rng.c @@ -7,7 +7,6 @@ * Based on RNGC driver in drivers/char/hw_random/imx-rngc.c in Linux */ -#include #include #include #include diff --git a/drivers/crypto/fsl/error.c b/drivers/crypto/fsl/error.c index c76574919c7..7b232d94c2a 100644 --- a/drivers/crypto/fsl/error.c +++ b/drivers/crypto/fsl/error.c @@ -7,9 +7,9 @@ * Derived from error.c file in linux drivers/crypto/caam */ -#include #include #include +#include #include "desc.h" #include "jr.h" diff --git a/drivers/crypto/fsl/fsl_blob.c b/drivers/crypto/fsl/fsl_blob.c index 9b6e4bca062..0ecd6befd25 100644 --- a/drivers/crypto/fsl/fsl_blob.c +++ b/drivers/crypto/fsl/fsl_blob.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c index f22f24b6077..79b32e2627c 100644 --- a/drivers/crypto/fsl/fsl_hash.c +++ b/drivers/crypto/fsl/fsl_hash.c @@ -4,7 +4,6 @@ * Copyright 2021 NXP */ -#include #include #include #include diff --git a/drivers/crypto/fsl/fsl_mfgprot.c b/drivers/crypto/fsl/fsl_mfgprot.c index 29af79f577d..7c22f8e012b 100644 --- a/drivers/crypto/fsl/fsl_mfgprot.c +++ b/drivers/crypto/fsl/fsl_mfgprot.c @@ -4,7 +4,6 @@ * Copyright 2017 NXP */ -#include #include #include #include diff --git a/drivers/crypto/fsl/fsl_rsa.c b/drivers/crypto/fsl/fsl_rsa.c index 335b7fe25ac..125a72ae6d3 100644 --- a/drivers/crypto/fsl/fsl_rsa.c +++ b/drivers/crypto/fsl/fsl_rsa.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c index d32c1fe5c31..55191736931 100644 --- a/drivers/crypto/fsl/jobdesc.c +++ b/drivers/crypto/fsl/jobdesc.c @@ -8,7 +8,7 @@ * */ -#include +#include #include #include #include "desc_constr.h" diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 8ae5c434bdb..27e24808946 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -6,7 +6,7 @@ * Based on CAAM driver in drivers/crypto/caam in Linux */ -#include +#include #include #include #include diff --git a/drivers/crypto/fsl/rng.c b/drivers/crypto/fsl/rng.c index 06364948052..786a710f5fb 100644 --- a/drivers/crypto/fsl/rng.c +++ b/drivers/crypto/fsl/rng.c @@ -7,7 +7,6 @@ */ #include -#include #include #include #include diff --git a/drivers/crypto/fsl/sec.c b/drivers/crypto/fsl/sec.c index 9de30a6112f..e9c39ddcfd9 100644 --- a/drivers/crypto/fsl/sec.c +++ b/drivers/crypto/fsl/sec.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include +#include #include #include #if CONFIG_SYS_FSL_SEC_COMPAT == 2 || CONFIG_SYS_FSL_SEC_COMPAT >= 4 diff --git a/drivers/crypto/hash/hash-uclass.c b/drivers/crypto/hash/hash-uclass.c index 446eb9e56a4..5d9f1e0d59b 100644 --- a/drivers/crypto/hash/hash-uclass.c +++ b/drivers/crypto/hash/hash-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_HASH -#include #include #include #include diff --git a/drivers/crypto/hash/hash_sw.c b/drivers/crypto/hash/hash_sw.c index d8065d68ea4..ffd4ab149ff 100644 --- a/drivers/crypto/hash/hash_sw.c +++ b/drivers/crypto/hash/hash_sw.c @@ -4,7 +4,6 @@ * Author: ChiaWei Wang */ #include -#include #include #include #include diff --git a/drivers/crypto/nuvoton/npcm_aes.c b/drivers/crypto/nuvoton/npcm_aes.c index 6493ea108ec..8d3a30ea918 100644 --- a/drivers/crypto/nuvoton/npcm_aes.c +++ b/drivers/crypto/nuvoton/npcm_aes.c @@ -3,13 +3,13 @@ * Copyright (c) 2021 Nuvoton Technology Corp. */ -#include #include #include #include #include #include #include +#include #define ONE_SECOND 0xC00000 diff --git a/drivers/crypto/nuvoton/npcm_sha.c b/drivers/crypto/nuvoton/npcm_sha.c index 2a5e6726880..6da162069aa 100644 --- a/drivers/crypto/nuvoton/npcm_sha.c +++ b/drivers/crypto/nuvoton/npcm_sha.c @@ -3,7 +3,6 @@ * Copyright (c) 2024 Nuvoton Technology Corp. */ -#include #include #include #include diff --git a/drivers/crypto/rsa_mod_exp/mod_exp_sw.c b/drivers/crypto/rsa_mod_exp/mod_exp_sw.c index 7bed444c3fb..4f59adc09c9 100644 --- a/drivers/crypto/rsa_mod_exp/mod_exp_sw.c +++ b/drivers/crypto/rsa_mod_exp/mod_exp_sw.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/drivers/crypto/rsa_mod_exp/mod_exp_uclass.c b/drivers/crypto/rsa_mod_exp/mod_exp_uclass.c index 057cc74b10b..107500dd6e0 100644 --- a/drivers/crypto/rsa_mod_exp/mod_exp_uclass.c +++ b/drivers/crypto/rsa_mod_exp/mod_exp_uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_MOD_EXP -#include #include #include #include diff --git a/drivers/ddr/altera/sdram_agilex.c b/drivers/ddr/altera/sdram_agilex.c index 65ecdd022c4..7f2cccb6af2 100644 --- a/drivers/ddr/altera/sdram_agilex.c +++ b/drivers/ddr/altera/sdram_agilex.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c index 8ef5fa4c481..bd2af94bb0d 100644 --- a/drivers/ddr/altera/sdram_arria10.c +++ b/drivers/ddr/altera/sdram_arria10.c @@ -3,7 +3,6 @@ * Copyright (C) 2017 Intel Corporation */ -#include #include #include #include diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c index 34d2a2789cc..46c53e7c7a3 100644 --- a/drivers/ddr/altera/sdram_gen5.c +++ b/drivers/ddr/altera/sdram_gen5.c @@ -2,7 +2,6 @@ /* * Copyright Altera Corporation (C) 2014-2015 */ -#include #include #include #include diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index d9039443b91..db09986f64b 100644 --- a/drivers/ddr/altera/sdram_n5x.c +++ b/drivers/ddr/altera/sdram_n5x.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index 4d36fb45332..4ac4c79e0ac 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index 4716abfc9a8..9e57c2ecfa4 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index e402f2929ab..7636e71a0a6 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -3,8 +3,8 @@ * Copyright Altera Corporation (C) 2012-2015 */ -#include #include +#include #include #include #include diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h index c72a683ffef..618ba00da64 100644 --- a/drivers/ddr/altera/sequencer.h +++ b/drivers/ddr/altera/sequencer.h @@ -6,6 +6,8 @@ #ifndef _SEQUENCER_H_ #define _SEQUENCER_H_ +#include + #define RW_MGR_NUM_DM_PER_WRITE_GROUP (seq->rwcfg->mem_data_mask_width \ / seq->rwcfg->mem_if_write_dqs_width) #define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP ( \ diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c index 9dada5e1175..9f9aea804d9 100644 --- a/drivers/ddr/fsl/arm_ddr_gen3.c +++ b/drivers/ddr/fsl/arm_ddr_gen3.c @@ -5,7 +5,7 @@ * Derived from mpc85xx_ddr_gen3.c, removed all workarounds */ -#include +#include #include #include #include diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 8f8c2c864c3..9a25192c079 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -10,12 +10,13 @@ * Author: James Yang [at freescale.com] */ -#include +#include #include #include #include #include #include +#include #include #include #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \ diff --git a/drivers/ddr/fsl/ddr1_dimm_params.c b/drivers/ddr/fsl/ddr1_dimm_params.c index e5481eaa0dd..cc87a95214d 100644 --- a/drivers/ddr/fsl/ddr1_dimm_params.c +++ b/drivers/ddr/fsl/ddr1_dimm_params.c @@ -3,7 +3,6 @@ * Copyright 2008 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/drivers/ddr/fsl/ddr2_dimm_params.c b/drivers/ddr/fsl/ddr2_dimm_params.c index 3b78118a9d8..5674685a191 100644 --- a/drivers/ddr/fsl/ddr2_dimm_params.c +++ b/drivers/ddr/fsl/ddr2_dimm_params.c @@ -3,9 +3,9 @@ * Copyright 2008 Freescale Semiconductor, Inc. */ -#include #include #include +#include #include #include diff --git a/drivers/ddr/fsl/ddr3_dimm_params.c b/drivers/ddr/fsl/ddr3_dimm_params.c index 1f8db90c45b..c30ecdaafaf 100644 --- a/drivers/ddr/fsl/ddr3_dimm_params.c +++ b/drivers/ddr/fsl/ddr3_dimm_params.c @@ -8,7 +8,7 @@ * JEDEC standard No.21-C 4_01_02_11R18.pdf */ -#include +#include #include #include diff --git a/drivers/ddr/fsl/ddr4_dimm_params.c b/drivers/ddr/fsl/ddr4_dimm_params.c index ea791622628..75e3bfe08be 100644 --- a/drivers/ddr/fsl/ddr4_dimm_params.c +++ b/drivers/ddr/fsl/ddr4_dimm_params.c @@ -10,10 +10,10 @@ * */ -#include #include #include #include +#include #include diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index f8d1468a26f..31c58d9a8e3 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -4,7 +4,7 @@ * Copyright 2021 NXP */ -#include +#include #include #include #include diff --git a/drivers/ddr/fsl/fsl_mmdc.c b/drivers/ddr/fsl/fsl_mmdc.c index 28f2219b2a4..7812b1b01ca 100644 --- a/drivers/ddr/fsl/fsl_mmdc.c +++ b/drivers/ddr/fsl/fsl_mmdc.c @@ -7,7 +7,7 @@ * Generic driver for Freescale MMDC(Multi Mode DDR Controller). */ -#include +#include #include #include #include diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c index eb2f06e8300..94a5e447d56 100644 --- a/drivers/ddr/fsl/interactive.c +++ b/drivers/ddr/fsl/interactive.c @@ -11,11 +11,11 @@ * York Sun [at freescale.com] */ -#include #include #include #include #include +#include #include #include #include diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c index 5e4ad56f071..aaf9800b372 100644 --- a/drivers/ddr/fsl/lc_common_dimm_params.c +++ b/drivers/ddr/fsl/lc_common_dimm_params.c @@ -4,7 +4,6 @@ * Copyright 2017-2021 NXP Semiconductor */ -#include #include #include #include diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index cd332718b64..31091bb4495 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -10,7 +10,7 @@ * Author: James Yang [at freescale.com] */ -#include +#include #include #include #include diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c index 16186bdbae7..a8520754006 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c @@ -3,7 +3,7 @@ * Copyright 2008 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c index b830e7cbd14..00b4b376dd4 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c @@ -3,9 +3,9 @@ * Copyright 2008-2011 Freescale Semiconductor, Inc. */ -#include +#include #include -#include +#include #include #include diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index 1c4a1cae4df..b0a61fa2b41 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -3,9 +3,10 @@ * Copyright 2008-2020 Freescale Semiconductor, Inc. */ -#include +#include #include #include +#include #include #include #include diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c index 7cff8234584..852a5d0eca4 100644 --- a/drivers/ddr/fsl/options.c +++ b/drivers/ddr/fsl/options.c @@ -4,16 +4,19 @@ * Copyright 2017-2018 NXP Semiconductor */ -#include +#include #include #include #include #include +#include #include #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \ defined(CONFIG_ARM) #include +#else +#include #endif /* diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index 60051392e71..0a73170e418 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -4,9 +4,10 @@ * Copyright 2021 NXP */ -#include +#include #ifdef CONFIG_PPC #include +#include #endif #include #include diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c index 52a4aa63230..e9209ce8b61 100644 --- a/drivers/ddr/imx/imx8m/ddr_init.c +++ b/drivers/ddr/imx/imx8m/ddr_init.c @@ -3,7 +3,6 @@ * Copyright 2018-2019 NXP */ -#include #include #include #include diff --git a/drivers/ddr/imx/imx8ulp/ddr_init.c b/drivers/ddr/imx/imx8ulp/ddr_init.c index c362a2da338..172e260a55d 100644 --- a/drivers/ddr/imx/imx8ulp/ddr_init.c +++ b/drivers/ddr/imx/imx8ulp/ddr_init.c @@ -2,7 +2,6 @@ /* * Copyright 2021 NXP */ -#include #include #include #include diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c index 7a333880e6b..5b0ad773875 100644 --- a/drivers/ddr/imx/imx9/ddr_init.c +++ b/drivers/ddr/imx/imx9/ddr_init.c @@ -3,7 +3,6 @@ * Copyright 2022 NXP */ -#include #include #include #include @@ -11,6 +10,7 @@ #include #include #include +#include static unsigned int g_cdd_rr_max[4]; static unsigned int g_cdd_rw_max[4]; diff --git a/drivers/ddr/imx/phy/ddrphy_train.c b/drivers/ddr/imx/phy/ddrphy_train.c index cd905f952c6..ccc10df1845 100644 --- a/drivers/ddr/imx/phy/ddrphy_train.c +++ b/drivers/ddr/imx/phy/ddrphy_train.c @@ -3,7 +3,6 @@ * Copyright 2018 NXP */ -#include #include #include #include diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c index 45e1a70dbd4..cf5bdad7abe 100644 --- a/drivers/ddr/imx/phy/ddrphy_utils.c +++ b/drivers/ddr/imx/phy/ddrphy_utils.c @@ -3,7 +3,6 @@ * Copyright 2018 NXP */ -#include #include #include #include diff --git a/drivers/ddr/imx/phy/helper.c b/drivers/ddr/imx/phy/helper.c index b9b2403012d..c1fc800f191 100644 --- a/drivers/ddr/imx/phy/helper.c +++ b/drivers/ddr/imx/phy/helper.c @@ -3,7 +3,6 @@ * Copyright 2018 NXP */ -#include #include #include #include diff --git a/drivers/ddr/marvell/axp/ddr3_dfs.c b/drivers/ddr/marvell/axp/ddr3_dfs.c index 2a4596680b1..985835ec923 100644 --- a/drivers/ddr/marvell/axp/ddr3_dfs.c +++ b/drivers/ddr/marvell/axp/ddr3_dfs.c @@ -3,7 +3,6 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ -#include #include #include #include diff --git a/drivers/ddr/marvell/axp/ddr3_dqs.c b/drivers/ddr/marvell/axp/ddr3_dqs.c index 0db94212b90..bda0d7ec473 100644 --- a/drivers/ddr/marvell/axp/ddr3_dqs.c +++ b/drivers/ddr/marvell/axp/ddr3_dqs.c @@ -3,7 +3,6 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ -#include #include #include #include diff --git a/drivers/ddr/marvell/axp/ddr3_hw_training.c b/drivers/ddr/marvell/axp/ddr3_hw_training.c index 35d98faf58f..bb3e1be1f4c 100644 --- a/drivers/ddr/marvell/axp/ddr3_hw_training.c +++ b/drivers/ddr/marvell/axp/ddr3_hw_training.c @@ -3,7 +3,6 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ -#include #include #include #include diff --git a/drivers/ddr/marvell/axp/ddr3_init.c b/drivers/ddr/marvell/axp/ddr3_init.c index a9dcb74cecb..23c6d119f61 100644 --- a/drivers/ddr/marvell/axp/ddr3_init.c +++ b/drivers/ddr/marvell/axp/ddr3_init.c @@ -3,7 +3,6 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ -#include #include #include #include diff --git a/drivers/ddr/marvell/axp/ddr3_pbs.c b/drivers/ddr/marvell/axp/ddr3_pbs.c index 069a42fbf5e..2322900185d 100644 --- a/drivers/ddr/marvell/axp/ddr3_pbs.c +++ b/drivers/ddr/marvell/axp/ddr3_pbs.c @@ -3,7 +3,6 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ -#include #include #include #include diff --git a/drivers/ddr/marvell/axp/ddr3_read_leveling.c b/drivers/ddr/marvell/axp/ddr3_read_leveling.c index 30a5c354885..db7003f72ca 100644 --- a/drivers/ddr/marvell/axp/ddr3_read_leveling.c +++ b/drivers/ddr/marvell/axp/ddr3_read_leveling.c @@ -3,7 +3,6 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ -#include #include #include #include diff --git a/drivers/ddr/marvell/axp/ddr3_sdram.c b/drivers/ddr/marvell/axp/ddr3_sdram.c index 0b150b20f3a..f8fee2623d0 100644 --- a/drivers/ddr/marvell/axp/ddr3_sdram.c +++ b/drivers/ddr/marvell/axp/ddr3_sdram.c @@ -3,7 +3,6 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ -#include #include #include #include diff --git a/drivers/ddr/marvell/axp/ddr3_spd.c b/drivers/ddr/marvell/axp/ddr3_spd.c index 4763403c127..c169a8ea16b 100644 --- a/drivers/ddr/marvell/axp/ddr3_spd.c +++ b/drivers/ddr/marvell/axp/ddr3_spd.c @@ -3,7 +3,6 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ -#include #include #include #include diff --git a/drivers/ddr/marvell/axp/ddr3_write_leveling.c b/drivers/ddr/marvell/axp/ddr3_write_leveling.c index d4add447774..ea7bac56d0e 100644 --- a/drivers/ddr/marvell/axp/ddr3_write_leveling.c +++ b/drivers/ddr/marvell/axp/ddr3_write_leveling.c @@ -3,7 +3,6 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ -#include #include #include #include diff --git a/drivers/ddr/marvell/axp/xor.c b/drivers/ddr/marvell/axp/xor.c index 76aea96682c..6ecacfeb933 100644 --- a/drivers/ddr/marvell/axp/xor.c +++ b/drivers/ddr/marvell/axp/xor.c @@ -3,7 +3,6 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ -#include #include #include #include diff --git a/drivers/ddr/microchip/ddr2.c b/drivers/ddr/microchip/ddr2.c index 149b6071cfd..bfba5d245c6 100644 --- a/drivers/ddr/microchip/ddr2.c +++ b/drivers/ddr/microchip/ddr2.c @@ -3,7 +3,6 @@ * (c) 2015 Paul Thacker * */ -#include #include #include #include diff --git a/drivers/demo/demo-pdata.c b/drivers/demo/demo-pdata.c index 818f77503a3..73711991626 100644 --- a/drivers/demo/demo-pdata.c +++ b/drivers/demo/demo-pdata.c @@ -3,7 +3,6 @@ * Copyright (c) 2013 Google, Inc */ -#include #include #include diff --git a/drivers/demo/demo-shape.c b/drivers/demo/demo-shape.c index b6b29bcb31b..3ccd5bced95 100644 --- a/drivers/demo/demo-shape.c +++ b/drivers/demo/demo-shape.c @@ -3,7 +3,6 @@ * Copyright (c) 2013 Google, Inc */ -#include #include #include #include diff --git a/drivers/demo/demo-simple.c b/drivers/demo/demo-simple.c index 28b271f7791..944d5897222 100644 --- a/drivers/demo/demo-simple.c +++ b/drivers/demo/demo-simple.c @@ -6,7 +6,6 @@ * Pavel Herrmann */ -#include #include #include #include diff --git a/drivers/demo/demo-uclass.c b/drivers/demo/demo-uclass.c index 09f9a47d4de..d7b1305dc65 100644 --- a/drivers/demo/demo-uclass.c +++ b/drivers/demo/demo-uclass.c @@ -6,7 +6,6 @@ * Pavel Herrmann */ -#include #include #include #include diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index 2adf26e2fe2..540d48fab77 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -6,7 +6,6 @@ * author: Lukasz Majewski */ -#include #include #include #include diff --git a/drivers/dfu/dfu_alt.c b/drivers/dfu/dfu_alt.c index ece3d2236f3..e9132936a90 100644 --- a/drivers/dfu/dfu_alt.c +++ b/drivers/dfu/dfu_alt.c @@ -4,7 +4,6 @@ * Lukasz Majewski */ -#include #include #include #include diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c index 12c54e90ef7..cfa6334e439 100644 --- a/drivers/dfu/dfu_mmc.c +++ b/drivers/dfu/dfu_mmc.c @@ -6,7 +6,6 @@ * author: Lukasz Majewski */ -#include #include #include #include diff --git a/drivers/dfu/dfu_mtd.c b/drivers/dfu/dfu_mtd.c index 485586989c8..c36ac09189f 100644 --- a/drivers/dfu/dfu_mtd.c +++ b/drivers/dfu/dfu_mtd.c @@ -7,7 +7,6 @@ * Based on dfu_nand.c */ -#include #include #include #include diff --git a/drivers/dfu/dfu_nand.c b/drivers/dfu/dfu_nand.c index 08e8cf5cdb3..940cfefc986 100644 --- a/drivers/dfu/dfu_nand.c +++ b/drivers/dfu/dfu_nand.c @@ -9,7 +9,6 @@ * author: Lukasz Majewski */ -#include #include #include #include diff --git a/drivers/dfu/dfu_ram.c b/drivers/dfu/dfu_ram.c index c4f4bd2e482..043acbf022f 100644 --- a/drivers/dfu/dfu_ram.c +++ b/drivers/dfu/dfu_ram.c @@ -8,7 +8,6 @@ * author: Lukasz Majewski */ -#include #include #include #include diff --git a/drivers/dfu/dfu_sf.c b/drivers/dfu/dfu_sf.c index 2dae1593706..7c1c0f9e2dc 100644 --- a/drivers/dfu/dfu_sf.c +++ b/drivers/dfu/dfu_sf.c @@ -3,7 +3,6 @@ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. */ -#include #include #include #include diff --git a/drivers/dfu/dfu_virt.c b/drivers/dfu/dfu_virt.c index 29f7a08f672..2c31445af12 100644 --- a/drivers/dfu/dfu_virt.c +++ b/drivers/dfu/dfu_virt.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2019, STMicroelectronics - All Rights Reserved */ -#include #include #include #include diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c index da988f6bb66..331815c469f 100644 --- a/drivers/dma/apbh_dma.c +++ b/drivers/dma/apbh_dma.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/drivers/dma/bcm6348-iudma.c b/drivers/dma/bcm6348-iudma.c index 33c7b981415..fd3a353d548 100644 --- a/drivers/dma/bcm6348-iudma.c +++ b/drivers/dma/bcm6348-iudma.c @@ -15,7 +15,6 @@ * Copyright (C) 2010 Broadcom Corporation */ -#include #include #include #include diff --git a/drivers/dma/dma-uclass.c b/drivers/dma/dma-uclass.c index 0c1d88e10c6..2c76ba3fe32 100644 --- a/drivers/dma/dma-uclass.c +++ b/drivers/dma/dma-uclass.c @@ -11,7 +11,6 @@ #define LOG_CATEGORY UCLASS_DMA -#include #include #include #include diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c index 700df2236bd..0cd9bcb5110 100644 --- a/drivers/dma/fsl_dma.c +++ b/drivers/dma/fsl_dma.c @@ -9,7 +9,6 @@ */ #include -#include #include #include diff --git a/drivers/dma/keystone_nav.c b/drivers/dma/keystone_nav.c index 9a5ba79f3fe..c84db454bfd 100644 --- a/drivers/dma/keystone_nav.c +++ b/drivers/dma/keystone_nav.c @@ -5,10 +5,10 @@ * (C) Copyright 2012-2014 * Texas Instruments Incorporated, */ -#include #include #include #include +#include struct qm_config qm_memmap = { .stat_cfg = KS2_QM_QUEUE_STATUS_BASE, diff --git a/drivers/dma/lpc32xx_dma.c b/drivers/dma/lpc32xx_dma.c index 0efdfd028cf..f15b67546a9 100644 --- a/drivers/dma/lpc32xx_dma.c +++ b/drivers/dma/lpc32xx_dma.c @@ -7,9 +7,9 @@ * Copyright (c) 2015 Tyco Fire Protection Products. */ -#include #include #include +#include #include #include #include diff --git a/drivers/dma/sandbox-dma-test.c b/drivers/dma/sandbox-dma-test.c index a19e5e37fb9..0290b93340f 100644 --- a/drivers/dma/sandbox-dma-test.c +++ b/drivers/dma/sandbox-dma-test.c @@ -7,7 +7,6 @@ * Author: Grygorii Strashko */ -#include #include #include #include diff --git a/drivers/dma/ti-edma3.c b/drivers/dma/ti-edma3.c index 31ffff07f5b..d64059f39ab 100644 --- a/drivers/dma/ti-edma3.c +++ b/drivers/dma/ti-edma3.c @@ -10,7 +10,6 @@ #include #include -#include #include #include #include diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 8f6d396653e..da341a24778 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -5,7 +5,6 @@ */ #define pr_fmt(fmt) "udma: " fmt -#include #include #include #include diff --git a/drivers/dma/xilinx_dpdma.c b/drivers/dma/xilinx_dpdma.c index d4ee21dfc07..1d615ec2838 100644 --- a/drivers/dma/xilinx_dpdma.c +++ b/drivers/dma/xilinx_dpdma.c @@ -3,7 +3,6 @@ * Copyright (C) 2021 Xilinx Inc. */ -#include #include #include #include diff --git a/drivers/extcon/extcon-max14526.c b/drivers/extcon/extcon-max14526.c index a33b5ef919c..2d2166bde68 100644 --- a/drivers/extcon/extcon-max14526.c +++ b/drivers/extcon/extcon-max14526.c @@ -3,7 +3,6 @@ * Copyright (c) 2022 Svyatoslav Ryhel */ -#include #include #include #include diff --git a/drivers/extcon/extcon-uclass.c b/drivers/extcon/extcon-uclass.c index 9dd22b57626..1a592873882 100644 --- a/drivers/extcon/extcon-uclass.c +++ b/drivers/extcon/extcon-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_EXTCON -#include #include #include diff --git a/drivers/fastboot/fb_command.c b/drivers/fastboot/fb_command.c index 01443c5d39e..e4484d65aca 100644 --- a/drivers/fastboot/fb_command.c +++ b/drivers/fastboot/fb_command.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 The Android Open Source Project */ -#include #include #include #include @@ -13,6 +12,7 @@ #include #include #include +#include #include /** diff --git a/drivers/fastboot/fb_common.c b/drivers/fastboot/fb_common.c index 3576b067729..12ffb463deb 100644 --- a/drivers/fastboot/fb_common.c +++ b/drivers/fastboot/fb_common.c @@ -11,11 +11,11 @@ */ #include -#include #include #include #include #include +#include /** * fastboot_buf_addr - base address of the fastboot download buffer diff --git a/drivers/fastboot/fb_getvar.c b/drivers/fastboot/fb_getvar.c index f65519c57b4..93cbd598e02 100644 --- a/drivers/fastboot/fb_getvar.c +++ b/drivers/fastboot/fb_getvar.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 The Android Open Source Project */ -#include #include #include #include @@ -12,6 +11,7 @@ #include #include #include +#include #include static void getvar_version(char *var_parameter, char *response); diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c index 060918e4910..f11eb66761b 100644 --- a/drivers/fastboot/fb_mmc.c +++ b/drivers/fastboot/fb_mmc.c @@ -4,7 +4,6 @@ */ #include -#include #include #include #include diff --git a/drivers/fastboot/fb_nand.c b/drivers/fastboot/fb_nand.c index bbe26ddcc9b..afc64fd5280 100644 --- a/drivers/fastboot/fb_nand.c +++ b/drivers/fastboot/fb_nand.c @@ -5,7 +5,6 @@ */ #include -#include #include #include diff --git a/drivers/firmware/arm-ffa/arm-ffa-uclass.c b/drivers/firmware/arm-ffa/arm-ffa-uclass.c index f1e91d151ea..e0767fc7551 100644 --- a/drivers/firmware/arm-ffa/arm-ffa-uclass.c +++ b/drivers/firmware/arm-ffa/arm-ffa-uclass.c @@ -5,7 +5,6 @@ * Authors: * Abdellatif El Khlifi */ -#include #include #include #include diff --git a/drivers/firmware/arm-ffa/arm-ffa.c b/drivers/firmware/arm-ffa/arm-ffa.c index ee0bf9a55b4..94e6105cb38 100644 --- a/drivers/firmware/arm-ffa/arm-ffa.c +++ b/drivers/firmware/arm-ffa/arm-ffa.c @@ -6,7 +6,6 @@ * Abdellatif El Khlifi */ -#include #include #include #include diff --git a/drivers/firmware/arm-ffa/ffa-emul-uclass.c b/drivers/firmware/arm-ffa/ffa-emul-uclass.c index 4bf9f6041fe..1521d9b66ac 100644 --- a/drivers/firmware/arm-ffa/ffa-emul-uclass.c +++ b/drivers/firmware/arm-ffa/ffa-emul-uclass.c @@ -5,7 +5,6 @@ * Authors: * Abdellatif El Khlifi */ -#include #include #include #include diff --git a/drivers/firmware/arm-ffa/sandbox_ffa.c b/drivers/firmware/arm-ffa/sandbox_ffa.c index 11142429c09..44b32a829dd 100644 --- a/drivers/firmware/arm-ffa/sandbox_ffa.c +++ b/drivers/firmware/arm-ffa/sandbox_ffa.c @@ -5,7 +5,6 @@ * Authors: * Abdellatif El Khlifi */ -#include #include #include #include diff --git a/drivers/firmware/firmware-sandbox.c b/drivers/firmware/firmware-sandbox.c index d970d75f781..226b5cfc191 100644 --- a/drivers/firmware/firmware-sandbox.c +++ b/drivers/firmware/firmware-sandbox.c @@ -5,7 +5,6 @@ * Copyright (C) 2018 Xilinx, Inc. */ -#include #include static const struct udevice_id generic_sandbox_firmware_ids[] = { diff --git a/drivers/firmware/firmware-uclass.c b/drivers/firmware/firmware-uclass.c index e83a147a000..84caf25548b 100644 --- a/drivers/firmware/firmware-uclass.c +++ b/drivers/firmware/firmware-uclass.c @@ -2,7 +2,6 @@ #define LOG_CATEGORY UCLASS_FIRMWARE -#include #include /* Firmware access is platform-dependent. No generic code in uclass */ diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index dfad798a2e7..f99507d86c6 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -5,7 +5,6 @@ * Copyright (C) 2018-2019 Xilinx, Inc. */ -#include #include #include #include diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c index 03544d76ed4..c32c3f5c6a5 100644 --- a/drivers/firmware/psci.c +++ b/drivers/firmware/psci.c @@ -6,7 +6,6 @@ * Copyright (C) 2015 ARM Limited */ -#include #include #include #include diff --git a/drivers/firmware/scmi/base.c b/drivers/firmware/scmi/base.c index 1d41a8a98fc..f4e3974ff5b 100644 --- a/drivers/firmware/scmi/base.c +++ b/drivers/firmware/scmi/base.c @@ -6,7 +6,6 @@ * author: AKASHI Takahiro */ -#include #include #include #include diff --git a/drivers/firmware/scmi/mailbox_agent.c b/drivers/firmware/scmi/mailbox_agent.c index 7ad3e8da9f0..6d4497f4b92 100644 --- a/drivers/firmware/scmi/mailbox_agent.c +++ b/drivers/firmware/scmi/mailbox_agent.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_SCMI_AGENT -#include #include #include #include diff --git a/drivers/firmware/scmi/optee_agent.c b/drivers/firmware/scmi/optee_agent.c index 48dbb88a3fb..631625d715b 100644 --- a/drivers/firmware/scmi/optee_agent.c +++ b/drivers/firmware/scmi/optee_agent.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_SCMI_AGENT -#include #include #include #include diff --git a/drivers/firmware/scmi/sandbox-scmi_agent.c b/drivers/firmware/scmi/sandbox-scmi_agent.c index cc9011c7312..19be280ec44 100644 --- a/drivers/firmware/scmi/sandbox-scmi_agent.c +++ b/drivers/firmware/scmi/sandbox-scmi_agent.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_SCMI_AGENT -#include #include #include #include diff --git a/drivers/firmware/scmi/sandbox-scmi_devices.c b/drivers/firmware/scmi/sandbox-scmi_devices.c index 603e2bb40af..96c2922b067 100644 --- a/drivers/firmware/scmi/sandbox-scmi_devices.c +++ b/drivers/firmware/scmi/sandbox-scmi_devices.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_MISC -#include #include #include #include diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c b/drivers/firmware/scmi/scmi_agent-uclass.c index 0f1003e167e..8c907c3b032 100644 --- a/drivers/firmware/scmi/scmi_agent-uclass.c +++ b/drivers/firmware/scmi/scmi_agent-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_SCMI_AGENT -#include #include #include #include diff --git a/drivers/firmware/scmi/smccc_agent.c b/drivers/firmware/scmi/smccc_agent.c index 972c6addde2..ac35d07ebaf 100644 --- a/drivers/firmware/scmi/smccc_agent.c +++ b/drivers/firmware/scmi/smccc_agent.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_SCMI_AGENT -#include #include #include #include diff --git a/drivers/firmware/scmi/smt.c b/drivers/firmware/scmi/smt.c index 509ed618a99..67d2f450024 100644 --- a/drivers/firmware/scmi/smt.c +++ b/drivers/firmware/scmi/smt.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_SCMI_AGENT -#include #include #include #include diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 6c581b9df9c..8ce0f46e70c 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -7,7 +7,6 @@ * Lokesh Vutla */ -#include #include #include #include diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c index 4c00cdf0b57..cb7877a8afe 100644 --- a/drivers/fpga/ACEX1K.c +++ b/drivers/fpga/ACEX1K.c @@ -9,7 +9,7 @@ #define LOG_CATEGORY UCLASS_FPGA -#include /* core U-Boot definitions */ +#include /* core U-Boot definitions */ #include #include #include /* ACEX device family */ diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index 6a4f0cb9bc0..ae06f0123a0 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -12,7 +12,6 @@ /* * Altera FPGA support */ -#include #include #include #include diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c index 6e8a313db35..7e78d6e2d6c 100644 --- a/drivers/fpga/cyclon2.c +++ b/drivers/fpga/cyclon2.c @@ -7,8 +7,9 @@ #define LOG_CATEGORY UCLASS_FPGA -#include /* core U-Boot definitions */ +#include /* core U-Boot definitions */ #include +#include #include #include /* ACEX device family */ #include diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index 81e6d8ffc0b..38ba6c21ea2 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -5,7 +5,6 @@ */ /* Generic FPGA support */ -#include /* core U-Boot definitions */ #include #include #include /* xilinx specific definitions */ diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c index 903d143a361..45caef4f5c1 100644 --- a/drivers/fpga/intel_sdm_mb.c +++ b/drivers/fpga/intel_sdm_mb.c @@ -3,14 +3,16 @@ * Copyright (C) 2018 Intel Corporation */ -#include #include #include +#include #include #include #include #include +#include #include +#include #define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 60000 #define RECONFIG_STATUS_INTERVAL_DELAY_US 1000000 diff --git a/drivers/fpga/ivm_core.c b/drivers/fpga/ivm_core.c index adc60919f3b..b9cecdd8720 100644 --- a/drivers/fpga/ivm_core.c +++ b/drivers/fpga/ivm_core.c @@ -29,7 +29,6 @@ * the ispVMLCOUNT function */ -#include #include #include #include diff --git a/drivers/fpga/lattice.c b/drivers/fpga/lattice.c index e292d991cd1..036580cad70 100644 --- a/drivers/fpga/lattice.c +++ b/drivers/fpga/lattice.c @@ -10,7 +10,6 @@ * Copyright 2009 Lattice Semiconductor Corp. */ -#include #include #include #include diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c index d73414d5ac5..bb98c0e2bcf 100644 --- a/drivers/fpga/socfpga.c +++ b/drivers/fpga/socfpga.c @@ -4,7 +4,7 @@ * All rights reserved. */ -#include +#include #include #include #include diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c index 96b195063e0..e9822b2bb0e 100644 --- a/drivers/fpga/socfpga_arria10.c +++ b/drivers/fpga/socfpga_arria10.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/fpga/socfpga_gen5.c b/drivers/fpga/socfpga_gen5.c index d73474f29ee..9473f057328 100644 --- a/drivers/fpga/socfpga_gen5.c +++ b/drivers/fpga/socfpga_gen5.c @@ -4,7 +4,7 @@ * All rights reserved. */ -#include +#include #include #include #include diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index 6eef87b78e1..9cd6cb7f0fb 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -6,7 +6,7 @@ #define LOG_CATEGORY UCLASS_FPGA -#include /* core U-Boot definitions */ +#include /* core U-Boot definitions */ #include #include /* Spartan-II device family */ diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index e892fa571f1..b4d87d47d93 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -11,8 +11,9 @@ #define LOG_CATEGORY UCLASS_FPGA -#include /* core U-Boot definitions */ +#include /* core U-Boot definitions */ #include +#include #include /* Spartan-II device family */ /* Note: The assumption is that we cannot possibly run fast enough to diff --git a/drivers/fpga/stratixII.c b/drivers/fpga/stratixII.c index b450a81072e..73fecd9dca5 100644 --- a/drivers/fpga/stratixII.c +++ b/drivers/fpga/stratixII.c @@ -4,7 +4,6 @@ * Eran Liberty, Extricom , eran.liberty@gmail.com */ -#include /* core U-Boot definitions */ #include #include diff --git a/drivers/fpga/stratixv.c b/drivers/fpga/stratixv.c index abae3b5b751..372f16d92d1 100644 --- a/drivers/fpga/stratixv.c +++ b/drivers/fpga/stratixv.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Stefan Roese */ -#include #include #include #include diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c index be58db54275..1957e8dcaca 100644 --- a/drivers/fpga/versalpl.c +++ b/drivers/fpga/versalpl.c @@ -4,7 +4,6 @@ * Siva Durga Prasad Paladugu > */ -#include #include #include #include diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index 3ded27f9b3f..8e2c12bb58b 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -14,7 +14,7 @@ #define LOG_CATEGORY UCLASS_FPGA -#include +#include #include #include #include diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 8170c3368ef..c46513226d9 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -11,13 +11,13 @@ * Xilinx FPGA support */ -#include #include #include #include #include #include #include +#include /* Local Static Functions */ static int xilinx_validate(xilinx_desc *desc, char *fn); diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index 2656f5fc5ec..2b62bbbe3cf 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index a2e3b305fa4..57467b4d975 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -6,10 +6,11 @@ * Joe Hershberger */ -#include +#include #include #include #include +#include #include #include #include diff --git a/drivers/fuzz/fuzzing_engine-uclass.c b/drivers/fuzz/fuzzing_engine-uclass.c index b16f1c4cfb7..08ce3ed2ec1 100644 --- a/drivers/fuzz/fuzzing_engine-uclass.c +++ b/drivers/fuzz/fuzzing_engine-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_FUZZING_ENGINE -#include #include #include diff --git a/drivers/fuzz/sandbox_fuzzing_engine.c b/drivers/fuzz/sandbox_fuzzing_engine.c index ebb938e5ba8..677402470ed 100644 --- a/drivers/fuzz/sandbox_fuzzing_engine.c +++ b/drivers/fuzz/sandbox_fuzzing_engine.c @@ -4,7 +4,6 @@ * Written by Andrew Scull */ -#include #include #include #include diff --git a/drivers/fwu-mdata/fwu-mdata-uclass.c b/drivers/fwu-mdata/fwu-mdata-uclass.c index 0a8edaaa418..bab7a7e80d1 100644 --- a/drivers/fwu-mdata/fwu-mdata-uclass.c +++ b/drivers/fwu-mdata/fwu-mdata-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_FWU_MDATA -#include #include #include #include diff --git a/drivers/gpio/74x164_gpio.c b/drivers/gpio/74x164_gpio.c index 7a7cfe86114..331428ccdb9 100644 --- a/drivers/gpio/74x164_gpio.c +++ b/drivers/gpio/74x164_gpio.c @@ -8,7 +8,6 @@ * */ -#include #include #include #include diff --git a/drivers/gpio/altera_pio.c b/drivers/gpio/altera_pio.c index edc5a8093b0..7ba1595e4ae 100644 --- a/drivers/gpio/altera_pio.c +++ b/drivers/gpio/altera_pio.c @@ -4,7 +4,6 @@ * Copyright (C) 2011 Missing Link Electronics * Joachim Foerster */ -#include #include #include #include diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c index f80f4afd24f..50a69815907 100644 --- a/drivers/gpio/at91_gpio.c +++ b/drivers/gpio/at91_gpio.c @@ -8,7 +8,6 @@ */ #include -#include #include #include #include diff --git a/drivers/gpio/atmel_pio4.c b/drivers/gpio/atmel_pio4.c index be1dd752bf7..65d064b46df 100644 --- a/drivers/gpio/atmel_pio4.c +++ b/drivers/gpio/atmel_pio4.c @@ -5,7 +5,6 @@ * Copyright (C) 2015 Atmel Corporation * Wenyou.Yang */ -#include #include #include #include diff --git a/drivers/gpio/axp_gpio.c b/drivers/gpio/axp_gpio.c index af6631697f5..6e632c8fc73 100644 --- a/drivers/gpio/axp_gpio.c +++ b/drivers/gpio/axp_gpio.c @@ -5,7 +5,6 @@ * X-Powers AXP Power Management ICs gpio driver */ -#include #include #include #include diff --git a/drivers/gpio/bcm2835_gpio.c b/drivers/gpio/bcm2835_gpio.c index 704a6fa7121..ccf84fdae11 100644 --- a/drivers/gpio/bcm2835_gpio.c +++ b/drivers/gpio/bcm2835_gpio.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/drivers/gpio/bcm6345_gpio.c b/drivers/gpio/bcm6345_gpio.c index e031f71a784..e76c84e806a 100644 --- a/drivers/gpio/bcm6345_gpio.c +++ b/drivers/gpio/bcm6345_gpio.c @@ -7,7 +7,6 @@ * Copyright (C) 2008-2011 Florian Fainelli */ -#include #include #include #include diff --git a/drivers/gpio/cortina_gpio.c b/drivers/gpio/cortina_gpio.c index 72ef523be96..e0ea14cce69 100644 --- a/drivers/gpio/cortina_gpio.c +++ b/drivers/gpio/cortina_gpio.c @@ -5,7 +5,6 @@ * GPIO Driver for Cortina Access CAxxxx Line of SoCs */ -#include #include #include #include diff --git a/drivers/gpio/da8xx_gpio.c b/drivers/gpio/da8xx_gpio.c index b310f2dbf65..1ccb9e69f15 100644 --- a/drivers/gpio/da8xx_gpio.c +++ b/drivers/gpio/da8xx_gpio.c @@ -6,7 +6,6 @@ * Laurence Withers */ -#include #include #include #include diff --git a/drivers/gpio/ftgpio010.c b/drivers/gpio/ftgpio010.c index 6c091d4fd87..4cb550a540c 100644 --- a/drivers/gpio/ftgpio010.c +++ b/drivers/gpio/ftgpio010.c @@ -3,7 +3,6 @@ * Faraday Technology's FTGPIO010 controller. */ -#include #include #include #include diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c index 1c3d18796b3..c5608f4a9df 100644 --- a/drivers/gpio/gpio-aspeed.c +++ b/drivers/gpio/gpio-aspeed.c @@ -6,7 +6,6 @@ * * Implementation extracted from the Linux kernel and adapted for u-boot. */ -#include #include #include diff --git a/drivers/gpio/gpio-fxl6408.c b/drivers/gpio/gpio-fxl6408.c index ca7aa14eeb2..c8d2dff5f7b 100644 --- a/drivers/gpio/gpio-fxl6408.c +++ b/drivers/gpio/gpio-fxl6408.c @@ -37,7 +37,6 @@ #include #include -#include #include #include #include diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c index 70778501232..d1a39938809 100644 --- a/drivers/gpio/gpio-rcar.c +++ b/drivers/gpio/gpio-rcar.c @@ -3,7 +3,6 @@ * Copyright (C) 2017 Marek Vasut */ -#include #include #include #include diff --git a/drivers/gpio/gpio-rza1.c b/drivers/gpio/gpio-rza1.c index f14be871e8d..8c3fe61b25f 100644 --- a/drivers/gpio/gpio-rza1.c +++ b/drivers/gpio/gpio-rza1.c @@ -3,7 +3,6 @@ * Copyright (C) 2019 Marek Vasut */ -#include #include #include #include diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 4234cd912c9..92ce68dd4a1 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_GPIO -#include #include #include #include diff --git a/drivers/gpio/gpio-uniphier.c b/drivers/gpio/gpio-uniphier.c index 61c705b5ac5..033fb4b60ee 100644 --- a/drivers/gpio/gpio-uniphier.c +++ b/drivers/gpio/gpio-uniphier.c @@ -4,7 +4,6 @@ * Author: Masahiro Yamada */ -#include #include #include #include diff --git a/drivers/gpio/gpio_slg7xl45106.c b/drivers/gpio/gpio_slg7xl45106.c index 4ad06c18b4b..a7c9ff53af7 100644 --- a/drivers/gpio/gpio_slg7xl45106.c +++ b/drivers/gpio/gpio_slg7xl45106.c @@ -5,7 +5,6 @@ * Copyright (C) 2021 Xilinx, Inc. */ -#include #include #include #include diff --git a/drivers/gpio/hi6220_gpio.c b/drivers/gpio/hi6220_gpio.c index e287c31b93f..7ceb5f424c9 100644 --- a/drivers/gpio/hi6220_gpio.c +++ b/drivers/gpio/hi6220_gpio.c @@ -4,7 +4,6 @@ * Peter Griffin */ -#include #include #include #include diff --git a/drivers/gpio/hsdk-creg-gpio.c b/drivers/gpio/hsdk-creg-gpio.c index 66f8441840b..734b31d3dc1 100644 --- a/drivers/gpio/hsdk-creg-gpio.c +++ b/drivers/gpio/hsdk-creg-gpio.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/gpio/imx_rgpio2p.c b/drivers/gpio/imx_rgpio2p.c index 3227a8d5b57..fc1d418315c 100644 --- a/drivers/gpio/imx_rgpio2p.c +++ b/drivers/gpio/imx_rgpio2p.c @@ -5,7 +5,6 @@ * RGPIO2P driver for the Freescale i.MX7ULP. */ -#include #include #include #include diff --git a/drivers/gpio/intel_broadwell_gpio.c b/drivers/gpio/intel_broadwell_gpio.c index 20af35de2cf..53ed0a3eed0 100644 --- a/drivers/gpio/intel_broadwell_gpio.c +++ b/drivers/gpio/intel_broadwell_gpio.c @@ -3,7 +3,6 @@ * Copyright (c) 2012 The Chromium OS Authors. */ -#include #include #include #include diff --git a/drivers/gpio/intel_gpio.c b/drivers/gpio/intel_gpio.c index 4a3ec6d6350..0ab6e8a90bc 100644 --- a/drivers/gpio/intel_gpio.c +++ b/drivers/gpio/intel_gpio.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_GPIO -#include #include #include #include diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c index 2ed0d0bea9a..096bc3b05bb 100644 --- a/drivers/gpio/intel_ich6_gpio.c +++ b/drivers/gpio/intel_ich6_gpio.c @@ -28,7 +28,6 @@ #define LOG_CATEGORY UCLASS_GPIO -#include #include #include #include diff --git a/drivers/gpio/iproc_gpio.c b/drivers/gpio/iproc_gpio.c index 7187d3257b9..8688f12e43c 100644 --- a/drivers/gpio/iproc_gpio.c +++ b/drivers/gpio/iproc_gpio.c @@ -3,7 +3,6 @@ * Copyright (C) 2020 Broadcom */ -#include #include #include #include diff --git a/drivers/gpio/kw_gpio.c b/drivers/gpio/kw_gpio.c index a15769793f1..e183f5594b5 100644 --- a/drivers/gpio/kw_gpio.c +++ b/drivers/gpio/kw_gpio.c @@ -12,7 +12,6 @@ * Dieter Kiermaier dk-arm-linux@gmx.de */ -#include #include #include #include diff --git a/drivers/gpio/lpc32xx_gpio.c b/drivers/gpio/lpc32xx_gpio.c index de66c765d11..2b537e007ba 100644 --- a/drivers/gpio/lpc32xx_gpio.c +++ b/drivers/gpio/lpc32xx_gpio.c @@ -6,7 +6,6 @@ * Written-by: Albert ARIBAUD */ -#include #include #include #include diff --git a/drivers/gpio/max7320_gpio.c b/drivers/gpio/max7320_gpio.c index 647aed907b4..f733cc924e5 100644 --- a/drivers/gpio/max7320_gpio.c +++ b/drivers/gpio/max7320_gpio.c @@ -7,7 +7,6 @@ * */ -#include #include #include #include diff --git a/drivers/gpio/mcp230xx_gpio.c b/drivers/gpio/mcp230xx_gpio.c index df99fde5660..42e7fe9d474 100644 --- a/drivers/gpio/mcp230xx_gpio.c +++ b/drivers/gpio/mcp230xx_gpio.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY UCLASS_GPIO -#include #include #include #include diff --git a/drivers/gpio/mpc83xx_spisel_boot.c b/drivers/gpio/mpc83xx_spisel_boot.c index fd26a36a0f9..2be8c73ae3d 100644 --- a/drivers/gpio/mpc83xx_spisel_boot.c +++ b/drivers/gpio/mpc83xx_spisel_boot.c @@ -5,7 +5,6 @@ * GPIO driver to set/clear SPISEL_BOOT pin on mpc83xx. */ -#include #include #include #include diff --git a/drivers/gpio/mpc8xx_gpio.c b/drivers/gpio/mpc8xx_gpio.c index 2f653465331..e2b12f8b56c 100644 --- a/drivers/gpio/mpc8xx_gpio.c +++ b/drivers/gpio/mpc8xx_gpio.c @@ -10,7 +10,6 @@ * Copyright 2010 eXMeritus, A Boeing Company */ -#include #include #include #include diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c index f7ffd8926ad..e9bd38f162c 100644 --- a/drivers/gpio/mpc8xxx_gpio.c +++ b/drivers/gpio/mpc8xxx_gpio.c @@ -9,7 +9,6 @@ * Copyright 2020-2021 NXP */ -#include #include #include #include diff --git a/drivers/gpio/mscc_sgpio.c b/drivers/gpio/mscc_sgpio.c index c97e44005ee..5a40304f1f9 100644 --- a/drivers/gpio/mscc_sgpio.c +++ b/drivers/gpio/mscc_sgpio.c @@ -7,7 +7,6 @@ * Copyright (c) 2018 Microsemi Corporation */ -#include #include #include #include diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c index f5d9ab54e81..2fb266f1285 100644 --- a/drivers/gpio/msm_gpio.c +++ b/drivers/gpio/msm_gpio.c @@ -5,7 +5,6 @@ * (C) Copyright 2015 Mateusz Kulikowski */ -#include #include #include #include diff --git a/drivers/gpio/mt7621_gpio.c b/drivers/gpio/mt7621_gpio.c index 43bb4df4da7..63a202310a5 100644 --- a/drivers/gpio/mt7621_gpio.c +++ b/drivers/gpio/mt7621_gpio.c @@ -7,7 +7,6 @@ * Copyright (C) 2013 John Crispin */ -#include #include #include #include diff --git a/drivers/gpio/mvebu_gpio.c b/drivers/gpio/mvebu_gpio.c index f706a6dfa4f..0d82380dde4 100644 --- a/drivers/gpio/mvebu_gpio.c +++ b/drivers/gpio/mvebu_gpio.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Stefan Roese */ -#include #include #include #include diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index 1dec4e35e0a..cac6b32b279 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -6,7 +6,6 @@ * Copyright (C) 2011 * Stefano Babic, DENX Software Engineering, */ -#include #include #include #include diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c index 1356f89ac2f..80910c9ec4c 100644 --- a/drivers/gpio/mxs_gpio.c +++ b/drivers/gpio/mxs_gpio.c @@ -6,7 +6,6 @@ * on behalf of DENX Software Engineering GmbH */ -#include #include #include #include diff --git a/drivers/gpio/nmk_gpio.c b/drivers/gpio/nmk_gpio.c index e1bb41b196c..c2716e71763 100644 --- a/drivers/gpio/nmk_gpio.c +++ b/drivers/gpio/nmk_gpio.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* Copyright (C) 2019 Stephan Gerhold */ -#include #include #include #include diff --git a/drivers/gpio/npcm_gpio.c b/drivers/gpio/npcm_gpio.c index 98e5dc79c1c..da3b3ffbc92 100644 --- a/drivers/gpio/npcm_gpio.c +++ b/drivers/gpio/npcm_gpio.c @@ -3,7 +3,6 @@ * Copyright (c) 2022 Nuvoton Technology Corp. */ -#include #include #include #include diff --git a/drivers/gpio/nx_gpio.c b/drivers/gpio/nx_gpio.c index e2565d70953..741b2ff7f17 100644 --- a/drivers/gpio/nx_gpio.c +++ b/drivers/gpio/nx_gpio.c @@ -4,7 +4,6 @@ * DeokJin, Lee */ -#include #include #include #include diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c index 50c4f75ddf5..1aceafcdf58 100644 --- a/drivers/gpio/omap_gpio.c +++ b/drivers/gpio/omap_gpio.c @@ -17,7 +17,6 @@ * Copyright (C) 2003-2005 Nokia Corporation * Written by Juha Yrjölä */ -#include #include #include #include diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c index b5ed35256ee..fc4dcf9f986 100644 --- a/drivers/gpio/pca953x.c +++ b/drivers/gpio/pca953x.c @@ -8,10 +8,11 @@ * pca9539, etc) */ -#include +#include #include #include #include +#include /* Default to an address that hopefully won't corrupt other i2c devices */ #ifndef CFG_SYS_I2C_PCA953X_ADDR diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c index b0c66d18317..80ebaadb3e4 100644 --- a/drivers/gpio/pca953x_gpio.c +++ b/drivers/gpio/pca953x_gpio.c @@ -18,7 +18,6 @@ * 2. Support Polarity Inversion */ -#include #include #include #include diff --git a/drivers/gpio/pcf8575_gpio.c b/drivers/gpio/pcf8575_gpio.c index f38e215c4d6..10ae86ec5d4 100644 --- a/drivers/gpio/pcf8575_gpio.c +++ b/drivers/gpio/pcf8575_gpio.c @@ -17,7 +17,6 @@ * */ -#include #include #include #include diff --git a/drivers/gpio/pic32_gpio.c b/drivers/gpio/pic32_gpio.c index 975a2af3ccb..d8edfefb2d7 100644 --- a/drivers/gpio/pic32_gpio.c +++ b/drivers/gpio/pic32_gpio.c @@ -4,7 +4,6 @@ * Purna Chandra Mandal */ -#include #include #include #include diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c index 0dd3434e9e0..80fee841ee3 100644 --- a/drivers/gpio/qcom_pmic_gpio.c +++ b/drivers/gpio/qcom_pmic_gpio.c @@ -5,7 +5,6 @@ * (C) Copyright 2015 Mateusz Kulikowski */ -#include #include #include #include diff --git a/drivers/gpio/qe_gpio.c b/drivers/gpio/qe_gpio.c index 16e8d1eae6e..ac6e68299e0 100644 --- a/drivers/gpio/qe_gpio.c +++ b/drivers/gpio/qe_gpio.c @@ -4,7 +4,6 @@ * Christophe Leroy */ -#include #include #include #include diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c index 2e901ac5c73..24ba12dd820 100644 --- a/drivers/gpio/rk_gpio.c +++ b/drivers/gpio/rk_gpio.c @@ -6,7 +6,6 @@ * Peter, Software Engineering, . */ -#include #include #include #include diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c index 06ed585f3d6..83e65aa4aec 100644 --- a/drivers/gpio/s5p_gpio.c +++ b/drivers/gpio/s5p_gpio.c @@ -4,7 +4,6 @@ * Minkyu Kang */ -#include #include #include #include diff --git a/drivers/gpio/sandbox.c b/drivers/gpio/sandbox.c index 305f9a6ff62..f5be2781443 100644 --- a/drivers/gpio/sandbox.c +++ b/drivers/gpio/sandbox.c @@ -3,7 +3,6 @@ * Copyright (c) 2011 The Chromium OS Authors. */ -#include #include #include #include diff --git a/drivers/gpio/sandbox_test.c b/drivers/gpio/sandbox_test.c index c76e1997419..4699a976252 100644 --- a/drivers/gpio/sandbox_test.c +++ b/drivers/gpio/sandbox_test.c @@ -5,7 +5,6 @@ * Copyright 2021 Google LLC */ -#include #include #include diff --git a/drivers/gpio/sh_pfc.c b/drivers/gpio/sh_pfc.c index 2495d6c1c15..9f6051c1c4d 100644 --- a/drivers/gpio/sh_pfc.c +++ b/drivers/gpio/sh_pfc.c @@ -9,7 +9,6 @@ * for more details. */ -#include #include #include #include diff --git a/drivers/gpio/sifive-gpio.c b/drivers/gpio/sifive-gpio.c index 151f484e8fd..90f59120ecd 100644 --- a/drivers/gpio/sifive-gpio.c +++ b/drivers/gpio/sifive-gpio.c @@ -5,7 +5,6 @@ * Copyright (C) 2019 SiFive, Inc. */ -#include #include #include #include diff --git a/drivers/gpio/sl28cpld-gpio.c b/drivers/gpio/sl28cpld-gpio.c index 700fc3df298..e85f9260ec3 100644 --- a/drivers/gpio/sl28cpld-gpio.c +++ b/drivers/gpio/sl28cpld-gpio.c @@ -5,7 +5,6 @@ * Copyright (c) 2021 Michael Walle */ -#include #include #include #include diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c index 7a2ca91c769..b8eb55465d3 100644 --- a/drivers/gpio/stm32_gpio.c +++ b/drivers/gpio/stm32_gpio.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_GPIO -#include #include #include #include diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c index e4463a223f7..5e86474d3db 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -9,7 +9,6 @@ * Tom Cubie */ -#include #include #include #include diff --git a/drivers/gpio/tca642x.c b/drivers/gpio/tca642x.c index b07496e6e49..1d45b500746 100644 --- a/drivers/gpio/tca642x.c +++ b/drivers/gpio/tca642x.c @@ -20,7 +20,7 @@ * MA 02111-1307 USA */ -#include +#include #include #include #include diff --git a/drivers/gpio/tegra186_gpio.c b/drivers/gpio/tegra186_gpio.c index 94a20d143e1..01b8245c8d5 100644 --- a/drivers/gpio/tegra186_gpio.c +++ b/drivers/gpio/tegra186_gpio.c @@ -4,7 +4,6 @@ * (based on tegra_gpio.c) */ -#include #include #include #include diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c index 55105f2802c..0c40d36c41e 100644 --- a/drivers/gpio/tegra_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -10,7 +10,6 @@ * Tom Warren (twarren@nvidia.com) */ -#include #include #include #include diff --git a/drivers/gpio/vybrid_gpio.c b/drivers/gpio/vybrid_gpio.c index 339392dcd35..5b4bba96da7 100644 --- a/drivers/gpio/vybrid_gpio.c +++ b/drivers/gpio/vybrid_gpio.c @@ -4,7 +4,6 @@ * Bhuvanchandra DV, Toradex, Inc. */ -#include #include #include #include diff --git a/drivers/gpio/xilinx_gpio.c b/drivers/gpio/xilinx_gpio.c index fa8d630b465..c0a92378b03 100644 --- a/drivers/gpio/xilinx_gpio.c +++ b/drivers/gpio/xilinx_gpio.c @@ -3,7 +3,6 @@ * Copyright (c) 2013 - 2018 Xilinx, Michal Simek */ -#include #include #include #include diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c index 71a56127c0a..7db58c70663 100644 --- a/drivers/gpio/zynq_gpio.c +++ b/drivers/gpio/zynq_gpio.c @@ -8,7 +8,6 @@ * Copyright (C) 2009 - 2014 Xilinx, Inc. */ -#include #include #include #include diff --git a/drivers/gpio/zynqmp_gpio_modepin.c b/drivers/gpio/zynqmp_gpio_modepin.c index e9565ff5430..8aaffaf37b3 100644 --- a/drivers/gpio/zynqmp_gpio_modepin.c +++ b/drivers/gpio/zynqmp_gpio_modepin.c @@ -5,7 +5,6 @@ * Copyright (C) 2021 Xilinx, Inc. */ -#include #include #include #include diff --git a/drivers/hwspinlock/hwspinlock-uclass.c b/drivers/hwspinlock/hwspinlock-uclass.c index e9a4d7f9fbb..ea93efc97df 100644 --- a/drivers/hwspinlock/hwspinlock-uclass.c +++ b/drivers/hwspinlock/hwspinlock-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_HWSPINLOCK -#include #include #include #include diff --git a/drivers/hwspinlock/sandbox_hwspinlock.c b/drivers/hwspinlock/sandbox_hwspinlock.c index be920f5f99d..fcda55517e1 100644 --- a/drivers/hwspinlock/sandbox_hwspinlock.c +++ b/drivers/hwspinlock/sandbox_hwspinlock.c @@ -3,7 +3,6 @@ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved */ -#include #include #include #include diff --git a/drivers/hwspinlock/stm32_hwspinlock.c b/drivers/hwspinlock/stm32_hwspinlock.c index 346b138e98f..5273b9bfed8 100644 --- a/drivers/hwspinlock/stm32_hwspinlock.c +++ b/drivers/hwspinlock/stm32_hwspinlock.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_HWSPINLOCK -#include #include #include #include diff --git a/drivers/i2c/acpi_i2c.c b/drivers/i2c/acpi_i2c.c index 142f41178c1..82cb5db5cc8 100644 --- a/drivers/i2c/acpi_i2c.c +++ b/drivers/i2c/acpi_i2c.c @@ -3,7 +3,6 @@ * Copyright 2019 Google LLC */ -#include #include #include #include diff --git a/drivers/i2c/ast2600_i2c.c b/drivers/i2c/ast2600_i2c.c index e566b01feac..9d1d70670b9 100644 --- a/drivers/i2c/ast2600_i2c.c +++ b/drivers/i2c/ast2600_i2c.c @@ -2,7 +2,6 @@ /* * Copyright ASPEED Technology Inc. */ -#include #include #include #include diff --git a/drivers/i2c/ast_i2c.c b/drivers/i2c/ast_i2c.c index 1c1d5566dad..02ee406bbd7 100644 --- a/drivers/i2c/ast_i2c.c +++ b/drivers/i2c/ast_i2c.c @@ -5,7 +5,6 @@ * Copyright 2017 Google, Inc. */ -#include #include #include #include diff --git a/drivers/i2c/at91_i2c.c b/drivers/i2c/at91_i2c.c index b7a25885e66..cfae36c74d1 100644 --- a/drivers/i2c/at91_i2c.c +++ b/drivers/i2c/at91_i2c.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/i2c/cros_ec_ldo.c b/drivers/i2c/cros_ec_ldo.c index c593540ac13..dfe823c142c 100644 --- a/drivers/i2c/cros_ec_ldo.c +++ b/drivers/i2c/cros_ec_ldo.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/i2c/cros_ec_tunnel.c b/drivers/i2c/cros_ec_tunnel.c index 75828b6e7c2..2d610e0a2aa 100644 --- a/drivers/i2c/cros_ec_tunnel.c +++ b/drivers/i2c/cros_ec_tunnel.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/i2c/davinci_i2c.c b/drivers/i2c/davinci_i2c.c index 25ef937dc0b..39132747208 100644 --- a/drivers/i2c/davinci_i2c.c +++ b/drivers/i2c/davinci_i2c.c @@ -11,7 +11,7 @@ * Please see doc/driver-model/i2c-howto.rst for instructions. */ -#include +#include #include #include #include diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index 29cf63375c7..e8c1623d41f 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -4,7 +4,6 @@ * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com. */ -#include #include #include #include diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c index 28495a3f428..11c98672265 100644 --- a/drivers/i2c/designware_i2c_pci.c +++ b/drivers/i2c/designware_i2c_pci.c @@ -5,7 +5,6 @@ * Copyright 2019 Google Inc */ -#include #include #include #include diff --git a/drivers/i2c/exynos_hs_i2c.c b/drivers/i2c/exynos_hs_i2c.c index a7349e06cfd..9a364fdae37 100644 --- a/drivers/i2c/exynos_hs_i2c.c +++ b/drivers/i2c/exynos_hs_i2c.c @@ -6,7 +6,6 @@ * David Mueller, ELSOFT AG, d.mueller@elsoft.ch */ -#include #include #include #include diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index d9d8ee81d2e..bac14fb2f42 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -6,7 +6,7 @@ * Changes for multibus/multiadapter I2C support. */ -#include +#include #include #include /* Functional interface */ #include diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c index 935b2ac6377..3f7cf8533ec 100644 --- a/drivers/i2c/i2c-cdns.c +++ b/drivers/i2c/i2c-cdns.c @@ -7,7 +7,6 @@ * with added driver-model support and code cleanup. */ -#include #include #include #include diff --git a/drivers/i2c/i2c-cortina.c b/drivers/i2c/i2c-cortina.c index 960ae8c700f..96f957164c1 100644 --- a/drivers/i2c/i2c-cortina.c +++ b/drivers/i2c/i2c-cortina.c @@ -4,12 +4,12 @@ * Arthur Li, Cortina Access, arthur.li@cortina-access.com. */ -#include #include #include #include #include #include +#include #include "i2c-cortina.h" static void set_speed(struct i2c_regs *regs, int i2c_spd) diff --git a/drivers/i2c/i2c-emul-uclass.c b/drivers/i2c/i2c-emul-uclass.c index d421ddfcbe2..0954d53847e 100644 --- a/drivers/i2c/i2c-emul-uclass.c +++ b/drivers/i2c/i2c-emul-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_I2C_EMUL -#include #include #include #include diff --git a/drivers/i2c/i2c-gpio.c b/drivers/i2c/i2c-gpio.c index 5fc3cfe42ef..e0a575fb4a4 100644 --- a/drivers/i2c/i2c-gpio.c +++ b/drivers/i2c/i2c-gpio.c @@ -5,7 +5,6 @@ * This file is based on: drivers/i2c/soft-i2c.c, * with added driver-model support and code cleanup. */ -#include #include #include #include diff --git a/drivers/i2c/i2c-microchip.c b/drivers/i2c/i2c-microchip.c index d453e243d6f..788747879a2 100644 --- a/drivers/i2c/i2c-microchip.c +++ b/drivers/i2c/i2c-microchip.c @@ -6,7 +6,6 @@ * Padmarao Begari * Conor Dooley */ -#include #include #include #include diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c index 98f95859f3b..380a9f8f3ad 100644 --- a/drivers/i2c/i2c-uclass.c +++ b/drivers/i2c/i2c-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_I2C -#include #include #include #include diff --git a/drivers/i2c/i2c-versatile.c b/drivers/i2c/i2c-versatile.c index 0a1a85dfc28..a8f0a170f79 100644 --- a/drivers/i2c/i2c-versatile.c +++ b/drivers/i2c/i2c-versatile.c @@ -5,7 +5,6 @@ * */ -#include #include #include #include diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c index fe0cd75d94a..7c43a5546d3 100644 --- a/drivers/i2c/i2c_core.c +++ b/drivers/i2c/i2c_core.c @@ -7,7 +7,7 @@ * * Multibus/multiadapter I2C core functions (wrappers) */ -#include +#include #include #include #include diff --git a/drivers/i2c/ihs_i2c.c b/drivers/i2c/ihs_i2c.c index d715714638f..dc88cd19167 100644 --- a/drivers/i2c/ihs_i2c.c +++ b/drivers/i2c/ihs_i2c.c @@ -4,7 +4,6 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */ -#include #include #include #include diff --git a/drivers/i2c/imx_lpi2c.c b/drivers/i2c/imx_lpi2c.c index ad9293c92e1..6c0d8eb5f4f 100644 --- a/drivers/i2c/imx_lpi2c.c +++ b/drivers/i2c/imx_lpi2c.c @@ -3,7 +3,6 @@ * Copyright 2016 Freescale Semiconductors, Inc. */ -#include #include #include #include diff --git a/drivers/i2c/intel_i2c.c b/drivers/i2c/intel_i2c.c index 4fc6f1a11a7..d8ceea10cda 100644 --- a/drivers/i2c/intel_i2c.c +++ b/drivers/i2c/intel_i2c.c @@ -7,11 +7,11 @@ * Copyright (C) 2016 Stefan Roese */ -#include #include #include #include #include +#include #include /* PCI Configuration Space (D31:F3): SMBus */ diff --git a/drivers/i2c/iproc_i2c.c b/drivers/i2c/iproc_i2c.c index 39af49c4ec5..6570f64fe77 100644 --- a/drivers/i2c/iproc_i2c.c +++ b/drivers/i2c/iproc_i2c.c @@ -6,7 +6,6 @@ #include #include -#include #include #include #include diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c index 496f4feec56..a4e42e64a9b 100644 --- a/drivers/i2c/lpc32xx_i2c.c +++ b/drivers/i2c/lpc32xx_i2c.c @@ -6,7 +6,7 @@ * Written-by: Albert ARIBAUD - 3ADEV */ -#include +#include #include #include #include diff --git a/drivers/i2c/meson_i2c.c b/drivers/i2c/meson_i2c.c index 434e3461b1d..19f1b6b0819 100644 --- a/drivers/i2c/meson_i2c.c +++ b/drivers/i2c/meson_i2c.c @@ -2,7 +2,6 @@ /* * (C) Copyright 2017 - Beniamino Galvani */ -#include #include #include #include diff --git a/drivers/i2c/muxes/i2c-arb-gpio-challenge.c b/drivers/i2c/muxes/i2c-arb-gpio-challenge.c index ad730e0e79f..a83d7cb0829 100644 --- a/drivers/i2c/muxes/i2c-arb-gpio-challenge.c +++ b/drivers/i2c/muxes/i2c-arb-gpio-challenge.c @@ -4,12 +4,12 @@ * Written by Simon Glass */ -#include #include #include #include #include #include +#include #include #include #include diff --git a/drivers/i2c/muxes/i2c-mux-gpio.c b/drivers/i2c/muxes/i2c-mux-gpio.c index 4ca206115f8..f212bd1f983 100644 --- a/drivers/i2c/muxes/i2c-mux-gpio.c +++ b/drivers/i2c/muxes/i2c-mux-gpio.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/i2c/muxes/i2c-mux-uclass.c b/drivers/i2c/muxes/i2c-mux-uclass.c index a5d1bb0576d..d1999d21feb 100644 --- a/drivers/i2c/muxes/i2c-mux-uclass.c +++ b/drivers/i2c/muxes/i2c-mux-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_I2C_MUX -#include #include #include #include diff --git a/drivers/i2c/muxes/pca954x.c b/drivers/i2c/muxes/pca954x.c index 0034dfbf6da..b4e3e16a976 100644 --- a/drivers/i2c/muxes/pca954x.c +++ b/drivers/i2c/muxes/pca954x.c @@ -5,7 +5,6 @@ * Written by Michal Simek */ -#include #include #include #include diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c index 5bc9cd7b295..949cc45d308 100644 --- a/drivers/i2c/mv_i2c.c +++ b/drivers/i2c/mv_i2c.c @@ -16,7 +16,6 @@ * Murray.Jensen@cmst.csiro.au, 27-Jan-01. */ -#include #include #include #include diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index c38330f758a..44e8e191b03 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -7,7 +7,7 @@ * Copyright (c) 2010 Albert Aribaud. */ -#include +#include #include #include #include diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index d501133a0c8..0acdaf7e743 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -14,7 +14,7 @@ * */ -#include +#include #include #include #include diff --git a/drivers/i2c/nx_i2c.c b/drivers/i2c/nx_i2c.c index 07cda0fa679..8562dd82bd6 100644 --- a/drivers/i2c/nx_i2c.c +++ b/drivers/i2c/nx_i2c.c @@ -1,8 +1,8 @@ -#include #include #include #include #include +#include #include #include #include diff --git a/drivers/i2c/ocores_i2c.c b/drivers/i2c/ocores_i2c.c index fff85118d0d..cf714d22ee4 100644 --- a/drivers/i2c/ocores_i2c.c +++ b/drivers/i2c/ocores_i2c.c @@ -12,7 +12,6 @@ * Andreas Larsson */ -#include #include #include #include diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index 6fc9d1eba9d..ebe472e20cd 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -38,7 +38,6 @@ * */ -#include #include #include #include diff --git a/drivers/i2c/qup_i2c.c b/drivers/i2c/qup_i2c.c index 5ae3cccd4ac..26707d63980 100644 --- a/drivers/i2c/qup_i2c.c +++ b/drivers/i2c/qup_i2c.c @@ -9,7 +9,6 @@ #include #include -#include #include #include #include diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c index ff9a2d80dda..f0f9b2afacf 100644 --- a/drivers/i2c/rcar_i2c.c +++ b/drivers/i2c/rcar_i2c.c @@ -11,7 +11,6 @@ * Kuninori Morimoto */ -#include #include #include #include diff --git a/drivers/i2c/rcar_iic.c b/drivers/i2c/rcar_iic.c index f0e50914c68..2aa0f5fbfae 100644 --- a/drivers/i2c/rcar_iic.c +++ b/drivers/i2c/rcar_iic.c @@ -9,7 +9,6 @@ * Copyright (C) 2011, 2013 Nobuhiro Iwamatsu */ -#include #include #include #include diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c index 9927af94a80..fa167268ae7 100644 --- a/drivers/i2c/rk_i2c.c +++ b/drivers/i2c/rk_i2c.c @@ -6,7 +6,6 @@ * Peter, Software Engineering, . */ -#include #include #include #include diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index 505e20bc61c..72d2ab0f73d 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -4,10 +4,10 @@ * David Mueller, ELSOFT AG, d.mueller@elsoft.ch */ -#include #include #include #include +#include #if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5) #include #include diff --git a/drivers/i2c/sandbox_i2c.c b/drivers/i2c/sandbox_i2c.c index c99e6de9332..74bb5e93397 100644 --- a/drivers/i2c/sandbox_i2c.c +++ b/drivers/i2c/sandbox_i2c.c @@ -5,7 +5,6 @@ * Copyright (c) 2014 Google, Inc */ -#include #include #include #include diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index 3335d9482a2..ab816101dea 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -7,7 +7,6 @@ * Please see doc/driver-model/i2c-howto.rst for instructions. */ -#include #include #include #include diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index ed8ba47de45..1f2afc65e8b 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -15,7 +15,7 @@ * Please see doc/driver-model/i2c-howto.rst for instructions. */ -#include +#include #if defined(CONFIG_AT91FAMILY) #include #include diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c index f42e08a6418..3f51b1dd1db 100644 --- a/drivers/i2c/stm32f7_i2c.c +++ b/drivers/i2c/stm32f7_i2c.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_I2C -#include #include #include #include diff --git a/drivers/i2c/sun6i_p2wi.c b/drivers/i2c/sun6i_p2wi.c index b8e07a533ca..c927c0edf25 100644 --- a/drivers/i2c/sun6i_p2wi.c +++ b/drivers/i2c/sun6i_p2wi.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/drivers/i2c/sun8i_rsb.c b/drivers/i2c/sun8i_rsb.c index f36f2c7afac..2197f180566 100644 --- a/drivers/i2c/sun8i_rsb.c +++ b/drivers/i2c/sun8i_rsb.c @@ -10,7 +10,6 @@ #include #include -#include #include #include #include diff --git a/drivers/i2c/tegra186_bpmp_i2c.c b/drivers/i2c/tegra186_bpmp_i2c.c index 588f6bdcc4b..d30eb523122 100644 --- a/drivers/i2c/tegra186_bpmp_i2c.c +++ b/drivers/i2c/tegra186_bpmp_i2c.c @@ -3,7 +3,6 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ -#include #include #include #include diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c index 57d77d56ea5..3c324bd2663 100644 --- a/drivers/i2c/tegra_i2c.c +++ b/drivers/i2c/tegra_i2c.c @@ -5,7 +5,6 @@ * NVIDIA Corporation */ -#include #include #include #include diff --git a/drivers/i2c/xilinx_xiic.c b/drivers/i2c/xilinx_xiic.c index 72199a62b2d..056024e350f 100644 --- a/drivers/i2c/xilinx_xiic.c +++ b/drivers/i2c/xilinx_xiic.c @@ -9,7 +9,6 @@ * Copyright (c) 2009-2010 Intel Corporation */ -#include #include #include #include diff --git a/drivers/input/apple_spi_kbd.c b/drivers/input/apple_spi_kbd.c index 7cf12f453a3..5b30cec2dcb 100644 --- a/drivers/input/apple_spi_kbd.c +++ b/drivers/input/apple_spi_kbd.c @@ -3,7 +3,6 @@ * Copyright (C) 2021 Mark Kettenis */ -#include #include #include #include diff --git a/drivers/input/button_kbd.c b/drivers/input/button_kbd.c index c73d3b18be9..0a917ac8b99 100644 --- a/drivers/input/button_kbd.c +++ b/drivers/input/button_kbd.c @@ -4,7 +4,6 @@ */ #include -#include #include #include #include diff --git a/drivers/input/cros_ec_keyb.c b/drivers/input/cros_ec_keyb.c index c4853463739..0917ee20fed 100644 --- a/drivers/input/cros_ec_keyb.c +++ b/drivers/input/cros_ec_keyb.c @@ -5,7 +5,6 @@ * Copyright (c) 2012 The Chromium OS Authors. */ -#include #include #include #include diff --git a/drivers/input/i8042.c b/drivers/input/i8042.c index e6070ca0152..9bf21053cf0 100644 --- a/drivers/input/i8042.c +++ b/drivers/input/i8042.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_KEYBOARD -#include #include #include #include diff --git a/drivers/input/input.c b/drivers/input/input.c index 8a6506e7c6f..3f146fb07e6 100644 --- a/drivers/input/input.c +++ b/drivers/input/input.c @@ -6,13 +6,13 @@ * (C) Copyright 2004 DENX Software Engineering, Wolfgang Denk, wd@denx.de */ -#include #include #include #include #include #include #include +#include #include #ifdef CONFIG_DM_KEYBOARD #include diff --git a/drivers/input/key_matrix.c b/drivers/input/key_matrix.c index e2fb2e17078..2e631660c88 100644 --- a/drivers/input/key_matrix.c +++ b/drivers/input/key_matrix.c @@ -6,7 +6,6 @@ * (C) Copyright 2004 DENX Software Engineering, Wolfgang Denk, wd@denx.de */ -#include #include #include #include diff --git a/drivers/input/keyboard-uclass.c b/drivers/input/keyboard-uclass.c index aefc8e825e2..df9ee8f7d65 100644 --- a/drivers/input/keyboard-uclass.c +++ b/drivers/input/keyboard-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_KEYBOARD -#include #include #include #include diff --git a/drivers/input/tegra-kbc.c b/drivers/input/tegra-kbc.c index d4741a76663..fc13975d4f0 100644 --- a/drivers/input/tegra-kbc.c +++ b/drivers/input/tegra-kbc.c @@ -4,7 +4,6 @@ * NVIDIA Corporation */ -#include #include #include #include @@ -13,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/iommu/apple_dart.c b/drivers/iommu/apple_dart.c index 6ecd84303bc..9327dea1e3b 100644 --- a/drivers/iommu/apple_dart.c +++ b/drivers/iommu/apple_dart.c @@ -3,7 +3,6 @@ * Copyright (C) 2021 Mark Kettenis */ -#include #include #include #include diff --git a/drivers/iommu/iommu-uclass.c b/drivers/iommu/iommu-uclass.c index dff3239cccb..bb31cd519d2 100644 --- a/drivers/iommu/iommu-uclass.c +++ b/drivers/iommu/iommu-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_IOMMU -#include #include #include #include diff --git a/drivers/iommu/sandbox_iommu.c b/drivers/iommu/sandbox_iommu.c index 6ceb7fd5ec3..e37976f86f0 100644 --- a/drivers/iommu/sandbox_iommu.c +++ b/drivers/iommu/sandbox_iommu.c @@ -3,7 +3,6 @@ * Copyright (C) 2021 Mark Kettenis */ -#include #include #include #include diff --git a/drivers/led/led-uclass.c b/drivers/led/led-uclass.c index a4be56fc258..f37bf6a1550 100644 --- a/drivers/led/led-uclass.c +++ b/drivers/led/led-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_LED -#include #include #include #include diff --git a/drivers/led/led_bcm6328.c b/drivers/led/led_bcm6328.c index f59a92fb1fd..dcc5741195c 100644 --- a/drivers/led/led_bcm6328.c +++ b/drivers/led/led_bcm6328.c @@ -3,7 +3,6 @@ * Copyright (C) 2017 Álvaro Fernández Rojas */ -#include #include #include #include diff --git a/drivers/led/led_bcm6358.c b/drivers/led/led_bcm6358.c index 25aa3994d0e..b1373ab7426 100644 --- a/drivers/led/led_bcm6358.c +++ b/drivers/led/led_bcm6358.c @@ -3,7 +3,6 @@ * Copyright (C) 2017 Álvaro Fernández Rojas */ -#include #include #include #include diff --git a/drivers/led/led_bcm6753.c b/drivers/led/led_bcm6753.c index 2466d930116..170caf7bdca 100644 --- a/drivers/led/led_bcm6753.c +++ b/drivers/led/led_bcm6753.c @@ -6,7 +6,6 @@ * drivers/led/led_bcm6858.c */ -#include #include #include #include diff --git a/drivers/led/led_bcm6858.c b/drivers/led/led_bcm6858.c index 397dc0d8693..a6efdcf6405 100644 --- a/drivers/led/led_bcm6858.c +++ b/drivers/led/led_bcm6858.c @@ -7,7 +7,6 @@ * drivers/led/led_bcm6358.c */ -#include #include #include #include diff --git a/drivers/led/led_cortina.c b/drivers/led/led_cortina.c index bcbe78d632a..2d3ad323d33 100644 --- a/drivers/led/led_cortina.c +++ b/drivers/led/led_cortina.c @@ -6,7 +6,6 @@ * */ -#include #include #include #include diff --git a/drivers/led/led_gpio.c b/drivers/led/led_gpio.c index 71421de628c..ce22fb49f2a 100644 --- a/drivers/led/led_gpio.c +++ b/drivers/led/led_gpio.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/led/led_pwm.c b/drivers/led/led_pwm.c index ae6de3087ab..15dd836509b 100644 --- a/drivers/led/led_pwm.c +++ b/drivers/led/led_pwm.c @@ -4,7 +4,6 @@ * Author: Ivan Vozvakhov */ -#include #include #include #include diff --git a/drivers/mailbox/apple-mbox.c b/drivers/mailbox/apple-mbox.c index 30c8e2f03fa..2ee49734f40 100644 --- a/drivers/mailbox/apple-mbox.c +++ b/drivers/mailbox/apple-mbox.c @@ -3,7 +3,6 @@ * Copyright (C) 2021 Mark Kettenis */ -#include #include #include #include diff --git a/drivers/mailbox/k3-sec-proxy.c b/drivers/mailbox/k3-sec-proxy.c index 05f6b1795d6..5eafe46fd4d 100644 --- a/drivers/mailbox/k3-sec-proxy.c +++ b/drivers/mailbox/k3-sec-proxy.c @@ -6,7 +6,6 @@ * Lokesh Vutla */ -#include #include #include #include diff --git a/drivers/mailbox/mailbox-uclass.c b/drivers/mailbox/mailbox-uclass.c index 85ba8c5fd99..4bf4987ce0a 100644 --- a/drivers/mailbox/mailbox-uclass.c +++ b/drivers/mailbox/mailbox-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_MAILBOX -#include #include #include #include diff --git a/drivers/mailbox/sandbox-mbox-test.c b/drivers/mailbox/sandbox-mbox-test.c index ffd4674d1ef..a2cfde2f62d 100644 --- a/drivers/mailbox/sandbox-mbox-test.c +++ b/drivers/mailbox/sandbox-mbox-test.c @@ -3,7 +3,6 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ -#include #include #include #include diff --git a/drivers/mailbox/sandbox-mbox.c b/drivers/mailbox/sandbox-mbox.c index 87d38de0cb6..87e06e492fe 100644 --- a/drivers/mailbox/sandbox-mbox.c +++ b/drivers/mailbox/sandbox-mbox.c @@ -3,7 +3,6 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ -#include #include #include #include diff --git a/drivers/mailbox/stm32-ipcc.c b/drivers/mailbox/stm32-ipcc.c index 046e1a8aca6..dda108735fc 100644 --- a/drivers/mailbox/stm32-ipcc.c +++ b/drivers/mailbox/stm32-ipcc.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_MAILBOX -#include #include #include #include diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c index 08c51c40f14..bfd4d7cdf2e 100644 --- a/drivers/mailbox/tegra-hsp.c +++ b/drivers/mailbox/tegra-hsp.c @@ -3,7 +3,6 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ -#include #include #include #include diff --git a/drivers/mailbox/zynqmp-ipi.c b/drivers/mailbox/zynqmp-ipi.c index eb86847bbe2..4df69734ed9 100644 --- a/drivers/mailbox/zynqmp-ipi.c +++ b/drivers/mailbox/zynqmp-ipi.c @@ -5,7 +5,6 @@ * Copyright (C) 2018-2019 Xilinx, Inc. */ -#include #include #include #include diff --git a/drivers/memory/stm32-fmc2-ebi.c b/drivers/memory/stm32-fmc2-ebi.c index 1ce96077858..713dead5c57 100644 --- a/drivers/memory/stm32-fmc2-ebi.c +++ b/drivers/memory/stm32-fmc2-ebi.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_NOP -#include #include #include #include diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index 41325eb0f94..29131f536a6 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -6,7 +6,6 @@ * Texas Instruments Incorporated, */ -#include #include #include diff --git a/drivers/memory/ti-gpmc.c b/drivers/memory/ti-gpmc.c index 8877b8f4385..8af48e199a7 100644 --- a/drivers/memory/ti-gpmc.c +++ b/drivers/memory/ti-gpmc.c @@ -7,7 +7,6 @@ #include #include -#include #include #include #include diff --git a/drivers/misc/altera_sysid.c b/drivers/misc/altera_sysid.c index 878df12771c..21e64fa3e6f 100644 --- a/drivers/misc/altera_sysid.c +++ b/drivers/misc/altera_sysid.c @@ -4,7 +4,6 @@ * Scott McNutt */ -#include #include #include #include diff --git a/drivers/misc/atsha204a-i2c.c b/drivers/misc/atsha204a-i2c.c index 707daa90bdb..3b9046da880 100644 --- a/drivers/misc/atsha204a-i2c.c +++ b/drivers/misc/atsha204a-i2c.c @@ -10,7 +10,6 @@ * published by the Free Software Foundation. */ -#include #include #include #include diff --git a/drivers/misc/cbmem_console.c b/drivers/misc/cbmem_console.c index ba3a599c4a5..8220addd579 100644 --- a/drivers/misc/cbmem_console.c +++ b/drivers/misc/cbmem_console.c @@ -3,8 +3,8 @@ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. */ -#include #include +#include #include void cbmemc_putc(struct stdio_dev *dev, char data) diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c index 9c1e6a5e3e7..fabe4964a33 100644 --- a/drivers/misc/cros_ec.c +++ b/drivers/misc/cros_ec.c @@ -15,7 +15,6 @@ #define LOG_CATEGORY UCLASS_CROS_EC -#include #include #include #include @@ -24,6 +23,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/misc/cros_ec_i2c.c b/drivers/misc/cros_ec_i2c.c index a1b78a3045d..5516aa8b3ff 100644 --- a/drivers/misc/cros_ec_i2c.c +++ b/drivers/misc/cros_ec_i2c.c @@ -12,7 +12,6 @@ * KBC. */ -#include #include #include #include diff --git a/drivers/misc/cros_ec_lpc.c b/drivers/misc/cros_ec_lpc.c index 1a8a81349c3..e2a3226362a 100644 --- a/drivers/misc/cros_ec_lpc.c +++ b/drivers/misc/cros_ec_lpc.c @@ -12,11 +12,11 @@ * KBC. */ -#include #include #include #include #include +#include #include #ifdef DEBUG_TRACE diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c index 1201535f4af..1cad51d474d 100644 --- a/drivers/misc/cros_ec_sandbox.c +++ b/drivers/misc/cros_ec_sandbox.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY UCLASS_CROS_EC -#include #include #include #include @@ -17,6 +16,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/misc/cros_ec_spi.c b/drivers/misc/cros_ec_spi.c index 591ff30df89..e86791c03a7 100644 --- a/drivers/misc/cros_ec_spi.c +++ b/drivers/misc/cros_ec_spi.c @@ -12,12 +12,12 @@ * KBC. */ -#include #include #include #include #include #include +#include int cros_ec_spi_packet(struct udevice *udev, int out_bytes, int in_bytes) { diff --git a/drivers/misc/ds4510.c b/drivers/misc/ds4510.c index 9340596f2c6..302015e2793 100644 --- a/drivers/misc/ds4510.c +++ b/drivers/misc/ds4510.c @@ -8,7 +8,6 @@ * and 4 programmable non-volatile GPIO pins. */ -#include #include #include #include diff --git a/drivers/misc/esm_pmic.c b/drivers/misc/esm_pmic.c index a518f750611..1963c8664a5 100644 --- a/drivers/misc/esm_pmic.c +++ b/drivers/misc/esm_pmic.c @@ -7,7 +7,6 @@ * */ -#include #include #include #include diff --git a/drivers/misc/fs_loader.c b/drivers/misc/fs_loader.c index 1ffc199ba1e..66803f4b997 100644 --- a/drivers/misc/fs_loader.c +++ b/drivers/misc/fs_loader.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_FS_FIRMWARE_LOADER -#include #include #include #include diff --git a/drivers/misc/fsl_devdis.c b/drivers/misc/fsl_devdis.c index 179053a298a..2c3d2348076 100644 --- a/drivers/misc/fsl_devdis.c +++ b/drivers/misc/fsl_devdis.c @@ -3,7 +3,7 @@ * Copyright 2015 Freescale Semiconductor, Inc. * Author: Zhuoyu Zhang */ -#include +#include #include #include #include diff --git a/drivers/misc/fsl_ifc.c b/drivers/misc/fsl_ifc.c index f165b8c36ba..93f41da0f97 100644 --- a/drivers/misc/fsl_ifc.c +++ b/drivers/misc/fsl_ifc.c @@ -4,7 +4,7 @@ * Author: Dipen Dudhat */ -#include +#include #include #include diff --git a/drivers/misc/fsl_iim.c b/drivers/misc/fsl_iim.c index 85cc3c26b2e..65468a68dbd 100644 --- a/drivers/misc/fsl_iim.c +++ b/drivers/misc/fsl_iim.c @@ -8,7 +8,6 @@ * Martha Marx */ -#include #include #include #include diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c index 6b831281e96..e7c0df78b6b 100644 --- a/drivers/misc/fsl_portals.c +++ b/drivers/misc/fsl_portals.c @@ -4,7 +4,7 @@ * Copyright 2017 NXP */ -#include +#include #include #include #include diff --git a/drivers/misc/fsl_sec_mon.c b/drivers/misc/fsl_sec_mon.c index 3597ee22242..7518089e1e3 100644 --- a/drivers/misc/fsl_sec_mon.c +++ b/drivers/misc/fsl_sec_mon.c @@ -3,7 +3,7 @@ * Copyright 2015 Freescale Semiconductor, Inc. */ -#include +#include #include #include diff --git a/drivers/misc/gdsys_ioep.c b/drivers/misc/gdsys_ioep.c index 145cfa23c6c..d4916a277b8 100644 --- a/drivers/misc/gdsys_ioep.c +++ b/drivers/misc/gdsys_ioep.c @@ -11,7 +11,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include #include #include #include diff --git a/drivers/misc/gdsys_rxaui_ctrl.c b/drivers/misc/gdsys_rxaui_ctrl.c index 8f5cbe420f8..d4cd63ca9f8 100644 --- a/drivers/misc/gdsys_rxaui_ctrl.c +++ b/drivers/misc/gdsys_rxaui_ctrl.c @@ -7,7 +7,6 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ -#include #include #include #include diff --git a/drivers/misc/gdsys_soc.c b/drivers/misc/gdsys_soc.c index 27e7dc48327..0adbb8df3c2 100644 --- a/drivers/misc/gdsys_soc.c +++ b/drivers/misc/gdsys_soc.c @@ -4,7 +4,6 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ -#include #include #include #include diff --git a/drivers/misc/gpio_led.c b/drivers/misc/gpio_led.c index 30679f80cf1..e63689967a7 100644 --- a/drivers/misc/gpio_led.c +++ b/drivers/misc/gpio_led.c @@ -5,7 +5,6 @@ * Licensed under the GPL-2 or later. */ -#include #include #include diff --git a/drivers/misc/i2c_eeprom.c b/drivers/misc/i2c_eeprom.c index 9111bd724cb..10f0173d805 100644 --- a/drivers/misc/i2c_eeprom.c +++ b/drivers/misc/i2c_eeprom.c @@ -5,8 +5,6 @@ #define LOG_CATEGORY UCLASS_I2C_EEPROM -#include -#include #include #include #include diff --git a/drivers/misc/i2c_eeprom_emul.c b/drivers/misc/i2c_eeprom_emul.c index 6f32087ede5..3ad2e047ee3 100644 --- a/drivers/misc/i2c_eeprom_emul.c +++ b/drivers/misc/i2c_eeprom_emul.c @@ -5,7 +5,6 @@ * Copyright (c) 2014 Google, Inc */ -#include #include #include #include diff --git a/drivers/misc/ihs_fpga.c b/drivers/misc/ihs_fpga.c index a0fece985d8..fe196b60819 100644 --- a/drivers/misc/ihs_fpga.c +++ b/drivers/misc/ihs_fpga.c @@ -9,7 +9,6 @@ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de */ -#include #include #include #include diff --git a/drivers/misc/imx8/fuse.c b/drivers/misc/imx8/fuse.c index b81f73f283f..90d251a4405 100644 --- a/drivers/misc/imx8/fuse.c +++ b/drivers/misc/imx8/fuse.c @@ -3,7 +3,6 @@ * Copyright 2019 NXP */ -#include #include #include #include diff --git a/drivers/misc/imx8/scu.c b/drivers/misc/imx8/scu.c index 798800aa758..bbd7e24200b 100644 --- a/drivers/misc/imx8/scu.c +++ b/drivers/misc/imx8/scu.c @@ -5,7 +5,6 @@ * Peng Fan */ -#include #include #include #include diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c index 6e2c678e614..591d71b096a 100644 --- a/drivers/misc/imx8/scu_api.c +++ b/drivers/misc/imx8/scu_api.c @@ -5,7 +5,6 @@ * Peng Fan */ -#include #include #include #include diff --git a/drivers/misc/imx_ele/ele_api.c b/drivers/misc/imx_ele/ele_api.c index e0ec22c7abf..3745504637b 100644 --- a/drivers/misc/imx_ele/ele_api.c +++ b/drivers/misc/imx_ele/ele_api.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/drivers/misc/imx_ele/ele_mu.c b/drivers/misc/imx_ele/ele_mu.c index 053cdcf0fe0..0cf81f33ba5 100644 --- a/drivers/misc/imx_ele/ele_mu.c +++ b/drivers/misc/imx_ele/ele_mu.c @@ -3,7 +3,6 @@ * Copyright 2020-2022 NXP */ -#include #include #include #include diff --git a/drivers/misc/imx_ele/fuse.c b/drivers/misc/imx_ele/fuse.c index 4e4dcb42cdd..d12539c8aac 100644 --- a/drivers/misc/imx_ele/fuse.c +++ b/drivers/misc/imx_ele/fuse.c @@ -3,7 +3,6 @@ * Copyright 2020 NXP */ -#include #include #include #include diff --git a/drivers/misc/irq-uclass.c b/drivers/misc/irq-uclass.c index 7b79ed2df46..79eb7c200dc 100644 --- a/drivers/misc/irq-uclass.c +++ b/drivers/misc/irq-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_IRQ -#include #include #include #include diff --git a/drivers/misc/irq_sandbox.c b/drivers/misc/irq_sandbox.c index 8b5573fcadd..5d176f63b5c 100644 --- a/drivers/misc/irq_sandbox.c +++ b/drivers/misc/irq_sandbox.c @@ -5,7 +5,6 @@ * Copyright 2019 Google LLC */ -#include #include #include #include diff --git a/drivers/misc/irq_sandbox_test.c b/drivers/misc/irq_sandbox_test.c index 95c45c24edb..3669b863bec 100644 --- a/drivers/misc/irq_sandbox_test.c +++ b/drivers/misc/irq_sandbox_test.c @@ -5,7 +5,6 @@ * Copyright 2021 Google LLC */ -#include #include #include #include diff --git a/drivers/misc/jz4780_efuse.c b/drivers/misc/jz4780_efuse.c index 1fba3271db6..5c92de26ec5 100644 --- a/drivers/misc/jz4780_efuse.c +++ b/drivers/misc/jz4780_efuse.c @@ -6,7 +6,6 @@ * Author: Alex Smith */ -#include #include #include #include diff --git a/drivers/misc/k3_avs.c b/drivers/misc/k3_avs.c index 0d29eff1ac0..87471cc3b16 100644 --- a/drivers/misc/k3_avs.c +++ b/drivers/misc/k3_avs.c @@ -7,7 +7,6 @@ * */ -#include #include #include #include diff --git a/drivers/misc/k3_esm.c b/drivers/misc/k3_esm.c index f6ac18bdc75..fa3d6565622 100644 --- a/drivers/misc/k3_esm.c +++ b/drivers/misc/k3_esm.c @@ -7,7 +7,6 @@ * */ -#include #include #include #include diff --git a/drivers/misc/ls2_sfp.c b/drivers/misc/ls2_sfp.c index 5351c7ed34f..8cb6e999bed 100644 --- a/drivers/misc/ls2_sfp.c +++ b/drivers/misc/ls2_sfp.c @@ -12,7 +12,6 @@ */ #define LOG_CATEGORY UCLASS_MISC -#include #include #include #include diff --git a/drivers/misc/microchip_flexcom.c b/drivers/misc/microchip_flexcom.c index e0a6f2d3880..c5ddecac755 100644 --- a/drivers/misc/microchip_flexcom.c +++ b/drivers/misc/microchip_flexcom.c @@ -4,7 +4,6 @@ * Author: Eugen Hristev */ -#include #include #include #include diff --git a/drivers/misc/misc-uclass.c b/drivers/misc/misc-uclass.c index cfe9d562fa0..1389e146b61 100644 --- a/drivers/misc/misc-uclass.c +++ b/drivers/misc/misc-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_MISC -#include #include #include #include diff --git a/drivers/misc/misc_sandbox.c b/drivers/misc/misc_sandbox.c index 31cde2dbac0..2473419df2a 100644 --- a/drivers/misc/misc_sandbox.c +++ b/drivers/misc/misc_sandbox.c @@ -4,7 +4,6 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ -#include #include #include diff --git a/drivers/misc/mpc83xx_serdes.c b/drivers/misc/mpc83xx_serdes.c index 93c87e998c4..cf9aa9b35b3 100644 --- a/drivers/misc/mpc83xx_serdes.c +++ b/drivers/misc/mpc83xx_serdes.c @@ -9,7 +9,6 @@ * Copyright (C) 2008 MontaVista Software, Inc. */ -#include #include #include #include diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c index 8ee18f29d9b..d1674caa138 100644 --- a/drivers/misc/mxc_ocotp.c +++ b/drivers/misc/mxc_ocotp.c @@ -11,7 +11,6 @@ * Copyright (C) 2011 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/drivers/misc/mxs_ocotp.c b/drivers/misc/mxs_ocotp.c index facc720c8ef..6432c62dac3 100644 --- a/drivers/misc/mxs_ocotp.c +++ b/drivers/misc/mxs_ocotp.c @@ -11,7 +11,6 @@ * etc.) which would make common driver an ifdef nightmare :-( */ -#include #include #include #include diff --git a/drivers/misc/npcm_host_intf.c b/drivers/misc/npcm_host_intf.c index 79f57f57d89..58bab888c3c 100644 --- a/drivers/misc/npcm_host_intf.c +++ b/drivers/misc/npcm_host_intf.c @@ -4,7 +4,6 @@ * Copyright (c) 2022 Nuvoton Technology Corp. */ -#include #include #include #include diff --git a/drivers/misc/npcm_otp.c b/drivers/misc/npcm_otp.c index 08029724c04..adb6135291d 100644 --- a/drivers/misc/npcm_otp.c +++ b/drivers/misc/npcm_otp.c @@ -4,7 +4,6 @@ */ #include -#include #include #include #include diff --git a/drivers/misc/nuvoton_nct6102d.c b/drivers/misc/nuvoton_nct6102d.c index daf5019d017..a3ca037d25f 100644 --- a/drivers/misc/nuvoton_nct6102d.c +++ b/drivers/misc/nuvoton_nct6102d.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Stefan Roese */ -#include #include #include #include diff --git a/drivers/misc/nvmem.c b/drivers/misc/nvmem.c index 5a2bd1f9f72..d0cb0a35b81 100644 --- a/drivers/misc/nvmem.c +++ b/drivers/misc/nvmem.c @@ -3,7 +3,6 @@ * Copyright (C) 2022 Sean Anderson */ -#include #include #include #include diff --git a/drivers/misc/p2sb-uclass.c b/drivers/misc/p2sb-uclass.c index f24857a1515..016c8073378 100644 --- a/drivers/misc/p2sb-uclass.c +++ b/drivers/misc/p2sb-uclass.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_P2SB -#include #include #include #include diff --git a/drivers/misc/p2sb_emul.c b/drivers/misc/p2sb_emul.c index 51f87161d5b..3dac6bd82e3 100644 --- a/drivers/misc/p2sb_emul.c +++ b/drivers/misc/p2sb_emul.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_MISC -#include #include #include #include diff --git a/drivers/misc/p2sb_sandbox.c b/drivers/misc/p2sb_sandbox.c index d80bca22a6b..9f3cd14958b 100644 --- a/drivers/misc/p2sb_sandbox.c +++ b/drivers/misc/p2sb_sandbox.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY UCLASS_P2SB -#include #include #include #include diff --git a/drivers/misc/pca9551_led.c b/drivers/misc/pca9551_led.c index cdc4390f815..040d0d5cf48 100644 --- a/drivers/misc/pca9551_led.c +++ b/drivers/misc/pca9551_led.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Stefan Roese */ -#include #include #include #include diff --git a/drivers/misc/pwrseq-uclass.c b/drivers/misc/pwrseq-uclass.c index a0f24e1bf3a..bddc3c33685 100644 --- a/drivers/misc/pwrseq-uclass.c +++ b/drivers/misc/pwrseq-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_PWRSEQ -#include #include #include diff --git a/drivers/misc/qfw.c b/drivers/misc/qfw.c index db98619fdf5..0e002ac25f4 100644 --- a/drivers/misc/qfw.c +++ b/drivers/misc/qfw.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_QFW -#include #include #include #include diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c index 2f96b79ea40..c7430147718 100644 --- a/drivers/misc/rockchip-efuse.c +++ b/drivers/misc/rockchip-efuse.c @@ -6,7 +6,6 @@ * Written by Philipp Tomsich */ -#include #include #include #include diff --git a/drivers/misc/rockchip-otp.c b/drivers/misc/rockchip-otp.c index 4f757083a1b..2123c31038f 100644 --- a/drivers/misc/rockchip-otp.c +++ b/drivers/misc/rockchip-otp.c @@ -3,7 +3,6 @@ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/drivers/misc/sandbox_adder.c b/drivers/misc/sandbox_adder.c index 3ea33e46e9f..de1c6357582 100644 --- a/drivers/misc/sandbox_adder.c +++ b/drivers/misc/sandbox_adder.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY UCLASS_MISC -#include #include #include #include diff --git a/drivers/misc/sifive-otp.c b/drivers/misc/sifive-otp.c index a624a358802..7fbcd3799e5 100644 --- a/drivers/misc/sifive-otp.c +++ b/drivers/misc/sifive-otp.c @@ -17,7 +17,6 @@ * Right now first 1KiB is used to store only serial number. */ -#include #include #include #include diff --git a/drivers/misc/sl28cpld.c b/drivers/misc/sl28cpld.c index 01ef1c6178f..1c61b005af3 100644 --- a/drivers/misc/sl28cpld.c +++ b/drivers/misc/sl28cpld.c @@ -3,7 +3,6 @@ * Copyright (c) 2021 Michael Walle */ -#include #include #include diff --git a/drivers/misc/smsc_lpc47m.c b/drivers/misc/smsc_lpc47m.c index bda064f1365..1b15907b093 100644 --- a/drivers/misc/smsc_lpc47m.c +++ b/drivers/misc/smsc_lpc47m.c @@ -3,7 +3,6 @@ * Copyright (C) 2014, Bin Meng */ -#include #include #include diff --git a/drivers/misc/smsc_sio1007.c b/drivers/misc/smsc_sio1007.c index 3b7b1c8bcf2..6d99aa61d91 100644 --- a/drivers/misc/smsc_sio1007.c +++ b/drivers/misc/smsc_sio1007.c @@ -3,7 +3,6 @@ * Copyright (C) 2016, Bin Meng */ -#include #include #include #include diff --git a/drivers/misc/spltest_sandbox.c b/drivers/misc/spltest_sandbox.c index 6b9701a06ae..3011a229271 100644 --- a/drivers/misc/spltest_sandbox.c +++ b/drivers/misc/spltest_sandbox.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include diff --git a/drivers/misc/status_led.c b/drivers/misc/status_led.c index a6e9c03a02e..3b1baa4f840 100644 --- a/drivers/misc/status_led.c +++ b/drivers/misc/status_led.c @@ -4,8 +4,8 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include +#include /* * The purpose of this code is to signal the operational status of a diff --git a/drivers/misc/stm32_rcc.c b/drivers/misc/stm32_rcc.c index c1e5428a6b8..0dd827e1dd0 100644 --- a/drivers/misc/stm32_rcc.c +++ b/drivers/misc/stm32_rcc.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_NOP -#include #include #include #include diff --git a/drivers/misc/stm32mp_fuse.c b/drivers/misc/stm32mp_fuse.c index 9fd6c367dc6..34be6c28c19 100644 --- a/drivers/misc/stm32mp_fuse.c +++ b/drivers/misc/stm32mp_fuse.c @@ -3,7 +3,6 @@ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved */ -#include #include #include #include diff --git a/drivers/misc/swap_case.c b/drivers/misc/swap_case.c index ee5c12bd0a4..d4a5620c62c 100644 --- a/drivers/misc/swap_case.c +++ b/drivers/misc/swap_case.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/misc/syscon_sandbox.c b/drivers/misc/syscon_sandbox.c index d5cef188d74..6adb4154c25 100644 --- a/drivers/misc/syscon_sandbox.c +++ b/drivers/misc/syscon_sandbox.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/misc/tegra186_bpmp.c b/drivers/misc/tegra186_bpmp.c index fecac9c4d90..a1585b81867 100644 --- a/drivers/misc/tegra186_bpmp.c +++ b/drivers/misc/tegra186_bpmp.c @@ -3,7 +3,6 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ -#include #include #include #include diff --git a/drivers/misc/tegra_car.c b/drivers/misc/tegra_car.c index 0ddbb3c619b..497ec18564c 100644 --- a/drivers/misc/tegra_car.c +++ b/drivers/misc/tegra_car.c @@ -3,7 +3,6 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ -#include #include #include #include diff --git a/drivers/misc/test_drv.c b/drivers/misc/test_drv.c index 927618256f0..9b1e357a139 100644 --- a/drivers/misc/test_drv.c +++ b/drivers/misc/test_drv.c @@ -3,7 +3,6 @@ * Copyright (c) 2014 Google, Inc */ -#include #include #include #include diff --git a/drivers/misc/turris_omnia_mcu.c b/drivers/misc/turris_omnia_mcu.c index 6b2f17c0002..be77acbd165 100644 --- a/drivers/misc/turris_omnia_mcu.c +++ b/drivers/misc/turris_omnia_mcu.c @@ -4,7 +4,6 @@ * Copyright (C) 2024 Marek Behún */ -#include #include #include #include diff --git a/drivers/misc/usb251xb.c b/drivers/misc/usb251xb.c index 92e92ba5e62..daba2c2d683 100644 --- a/drivers/misc/usb251xb.c +++ b/drivers/misc/usb251xb.c @@ -10,7 +10,6 @@ * https://patchwork.kernel.org/patch/9257715/ */ -#include #include #include #include diff --git a/drivers/misc/vexpress_config.c b/drivers/misc/vexpress_config.c index 99aad1412ae..e7655ceff74 100644 --- a/drivers/misc/vexpress_config.c +++ b/drivers/misc/vexpress_config.c @@ -4,7 +4,6 @@ * Author: Liviu Dudau * */ -#include #include #include #include diff --git a/drivers/misc/winbond_w83627.c b/drivers/misc/winbond_w83627.c index 3838b3f74f4..87b9043e65c 100644 --- a/drivers/misc/winbond_w83627.c +++ b/drivers/misc/winbond_w83627.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Stefan Roese */ -#include #include #include diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 549634891a3..d0944793c92 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -147,9 +147,16 @@ config SPL_MMC_IO_VOLTAGE support. For eMMC this not mandatory, but not enabling this option may prevent the driver of using the faster modes. +config MMC_SUPPORTS_TUNING + bool + +config SPL_MMC_SUPPORTS_TUNING + bool + config MMC_UHS_SUPPORT bool "enable UHS support" depends on MMC_IO_VOLTAGE + select MMC_SUPPORTS_TUNING help The Ultra High Speed (UHS) bus is available on some SDHC and SDXC cards. The IO voltage must be switchable from 3.3v to 1.8v. The bus @@ -158,6 +165,7 @@ config MMC_UHS_SUPPORT config SPL_MMC_UHS_SUPPORT bool "enable UHS support in SPL" depends on SPL_MMC_IO_VOLTAGE + select SPL_MMC_SUPPORTS_TUNING help The Ultra High Speed (UHS) bus is available on some SDHC and SDXC cards. The IO voltage must be switchable from 3.3v to 1.8v. The bus @@ -193,6 +201,7 @@ config SPL_MMC_HS400_SUPPORT config MMC_HS200_SUPPORT bool "enable HS200 support" + select MMC_SUPPORTS_TUNING help The HS200 mode is support by some eMMC. The bus frequency is up to 200MHz. This mode requires tuning the IO. @@ -200,6 +209,7 @@ config MMC_HS200_SUPPORT config SPL_MMC_HS200_SUPPORT bool "enable HS200 support in SPL" depends on SPL_MMC + select SPL_MMC_SUPPORTS_TUNING help The HS200 mode is support by some eMMC. The bus frequency is up to 200MHz. This mode requires tuning the IO. @@ -347,6 +357,7 @@ config MMC_OCTEONTX bool "Marvell Octeon Multimedia Card Interface support" depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) depends on DM_MMC + select MMC_SUPPORTS_TUNING if ARCH_OCTEONTX2 help This selects the Octeon Multimedia card Interface. If you have an OcteonTX/TX2 or MIPS Octeon board with a diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c index fadab7d40bb..48fac7a11b4 100644 --- a/drivers/mmc/am654_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include @@ -397,7 +396,7 @@ static void am654_sdhci_write_b(struct sdhci_host *host, u8 val, int reg) writeb(val, host->ioaddr + reg); } -#ifdef MMC_SUPPORTS_TUNING +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) #define ITAPDLY_LENGTH 32 #define ITAPDLY_LAST_INDEX (ITAPDLY_LENGTH - 1) @@ -500,7 +499,7 @@ static int am654_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) } #endif const struct sdhci_ops am654_sdhci_ops = { -#ifdef MMC_SUPPORTS_TUNING +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) .platform_execute_tuning = am654_sdhci_execute_tuning, #endif .deferred_probe = am654_sdhci_deferred_probe, @@ -560,7 +559,7 @@ static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host *host) } const struct sdhci_ops j721e_4bit_sdhci_ops = { -#ifdef MMC_SUPPORTS_TUNING +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) .platform_execute_tuning = am654_sdhci_execute_tuning, #endif .deferred_probe = am654_sdhci_deferred_probe, diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c index cecc7ad783d..f00b0ff0dc9 100644 --- a/drivers/mmc/arm_pl180_mmci.c +++ b/drivers/mmc/arm_pl180_mmci.c @@ -11,7 +11,6 @@ /* #define DEBUG */ -#include "common.h" #include #include #include diff --git a/drivers/mmc/aspeed_sdhci.c b/drivers/mmc/aspeed_sdhci.c index c9626c6beb8..87a6f66ebb3 100644 --- a/drivers/mmc/aspeed_sdhci.c +++ b/drivers/mmc/aspeed_sdhci.c @@ -4,7 +4,6 @@ * Eddie James */ -#include #include #include #include diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c index d92bad97b71..0b265196f02 100644 --- a/drivers/mmc/atmel_sdhci.c +++ b/drivers/mmc/atmel_sdhci.c @@ -4,7 +4,6 @@ * Wenyou.Yang */ -#include #include #include #include diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c index 5e48394fd0f..598a51d914a 100644 --- a/drivers/mmc/bcm2835_sdhci.c +++ b/drivers/mmc/bcm2835_sdhci.c @@ -36,7 +36,6 @@ * Inspired by sdhci-pci.c, by Pierre Ossman */ -#include #include #include #include diff --git a/drivers/mmc/bcm2835_sdhost.c b/drivers/mmc/bcm2835_sdhost.c index 5c23c03d10d..720127468d3 100644 --- a/drivers/mmc/bcm2835_sdhost.c +++ b/drivers/mmc/bcm2835_sdhost.c @@ -30,7 +30,6 @@ * sdhci.c and sdhci-pci.c by Pierre Ossman */ #include -#include #include #include #include diff --git a/drivers/mmc/bcmstb_sdhci.c b/drivers/mmc/bcmstb_sdhci.c index 49846adcf54..7bddbebb162 100644 --- a/drivers/mmc/bcmstb_sdhci.c +++ b/drivers/mmc/bcmstb_sdhci.c @@ -6,7 +6,6 @@ * Author: Thomas Fitzsimmons */ -#include #include #include #include diff --git a/drivers/mmc/ca_dw_mmc.c b/drivers/mmc/ca_dw_mmc.c index a17ed8c11cb..54a2ba4795e 100644 --- a/drivers/mmc/ca_dw_mmc.c +++ b/drivers/mmc/ca_dw_mmc.c @@ -4,7 +4,6 @@ * Arthur Li */ -#include #include #include #include diff --git a/drivers/mmc/davinci_mmc.c b/drivers/mmc/davinci_mmc.c index 3a3d23aec00..5107fcd8362 100644 --- a/drivers/mmc/davinci_mmc.c +++ b/drivers/mmc/davinci_mmc.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index e1036641452..e6107c770fe 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index 2f849c43b12..a51f762988d 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -4,7 +4,6 @@ * Jaehoon Chung */ -#include #include #include #include diff --git a/drivers/mmc/f_sdh30.c b/drivers/mmc/f_sdh30.c index 3d587a464d5..f47cf848521 100644 --- a/drivers/mmc/f_sdh30.c +++ b/drivers/mmc/f_sdh30.c @@ -5,7 +5,6 @@ * Copyright 2021 Socionext, Inc. */ -#include #include #include #include diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 595d88bd562..0c66980b621 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -10,7 +10,6 @@ */ #include -#include #include #include #include @@ -1102,7 +1101,7 @@ static int fsl_esdhc_reinit(struct udevice *dev) return esdhc_init_common(priv, &plat->mmc); } -#ifdef MMC_SUPPORTS_TUNING +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode) { struct fsl_esdhc_plat *plat = dev_get_plat(dev); @@ -1175,7 +1174,7 @@ static const struct dm_mmc_ops fsl_esdhc_ops = { .get_cd = fsl_esdhc_get_cd, .send_cmd = fsl_esdhc_send_cmd, .set_ios = fsl_esdhc_set_ios, -#ifdef MMC_SUPPORTS_TUNING +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) .execute_tuning = fsl_esdhc_execute_tuning, #endif .reinit = fsl_esdhc_reinit, diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index b74c0140020..a9b8d7dd67f 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -11,7 +11,6 @@ */ #include -#include #include #include #include @@ -635,7 +634,7 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) priv->clock = clock; } -#ifdef MMC_SUPPORTS_TUNING +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) static int esdhc_change_pinstate(struct udevice *dev) { struct fsl_esdhc_priv *priv = dev_get_priv(dev); @@ -913,7 +912,7 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) int ret __maybe_unused; u32 clock; -#ifdef MMC_SUPPORTS_TUNING +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) /* * call esdhc_set_timing() before update the clock rate, * This is because current we support DDR and SDR mode, @@ -951,7 +950,7 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); } -#ifdef MMC_SUPPORTS_TUNING +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) /* * For HS400/HS400ES mode, make sure set the strobe dll in the * target clock rate. So call esdhc_set_strobe_dll() after the @@ -1618,7 +1617,7 @@ static const struct dm_mmc_ops fsl_esdhc_ops = { .get_cd = fsl_esdhc_get_cd, .send_cmd = fsl_esdhc_send_cmd, .set_ios = fsl_esdhc_set_ios, -#ifdef MMC_SUPPORTS_TUNING +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) .execute_tuning = fsl_esdhc_execute_tuning, #endif #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c index 6d7c0cff22a..1a11258be4d 100644 --- a/drivers/mmc/fsl_esdhc_spl.c +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -3,7 +3,7 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/drivers/mmc/ftsdc010_mci.c b/drivers/mmc/ftsdc010_mci.c index cabb747fbbd..11e44264e47 100644 --- a/drivers/mmc/ftsdc010_mci.c +++ b/drivers/mmc/ftsdc010_mci.c @@ -9,7 +9,6 @@ * Author: Rick Chen (rick@andestech.com) */ -#include #include #include #include diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index 3ee99558f6f..6a531fa0961 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -8,7 +8,7 @@ * Copyright (C) 2004-2006 Atmel Corporation */ -#include +#include #include #include #include diff --git a/drivers/mmc/hi6220_dw_mmc.c b/drivers/mmc/hi6220_dw_mmc.c index dc0210402bd..c68a9157bfc 100644 --- a/drivers/mmc/hi6220_dw_mmc.c +++ b/drivers/mmc/hi6220_dw_mmc.c @@ -4,7 +4,6 @@ * peter.griffin */ -#include #include #include #include diff --git a/drivers/mmc/iproc_sdhci.c b/drivers/mmc/iproc_sdhci.c index 11d86ad658f..7ab74ff117a 100644 --- a/drivers/mmc/iproc_sdhci.c +++ b/drivers/mmc/iproc_sdhci.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/drivers/mmc/jz_mmc.c b/drivers/mmc/jz_mmc.c index 61e48ee0f62..fc10bb256a4 100644 --- a/drivers/mmc/jz_mmc.c +++ b/drivers/mmc/jz_mmc.c @@ -6,7 +6,6 @@ * Author: Paul Burton */ -#include #include #include #include diff --git a/drivers/mmc/kona_sdhci.c b/drivers/mmc/kona_sdhci.c index 2bbe673b912..83f14122632 100644 --- a/drivers/mmc/kona_sdhci.c +++ b/drivers/mmc/kona_sdhci.c @@ -3,7 +3,6 @@ * Copyright 2013 Broadcom Corporation. */ -#include #include #include #include diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index 0825c0a2a83..5852b24c6d2 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -3,7 +3,6 @@ * (C) Copyright 2016 Carlo Caione */ -#include #include #include #include diff --git a/drivers/mmc/mmc-pwrseq.c b/drivers/mmc/mmc-pwrseq.c index 2539f61323d..a1c9624a222 100644 --- a/drivers/mmc/mmc-pwrseq.c +++ b/drivers/mmc/mmc-pwrseq.c @@ -4,7 +4,6 @@ * Jaehoon Chung */ -#include #include #include #include diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c index 24170c59ecc..da6a39b7d99 100644 --- a/drivers/mmc/mmc-uclass.c +++ b/drivers/mmc/mmc-uclass.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY UCLASS_MMC -#include #include #include #include @@ -112,7 +111,7 @@ int mmc_getcd(struct mmc *mmc) return dm_mmc_get_cd(mmc->dev); } -#ifdef MMC_SUPPORTS_TUNING +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) static int dm_mmc_execute_tuning(struct udevice *dev, uint opcode) { struct dm_mmc_ops *ops = mmc_get_ops(dev); diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 7b068c71ff3..b18dc331f78 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -8,7 +8,6 @@ */ #include -#include #include #include #include @@ -17,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -24,6 +24,7 @@ #include #include #include +#include #include #include "mmc_private.h" @@ -329,7 +330,7 @@ int mmc_set_blocklen(struct mmc *mmc, int len) MMC_QUIRK_RETRY_SET_BLOCKLEN, 4); } -#ifdef MMC_SUPPORTS_TUNING +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) static const u8 tuning_blk_pattern_4bit[] = { 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc, 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef, @@ -1621,7 +1622,7 @@ static inline int bus_width(uint cap) } #if !CONFIG_IS_ENABLED(DM_MMC) -#ifdef MMC_SUPPORTS_TUNING +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) static int mmc_execute_tuning(struct mmc *mmc, uint opcode) { return -ENOTSUPP; @@ -1702,7 +1703,7 @@ void mmc_dump_capabilities(const char *text, uint caps) struct mode_width_tuning { enum bus_mode mode; uint widths; -#ifdef MMC_SUPPORTS_TUNING +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) uint tuning; #endif }; @@ -1743,7 +1744,7 @@ static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage) #if !CONFIG_IS_ENABLED(MMC_TINY) static const struct mode_width_tuning sd_modes_by_pref[] = { #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) -#ifdef MMC_SUPPORTS_TUNING +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) { .mode = UHS_SDR104, .widths = MMC_MODE_4BIT | MMC_MODE_1BIT, @@ -1846,7 +1847,7 @@ static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps) mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE); -#ifdef MMC_SUPPORTS_TUNING +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) /* execute tuning if needed */ if (mwt->tuning && !mmc_host_is_spi(mmc)) { err = mmc_execute_tuning(mmc, @@ -2224,7 +2225,7 @@ static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps) mmc_select_mode(mmc, mwt->mode); mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE); -#ifdef MMC_SUPPORTS_TUNING +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) /* execute tuning if needed */ if (mwt->tuning) { diff --git a/drivers/mmc/mmc_boot.c b/drivers/mmc/mmc_boot.c index 0a74b1fb776..367c957b518 100644 --- a/drivers/mmc/mmc_boot.c +++ b/drivers/mmc/mmc_boot.c @@ -4,7 +4,6 @@ * Written by Amar */ -#include #include #include #include "mmc_private.h" diff --git a/drivers/mmc/mmc_bootdev.c b/drivers/mmc/mmc_bootdev.c index 55ecead2ddf..5a1688b75d0 100644 --- a/drivers/mmc/mmc_bootdev.c +++ b/drivers/mmc/mmc_bootdev.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/mmc/mmc_legacy.c b/drivers/mmc/mmc_legacy.c index a101ee43fde..a87d2276c1b 100644 --- a/drivers/mmc/mmc_legacy.c +++ b/drivers/mmc/mmc_legacy.c @@ -5,7 +5,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c index bcea800e5f6..675e642efd0 100644 --- a/drivers/mmc/mmc_spi.c +++ b/drivers/mmc/mmc_spi.c @@ -6,7 +6,6 @@ * * Licensed under the GPL-2 or later. */ -#include #include #include #include diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c index a6f93380dd0..c023d15e52a 100644 --- a/drivers/mmc/mmc_write.c +++ b/drivers/mmc/mmc_write.c @@ -7,7 +7,6 @@ */ #include -#include #include #include #include diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index 5e9d66526a8..4ce0de6c47d 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -7,7 +7,6 @@ * Based on Linux driver */ -#include #include #include #include diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c index 296aaee7331..3a9258255a7 100644 --- a/drivers/mmc/mtk-sd.c +++ b/drivers/mmc/mtk-sd.c @@ -7,7 +7,6 @@ */ #include -#include #include #include #include @@ -1011,7 +1010,7 @@ static int msdc_ops_get_wp(struct udevice *dev) #endif } -#ifdef MMC_SUPPORTS_TUNING +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) static u32 test_delay_bit(u32 delay, u32 bit) { bit %= PAD_DELAY_MAX; @@ -1760,7 +1759,7 @@ static const struct dm_mmc_ops msdc_ops = { .set_ios = msdc_ops_set_ios, .get_cd = msdc_ops_get_cd, .get_wp = msdc_ops_get_wp, -#ifdef MMC_SUPPORTS_TUNING +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) .execute_tuning = msdc_execute_tuning, #endif .wait_dat0 = msdc_ops_wait_dat0, diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c index dbdd671c88b..2da5334c21f 100644 --- a/drivers/mmc/mv_sdhci.c +++ b/drivers/mmc/mv_sdhci.c @@ -3,7 +3,6 @@ * Marvell SD Host Controller Interface */ -#include #include #include #include diff --git a/drivers/mmc/mvebu_mmc.c b/drivers/mmc/mvebu_mmc.c index fea55c61ed7..5af1953cd14 100644 --- a/drivers/mmc/mvebu_mmc.c +++ b/drivers/mmc/mvebu_mmc.c @@ -7,7 +7,6 @@ * Written-by: Maen Suleiman, Gerald Kerma */ -#include #include #include #include diff --git a/drivers/mmc/mxcmmc.c b/drivers/mmc/mxcmmc.c index 0057273a2a7..1acea6f820b 100644 --- a/drivers/mmc/mxcmmc.c +++ b/drivers/mmc/mxcmmc.c @@ -17,7 +17,6 @@ */ #include -#include #include #include #include diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c index 35a8e21058e..95390a5be7e 100644 --- a/drivers/mmc/mxsmmc.c +++ b/drivers/mmc/mxsmmc.c @@ -20,7 +20,6 @@ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net */ -#include #include #include #include diff --git a/drivers/mmc/nexell_dw_mmc.c b/drivers/mmc/nexell_dw_mmc.c index 2723e4887cf..2e1ce54c7d5 100644 --- a/drivers/mmc/nexell_dw_mmc.c +++ b/drivers/mmc/nexell_dw_mmc.c @@ -6,7 +6,6 @@ * (C) Copyright 2019 Stefan Bosch */ -#include #include #include #include diff --git a/drivers/mmc/npcm_sdhci.c b/drivers/mmc/npcm_sdhci.c index d63521d6855..dff4732ea06 100644 --- a/drivers/mmc/npcm_sdhci.c +++ b/drivers/mmc/npcm_sdhci.c @@ -3,7 +3,6 @@ * Copyright (c) 2022 Nuvoton Technology Corp. */ -#include #include #include #include diff --git a/drivers/mmc/octeontx_hsmmc.c b/drivers/mmc/octeontx_hsmmc.c index 7f9c4f4d36d..3b5e1221732 100644 --- a/drivers/mmc/octeontx_hsmmc.c +++ b/drivers/mmc/octeontx_hsmmc.c @@ -794,7 +794,7 @@ octeontx_mmc_get_cr_mods(struct mmc *mmc, const struct mmc_cmd *cmd, u8 desired_ctype = 0; if (IS_MMC(mmc)) { -#ifdef MMC_SUPPORTS_TUNING +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) { if (cmd->resp_type == MMC_RSP_R1) cr.rtype_xor = 1; @@ -1631,7 +1631,7 @@ static int octeontx_mmc_dev_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, return octeontx_mmc_send_cmd(dev_to_mmc(dev), cmd, data); } -#ifdef MMC_SUPPORTS_TUNING +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) static int octeontx_mmc_test_cmd(struct mmc *mmc, u32 opcode, int *statp) { struct mmc_cmd cmd; @@ -2421,12 +2421,12 @@ static int octeontx_mmc_execute_tuning(struct udevice *dev, u32 opcode) return 0; } -#else /* MMC_SUPPORTS_TUNING */ +#else /* CONFIG_MMC_SUPPORTS_TUNING */ static void octeontx_mmc_set_emm_timing(struct mmc *mmc, union mio_emm_timing emm_timing) { } -#endif /* MMC_SUPPORTS_TUNING */ +#endif /* CONFIG_MMC_SUPPORTS_TUNING */ /** * Calculate the clock period with rounding up @@ -2573,7 +2573,7 @@ static int octeontx_mmc_set_ios(struct udevice *dev) err = octeontx_mmc_configure_delay(mmc); -#ifdef MMC_SUPPORTS_TUNING +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) if (!err && mmc->selected_mode == MMC_HS_400 && !slot->hs400_tuned) { debug("%s: Tuning HS400 mode\n", __func__); err = octeontx_tune_hs400(mmc); @@ -3776,7 +3776,7 @@ static const struct dm_mmc_ops octeontx_hsmmc_ops = { .set_ios = octeontx_mmc_set_ios, .get_cd = octeontx_mmc_get_cd, .get_wp = octeontx_mmc_get_wp, -#ifdef MMC_SUPPORTS_TUNING +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) .execute_tuning = octeontx_mmc_execute_tuning, #endif }; diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 99f21b2c546..2b7f9fc9a20 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -23,7 +23,6 @@ */ #include -#include #include #include #include @@ -577,7 +576,7 @@ static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc) return val; } -#ifdef MMC_SUPPORTS_TUNING +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) static void omap_hsmmc_disable_tuning(struct mmc *mmc) { struct hsmmc *mmc_base; @@ -1518,7 +1517,7 @@ static const struct dm_mmc_ops omap_hsmmc_ops = { .get_cd = omap_hsmmc_getcd, .get_wp = omap_hsmmc_getwp, #endif -#ifdef MMC_SUPPORTS_TUNING +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) .execute_tuning = omap_hsmmc_execute_tuning, #endif .wait_dat0 = omap_hsmmc_wait_dat0, diff --git a/drivers/mmc/owl_mmc.c b/drivers/mmc/owl_mmc.c index e84171a661a..bd4906f58e7 100644 --- a/drivers/mmc/owl_mmc.c +++ b/drivers/mmc/owl_mmc.c @@ -11,7 +11,6 @@ * channel, and those special bits used in this driver is picked from vendor * source exclusively for MMC/SD. */ -#include #include #include #include diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c index 4d163ccba04..d446c55f72b 100644 --- a/drivers/mmc/pci_mmc.c +++ b/drivers/mmc/pci_mmc.c @@ -4,7 +4,6 @@ * Copyright (C) 2014, Bin Meng */ -#include #include #include #include diff --git a/drivers/mmc/piton_mmc.c b/drivers/mmc/piton_mmc.c index a330bbf8cbe..fed1f841608 100644 --- a/drivers/mmc/piton_mmc.c +++ b/drivers/mmc/piton_mmc.c @@ -11,7 +11,6 @@ #include #include -#include #include #include #include diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index ad4529d6afa..1a10b7057a4 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -3,7 +3,6 @@ * Copyright (c) 2013 Google, Inc */ -#include #include #include #include diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index c889c7bc985..35667b86b50 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -5,7 +5,6 @@ * Rockchip SD Host Controller Interface */ -#include #include #include #include diff --git a/drivers/mmc/rpmb.c b/drivers/mmc/rpmb.c index b68d98573c9..0658ce22cf1 100644 --- a/drivers/mmc/rpmb.c +++ b/drivers/mmc/rpmb.c @@ -8,7 +8,6 @@ */ #include -#include #include #include #include diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 3b74feae68c..80dbb38c9b3 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -4,7 +4,6 @@ * Jaehoon Chung */ -#include #include #include #include diff --git a/drivers/mmc/sandbox_mmc.c b/drivers/mmc/sandbox_mmc.c index 0ba7940a4db..a24520f2e78 100644 --- a/drivers/mmc/sandbox_mmc.c +++ b/drivers/mmc/sandbox_mmc.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/mmc/sdhci-adma.c b/drivers/mmc/sdhci-adma.c index 283ba956deb..fdb189d71a6 100644 --- a/drivers/mmc/sdhci-adma.c +++ b/drivers/mmc/sdhci-adma.c @@ -3,7 +3,6 @@ * SDHCI ADMA2 helper functions. */ -#include #include #include #include diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c index c0a9f60b149..07ec35a0463 100644 --- a/drivers/mmc/sdhci-cadence.c +++ b/drivers/mmc/sdhci-cadence.c @@ -4,7 +4,6 @@ * Author: Masahiro Yamada */ -#include #include #include #include @@ -274,7 +273,7 @@ static int sdhci_cdns_probe(struct udevice *dev) host->ops = &sdhci_cdns_ops; host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD; sdhci_cdns_mmc_ops = sdhci_ops; -#ifdef MMC_SUPPORTS_TUNING +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) sdhci_cdns_mmc_ops.execute_tuning = sdhci_cdns_execute_tuning; #endif diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index af654ea8d13..560b7e889c7 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -7,7 +7,6 @@ * Murray.Jensen@cmst.csiro.au, 27-Jan-01. */ -#include #include #include #include @@ -15,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -351,7 +351,7 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, return -ECOMM; } -#if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING) +#if defined(CONFIG_DM_MMC) && CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) static int sdhci_execute_tuning(struct udevice *dev, uint opcode) { int err; @@ -848,7 +848,7 @@ const struct dm_mmc_ops sdhci_ops = { .set_ios = sdhci_set_ios, .get_cd = sdhci_get_cd, .deferred_probe = sdhci_deferred_probe, -#ifdef MMC_SUPPORTS_TUNING +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) .execute_tuning = sdhci_execute_tuning, #endif .wait_dat0 = sdhci_wait_dat0, diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c index 76dc1c68b82..06a30d5efb8 100644 --- a/drivers/mmc/sh_mmcif.c +++ b/drivers/mmc/sh_mmcif.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/drivers/mmc/snps_dw_mmc.c b/drivers/mmc/snps_dw_mmc.c index 0134399e393..9bdbe5070b1 100644 --- a/drivers/mmc/snps_dw_mmc.c +++ b/drivers/mmc/snps_dw_mmc.c @@ -7,7 +7,6 @@ * Author: Eugeniy Paltsev */ -#include #include #include #include diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 387cb8b6b50..f738019b835 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -3,7 +3,6 @@ * (C) Copyright 2013 Altera Corporation */ -#include #include #include #include diff --git a/drivers/mmc/sti_sdhci.c b/drivers/mmc/sti_sdhci.c index 23a1dd43c9b..91018b7e21a 100644 --- a/drivers/mmc/sti_sdhci.c +++ b/drivers/mmc/sti_sdhci.c @@ -4,7 +4,6 @@ * Author(s): Patrice Chotard, for STMicroelectronics. */ -#include #include #include #include diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c index 39ae79ba129..9483fb57daf 100644 --- a/drivers/mmc/stm32_sdmmc2.c +++ b/drivers/mmc/stm32_sdmmc2.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_MMC -#include #include #include #include diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 714706d2411..0b56d1405be 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -13,7 +13,6 @@ * proper DM_MMC implementation at the end. */ -#include #include #include #include diff --git a/drivers/mmc/tangier_sdhci.c b/drivers/mmc/tangier_sdhci.c index 11564273324..ae65c310b68 100644 --- a/drivers/mmc/tangier_sdhci.c +++ b/drivers/mmc/tangier_sdhci.c @@ -2,7 +2,6 @@ /* * Copyright (c) 2017 Intel Corporation */ -#include #include #include #include diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index c01fb3d0165..5ed7f01d3f3 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -7,7 +7,6 @@ */ #include -#include #include #include #include diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c index 719c4830bc3..0b396122b46 100644 --- a/drivers/mmc/tmio-common.c +++ b/drivers/mmc/tmio-common.c @@ -4,7 +4,6 @@ * Author: Masahiro Yamada */ -#include #include #include #include diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c index 8cde4308aae..5b3650d52ee 100644 --- a/drivers/mmc/uniphier-sd.c +++ b/drivers/mmc/uniphier-sd.c @@ -4,7 +4,6 @@ * Author: Masahiro Yamada */ -#include #include #include #include diff --git a/drivers/mmc/xenon_sdhci.c b/drivers/mmc/xenon_sdhci.c index 27dbe0404e0..0e4902fab77 100644 --- a/drivers/mmc/xenon_sdhci.c +++ b/drivers/mmc/xenon_sdhci.c @@ -14,7 +14,6 @@ * Stefan Roese */ -#include #include #include #include diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 935540d1719..898be5a0913 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -7,7 +7,6 @@ */ #include -#include #include #include #include diff --git a/drivers/mtd/altera_qspi.c b/drivers/mtd/altera_qspi.c index d31391f36a4..c26615821c8 100644 --- a/drivers/mtd/altera_qspi.c +++ b/drivers/mtd/altera_qspi.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Thomas Chou */ -#include #include #include #include diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 8ade7949a68..a7826e81c17 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -16,7 +16,7 @@ /* The DEBUG define must be before common to enable debugging */ /* #define DEBUG */ -#include +#include #include #include #include @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/mtd/cfi_mtd.c b/drivers/mtd/cfi_mtd.c index bf4473ba9e8..b14d4773931 100644 --- a/drivers/mtd/cfi_mtd.c +++ b/drivers/mtd/cfi_mtd.c @@ -5,7 +5,6 @@ * Written by: Piotr Ziecik */ -#include #include #include #include diff --git a/drivers/mtd/hbmc-am654.c b/drivers/mtd/hbmc-am654.c index 8161087b50c..599beda30d5 100644 --- a/drivers/mtd/hbmc-am654.c +++ b/drivers/mtd/hbmc-am654.c @@ -3,7 +3,6 @@ // Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ // Author: Vignesh Raghavendra -#include #include #include #include diff --git a/drivers/mtd/jedec_flash.c b/drivers/mtd/jedec_flash.c index 859c7fd4ec2..a832f348f22 100644 --- a/drivers/mtd/jedec_flash.c +++ b/drivers/mtd/jedec_flash.c @@ -11,7 +11,6 @@ /* The DEBUG define must be before common to enable debugging */ /*#define DEBUG*/ -#include #include #include #include diff --git a/drivers/mtd/mtd-uclass.c b/drivers/mtd/mtd-uclass.c index 0743fe7af9f..720bd824c4d 100644 --- a/drivers/mtd/mtd-uclass.c +++ b/drivers/mtd/mtd-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_MTD -#include #include #include #include diff --git a/drivers/mtd/mtd_uboot.c b/drivers/mtd/mtd_uboot.c index 14ce726b10d..69cb3b51f92 100644 --- a/drivers/mtd/mtd_uboot.c +++ b/drivers/mtd/mtd_uboot.c @@ -3,7 +3,6 @@ * (C) Copyright 2014 * Heiko Schocher, DENX Software Engineering, hs@denx.de. */ -#include #include #include #include diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c index 4886392a1cf..be1d19b4ffa 100644 --- a/drivers/mtd/mtdpart.c +++ b/drivers/mtd/mtdpart.c @@ -19,7 +19,6 @@ #include #endif -#include #include #include #include diff --git a/drivers/mtd/nand/bbt.c b/drivers/mtd/nand/bbt.c index 972aec6e266..4ff0999f62a 100644 --- a/drivers/mtd/nand/bbt.c +++ b/drivers/mtd/nand/bbt.c @@ -9,7 +9,6 @@ #define pr_fmt(fmt) "nand-bbt: " fmt -#include #include #include #include diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c index f6d9c584f78..472ad0bdefb 100644 --- a/drivers/mtd/nand/core.c +++ b/drivers/mtd/nand/core.c @@ -9,7 +9,6 @@ #define pr_fmt(fmt) "nand: " fmt -#include #include #ifndef __UBOOT__ #include diff --git a/drivers/mtd/nand/raw/am335x_spl_bch.c b/drivers/mtd/nand/raw/am335x_spl_bch.c index 6831af98b73..64d8ce0965a 100644 --- a/drivers/mtd/nand/raw/am335x_spl_bch.c +++ b/drivers/mtd/nand/raw/am335x_spl_bch.c @@ -9,7 +9,7 @@ * Stefan Roese, DENX Software Engineering, sr@denx.de. */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/arasan_nfc.c b/drivers/mtd/nand/raw/arasan_nfc.c index ffcd963b3da..4f013efafb3 100644 --- a/drivers/mtd/nand/raw/arasan_nfc.c +++ b/drivers/mtd/nand/raw/arasan_nfc.c @@ -5,7 +5,6 @@ * Copyright (C) 2014 - 2015 Xilinx, Inc. */ -#include #include #include #include diff --git a/drivers/mtd/nand/raw/atmel_nand.c b/drivers/mtd/nand/raw/atmel_nand.c index 6d94e7af38e..4dbf7b47135 100644 --- a/drivers/mtd/nand/raw/atmel_nand.c +++ b/drivers/mtd/nand/raw/atmel_nand.c @@ -10,7 +10,7 @@ * (C) Copyright 2012 ATMEL, Hong Xu */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c index 4e6d99fd3ca..3f59fbbbb8f 100644 --- a/drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c +++ b/drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c index 6164989b937..d54de0b3ecc 100644 --- a/drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c +++ b/drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c index feae66ef25a..a101222a28f 100644 --- a/drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c +++ b/drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c index dbd85af7079..385642d0c09 100644 --- a/drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c +++ b/drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/drivers/mtd/nand/raw/brcmnand/bcm6838_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm6838_nand.c index ef3649688c6..407898ddae6 100644 --- a/drivers/mtd/nand/raw/brcmnand/bcm6838_nand.c +++ b/drivers/mtd/nand/raw/brcmnand/bcm6838_nand.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c index 027fdd37da3..564c678c9ef 100644 --- a/drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c +++ b/drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index efbf9a3120a..b7bf7cc0893 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -12,7 +12,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand_compat.c b/drivers/mtd/nand/raw/brcmnand/brcmnand_compat.c index a6acf556bcc..b3b3df5c042 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand_compat.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand_compat.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/drivers/mtd/nand/raw/brcmnand/iproc_nand.c b/drivers/mtd/nand/raw/brcmnand/iproc_nand.c index 69711d98ce1..430d6c93853 100644 --- a/drivers/mtd/nand/raw/brcmnand/iproc_nand.c +++ b/drivers/mtd/nand/raw/brcmnand/iproc_nand.c @@ -4,7 +4,6 @@ * Copyright (C) 2015 Broadcom Corporation */ -#include #include #include #include diff --git a/drivers/mtd/nand/raw/cortina_nand.c b/drivers/mtd/nand/raw/cortina_nand.c index b7be6602f7c..06918a46e93 100644 --- a/drivers/mtd/nand/raw/cortina_nand.c +++ b/drivers/mtd/nand/raw/cortina_nand.c @@ -3,7 +3,6 @@ * Copyright (c) 2020, Cortina Access Inc.. */ -#include #include #include #include diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c index 71bbb8231bf..d4daf06b8de 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -28,7 +28,7 @@ - */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c index c827f80281c..b2401116689 100644 --- a/drivers/mtd/nand/raw/denali.c +++ b/drivers/mtd/nand/raw/denali.c @@ -5,7 +5,6 @@ * Copyright (C) 2009-2010, Intel Corporation and its suppliers. */ -#include #include #include #include diff --git a/drivers/mtd/nand/raw/denali_spl.c b/drivers/mtd/nand/raw/denali_spl.c index 165a23312cb..b1e2c9d8161 100644 --- a/drivers/mtd/nand/raw/denali_spl.c +++ b/drivers/mtd/nand/raw/denali_spl.c @@ -4,7 +4,7 @@ * Copyright (C) 2014-2015 Masahiro Yamada */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c index 7853c3f74e2..157330cb287 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_nand.c +++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c @@ -7,7 +7,7 @@ * Scott Wood */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/fsl_elbc_spl.c b/drivers/mtd/nand/raw/fsl_elbc_spl.c index 26aaab08e89..17b8ef7ff4b 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_spl.c +++ b/drivers/mtd/nand/raw/fsl_elbc_spl.c @@ -9,7 +9,7 @@ * Author: Scott Wood */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/fsl_ifc_nand.c b/drivers/mtd/nand/raw/fsl_ifc_nand.c index 1d7c1fddd3f..857d50ef9b0 100644 --- a/drivers/mtd/nand/raw/fsl_ifc_nand.c +++ b/drivers/mtd/nand/raw/fsl_ifc_nand.c @@ -6,7 +6,7 @@ * Authors: Dipen Dudhat */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/fsl_ifc_spl.c b/drivers/mtd/nand/raw/fsl_ifc_spl.c index 69d26f1f79a..c2ebee94870 100644 --- a/drivers/mtd/nand/raw/fsl_ifc_spl.c +++ b/drivers/mtd/nand/raw/fsl_ifc_spl.c @@ -6,7 +6,7 @@ * Author: Dipen Dudhat */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/kirkwood_nand.c b/drivers/mtd/nand/raw/kirkwood_nand.c index 621d2d232c8..cd182be268d 100644 --- a/drivers/mtd/nand/raw/kirkwood_nand.c +++ b/drivers/mtd/nand/raw/kirkwood_nand.c @@ -5,7 +5,6 @@ * Written-by: Prafulla Wadaskar */ -#include #include #include #include diff --git a/drivers/mtd/nand/raw/kmeter1_nand.c b/drivers/mtd/nand/raw/kmeter1_nand.c index dfe73d64e46..e9398eb4093 100644 --- a/drivers/mtd/nand/raw/kmeter1_nand.c +++ b/drivers/mtd/nand/raw/kmeter1_nand.c @@ -4,7 +4,7 @@ * Heiko Schocher, DENX Software Engineering, hs@denx.de */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c index f8ae216d56c..c89661badbf 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c @@ -19,7 +19,7 @@ * should not rely on the ECC validity. */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c index b21a0b9d293..4d643bc64bc 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c @@ -10,7 +10,7 @@ * Author: Kevin Wells */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c index dbdc5b0bca1..0750b38f708 100644 --- a/drivers/mtd/nand/raw/mxc_nand.c +++ b/drivers/mtd/nand/raw/mxc_nand.c @@ -5,7 +5,7 @@ * Copyright 2009 Ilya Yanok, */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/mxc_nand_spl.c b/drivers/mtd/nand/raw/mxc_nand_spl.c index a855c9987f8..c5872848954 100644 --- a/drivers/mtd/nand/raw/mxc_nand_spl.c +++ b/drivers/mtd/nand/raw/mxc_nand_spl.c @@ -10,7 +10,7 @@ * Stefan Roese, DENX Software Engineering, sr at denx.de. */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/mxic_nand.c b/drivers/mtd/nand/raw/mxic_nand.c index 6abdc24bd30..0e54b5f6938 100644 --- a/drivers/mtd/nand/raw/mxic_nand.c +++ b/drivers/mtd/nand/raw/mxic_nand.c @@ -6,7 +6,6 @@ * Zhengxun Li */ -#include #include #include #include diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index fd65772af80..11b0247b284 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -13,7 +13,6 @@ * Copyright 2017-2019 NXP */ -#include #include #include #include diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c index f7d3f02f85a..c8e064347ad 100644 --- a/drivers/mtd/nand/raw/mxs_nand_spl.c +++ b/drivers/mtd/nand/raw/mxs_nand_spl.c @@ -4,7 +4,6 @@ * Copyright 2019 NXP * Author: Tim Harvey */ -#include #include #include #include diff --git a/drivers/mtd/nand/raw/nand.c b/drivers/mtd/nand/raw/nand.c index b591170346d..36054492e18 100644 --- a/drivers/mtd/nand/raw/nand.c +++ b/drivers/mtd/nand/raw/nand.c @@ -5,7 +5,7 @@ * Ladislav Michl */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 688d17ba3c2..18b95caffef 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -28,7 +28,6 @@ */ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt -#include #include #include #include diff --git a/drivers/mtd/nand/raw/nand_bbt.c b/drivers/mtd/nand/raw/nand_bbt.c index cd451870a6f..1fb8535ab05 100644 --- a/drivers/mtd/nand/raw/nand_bbt.c +++ b/drivers/mtd/nand/raw/nand_bbt.c @@ -57,7 +57,6 @@ * */ -#include #include #include #include diff --git a/drivers/mtd/nand/raw/nand_bch.c b/drivers/mtd/nand/raw/nand_bch.c index bb48ebbb96c..f317cc26c90 100644 --- a/drivers/mtd/nand/raw/nand_bch.c +++ b/drivers/mtd/nand/raw/nand_bch.c @@ -7,7 +7,6 @@ * */ -#include #include #include #include diff --git a/drivers/mtd/nand/raw/nand_ecc.c b/drivers/mtd/nand/raw/nand_ecc.c index 2bc329be1a3..0530ccb0722 100644 --- a/drivers/mtd/nand/raw/nand_ecc.c +++ b/drivers/mtd/nand/raw/nand_ecc.c @@ -22,7 +22,6 @@ * this file might be covered by the GNU General Public License. */ -#include #include #include diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index be60d6d9d99..4f46378ffe1 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -6,7 +6,6 @@ * published by the Free Software Foundation. * */ -#include #include #include diff --git a/drivers/mtd/nand/raw/nand_spl_load.c b/drivers/mtd/nand/raw/nand_spl_load.c index 7ac9bf4d120..87af675c139 100644 --- a/drivers/mtd/nand/raw/nand_spl_load.c +++ b/drivers/mtd/nand/raw/nand_spl_load.c @@ -4,7 +4,7 @@ * Heiko Schocher, DENX Software Engineering, hs@denx.de. */ -#include +#include #include /* diff --git a/drivers/mtd/nand/raw/nand_spl_simple.c b/drivers/mtd/nand/raw/nand_spl_simple.c index 80d6e0e1e4e..c0956ab0e49 100644 --- a/drivers/mtd/nand/raw/nand_spl_simple.c +++ b/drivers/mtd/nand/raw/nand_spl_simple.c @@ -4,7 +4,7 @@ * Stefan Roese, DENX Software Engineering, sr@denx.de. */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/nand_timings.c b/drivers/mtd/nand/raw/nand_timings.c index e6aa7903913..c1bac1d01cc 100644 --- a/drivers/mtd/nand/raw/nand_timings.c +++ b/drivers/mtd/nand/raw/nand_timings.c @@ -8,7 +8,6 @@ * published by the Free Software Foundation. * */ -#include #include #include #include diff --git a/drivers/mtd/nand/raw/nand_util.c b/drivers/mtd/nand/raw/nand_util.c index 72cc24f4037..fda4239fa79 100644 --- a/drivers/mtd/nand/raw/nand_util.c +++ b/drivers/mtd/nand/raw/nand_util.c @@ -18,7 +18,6 @@ * Copyright 2010 Freescale Semiconductor */ -#include #include #include #include diff --git a/drivers/mtd/nand/raw/omap_elm.c b/drivers/mtd/nand/raw/omap_elm.c index 015ec9bc2de..61751b9ae2d 100644 --- a/drivers/mtd/nand/raw/omap_elm.c +++ b/drivers/mtd/nand/raw/omap_elm.c @@ -12,7 +12,6 @@ * sets in uboot */ -#include #include #include #include diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index 2f8fa7d73d2..92a92ad63a0 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -4,7 +4,7 @@ * Rohit Choraria */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/pxa3xx_nand.c b/drivers/mtd/nand/raw/pxa3xx_nand.c index 1d9a6d107b1..17c5601bead 100644 --- a/drivers/mtd/nand/raw/pxa3xx_nand.c +++ b/drivers/mtd/nand/raw/pxa3xx_nand.c @@ -6,7 +6,6 @@ * Copyright © 2006 Marvell International Ltd. */ -#include #include #include #include diff --git a/drivers/mtd/nand/raw/rockchip_nfc.c b/drivers/mtd/nand/raw/rockchip_nfc.c index 088cc7fead2..f730e15d041 100644 --- a/drivers/mtd/nand/raw/rockchip_nfc.c +++ b/drivers/mtd/nand/raw/rockchip_nfc.c @@ -5,7 +5,6 @@ * Author: Yifeng Zhao */ -#include #include #include #include diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c index d284b8cbb12..083ea4c5a74 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_MTD -#include #include #include #include diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi_nand.c index 0b5b74dc242..34197bb09a1 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -25,7 +25,6 @@ */ #include -#include #include #include #include diff --git a/drivers/mtd/nand/raw/sunxi_nand_spl.c b/drivers/mtd/nand/raw/sunxi_nand_spl.c index c9b8c78ed75..040138e2559 100644 --- a/drivers/mtd/nand/raw/sunxi_nand_spl.c +++ b/drivers/mtd/nand/raw/sunxi_nand_spl.c @@ -6,7 +6,6 @@ #include #include -#include #include #include #include diff --git a/drivers/mtd/nand/raw/tegra_nand.c b/drivers/mtd/nand/raw/tegra_nand.c index 6086ecdfa3d..8285f87359e 100644 --- a/drivers/mtd/nand/raw/tegra_nand.c +++ b/drivers/mtd/nand/raw/tegra_nand.c @@ -6,7 +6,6 @@ * (C) Copyright 2006 DENX Software Engineering */ -#include #include #include #include diff --git a/drivers/mtd/nand/raw/vf610_nfc.c b/drivers/mtd/nand/raw/vf610_nfc.c index d2363a0662e..10265950368 100644 --- a/drivers/mtd/nand/raw/vf610_nfc.c +++ b/drivers/mtd/nand/raw/vf610_nfc.c @@ -21,7 +21,7 @@ * - HW ECC: Only 24 and 32-bit error correction implemented. */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/zynq_nand.c b/drivers/mtd/nand/raw/zynq_nand.c index bacaf13c570..5f90171a6fe 100644 --- a/drivers/mtd/nand/raw/zynq_nand.c +++ b/drivers/mtd/nand/raw/zynq_nand.c @@ -6,7 +6,6 @@ * This driver is based on plat_nand.c and mxc_nand.c drivers */ -#include #include #include #include diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 62c28aa422d..ef50237f10e 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -21,7 +21,6 @@ #include #include #else -#include #include #include #include diff --git a/drivers/mtd/nvmxip/nvmxip-uclass.c b/drivers/mtd/nvmxip/nvmxip-uclass.c index 9a316d1de39..95dfa58def1 100644 --- a/drivers/mtd/nvmxip/nvmxip-uclass.c +++ b/drivers/mtd/nvmxip/nvmxip-uclass.c @@ -6,7 +6,6 @@ * Abdellatif El Khlifi */ -#include #include #include #if CONFIG_IS_ENABLED(SANDBOX64) diff --git a/drivers/mtd/nvmxip/nvmxip.c b/drivers/mtd/nvmxip/nvmxip.c index 0bd98d64275..229938db380 100644 --- a/drivers/mtd/nvmxip/nvmxip.c +++ b/drivers/mtd/nvmxip/nvmxip.c @@ -6,7 +6,6 @@ * Abdellatif El Khlifi */ -#include #include #include #include diff --git a/drivers/mtd/nvmxip/nvmxip_qspi.c b/drivers/mtd/nvmxip/nvmxip_qspi.c index 4d7471118a4..460887c7da3 100644 --- a/drivers/mtd/nvmxip/nvmxip_qspi.c +++ b/drivers/mtd/nvmxip/nvmxip_qspi.c @@ -6,7 +6,6 @@ * Abdellatif El Khlifi */ -#include #include #include #include diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index 762b01c1b0f..edecb841338 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -19,7 +19,6 @@ * published by the Free Software Foundation. */ -#include #include #include #include diff --git a/drivers/mtd/onenand/onenand_bbt.c b/drivers/mtd/onenand/onenand_bbt.c index cc1e449f4a7..6af1cb2ec19 100644 --- a/drivers/mtd/onenand/onenand_bbt.c +++ b/drivers/mtd/onenand/onenand_bbt.c @@ -14,7 +14,6 @@ * published by the Free Software Foundation. */ -#include #include #include #include diff --git a/drivers/mtd/onenand/onenand_spl.c b/drivers/mtd/onenand/onenand_spl.c index 2699958a5de..a9d54a243ad 100644 --- a/drivers/mtd/onenand/onenand_spl.c +++ b/drivers/mtd/onenand/onenand_spl.c @@ -7,9 +7,10 @@ * Kyungmin Park */ -#include +#include #include #include +#include #include #include diff --git a/drivers/mtd/onenand/onenand_uboot.c b/drivers/mtd/onenand/onenand_uboot.c index ecacabefadc..db0ac6c1fb8 100644 --- a/drivers/mtd/onenand/onenand_uboot.c +++ b/drivers/mtd/onenand/onenand_uboot.c @@ -13,7 +13,7 @@ * OneNAND initialization at U-Boot */ -#include +#include #include #include #include diff --git a/drivers/mtd/onenand/samsung.c b/drivers/mtd/onenand/samsung.c index c415e5149a0..ccfdad4913e 100644 --- a/drivers/mtd/onenand/samsung.c +++ b/drivers/mtd/onenand/samsung.c @@ -9,7 +9,6 @@ * Emulate the pseudo BufferRAM */ -#include #include #include #include diff --git a/drivers/mtd/renesas_rpc_hf.c b/drivers/mtd/renesas_rpc_hf.c index 979b64d4a2f..8dcffde9aa3 100644 --- a/drivers/mtd/renesas_rpc_hf.c +++ b/drivers/mtd/renesas_rpc_hf.c @@ -7,7 +7,6 @@ * Copyright (C) 2017 Marek Vasut */ -#include #include #include #include diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c index cdbdbd6ea58..73eea922c33 100644 --- a/drivers/mtd/spi/fsl_espi_spl.c +++ b/drivers/mtd/spi/fsl_espi_spl.c @@ -3,7 +3,7 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c index 4fe547171a5..2d5a16bf6a2 100644 --- a/drivers/mtd/spi/sandbox.c +++ b/drivers/mtd/spi/sandbox.c @@ -10,7 +10,6 @@ #define LOG_CATEGORY UCLASS_SPI_FLASH -#include #include #include #include diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c index 2da0cf0dcf9..a4d15bd64aa 100644 --- a/drivers/mtd/spi/sf-uclass.c +++ b/drivers/mtd/spi/sf-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_SPI_FLASH -#include #include #include #include diff --git a/drivers/mtd/spi/sf_bootdev.c b/drivers/mtd/spi/sf_bootdev.c index d6b47b11ce4..017a74a3016 100644 --- a/drivers/mtd/spi/sf_bootdev.c +++ b/drivers/mtd/spi/sf_bootdev.c @@ -5,7 +5,6 @@ * Copyright 2022 Google LLC */ -#include #include #include #include diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c index 6a0d953a729..6db24189c8e 100644 --- a/drivers/mtd/spi/sf_dataflash.c +++ b/drivers/mtd/spi/sf_dataflash.c @@ -6,7 +6,6 @@ * Haikun Wang (haikun.wang@freescale.com) */ -#include #include #include #include diff --git a/drivers/mtd/spi/sf_mtd.c b/drivers/mtd/spi/sf_mtd.c index 071b25ac67f..7342f26d88e 100644 --- a/drivers/mtd/spi/sf_mtd.c +++ b/drivers/mtd/spi/sf_mtd.c @@ -3,7 +3,6 @@ * Copyright (C) 2012-2014 Daniel Schwierzeck, daniel.schwierzeck@gmail.com */ -#include #include #include #include diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index de6516f1065..7100b64bf22 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -7,7 +7,6 @@ * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. */ -#include #include #include #include diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index f86003ca8c0..982dd251150 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -9,7 +9,6 @@ * Synced from Linux v4.19 */ -#include #include #include #include diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 4e83b8c94c9..684206ea07d 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -6,7 +6,6 @@ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ */ -#include #include #include diff --git a/drivers/mtd/spi/spi-nor-tiny.c b/drivers/mtd/spi/spi-nor-tiny.c index 0719fe845ca..5755c5eed29 100644 --- a/drivers/mtd/spi/spi-nor-tiny.c +++ b/drivers/mtd/spi/spi-nor-tiny.c @@ -9,7 +9,6 @@ * Synced from Linux v4.19 */ -#include #include #include #include diff --git a/drivers/mtd/stm32_flash.c b/drivers/mtd/stm32_flash.c index 4523344ba6b..ec83be6b51f 100644 --- a/drivers/mtd/stm32_flash.c +++ b/drivers/mtd/stm32_flash.c @@ -4,7 +4,7 @@ * Kamil Lulko, */ -#include +#include #include #include #include diff --git a/drivers/mtd/ubispl/ubispl.c b/drivers/mtd/ubispl/ubispl.c index b58d8e8d565..90a7c4c6f9e 100644 --- a/drivers/mtd/ubispl/ubispl.c +++ b/drivers/mtd/ubispl/ubispl.c @@ -7,7 +7,6 @@ * Copyright (c) International Business Machines Corp., 2006 */ -#include #include #include #include diff --git a/drivers/mux/mmio.c b/drivers/mux/mmio.c index 00e0282dcc0..e1125458a62 100644 --- a/drivers/mux/mmio.c +++ b/drivers/mux/mmio.c @@ -6,7 +6,6 @@ * Copyright (C) 2017 Pengutronix, Philipp Zabel * Copyright (C) 2019 Texas Instrument, Jean-jacques Hiblot */ -#include #include #include #include diff --git a/drivers/mux/mux-uclass.c b/drivers/mux/mux-uclass.c index 8833888ded3..8a3e7a84f41 100644 --- a/drivers/mux/mux-uclass.c +++ b/drivers/mux/mux-uclass.c @@ -13,7 +13,6 @@ #define LOG_CATEGORY UCLASS_MUX -#include #include #include #include diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index b2d7b499766..b4ff033afa9 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -193,6 +193,24 @@ config CALXEDA_XGMAC This driver supports the XGMAC in Calxeda Highbank and Midway machines. +config DWC_ETH_XGMAC + bool "Synopsys DWC Ethernet XGMAC device support" + select PHYLIB + help + This driver supports the Synopsys Designware Ethernet XGMAC (10G + Ethernet MAC) IP block. The IP supports many options for bus type, + clocking/reset structure, and feature list. + +config DWC_ETH_XGMAC_SOCFPGA + bool "Synopsys DWC Ethernet XGMAC device support for SOCFPGA" + select REGMAP + select SYSCON + depends on DWC_ETH_XGMAC + default y if TARGET_SOCFPGA_AGILEX5 + help + The Synopsys Designware Ethernet XGMAC IP block with specific + configuration used in Intel SoC FPGA chip. + config DRIVER_DM9000 bool "Davicom DM9000 controller driver" help diff --git a/drivers/net/Makefile b/drivers/net/Makefile index dc3404519d6..dce71685c3d 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -22,6 +22,8 @@ obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o obj-$(CONFIG_DWC_ETH_QOS_ROCKCHIP) += dwc_eth_qos_rockchip.o obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o +obj-$(CONFIG_DWC_ETH_XGMAC) += dwc_eth_xgmac.o +obj-$(CONFIG_DWC_ETH_XGMAC_SOCFPGA) += dwc_eth_xgmac_socfpga.o obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o obj-$(CONFIG_DWC_ETH_QOS_STM32) += dwc_eth_qos_stm32.o obj-$(CONFIG_E1000) += e1000.o diff --git a/drivers/net/ag7xxx.c b/drivers/net/ag7xxx.c index da1f3f45808..059a65d4661 100644 --- a/drivers/net/ag7xxx.c +++ b/drivers/net/ag7xxx.c @@ -6,7 +6,6 @@ * Copyright (C) 2019 Rosy Song */ -#include #include #include #include diff --git a/drivers/net/altera_tse.c b/drivers/net/altera_tse.c index e2340936fa6..c57aafd0026 100644 --- a/drivers/net/altera_tse.c +++ b/drivers/net/altera_tse.c @@ -8,7 +8,6 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#include #include #include #include diff --git a/drivers/net/aspeed_mdio.c b/drivers/net/aspeed_mdio.c index a99715a7282..f2e4392aa9a 100644 --- a/drivers/net/aspeed_mdio.c +++ b/drivers/net/aspeed_mdio.c @@ -7,7 +7,6 @@ * This file is inspired from the Linux kernel driver drivers/net/phy/mdio-aspeed.c */ -#include #include #include #include diff --git a/drivers/net/bcm-sf2-eth-gmac.c b/drivers/net/bcm-sf2-eth-gmac.c index cbe1e85222f..ba244b4a26e 100644 --- a/drivers/net/bcm-sf2-eth-gmac.c +++ b/drivers/net/bcm-sf2-eth-gmac.c @@ -11,7 +11,6 @@ #endif #include -#include #include #include #include diff --git a/drivers/net/bcm-sf2-eth.c b/drivers/net/bcm-sf2-eth.c index 1524f5c9989..c10719c6b51 100644 --- a/drivers/net/bcm-sf2-eth.c +++ b/drivers/net/bcm-sf2-eth.c @@ -3,7 +3,6 @@ * Copyright 2014 Broadcom Corporation. */ -#include #include #include #include diff --git a/drivers/net/bcm6348-eth.c b/drivers/net/bcm6348-eth.c index 15a94f6ce9a..f87db4ab46e 100644 --- a/drivers/net/bcm6348-eth.c +++ b/drivers/net/bcm6348-eth.c @@ -6,7 +6,6 @@ * Copyright (C) 2008 Maxime Bizon */ -#include #include #include #include diff --git a/drivers/net/bcm6368-eth.c b/drivers/net/bcm6368-eth.c index 9679a45b075..0601fcc42f5 100644 --- a/drivers/net/bcm6368-eth.c +++ b/drivers/net/bcm6368-eth.c @@ -6,7 +6,6 @@ * Copyright (C) 2008 Maxime Bizon */ -#include #include #include #include diff --git a/drivers/net/bnxt/bnxt.c b/drivers/net/bnxt/bnxt.c index 1c9a9962408..25fbcd7b116 100644 --- a/drivers/net/bnxt/bnxt.c +++ b/drivers/net/bnxt/bnxt.c @@ -3,7 +3,6 @@ * Copyright 2019-2021 Broadcom. */ -#include #include #include diff --git a/drivers/net/calxedaxgmac.c b/drivers/net/calxedaxgmac.c index eb1e2a756cd..ebb399457fb 100644 --- a/drivers/net/calxedaxgmac.c +++ b/drivers/net/calxedaxgmac.c @@ -3,7 +3,6 @@ * Copyright 2010-2011 Calxeda, Inc. */ -#include #include #include #include diff --git a/drivers/net/cortina_ni.c b/drivers/net/cortina_ni.c index ef6ecd88b0c..79026882800 100644 --- a/drivers/net/cortina_ni.c +++ b/drivers/net/cortina_ni.c @@ -7,7 +7,6 @@ * Ethernet MAC Driver for all supported CAxxxx SoCs */ -#include #include #include #include diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c index 4e7af95b41c..ce028f451f1 100644 --- a/drivers/net/dc2114x.c +++ b/drivers/net/dc2114x.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 682045cea2c..07b0f49ef58 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -8,7 +8,6 @@ * Designware ethernet IP driver for U-Boot */ -#include #include #include #include diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index bec8d67dad0..9e17f0b9c28 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -49,7 +49,6 @@ * TODO: external MII is not functional, only internal at the moment. */ -#include #include #include #include diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 32a5d52165a..67ac86f82bc 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -29,7 +29,6 @@ #define LOG_CATEGORY UCLASS_ETH -#include #include #include #include diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c index 9c4e3904413..d6bed278ca7 100644 --- a/drivers/net/dwc_eth_qos_imx.c +++ b/drivers/net/dwc_eth_qos_imx.c @@ -3,7 +3,6 @@ * Copyright 2022 NXP */ -#include #include #include #include diff --git a/drivers/net/dwc_eth_qos_qcom.c b/drivers/net/dwc_eth_qos_qcom.c index 8178138fc65..77d626393d5 100644 --- a/drivers/net/dwc_eth_qos_qcom.c +++ b/drivers/net/dwc_eth_qos_qcom.c @@ -5,7 +5,6 @@ * Qcom DWMAC specific glue layer */ -#include #include #include #include diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c index fa9e513faea..c4557e57988 100644 --- a/drivers/net/dwc_eth_qos_rockchip.c +++ b/drivers/net/dwc_eth_qos_rockchip.c @@ -8,7 +8,6 @@ * part in order to simplify future porting of fixes and support for other SoCs. */ -#include #include #include #include diff --git a/drivers/net/dwc_eth_qos_starfive.c b/drivers/net/dwc_eth_qos_starfive.c index 5be8ac0f1a5..09e714ce76a 100644 --- a/drivers/net/dwc_eth_qos_starfive.c +++ b/drivers/net/dwc_eth_qos_starfive.c @@ -4,7 +4,6 @@ * Author: Yanhong Wang */ -#include #include #include #include diff --git a/drivers/net/dwc_eth_xgmac.c b/drivers/net/dwc_eth_xgmac.c new file mode 100644 index 00000000000..d3e5f9255f5 --- /dev/null +++ b/drivers/net/dwc_eth_xgmac.c @@ -0,0 +1,1165 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023, Intel Corporation. + * + * Portions based on U-Boot's dwc_eth_qos.c. + */ + +/* + * This driver supports the Synopsys Designware Ethernet XGMAC (10G Ethernet + * MAC) IP block. The IP supports multiple options for bus type, clocking/ + * reset structure, and feature list. + * + * The driver is written such that generic core logic is kept separate from + * configuration-specific logic. Code that interacts with configuration- + * specific resources is split out into separate functions to avoid polluting + * common code. If/when this driver is enhanced to support multiple + * configurations, the core code should be adapted to call all configuration- + * specific functions through function pointers, with the definition of those + * function pointers being supplied by struct udevice_id xgmac_ids[]'s .data + * field. + * + * This configuration uses an AXI master/DMA bus, an AHB slave/register bus, + * contains the DMA, MTL, and MAC sub-blocks, and supports a single RGMII PHY. + * This configuration also has SW control over all clock and reset signals to + * the HW block. + */ + +#define LOG_CATEGORY UCLASS_ETH + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dwc_eth_xgmac.h" + +static void *xgmac_alloc_descs(struct xgmac_priv *xgmac, unsigned int num) +{ + return memalign(ARCH_DMA_MINALIGN, num * xgmac->desc_size); +} + +static void xgmac_free_descs(void *descs) +{ + free(descs); +} + +static struct xgmac_desc *xgmac_get_desc(struct xgmac_priv *xgmac, + unsigned int num, bool rx) +{ + return (rx ? xgmac->rx_descs : xgmac->tx_descs) + + (num * xgmac->desc_size); +} + +void xgmac_inval_desc_generic(void *desc) +{ + unsigned long start; + unsigned long end; + + if (!desc) { + pr_err("%s invalid input buffer\n", __func__); + return; + } + + start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); + end = ALIGN(start + sizeof(struct xgmac_desc), + ARCH_DMA_MINALIGN); + + invalidate_dcache_range(start, end); +} + +void xgmac_flush_desc_generic(void *desc) +{ + unsigned long start; + unsigned long end; + + if (!desc) { + pr_err("%s invalid input buffer\n", __func__); + return; + } + + start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); + end = ALIGN(start + sizeof(struct xgmac_desc), + ARCH_DMA_MINALIGN); + + flush_dcache_range(start, end); +} + +void xgmac_inval_buffer_generic(void *buf, size_t size) +{ + unsigned long start; + unsigned long end; + + if (!buf) { + pr_err("%s invalid input buffer\n", __func__); + return; + } + + start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); + end = ALIGN((unsigned long)buf + size, + ARCH_DMA_MINALIGN); + + invalidate_dcache_range(start, end); +} + +void xgmac_flush_buffer_generic(void *buf, size_t size) +{ + unsigned long start; + unsigned long end; + + if (!buf) { + pr_err("%s invalid input buffer\n", __func__); + return; + } + + start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); + end = ALIGN((unsigned long)buf + size, + ARCH_DMA_MINALIGN); + + flush_dcache_range(start, end); +} + +static int xgmac_mdio_wait_idle(struct xgmac_priv *xgmac) +{ + return wait_for_bit_le32(&xgmac->mac_regs->mdio_data, + XGMAC_MAC_MDIO_ADDRESS_SBUSY, false, + XGMAC_TIMEOUT_100MS, true); +} + +static int xgmac_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad, + int mdio_reg) +{ + struct xgmac_priv *xgmac = bus->priv; + u32 val; + u32 hw_addr; + int ret; + + debug("%s(dev=%p, addr=0x%x, reg=%d):\n", __func__, xgmac->dev, mdio_addr, + mdio_reg); + + ret = xgmac_mdio_wait_idle(xgmac); + if (ret) { + pr_err("MDIO not idle at entry: %d\n", ret); + return ret; + } + + /* Set clause 22 format */ + val = BIT(mdio_addr); + writel(val, &xgmac->mac_regs->mdio_clause_22_port); + + hw_addr = (mdio_addr << XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT) | + (mdio_reg & XGMAC_MAC_MDIO_REG_ADDR_C22P_MASK); + + val = xgmac->config->config_mac_mdio << + XGMAC_MAC_MDIO_ADDRESS_CR_SHIFT; + + val |= XGMAC_MAC_MDIO_ADDRESS_SADDR | + XGMAC_MDIO_SINGLE_CMD_ADDR_CMD_READ | + XGMAC_MAC_MDIO_ADDRESS_SBUSY; + + ret = xgmac_mdio_wait_idle(xgmac); + if (ret) { + pr_err("MDIO not idle at entry: %d\n", ret); + return ret; + } + + writel(hw_addr, &xgmac->mac_regs->mdio_address); + writel(val, &xgmac->mac_regs->mdio_data); + + ret = xgmac_mdio_wait_idle(xgmac); + if (ret) { + pr_err("MDIO read didn't complete: %d\n", ret); + return ret; + } + + val = readl(&xgmac->mac_regs->mdio_data); + val &= XGMAC_MAC_MDIO_DATA_GD_MASK; + + debug("%s: val=0x%x\n", __func__, val); + + return val; +} + +static int xgmac_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad, + int mdio_reg, u16 mdio_val) +{ + struct xgmac_priv *xgmac = bus->priv; + u32 val; + u32 hw_addr; + int ret; + + debug("%s(dev=%p, addr=0x%x, reg=%d, val=0x%x):\n", __func__, xgmac->dev, + mdio_addr, mdio_reg, mdio_val); + + ret = xgmac_mdio_wait_idle(xgmac); + if (ret) { + pr_err("MDIO not idle at entry: %d\n", ret); + return ret; + } + + /* Set clause 22 format */ + val = BIT(mdio_addr); + writel(val, &xgmac->mac_regs->mdio_clause_22_port); + + hw_addr = (mdio_addr << XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT) | + (mdio_reg & XGMAC_MAC_MDIO_REG_ADDR_C22P_MASK); + + hw_addr |= (mdio_reg >> XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT) << + XGMAC_MAC_MDIO_ADDRESS_DA_SHIFT; + + val = (xgmac->config->config_mac_mdio << + XGMAC_MAC_MDIO_ADDRESS_CR_SHIFT); + + val |= XGMAC_MAC_MDIO_ADDRESS_SADDR | + mdio_val | XGMAC_MDIO_SINGLE_CMD_ADDR_CMD_WRITE | + XGMAC_MAC_MDIO_ADDRESS_SBUSY; + + ret = xgmac_mdio_wait_idle(xgmac); + if (ret) { + pr_err("MDIO not idle at entry: %d\n", ret); + return ret; + } + + writel(hw_addr, &xgmac->mac_regs->mdio_address); + writel(val, &xgmac->mac_regs->mdio_data); + + ret = xgmac_mdio_wait_idle(xgmac); + if (ret) { + pr_err("MDIO write didn't complete: %d\n", ret); + return ret; + } + + return 0; +} + +static int xgmac_set_full_duplex(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + clrbits_le32(&xgmac->mac_regs->mac_extended_conf, XGMAC_MAC_EXT_CONF_HD); + + return 0; +} + +static int xgmac_set_half_duplex(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + setbits_le32(&xgmac->mac_regs->mac_extended_conf, XGMAC_MAC_EXT_CONF_HD); + + /* WAR: Flush TX queue when switching to half-duplex */ + setbits_le32(&xgmac->mtl_regs->txq0_operation_mode, + XGMAC_MTL_TXQ0_OPERATION_MODE_FTQ); + + return 0; +} + +static int xgmac_set_gmii_speed(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + u32 val; + + debug("%s(dev=%p):\n", __func__, dev); + + val = XGMAC_MAC_CONF_SS_1G_GMII << XGMAC_MAC_CONF_SS_SHIFT; + writel(val, &xgmac->mac_regs->tx_configuration); + + return 0; +} + +static int xgmac_set_mii_speed_100(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + u32 val; + + debug("%s(dev=%p):\n", __func__, dev); + + val = XGMAC_MAC_CONF_SS_100M_MII << XGMAC_MAC_CONF_SS_SHIFT; + writel(val, &xgmac->mac_regs->tx_configuration); + + return 0; +} + +static int xgmac_set_mii_speed_10(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + u32 val; + + debug("%s(dev=%p):\n", __func__, dev); + + val = XGMAC_MAC_CONF_SS_2_10M_MII << XGMAC_MAC_CONF_SS_SHIFT; + writel(val, &xgmac->mac_regs->tx_configuration); + + return 0; +} + +static int xgmac_adjust_link(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + int ret; + bool en_calibration; + + debug("%s(dev=%p):\n", __func__, dev); + + if (xgmac->phy->duplex) + ret = xgmac_set_full_duplex(dev); + else + ret = xgmac_set_half_duplex(dev); + if (ret < 0) { + pr_err("xgmac_set_*_duplex() failed: %d\n", ret); + return ret; + } + + switch (xgmac->phy->speed) { + case SPEED_1000: + en_calibration = true; + ret = xgmac_set_gmii_speed(dev); + break; + case SPEED_100: + en_calibration = true; + ret = xgmac_set_mii_speed_100(dev); + break; + case SPEED_10: + en_calibration = false; + ret = xgmac_set_mii_speed_10(dev); + break; + default: + pr_err("invalid speed %d\n", xgmac->phy->speed); + return -EINVAL; + } + if (ret < 0) { + pr_err("xgmac_set_*mii_speed*() failed: %d\n", ret); + return ret; + } + + if (en_calibration) { + ret = xgmac->config->ops->xgmac_calibrate_pads(dev); + if (ret < 0) { + pr_err("xgmac_calibrate_pads() failed: %d\n", + ret); + return ret; + } + } else { + ret = xgmac->config->ops->xgmac_disable_calibration(dev); + if (ret < 0) { + pr_err("xgmac_disable_calibration() failed: %d\n", + ret); + return ret; + } + } + + return 0; +} + +static int xgmac_write_hwaddr(struct udevice *dev) +{ + struct eth_pdata *plat = dev_get_plat(dev); + struct xgmac_priv *xgmac = dev_get_priv(dev); + u32 val; + + /* + * This function may be called before start() or after stop(). At that + * time, on at least some configurations of the XGMAC HW, all clocks to + * the XGMAC HW block will be stopped, and a reset signal applied. If + * any register access is attempted in this state, bus timeouts or CPU + * hangs may occur. This check prevents that. + * + * A simple solution to this problem would be to not implement + * write_hwaddr(), since start() always writes the MAC address into HW + * anyway. However, it is desirable to implement write_hwaddr() to + * support the case of SW that runs subsequent to U-Boot which expects + * the MAC address to already be programmed into the XGMAC registers, + * which must happen irrespective of whether the U-Boot user (or + * scripts) actually made use of the XGMAC device, and hence + * irrespective of whether start() was ever called. + * + */ + if (!xgmac->config->reg_access_always_ok && !xgmac->reg_access_ok) + return 0; + + /* Update the MAC address */ + val = (plat->enetaddr[5] << 8) | + (plat->enetaddr[4]); + writel(val, &xgmac->mac_regs->address0_high); + val = (plat->enetaddr[3] << 24) | + (plat->enetaddr[2] << 16) | + (plat->enetaddr[1] << 8) | + (plat->enetaddr[0]); + writel(val, &xgmac->mac_regs->address0_low); + return 0; +} + +static int xgmac_read_rom_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct xgmac_priv *xgmac = dev_get_priv(dev); + int ret; + + ret = xgmac->config->ops->xgmac_get_enetaddr(dev); + if (ret < 0) + return ret; + + return !is_valid_ethaddr(pdata->enetaddr); +} + +static int xgmac_get_phy_addr(struct xgmac_priv *priv, struct udevice *dev) +{ + struct ofnode_phandle_args phandle_args; + int reg; + + if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, + &phandle_args)) { + debug("Failed to find phy-handle"); + return -ENODEV; + } + + priv->phy_of_node = phandle_args.node; + + reg = ofnode_read_u32_default(phandle_args.node, "reg", 0); + + return reg; +} + +static int xgmac_start(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + int ret, i; + u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl; + ulong last_rx_desc; + ulong desc_pad; + + struct xgmac_desc *tx_desc = NULL; + struct xgmac_desc *rx_desc = NULL; + int addr = -1; + + debug("%s(dev=%p):\n", __func__, dev); + + xgmac->tx_desc_idx = 0; + xgmac->rx_desc_idx = 0; + + ret = xgmac->config->ops->xgmac_start_resets(dev); + if (ret < 0) { + pr_err("xgmac_start_resets() failed: %d\n", ret); + goto err; + } + + xgmac->reg_access_ok = true; + + ret = wait_for_bit_le32(&xgmac->dma_regs->mode, + XGMAC_DMA_MODE_SWR, false, + xgmac->config->swr_wait, false); + if (ret) { + pr_err("XGMAC_DMA_MODE_SWR stuck: %d\n", ret); + goto err_stop_resets; + } + + ret = xgmac->config->ops->xgmac_calibrate_pads(dev); + if (ret < 0) { + pr_err("xgmac_calibrate_pads() failed: %d\n", ret); + goto err_stop_resets; + } + + /* + * if PHY was already connected and configured, + * don't need to reconnect/reconfigure again + */ + if (!xgmac->phy) { + addr = xgmac_get_phy_addr(xgmac, dev); + xgmac->phy = phy_connect(xgmac->mii, addr, dev, + xgmac->config->interface(dev)); + if (!xgmac->phy) { + pr_err("phy_connect() failed\n"); + goto err_stop_resets; + } + + if (xgmac->max_speed) { + ret = phy_set_supported(xgmac->phy, xgmac->max_speed); + if (ret) { + pr_err("phy_set_supported() failed: %d\n", ret); + goto err_shutdown_phy; + } + } + + xgmac->phy->node = xgmac->phy_of_node; + ret = phy_config(xgmac->phy); + if (ret < 0) { + pr_err("phy_config() failed: %d\n", ret); + goto err_shutdown_phy; + } + } + + ret = phy_startup(xgmac->phy); + if (ret < 0) { + pr_err("phy_startup() failed: %d\n", ret); + goto err_shutdown_phy; + } + + if (!xgmac->phy->link) { + pr_err("No link\n"); + goto err_shutdown_phy; + } + + ret = xgmac_adjust_link(dev); + if (ret < 0) { + pr_err("xgmac_adjust_link() failed: %d\n", ret); + goto err_shutdown_phy; + } + + /* Configure MTL */ + + /* Enable Store and Forward mode for TX */ + /* Program Tx operating mode */ + setbits_le32(&xgmac->mtl_regs->txq0_operation_mode, + XGMAC_MTL_TXQ0_OPERATION_MODE_TSF | + (XGMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED << + XGMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT)); + + /* Transmit Queue weight */ + writel(0x10, &xgmac->mtl_regs->txq0_quantum_weight); + + /* Enable Store and Forward mode for RX, since no jumbo frame */ + setbits_le32(&xgmac->mtl_regs->rxq0_operation_mode, + XGMAC_MTL_RXQ0_OPERATION_MODE_RSF); + + /* Transmit/Receive queue fifo size; use all RAM for 1 queue */ + val = readl(&xgmac->mac_regs->hw_feature1); + tx_fifo_sz = (val >> XGMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) & + XGMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK; + rx_fifo_sz = (val >> XGMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) & + XGMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK; + + /* + * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting. + * r/tqs is encoded as (n / 256) - 1. + */ + tqs = (128 << tx_fifo_sz) / 256 - 1; + rqs = (128 << rx_fifo_sz) / 256 - 1; + + clrsetbits_le32(&xgmac->mtl_regs->txq0_operation_mode, + XGMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK << + XGMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT, + tqs << XGMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT); + clrsetbits_le32(&xgmac->mtl_regs->rxq0_operation_mode, + XGMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK << + XGMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT, + rqs << XGMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT); + + setbits_le32(&xgmac->mtl_regs->rxq0_operation_mode, + XGMAC_MTL_RXQ0_OPERATION_MODE_EHFC); + + /* Configure MAC */ + clrsetbits_le32(&xgmac->mac_regs->rxq_ctrl0, + XGMAC_MAC_RXQ_CTRL0_RXQ0EN_MASK << + XGMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT, + xgmac->config->config_mac << + XGMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT); + + /* Multicast and Broadcast Queue Enable */ + setbits_le32(&xgmac->mac_regs->rxq_ctrl1, + XGMAC_MAC_RXQ_CTRL1_MCBCQEN); + + /* enable promise mode and receive all mode */ + setbits_le32(&xgmac->mac_regs->mac_packet_filter, + XGMAC_MAC_PACKET_FILTER_RA | + XGMAC_MAC_PACKET_FILTER_PR); + + /* Set TX flow control parameters */ + /* Set Pause Time */ + setbits_le32(&xgmac->mac_regs->q0_tx_flow_ctrl, + XGMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK << + XGMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT); + + /* Assign priority for RX flow control */ + clrbits_le32(&xgmac->mac_regs->rxq_ctrl2, + XGMAC_MAC_RXQ_CTRL2_PSRQ0_MASK << + XGMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT); + + /* Enable flow control */ + setbits_le32(&xgmac->mac_regs->q0_tx_flow_ctrl, + XGMAC_MAC_Q0_TX_FLOW_CTRL_TFE); + setbits_le32(&xgmac->mac_regs->rx_flow_ctrl, + XGMAC_MAC_RX_FLOW_CTRL_RFE); + + clrbits_le32(&xgmac->mac_regs->tx_configuration, + XGMAC_MAC_CONF_JD); + + clrbits_le32(&xgmac->mac_regs->rx_configuration, + XGMAC_MAC_CONF_JE | + XGMAC_MAC_CONF_GPSLCE | + XGMAC_MAC_CONF_WD); + + setbits_le32(&xgmac->mac_regs->rx_configuration, + XGMAC_MAC_CONF_ACS | + XGMAC_MAC_CONF_CST); + + ret = xgmac_write_hwaddr(dev); + if (ret < 0) { + pr_err("xgmac_write_hwaddr() failed: %d\n", ret); + goto err; + } + + /* Configure DMA */ + clrsetbits_le32(&xgmac->dma_regs->sysbus_mode, + XGMAC_DMA_SYSBUS_MODE_AAL, + XGMAC_DMA_SYSBUS_MODE_EAME | + XGMAC_DMA_SYSBUS_MODE_UNDEF); + + /* Enable OSP mode */ + setbits_le32(&xgmac->dma_regs->ch0_tx_control, + XGMAC_DMA_CH0_TX_CONTROL_OSP); + + /* RX buffer size. Must be a multiple of bus width */ + clrsetbits_le32(&xgmac->dma_regs->ch0_rx_control, + XGMAC_DMA_CH0_RX_CONTROL_RBSZ_MASK << + XGMAC_DMA_CH0_RX_CONTROL_RBSZ_SHIFT, + XGMAC_MAX_PACKET_SIZE << + XGMAC_DMA_CH0_RX_CONTROL_RBSZ_SHIFT); + + desc_pad = (xgmac->desc_size - sizeof(struct xgmac_desc)) / + xgmac->config->axi_bus_width; + + setbits_le32(&xgmac->dma_regs->ch0_control, + XGMAC_DMA_CH0_CONTROL_PBLX8 | + (desc_pad << XGMAC_DMA_CH0_CONTROL_DSL_SHIFT)); + + /* + * Burst length must be < 1/2 FIFO size. + * FIFO size in tqs is encoded as (n / 256) - 1. + * Each burst is n * 8 (PBLX8) * 16 (AXI width) == 128 bytes. + * Half of n * 256 is n * 128, so pbl == tqs, modulo the -1. + */ + pbl = tqs + 1; + if (pbl > 32) + pbl = 32; + + clrsetbits_le32(&xgmac->dma_regs->ch0_tx_control, + XGMAC_DMA_CH0_TX_CONTROL_TXPBL_MASK << + XGMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT, + pbl << XGMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT); + + clrsetbits_le32(&xgmac->dma_regs->ch0_rx_control, + XGMAC_DMA_CH0_RX_CONTROL_RXPBL_MASK << + XGMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT, + 8 << XGMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT); + + /* DMA performance configuration */ + val = (XGMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK << + XGMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) | + (XGMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK << + XGMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT) | + XGMAC_DMA_SYSBUS_MODE_EAME | + XGMAC_DMA_SYSBUS_MODE_BLEN16 | + XGMAC_DMA_SYSBUS_MODE_BLEN8 | + XGMAC_DMA_SYSBUS_MODE_BLEN4 | + XGMAC_DMA_SYSBUS_MODE_BLEN32; + + writel(val, &xgmac->dma_regs->sysbus_mode); + + /* Set up descriptors */ + + memset(xgmac->tx_descs, 0, xgmac->desc_size * XGMAC_DESCRIPTORS_TX); + memset(xgmac->rx_descs, 0, xgmac->desc_size * XGMAC_DESCRIPTORS_RX); + + for (i = 0; i < XGMAC_DESCRIPTORS_TX; i++) { + tx_desc = (struct xgmac_desc *)xgmac_get_desc(xgmac, i, false); + + xgmac->config->ops->xgmac_flush_desc(tx_desc); + } + + for (i = 0; i < XGMAC_DESCRIPTORS_RX; i++) { + rx_desc = (struct xgmac_desc *)xgmac_get_desc(xgmac, i, true); + + rx_desc->des0 = (uintptr_t)(xgmac->rx_dma_buf + + (i * XGMAC_MAX_PACKET_SIZE)); + rx_desc->des3 = XGMAC_DESC3_OWN; + /* Flush the cache to the memory */ + mb(); + xgmac->config->ops->xgmac_flush_desc(rx_desc); + xgmac->config->ops->xgmac_inval_buffer(xgmac->rx_dma_buf + + (i * XGMAC_MAX_PACKET_SIZE), + XGMAC_MAX_PACKET_SIZE); + } + + writel(0, &xgmac->dma_regs->ch0_txdesc_list_haddress); + writel((ulong)xgmac_get_desc(xgmac, 0, false), + &xgmac->dma_regs->ch0_txdesc_list_address); + writel(XGMAC_DESCRIPTORS_TX - 1, + &xgmac->dma_regs->ch0_txdesc_ring_length); + writel(0, &xgmac->dma_regs->ch0_rxdesc_list_haddress); + writel((ulong)xgmac_get_desc(xgmac, 0, true), + &xgmac->dma_regs->ch0_rxdesc_list_address); + writel(XGMAC_DESCRIPTORS_RX - 1, + &xgmac->dma_regs->ch0_rxdesc_ring_length); + + /* Enable everything */ + setbits_le32(&xgmac->dma_regs->ch0_tx_control, + XGMAC_DMA_CH0_TX_CONTROL_ST); + setbits_le32(&xgmac->dma_regs->ch0_rx_control, + XGMAC_DMA_CH0_RX_CONTROL_SR); + setbits_le32(&xgmac->mac_regs->tx_configuration, + XGMAC_MAC_CONF_TE); + setbits_le32(&xgmac->mac_regs->rx_configuration, + XGMAC_MAC_CONF_RE); + + /* TX tail pointer not written until we need to TX a packet */ + /* + * Point RX tail pointer at last descriptor. Ideally, we'd point at the + * first descriptor, implying all descriptors were available. However, + * that's not distinguishable from none of the descriptors being + * available. + */ + last_rx_desc = (ulong)xgmac_get_desc(xgmac, XGMAC_DESCRIPTORS_RX - 1, true); + writel(last_rx_desc, &xgmac->dma_regs->ch0_rxdesc_tail_pointer); + + xgmac->started = true; + + debug("%s: OK\n", __func__); + return 0; + +err_shutdown_phy: + phy_shutdown(xgmac->phy); +err_stop_resets: + xgmac->config->ops->xgmac_stop_resets(dev); +err: + pr_err("FAILED: %d\n", ret); + return ret; +} + +static void xgmac_stop(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + unsigned long start_time; + u32 val; + u32 trcsts; + u32 txqsts; + u32 prxq; + u32 rxqsts; + + debug("%s(dev=%p):\n", __func__, dev); + + if (!xgmac->started) + return; + xgmac->started = false; + xgmac->reg_access_ok = false; + + /* Disable TX DMA */ + clrbits_le32(&xgmac->dma_regs->ch0_tx_control, + XGMAC_DMA_CH0_TX_CONTROL_ST); + + /* Wait for TX all packets to drain out of MTL */ + start_time = get_timer(0); + + while (get_timer(start_time) < XGMAC_TIMEOUT_100MS) { + val = readl(&xgmac->mtl_regs->txq0_debug); + + trcsts = (val >> XGMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) & + XGMAC_MTL_TXQ0_DEBUG_TRCSTS_MASK; + + txqsts = val & XGMAC_MTL_TXQ0_DEBUG_TXQSTS; + + if (trcsts != XGMAC_MTL_TXQ0_DEBUG_TRCSTS_READ_STATE && !txqsts) + break; + } + + /* Turn off MAC TX and RX */ + clrbits_le32(&xgmac->mac_regs->tx_configuration, + XGMAC_MAC_CONF_RE); + clrbits_le32(&xgmac->mac_regs->rx_configuration, + XGMAC_MAC_CONF_RE); + + /* Wait for all RX packets to drain out of MTL */ + start_time = get_timer(0); + + while (get_timer(start_time) < XGMAC_TIMEOUT_100MS) { + val = readl(&xgmac->mtl_regs->rxq0_debug); + + prxq = (val >> XGMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT) & + XGMAC_MTL_RXQ0_DEBUG_PRXQ_MASK; + + rxqsts = (val >> XGMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) & + XGMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK; + + if (!prxq && !rxqsts) + break; + } + + /* Turn off RX DMA */ + clrbits_le32(&xgmac->dma_regs->ch0_rx_control, + XGMAC_DMA_CH0_RX_CONTROL_SR); + + if (xgmac->phy) + phy_shutdown(xgmac->phy); + + xgmac->config->ops->xgmac_stop_resets(dev); + + debug("%s: OK\n", __func__); +} + +static int xgmac_send(struct udevice *dev, void *packet, int length) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + struct xgmac_desc *tx_desc; + unsigned long start_time; + + debug("%s(dev=%p, packet=%p, length=%d):\n", __func__, dev, packet, + length); + + memcpy(xgmac->tx_dma_buf, packet, length); + xgmac->config->ops->xgmac_flush_buffer(xgmac->tx_dma_buf, length); + + tx_desc = xgmac_get_desc(xgmac, xgmac->tx_desc_idx, false); + xgmac->tx_desc_idx++; + xgmac->tx_desc_idx %= XGMAC_DESCRIPTORS_TX; + + tx_desc->des0 = (ulong)xgmac->tx_dma_buf; + tx_desc->des1 = 0; + tx_desc->des2 = length; + /* + * Make sure that if HW sees the _OWN write below, it will see all the + * writes to the rest of the descriptor too. + */ + mb(); + tx_desc->des3 = XGMAC_DESC3_OWN | XGMAC_DESC3_FD | XGMAC_DESC3_LD | length; + xgmac->config->ops->xgmac_flush_desc(tx_desc); + + writel((ulong)xgmac_get_desc(xgmac, xgmac->tx_desc_idx, false), + &xgmac->dma_regs->ch0_txdesc_tail_pointer); + + start_time = get_timer(0); + + while (get_timer(start_time) < XGMAC_TIMEOUT_100MS) { + xgmac->config->ops->xgmac_inval_desc(tx_desc); + if (!(readl(&tx_desc->des3) & XGMAC_DESC3_OWN)) + return 0; + } + debug("%s: TX timeout\n", __func__); + + return -ETIMEDOUT; +} + +static int xgmac_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + struct xgmac_desc *rx_desc; + int length; + + debug("%s(dev=%p, flags=0x%x):\n", __func__, dev, flags); + + rx_desc = xgmac_get_desc(xgmac, xgmac->rx_desc_idx, true); + xgmac->config->ops->xgmac_inval_desc(rx_desc); + if (rx_desc->des3 & XGMAC_DESC3_OWN) { + debug("%s: RX packet not available\n", __func__); + return -EAGAIN; + } + + *packetp = xgmac->rx_dma_buf + + (xgmac->rx_desc_idx * XGMAC_MAX_PACKET_SIZE); + length = rx_desc->des3 & XGMAC_RDES3_PKT_LENGTH_MASK; + debug("%s: *packetp=%p, length=%d\n", __func__, *packetp, length); + + xgmac->config->ops->xgmac_inval_buffer(*packetp, length); + + return length; +} + +static int xgmac_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + u32 idx, idx_mask = xgmac->desc_per_cacheline - 1; + uchar *packet_expected; + struct xgmac_desc *rx_desc; + + debug("%s(packet=%p, length=%d)\n", __func__, packet, length); + + packet_expected = xgmac->rx_dma_buf + + (xgmac->rx_desc_idx * XGMAC_MAX_PACKET_SIZE); + if (packet != packet_expected) { + debug("%s: Unexpected packet (expected %p)\n", __func__, + packet_expected); + return -EINVAL; + } + + xgmac->config->ops->xgmac_inval_buffer(packet, length); + + if ((xgmac->rx_desc_idx & idx_mask) == idx_mask) { + for (idx = xgmac->rx_desc_idx - idx_mask; + idx <= xgmac->rx_desc_idx; + idx++) { + rx_desc = xgmac_get_desc(xgmac, idx, true); + rx_desc->des0 = 0; + /* Flush the cache to the memory */ + mb(); + xgmac->config->ops->xgmac_flush_desc(rx_desc); + xgmac->config->ops->xgmac_inval_buffer(packet, length); + rx_desc->des0 = (u32)(ulong)(xgmac->rx_dma_buf + + (idx * XGMAC_MAX_PACKET_SIZE)); + rx_desc->des1 = 0; + rx_desc->des2 = 0; + /* + * Make sure that if HW sees the _OWN write below, + * it will see all the writes to the rest of the + * descriptor too. + */ + mb(); + rx_desc->des3 = XGMAC_DESC3_OWN; + xgmac->config->ops->xgmac_flush_desc(rx_desc); + } + writel((ulong)rx_desc, &xgmac->dma_regs->ch0_rxdesc_tail_pointer); + } + + xgmac->rx_desc_idx++; + xgmac->rx_desc_idx %= XGMAC_DESCRIPTORS_RX; + + return 0; +} + +static int xgmac_probe_resources_core(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + unsigned int desc_step; + int ret; + + debug("%s(dev=%p):\n", __func__, dev); + + /* Maximum distance between neighboring descriptors, in Bytes. */ + desc_step = sizeof(struct xgmac_desc); + + if (desc_step < ARCH_DMA_MINALIGN) { + /* + * The hardware implementation cannot place one descriptor + * per cacheline, it is necessary to place multiple descriptors + * per cacheline in memory and do cache management carefully. + */ + xgmac->desc_size = BIT(fls(desc_step) - 1); + } else { + xgmac->desc_size = ALIGN(sizeof(struct xgmac_desc), + (unsigned int)ARCH_DMA_MINALIGN); + } + xgmac->desc_per_cacheline = ARCH_DMA_MINALIGN / xgmac->desc_size; + + xgmac->tx_descs = xgmac_alloc_descs(xgmac, XGMAC_DESCRIPTORS_TX); + if (!xgmac->tx_descs) { + debug("%s: xgmac_alloc_descs(tx) failed\n", __func__); + ret = -ENOMEM; + goto err; + } + + xgmac->rx_descs = xgmac_alloc_descs(xgmac, XGMAC_DESCRIPTORS_RX); + if (!xgmac->rx_descs) { + debug("%s: xgmac_alloc_descs(rx) failed\n", __func__); + ret = -ENOMEM; + goto err_free_tx_descs; + } + + xgmac->tx_dma_buf = memalign(XGMAC_BUFFER_ALIGN, XGMAC_MAX_PACKET_SIZE); + if (!xgmac->tx_dma_buf) { + debug("%s: memalign(tx_dma_buf) failed\n", __func__); + ret = -ENOMEM; + goto err_free_descs; + } + debug("%s: tx_dma_buf=%p\n", __func__, xgmac->tx_dma_buf); + + xgmac->rx_dma_buf = memalign(XGMAC_BUFFER_ALIGN, XGMAC_RX_BUFFER_SIZE); + if (!xgmac->rx_dma_buf) { + debug("%s: memalign(rx_dma_buf) failed\n", __func__); + ret = -ENOMEM; + goto err_free_tx_dma_buf; + } + debug("%s: rx_dma_buf=%p\n", __func__, xgmac->rx_dma_buf); + + xgmac->rx_pkt = malloc(XGMAC_MAX_PACKET_SIZE); + if (!xgmac->rx_pkt) { + debug("%s: malloc(rx_pkt) failed\n", __func__); + ret = -ENOMEM; + goto err_free_rx_dma_buf; + } + debug("%s: rx_pkt=%p\n", __func__, xgmac->rx_pkt); + + xgmac->config->ops->xgmac_inval_buffer(xgmac->rx_dma_buf, + XGMAC_MAX_PACKET_SIZE * XGMAC_DESCRIPTORS_RX); + + debug("%s: OK\n", __func__); + return 0; + +err_free_rx_dma_buf: + free(xgmac->rx_dma_buf); +err_free_tx_dma_buf: + free(xgmac->tx_dma_buf); +err_free_descs: + xgmac_free_descs(xgmac->rx_descs); +err_free_tx_descs: + xgmac_free_descs(xgmac->tx_descs); +err: + + debug("%s: returns %d\n", __func__, ret); + return ret; +} + +static int xgmac_remove_resources_core(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + free(xgmac->rx_pkt); + free(xgmac->rx_dma_buf); + free(xgmac->tx_dma_buf); + xgmac_free_descs(xgmac->rx_descs); + xgmac_free_descs(xgmac->tx_descs); + + debug("%s: OK\n", __func__); + return 0; +} + +/* board-specific Ethernet Interface initializations. */ +__weak int board_interface_eth_init(struct udevice *dev, + phy_interface_t interface_type) +{ + return 0; +} + +static int xgmac_probe(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + int ret; + + debug("%s(dev=%p):\n", __func__, dev); + + xgmac->dev = dev; + xgmac->config = (void *)dev_get_driver_data(dev); + + xgmac->regs = dev_read_addr(dev); + if (xgmac->regs == FDT_ADDR_T_NONE) { + pr_err("dev_read_addr() failed\n"); + return -ENODEV; + } + xgmac->mac_regs = (void *)(xgmac->regs + XGMAC_MAC_REGS_BASE); + xgmac->mtl_regs = (void *)(xgmac->regs + XGMAC_MTL_REGS_BASE); + xgmac->dma_regs = (void *)(xgmac->regs + XGMAC_DMA_REGS_BASE); + + xgmac->max_speed = dev_read_u32_default(dev, "max-speed", 0); + + ret = xgmac_probe_resources_core(dev); + if (ret < 0) { + pr_err("xgmac_probe_resources_core() failed: %d\n", ret); + return ret; + } + + ret = xgmac->config->ops->xgmac_probe_resources(dev); + if (ret < 0) { + pr_err("xgmac_probe_resources() failed: %d\n", ret); + goto err_remove_resources_core; + } + + ret = xgmac->config->ops->xgmac_start_clks(dev); + if (ret < 0) { + pr_err("xgmac_start_clks() failed: %d\n", ret); + return ret; + } + + if (IS_ENABLED(CONFIG_DM_ETH_PHY)) + xgmac->mii = eth_phy_get_mdio_bus(dev); + + if (!xgmac->mii) { + xgmac->mii = mdio_alloc(); + if (!xgmac->mii) { + pr_err("mdio_alloc() failed\n"); + ret = -ENOMEM; + goto err_stop_clks; + } + xgmac->mii->read = xgmac_mdio_read; + xgmac->mii->write = xgmac_mdio_write; + xgmac->mii->priv = xgmac; + strcpy(xgmac->mii->name, dev->name); + + ret = mdio_register(xgmac->mii); + if (ret < 0) { + pr_err("mdio_register() failed: %d\n", ret); + goto err_free_mdio; + } + } + + if (IS_ENABLED(CONFIG_DM_ETH_PHY)) + eth_phy_set_mdio_bus(dev, xgmac->mii); + + debug("%s: OK\n", __func__); + return 0; + +err_free_mdio: + mdio_free(xgmac->mii); +err_stop_clks: + xgmac->config->ops->xgmac_stop_clks(dev); +err_remove_resources_core: + xgmac_remove_resources_core(dev); + + debug("%s: returns %d\n", __func__, ret); + return ret; +} + +static int xgmac_remove(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + mdio_unregister(xgmac->mii); + mdio_free(xgmac->mii); + xgmac->config->ops->xgmac_stop_clks(dev); + xgmac->config->ops->xgmac_remove_resources(dev); + + xgmac_remove_resources_core(dev); + + debug("%s: OK\n", __func__); + return 0; +} + +int xgmac_null_ops(struct udevice *dev) +{ + return 0; +} + +static const struct eth_ops xgmac_ops = { + .start = xgmac_start, + .stop = xgmac_stop, + .send = xgmac_send, + .recv = xgmac_recv, + .free_pkt = xgmac_free_pkt, + .write_hwaddr = xgmac_write_hwaddr, + .read_rom_hwaddr = xgmac_read_rom_hwaddr, +}; + +static const struct udevice_id xgmac_ids[] = { + { + .compatible = "intel,socfpga-dwxgmac", + .data = (ulong)&xgmac_socfpga_config + }, + { } +}; + +U_BOOT_DRIVER(eth_xgmac) = { + .name = "eth_xgmac", + .id = UCLASS_ETH, + .of_match = of_match_ptr(xgmac_ids), + .probe = xgmac_probe, + .remove = xgmac_remove, + .ops = &xgmac_ops, + .priv_auto = sizeof(struct xgmac_priv), + .plat_auto = sizeof(struct eth_pdata), +}; diff --git a/drivers/net/dwc_eth_xgmac.h b/drivers/net/dwc_eth_xgmac.h new file mode 100644 index 00000000000..259f815f3f2 --- /dev/null +++ b/drivers/net/dwc_eth_xgmac.h @@ -0,0 +1,298 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2023 Intel Coporation. + */ + +#include +#include + +/* Core registers */ + +#define XGMAC_MAC_REGS_BASE 0x000 + +struct xgmac_mac_regs { + u32 tx_configuration; /* 0x000 */ + u32 rx_configuration; /* 0x004 */ + u32 mac_packet_filter; /* 0x008 */ + u32 unused_00c[(0x070 - 0x00c) / 4]; /* 0x00c */ + u32 q0_tx_flow_ctrl; /* 0x070 */ + u32 unused_070[(0x090 - 0x074) / 4]; /* 0x074 */ + u32 rx_flow_ctrl; /* 0x090 */ + u32 unused_094[(0x0a0 - 0x094) / 4]; /* 0x094 */ + u32 rxq_ctrl0; /* 0x0a0 */ + u32 rxq_ctrl1; /* 0x0a4 */ + u32 rxq_ctrl2; /* 0x0a8 */ + u32 unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */ + u32 us_tic_counter; /* 0x0dc */ + u32 unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */ + u32 hw_feature0; /* 0x11c */ + u32 hw_feature1; /* 0x120 */ + u32 hw_feature2; /* 0x124 */ + u32 hw_feature3; /* 0x128 */ + u32 hw_feature4; /* 0x12c */ + u32 unused_130[(0x140 - 0x130) / 4]; /* 0x130 */ + u32 mac_extended_conf; /* 0x140 */ + u32 unused_144[(0x200 - 0x144) / 4]; /* 0x144 */ + u32 mdio_address; /* 0x200 */ + u32 mdio_data; /* 0x204 */ + u32 mdio_cont_write_addr; /* 0x208 */ + u32 mdio_cont_write_data; /* 0x20c */ + u32 mdio_cont_scan_port_enable; /* 0x210 */ + u32 mdio_intr_status; /* 0x214 */ + u32 mdio_intr_enable; /* 0x218 */ + u32 mdio_port_cnct_dsnct_status; /* 0x21c */ + u32 mdio_clause_22_port; /* 0x220 */ + u32 unused_224[(0x300 - 0x224) / 4]; /* 0x224 */ + u32 address0_high; /* 0x300 */ + u32 address0_low; /* 0x304 */ +}; + +#define XGMAC_TIMEOUT_100MS 100000 +#define XGMAC_MAC_CONF_SS_SHIFT 29 +#define XGMAC_MAC_CONF_SS_10G_XGMII 0 +#define XGMAC_MAC_CONF_SS_2_5G_GMII 2 +#define XGMAC_MAC_CONF_SS_1G_GMII 3 +#define XGMAC_MAC_CONF_SS_100M_MII 4 +#define XGMAC_MAC_CONF_SS_5G_XGMII 5 +#define XGMAC_MAC_CONF_SS_2_5G_XGMII 6 +#define XGMAC_MAC_CONF_SS_2_10M_MII 7 + +#define XGMAC_MAC_CONF_JD BIT(16) +#define XGMAC_MAC_CONF_JE BIT(8) +#define XGMAC_MAC_CONF_WD BIT(7) +#define XGMAC_MAC_CONF_GPSLCE BIT(6) +#define XGMAC_MAC_CONF_CST BIT(2) +#define XGMAC_MAC_CONF_ACS BIT(1) +#define XGMAC_MAC_CONF_TE BIT(0) +#define XGMAC_MAC_CONF_RE BIT(0) + +#define XGMAC_MAC_EXT_CONF_HD BIT(24) + +#define XGMAC_MAC_PACKET_FILTER_RA BIT(31) +#define XGMAC_MAC_PACKET_FILTER_PR BIT(0) + +#define XGMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16 +#define XGMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK GENMASK(15, 0) +#define XGMAC_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1) + +#define XGMAC_MAC_RX_FLOW_CTRL_RFE BIT(0) +#define XGMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0 +#define XGMAC_MAC_RXQ_CTRL0_RXQ0EN_MASK GENMASK(1, 0) +#define XGMAC_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0 +#define XGMAC_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2 +#define XGMAC_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1 + +#define XGMAC_MAC_RXQ_CTRL1_MCBCQEN BIT(15) + +#define XGMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0 +#define XGMAC_MAC_RXQ_CTRL2_PSRQ0_MASK GENMASK(7, 0) + +#define XGMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6 +#define XGMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK GENMASK(4, 0) +#define XGMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0 +#define XGMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK GENMASK(4, 0) + +#define XGMAC_MDIO_SINGLE_CMD_SHIFT 16 +#define XGMAC_MDIO_SINGLE_CMD_ADDR_CMD_READ 3 << XGMAC_MDIO_SINGLE_CMD_SHIFT +#define XGMAC_MDIO_SINGLE_CMD_ADDR_CMD_WRITE BIT(16) +#define XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT 16 +#define XGMAC_MAC_MDIO_ADDRESS_PA_MASK GENMASK(15, 0) +#define XGMAC_MAC_MDIO_ADDRESS_DA_SHIFT 21 +#define XGMAC_MAC_MDIO_ADDRESS_CR_SHIFT 19 +#define XGMAC_MAC_MDIO_ADDRESS_CR_100_150 0 +#define XGMAC_MAC_MDIO_ADDRESS_CR_150_250 1 +#define XGMAC_MAC_MDIO_ADDRESS_CR_250_300 2 +#define XGMAC_MAC_MDIO_ADDRESS_CR_300_350 3 +#define XGMAC_MAC_MDIO_ADDRESS_CR_350_400 4 +#define XGMAC_MAC_MDIO_ADDRESS_CR_400_500 5 +#define XGMAC_MAC_MDIO_ADDRESS_SADDR BIT(18) +#define XGMAC_MAC_MDIO_ADDRESS_SBUSY BIT(22) +#define XGMAC_MAC_MDIO_REG_ADDR_C22P_MASK GENMASK(4, 0) +#define XGMAC_MAC_MDIO_DATA_GD_MASK GENMASK(15, 0) + +/* MTL Registers */ + +#define XGMAC_MTL_REGS_BASE 0x1000 + +struct xgmac_mtl_regs { + u32 mtl_operation_mode; /* 0x1000 */ + u32 unused_1004[(0x1030 - 0x1004) / 4]; /* 0x1004 */ + u32 mtl_rxq_dma_map0; /* 0x1030 */ + u32 mtl_rxq_dma_map1; /* 0x1034 */ + u32 mtl_rxq_dma_map2; /* 0x1038 */ + u32 mtl_rxq_dma_map3; /* 0x103c */ + u32 mtl_tc_prty_map0; /* 0x1040 */ + u32 mtl_tc_prty_map1; /* 0x1044 */ + u32 unused_1048[(0x1100 - 0x1048) / 4]; /* 0x1048 */ + u32 txq0_operation_mode; /* 0x1100 */ + u32 unused_1104; /* 0x1104 */ + u32 txq0_debug; /* 0x1108 */ + u32 unused_100c[(0x1118 - 0x110c) / 4]; /* 0x110c */ + u32 txq0_quantum_weight; /* 0x1118 */ + u32 unused_111c[(0x1140 - 0x111c) / 4]; /* 0x111c */ + u32 rxq0_operation_mode; /* 0x1140 */ + u32 unused_1144; /* 0x1144 */ + u32 rxq0_debug; /* 0x1148 */ +}; + +#define XGMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16 +#define XGMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK GENMASK(8, 0) +#define XGMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2 +#define XGMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2 +#define XGMAC_MTL_TXQ0_OPERATION_MODE_TSF BIT(1) +#define XGMAC_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0) + +#define XGMAC_MTL_TXQ0_DEBUG_TXQSTS BIT(4) +#define XGMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1 +#define XGMAC_MTL_TXQ0_DEBUG_TRCSTS_MASK GENMASK(2, 0) +#define XGMAC_MTL_TXQ0_DEBUG_TRCSTS_READ_STATE 0x1 + +#define XGMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 16 +#define XGMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK GENMASK(9, 0) +#define XGMAC_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7) +#define XGMAC_MTL_RXQ0_OPERATION_MODE_RSF BIT(5) + +#define XGMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16 +#define XGMAC_MTL_RXQ0_DEBUG_PRXQ_MASK GENMASK(14, 0) +#define XGMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4 +#define XGMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK GENMASK(1, 0) + +/* DMA Registers */ + +#define XGMAC_DMA_REGS_BASE 0x3000 + +struct xgmac_dma_regs { + u32 mode; /* 0x3000 */ + u32 sysbus_mode; /* 0x3004 */ + u32 unused_3008[(0x3100 - 0x3008) / 4]; /* 0x3008 */ + u32 ch0_control; /* 0x3100 */ + u32 ch0_tx_control; /* 0x3104 */ + u32 ch0_rx_control; /* 0x3108 */ + u32 slot_func_control_status; /* 0x310c */ + u32 ch0_txdesc_list_haddress; /* 0x3110 */ + u32 ch0_txdesc_list_address; /* 0x3114 */ + u32 ch0_rxdesc_list_haddress; /* 0x3118 */ + u32 ch0_rxdesc_list_address; /* 0x311c */ + u32 unused_3120; /* 0x3120 */ + u32 ch0_txdesc_tail_pointer; /* 0x3124 */ + u32 unused_3128; /* 0x3128 */ + u32 ch0_rxdesc_tail_pointer; /* 0x312c */ + u32 ch0_txdesc_ring_length; /* 0x3130 */ + u32 ch0_rxdesc_ring_length; /* 0x3134 */ + u32 unused_3138[(0x3160 - 0x3138) / 4]; /* 0x3138 */ + u32 ch0_status; /* 0x3160 */ +}; + +#define XGMAC_DMA_MODE_SWR BIT(0) +#define XGMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT 24 +#define XGMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK GENMASK(4, 0) +#define XGMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16 +#define XGMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK GENMASK(4, 0) +#define XGMAC_DMA_SYSBUS_MODE_AAL BIT(12) +#define XGMAC_DMA_SYSBUS_MODE_EAME BIT(11) +#define XGMAC_DMA_SYSBUS_MODE_BLEN32 BIT(4) +#define XGMAC_DMA_SYSBUS_MODE_BLEN16 BIT(3) +#define XGMAC_DMA_SYSBUS_MODE_BLEN8 BIT(2) +#define XGMAC_DMA_SYSBUS_MODE_BLEN4 BIT(1) +#define XGMAC_DMA_SYSBUS_MODE_UNDEF BIT(0) + +#define XGMAC_DMA_CH0_CONTROL_DSL_SHIFT 18 +#define XGMAC_DMA_CH0_CONTROL_PBLX8 BIT(16) + +#define XGMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16 +#define XGMAC_DMA_CH0_TX_CONTROL_TXPBL_MASK GENMASK(5, 0) +#define XGMAC_DMA_CH0_TX_CONTROL_OSP BIT(4) +#define XGMAC_DMA_CH0_TX_CONTROL_ST BIT(0) + +#define XGMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16 +#define XGMAC_DMA_CH0_RX_CONTROL_RXPBL_MASK GENMASK(5, 0) +#define XGMAC_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 4 +#define XGMAC_DMA_CH0_RX_CONTROL_RBSZ_MASK GENMASK(10, 0) +#define XGMAC_DMA_CH0_RX_CONTROL_SR BIT(0) + +/* Descriptors */ +#define XGMAC_DESCRIPTORS_TX 8 +#define XGMAC_DESCRIPTORS_RX 8 +#define XGMAC_BUFFER_ALIGN ARCH_DMA_MINALIGN +#define XGMAC_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN) +#define XGMAC_RX_BUFFER_SIZE (XGMAC_DESCRIPTORS_RX * XGMAC_MAX_PACKET_SIZE) + +#define XGMAC_RDES3_PKT_LENGTH_MASK GENMASK(13, 0) + +struct xgmac_desc { + u32 des0; + u32 des1; + u32 des2; + u32 des3; +}; + +#define XGMAC_DESC3_OWN BIT(31) +#define XGMAC_DESC3_FD BIT(29) +#define XGMAC_DESC3_LD BIT(28) + +#define XGMAC_AXI_WIDTH_32 4 +#define XGMAC_AXI_WIDTH_64 8 +#define XGMAC_AXI_WIDTH_128 16 + +struct xgmac_config { + bool reg_access_always_ok; + int swr_wait; + int config_mac; + int config_mac_mdio; + unsigned int axi_bus_width; + phy_interface_t (*interface)(const struct udevice *dev); + struct xgmac_ops *ops; +}; + +struct xgmac_ops { + void (*xgmac_inval_desc)(void *desc); + void (*xgmac_flush_desc)(void *desc); + void (*xgmac_inval_buffer)(void *buf, size_t size); + void (*xgmac_flush_buffer)(void *buf, size_t size); + int (*xgmac_probe_resources)(struct udevice *dev); + int (*xgmac_remove_resources)(struct udevice *dev); + int (*xgmac_stop_resets)(struct udevice *dev); + int (*xgmac_start_resets)(struct udevice *dev); + int (*xgmac_stop_clks)(struct udevice *dev); + int (*xgmac_start_clks)(struct udevice *dev); + int (*xgmac_calibrate_pads)(struct udevice *dev); + int (*xgmac_disable_calibration)(struct udevice *dev); + int (*xgmac_get_enetaddr)(struct udevice *dev); +}; + +struct xgmac_priv { + struct udevice *dev; + const struct xgmac_config *config; + fdt_addr_t regs; + struct xgmac_mac_regs *mac_regs; + struct xgmac_mtl_regs *mtl_regs; + struct xgmac_dma_regs *dma_regs; + struct reset_ctl reset_ctl; + struct reset_ctl_bulk reset_bulk; + struct clk clk_common; + struct mii_dev *mii; + struct phy_device *phy; + ofnode phy_of_node; + void *syscon_phy; + u32 syscon_phy_regshift; + u32 max_speed; + void *tx_descs; + void *rx_descs; + int tx_desc_idx, rx_desc_idx; + unsigned int desc_size; + unsigned int desc_per_cacheline; + void *tx_dma_buf; + void *rx_dma_buf; + void *rx_pkt; + bool started; + bool reg_access_ok; + bool clk_ck_enabled; +}; + +void xgmac_inval_desc_generic(void *desc); +void xgmac_flush_desc_generic(void *desc); +void xgmac_inval_buffer_generic(void *buf, size_t size); +void xgmac_flush_buffer_generic(void *buf, size_t size); +int xgmac_null_ops(struct udevice *dev); + +extern struct xgmac_config xgmac_socfpga_config; diff --git a/drivers/net/dwc_eth_xgmac_socfpga.c b/drivers/net/dwc_eth_xgmac_socfpga.c new file mode 100644 index 00000000000..270c1b0ca6c --- /dev/null +++ b/drivers/net/dwc_eth_xgmac_socfpga.c @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023, Intel Corporation + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dwc_eth_xgmac.h" + +#define SOCFPGA_XGMAC_SYSCON_ARG_COUNT 2 + +static int dwxgmac_socfpga_do_setphy(struct udevice *dev, u32 modereg) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + int ret; + + u32 modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << + xgmac->syscon_phy_regshift; + + if (!(IS_ENABLED(CONFIG_SPL_BUILD)) && IS_ENABLED(CONFIG_SPL_ATF)) { + u32 index = ((u64)xgmac->syscon_phy - socfpga_get_sysmgr_addr() - + SYSMGR_SOC64_EMAC0) >> 2; + + u32 id = SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 + index; + + ret = socfpga_secure_reg_update32(id, + modemask, + modereg << + xgmac->syscon_phy_regshift); + if (ret) { + dev_err(dev, "Failed to set PHY register via SMC call\n"); + return ret; + } + + } else { + clrsetbits_le32(xgmac->phy, modemask, modereg); + } + + return 0; +} + +static int xgmac_probe_resources_socfpga(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + struct regmap *reg_map; + struct ofnode_phandle_args args; + void *range; + phy_interface_t interface; + int ret; + u32 modereg; + + interface = xgmac->config->interface(dev); + + switch (interface) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: + modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; + break; + case PHY_INTERFACE_MODE_RMII: + modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; + break; + case PHY_INTERFACE_MODE_RGMII: + modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; + break; + default: + dev_err(dev, "Unsupported PHY mode\n"); + return -EINVAL; + } + + /* Get PHY syscon */ + ret = dev_read_phandle_with_args(dev, "altr,sysmgr-syscon", NULL, + SOCFPGA_XGMAC_SYSCON_ARG_COUNT, + 0, &args); + + if (ret) { + dev_err(dev, "Failed to get syscon: %d\n", ret); + return ret; + } + + if (args.args_count != SOCFPGA_XGMAC_SYSCON_ARG_COUNT) { + dev_err(dev, "Invalid number of syscon args\n"); + return -EINVAL; + } + + reg_map = syscon_node_to_regmap(args.node); + if (IS_ERR(reg_map)) { + ret = PTR_ERR(reg_map); + dev_err(dev, "Failed to get reg_map: %d\n", ret); + return ret; + } + + range = regmap_get_range(reg_map, 0); + if (!range) { + dev_err(dev, "Failed to get reg_map: %d\n", ret); + return -ENOMEM; + } + + xgmac->syscon_phy = range + args.args[0]; + xgmac->syscon_phy_regshift = args.args[1]; + + /* Get Reset Bulk */ + ret = reset_get_bulk(dev, &xgmac->reset_bulk); + if (ret) { + dev_err(dev, "Failed to get reset: %d\n", ret); + return ret; + } + + ret = reset_assert_bulk(&xgmac->reset_bulk); + if (ret) { + dev_err(dev, "XGMAC failed to assert reset: %d\n", ret); + return ret; + } + + ret = dwxgmac_socfpga_do_setphy(dev, modereg); + if (ret) + return ret; + + ret = reset_deassert_bulk(&xgmac->reset_bulk); + if (ret) { + dev_err(dev, "XGMAC failed to de-assert reset: %d\n", ret); + return ret; + } + + ret = clk_get_by_name(dev, "stmmaceth", &xgmac->clk_common); + if (ret) { + pr_err("clk_get_by_name(stmmaceth) failed: %d", ret); + goto err_probe; + } + return 0; + +err_probe: + debug("%s: returns %d\n", __func__, ret); + return ret; +} + +static int xgmac_get_enetaddr_socfpga(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct xgmac_priv *xgmac = dev_get_priv(dev); + u32 hi_addr, lo_addr; + + debug("%s(dev=%p):\n", __func__, dev); + + /* Read the MAC Address from the hardawre */ + hi_addr = readl(&xgmac->mac_regs->address0_high); + lo_addr = readl(&xgmac->mac_regs->address0_low); + + pdata->enetaddr[0] = lo_addr & 0xff; + pdata->enetaddr[1] = (lo_addr >> 8) & 0xff; + pdata->enetaddr[2] = (lo_addr >> 16) & 0xff; + pdata->enetaddr[3] = (lo_addr >> 24) & 0xff; + pdata->enetaddr[4] = hi_addr & 0xff; + pdata->enetaddr[5] = (hi_addr >> 8) & 0xff; + + return !is_valid_ethaddr(pdata->enetaddr); +} + +static int xgmac_start_resets_socfpga(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + int ret; + + debug("%s(dev=%p):\n", __func__, dev); + + ret = reset_assert_bulk(&xgmac->reset_bulk); + if (ret < 0) { + pr_err("xgmac reset assert failed: %d", ret); + return ret; + } + + udelay(2); + + ret = reset_deassert_bulk(&xgmac->reset_bulk); + if (ret < 0) { + pr_err("xgmac reset de-assert failed: %d", ret); + return ret; + } + + return 0; +} + +static struct xgmac_ops xgmac_socfpga_ops = { + .xgmac_inval_desc = xgmac_inval_desc_generic, + .xgmac_flush_desc = xgmac_flush_desc_generic, + .xgmac_inval_buffer = xgmac_inval_buffer_generic, + .xgmac_flush_buffer = xgmac_flush_buffer_generic, + .xgmac_probe_resources = xgmac_probe_resources_socfpga, + .xgmac_remove_resources = xgmac_null_ops, + .xgmac_stop_resets = xgmac_null_ops, + .xgmac_start_resets = xgmac_start_resets_socfpga, + .xgmac_stop_clks = xgmac_null_ops, + .xgmac_start_clks = xgmac_null_ops, + .xgmac_calibrate_pads = xgmac_null_ops, + .xgmac_disable_calibration = xgmac_null_ops, + .xgmac_get_enetaddr = xgmac_get_enetaddr_socfpga, +}; + +struct xgmac_config __maybe_unused xgmac_socfpga_config = { + .reg_access_always_ok = false, + .swr_wait = 50, + .config_mac = XGMAC_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB, + .config_mac_mdio = XGMAC_MAC_MDIO_ADDRESS_CR_350_400, + .axi_bus_width = XGMAC_AXI_WIDTH_64, + .interface = dev_read_phy_mode, + .ops = &xgmac_socfpga_ops +}; diff --git a/drivers/net/dwmac_meson8b.c b/drivers/net/dwmac_meson8b.c index 871171e1be5..fde4aabbace 100644 --- a/drivers/net/dwmac_meson8b.c +++ b/drivers/net/dwmac_meson8b.c @@ -3,7 +3,6 @@ * Copyright (C) 2021 BayLibre, SAS */ -#include #include #include #include diff --git a/drivers/net/dwmac_s700.c b/drivers/net/dwmac_s700.c index 744b58bdd1a..969d247b4f3 100644 --- a/drivers/net/dwmac_s700.c +++ b/drivers/net/dwmac_s700.c @@ -5,7 +5,6 @@ * Actions DWMAC specific glue layer */ -#include #include #include #include diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c index 82fdff51dac..bba3fc4d34b 100644 --- a/drivers/net/dwmac_socfpga.c +++ b/drivers/net/dwmac_socfpga.c @@ -5,7 +5,6 @@ * Altera SoCFPGA EMAC extras */ -#include #include #include #include diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 4e7ba666770..663d900eb09 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -29,7 +29,6 @@ tested on both gig copper and gig fiber boards * Copyright 2011 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/drivers/net/e1000_spi.c b/drivers/net/e1000_spi.c index 69adf282c73..1e830b99f1d 100644 --- a/drivers/net/e1000_spi.c +++ b/drivers/net/e1000_spi.c @@ -1,9 +1,9 @@ -#include #include #include #include #include "e1000.h" #include +#include #include /*----------------------------------------------------------------------- diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c index 38d96ab72b6..d18a8d577ca 100644 --- a/drivers/net/eepro100.c +++ b/drivers/net/eepro100.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include diff --git a/drivers/net/eth-phy-uclass.c b/drivers/net/eth-phy-uclass.c index 9d1e8d38ffa..1dae26878e6 100644 --- a/drivers/net/eth-phy-uclass.c +++ b/drivers/net/eth-phy-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_ETH_PHY -#include #include #include #include diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c index 13fad8119bb..dc7e6f1929f 100644 --- a/drivers/net/ethoc.c +++ b/drivers/net/ethoc.c @@ -9,7 +9,6 @@ * Copyright (C) 2016 Cadence Design Systems Inc. */ -#include #include #include #include diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 90af18f80a8..0a0d92bc2cd 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -7,7 +7,6 @@ * (C) Copyright 2007 Pengutronix, Juergen Beisert */ -#include #include #include #include diff --git a/drivers/net/fm/b4860.c b/drivers/net/fm/b4860.c index 1c5543e3c87..46a0d38b101 100644 --- a/drivers/net/fm/b4860.c +++ b/drivers/net/fm/b4860.c @@ -3,7 +3,7 @@ * Copyright 2012 Freescale Semiconductor, Inc. * Roy Zang */ -#include +#include #include #include #include diff --git a/drivers/net/fm/dtsec.c b/drivers/net/fm/dtsec.c index c51a65cb94f..371d9f07a46 100644 --- a/drivers/net/fm/dtsec.c +++ b/drivers/net/fm/dtsec.c @@ -3,7 +3,6 @@ * Copyright 2009-2011 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index 9fd26de0d72..19f3f0fef07 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -4,7 +4,7 @@ * Copyright 2020 NXP * Dave Liu */ -#include +#include #include #include #include diff --git a/drivers/net/fm/ls1043.c b/drivers/net/fm/ls1043.c index 3db5c907a2a..41b75761fdd 100644 --- a/drivers/net/fm/ls1043.c +++ b/drivers/net/fm/ls1043.c @@ -2,7 +2,7 @@ /* * Copyright 2015 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/drivers/net/fm/ls1046.c b/drivers/net/fm/ls1046.c index 3b0ee98ddd3..56c5c6846a4 100644 --- a/drivers/net/fm/ls1046.c +++ b/drivers/net/fm/ls1046.c @@ -2,7 +2,7 @@ /* * Copyright 2016 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c index eeb67a39a77..37b54626af0 100644 --- a/drivers/net/fm/memac.c +++ b/drivers/net/fm/memac.c @@ -7,7 +7,6 @@ /* MAXFRM - maximum frame length */ #define MAXFRM_MASK 0x0000ffff -#include #include #include #include diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c index e0b62b94490..26425d94ae5 100644 --- a/drivers/net/fm/memac_phy.c +++ b/drivers/net/fm/memac_phy.c @@ -5,7 +5,6 @@ * Roy Zang * Some part is taken from tsec.c */ -#include #include #include #include diff --git a/drivers/net/fm/p1023.c b/drivers/net/fm/p1023.c index 9013b276bc9..362bc9f30a1 100644 --- a/drivers/net/fm/p1023.c +++ b/drivers/net/fm/p1023.c @@ -2,7 +2,7 @@ /* * Copyright 2011 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/drivers/net/fm/p4080.c b/drivers/net/fm/p4080.c index 7ad993221f7..6e63e338e5d 100644 --- a/drivers/net/fm/p4080.c +++ b/drivers/net/fm/p4080.c @@ -2,7 +2,7 @@ /* * Copyright 2011 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/drivers/net/fm/p5020.c b/drivers/net/fm/p5020.c index f931491b112..4fc1f723a3d 100644 --- a/drivers/net/fm/p5020.c +++ b/drivers/net/fm/p5020.c @@ -2,7 +2,7 @@ /* * Copyright 2011 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/drivers/net/fm/p5040.c b/drivers/net/fm/p5040.c index ef9f4bcce4d..f6ae947ef99 100644 --- a/drivers/net/fm/p5040.c +++ b/drivers/net/fm/p5040.c @@ -2,7 +2,7 @@ /* * Copyright 2011 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/drivers/net/fm/t1024.c b/drivers/net/fm/t1024.c index 70ab4610cdf..18d71e7b60e 100644 --- a/drivers/net/fm/t1024.c +++ b/drivers/net/fm/t1024.c @@ -4,7 +4,7 @@ * Shengzhou Liu */ -#include +#include #include #include #include diff --git a/drivers/net/fm/t1040.c b/drivers/net/fm/t1040.c index 5c260bed7fd..dafa6d638e3 100644 --- a/drivers/net/fm/t1040.c +++ b/drivers/net/fm/t1040.c @@ -2,7 +2,7 @@ /* * Copyright 2013 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/drivers/net/fm/t2080.c b/drivers/net/fm/t2080.c index 6174934d2b8..390ca0aee70 100644 --- a/drivers/net/fm/t2080.c +++ b/drivers/net/fm/t2080.c @@ -5,7 +5,7 @@ * Shengzhou Liu */ -#include +#include #include #include #include diff --git a/drivers/net/fm/t4240.c b/drivers/net/fm/t4240.c index f0a02bfe457..df76073eecd 100644 --- a/drivers/net/fm/t4240.c +++ b/drivers/net/fm/t4240.c @@ -3,7 +3,7 @@ * Copyright 2012 Freescale Semiconductor, Inc. * Roy Zang */ -#include +#include #include #include #include diff --git a/drivers/net/fm/tgec.c b/drivers/net/fm/tgec.c index 9cc9f3fde3a..f7b51ce0bba 100644 --- a/drivers/net/fm/tgec.c +++ b/drivers/net/fm/tgec.c @@ -7,7 +7,6 @@ /* MAXFRM - maximum frame length */ #define MAXFRM_MASK 0x0000ffff -#include #include #include #include diff --git a/drivers/net/fm/tgec_phy.c b/drivers/net/fm/tgec_phy.c index 22225c2f82f..f6c8f80c835 100644 --- a/drivers/net/fm/tgec_phy.c +++ b/drivers/net/fm/tgec_phy.c @@ -4,7 +4,6 @@ * Andy Fleming * Some part is taken from tsec.c */ -#include #include #include #include diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index f5c5057bec1..c2869ce4010 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. * Copyright 2017-2018, 2020-2021 NXP */ -#include +#include #include #include #include diff --git a/drivers/net/fsl-mc/mc_sys.c b/drivers/net/fsl-mc/mc_sys.c index 4d32516b005..482fb0463d5 100644 --- a/drivers/net/fsl-mc/mc_sys.c +++ b/drivers/net/fsl-mc/mc_sys.c @@ -8,7 +8,6 @@ #include #include -#include #include #include #include diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index 1fd5089cc4b..a6b0bafc8c6 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -4,7 +4,6 @@ * Copyright 2017-2021 NXP */ -#include #include #include #include diff --git a/drivers/net/fsl_enetc_mdio.c b/drivers/net/fsl_enetc_mdio.c index 50ad76dfeb5..2d5fcbb6dbd 100644 --- a/drivers/net/fsl_enetc_mdio.c +++ b/drivers/net/fsl_enetc_mdio.c @@ -4,7 +4,6 @@ * Copyright 2019 NXP */ -#include #include #include #include diff --git a/drivers/net/fsl_ls_mdio.c b/drivers/net/fsl_ls_mdio.c index fce73937502..e3c37d9045f 100644 --- a/drivers/net/fsl_ls_mdio.c +++ b/drivers/net/fsl_ls_mdio.c @@ -3,7 +3,6 @@ * Copyright 2020 NXP */ -#include #include #include #include diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c index 5fd11db05f5..a0f1c59e058 100644 --- a/drivers/net/fsl_mdio.c +++ b/drivers/net/fsl_mdio.c @@ -5,7 +5,6 @@ * Mingkai Hu */ -#include #include #include #include diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index 9b536fd5ab8..8781e50a48d 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -11,7 +11,6 @@ * Copyright (C) 2018, IBM Corporation. */ -#include #include #include #include diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c index fae3adc3de3..199a0723b84 100644 --- a/drivers/net/ftmac100.c +++ b/drivers/net/ftmac100.c @@ -7,7 +7,6 @@ */ #include -#include #include #include #include diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index 51f835adabc..d63e2dbfaeb 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -5,7 +5,6 @@ * Rockchip GMAC ethernet IP driver for U-Boot */ -#include #include #include #include diff --git a/drivers/net/higmacv300.c b/drivers/net/higmacv300.c index 1862235d0cd..6b88f6fbf59 100644 --- a/drivers/net/higmacv300.c +++ b/drivers/net/higmacv300.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/net/ks8851_mll.c b/drivers/net/ks8851_mll.c index 518548e3bbc..cc2e826257a 100644 --- a/drivers/net/ks8851_mll.c +++ b/drivers/net/ks8851_mll.c @@ -6,7 +6,6 @@ #include #include -#include #include #include #include diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index 87fbada06ba..b72198ca530 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -4,7 +4,6 @@ * Copyright 2017, 2023 NXP */ -#include #include #include #include diff --git a/drivers/net/ldpaa_eth/ldpaa_wriop.c b/drivers/net/ldpaa_eth/ldpaa_wriop.c index adecb813576..a803b8fa797 100644 --- a/drivers/net/ldpaa_eth/ldpaa_wriop.c +++ b/drivers/net/ldpaa_eth/ldpaa_wriop.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Freescale Semiconductor */ -#include #include #include #include diff --git a/drivers/net/ldpaa_eth/ls1088a.c b/drivers/net/ldpaa_eth/ls1088a.c index 32bcb51725a..2727fb01179 100644 --- a/drivers/net/ldpaa_eth/ls1088a.c +++ b/drivers/net/ldpaa_eth/ls1088a.c @@ -2,7 +2,7 @@ /* * Copyright 2017 NXP */ -#include +#include #include #include #include diff --git a/drivers/net/ldpaa_eth/ls2080a.c b/drivers/net/ldpaa_eth/ls2080a.c index 845a36bce87..05017552b3f 100644 --- a/drivers/net/ldpaa_eth/ls2080a.c +++ b/drivers/net/ldpaa_eth/ls2080a.c @@ -2,7 +2,7 @@ /* * Copyright 2015 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/drivers/net/ldpaa_eth/lx2160a.c b/drivers/net/ldpaa_eth/lx2160a.c index c2641a92d7e..25ae684063b 100644 --- a/drivers/net/ldpaa_eth/lx2160a.c +++ b/drivers/net/ldpaa_eth/lx2160a.c @@ -2,7 +2,7 @@ /* * Copyright 2018, 2020 NXP */ -#include +#include #include #include #include diff --git a/drivers/net/macb.c b/drivers/net/macb.c index bca014c3cbb..cbf5f605518 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2005-2006 Atmel Corporation */ -#include #include #include #include diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index ec1fae9688b..04b711e4f65 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -10,7 +10,7 @@ * (C) 2019 Angelo Dureghello */ -#include +#include #include #include #include diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c index eae20654513..9bf887035d7 100644 --- a/drivers/net/mcfmii.c +++ b/drivers/net/mcfmii.c @@ -4,7 +4,6 @@ * TsiChung Liew (Tsi-Chung.Liew@freescale.com) */ -#include #include #include #include diff --git a/drivers/net/mdio-ipq4019.c b/drivers/net/mdio-ipq4019.c index 50134b4d9b6..c824c3da3dd 100644 --- a/drivers/net/mdio-ipq4019.c +++ b/drivers/net/mdio-ipq4019.c @@ -11,7 +11,6 @@ */ #include -#include #include #include #include diff --git a/drivers/net/mpc8xx_fec.c b/drivers/net/mpc8xx_fec.c index 78337731e1f..c44fa6acdd7 100644 --- a/drivers/net/mpc8xx_fec.c +++ b/drivers/net/mpc8xx_fec.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include diff --git a/drivers/net/mscc_eswitch/jr2_switch.c b/drivers/net/mscc_eswitch/jr2_switch.c index 7157428a685..925888e0765 100644 --- a/drivers/net/mscc_eswitch/jr2_switch.c +++ b/drivers/net/mscc_eswitch/jr2_switch.c @@ -3,7 +3,6 @@ * Copyright (c) 2018 Microsemi Corporation */ -#include #include #include #include diff --git a/drivers/net/mscc_eswitch/luton_switch.c b/drivers/net/mscc_eswitch/luton_switch.c index 5e4f00c4f4d..2f3d0911fdf 100644 --- a/drivers/net/mscc_eswitch/luton_switch.c +++ b/drivers/net/mscc_eswitch/luton_switch.c @@ -3,7 +3,6 @@ * Copyright (c) 2019 Microsemi Corporation */ -#include #include #include #include diff --git a/drivers/net/mscc_eswitch/ocelot_switch.c b/drivers/net/mscc_eswitch/ocelot_switch.c index 7ea1f551a11..30bb4b5bad8 100644 --- a/drivers/net/mscc_eswitch/ocelot_switch.c +++ b/drivers/net/mscc_eswitch/ocelot_switch.c @@ -3,7 +3,6 @@ * Copyright (c) 2018 Microsemi Corporation */ -#include #include #include #include diff --git a/drivers/net/mscc_eswitch/serval_switch.c b/drivers/net/mscc_eswitch/serval_switch.c index be06e483373..8eab41df99a 100644 --- a/drivers/net/mscc_eswitch/serval_switch.c +++ b/drivers/net/mscc_eswitch/serval_switch.c @@ -3,7 +3,6 @@ * Copyright (c) 2019 Microsemi Corporation */ -#include #include #include #include diff --git a/drivers/net/mscc_eswitch/servalt_switch.c b/drivers/net/mscc_eswitch/servalt_switch.c index 2d2329c204a..61547d7933e 100644 --- a/drivers/net/mscc_eswitch/servalt_switch.c +++ b/drivers/net/mscc_eswitch/servalt_switch.c @@ -3,7 +3,6 @@ * Copyright (c) 2019 Microsemi Corporation */ -#include #include #include #include diff --git a/drivers/net/mt7628-eth.c b/drivers/net/mt7628-eth.c index b95de474fb0..fc8a6bb331b 100644 --- a/drivers/net/mt7628-eth.c +++ b/drivers/net/mt7628-eth.c @@ -13,7 +13,6 @@ * copyrights here, so I can't add them here. */ -#include #include #include #include diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c index 75e7bcf83b7..94f17a97fe0 100644 --- a/drivers/net/mtk_eth.c +++ b/drivers/net/mtk_eth.c @@ -6,7 +6,6 @@ * Author: Mark Lee */ -#include #include #include #include diff --git a/drivers/net/mv88e6xxx.c b/drivers/net/mv88e6xxx.c index 8fbbc1cacca..557b6b2c8f6 100644 --- a/drivers/net/mv88e6xxx.c +++ b/drivers/net/mv88e6xxx.c @@ -23,7 +23,6 @@ * on the mv88e6176 via an SGMII interface. */ -#include #include #include #include diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index 3587ca2124e..17b62bbc205 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -11,7 +11,6 @@ * Copyright (C) 2002 rabeeh@galileo.co.il */ -#include #include #include #include diff --git a/drivers/net/mvmdio.c b/drivers/net/mvmdio.c index 5ebcfe14b7f..3315e06f591 100644 --- a/drivers/net/mvmdio.c +++ b/drivers/net/mvmdio.c @@ -4,7 +4,6 @@ * Author: Ken Ma */ -#include #include #include #include diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c index 24933473fa0..f014d39b175 100644 --- a/drivers/net/mvneta.c +++ b/drivers/net/mvneta.c @@ -12,7 +12,6 @@ * Thomas Petazzoni */ -#include #include #include #include diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 1cd54307650..d19a79d1600 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -13,7 +13,6 @@ * warranty of any kind, whether express or implied. */ -#include #include #include #include diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c index 151bc55e076..1943de8ba73 100644 --- a/drivers/net/netconsole.c +++ b/drivers/net/netconsole.c @@ -4,12 +4,12 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include #include #include +#include #ifndef CFG_NETCONSOLE_BUFFER_SIZE #define CFG_NETCONSOLE_BUFFER_SIZE 512 diff --git a/drivers/net/npcm750_eth.c b/drivers/net/npcm750_eth.c index 2028f4ae286..f0ec6c556cc 100644 --- a/drivers/net/npcm750_eth.c +++ b/drivers/net/npcm750_eth.c @@ -3,7 +3,6 @@ * Copyright (c) 2021 Nuvoton Technology Corp. */ -#include #include #include #include diff --git a/drivers/net/pch_gbe.c b/drivers/net/pch_gbe.c index ecf8c28fe41..adeca3d040d 100644 --- a/drivers/net/pch_gbe.c +++ b/drivers/net/pch_gbe.c @@ -5,7 +5,6 @@ * Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver */ -#include #include #include #include diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index a1f3c2bd290..180a96af16b 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -6,7 +6,6 @@ * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer. */ -#include #include #include #include diff --git a/drivers/net/pfe_eth/pfe_cmd.c b/drivers/net/pfe_eth/pfe_cmd.c index 2fe0db0fe71..99c2a8d4e92 100644 --- a/drivers/net/pfe_eth/pfe_cmd.c +++ b/drivers/net/pfe_eth/pfe_cmd.c @@ -9,7 +9,6 @@ * @brief PFE utility commands */ -#include #include #include #include diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c index ab532c5a420..e24a6f93d91 100644 --- a/drivers/net/pfe_eth/pfe_eth.c +++ b/drivers/net/pfe_eth/pfe_eth.c @@ -4,7 +4,7 @@ * Copyright 2017 NXP */ -#include +#include #include #include #include diff --git a/drivers/net/pfe_eth/pfe_mdio.c b/drivers/net/pfe_eth/pfe_mdio.c index ff48726dbf5..ce2f76eabc8 100644 --- a/drivers/net/pfe_eth/pfe_mdio.c +++ b/drivers/net/pfe_eth/pfe_mdio.c @@ -3,7 +3,7 @@ * Copyright 2015-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP */ -#include +#include #include #include #include diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c index 0970449d0f9..ce448810ff6 100644 --- a/drivers/net/phy/adin.c +++ b/drivers/net/phy/adin.c @@ -6,7 +6,6 @@ * Copyright 2022 Variscite Ltd. * Copyright 2022 Josua Mayer */ -#include #include #include #include diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index a958e88d44f..4517a6b13ba 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -6,7 +6,6 @@ * Copyright 2018, 2021 NXP */ #include -#include #include #include #include diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index abb7bdf537c..61525f68c35 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -6,7 +6,6 @@ * author Andy Fleming * Copyright (c) 2019 Michael Walle */ -#include #include #include #include diff --git a/drivers/net/phy/b53.c b/drivers/net/phy/b53.c index 26e8e2fe64f..e95363067fe 100644 --- a/drivers/net/phy/b53.c +++ b/drivers/net/phy/b53.c @@ -22,7 +22,6 @@ * cover other switches would be trivial. */ -#include #include #include #include diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c index ecccb7c3b54..0a49015eb89 100644 --- a/drivers/net/phy/broadcom.c +++ b/drivers/net/phy/broadcom.c @@ -5,7 +5,6 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. * author Andy Fleming */ -#include #include #include diff --git a/drivers/net/phy/ca_phy.c b/drivers/net/phy/ca_phy.c index edef21867b0..5b2c67d2fda 100644 --- a/drivers/net/phy/ca_phy.c +++ b/drivers/net/phy/ca_phy.c @@ -8,7 +8,6 @@ */ #include -#include #include #include #include diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c index 1cf8b28f582..d043e859bad 100644 --- a/drivers/net/phy/cortina.c +++ b/drivers/net/phy/cortina.c @@ -8,7 +8,6 @@ */ #include -#include #include #include #include diff --git a/drivers/net/phy/davicom.c b/drivers/net/phy/davicom.c index 31ffa1ac7a9..72d66812985 100644 --- a/drivers/net/phy/davicom.c +++ b/drivers/net/phy/davicom.c @@ -5,7 +5,6 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. * author Andy Fleming */ -#include #include #define MIIM_DM9161_SCR 0x10 diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index b6726031ebb..772cde1c520 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -3,7 +3,6 @@ * TI PHY drivers * */ -#include #include #include #include diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c index f9d4782580e..b6fb5adae1f 100644 --- a/drivers/net/phy/dp83869.c +++ b/drivers/net/phy/dp83869.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/drivers/net/phy/ethernet_id.c b/drivers/net/phy/ethernet_id.c index 4dfdee60dcc..2f8454ca27d 100644 --- a/drivers/net/phy/ethernet_id.c +++ b/drivers/net/phy/ethernet_id.c @@ -5,7 +5,6 @@ * Copyright (C) 2022 Xilinx, Inc. */ -#include #include #include #include diff --git a/drivers/net/phy/fixed.c b/drivers/net/phy/fixed.c index 2f0823b8365..11d36164976 100644 --- a/drivers/net/phy/fixed.c +++ b/drivers/net/phy/fixed.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/drivers/net/phy/generic_10g.c b/drivers/net/phy/generic_10g.c index 34ac51ea070..38dc9a88563 100644 --- a/drivers/net/phy/generic_10g.c +++ b/drivers/net/phy/generic_10g.c @@ -7,7 +7,6 @@ * * Based loosely off of Linux's PHY Lib */ -#include #include #include diff --git a/drivers/net/phy/intel_xway.c b/drivers/net/phy/intel_xway.c index 9d1b97d349f..fe50eec011a 100644 --- a/drivers/net/phy/intel_xway.c +++ b/drivers/net/phy/intel_xway.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include diff --git a/drivers/net/phy/lxt.c b/drivers/net/phy/lxt.c index 20940033a38..a817c58b128 100644 --- a/drivers/net/phy/lxt.c +++ b/drivers/net/phy/lxt.c @@ -5,7 +5,6 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. * author Andy Fleming */ -#include #include /* LXT971 Status 2 registers */ diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index 0a90f710dfe..b0a0b7fcb38 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -5,7 +5,6 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. * author Andy Fleming */ -#include #include #include #include diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c index 9e64672f5ca..8c95bcbb9ad 100644 --- a/drivers/net/phy/marvell10g.c +++ b/drivers/net/phy/marvell10g.c @@ -22,7 +22,6 @@ * If both the fiber and copper ports are connected, the first to gain * link takes priority and the other port is completely locked out. */ -#include #include #include #include diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c index b49c9b5f495..d43b476b3c8 100644 --- a/drivers/net/phy/meson-gxl.c +++ b/drivers/net/phy/meson-gxl.c @@ -7,7 +7,6 @@ * Author: Neil Armstrong */ #include -#include #include #include #include diff --git a/drivers/net/phy/micrel_ksz8xxx.c b/drivers/net/phy/micrel_ksz8xxx.c index b0f3abcb037..a9a64466ac2 100644 --- a/drivers/net/phy/micrel_ksz8xxx.c +++ b/drivers/net/phy/micrel_ksz8xxx.c @@ -6,7 +6,6 @@ * author Andy Fleming * (C) 2012 NetModule AG, David Andrey, added KSZ9031 */ -#include #include #include #include diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c index ffc3c987eaa..556d75e31ed 100644 --- a/drivers/net/phy/micrel_ksz90x1.c +++ b/drivers/net/phy/micrel_ksz90x1.c @@ -8,7 +8,6 @@ * (C) Copyright 2017 Adaptrum, Inc. * Written by Alexandru Gagniuc for Adaptrum, Inc. */ -#include #include #include #include diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c index cf71f7d4e7e..083d9d3996d 100644 --- a/drivers/net/phy/miiphybb.c +++ b/drivers/net/phy/miiphybb.c @@ -12,7 +12,6 @@ * channel. */ -#include #include #include #include diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c index a2c763c8791..a96430cec43 100644 --- a/drivers/net/phy/motorcomm.c +++ b/drivers/net/phy/motorcomm.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 85778106edd..ecc10f788af 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -29,7 +29,6 @@ * changes may be required. */ -#include #include #include #include diff --git a/drivers/net/phy/mv88e6352.c b/drivers/net/phy/mv88e6352.c index 56060762d85..6284298ebc1 100644 --- a/drivers/net/phy/mv88e6352.c +++ b/drivers/net/phy/mv88e6352.c @@ -4,7 +4,6 @@ * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com */ -#include #include #include #include diff --git a/drivers/net/phy/natsemi.c b/drivers/net/phy/natsemi.c index 6b9e99ea115..f7e514ef203 100644 --- a/drivers/net/phy/natsemi.c +++ b/drivers/net/phy/natsemi.c @@ -5,7 +5,6 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. * author Andy Fleming */ -#include #include /* NatSemi DP83630 */ diff --git a/drivers/net/phy/ncsi.c b/drivers/net/phy/ncsi.c index 2bca116a9d8..a1de438ffff 100644 --- a/drivers/net/phy/ncsi.c +++ b/drivers/net/phy/ncsi.c @@ -5,7 +5,6 @@ * Copyright (C) 2019, IBM Corporation. */ -#include #include #include #include diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c index f24fc5b2de6..a1e4c3d053b 100644 --- a/drivers/net/phy/nxp-c45-tja11xx.c +++ b/drivers/net/phy/nxp-c45-tja11xx.c @@ -5,7 +5,6 @@ * Copyright 2021 NXP * Author: Radu Pirea */ -#include #include #include #include diff --git a/drivers/net/phy/nxp-tja11xx.c b/drivers/net/phy/nxp-tja11xx.c index 471b0e322b5..a61471f4277 100644 --- a/drivers/net/phy/nxp-tja11xx.c +++ b/drivers/net/phy/nxp-tja11xx.c @@ -6,7 +6,6 @@ * Copyright (C) 2018 Marek Vasut */ -#include #include #include #include diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 270176cfe62..fbf85d90f54 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -7,7 +7,6 @@ * * Based loosely off of Linux's PHY Lib */ -#include #include #include #include diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index 7e1036b2271..30f35cced9d 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -6,7 +6,6 @@ * author Andy Fleming * Copyright 2016 Karsten Merker */ -#include #include #include #include diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c index 056b607e0b8..0d823f5f2b1 100644 --- a/drivers/net/phy/smsc.c +++ b/drivers/net/phy/smsc.c @@ -9,7 +9,6 @@ * Some code copied from linux kernel * Copyright (c) 2006 Herbert Valerio Riedel */ -#include #include /* This code does not check the partner abilities. */ diff --git a/drivers/net/phy/teranetics.c b/drivers/net/phy/teranetics.c index 15f2c12ed83..b39311976d6 100644 --- a/drivers/net/phy/teranetics.c +++ b/drivers/net/phy/teranetics.c @@ -5,7 +5,6 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. * author Andy Fleming */ -#include #include #include diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c index c5cf0d7dfbd..4867d1931b4 100644 --- a/drivers/net/phy/vitesse.c +++ b/drivers/net/phy/vitesse.c @@ -6,7 +6,6 @@ * Original Author: Andy Fleming * Add vsc8662 phy support - Priyanka Jain */ -#include #include /* Cicada Auxiliary Control/Status Register */ diff --git a/drivers/net/phy/xilinx_gmii2rgmii.c b/drivers/net/phy/xilinx_gmii2rgmii.c index e2969bc4842..e44b7b75bd5 100644 --- a/drivers/net/phy/xilinx_gmii2rgmii.c +++ b/drivers/net/phy/xilinx_gmii2rgmii.c @@ -5,7 +5,6 @@ * Copyright (C) 2018 Xilinx, Inc. */ -#include #include #include #include diff --git a/drivers/net/phy/xilinx_phy.c b/drivers/net/phy/xilinx_phy.c index c07c780193f..a59e17d11e5 100644 --- a/drivers/net/phy/xilinx_phy.c +++ b/drivers/net/phy/xilinx_phy.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/drivers/net/pic32_eth.c b/drivers/net/pic32_eth.c index 1333a3aa7e4..eea3c48aeff 100644 --- a/drivers/net/pic32_eth.c +++ b/drivers/net/pic32_eth.c @@ -3,7 +3,6 @@ * (c) 2015 Purna Chandra Mandal * */ -#include #include #include #include diff --git a/drivers/net/pic32_mdio.c b/drivers/net/pic32_mdio.c index d4049cfea52..8610f9a1aa5 100644 --- a/drivers/net/pic32_mdio.c +++ b/drivers/net/pic32_mdio.c @@ -5,7 +5,6 @@ * Copyright 2015 Microchip Inc. * Purna Chandra Mandal */ -#include #include #include #include diff --git a/drivers/net/qe/dm_qe_uec.c b/drivers/net/qe/dm_qe_uec.c index 6d1509d90cf..ac3aedd8b49 100644 --- a/drivers/net/qe/dm_qe_uec.c +++ b/drivers/net/qe/dm_qe_uec.c @@ -7,7 +7,6 @@ * Copyright (C) 2020 Heiko Schocher */ -#include #include #include #include diff --git a/drivers/net/qe/dm_qe_uec_phy.c b/drivers/net/qe/dm_qe_uec_phy.c index a0bcc8d3e55..8c0168be859 100644 --- a/drivers/net/qe/dm_qe_uec_phy.c +++ b/drivers/net/qe/dm_qe_uec_phy.c @@ -8,7 +8,6 @@ * Copyright (C) 2020 Heiko Schocher */ -#include #include #include #include diff --git a/drivers/net/qe/uccf.c b/drivers/net/qe/uccf.c index 00848a1a37d..badf4e5db3e 100644 --- a/drivers/net/qe/uccf.c +++ b/drivers/net/qe/uccf.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include diff --git a/drivers/net/qe/uccf.h b/drivers/net/qe/uccf.h index 99f8458edf6..e60bbe241cd 100644 --- a/drivers/net/qe/uccf.h +++ b/drivers/net/qe/uccf.h @@ -9,8 +9,8 @@ #ifndef __UCCF_H__ #define __UCCF_H__ -#include "common.h" -#include "linux/immap_qe.h" +#include +#include #include /* Fast or Giga ethernet */ diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index 4764bca7082..f1401d2f6ed 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -8,7 +8,6 @@ * Based on the SuperH Ethernet driver. */ -#include #include #include #include diff --git a/drivers/net/rswitch.c b/drivers/net/rswitch.c index 5a69ca1a0f9..8e1b6e2f6f6 100644 --- a/drivers/net/rswitch.c +++ b/drivers/net/rswitch.c @@ -9,7 +9,6 @@ #include #include -#include #include #include #include diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c index d8f24ec81a2..2e0afad089f 100644 --- a/drivers/net/rtl8139.c +++ b/drivers/net/rtl8139.c @@ -68,7 +68,6 @@ * */ -#include #include #include #include diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index 93e83661cec..e80aebc0bcf 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -39,7 +39,6 @@ * 26 August 2006 Mihai Georgian * Modified to use le32_to_cpu and cpu_to_le32 properly */ -#include #include #include #include diff --git a/drivers/net/sandbox-raw-bus.c b/drivers/net/sandbox-raw-bus.c index fb1ba5a8c83..15670d6d24a 100644 --- a/drivers/net/sandbox-raw-bus.c +++ b/drivers/net/sandbox-raw-bus.c @@ -4,7 +4,6 @@ * Copyright (c) 2018 Joe Hershberger */ -#include #include #include #include diff --git a/drivers/net/sandbox-raw.c b/drivers/net/sandbox-raw.c index 99eb7a3bbff..1d716716778 100644 --- a/drivers/net/sandbox-raw.c +++ b/drivers/net/sandbox-raw.c @@ -8,7 +8,6 @@ #include #include -#include #include #include #include diff --git a/drivers/net/sandbox.c b/drivers/net/sandbox.c index 13022addb6a..fe3627db6e3 100644 --- a/drivers/net/sandbox.c +++ b/drivers/net/sandbox.c @@ -6,7 +6,6 @@ * Joe Hershberger */ -#include #include #include #include diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 7b1f59dc498..f1ce994cfd5 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -9,7 +9,6 @@ */ #include -#include #include #include #include diff --git a/drivers/net/sja1105.c b/drivers/net/sja1105.c index 48f044c6472..0ba84a4496f 100644 --- a/drivers/net/sja1105.c +++ b/drivers/net/sja1105.c @@ -8,7 +8,6 @@ * Ported from Linux (drivers/net/dsa/sja1105/). */ -#include #include #include #include diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 616b7ce174f..f39ba40944f 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -5,7 +5,6 @@ * (c) 2007 Pengutronix, Sascha Hauer */ -#include #include #include #include diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 8bff4fe9a9e..f4b97798d2d 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c index f546ad1fe8d..3dee849c97e 100644 --- a/drivers/net/sunxi_emac.c +++ b/drivers/net/sunxi_emac.c @@ -5,7 +5,6 @@ * (C) Copyright 2012, Stefan Roese */ -#include #include #include #include diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index 65ade1afd05..c70b42f6bcc 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -6,7 +6,6 @@ * */ -#include #include #include #include diff --git a/drivers/net/ti/cpsw-common.c b/drivers/net/ti/cpsw-common.c index d5428274d19..3e66d7c7bdf 100644 --- a/drivers/net/ti/cpsw-common.c +++ b/drivers/net/ti/cpsw-common.c @@ -5,7 +5,6 @@ * Copyright (C) 2016, Texas Instruments, Incorporated */ -#include #include #include #include diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c index 9a5e9642df1..d7746f454ba 100644 --- a/drivers/net/ti/cpsw.c +++ b/drivers/net/ti/cpsw.c @@ -5,7 +5,6 @@ * Copyright (C) 2010-2018 Texas Instruments Incorporated - https://www.ti.com/ */ -#include #include #include #include diff --git a/drivers/net/ti/cpsw_mdio.c b/drivers/net/ti/cpsw_mdio.c index f1b1eba75d0..9e0083ca789 100644 --- a/drivers/net/ti/cpsw_mdio.c +++ b/drivers/net/ti/cpsw_mdio.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/drivers/net/ti/davinci_emac.c b/drivers/net/ti/davinci_emac.c index 034877a7690..03a1a7a1159 100644 --- a/drivers/net/ti/davinci_emac.c +++ b/drivers/net/ti/davinci_emac.c @@ -21,7 +21,7 @@ * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot. * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors */ -#include +#include #include #include #include diff --git a/drivers/net/ti/keystone_net.c b/drivers/net/ti/keystone_net.c index 43dbf3f1067..c6e5bf21cf0 100644 --- a/drivers/net/ti/keystone_net.c +++ b/drivers/net/ti/keystone_net.c @@ -5,7 +5,6 @@ * (C) Copyright 2012-2014 * Texas Instruments Incorporated, */ -#include #include #include #include diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 8833e3098d5..6481ee24a60 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -8,7 +8,6 @@ */ #include -#include #include #include #include diff --git a/drivers/net/vsc7385.c b/drivers/net/vsc7385.c index 09883f06be2..bd1869dfc83 100644 --- a/drivers/net/vsc7385.c +++ b/drivers/net/vsc7385.c @@ -13,7 +13,6 @@ */ #include -#include #include #include #include diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index ef151ee51b4..a1a39f61488 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -7,7 +7,6 @@ */ #include -#include #include #include #include diff --git a/drivers/net/xilinx_axi_mrmac.c b/drivers/net/xilinx_axi_mrmac.c index 410fb25ddef..555651937f8 100644 --- a/drivers/net/xilinx_axi_mrmac.c +++ b/drivers/net/xilinx_axi_mrmac.c @@ -9,7 +9,6 @@ */ #include -#include #include #include #include diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 16ba915fbaa..c25ac2e6600 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -6,7 +6,6 @@ * Michal SIMEK */ -#include #include #include #include diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 7c57d32614f..b41ee95892e 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -9,7 +9,6 @@ */ #include -#include #include #include #include diff --git a/drivers/nvme/nvme-uclass.c b/drivers/nvme/nvme-uclass.c index f3af6a27b63..44c88ad27f3 100644 --- a/drivers/nvme/nvme-uclass.c +++ b/drivers/nvme/nvme-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_NVME -#include #include #include #include diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c index 59a139baa0b..7c58ceb78f5 100644 --- a/drivers/nvme/nvme.c +++ b/drivers/nvme/nvme.c @@ -4,7 +4,6 @@ * Copyright (C) 2017 Bin Meng */ -#include #include #include #include diff --git a/drivers/nvme/nvme_apple.c b/drivers/nvme/nvme_apple.c index 819b748dc02..7e7538553e3 100644 --- a/drivers/nvme/nvme_apple.c +++ b/drivers/nvme/nvme_apple.c @@ -3,7 +3,6 @@ * (C) Copyright 2021 Mark Kettenis */ -#include #include #include #include diff --git a/drivers/nvme/nvme_pci.c b/drivers/nvme/nvme_pci.c index 5bb43d299fc..c24f8cf1eb1 100644 --- a/drivers/nvme/nvme_pci.c +++ b/drivers/nvme/nvme_pci.c @@ -4,7 +4,6 @@ * Copyright (C) 2017 Bin Meng */ -#include #include #include #include diff --git a/drivers/nvme/nvme_show.c b/drivers/nvme/nvme_show.c index 72cbac82bcc..158102363e9 100644 --- a/drivers/nvme/nvme_show.c +++ b/drivers/nvme/nvme_show.c @@ -4,7 +4,6 @@ * Copyright (C) 2017 Bin Meng */ -#include #include #include #include diff --git a/drivers/pch/pch-uclass.c b/drivers/pch/pch-uclass.c index af028f9ceca..9af24758004 100644 --- a/drivers/pch/pch-uclass.c +++ b/drivers/pch/pch-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_PCH -#include #include #include diff --git a/drivers/pch/pch7.c b/drivers/pch/pch7.c index 5fb35a19eff..4ef82a77e27 100644 --- a/drivers/pch/pch7.c +++ b/drivers/pch/pch7.c @@ -3,7 +3,6 @@ * Copyright (C) 2014 Google, Inc */ -#include #include #include #include diff --git a/drivers/pch/pch9.c b/drivers/pch/pch9.c index 3137eb2c28f..24b0465efde 100644 --- a/drivers/pch/pch9.c +++ b/drivers/pch/pch9.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_PCH -#include #include #include #include diff --git a/drivers/pch/sandbox_pch.c b/drivers/pch/sandbox_pch.c index 37c368954b4..aa82dca560f 100644 --- a/drivers/pch/sandbox_pch.c +++ b/drivers/pch/sandbox_pch.c @@ -3,7 +3,6 @@ * Copyright 2018 Google LLC */ -#include #include #include diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index af0e55cd2f2..f5db4bdb760 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -25,7 +25,6 @@ * */ -#include #include #include #include diff --git a/drivers/pci/pci-emul-uclass.c b/drivers/pci/pci-emul-uclass.c index a0b8afb87a0..166ee9fcd43 100644 --- a/drivers/pci/pci-emul-uclass.c +++ b/drivers/pci/pci-emul-uclass.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/pci/pci-rcar-gen2.c b/drivers/pci/pci-rcar-gen2.c index b81eb353689..12c31e74087 100644 --- a/drivers/pci/pci-rcar-gen2.c +++ b/drivers/pci/pci-rcar-gen2.c @@ -5,7 +5,7 @@ * Copyright (C) 2018 Marek Vasut */ -#include +#include #include #include #include diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c index 1252ef74c58..76878246f1e 100644 --- a/drivers/pci/pci-rcar-gen3.c +++ b/drivers/pci/pci-rcar-gen3.c @@ -15,7 +15,6 @@ * Author: Phil Edworthy */ -#include #include #include #include diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 1a48256de03..6571e653049 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_PCI -#include #include #include #include diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index 01230360bad..90f81886445 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -8,7 +8,7 @@ * Copyright (c) 2021 Maciej W. Rozycki */ -#include +#include #include #include #include diff --git a/drivers/pci/pci_auto_common.c b/drivers/pci/pci_auto_common.c index 2f4aff01049..cfa818ed821 100644 --- a/drivers/pci/pci_auto_common.c +++ b/drivers/pci/pci_auto_common.c @@ -11,7 +11,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/pci/pci_common.c b/drivers/pci/pci_common.c index a18251297fd..a57cf11cc53 100644 --- a/drivers/pci/pci_common.c +++ b/drivers/pci/pci_common.c @@ -9,7 +9,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include diff --git a/drivers/pci/pci_compat.c b/drivers/pci/pci_compat.c index 9dddca8efe0..8233925e525 100644 --- a/drivers/pci/pci_compat.c +++ b/drivers/pci/pci_compat.c @@ -4,7 +4,6 @@ * * Copyright (C) 2014 Google, Inc */ -#include #include #include #include diff --git a/drivers/pci/pci_ftpci100.c b/drivers/pci/pci_ftpci100.c index a1775445005..43275b3d6a2 100644 --- a/drivers/pci/pci_ftpci100.c +++ b/drivers/pci/pci_ftpci100.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-or-later -#include #include #include #include diff --git a/drivers/pci/pci_mpc85xx.c b/drivers/pci/pci_mpc85xx.c index 249cfe66466..c07feba7976 100644 --- a/drivers/pci/pci_mpc85xx.c +++ b/drivers/pci/pci_mpc85xx.c @@ -4,7 +4,6 @@ * Heiko Schocher, DENX Software Engineering, hs@denx.de. * */ -#include #include #include #include diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index 83559550e6f..77815513b76 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -10,7 +10,6 @@ * Pali Rohár */ -#include #include #include #include diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 438583aa017..78e5de937cd 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -24,7 +24,6 @@ #define LOG_CATEGORY UCLASS_PCI -#include #include #include #include @@ -36,6 +35,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/pci/pci_sandbox.c b/drivers/pci/pci_sandbox.c index ca44d002371..fed0850458d 100644 --- a/drivers/pci/pci_sandbox.c +++ b/drivers/pci/pci_sandbox.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/pci/pci_sh7751.c b/drivers/pci/pci_sh7751.c index c1be56ce7a0..3cd01e9b94a 100644 --- a/drivers/pci/pci_sh7751.c +++ b/drivers/pci/pci_sh7751.c @@ -5,7 +5,7 @@ * (C) 2007,2008 Nobuhiro Iwamatsu */ -#include +#include #include #include #include diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c index d6374a58e33..bb8832c6ab9 100644 --- a/drivers/pci/pci_tegra.c +++ b/drivers/pci/pci_tegra.c @@ -11,7 +11,6 @@ #define pr_fmt(fmt) "tegra-pcie: " fmt -#include #include #include #include diff --git a/drivers/pci/pci_x86.c b/drivers/pci/pci_x86.c index 8d036930e73..ab76166451c 100644 --- a/drivers/pci/pci_x86.c +++ b/drivers/pci/pci_x86.c @@ -3,7 +3,6 @@ * Copyright (c) 2015 Google, Inc */ -#include #include #include #include diff --git a/drivers/pci/pcie_apple.c b/drivers/pci/pcie_apple.c index 21bafba3b0e..6a8e715d4b6 100644 --- a/drivers/pci/pcie_apple.c +++ b/drivers/pci/pcie_apple.c @@ -16,7 +16,6 @@ * Author: Marc Zyngier */ -#include #include #include #include diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c index cd45f0bee9b..f978c64365c 100644 --- a/drivers/pci/pcie_brcmstb.c +++ b/drivers/pci/pcie_brcmstb.c @@ -12,7 +12,6 @@ * Copyright (C) 2020 Nicolas Saenz Julienne */ -#include #include #include #include diff --git a/drivers/pci/pcie_dw_common.c b/drivers/pci/pcie_dw_common.c index 74fb6df412c..0673e516c6f 100644 --- a/drivers/pci/pcie_dw_common.c +++ b/drivers/pci/pcie_dw_common.c @@ -8,7 +8,6 @@ * Copyright (C) 2018 Texas Instruments, Inc */ -#include #include #include #include diff --git a/drivers/pci/pcie_dw_meson.c b/drivers/pci/pcie_dw_meson.c index f953797908b..bb78e7874b1 100644 --- a/drivers/pci/pcie_dw_meson.c +++ b/drivers/pci/pcie_dw_meson.c @@ -9,7 +9,6 @@ * Copyright (c) 2021 Rockchip, Inc. */ -#include #include #include #include diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c index c41f3f15304..43b919175c9 100644 --- a/drivers/pci/pcie_dw_mvebu.c +++ b/drivers/pci/pcie_dw_mvebu.c @@ -10,10 +10,11 @@ * - drivers/pci/pcie_xilinx.c */ -#include +#include #include #include #include +#include #include #include #include diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c index bc4635f6713..1bad51fb3eb 100644 --- a/drivers/pci/pcie_dw_rockchip.c +++ b/drivers/pci/pcie_dw_rockchip.c @@ -5,7 +5,6 @@ * Copyright (c) 2021 Rockchip, Inc. */ -#include #include #include #include diff --git a/drivers/pci/pcie_dw_sifive.c b/drivers/pci/pcie_dw_sifive.c index fac3f182372..6285edf4b03 100644 --- a/drivers/pci/pcie_dw_sifive.c +++ b/drivers/pci/pcie_dw_sifive.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/pci/pcie_dw_ti.c b/drivers/pci/pcie_dw_ti.c index 4195a02de39..78a5d035865 100644 --- a/drivers/pci/pcie_dw_ti.c +++ b/drivers/pci/pcie_dw_ti.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Texas Instruments, Inc */ -#include #include #include #include diff --git a/drivers/pci/pcie_ecam_generic.c b/drivers/pci/pcie_ecam_generic.c index f5bc6e3d92d..3cb2bbbccb4 100644 --- a/drivers/pci/pcie_ecam_generic.c +++ b/drivers/pci/pcie_ecam_generic.c @@ -7,7 +7,6 @@ * Copyright (C) 2016 Imagination Technologies */ -#include #include #include #include diff --git a/drivers/pci/pcie_ecam_synquacer.c b/drivers/pci/pcie_ecam_synquacer.c index e3e22891088..fc855dfca4e 100644 --- a/drivers/pci/pcie_ecam_synquacer.c +++ b/drivers/pci/pcie_ecam_synquacer.c @@ -8,7 +8,6 @@ * Copyright (C) 2021 Linaro Ltd. */ -#include #include #include #include diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index ec917ee7d5b..18af23c9504 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -6,7 +6,7 @@ * Author: Hou Zhiqiang */ -#include +#include #include #include #include diff --git a/drivers/pci/pcie_fsl_fixup.c b/drivers/pci/pcie_fsl_fixup.c index f4e227895d1..9187e7af746 100644 --- a/drivers/pci/pcie_fsl_fixup.c +++ b/drivers/pci/pcie_fsl_fixup.c @@ -6,7 +6,6 @@ * Author: Hou Zhiqiang */ -#include #ifdef CONFIG_OF_BOARD_SETUP #include #include diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 78f2c7d6bcd..11c4ccbfc55 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -17,7 +17,6 @@ * those too in order to have a single modern PCIe iMX driver. */ -#include #include #include #include diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c index 60195cfe1b6..959fd369086 100644 --- a/drivers/pci/pcie_intel_fpga.c +++ b/drivers/pci/pcie_intel_fpga.c @@ -6,7 +6,6 @@ * */ -#include #include #include #include diff --git a/drivers/pci/pcie_iproc.c b/drivers/pci/pcie_iproc.c index d6d3a9e2025..360ef1b011f 100644 --- a/drivers/pci/pcie_iproc.c +++ b/drivers/pci/pcie_iproc.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 3c7c4ca18e8..1be33095b9c 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -5,7 +5,6 @@ * Layerscape PCIe driver */ -#include #include #include #include diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c index 83f7eebd627..3520488b345 100644 --- a/drivers/pci/pcie_layerscape_ep.c +++ b/drivers/pci/pcie_layerscape_ep.c @@ -4,7 +4,7 @@ * Layerscape PCIe EP driver */ -#include +#include #include #include #include diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c index c5198353957..ec4a7e7b657 100644 --- a/drivers/pci/pcie_layerscape_fixup.c +++ b/drivers/pci/pcie_layerscape_fixup.c @@ -5,7 +5,6 @@ * Layerscape PCIe driver */ -#include #include #include #include diff --git a/drivers/pci/pcie_layerscape_fixup_common.c b/drivers/pci/pcie_layerscape_fixup_common.c index 095874a9276..f37e37f6b15 100644 --- a/drivers/pci/pcie_layerscape_fixup_common.c +++ b/drivers/pci/pcie_layerscape_fixup_common.c @@ -7,10 +7,10 @@ * */ -#include #include #include #include +#include #include #include #include "pcie_layerscape_fixup_common.h" diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c index 021c975869f..57dc91f2fae 100644 --- a/drivers/pci/pcie_layerscape_gen4.c +++ b/drivers/pci/pcie_layerscape_gen4.c @@ -6,7 +6,7 @@ * Author: Hou Zhiqiang */ -#include +#include #include #include #include diff --git a/drivers/pci/pcie_layerscape_gen4_fixup.c b/drivers/pci/pcie_layerscape_gen4_fixup.c index b2a45bf105c..60c4338bcdb 100644 --- a/drivers/pci/pcie_layerscape_gen4_fixup.c +++ b/drivers/pci/pcie_layerscape_gen4_fixup.c @@ -7,7 +7,6 @@ * */ -#include #include #include #include diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c index 6a5bf88da23..e7913d43a8b 100644 --- a/drivers/pci/pcie_layerscape_rc.c +++ b/drivers/pci/pcie_layerscape_rc.c @@ -4,7 +4,6 @@ * Layerscape PCIe driver */ -#include #include #include #include diff --git a/drivers/pci/pcie_mediatek.c b/drivers/pci/pcie_mediatek.c index f0f34b5d119..04d8cc29afd 100644 --- a/drivers/pci/pcie_mediatek.c +++ b/drivers/pci/pcie_mediatek.c @@ -7,7 +7,6 @@ * Honghui Zhang */ -#include #include #include #include diff --git a/drivers/pci/pcie_phytium.c b/drivers/pci/pcie_phytium.c index 3bd1f5cd6d9..94de89bcad7 100644 --- a/drivers/pci/pcie_phytium.c +++ b/drivers/pci/pcie_phytium.c @@ -7,7 +7,6 @@ * Copyright (C) 2019 */ -#include #include #include #include diff --git a/drivers/pci/pcie_plda_common.c b/drivers/pci/pcie_plda_common.c index cd74bb47116..622a5cee109 100644 --- a/drivers/pci/pcie_plda_common.c +++ b/drivers/pci/pcie_plda_common.c @@ -6,7 +6,6 @@ * */ -#include #include #include #include diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c index 624841e9d8b..19f9e58a640 100644 --- a/drivers/pci/pcie_rockchip.c +++ b/drivers/pci/pcie_rockchip.c @@ -11,7 +11,6 @@ * Bits taken from Linux Rockchip PCIe host controller. */ -#include #include #include #include diff --git a/drivers/pci/pcie_starfive_jh7110.c b/drivers/pci/pcie_starfive_jh7110.c index 903a544d37f..569fbfd35c8 100644 --- a/drivers/pci/pcie_starfive_jh7110.c +++ b/drivers/pci/pcie_starfive_jh7110.c @@ -7,7 +7,6 @@ * */ -#include #include #include #include diff --git a/drivers/pci/pcie_uniphier.c b/drivers/pci/pcie_uniphier.c index f2edea9899a..d1170b576bc 100644 --- a/drivers/pci/pcie_uniphier.c +++ b/drivers/pci/pcie_uniphier.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/drivers/pci/pcie_xilinx.c b/drivers/pci/pcie_xilinx.c index 3db460b5f93..a674ab04bee 100644 --- a/drivers/pci/pcie_xilinx.c +++ b/drivers/pci/pcie_xilinx.c @@ -5,7 +5,6 @@ * Copyright (C) 2016 Imagination Technologies */ -#include #include #include #include diff --git a/drivers/pci_endpoint/pci_ep-uclass.c b/drivers/pci_endpoint/pci_ep-uclass.c index 6ee4cfbdb4a..902d1a51eaa 100644 --- a/drivers/pci_endpoint/pci_ep-uclass.c +++ b/drivers/pci_endpoint/pci_ep-uclass.c @@ -11,7 +11,6 @@ #define LOG_CATEGORY UCLASS_PCI_EP -#include #include #include #include diff --git a/drivers/pci_endpoint/pcie-cadence-ep.c b/drivers/pci_endpoint/pcie-cadence-ep.c index d58c64982b2..e02ea14e4e4 100644 --- a/drivers/pci_endpoint/pcie-cadence-ep.c +++ b/drivers/pci_endpoint/pcie-cadence-ep.c @@ -4,7 +4,6 @@ * Written by Ramon Fried */ -#include #include #include #include diff --git a/drivers/pci_endpoint/sandbox-pci_ep.c b/drivers/pci_endpoint/sandbox-pci_ep.c index de148cddb91..aa623fa357d 100644 --- a/drivers/pci_endpoint/sandbox-pci_ep.c +++ b/drivers/pci_endpoint/sandbox-pci_ep.c @@ -3,7 +3,6 @@ * Copyright (c) 2019 Ramon Fried */ -#include #include #include #include diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index 6624e9134f4..b9306c9a827 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -10,7 +10,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include #include #include #include diff --git a/drivers/phy/bcm6318-usbh-phy.c b/drivers/phy/bcm6318-usbh-phy.c index a2fa446cb1c..d715541bd4c 100644 --- a/drivers/phy/bcm6318-usbh-phy.c +++ b/drivers/phy/bcm6318-usbh-phy.c @@ -7,7 +7,6 @@ * Copyright 2013 Florian Fainelli */ -#include #include #include #include diff --git a/drivers/phy/bcm6348-usbh-phy.c b/drivers/phy/bcm6348-usbh-phy.c index 857fb575ef1..ffb37b634a3 100644 --- a/drivers/phy/bcm6348-usbh-phy.c +++ b/drivers/phy/bcm6348-usbh-phy.c @@ -7,7 +7,6 @@ * Copyright 2013 Florian Fainelli */ -#include #include #include #include diff --git a/drivers/phy/bcm6358-usbh-phy.c b/drivers/phy/bcm6358-usbh-phy.c index bfdcfb0d245..a8d24609bfc 100644 --- a/drivers/phy/bcm6358-usbh-phy.c +++ b/drivers/phy/bcm6358-usbh-phy.c @@ -7,7 +7,6 @@ * Copyright 2013 Florian Fainelli */ -#include #include #include #include diff --git a/drivers/phy/bcm6368-usbh-phy.c b/drivers/phy/bcm6368-usbh-phy.c index 1a2870d5149..5bee130425d 100644 --- a/drivers/phy/bcm6368-usbh-phy.c +++ b/drivers/phy/bcm6368-usbh-phy.c @@ -7,7 +7,6 @@ * Copyright 2013 Florian Fainelli */ -#include #include #include #include diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 4bb8a0ca7f3..f5e23f36c56 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -11,7 +11,6 @@ * Jean-Jacques Hiblot * */ -#include #include #include #include diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c index ef924e7af50..d4e8ece4935 100644 --- a/drivers/phy/cadence/phy-cadence-torrent.c +++ b/drivers/phy/cadence/phy-cadence-torrent.c @@ -10,7 +10,6 @@ * */ -#include #include #include #include diff --git a/drivers/phy/keystone-usb-phy.c b/drivers/phy/keystone-usb-phy.c index 3bb9c0814c1..cfc15203d63 100644 --- a/drivers/phy/keystone-usb-phy.c +++ b/drivers/phy/keystone-usb-phy.c @@ -4,7 +4,6 @@ * Written by Jean-Jacques Hiblot */ -#include #include #include #include diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index c490dc69c69..bca325d1996 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -3,7 +3,6 @@ * Copyright (C) 2015-2016 Marvell International Ltd. */ -#include #include #include #include diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index 7272dfb9fe8..a666a4e794e 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -5,7 +5,6 @@ * Copyright (C) 2016 Stefan Roese */ -#include #include #include #include diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index bb15fbaf347..b8cdedf6edf 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -3,7 +3,6 @@ * Copyright (C) 2015-2016 Marvell International Ltd. */ -#include #include #include #include @@ -12,6 +11,7 @@ #include #include #include +#include #include #include "comphy_core.h" diff --git a/drivers/phy/marvell/comphy_mux.c b/drivers/phy/marvell/comphy_mux.c index 10981d25ec9..a8aa37fc46f 100644 --- a/drivers/phy/marvell/comphy_mux.c +++ b/drivers/phy/marvell/comphy_mux.c @@ -3,7 +3,6 @@ * Copyright (C) 2015-2016 Marvell International Ltd. */ -#include #include #include diff --git a/drivers/phy/meson-axg-mipi-dphy.c b/drivers/phy/meson-axg-mipi-dphy.c index faa1d9d6d37..3f89de19970 100644 --- a/drivers/phy/meson-axg-mipi-dphy.c +++ b/drivers/phy/meson-axg-mipi-dphy.c @@ -7,7 +7,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/drivers/phy/meson-axg-mipi-pcie-analog.c b/drivers/phy/meson-axg-mipi-pcie-analog.c index 236ea1ce5ca..731917cef43 100644 --- a/drivers/phy/meson-axg-mipi-pcie-analog.c +++ b/drivers/phy/meson-axg-mipi-pcie-analog.c @@ -7,7 +7,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/drivers/phy/meson-g12a-usb2.c b/drivers/phy/meson-g12a-usb2.c index 3958d2404b8..8cded12438b 100644 --- a/drivers/phy/meson-g12a-usb2.c +++ b/drivers/phy/meson-g12a-usb2.c @@ -7,7 +7,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/drivers/phy/meson-g12a-usb3-pcie.c b/drivers/phy/meson-g12a-usb3-pcie.c index 1eaff410efa..4d183867c3a 100644 --- a/drivers/phy/meson-g12a-usb3-pcie.c +++ b/drivers/phy/meson-g12a-usb3-pcie.c @@ -7,7 +7,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/drivers/phy/meson-gxbb-usb2.c b/drivers/phy/meson-gxbb-usb2.c index 725b056a71a..4c88ccf3927 100644 --- a/drivers/phy/meson-gxbb-usb2.c +++ b/drivers/phy/meson-gxbb-usb2.c @@ -8,7 +8,6 @@ * Author: Beniamino Galvani */ -#include #include #include #include diff --git a/drivers/phy/meson-gxl-usb2.c b/drivers/phy/meson-gxl-usb2.c index d633effa404..92c285103c4 100644 --- a/drivers/phy/meson-gxl-usb2.c +++ b/drivers/phy/meson-gxl-usb2.c @@ -7,7 +7,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/drivers/phy/mt76x8-usb-phy.c b/drivers/phy/mt76x8-usb-phy.c index 4069208b679..99f8a221f5a 100644 --- a/drivers/phy/mt76x8-usb-phy.c +++ b/drivers/phy/mt76x8-usb-phy.c @@ -7,7 +7,6 @@ */ #include -#include #include #include #include diff --git a/drivers/phy/nop-phy.c b/drivers/phy/nop-phy.c index c53e3216d0f..286171cba76 100644 --- a/drivers/phy/nop-phy.c +++ b/drivers/phy/nop-phy.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/drivers/phy/omap-usb2-phy.c b/drivers/phy/omap-usb2-phy.c index d3d38062ecf..2be0178882a 100644 --- a/drivers/phy/omap-usb2-phy.c +++ b/drivers/phy/omap-usb2-phy.c @@ -6,7 +6,6 @@ * Written by Jean-Jacques Hiblot */ -#include #include #include #include diff --git a/drivers/phy/phy-ab8500-usb.c b/drivers/phy/phy-ab8500-usb.c index 3d3d48c9733..5de7b6f86cc 100644 --- a/drivers/phy/phy-ab8500-usb.c +++ b/drivers/phy/phy-ab8500-usb.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* Copyright (C) 2019 Stephan Gerhold */ -#include #include #include #include diff --git a/drivers/phy/phy-apple-atc.c b/drivers/phy/phy-apple-atc.c index 15c5b8a1c2d..78eedf676b0 100644 --- a/drivers/phy/phy-apple-atc.c +++ b/drivers/phy/phy-apple-atc.c @@ -3,7 +3,6 @@ * Copyright (C) 2022 Mark Kettenis */ -#include #include #include #include diff --git a/drivers/phy/phy-bcm-sr-pcie.c b/drivers/phy/phy-bcm-sr-pcie.c index cf33bab3707..97859a0cb87 100644 --- a/drivers/phy/phy-bcm-sr-pcie.c +++ b/drivers/phy/phy-bcm-sr-pcie.c @@ -3,7 +3,6 @@ * Copyright (C) 2019 Broadcom */ -#include #include #include #include diff --git a/drivers/phy/phy-core-mipi-dphy.c b/drivers/phy/phy-core-mipi-dphy.c index bb61816add2..8fb985a1e68 100644 --- a/drivers/phy/phy-core-mipi-dphy.c +++ b/drivers/phy/phy-core-mipi-dphy.c @@ -4,8 +4,8 @@ * Copyright (C) 2018 Cadence Design Systems Inc. */ -#include #include +#include #include #include diff --git a/drivers/phy/phy-da8xx-usb.c b/drivers/phy/phy-da8xx-usb.c index d025188eae9..cf26aaaa3d8 100644 --- a/drivers/phy/phy-da8xx-usb.c +++ b/drivers/phy/phy-da8xx-usb.c @@ -6,9 +6,9 @@ * DT support added by: Adam Ford */ -#include #include #include +#include #include #include #include diff --git a/drivers/phy/phy-imx8mq-usb.c b/drivers/phy/phy-imx8mq-usb.c index e5e96e77a68..75763046adc 100644 --- a/drivers/phy/phy-imx8mq-usb.c +++ b/drivers/phy/phy-imx8mq-usb.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/drivers/phy/phy-mtk-tphy.c b/drivers/phy/phy-mtk-tphy.c index ea9edf212c6..6f9ac1528e8 100644 --- a/drivers/phy/phy-mtk-tphy.c +++ b/drivers/phy/phy-mtk-tphy.c @@ -5,7 +5,6 @@ * Ryder Lee */ -#include #include #include #include diff --git a/drivers/phy/phy-npcm-usb.c b/drivers/phy/phy-npcm-usb.c index 09fb14e26f0..2cca0f4a054 100644 --- a/drivers/phy/phy-npcm-usb.c +++ b/drivers/phy/phy-npcm-usb.c @@ -3,7 +3,6 @@ * Copyright (c) 2021 Nuvoton Technology Corp. */ -#include #include #include #include diff --git a/drivers/phy/phy-rcar-gen2.c b/drivers/phy/phy-rcar-gen2.c index e528c4ec579..f9428c7ad12 100644 --- a/drivers/phy/phy-rcar-gen2.c +++ b/drivers/phy/phy-rcar-gen2.c @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut */ -#include #include #include #include diff --git a/drivers/phy/phy-rcar-gen3.c b/drivers/phy/phy-rcar-gen3.c index 03c747b373b..7c292cae0e2 100644 --- a/drivers/phy/phy-rcar-gen3.c +++ b/drivers/phy/phy-rcar-gen3.c @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut */ -#include #include #include #include diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c index 000e495dbd4..8d643b762f9 100644 --- a/drivers/phy/phy-stm32-usbphyc.c +++ b/drivers/phy/phy-stm32-usbphyc.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_PHY -#include #include #include #include diff --git a/drivers/phy/phy-ti-am654.c b/drivers/phy/phy-ti-am654.c index 70a746d2c92..c3d9972397a 100644 --- a/drivers/phy/phy-ti-am654.c +++ b/drivers/phy/phy-ti-am654.c @@ -6,7 +6,6 @@ * Author: Kishon Vijay Abraham I */ -#include #include #include #include diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c index 0dcfe258bc4..acdcda15b5b 100644 --- a/drivers/phy/phy-uclass.c +++ b/drivers/phy/phy-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_PHY -#include #include #include #include diff --git a/drivers/phy/phy-zynqmp.c b/drivers/phy/phy-zynqmp.c index d1288bb17f3..7049e740d56 100644 --- a/drivers/phy/phy-zynqmp.c +++ b/drivers/phy/phy-zynqmp.c @@ -9,7 +9,6 @@ * Author: Laurent Pinchart */ -#include #include #include #include diff --git a/drivers/phy/qcom/msm8916-usbh-phy.c b/drivers/phy/qcom/msm8916-usbh-phy.c index f52046f7cb0..4b435aa2a6e 100644 --- a/drivers/phy/qcom/msm8916-usbh-phy.c +++ b/drivers/phy/qcom/msm8916-usbh-phy.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Ramon Fried */ -#include #include #include #include diff --git a/drivers/phy/qcom/phy-qcom-ipq4019-usb.c b/drivers/phy/qcom/phy-qcom-ipq4019-usb.c index 5808489249f..3b647324e02 100644 --- a/drivers/phy/qcom/phy-qcom-ipq4019-usb.c +++ b/drivers/phy/qcom/phy-qcom-ipq4019-usb.c @@ -8,7 +8,6 @@ */ #include -#include #include #include #include diff --git a/drivers/phy/qcom/phy-qcom-usb-hs-28nm.c b/drivers/phy/qcom/phy-qcom-usb-hs-28nm.c index 05a9a2cf1d7..c344809a608 100644 --- a/drivers/phy/qcom/phy-qcom-usb-hs-28nm.c +++ b/drivers/phy/qcom/phy-qcom-usb-hs-28nm.c @@ -5,7 +5,6 @@ * Based on Linux driver */ -#include #include #include #include diff --git a/drivers/phy/qcom/phy-qcom-usb-ss.c b/drivers/phy/qcom/phy-qcom-usb-ss.c index 1b03a3c43dc..270d09d883c 100644 --- a/drivers/phy/qcom/phy-qcom-usb-ss.c +++ b/drivers/phy/qcom/phy-qcom-usb-ss.c @@ -5,7 +5,6 @@ * Based on Linux driver */ -#include #include #include #include diff --git a/drivers/phy/renesas/r8a779f0-ether-serdes.c b/drivers/phy/renesas/r8a779f0-ether-serdes.c index bd1fdd3a667..40284ef2fd3 100644 --- a/drivers/phy/renesas/r8a779f0-ether-serdes.c +++ b/drivers/phy/renesas/r8a779f0-ether-serdes.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 9ca66bf8db9..3ad339bccc1 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -5,7 +5,6 @@ * Copyright (C) 2021 Rockchip Electronics Co., Ltd. */ -#include #include #include #include diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c index 44ca4bc7919..660037034ec 100644 --- a/drivers/phy/rockchip/phy-rockchip-pcie.c +++ b/drivers/phy/rockchip/phy-rockchip-pcie.c @@ -7,7 +7,6 @@ * Copyright (C) 2016 ROCKCHIP, Inc. */ -#include #include #include #include diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c index a4392daf4c9..2737bd81dd9 100644 --- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c +++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c @@ -5,7 +5,6 @@ * Copyright (C) 2021 Rockchip Electronics Co., Ltd. */ -#include #include #include #include diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c index 47c69dd6c45..c7459dbc5fc 100644 --- a/drivers/phy/rockchip/phy-rockchip-typec.c +++ b/drivers/phy/rockchip/phy-rockchip-typec.c @@ -8,7 +8,6 @@ * Kever Yang */ -#include #include #include #include diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c index 18e76402799..9deec47ae46 100644 --- a/drivers/phy/rockchip/phy-rockchip-usbdp.c +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c @@ -5,7 +5,6 @@ * Copyright (C) 2021 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/drivers/phy/sandbox-phy.c b/drivers/phy/sandbox-phy.c index 7e123da25fb..b159147a765 100644 --- a/drivers/phy/sandbox-phy.c +++ b/drivers/phy/sandbox-phy.c @@ -4,7 +4,6 @@ * Written by Jean-Jacques Hiblot */ -#include #include #include diff --git a/drivers/phy/socionext/phy-uniphier-pcie.c b/drivers/phy/socionext/phy-uniphier-pcie.c index d352c4ca3a9..91208dfe120 100644 --- a/drivers/phy/socionext/phy-uniphier-pcie.c +++ b/drivers/phy/socionext/phy-uniphier-pcie.c @@ -4,7 +4,6 @@ * Copyright 2019-2021 Socionext, Inc. */ -#include #include #include #include diff --git a/drivers/phy/socionext/phy-uniphier-usb3.c b/drivers/phy/socionext/phy-uniphier-usb3.c index 1d65b0b08f7..1d65c1f7da5 100644 --- a/drivers/phy/socionext/phy-uniphier-usb3.c +++ b/drivers/phy/socionext/phy-uniphier-usb3.c @@ -4,7 +4,6 @@ * Copyright 2019-2023 Socionext, Inc. */ -#include #include #include diff --git a/drivers/phy/sti_usb_phy.c b/drivers/phy/sti_usb_phy.c index 9e5ac9bfde6..2447e89f50d 100644 --- a/drivers/phy/sti_usb_phy.c +++ b/drivers/phy/sti_usb_phy.c @@ -4,7 +4,6 @@ * Author(s): Patrice Chotard, for STMicroelectronics. */ -#include #include #include #include diff --git a/drivers/phy/ti-pipe3-phy.c b/drivers/phy/ti-pipe3-phy.c index 29a35ae5ffb..62f6cc2bfbf 100644 --- a/drivers/phy/ti-pipe3-phy.c +++ b/drivers/phy/ti-pipe3-phy.c @@ -4,7 +4,6 @@ * Written by Jean-Jacques Hiblot */ -#include #include #include #include diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index daf62f5deda..c69a342e2b4 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -4,7 +4,6 @@ * Jean-Jacques Hiblot */ -#include #include #include #include diff --git a/drivers/pinctrl/aspeed/pinctrl_ast2500.c b/drivers/pinctrl/aspeed/pinctrl_ast2500.c index 93920a6389b..9e7c347caf8 100644 --- a/drivers/pinctrl/aspeed/pinctrl_ast2500.c +++ b/drivers/pinctrl/aspeed/pinctrl_ast2500.c @@ -3,7 +3,6 @@ * Copyright 2017 Google, Inc */ -#include #include #include #include diff --git a/drivers/pinctrl/aspeed/pinctrl_ast2600.c b/drivers/pinctrl/aspeed/pinctrl_ast2600.c index 8a4f9705ca9..bc12590e583 100644 --- a/drivers/pinctrl/aspeed/pinctrl_ast2600.c +++ b/drivers/pinctrl/aspeed/pinctrl_ast2600.c @@ -3,7 +3,6 @@ * Copyright (C) ASPEED Technology Inc. */ -#include #include #include #include diff --git a/drivers/pinctrl/ath79/pinctrl_ar933x.c b/drivers/pinctrl/ath79/pinctrl_ar933x.c index eb673a9f69c..61e37a2e559 100644 --- a/drivers/pinctrl/ath79/pinctrl_ar933x.c +++ b/drivers/pinctrl/ath79/pinctrl_ar933x.c @@ -3,7 +3,6 @@ * Copyright (C) 2015-2016 Wills Wang */ -#include #include #include #include diff --git a/drivers/pinctrl/ath79/pinctrl_qca953x.c b/drivers/pinctrl/ath79/pinctrl_qca953x.c index 0d534268e96..e4f695fc4d4 100644 --- a/drivers/pinctrl/ath79/pinctrl_qca953x.c +++ b/drivers/pinctrl/ath79/pinctrl_qca953x.c @@ -3,7 +3,6 @@ * Copyright (C) 2015-2016 Wills Wang */ -#include #include #include #include diff --git a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c index e949cb70900..cf9350c151e 100644 --- a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c +++ b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c @@ -10,7 +10,6 @@ * https://spdx.org/licenses */ -#include #include #include #include diff --git a/drivers/pinctrl/broadcom/pinctrl-bcm6838.c b/drivers/pinctrl/broadcom/pinctrl-bcm6838.c index 58f28a13709..7d0c09a130c 100644 --- a/drivers/pinctrl/broadcom/pinctrl-bcm6838.c +++ b/drivers/pinctrl/broadcom/pinctrl-bcm6838.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 -#include #include #include #include diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.c b/drivers/pinctrl/exynos/pinctrl-exynos.c index 8a045cdf7aa..b393127c642 100644 --- a/drivers/pinctrl/exynos/pinctrl-exynos.c +++ b/drivers/pinctrl/exynos/pinctrl-exynos.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/drivers/pinctrl/exynos/pinctrl-exynos7420.c b/drivers/pinctrl/exynos/pinctrl-exynos7420.c index 77d510d8f60..8fdf60715a5 100644 --- a/drivers/pinctrl/exynos/pinctrl-exynos7420.c +++ b/drivers/pinctrl/exynos/pinctrl-exynos7420.c @@ -5,7 +5,6 @@ * Thomas Abraham */ -#include #include #include #include diff --git a/drivers/pinctrl/exynos/pinctrl-exynos78x0.c b/drivers/pinctrl/exynos/pinctrl-exynos78x0.c index 1b696fdfd28..61b98443daf 100644 --- a/drivers/pinctrl/exynos/pinctrl-exynos78x0.c +++ b/drivers/pinctrl/exynos/pinctrl-exynos78x0.c @@ -9,7 +9,6 @@ * Thomas Abraham */ -#include #include #include #include diff --git a/drivers/pinctrl/intel/pinctrl.c b/drivers/pinctrl/intel/pinctrl.c index 1607000dedc..6cfe83a593a 100644 --- a/drivers/pinctrl/intel/pinctrl.c +++ b/drivers/pinctrl/intel/pinctrl.c @@ -16,7 +16,6 @@ #define LOG_CATEGORY UCLASS_GPIO -#include #include #include #include diff --git a/drivers/pinctrl/intel/pinctrl_apl.c b/drivers/pinctrl/intel/pinctrl_apl.c index 181a6ff2702..e554d285435 100644 --- a/drivers/pinctrl/intel/pinctrl_apl.c +++ b/drivers/pinctrl/intel/pinctrl_apl.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_GPIO -#include #include #include #include diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 0baef57c1c2..37fc28bb779 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -4,7 +4,6 @@ * Author: Ryder Lee */ -#include #include #include #include diff --git a/drivers/pinctrl/meson/pinctrl-meson-a1.c b/drivers/pinctrl/meson/pinctrl-meson-a1.c index 30cf3bc0be4..7e9ac6390b1 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-a1.c +++ b/drivers/pinctrl/meson/pinctrl-meson-a1.c @@ -6,7 +6,6 @@ * Author: Igor Prusov */ -#include #include #include #include diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c index cfe94cf9e17..52c726cf038 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c +++ b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c @@ -6,7 +6,6 @@ #include #include -#include #include #include #include diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c b/drivers/pinctrl/meson/pinctrl-meson-axg.c index 820a6c9bb1a..94e09cd3f8a 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-axg.c +++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c @@ -7,7 +7,6 @@ * Author: Xingyu Chen */ -#include #include #include #include diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c index 90a4f8056cd..24f47f82558 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-g12a.c +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c @@ -8,7 +8,6 @@ * Author: Yixun Lan */ -#include #include #include #include diff --git a/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c b/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c index 99502d89c6c..396b3a0e842 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c @@ -5,7 +5,6 @@ #include #include -#include #include #include #include diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c index 93a895c9fa7..03ae1f9f8a5 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c @@ -6,7 +6,6 @@ * Copyright (C) 2016 Endless Mobile, Inc. */ -#include #include #include #include diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c index a44145e2d4e..16517f95ddb 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c @@ -6,7 +6,6 @@ * Copyright (C) 2016 Endless Mobile, Inc. */ -#include #include #include #include diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index ee362d8464f..babf1bccc96 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -3,7 +3,6 @@ * (C) Copyright 2016 - Beniamino Galvani */ -#include #include #include #include diff --git a/drivers/pinctrl/mscc/mscc-common.c b/drivers/pinctrl/mscc/mscc-common.c index 307ed1db875..2af5587ec47 100644 --- a/drivers/pinctrl/mscc/mscc-common.c +++ b/drivers/pinctrl/mscc/mscc-common.c @@ -10,7 +10,6 @@ #include #include -#include #include #include #include diff --git a/drivers/pinctrl/mscc/pinctrl-jr2.c b/drivers/pinctrl/mscc/pinctrl-jr2.c index cb340581cc0..4ef4040cd70 100644 --- a/drivers/pinctrl/mscc/pinctrl-jr2.c +++ b/drivers/pinctrl/mscc/pinctrl-jr2.c @@ -6,7 +6,6 @@ * Copyright (c) 2018 Microsemi Corporation */ -#include #include #include #include diff --git a/drivers/pinctrl/mscc/pinctrl-luton.c b/drivers/pinctrl/mscc/pinctrl-luton.c index 325c9a9705b..7707350aace 100644 --- a/drivers/pinctrl/mscc/pinctrl-luton.c +++ b/drivers/pinctrl/mscc/pinctrl-luton.c @@ -7,7 +7,6 @@ * Copyright (c) 2018 Microsemi Corporation */ -#include #include #include #include diff --git a/drivers/pinctrl/mscc/pinctrl-ocelot.c b/drivers/pinctrl/mscc/pinctrl-ocelot.c index 57e2ef0d7c1..826388c2f74 100644 --- a/drivers/pinctrl/mscc/pinctrl-ocelot.c +++ b/drivers/pinctrl/mscc/pinctrl-ocelot.c @@ -10,7 +10,6 @@ #include #include -#include #include #include #include diff --git a/drivers/pinctrl/mscc/pinctrl-serval.c b/drivers/pinctrl/mscc/pinctrl-serval.c index a6b9796df81..2081cd6750c 100644 --- a/drivers/pinctrl/mscc/pinctrl-serval.c +++ b/drivers/pinctrl/mscc/pinctrl-serval.c @@ -6,7 +6,6 @@ * Copyright (c) 2019 Microsemi Corporation */ -#include #include #include #include diff --git a/drivers/pinctrl/mscc/pinctrl-servalt.c b/drivers/pinctrl/mscc/pinctrl-servalt.c index 8e8678580db..efa4e26d9f7 100644 --- a/drivers/pinctrl/mscc/pinctrl-servalt.c +++ b/drivers/pinctrl/mscc/pinctrl-servalt.c @@ -6,7 +6,6 @@ * Copyright (c) 2019 Microsemi Corporation */ -#include #include #include #include diff --git a/drivers/pinctrl/mtmips/pinctrl-mt7628.c b/drivers/pinctrl/mtmips/pinctrl-mt7628.c index 79c63c7caec..dc7acec4a77 100644 --- a/drivers/pinctrl/mtmips/pinctrl-mt7628.c +++ b/drivers/pinctrl/mtmips/pinctrl-mt7628.c @@ -5,7 +5,6 @@ * Author: Weijie Gao */ -#include #include #include #include diff --git a/drivers/pinctrl/mtmips/pinctrl-mtmips-common.c b/drivers/pinctrl/mtmips/pinctrl-mtmips-common.c index 869b7810685..bab34e97b61 100644 --- a/drivers/pinctrl/mtmips/pinctrl-mtmips-common.c +++ b/drivers/pinctrl/mtmips/pinctrl-mtmips-common.c @@ -5,7 +5,6 @@ * Author: Weijie Gao */ -#include #include #include #include diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index e834dddfd13..64036296e24 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -16,7 +16,6 @@ * https://spdx.org/licenses */ -#include #include #include #include diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c index 252151f3e5d..78184d2860a 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later // (C) 2022 Pali Rohár -#include #include #include #include diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c index fd49a97b5b0..0d5fa4ceb9c 100644 --- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c +++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c @@ -4,7 +4,6 @@ * https://spdx.org/licenses */ -#include #include #include #include diff --git a/drivers/pinctrl/nexell/pinctrl-nexell.c b/drivers/pinctrl/nexell/pinctrl-nexell.c index 20497a746d2..d5be7baf50d 100644 --- a/drivers/pinctrl/nexell/pinctrl-nexell.c +++ b/drivers/pinctrl/nexell/pinctrl-nexell.c @@ -5,7 +5,6 @@ * Bongyu, KOO */ -#include #include #include #include diff --git a/drivers/pinctrl/nexell/pinctrl-s5pxx18.c b/drivers/pinctrl/nexell/pinctrl-s5pxx18.c index 863eb1455d2..e7d0994f29e 100644 --- a/drivers/pinctrl/nexell/pinctrl-s5pxx18.c +++ b/drivers/pinctrl/nexell/pinctrl-s5pxx18.c @@ -7,7 +7,6 @@ * (C) Copyright 2019 Stefan Bosch */ -#include #include #include #include diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c index 1596dcc4747..ff466c49104 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx.c +++ b/drivers/pinctrl/nxp/pinctrl-imx.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Peng Fan */ -#include #include #include #include diff --git a/drivers/pinctrl/nxp/pinctrl-imx5.c b/drivers/pinctrl/nxp/pinctrl-imx5.c index b32b748cfc6..6b690fdce8f 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx5.c +++ b/drivers/pinctrl/nxp/pinctrl-imx5.c @@ -4,7 +4,6 @@ * Copyright (C) 2016 Peng Fan */ -#include #include #include diff --git a/drivers/pinctrl/nxp/pinctrl-imx6.c b/drivers/pinctrl/nxp/pinctrl-imx6.c index 6994dbb61a3..322eec87ff5 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx6.c +++ b/drivers/pinctrl/nxp/pinctrl-imx6.c @@ -4,7 +4,6 @@ * Copyright (C) 2016 Peng Fan */ -#include #include #include diff --git a/drivers/pinctrl/nxp/pinctrl-imx7.c b/drivers/pinctrl/nxp/pinctrl-imx7.c index 77ddb8e0b9d..a8275e26456 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx7.c +++ b/drivers/pinctrl/nxp/pinctrl-imx7.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Peng Fan */ -#include #include #include diff --git a/drivers/pinctrl/nxp/pinctrl-imx7ulp.c b/drivers/pinctrl/nxp/pinctrl-imx7ulp.c index 6da9ff7c5bc..7ea2dbe7d36 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx7ulp.c +++ b/drivers/pinctrl/nxp/pinctrl-imx7ulp.c @@ -5,7 +5,6 @@ * Peng Fan */ -#include #include #include diff --git a/drivers/pinctrl/nxp/pinctrl-imx8.c b/drivers/pinctrl/nxp/pinctrl-imx8.c index 46af44ecb1f..4e9a9ea6808 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx8.c +++ b/drivers/pinctrl/nxp/pinctrl-imx8.c @@ -3,7 +3,6 @@ * Copyright 2018 NXP */ -#include #include #include #include diff --git a/drivers/pinctrl/nxp/pinctrl-imx8ulp.c b/drivers/pinctrl/nxp/pinctrl-imx8ulp.c index 4e8fa08bc6e..73d3c009d5b 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx8ulp.c +++ b/drivers/pinctrl/nxp/pinctrl-imx8ulp.c @@ -4,7 +4,6 @@ * */ -#include #include #include diff --git a/drivers/pinctrl/nxp/pinctrl-imxrt.c b/drivers/pinctrl/nxp/pinctrl-imxrt.c index 53b70da869e..23f07f8d1e0 100644 --- a/drivers/pinctrl/nxp/pinctrl-imxrt.c +++ b/drivers/pinctrl/nxp/pinctrl-imxrt.c @@ -4,7 +4,6 @@ * Author(s): Giulio Benetti */ -#include #include #include diff --git a/drivers/pinctrl/nxp/pinctrl-mxs.c b/drivers/pinctrl/nxp/pinctrl-mxs.c index eb90e28d4b2..85ab5fdf640 100644 --- a/drivers/pinctrl/nxp/pinctrl-mxs.c +++ b/drivers/pinctrl/nxp/pinctrl-mxs.c @@ -4,7 +4,6 @@ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de */ -#include #include #include #include diff --git a/drivers/pinctrl/nxp/pinctrl-scu.c b/drivers/pinctrl/nxp/pinctrl-scu.c index 4959834c0fc..42d5c96468c 100644 --- a/drivers/pinctrl/nxp/pinctrl-scu.c +++ b/drivers/pinctrl/nxp/pinctrl-scu.c @@ -3,7 +3,6 @@ * Copyright 2018-2019 NXP */ -#include #include #include #include diff --git a/drivers/pinctrl/nxp/pinctrl-vf610.c b/drivers/pinctrl/nxp/pinctrl-vf610.c index 14e2e9d3ee6..adf3073f1be 100644 --- a/drivers/pinctrl/nxp/pinctrl-vf610.c +++ b/drivers/pinctrl/nxp/pinctrl-vf610.c @@ -4,7 +4,6 @@ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de */ -#include #include #include diff --git a/drivers/pinctrl/pinctrl-apple.c b/drivers/pinctrl/pinctrl-apple.c index 62476358c34..f373afde58e 100644 --- a/drivers/pinctrl/pinctrl-apple.c +++ b/drivers/pinctrl/pinctrl-apple.c @@ -3,7 +3,6 @@ * (C) Copyright 2021 Mark Kettenis */ -#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index 84b398619c4..c697a4c3456 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -6,7 +6,6 @@ * Wenyou.Yang */ -#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index b7aab12f11c..5038cb535e3 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -6,7 +6,6 @@ * Wenyou.Yang */ -#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-generic.c b/drivers/pinctrl/pinctrl-generic.c index 8909b57810a..2464acf0b85 100644 --- a/drivers/pinctrl/pinctrl-generic.c +++ b/drivers/pinctrl/pinctrl-generic.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Masahiro Yamada */ -#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-k210.c b/drivers/pinctrl/pinctrl-k210.c index ee35dfe1420..dad036610c9 100644 --- a/drivers/pinctrl/pinctrl-k210.c +++ b/drivers/pinctrl/pinctrl-k210.c @@ -3,7 +3,6 @@ * Copyright (C) 2020 Sean Anderson */ -#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-qe-io.c b/drivers/pinctrl/pinctrl-qe-io.c index dc0be7ce3bd..61db9274cc3 100644 --- a/drivers/pinctrl/pinctrl-qe-io.c +++ b/drivers/pinctrl/pinctrl-qe-io.c @@ -6,7 +6,6 @@ * based on source code of Shlomi Gridish */ -#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-sandbox.c b/drivers/pinctrl/pinctrl-sandbox.c index 77659774509..a5d056643a0 100644 --- a/drivers/pinctrl/pinctrl-sandbox.c +++ b/drivers/pinctrl/pinctrl-sandbox.c @@ -4,7 +4,6 @@ * Copyright (C) 2015 Masahiro Yamada */ -#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index d1db377c137..a3802d22d4f 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -4,7 +4,6 @@ * Copyright (C) 2021 Dario Binacchi */ -#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-sti.c b/drivers/pinctrl/pinctrl-sti.c index 1ff7ea00555..4996b69d9af 100644 --- a/drivers/pinctrl/pinctrl-sti.c +++ b/drivers/pinctrl/pinctrl-sti.c @@ -6,7 +6,6 @@ * Author(s): Patrice Chotard, for STMicroelectronics. */ -#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c index 509e2a80e9a..61f335c4eb1 100644 --- a/drivers/pinctrl/pinctrl-stmfx.c +++ b/drivers/pinctrl/pinctrl-stmfx.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_PINCTRL -#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c index b277ad5c48f..d9c76898a96 100644 --- a/drivers/pinctrl/pinctrl-uclass.c +++ b/drivers/pinctrl/pinctrl-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_PINCTRL -#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c index eb17a4290b7..6fa203a3b86 100644 --- a/drivers/pinctrl/pinctrl-zynqmp.c +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -8,7 +8,6 @@ * Copyright (C) 2021 Xilinx, Inc. All rights reserved. */ -#include #include #include #include diff --git a/drivers/pinctrl/pinctrl_pic32.c b/drivers/pinctrl/pinctrl_pic32.c index 54d97ac0ae3..9f38b56e9c0 100644 --- a/drivers/pinctrl/pinctrl_pic32.c +++ b/drivers/pinctrl/pinctrl_pic32.c @@ -4,7 +4,6 @@ * Copyright (c) 2015 Microchip Technology Inc. * Written by Purna Chandra Mandal */ -#include #include #include #include diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index 7120b8edba0..eada1001240 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_PINCTRL -#include #include #include #include diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c index b14a8921af4..0c7437822ff 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c @@ -6,7 +6,6 @@ * */ -#include #include #include "pinctrl-qcom.h" diff --git a/drivers/pinctrl/qcom/pinctrl-apq8096.c b/drivers/pinctrl/qcom/pinctrl-apq8096.c index 9697cb5beb7..132ece868bf 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8096.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8096.c @@ -6,7 +6,6 @@ * */ -#include #include #include "pinctrl-qcom.h" diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c index 26ab487857f..3215c677b26 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c @@ -7,7 +7,6 @@ * Author: Robert Marko */ -#include #include #include "pinctrl-qcom.h" diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c index e68971b37ff..3c3336e7635 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.c +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c @@ -6,7 +6,6 @@ * */ -#include #include #include #include diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c index 4b7c670c90b..fb6defaeddf 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs404.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c @@ -5,7 +5,6 @@ * (C) Copyright 2022 Sumit Garg */ -#include #include #include "pinctrl-qcom.h" diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index c1e5cc01fde..f1a23f51099 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -7,7 +7,6 @@ * */ -#include #include #include "pinctrl-qcom.h" diff --git a/drivers/pinctrl/rockchip/pinctrl-px30.c b/drivers/pinctrl/rockchip/pinctrl-px30.c index 2c35491b24d..cc7885bae40 100644 --- a/drivers/pinctrl/rockchip/pinctrl-px30.c +++ b/drivers/pinctrl/rockchip/pinctrl-px30.c @@ -3,7 +3,6 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3036.c b/drivers/pinctrl/rockchip/pinctrl-rk3036.c index afcd34396e2..b14386ccd93 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3036.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3036.c @@ -3,7 +3,6 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3066.c b/drivers/pinctrl/rockchip/pinctrl-rk3066.c index 598b63223e3..60e088a9a6f 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3066.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3066.c @@ -3,7 +3,6 @@ * (C) Copyright 2021 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3128.c b/drivers/pinctrl/rockchip/pinctrl-rk3128.c index 355c45eb7f8..d00fc3da8b2 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3128.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3128.c @@ -3,7 +3,6 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3188.c b/drivers/pinctrl/rockchip/pinctrl-rk3188.c index 9a982cbfad9..83db51f66ae 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3188.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3188.c @@ -3,7 +3,6 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rk322x.c b/drivers/pinctrl/rockchip/pinctrl-rk322x.c index 351406da2d4..b804597c048 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk322x.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk322x.c @@ -3,7 +3,6 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c index a976b7aeeb2..3870c1b7a34 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c @@ -3,7 +3,6 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3308.c b/drivers/pinctrl/rockchip/pinctrl-rk3308.c index f9ac6347eaf..2cd91b10a3b 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3308.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3308.c @@ -3,7 +3,6 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c index 65a75007677..47c2e923a1b 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c @@ -3,7 +3,6 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3368.c b/drivers/pinctrl/rockchip/pinctrl-rk3368.c index ba867a89174..9ae06ed19e9 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3368.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3368.c @@ -3,7 +3,6 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3399.c b/drivers/pinctrl/rockchip/pinctrl-rk3399.c index ae785573baf..b7a5092c032 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3399.c @@ -3,7 +3,6 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3568.c b/drivers/pinctrl/rockchip/pinctrl-rk3568.c index 1d439198260..5deedc648a4 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3568.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c @@ -3,7 +3,6 @@ * (C) Copyright 2020 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3588.c b/drivers/pinctrl/rockchip/pinctrl-rk3588.c index 548cf09bcca..98ababc7c90 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3588.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3588.c @@ -3,7 +3,6 @@ * (C) Copyright 2021 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index 8ef089994f4..3e74e2f1489 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -3,7 +3,6 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1108.c b/drivers/pinctrl/rockchip/pinctrl-rv1108.c index 5b70b503d2b..3eff5f59598 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rv1108.c +++ b/drivers/pinctrl/rockchip/pinctrl-rv1108.c @@ -3,7 +3,6 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1126.c b/drivers/pinctrl/rockchip/pinctrl-rv1126.c index eefb8b17768..efa2408b204 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rv1126.c +++ b/drivers/pinctrl/rockchip/pinctrl-rv1126.c @@ -3,7 +3,6 @@ * (C) Copyright 2020 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/drivers/pinctrl/starfive/pinctrl-starfive.c b/drivers/pinctrl/starfive/pinctrl-starfive.c index 9b09cc21cfa..95b1a752de2 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive.c @@ -7,7 +7,6 @@ * Author: Jianlong Huang */ -#include #include #include #include diff --git a/drivers/pinctrl/tegra/funcmux-tegra114.c b/drivers/pinctrl/tegra/funcmux-tegra114.c index 23a27c86888..23e9e238367 100644 --- a/drivers/pinctrl/tegra/funcmux-tegra114.c +++ b/drivers/pinctrl/tegra/funcmux-tegra114.c @@ -5,7 +5,6 @@ /* Tegra114 high-level function multiplexing */ -#include #include #include #include diff --git a/drivers/pinctrl/tegra/funcmux-tegra124.c b/drivers/pinctrl/tegra/funcmux-tegra124.c index e7ad85fde2d..b041cead344 100644 --- a/drivers/pinctrl/tegra/funcmux-tegra124.c +++ b/drivers/pinctrl/tegra/funcmux-tegra124.c @@ -6,7 +6,6 @@ /* Tegra124 high-level function multiplexing */ -#include #include #include #include diff --git a/drivers/pinctrl/tegra/funcmux-tegra20.c b/drivers/pinctrl/tegra/funcmux-tegra20.c index 90fe0cba8ea..b8c91323785 100644 --- a/drivers/pinctrl/tegra/funcmux-tegra20.c +++ b/drivers/pinctrl/tegra/funcmux-tegra20.c @@ -4,7 +4,6 @@ */ /* Tegra20 high-level function multiplexing */ -#include #include #include #include diff --git a/drivers/pinctrl/tegra/funcmux-tegra210.c b/drivers/pinctrl/tegra/funcmux-tegra210.c index 30d994a17ff..d52b6150e59 100644 --- a/drivers/pinctrl/tegra/funcmux-tegra210.c +++ b/drivers/pinctrl/tegra/funcmux-tegra210.c @@ -6,7 +6,6 @@ /* Tegra210 high-level function multiplexing */ -#include #include #include #include diff --git a/drivers/pinctrl/tegra/funcmux-tegra30.c b/drivers/pinctrl/tegra/funcmux-tegra30.c index c3ee787f33b..e31b859beb8 100644 --- a/drivers/pinctrl/tegra/funcmux-tegra30.c +++ b/drivers/pinctrl/tegra/funcmux-tegra30.c @@ -5,7 +5,6 @@ /* Tegra30 high-level function multiplexing */ -#include #include #include #include diff --git a/drivers/pinctrl/tegra/pinmux-common.c b/drivers/pinctrl/tegra/pinmux-common.c index 16b03bfe7b0..5266c8db487 100644 --- a/drivers/pinctrl/tegra/pinmux-common.c +++ b/drivers/pinctrl/tegra/pinmux-common.c @@ -4,7 +4,6 @@ * Copyright (c) 2011 The Chromium OS Authors. */ -#include #include #include #include diff --git a/drivers/pinctrl/tegra/pinmux-tegra114.c b/drivers/pinctrl/tegra/pinmux-tegra114.c index 11796602c54..15c6b653aed 100644 --- a/drivers/pinctrl/tegra/pinmux-tegra114.c +++ b/drivers/pinctrl/tegra/pinmux-tegra114.c @@ -3,7 +3,6 @@ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. */ -#include #include #include diff --git a/drivers/pinctrl/tegra/pinmux-tegra124.c b/drivers/pinctrl/tegra/pinmux-tegra124.c index 261ce64b205..6d5b720aa0e 100644 --- a/drivers/pinctrl/tegra/pinmux-tegra124.c +++ b/drivers/pinctrl/tegra/pinmux-tegra124.c @@ -3,7 +3,6 @@ * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. */ -#include #include #include diff --git a/drivers/pinctrl/tegra/pinmux-tegra20.c b/drivers/pinctrl/tegra/pinmux-tegra20.c index 0af39e74c53..c1f86476b9e 100644 --- a/drivers/pinctrl/tegra/pinmux-tegra20.c +++ b/drivers/pinctrl/tegra/pinmux-tegra20.c @@ -5,7 +5,6 @@ /* Tegra20 pin multiplexing functions */ -#include #include #include diff --git a/drivers/pinctrl/tegra/pinmux-tegra30.c b/drivers/pinctrl/tegra/pinmux-tegra30.c index d11b2aa572d..59ce9cea4a9 100644 --- a/drivers/pinctrl/tegra/pinmux-tegra30.c +++ b/drivers/pinctrl/tegra/pinmux-tegra30.c @@ -3,7 +3,6 @@ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. */ -#include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c index bdca3f2f715..eafb65496a3 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c @@ -4,7 +4,6 @@ * Author: Masahiro Yamada */ -#include #include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c index a1a3cd73859..778a9899483 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c @@ -4,7 +4,6 @@ * Author: Masahiro Yamada */ -#include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c index 7a92a46c17f..3ef10151dab 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c @@ -4,7 +4,6 @@ * Author: Masahiro Yamada */ -#include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c index d33e4d7dd25..9302e309e20 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c @@ -4,7 +4,6 @@ * Author: Masahiro Yamada */ -#include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c index 0e3eb131ecf..f7c5bf3bcae 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c @@ -4,7 +4,6 @@ * Author: Masahiro Yamada */ -#include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c index 7ba2266092f..2704a50749e 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c @@ -4,7 +4,6 @@ * Author: Masahiro Yamada */ -#include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c index 9ce2e2c270e..655ec6e6057 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c @@ -4,7 +4,6 @@ * Author: Masahiro Yamada */ -#include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c index e8c2018097c..226272c2b82 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c @@ -4,7 +4,6 @@ * Author: Masahiro Yamada */ -#include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c index 8a8f1269bb5..8df13ca209c 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c @@ -5,7 +5,6 @@ * Author: Dai Okamura */ -#include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c index 04c06fb280e..c045ae99ac5 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c @@ -4,7 +4,6 @@ * Author: Masahiro Yamada */ -#include #include #include diff --git a/drivers/power/acpi_pmc/acpi-pmc-uclass.c b/drivers/power/acpi_pmc/acpi-pmc-uclass.c index 34446a34e60..c289cede15b 100644 --- a/drivers/power/acpi_pmc/acpi-pmc-uclass.c +++ b/drivers/power/acpi_pmc/acpi-pmc-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_ACPI_PMC -#include #include #include #include diff --git a/drivers/power/acpi_pmc/pmc_emul.c b/drivers/power/acpi_pmc/pmc_emul.c index 8015031da85..8eff3d9fa7a 100644 --- a/drivers/power/acpi_pmc/pmc_emul.c +++ b/drivers/power/acpi_pmc/pmc_emul.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/power/acpi_pmc/sandbox.c b/drivers/power/acpi_pmc/sandbox.c index 8cf03f737c0..ed1bb198093 100644 --- a/drivers/power/acpi_pmc/sandbox.c +++ b/drivers/power/acpi_pmc/sandbox.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY UCLASS_ACPI_PMC -#include #include #include #include diff --git a/drivers/power/axp152.c b/drivers/power/axp152.c index a93987c1538..5a62382ab86 100644 --- a/drivers/power/axp152.c +++ b/drivers/power/axp152.c @@ -3,8 +3,8 @@ * (C) Copyright 2012 * Henrik Nordstrom */ -#include #include +#include #include #include diff --git a/drivers/power/axp209.c b/drivers/power/axp209.c index 3447b9f0113..6ae416982eb 100644 --- a/drivers/power/axp209.c +++ b/drivers/power/axp209.c @@ -4,11 +4,11 @@ * Henrik Nordstrom */ -#include #include #include #include #include +#include #ifdef CONFIG_AXP_ALDO3_VOLT_SLOPE_08 # define AXP209_VRC_SLOPE AXP209_VRC_LDO3_800uV_uS diff --git a/drivers/power/axp221.c b/drivers/power/axp221.c index d251c314b98..c22ca03f469 100644 --- a/drivers/power/axp221.c +++ b/drivers/power/axp221.c @@ -9,7 +9,6 @@ * (C) Copyright 2013 Oliver Schinagl */ -#include #include #include #include diff --git a/drivers/power/axp305.c b/drivers/power/axp305.c index 049ef07f746..0312ad9af76 100644 --- a/drivers/power/axp305.c +++ b/drivers/power/axp305.c @@ -9,7 +9,6 @@ * (C) Copyright 2013 Oliver Schinagl */ -#include #include #include #include diff --git a/drivers/power/axp313.c b/drivers/power/axp313.c index bbc9e911115..09ecb5b1ec2 100644 --- a/drivers/power/axp313.c +++ b/drivers/power/axp313.c @@ -10,7 +10,6 @@ * (C) Copyright 2013 Oliver Schinagl */ -#include #include #include #include diff --git a/drivers/power/axp809.c b/drivers/power/axp809.c index d327a584ded..9e38e1a7450 100644 --- a/drivers/power/axp809.c +++ b/drivers/power/axp809.c @@ -10,7 +10,6 @@ * (C) Copyright 2013 Oliver Schinagl */ -#include #include #include #include diff --git a/drivers/power/axp818.c b/drivers/power/axp818.c index 08286ea3b55..83ae6ecc138 100644 --- a/drivers/power/axp818.c +++ b/drivers/power/axp818.c @@ -10,7 +10,6 @@ * (C) Copyright 2013 Oliver Schinagl */ -#include #include #include #include diff --git a/drivers/power/domain/apple-pmgr.c b/drivers/power/domain/apple-pmgr.c index 402c5b1fd18..bf9940621ee 100644 --- a/drivers/power/domain/apple-pmgr.c +++ b/drivers/power/domain/apple-pmgr.c @@ -3,7 +3,6 @@ * Copyright (C) 2021 Mark Kettenis */ -#include #include #include #include diff --git a/drivers/power/domain/bcm6328-power-domain.c b/drivers/power/domain/bcm6328-power-domain.c index 80144dd9772..36b5a933748 100644 --- a/drivers/power/domain/bcm6328-power-domain.c +++ b/drivers/power/domain/bcm6328-power-domain.c @@ -3,7 +3,6 @@ * Copyright (C) 2017 Álvaro Fernández Rojas */ -#include #include #include #include diff --git a/drivers/power/domain/imx8-power-domain-legacy.c b/drivers/power/domain/imx8-power-domain-legacy.c index c8ca2665752..713a51d7807 100644 --- a/drivers/power/domain/imx8-power-domain-legacy.c +++ b/drivers/power/domain/imx8-power-domain-legacy.c @@ -3,7 +3,6 @@ * Copyright 2017 NXP */ -#include #include #include #include diff --git a/drivers/power/domain/imx8-power-domain.c b/drivers/power/domain/imx8-power-domain.c index b45e468756b..e8dcc057fee 100644 --- a/drivers/power/domain/imx8-power-domain.c +++ b/drivers/power/domain/imx8-power-domain.c @@ -4,7 +4,6 @@ */ #define DEBUG -#include #include #include #include diff --git a/drivers/power/domain/imx8m-power-domain.c b/drivers/power/domain/imx8m-power-domain.c index df5d7d69562..8b6870c8646 100644 --- a/drivers/power/domain/imx8m-power-domain.c +++ b/drivers/power/domain/imx8m-power-domain.c @@ -3,7 +3,6 @@ * Copyright 2017 NXP */ -#include #include #include #include diff --git a/drivers/power/domain/imx8mp-hsiomix.c b/drivers/power/domain/imx8mp-hsiomix.c index 6188a04c45e..455ad53ef52 100644 --- a/drivers/power/domain/imx8mp-hsiomix.c +++ b/drivers/power/domain/imx8mp-hsiomix.c @@ -3,7 +3,6 @@ * Copyright (C) 2022 Marek Vasut */ -#include #include #include #include diff --git a/drivers/power/domain/meson-ee-pwrc.c b/drivers/power/domain/meson-ee-pwrc.c index 676fded8080..20e9f32b381 100644 --- a/drivers/power/domain/meson-ee-pwrc.c +++ b/drivers/power/domain/meson-ee-pwrc.c @@ -4,7 +4,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/drivers/power/domain/meson-gx-pwrc-vpu.c b/drivers/power/domain/meson-gx-pwrc-vpu.c index 612660ce89f..1c56e8508c3 100644 --- a/drivers/power/domain/meson-gx-pwrc-vpu.c +++ b/drivers/power/domain/meson-gx-pwrc-vpu.c @@ -6,7 +6,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/drivers/power/domain/mtk-power-domain.c b/drivers/power/domain/mtk-power-domain.c index 3b84147d481..2d1ba1855a5 100644 --- a/drivers/power/domain/mtk-power-domain.c +++ b/drivers/power/domain/mtk-power-domain.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/drivers/power/domain/power-domain-uclass.c b/drivers/power/domain/power-domain-uclass.c index f6286c70c1d..938bd8cbc9f 100644 --- a/drivers/power/domain/power-domain-uclass.c +++ b/drivers/power/domain/power-domain-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_POWER_DOMAIN -#include #include #include #include diff --git a/drivers/power/domain/sandbox-power-domain-test.c b/drivers/power/domain/sandbox-power-domain-test.c index 1bf52f1d861..08c15ef342b 100644 --- a/drivers/power/domain/sandbox-power-domain-test.c +++ b/drivers/power/domain/sandbox-power-domain-test.c @@ -3,7 +3,6 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ -#include #include #include #include diff --git a/drivers/power/domain/sandbox-power-domain.c b/drivers/power/domain/sandbox-power-domain.c index 04a071044f3..9dd490b14a3 100644 --- a/drivers/power/domain/sandbox-power-domain.c +++ b/drivers/power/domain/sandbox-power-domain.c @@ -3,7 +3,6 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ -#include #include #include #include diff --git a/drivers/power/domain/tegra186-power-domain.c b/drivers/power/domain/tegra186-power-domain.c index 46da541b75a..334c460c805 100644 --- a/drivers/power/domain/tegra186-power-domain.c +++ b/drivers/power/domain/tegra186-power-domain.c @@ -3,7 +3,6 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ -#include #include #include #include diff --git a/drivers/power/domain/ti-power-domain.c b/drivers/power/domain/ti-power-domain.c index 8996c40ddc0..b059dd37376 100644 --- a/drivers/power/domain/ti-power-domain.c +++ b/drivers/power/domain/ti-power-domain.c @@ -7,7 +7,6 @@ */ #include -#include #include #include #include diff --git a/drivers/power/domain/ti-sci-power-domain.c b/drivers/power/domain/ti-sci-power-domain.c index 8d6abe13dbc..0a9f498b97b 100644 --- a/drivers/power/domain/ti-sci-power-domain.c +++ b/drivers/power/domain/ti-sci-power-domain.c @@ -8,7 +8,6 @@ * Loosely based on Linux kernel ti_sci_pm_domains.c... */ -#include #include #include #include diff --git a/drivers/power/domain/zynqmp-power-domain.c b/drivers/power/domain/zynqmp-power-domain.c index 5ee9e020fb3..ac93934eb42 100644 --- a/drivers/power/domain/zynqmp-power-domain.c +++ b/drivers/power/domain/zynqmp-power-domain.c @@ -3,7 +3,6 @@ * Copyright (c) 2021, Xilinx. Inc. */ -#include #include #include #include diff --git a/drivers/power/exynos-tmu.c b/drivers/power/exynos-tmu.c index 6d62f6cae40..21c2fabce1b 100644 --- a/drivers/power/exynos-tmu.c +++ b/drivers/power/exynos-tmu.c @@ -17,11 +17,12 @@ * MA 02111-1307 USA */ -#include #include #include #include +#include #include +#include #include #include diff --git a/drivers/power/mt6323.c b/drivers/power/mt6323.c index 354817a0378..dd6cbcf1820 100644 --- a/drivers/power/mt6323.c +++ b/drivers/power/mt6323.c @@ -3,7 +3,6 @@ * Copyright (C) 2019 Frank Wunderlich */ -#include #include #include #include diff --git a/drivers/power/pmic/ab8500.c b/drivers/power/pmic/ab8500.c index 1f64f217c34..9ba096711e1 100644 --- a/drivers/power/pmic/ab8500.c +++ b/drivers/power/pmic/ab8500.c @@ -7,7 +7,6 @@ * Copyright (C) ST-Ericsson SA 2010 */ -#include #include #include #include diff --git a/drivers/power/pmic/act8846.c b/drivers/power/pmic/act8846.c index 8f0f5a6d96e..3058ef0f893 100644 --- a/drivers/power/pmic/act8846.c +++ b/drivers/power/pmic/act8846.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/power/pmic/as3722.c b/drivers/power/pmic/as3722.c index c7dd9705d18..9b0f4fb9736 100644 --- a/drivers/power/pmic/as3722.c +++ b/drivers/power/pmic/as3722.c @@ -5,7 +5,6 @@ #define pr_fmt(fmt) "as3722: " fmt -#include #include #include #include diff --git a/drivers/power/pmic/as3722_gpio.c b/drivers/power/pmic/as3722_gpio.c index 987fbdf9bc0..52d8bd00b1f 100644 --- a/drivers/power/pmic/as3722_gpio.c +++ b/drivers/power/pmic/as3722_gpio.c @@ -3,7 +3,6 @@ * Copyright (C) 2014 NVIDIA Corporation */ -#include #include #include #include diff --git a/drivers/power/pmic/bd71837.c b/drivers/power/pmic/bd71837.c index ee6ae78e5c4..a5df2570fc3 100644 --- a/drivers/power/pmic/bd71837.c +++ b/drivers/power/pmic/bd71837.c @@ -3,7 +3,6 @@ * Copyright 2018 NXP */ -#include #include #include #include diff --git a/drivers/power/pmic/da9063.c b/drivers/power/pmic/da9063.c index ca95b82e6d0..7bd3df39142 100644 --- a/drivers/power/pmic/da9063.c +++ b/drivers/power/pmic/da9063.c @@ -4,7 +4,6 @@ * Martin Fuzzey */ -#include #include #include #include diff --git a/drivers/power/pmic/fan53555.c b/drivers/power/pmic/fan53555.c index d556b9a5878..95bf600cbc3 100644 --- a/drivers/power/pmic/fan53555.c +++ b/drivers/power/pmic/fan53555.c @@ -3,7 +3,6 @@ * (C) 2018 Theobroma Systems Design und Consulting GmbH */ -#include #include #include #include diff --git a/drivers/power/pmic/i2c_pmic_emul.c b/drivers/power/pmic/i2c_pmic_emul.c index f0a03742f87..6e81b9c3427 100644 --- a/drivers/power/pmic/i2c_pmic_emul.c +++ b/drivers/power/pmic/i2c_pmic_emul.c @@ -4,7 +4,6 @@ * Przemyslaw Marczak */ -#include #include #include #include diff --git a/drivers/power/pmic/lp873x.c b/drivers/power/pmic/lp873x.c index fda5bc15164..2c8fa4ea312 100644 --- a/drivers/power/pmic/lp873x.c +++ b/drivers/power/pmic/lp873x.c @@ -4,7 +4,6 @@ * Keerthy */ -#include #include #include #include diff --git a/drivers/power/pmic/lp87565.c b/drivers/power/pmic/lp87565.c index 904e02c4d81..c2ff75bbcdc 100644 --- a/drivers/power/pmic/lp87565.c +++ b/drivers/power/pmic/lp87565.c @@ -4,7 +4,6 @@ * Keerthy */ -#include #include #include #include diff --git a/drivers/power/pmic/max77686.c b/drivers/power/pmic/max77686.c index 7e6f7d1966f..bfe57b386d3 100644 --- a/drivers/power/pmic/max77686.c +++ b/drivers/power/pmic/max77686.c @@ -4,7 +4,6 @@ * Przemyslaw Marczak */ -#include #include #include #include diff --git a/drivers/power/pmic/max8997.c b/drivers/power/pmic/max8997.c index 504a63bf743..4afa6c84ef8 100644 --- a/drivers/power/pmic/max8997.c +++ b/drivers/power/pmic/max8997.c @@ -4,7 +4,6 @@ * Jaehoon Chung */ -#include #include #include #include diff --git a/drivers/power/pmic/max8998.c b/drivers/power/pmic/max8998.c index d155474447f..05669023753 100644 --- a/drivers/power/pmic/max8998.c +++ b/drivers/power/pmic/max8998.c @@ -4,7 +4,6 @@ * Jaehoon Chung */ -#include #include #include #include diff --git a/drivers/power/pmic/mc34708.c b/drivers/power/pmic/mc34708.c index 40d732224b6..43badb5767a 100644 --- a/drivers/power/pmic/mc34708.c +++ b/drivers/power/pmic/mc34708.c @@ -5,7 +5,6 @@ * */ -#include #include #include #include diff --git a/drivers/power/pmic/mp5416.c b/drivers/power/pmic/mp5416.c index 6180adf77e2..9d44f0ae655 100644 --- a/drivers/power/pmic/mp5416.c +++ b/drivers/power/pmic/mp5416.c @@ -2,7 +2,6 @@ /* * Copyright 2020 Gateworks Corporation */ -#include #include #include #include diff --git a/drivers/power/pmic/palmas.c b/drivers/power/pmic/palmas.c index e340a32279f..f676bf64169 100644 --- a/drivers/power/pmic/palmas.c +++ b/drivers/power/pmic/palmas.c @@ -4,7 +4,6 @@ * Keerthy */ -#include #include #include #include diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c index 0bbe98cd8a2..07af6273d8a 100644 --- a/drivers/power/pmic/pca9450.c +++ b/drivers/power/pmic/pca9450.c @@ -3,7 +3,6 @@ * Copyright 2019 NXP */ -#include #include #include #include diff --git a/drivers/power/pmic/pfuze100.c b/drivers/power/pmic/pfuze100.c index 15420acb472..9e09805d251 100644 --- a/drivers/power/pmic/pfuze100.c +++ b/drivers/power/pmic/pfuze100.c @@ -4,7 +4,6 @@ * Peng Fan */ -#include #include #include #include diff --git a/drivers/power/pmic/pmic-uclass.c b/drivers/power/pmic/pmic-uclass.c index 0e2f5e1f411..bb459816d14 100644 --- a/drivers/power/pmic/pmic-uclass.c +++ b/drivers/power/pmic/pmic-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_PMIC -#include #include #include #include diff --git a/drivers/power/pmic/pmic_hi6553.c b/drivers/power/pmic/pmic_hi6553.c index 80b9078cf8f..05305013882 100644 --- a/drivers/power/pmic/pmic_hi6553.c +++ b/drivers/power/pmic/pmic_hi6553.c @@ -4,7 +4,6 @@ * Peter Griffin */ #include -#include #include #include #include diff --git a/drivers/power/pmic/pmic_ltc3676.c b/drivers/power/pmic/pmic_ltc3676.c index af94f37b0f1..145a631b6b2 100644 --- a/drivers/power/pmic/pmic_ltc3676.c +++ b/drivers/power/pmic/pmic_ltc3676.c @@ -4,7 +4,6 @@ * Tim Harvey */ -#include #include #include #include diff --git a/drivers/power/pmic/pmic_mc34vr500.c b/drivers/power/pmic/pmic_mc34vr500.c index 9dd1c46ea22..0dfdfbdf3dc 100644 --- a/drivers/power/pmic/pmic_mc34vr500.c +++ b/drivers/power/pmic/pmic_mc34vr500.c @@ -4,7 +4,6 @@ * Hou Zhiqiang */ -#include #include #include #include diff --git a/drivers/power/pmic/pmic_pca9450.c b/drivers/power/pmic/pmic_pca9450.c index 8c4d0a92306..12500ba9990 100644 --- a/drivers/power/pmic/pmic_pca9450.c +++ b/drivers/power/pmic/pmic_pca9450.c @@ -3,7 +3,6 @@ * Copyright 2019 NXP */ -#include #include #include #include diff --git a/drivers/power/pmic/pmic_pfuze100.c b/drivers/power/pmic/pmic_pfuze100.c index 5115b55e49d..a266709d8d0 100644 --- a/drivers/power/pmic/pmic_pfuze100.c +++ b/drivers/power/pmic/pmic_pfuze100.c @@ -4,7 +4,6 @@ * Tim Harvey */ -#include #include #include #include diff --git a/drivers/power/pmic/pmic_pfuze3000.c b/drivers/power/pmic/pmic_pfuze3000.c index a6d97252bc9..602c4744aa6 100644 --- a/drivers/power/pmic/pmic_pfuze3000.c +++ b/drivers/power/pmic/pmic_pfuze3000.c @@ -4,7 +4,6 @@ * Peng Fan */ -#include #include #include #include diff --git a/drivers/power/pmic/pmic_qcom.c b/drivers/power/pmic/pmic_qcom.c index f2ac6494811..92d0a95859b 100644 --- a/drivers/power/pmic/pmic_qcom.c +++ b/drivers/power/pmic/pmic_qcom.c @@ -4,7 +4,6 @@ * * (C) Copyright 2015 Mateusz Kulikowski */ -#include #include #include #include diff --git a/drivers/power/pmic/pmic_tps62362.c b/drivers/power/pmic/pmic_tps62362.c index 6426d1488a5..4f0e406d560 100644 --- a/drivers/power/pmic/pmic_tps62362.c +++ b/drivers/power/pmic/pmic_tps62362.c @@ -4,7 +4,6 @@ * Author: Felipe Balbi */ -#include #include #include #include diff --git a/drivers/power/pmic/pmic_tps65217.c b/drivers/power/pmic/pmic_tps65217.c index ccbf2235933..bd44e0d9ae0 100644 --- a/drivers/power/pmic/pmic_tps65217.c +++ b/drivers/power/pmic/pmic_tps65217.c @@ -4,7 +4,6 @@ * Texas Instruments, */ -#include #include #include #include diff --git a/drivers/power/pmic/pmic_tps65218.c b/drivers/power/pmic/pmic_tps65218.c index 67174901804..49d07e95cd7 100644 --- a/drivers/power/pmic/pmic_tps65218.c +++ b/drivers/power/pmic/pmic_tps65218.c @@ -4,7 +4,6 @@ * Texas Instruments, */ -#include #include #include #include diff --git a/drivers/power/pmic/pmic_tps65910.c b/drivers/power/pmic/pmic_tps65910.c index e3de7308215..df9bb66a7f9 100644 --- a/drivers/power/pmic/pmic_tps65910.c +++ b/drivers/power/pmic/pmic_tps65910.c @@ -4,7 +4,6 @@ * Texas Instruments, */ -#include #include #include diff --git a/drivers/power/pmic/pmic_tps65910_dm.c b/drivers/power/pmic/pmic_tps65910_dm.c index ecf836eb0e6..de8d805566a 100644 --- a/drivers/power/pmic/pmic_tps65910_dm.c +++ b/drivers/power/pmic/pmic_tps65910_dm.c @@ -3,7 +3,6 @@ * Copyright (C) EETS GmbH, 2017, Felix Brack */ -#include #include #include #include diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c index 3a8261d1749..12ff26a0855 100644 --- a/drivers/power/pmic/rk8xx.c +++ b/drivers/power/pmic/rk8xx.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/power/pmic/rn5t567.c b/drivers/power/pmic/rn5t567.c index 9d103dd8405..0124d84a729 100644 --- a/drivers/power/pmic/rn5t567.c +++ b/drivers/power/pmic/rn5t567.c @@ -4,7 +4,6 @@ * Stefan Agner */ -#include #include #include #include diff --git a/drivers/power/pmic/s2mps11.c b/drivers/power/pmic/s2mps11.c index 5ff4f205211..17780017035 100644 --- a/drivers/power/pmic/s2mps11.c +++ b/drivers/power/pmic/s2mps11.c @@ -4,7 +4,6 @@ * Przemyslaw Marczak */ -#include #include #include #include diff --git a/drivers/power/pmic/s5m8767.c b/drivers/power/pmic/s5m8767.c index eea072ae824..799d0012540 100644 --- a/drivers/power/pmic/s5m8767.c +++ b/drivers/power/pmic/s5m8767.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Google, Inc */ -#include #include #include #include diff --git a/drivers/power/pmic/sandbox.c b/drivers/power/pmic/sandbox.c index 14b82455f5f..ddc11d6df86 100644 --- a/drivers/power/pmic/sandbox.c +++ b/drivers/power/pmic/sandbox.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_PMIC -#include #include #include #include diff --git a/drivers/power/pmic/stpmic1.c b/drivers/power/pmic/stpmic1.c index 8701d4f971c..c99a0c27b33 100644 --- a/drivers/power/pmic/stpmic1.c +++ b/drivers/power/pmic/stpmic1.c @@ -3,7 +3,6 @@ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved */ -#include #include #include #include diff --git a/drivers/power/pmic/tps65090.c b/drivers/power/pmic/tps65090.c index 2a04d5948a5..ad2ab34719e 100644 --- a/drivers/power/pmic/tps65090.c +++ b/drivers/power/pmic/tps65090.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/power/pmic/tps65219.c b/drivers/power/pmic/tps65219.c index 9462afee77f..0716af027a3 100644 --- a/drivers/power/pmic/tps65219.c +++ b/drivers/power/pmic/tps65219.c @@ -4,7 +4,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/drivers/power/pmic/tps65941.c b/drivers/power/pmic/tps65941.c index 943d845086c..c3490db2a08 100644 --- a/drivers/power/pmic/tps65941.c +++ b/drivers/power/pmic/tps65941.c @@ -4,7 +4,6 @@ * Keerthy */ -#include #include #include #include diff --git a/drivers/power/power_core.c b/drivers/power/power_core.c index 4f7ba099cd9..1caf9f09346 100644 --- a/drivers/power/power_core.c +++ b/drivers/power/power_core.c @@ -9,7 +9,6 @@ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/drivers/power/power_dialog.c b/drivers/power/power_dialog.c index ad7aaf35a9a..a5c7ea34c4a 100644 --- a/drivers/power/power_dialog.c +++ b/drivers/power/power_dialog.c @@ -4,7 +4,7 @@ * Lukasz Majewski */ -#include +#include #include #include #include diff --git a/drivers/power/power_fsl.c b/drivers/power/power_fsl.c index 9dc930fb305..a10a14a7961 100644 --- a/drivers/power/power_fsl.c +++ b/drivers/power/power_fsl.c @@ -4,7 +4,7 @@ * Lukasz Majewski */ -#include +#include #include #include #include diff --git a/drivers/power/power_i2c.c b/drivers/power/power_i2c.c index b67ac2f027b..a871fc41987 100644 --- a/drivers/power/power_i2c.c +++ b/drivers/power/power_i2c.c @@ -10,7 +10,6 @@ * (C) Copyright 2019 NXP */ -#include #include #include #include diff --git a/drivers/power/power_spi.c b/drivers/power/power_spi.c index 1eaf9773ef8..54427316ce4 100644 --- a/drivers/power/power_spi.c +++ b/drivers/power/power_spi.c @@ -9,7 +9,6 @@ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/drivers/power/regulator/act8846.c b/drivers/power/regulator/act8846.c index bdce97365dd..d3e72da0d35 100644 --- a/drivers/power/regulator/act8846.c +++ b/drivers/power/regulator/act8846.c @@ -8,7 +8,6 @@ * zyw */ -#include #include #include #include diff --git a/drivers/power/regulator/anatop_regulator.c b/drivers/power/regulator/anatop_regulator.c index 096a1565d5a..824a753db16 100644 --- a/drivers/power/regulator/anatop_regulator.c +++ b/drivers/power/regulator/anatop_regulator.c @@ -4,7 +4,6 @@ * Copyright (C) 2021 Linaro */ -#include #include #include #include diff --git a/drivers/power/regulator/as3722_regulator.c b/drivers/power/regulator/as3722_regulator.c index ec0776b440b..8d60965fe9a 100644 --- a/drivers/power/regulator/as3722_regulator.c +++ b/drivers/power/regulator/as3722_regulator.c @@ -6,7 +6,6 @@ * Placeholder regulator driver for as3722. */ -#include #include #include #include diff --git a/drivers/power/regulator/bd71837.c b/drivers/power/regulator/bd71837.c index 913ed88d45f..59aec1a7313 100644 --- a/drivers/power/regulator/bd71837.c +++ b/drivers/power/regulator/bd71837.c @@ -5,7 +5,6 @@ * ROHM BD71837 regulator driver */ -#include #include #include #include diff --git a/drivers/power/regulator/da9063.c b/drivers/power/regulator/da9063.c index 8df1abcf788..5d566b06a52 100644 --- a/drivers/power/regulator/da9063.c +++ b/drivers/power/regulator/da9063.c @@ -4,7 +4,6 @@ * Martin Fuzzey */ -#include #include #include #include diff --git a/drivers/power/regulator/fan53555.c b/drivers/power/regulator/fan53555.c index fa8d88f2e0d..5cba58f91ca 100644 --- a/drivers/power/regulator/fan53555.c +++ b/drivers/power/regulator/fan53555.c @@ -3,7 +3,6 @@ * (C) 2018 Theobroma Systems Design und Consulting GmbH */ -#include #include #include #include diff --git a/drivers/power/regulator/fixed.c b/drivers/power/regulator/fixed.c index 590c288d657..98c89bf2aff 100644 --- a/drivers/power/regulator/fixed.c +++ b/drivers/power/regulator/fixed.c @@ -5,7 +5,6 @@ * Przemyslaw Marczak */ -#include #include #include #include diff --git a/drivers/power/regulator/gpio-regulator.c b/drivers/power/regulator/gpio-regulator.c index 74137b7b876..38b22535c3d 100644 --- a/drivers/power/regulator/gpio-regulator.c +++ b/drivers/power/regulator/gpio-regulator.c @@ -4,7 +4,6 @@ * Keerthy */ -#include #include #include #include diff --git a/drivers/power/regulator/lp873x_regulator.c b/drivers/power/regulator/lp873x_regulator.c index c326f8efa47..c59d77118ad 100644 --- a/drivers/power/regulator/lp873x_regulator.c +++ b/drivers/power/regulator/lp873x_regulator.c @@ -6,7 +6,6 @@ * Keerthy */ -#include #include #include #include diff --git a/drivers/power/regulator/lp87565_regulator.c b/drivers/power/regulator/lp87565_regulator.c index 6bbc831d2c8..d622d956815 100644 --- a/drivers/power/regulator/lp87565_regulator.c +++ b/drivers/power/regulator/lp87565_regulator.c @@ -6,7 +6,6 @@ * Keerthy */ -#include #include #include #include diff --git a/drivers/power/regulator/max77686.c b/drivers/power/regulator/max77686.c index 3a208039934..4e0ba12a0ef 100644 --- a/drivers/power/regulator/max77686.c +++ b/drivers/power/regulator/max77686.c @@ -6,7 +6,6 @@ * Przemyslaw Marczak */ -#include #include #include #include diff --git a/drivers/power/regulator/npcm8xx_regulator.c b/drivers/power/regulator/npcm8xx_regulator.c index fcd1058cdf5..30d1b8945cb 100644 --- a/drivers/power/regulator/npcm8xx_regulator.c +++ b/drivers/power/regulator/npcm8xx_regulator.c @@ -3,7 +3,6 @@ * Copyright (c) 2022 Nuvoton Technology Corp. */ -#include #include #include #include diff --git a/drivers/power/regulator/palmas_regulator.c b/drivers/power/regulator/palmas_regulator.c index d615e947340..2286eac93fb 100644 --- a/drivers/power/regulator/palmas_regulator.c +++ b/drivers/power/regulator/palmas_regulator.c @@ -6,7 +6,6 @@ * Keerthy */ -#include #include #include #include diff --git a/drivers/power/regulator/pbias_regulator.c b/drivers/power/regulator/pbias_regulator.c index cf4e2858443..8f599cab689 100644 --- a/drivers/power/regulator/pbias_regulator.c +++ b/drivers/power/regulator/pbias_regulator.c @@ -4,7 +4,6 @@ * Jean-Jacques Hiblot */ -#include #include #include #include diff --git a/drivers/power/regulator/pca9450.c b/drivers/power/regulator/pca9450.c index 7ca20d1f7f8..9faf1eab5f9 100644 --- a/drivers/power/regulator/pca9450.c +++ b/drivers/power/regulator/pca9450.c @@ -7,7 +7,6 @@ * ROHM BD71837 regulator driver */ -#include #include #include #include diff --git a/drivers/power/regulator/pfuze100.c b/drivers/power/regulator/pfuze100.c index 1d926689b3b..bf3a7019411 100644 --- a/drivers/power/regulator/pfuze100.c +++ b/drivers/power/regulator/pfuze100.c @@ -5,7 +5,6 @@ * Peng Fan */ -#include #include #include #include diff --git a/drivers/power/regulator/pwm_regulator.c b/drivers/power/regulator/pwm_regulator.c index ca59f3ae3e1..ff738faadc5 100644 --- a/drivers/power/regulator/pwm_regulator.c +++ b/drivers/power/regulator/pwm_regulator.c @@ -7,7 +7,6 @@ * Author: Lee Jones */ -#include #include #include #include diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 77d101f262e..66fd531da04 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_REGULATOR -#include #include #include #include diff --git a/drivers/power/regulator/regulator_common.c b/drivers/power/regulator/regulator_common.c index 0116fa01bbf..e3565d32a01 100644 --- a/drivers/power/regulator/regulator_common.c +++ b/drivers/power/regulator/regulator_common.c @@ -4,7 +4,6 @@ * Sven Schwermer */ -#include #include #include #include diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c index 1bd4605d43a..bf3af781527 100644 --- a/drivers/power/regulator/rk8xx.c +++ b/drivers/power/regulator/rk8xx.c @@ -8,7 +8,6 @@ * zyw */ -#include #include #include #include diff --git a/drivers/power/regulator/s2mps11_regulator.c b/drivers/power/regulator/s2mps11_regulator.c index 987a1f9d863..96de55065fe 100644 --- a/drivers/power/regulator/s2mps11_regulator.c +++ b/drivers/power/regulator/s2mps11_regulator.c @@ -4,7 +4,6 @@ * Jaehoon Chung */ -#include #include #include #include diff --git a/drivers/power/regulator/s5m8767.c b/drivers/power/regulator/s5m8767.c index 23575831f38..0dcf0990802 100644 --- a/drivers/power/regulator/s5m8767.c +++ b/drivers/power/regulator/s5m8767.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Google, Inc */ -#include #include #include #include diff --git a/drivers/power/regulator/sandbox.c b/drivers/power/regulator/sandbox.c index 71ef0c5441a..80a68f5a30d 100644 --- a/drivers/power/regulator/sandbox.c +++ b/drivers/power/regulator/sandbox.c @@ -4,7 +4,6 @@ * Przemyslaw Marczak */ -#include #include #include #include diff --git a/drivers/power/regulator/scmi_regulator.c b/drivers/power/regulator/scmi_regulator.c index 9c72c35d039..99f6506f162 100644 --- a/drivers/power/regulator/scmi_regulator.c +++ b/drivers/power/regulator/scmi_regulator.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_REGULATOR -#include #include #include #include diff --git a/drivers/power/regulator/stm32-vrefbuf.c b/drivers/power/regulator/stm32-vrefbuf.c index c37998a4bac..dd8a33f15be 100644 --- a/drivers/power/regulator/stm32-vrefbuf.c +++ b/drivers/power/regulator/stm32-vrefbuf.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_REGULATOR -#include #include #include #include diff --git a/drivers/power/regulator/stpmic1.c b/drivers/power/regulator/stpmic1.c index 4839d834316..b5ffa1cd589 100644 --- a/drivers/power/regulator/stpmic1.c +++ b/drivers/power/regulator/stpmic1.c @@ -4,7 +4,6 @@ * Author: Christophe Kerello */ -#include #include #include #include diff --git a/drivers/power/regulator/tps62360_regulator.c b/drivers/power/regulator/tps62360_regulator.c index 7014b1982d0..9acc6b90549 100644 --- a/drivers/power/regulator/tps62360_regulator.c +++ b/drivers/power/regulator/tps62360_regulator.c @@ -4,7 +4,6 @@ * Tero Kristo */ -#include #include #include #include diff --git a/drivers/power/regulator/tps65090_regulator.c b/drivers/power/regulator/tps65090_regulator.c index fa15e61a10e..2d414de1490 100644 --- a/drivers/power/regulator/tps65090_regulator.c +++ b/drivers/power/regulator/tps65090_regulator.c @@ -3,10 +3,10 @@ * Copyright (c) 2015 Google, Inc */ -#include #include #include #include +#include #include #include #include diff --git a/drivers/power/regulator/tps65219_regulator.c b/drivers/power/regulator/tps65219_regulator.c index f87d07e61fb..b7124fed024 100644 --- a/drivers/power/regulator/tps65219_regulator.c +++ b/drivers/power/regulator/tps65219_regulator.c @@ -5,7 +5,6 @@ * */ -#include #include #include #include diff --git a/drivers/power/regulator/tps65910_regulator.c b/drivers/power/regulator/tps65910_regulator.c index a4b9d449274..562fd7db190 100644 --- a/drivers/power/regulator/tps65910_regulator.c +++ b/drivers/power/regulator/tps65910_regulator.c @@ -3,7 +3,6 @@ * Copyright (C) EETS GmbH, 2017, Felix Brack */ -#include #include #include #include diff --git a/drivers/power/regulator/tps65941_regulator.c b/drivers/power/regulator/tps65941_regulator.c index 5809a53fa21..bc4d153fd84 100644 --- a/drivers/power/regulator/tps65941_regulator.c +++ b/drivers/power/regulator/tps65941_regulator.c @@ -6,7 +6,6 @@ * Keerthy */ -#include #include #include #include diff --git a/drivers/power/sy8106a.c b/drivers/power/sy8106a.c index 45f47939869..fb6028de71a 100644 --- a/drivers/power/sy8106a.c +++ b/drivers/power/sy8106a.c @@ -3,7 +3,6 @@ * (C) Copyright 2016 * Jelle van der Waa */ -#include #include #include diff --git a/drivers/power/tps6586x.c b/drivers/power/tps6586x.c index 37f1c459a63..4034a9b49dd 100644 --- a/drivers/power/tps6586x.c +++ b/drivers/power/tps6586x.c @@ -4,12 +4,12 @@ * (C) Copyright 2010,2011 NVIDIA Corporation */ -#include #include #include #include #include #include +#include static struct udevice *tps6586x_dev; diff --git a/drivers/pwm/cros_ec_pwm.c b/drivers/pwm/cros_ec_pwm.c index 4a39c319aa2..b89f00f151b 100644 --- a/drivers/pwm/cros_ec_pwm.c +++ b/drivers/pwm/cros_ec_pwm.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/drivers/pwm/exynos_pwm.c b/drivers/pwm/exynos_pwm.c index 609025d680d..5ded60978f4 100644 --- a/drivers/pwm/exynos_pwm.c +++ b/drivers/pwm/exynos_pwm.c @@ -3,7 +3,6 @@ * Copyright 2016 Google Inc. */ -#include #include #include #include diff --git a/drivers/pwm/pwm-aspeed.c b/drivers/pwm/pwm-aspeed.c index b03472d2345..ebc9d9a8975 100644 --- a/drivers/pwm/pwm-aspeed.c +++ b/drivers/pwm/pwm-aspeed.c @@ -38,7 +38,6 @@ * This improvement can disable/enable through PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE. */ -#include #include #include #include diff --git a/drivers/pwm/pwm-at91.c b/drivers/pwm/pwm-at91.c index 3ff1fb6d5c3..ffc37180eb4 100644 --- a/drivers/pwm/pwm-at91.c +++ b/drivers/pwm/pwm-at91.c @@ -9,7 +9,6 @@ * Based on drivers/pwm/pwm-atmel.c from Linux. */ #include -#include #include #include #include diff --git a/drivers/pwm/pwm-cadence-ttc.c b/drivers/pwm/pwm-cadence-ttc.c index d9f6736a7ae..767628833bc 100644 --- a/drivers/pwm/pwm-cadence-ttc.c +++ b/drivers/pwm/pwm-cadence-ttc.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_PWM #include -#include #include #include #include diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c index 8fbb40cc276..320ea7c4239 100644 --- a/drivers/pwm/pwm-imx.c +++ b/drivers/pwm/pwm-imx.c @@ -6,7 +6,6 @@ * Basic support for the pwm module on imx6. */ -#include #include #include #include diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 60959720dac..c2597d8b669 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -16,7 +16,6 @@ * current period to complete first). */ -#include #include #include #include diff --git a/drivers/pwm/pwm-mtk.c b/drivers/pwm/pwm-mtk.c index ad845ed9662..9776a41ff48 100644 --- a/drivers/pwm/pwm-mtk.c +++ b/drivers/pwm/pwm-mtk.c @@ -5,7 +5,6 @@ * Author: Sam Shih */ -#include #include #include #include diff --git a/drivers/pwm/pwm-sifive.c b/drivers/pwm/pwm-sifive.c index b9813a3b6bb..e9777c71f5e 100644 --- a/drivers/pwm/pwm-sifive.c +++ b/drivers/pwm/pwm-sifive.c @@ -12,7 +12,6 @@ * - The hardware generates only inverted output. */ -#include #include #include #include diff --git a/drivers/pwm/pwm-ti-ehrpwm.c b/drivers/pwm/pwm-ti-ehrpwm.c index fefa3c65ec4..563109ef0f8 100644 --- a/drivers/pwm/pwm-ti-ehrpwm.c +++ b/drivers/pwm/pwm-ti-ehrpwm.c @@ -7,7 +7,6 @@ * Based on Linux kernel drivers/pwm/pwm-tiehrpwm.c */ -#include #include #include #include diff --git a/drivers/pwm/pwm-uclass.c b/drivers/pwm/pwm-uclass.c index 648d0757ba6..6543db1d623 100644 --- a/drivers/pwm/pwm-uclass.c +++ b/drivers/pwm/pwm-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_PWM -#include #include #include diff --git a/drivers/pwm/rk_pwm.c b/drivers/pwm/rk_pwm.c index 1858d597338..0a64eb01dc2 100644 --- a/drivers/pwm/rk_pwm.c +++ b/drivers/pwm/rk_pwm.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/pwm/sandbox_pwm.c b/drivers/pwm/sandbox_pwm.c index 4df15f0a2e8..0d798609dda 100644 --- a/drivers/pwm/sandbox_pwm.c +++ b/drivers/pwm/sandbox_pwm.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/pwm/sunxi_pwm.c b/drivers/pwm/sunxi_pwm.c index bb1bec05ec3..2140a05b679 100644 --- a/drivers/pwm/sunxi_pwm.c +++ b/drivers/pwm/sunxi_pwm.c @@ -3,7 +3,6 @@ * Copyright (c) 2017-2018 Vasily Khoruzhick */ -#include #include #include #include diff --git a/drivers/pwm/tegra_pwm.c b/drivers/pwm/tegra_pwm.c index 87034706060..e3f1417f2ad 100644 --- a/drivers/pwm/tegra_pwm.c +++ b/drivers/pwm/tegra_pwm.c @@ -3,7 +3,6 @@ * Copyright 2016 Google Inc. */ -#include #include #include #include diff --git a/drivers/ram/aspeed/sdram_ast2500.c b/drivers/ram/aspeed/sdram_ast2500.c index dc466a88e71..0d6ab79f96f 100644 --- a/drivers/ram/aspeed/sdram_ast2500.c +++ b/drivers/ram/aspeed/sdram_ast2500.c @@ -5,7 +5,7 @@ * Copyright 2016 Google, Inc */ -#include +#include #include #include #include diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c index d463933363e..55e80fba3dc 100644 --- a/drivers/ram/aspeed/sdram_ast2600.c +++ b/drivers/ram/aspeed/sdram_ast2600.c @@ -2,7 +2,7 @@ /* * Copyright (C) ASPEED Technology Inc. */ -#include +#include #include #include #include diff --git a/drivers/ram/bmips_ram.c b/drivers/ram/bmips_ram.c index 98045248ecf..760bebdbba0 100644 --- a/drivers/ram/bmips_ram.c +++ b/drivers/ram/bmips_ram.c @@ -7,7 +7,6 @@ * Copyright (C) 2009 Florian Fainelli */ -#include #include #include #include diff --git a/drivers/ram/cadence/ddr_ctrl.c b/drivers/ram/cadence/ddr_ctrl.c index 3e5959a84a3..0fa60e766a7 100644 --- a/drivers/ram/cadence/ddr_ctrl.c +++ b/drivers/ram/cadence/ddr_ctrl.c @@ -24,7 +24,6 @@ * bandwidth allocated to each AXI slave can be set. */ -#include #include #include #include diff --git a/drivers/ram/imxrt_sdram.c b/drivers/ram/imxrt_sdram.c index 6a15242c20c..3df106c9b79 100644 --- a/drivers/ram/imxrt_sdram.c +++ b/drivers/ram/imxrt_sdram.c @@ -4,7 +4,6 @@ * Author(s): Giulio Benetti */ -#include #include #include #include diff --git a/drivers/ram/k3-am654-ddrss.c b/drivers/ram/k3-am654-ddrss.c index cff8ffc8929..21ff9d761e1 100644 --- a/drivers/ram/k3-am654-ddrss.c +++ b/drivers/ram/k3-am654-ddrss.c @@ -6,7 +6,6 @@ * Lokesh Vutla */ -#include #include #include #include diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index a5c9b82cf1d..525b6d5b79f 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -5,7 +5,6 @@ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ */ -#include #include #include #include diff --git a/drivers/ram/mediatek/ddr3-mt7629.c b/drivers/ram/mediatek/ddr3-mt7629.c index f65fcf179cf..c27c4593b9d 100644 --- a/drivers/ram/mediatek/ddr3-mt7629.c +++ b/drivers/ram/mediatek/ddr3-mt7629.c @@ -8,7 +8,7 @@ */ #include -#include +#include #include #include #include diff --git a/drivers/ram/mpc83xx_sdram.c b/drivers/ram/mpc83xx_sdram.c index 11676d4fae7..28a663289a2 100644 --- a/drivers/ram/mpc83xx_sdram.c +++ b/drivers/ram/mpc83xx_sdram.c @@ -4,7 +4,6 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ -#include #include #include #include diff --git a/drivers/ram/ram-uclass.c b/drivers/ram/ram-uclass.c index 4e21240fd4c..a33d583cc44 100644 --- a/drivers/ram/ram-uclass.c +++ b/drivers/ram/ram-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_RAM -#include #include #include #include diff --git a/drivers/ram/renesas/rzn1/ddr_async.c b/drivers/ram/renesas/rzn1/ddr_async.c index 7a81497bc92..4d470aae191 100644 --- a/drivers/ram/renesas/rzn1/ddr_async.c +++ b/drivers/ram/renesas/rzn1/ddr_async.c @@ -7,7 +7,6 @@ * * Copyright (C) 2015 Renesas Electronics Europe Ltd */ -#include #include #include #include diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c index 5279bf0a154..42114a5aa91 100644 --- a/drivers/ram/rockchip/dmc-rk3368.c +++ b/drivers/ram/rockchip/dmc-rk3368.c @@ -3,7 +3,7 @@ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH */ -#include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_common.c b/drivers/ram/rockchip/sdram_common.c index 60fc90d0a5c..b7a8fce607c 100644 --- a/drivers/ram/rockchip/sdram_common.c +++ b/drivers/ram/rockchip/sdram_common.c @@ -3,7 +3,7 @@ * (C) Copyright 2018 Rockchip Electronics Co., Ltd. */ -#include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_pctl_px30.c b/drivers/ram/rockchip/sdram_pctl_px30.c index e5c80fb83b3..3ec98af536e 100644 --- a/drivers/ram/rockchip/sdram_pctl_px30.c +++ b/drivers/ram/rockchip/sdram_pctl_px30.c @@ -3,7 +3,6 @@ * (C) Copyright 2018 Rockchip Electronics Co., Ltd. */ -#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_phy_px30.c b/drivers/ram/rockchip/sdram_phy_px30.c index f7f6de1ba98..5416eef3878 100644 --- a/drivers/ram/rockchip/sdram_phy_px30.c +++ b/drivers/ram/rockchip/sdram_phy_px30.c @@ -3,7 +3,6 @@ * (C) Copyright 2018 Rockchip Electronics Co., Ltd. */ -#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_px30.c b/drivers/ram/rockchip/sdram_px30.c index 21498e89570..37e62120504 100644 --- a/drivers/ram/rockchip/sdram_px30.c +++ b/drivers/ram/rockchip/sdram_px30.c @@ -3,7 +3,7 @@ * (C) Copyright 2018 Rockchip Electronics Co., Ltd. */ -#include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3066.c b/drivers/ram/rockchip/sdram_rk3066.c index 562cf544c90..a280e2d9fa1 100644 --- a/drivers/ram/rockchip/sdram_rk3066.c +++ b/drivers/ram/rockchip/sdram_rk3066.c @@ -6,7 +6,7 @@ * Adapted from the very similar rk3188 ddr init. */ -#include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3128.c b/drivers/ram/rockchip/sdram_rk3128.c index ded65393806..66611f80b2d 100644 --- a/drivers/ram/rockchip/sdram_rk3128.c +++ b/drivers/ram/rockchip/sdram_rk3128.c @@ -3,7 +3,7 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd. */ -#include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3188.c b/drivers/ram/rockchip/sdram_rk3188.c index e1b28c6e593..618bce5c9f4 100644 --- a/drivers/ram/rockchip/sdram_rk3188.c +++ b/drivers/ram/rockchip/sdram_rk3188.c @@ -6,7 +6,7 @@ * Adapted from the very similar rk3288 ddr init. */ -#include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk322x.c b/drivers/ram/rockchip/sdram_rk322x.c index 5fc23c11193..a48a5091184 100644 --- a/drivers/ram/rockchip/sdram_rk322x.c +++ b/drivers/ram/rockchip/sdram_rk322x.c @@ -2,7 +2,7 @@ /* * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ -#include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c index 242d564a7d2..c9f61e933e9 100644 --- a/drivers/ram/rockchip/sdram_rk3288.c +++ b/drivers/ram/rockchip/sdram_rk3288.c @@ -6,7 +6,7 @@ * Adapted from coreboot. */ -#include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3308.c b/drivers/ram/rockchip/sdram_rk3308.c index 264366291cf..8071997f8d8 100644 --- a/drivers/ram/rockchip/sdram_rk3308.c +++ b/drivers/ram/rockchip/sdram_rk3308.c @@ -3,7 +3,7 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd. */ -#include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c index b5ca8ca436f..99690d67a50 100644 --- a/drivers/ram/rockchip/sdram_rk3328.c +++ b/drivers/ram/rockchip/sdram_rk3328.c @@ -2,7 +2,7 @@ /* * (C) Copyright 2017 Rockchip Electronics Co., Ltd. */ -#include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 02cc4a38cf0..ef9a1824b2b 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -5,7 +5,7 @@ * Adapted from coreboot. */ -#include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3568.c b/drivers/ram/rockchip/sdram_rk3568.c index f661615c1b9..a252d5c7010 100644 --- a/drivers/ram/rockchip/sdram_rk3568.c +++ b/drivers/ram/rockchip/sdram_rk3568.c @@ -3,7 +3,7 @@ * (C) Copyright 2021 Rockchip Electronics Co., Ltd. */ -#include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3588.c b/drivers/ram/rockchip/sdram_rk3588.c index cf56e2a9412..a144b432d76 100644 --- a/drivers/ram/rockchip/sdram_rk3588.c +++ b/drivers/ram/rockchip/sdram_rk3588.c @@ -3,7 +3,7 @@ * (C) Copyright 2021 Rockchip Electronics Co., Ltd. */ -#include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rv1126.c b/drivers/ram/rockchip/sdram_rv1126.c index 849e15a9193..4fbb088a8d9 100644 --- a/drivers/ram/rockchip/sdram_rv1126.c +++ b/drivers/ram/rockchip/sdram_rv1126.c @@ -4,7 +4,7 @@ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. */ -#include +#include #include #include #include diff --git a/drivers/ram/sandbox_ram.c b/drivers/ram/sandbox_ram.c index 910dce623e9..2097da56532 100644 --- a/drivers/ram/sandbox_ram.c +++ b/drivers/ram/sandbox_ram.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/ram/sifive/sifive_ddr.c b/drivers/ram/sifive/sifive_ddr.c index 4bd69a62be2..bd2f438d727 100644 --- a/drivers/ram/sifive/sifive_ddr.c +++ b/drivers/ram/sifive/sifive_ddr.c @@ -6,7 +6,6 @@ * Pragnesh Patel */ -#include #include #include #include diff --git a/drivers/ram/starfive/ddrcsr_boot.c b/drivers/ram/starfive/ddrcsr_boot.c index f2dd55f74a0..6764b3ed5cc 100644 --- a/drivers/ram/starfive/ddrcsr_boot.c +++ b/drivers/ram/starfive/ddrcsr_boot.c @@ -4,7 +4,6 @@ * Author: Yanhong Wang */ -#include #include #include #include diff --git a/drivers/ram/starfive/ddrphy_start.c b/drivers/ram/starfive/ddrphy_start.c index 479b6ef1041..efe3f8a181a 100644 --- a/drivers/ram/starfive/ddrphy_start.c +++ b/drivers/ram/starfive/ddrphy_start.c @@ -4,7 +4,6 @@ * Author: Yanhong Wang */ -#include #include #include "starfive_ddr.h" diff --git a/drivers/ram/starfive/ddrphy_train.c b/drivers/ram/starfive/ddrphy_train.c index 0740f49be5b..0aff1e8727e 100644 --- a/drivers/ram/starfive/ddrphy_train.c +++ b/drivers/ram/starfive/ddrphy_train.c @@ -4,7 +4,7 @@ * Author: Yanhong Wang */ -#include +#include #include static const u32 ddr_train_data[] = { diff --git a/drivers/ram/starfive/ddrphy_utils.c b/drivers/ram/starfive/ddrphy_utils.c index 1c9fe0a7846..d6dd6ee7a85 100644 --- a/drivers/ram/starfive/ddrphy_utils.c +++ b/drivers/ram/starfive/ddrphy_utils.c @@ -4,7 +4,7 @@ * Author: Yanhong Wang */ -#include +#include #include static const u32 ddr_phy_data[] = { diff --git a/drivers/ram/starfive/starfive_ddr.c b/drivers/ram/starfive/starfive_ddr.c index a0a3d6b33dc..b31ed3bcf61 100644 --- a/drivers/ram/starfive/starfive_ddr.c +++ b/drivers/ram/starfive/starfive_ddr.c @@ -4,7 +4,6 @@ * Author: Yanhong Wang */ -#include #include #include #include diff --git a/drivers/ram/starfive/starfive_ddr.h b/drivers/ram/starfive/starfive_ddr.h index d0ec1c1da80..c29d26b510c 100644 --- a/drivers/ram/starfive/starfive_ddr.h +++ b/drivers/ram/starfive/starfive_ddr.h @@ -7,6 +7,8 @@ #ifndef __STARFIVE_DDR_H__ #define __STARFIVE_DDR_H__ +#include + #define SEC_CTRL_ADDR 0x1000 #define PHY_BASE_ADDR 0x800 #define PHY_AC_BASE_ADDR 0x1000 diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c index 891f4137813..10dc05dd640 100644 --- a/drivers/ram/stm32_sdram.c +++ b/drivers/ram/stm32_sdram.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_RAM -#include #include #include #include diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c index 8ee4e24f39d..d7834b32299 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ddr.c +++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_RAM -#include #include #include #include diff --git a/drivers/ram/stm32mp1/stm32mp1_interactive.c b/drivers/ram/stm32mp1/stm32mp1_interactive.c index 2c19847c663..6340afbb870 100644 --- a/drivers/ram/stm32mp1/stm32mp1_interactive.c +++ b/drivers/ram/stm32mp1/stm32mp1_interactive.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_RAM -#include #include #include #include diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c index a82b1db7592..debc458c0e2 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ram.c +++ b/drivers/ram/stm32mp1/stm32mp1_ram.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_RAM -#include #include #include #include diff --git a/drivers/ram/stm32mp1/stm32mp1_tests.c b/drivers/ram/stm32mp1/stm32mp1_tests.c index c5f33544144..6108faa7073 100644 --- a/drivers/ram/stm32mp1/stm32mp1_tests.c +++ b/drivers/ram/stm32mp1/stm32mp1_tests.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_RAM -#include #include #include #include diff --git a/drivers/ram/sunxi/dram_sun20i_d1.c b/drivers/ram/sunxi/dram_sun20i_d1.c index 38379281d73..a1794032f3b 100644 --- a/drivers/ram/sunxi/dram_sun20i_d1.c +++ b/drivers/ram/sunxi/dram_sun20i_d1.c @@ -13,7 +13,7 @@ */ #include -#include +#include #ifdef CONFIG_RAM #include #include diff --git a/drivers/reboot-mode/reboot-mode-gpio.c b/drivers/reboot-mode/reboot-mode-gpio.c index 305174736ed..22ee40c3433 100644 --- a/drivers/reboot-mode/reboot-mode-gpio.c +++ b/drivers/reboot-mode/reboot-mode-gpio.c @@ -3,7 +3,6 @@ * Copyright (c), Vaisala Oyj */ -#include #include #include #include diff --git a/drivers/reboot-mode/reboot-mode-nvmem.c b/drivers/reboot-mode/reboot-mode-nvmem.c index da41ca41d9a..b9af242520a 100644 --- a/drivers/reboot-mode/reboot-mode-nvmem.c +++ b/drivers/reboot-mode/reboot-mode-nvmem.c @@ -3,7 +3,6 @@ * Copyright (C) 2022 Sean Anderson */ -#include #include #include #include diff --git a/drivers/reboot-mode/reboot-mode-rtc.c b/drivers/reboot-mode/reboot-mode-rtc.c index 972d0cdbcb5..4f4ad63febc 100644 --- a/drivers/reboot-mode/reboot-mode-rtc.c +++ b/drivers/reboot-mode/reboot-mode-rtc.c @@ -3,7 +3,6 @@ * Copyright (c), Vaisala Oyj */ -#include #include #include #include diff --git a/drivers/reboot-mode/reboot-mode-uclass.c b/drivers/reboot-mode/reboot-mode-uclass.c index 2b38aa26b85..7cbe02eb4ed 100644 --- a/drivers/reboot-mode/reboot-mode-uclass.c +++ b/drivers/reboot-mode/reboot-mode-uclass.c @@ -3,7 +3,6 @@ * Copyright (c), Vaisala Oyj */ -#include #include #include #include diff --git a/drivers/remoteproc/ipu_rproc.c b/drivers/remoteproc/ipu_rproc.c index 996e658e871..2ca78b550a7 100644 --- a/drivers/remoteproc/ipu_rproc.c +++ b/drivers/remoteproc/ipu_rproc.c @@ -8,7 +8,6 @@ * Keerthy */ -#include #include #include #include diff --git a/drivers/remoteproc/k3_system_controller.c b/drivers/remoteproc/k3_system_controller.c index 071de40fbd6..71238a6058a 100644 --- a/drivers/remoteproc/k3_system_controller.c +++ b/drivers/remoteproc/k3_system_controller.c @@ -6,7 +6,6 @@ * Lokesh Vutla */ -#include #include #include #include diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c index 6ec55e27d9d..9aec138637b 100644 --- a/drivers/remoteproc/pru_rproc.c +++ b/drivers/remoteproc/pru_rproc.c @@ -6,7 +6,6 @@ * Keerthy */ -#include #include #include #include @@ -399,10 +398,12 @@ static void pru_set_id(struct pru_privdata *priv, struct udevice *dev) { u32 mask2 = 0x38000; - if (device_is_compatible(dev, "ti,am654-rtu")) + if (device_is_compatible(dev, "ti,am654-rtu") || + device_is_compatible(dev, "ti,am642-rtu")) mask2 = 0x6000; - if (device_is_compatible(dev, "ti,am654-tx-pru")) + if (device_is_compatible(dev, "ti,am654-tx-pru") || + device_is_compatible(dev, "ti,am642-tx-pru")) mask2 = 0xc000; if ((priv->pru_iram & mask2) == mask2) @@ -448,6 +449,9 @@ static const struct udevice_id pru_ids[] = { { .compatible = "ti,am654-pru"}, { .compatible = "ti,am654-rtu"}, { .compatible = "ti,am654-tx-pru" }, + { .compatible = "ti,am642-pru"}, + { .compatible = "ti,am642-rtu"}, + { .compatible = "ti,am642-tx-pru" }, {} }; diff --git a/drivers/remoteproc/rproc-elf-loader.c b/drivers/remoteproc/rproc-elf-loader.c index 5e070e5076e..ab1836b3f07 100644 --- a/drivers/remoteproc/rproc-elf-loader.c +++ b/drivers/remoteproc/rproc-elf-loader.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2019, STMicroelectronics - All Rights Reserved */ -#include #include #include #include diff --git a/drivers/remoteproc/rproc-uclass.c b/drivers/remoteproc/rproc-uclass.c index aa7f7586a81..3ba2b40dca3 100644 --- a/drivers/remoteproc/rproc-uclass.c +++ b/drivers/remoteproc/rproc-uclass.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY UCLASS_REMOTEPROC #define pr_fmt(fmt) "%s: " fmt, __func__ -#include #include #include #include diff --git a/drivers/remoteproc/sandbox_testproc.c b/drivers/remoteproc/sandbox_testproc.c index f76f68ebeb4..ad575a7c10f 100644 --- a/drivers/remoteproc/sandbox_testproc.c +++ b/drivers/remoteproc/sandbox_testproc.c @@ -4,7 +4,6 @@ * Texas Instruments Incorporated - https://www.ti.com/ */ #define pr_fmt(fmt) "%s: " fmt, __func__ -#include #include #include #include diff --git a/drivers/remoteproc/stm32_copro.c b/drivers/remoteproc/stm32_copro.c index 3e322c4d719..f45da9a68ac 100644 --- a/drivers/remoteproc/stm32_copro.c +++ b/drivers/remoteproc/stm32_copro.c @@ -4,7 +4,6 @@ */ #define LOG_CATEGORY UCLASS_REMOTEPROC -#include #include #include #include diff --git a/drivers/remoteproc/ti_k3_arm64_rproc.c b/drivers/remoteproc/ti_k3_arm64_rproc.c index 767493c1383..d3eb957b2e4 100644 --- a/drivers/remoteproc/ti_k3_arm64_rproc.c +++ b/drivers/remoteproc/ti_k3_arm64_rproc.c @@ -7,7 +7,6 @@ * */ -#include #include #include #include diff --git a/drivers/remoteproc/ti_k3_dsp_rproc.c b/drivers/remoteproc/ti_k3_dsp_rproc.c index ed13729c33a..076b6f2acdb 100644 --- a/drivers/remoteproc/ti_k3_dsp_rproc.c +++ b/drivers/remoteproc/ti_k3_dsp_rproc.c @@ -7,7 +7,6 @@ * Suman Anna */ -#include #include #include #include diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c index 35835b2d61c..74bf0433e12 100644 --- a/drivers/remoteproc/ti_k3_r5f_rproc.c +++ b/drivers/remoteproc/ti_k3_r5f_rproc.c @@ -7,7 +7,6 @@ * Suman Anna */ -#include #include #include #include diff --git a/drivers/remoteproc/ti_power_proc.c b/drivers/remoteproc/ti_power_proc.c index f55df4a9119..cf150af4ef9 100644 --- a/drivers/remoteproc/ti_power_proc.c +++ b/drivers/remoteproc/ti_power_proc.c @@ -4,7 +4,6 @@ * Texas Instruments Incorporated - https://www.ti.com/ */ #define pr_fmt(fmt) "%s: " fmt, __func__ -#include #include #include #include diff --git a/drivers/reset/reset-ast2500.c b/drivers/reset/reset-ast2500.c index d9cecf3a72e..0ed5396b3e9 100644 --- a/drivers/reset/reset-ast2500.c +++ b/drivers/reset/reset-ast2500.c @@ -4,7 +4,6 @@ * Copyright 2020 ASPEED Technology Inc. */ -#include #include #include #include diff --git a/drivers/reset/reset-ast2600.c b/drivers/reset/reset-ast2600.c index 1732a450efc..ec7b9b6625d 100644 --- a/drivers/reset/reset-ast2600.c +++ b/drivers/reset/reset-ast2600.c @@ -3,7 +3,6 @@ * Copyright 2020 ASPEED Technology Inc. */ -#include #include #include #include diff --git a/drivers/reset/reset-bcm6345.c b/drivers/reset/reset-bcm6345.c index 5383f59ca37..6f140574216 100644 --- a/drivers/reset/reset-bcm6345.c +++ b/drivers/reset/reset-bcm6345.c @@ -6,7 +6,6 @@ * Copyright (C) 2012 Jonas Gorski */ -#include #include #include #include diff --git a/drivers/reset/reset-dra7.c b/drivers/reset/reset-dra7.c index 05101a94f9b..2f0ec4c042f 100644 --- a/drivers/reset/reset-dra7.c +++ b/drivers/reset/reset-dra7.c @@ -7,7 +7,6 @@ */ #include -#include #include #include #include diff --git a/drivers/reset/reset-hisilicon.c b/drivers/reset/reset-hisilicon.c index 85e02b296b0..aca54cd6701 100644 --- a/drivers/reset/reset-hisilicon.c +++ b/drivers/reset/reset-hisilicon.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/reset/reset-hsdk.c b/drivers/reset/reset-hsdk.c index 74b1173e887..747e73b17fc 100644 --- a/drivers/reset/reset-hsdk.c +++ b/drivers/reset/reset-hsdk.c @@ -8,7 +8,6 @@ #include #include -#include #include #include #include diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c index a3b3132f2fa..65a352b71fd 100644 --- a/drivers/reset/reset-imx7.c +++ b/drivers/reset/reset-imx7.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/reset/reset-jh7110.c b/drivers/reset/reset-jh7110.c index d6bdf6bb00c..adf722d5871 100644 --- a/drivers/reset/reset-jh7110.c +++ b/drivers/reset/reset-jh7110.c @@ -5,7 +5,6 @@ * */ -#include #include #include #include diff --git a/drivers/reset/reset-mediatek.c b/drivers/reset/reset-mediatek.c index 97ed221f739..4b3afab92ea 100644 --- a/drivers/reset/reset-mediatek.c +++ b/drivers/reset/reset-mediatek.c @@ -6,7 +6,6 @@ * Weijie Gao */ -#include #include #include #include diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c index 9d0c8b354f4..6337cdaaffa 100644 --- a/drivers/reset/reset-meson.c +++ b/drivers/reset/reset-meson.c @@ -6,7 +6,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/drivers/reset/reset-mtmips.c b/drivers/reset/reset-mtmips.c index 7bb8469823c..2db6766280f 100644 --- a/drivers/reset/reset-mtmips.c +++ b/drivers/reset/reset-mtmips.c @@ -5,7 +5,6 @@ * Author: Weijie Gao */ -#include #include #include #include diff --git a/drivers/reset/reset-raspberrypi.c b/drivers/reset/reset-raspberrypi.c index 804e32b8dd1..1792f0813f7 100644 --- a/drivers/reset/reset-raspberrypi.c +++ b/drivers/reset/reset-raspberrypi.c @@ -4,7 +4,6 @@ * * Copyright (C) 2020 Nicolas Saenz Julienne */ -#include #include #include #include diff --git a/drivers/reset/reset-rockchip.c b/drivers/reset/reset-rockchip.c index 6cabaa10a35..876eb7dddaa 100644 --- a/drivers/reset/reset-rockchip.c +++ b/drivers/reset/reset-rockchip.c @@ -3,7 +3,6 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/drivers/reset/reset-scmi.c b/drivers/reset/reset-scmi.c index b76711f0a8f..6dc1fcb3365 100644 --- a/drivers/reset/reset-scmi.c +++ b/drivers/reset/reset-scmi.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_RESET -#include #include #include #include diff --git a/drivers/reset/reset-sifive.c b/drivers/reset/reset-sifive.c index 23513b2f541..65f857149b9 100644 --- a/drivers/reset/reset-sifive.c +++ b/drivers/reset/reset-sifive.c @@ -4,7 +4,6 @@ * Author: Sagar Kadam */ -#include #include #include #include diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index 6e3f03e2484..866437fd24f 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -12,7 +12,6 @@ * Maxime Ripard */ -#include #include #include #include diff --git a/drivers/reset/reset-sunxi.c b/drivers/reset/reset-sunxi.c index e484d1fff44..fd47e1f9e37 100644 --- a/drivers/reset/reset-sunxi.c +++ b/drivers/reset/reset-sunxi.c @@ -4,7 +4,6 @@ * Author: Jagan Teki */ -#include #include #include #include diff --git a/drivers/reset/reset-syscon.c b/drivers/reset/reset-syscon.c index ff387ab6b22..5be8c9492af 100644 --- a/drivers/reset/reset-syscon.c +++ b/drivers/reset/reset-syscon.c @@ -3,7 +3,6 @@ * Copyright (C) 2020 Sean Anderson */ -#include #include #include #include diff --git a/drivers/reset/reset-ti-sci.c b/drivers/reset/reset-ti-sci.c index fd654a08f13..e69bcd41cbe 100644 --- a/drivers/reset/reset-ti-sci.c +++ b/drivers/reset/reset-ti-sci.c @@ -8,7 +8,6 @@ * Loosely based on Linux kernel reset-ti-sci.c... */ -#include #include #include #include diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c index b972faf0132..fe4cebf54f1 100644 --- a/drivers/reset/reset-uclass.c +++ b/drivers/reset/reset-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_RESET -#include #include #include #include diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c index 35e3ccebd72..49b001f0594 100644 --- a/drivers/reset/reset-uniphier.c +++ b/drivers/reset/reset-uniphier.c @@ -5,7 +5,6 @@ * Author: Kunihiko Hayashi */ -#include #include #include #include diff --git a/drivers/reset/reset-zynqmp.c b/drivers/reset/reset-zynqmp.c index 87b4df5bf81..b9c4f09fdfd 100644 --- a/drivers/reset/reset-zynqmp.c +++ b/drivers/reset/reset-zynqmp.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_RESET -#include #include #include #include diff --git a/drivers/reset/rst-rk3588.c b/drivers/reset/rst-rk3588.c index 2c524e4c403..eae2eb10de2 100644 --- a/drivers/reset/rst-rk3588.c +++ b/drivers/reset/rst-rk3588.c @@ -5,7 +5,6 @@ * Author: Sebastian Reichel */ -#include #include #include #include diff --git a/drivers/reset/sandbox-reset-test.c b/drivers/reset/sandbox-reset-test.c index 51b79810c89..dfacb764bc7 100644 --- a/drivers/reset/sandbox-reset-test.c +++ b/drivers/reset/sandbox-reset-test.c @@ -3,7 +3,6 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ -#include #include #include #include diff --git a/drivers/reset/sandbox-reset.c b/drivers/reset/sandbox-reset.c index 97b1b92e4a6..adf9eedcba6 100644 --- a/drivers/reset/sandbox-reset.c +++ b/drivers/reset/sandbox-reset.c @@ -3,7 +3,6 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ -#include #include #include #include diff --git a/drivers/reset/sti-reset.c b/drivers/reset/sti-reset.c index 5305270fbf2..412a0c5b452 100644 --- a/drivers/reset/sti-reset.c +++ b/drivers/reset/sti-reset.c @@ -4,7 +4,6 @@ * Author(s): Patrice Chotard, for STMicroelectronics. */ -#include #include #include #include diff --git a/drivers/reset/stm32-reset.c b/drivers/reset/stm32-reset.c index 0bbde29810b..9d4f361b251 100644 --- a/drivers/reset/stm32-reset.c +++ b/drivers/reset/stm32-reset.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_RESET -#include #include #include #include diff --git a/drivers/reset/tegra-car-reset.c b/drivers/reset/tegra-car-reset.c index 501e9cab8f7..e3ecc8d3735 100644 --- a/drivers/reset/tegra-car-reset.c +++ b/drivers/reset/tegra-car-reset.c @@ -3,7 +3,6 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ -#include #include #include #include diff --git a/drivers/reset/tegra186-reset.c b/drivers/reset/tegra186-reset.c index d43da454114..89624227c29 100644 --- a/drivers/reset/tegra186-reset.c +++ b/drivers/reset/tegra186-reset.c @@ -3,7 +3,6 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ -#include #include #include #include diff --git a/drivers/rtc/abx80x.c b/drivers/rtc/abx80x.c index 823aff03f5f..1235b840ab0 100644 --- a/drivers/rtc/abx80x.c +++ b/drivers/rtc/abx80x.c @@ -12,7 +12,6 @@ * */ -#include #include #include #include diff --git a/drivers/rtc/davinci.c b/drivers/rtc/davinci.c index c7ce41bbf5c..a20b73e1990 100644 --- a/drivers/rtc/davinci.c +++ b/drivers/rtc/davinci.c @@ -4,7 +4,6 @@ * Heiko Schocher * Copyright (C) 2021 Dario Binacchi */ -#include #include #include #include diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c index 0e9d3d24dd8..ba06ff9f0be 100644 --- a/drivers/rtc/ds1307.c +++ b/drivers/rtc/ds1307.c @@ -13,7 +13,7 @@ * based on ds1337.c */ -#include +#include #include #include #include diff --git a/drivers/rtc/ds1337.c b/drivers/rtc/ds1337.c index 2c780ab8edf..7eccf1cb8c5 100644 --- a/drivers/rtc/ds1337.c +++ b/drivers/rtc/ds1337.c @@ -11,7 +11,7 @@ * DS1337 Real Time Clock (RTC). */ -#include +#include #include #include #include diff --git a/drivers/rtc/ds1374.c b/drivers/rtc/ds1374.c index 89442f9386b..895dbbaf1c7 100644 --- a/drivers/rtc/ds1374.c +++ b/drivers/rtc/ds1374.c @@ -13,7 +13,7 @@ * based on ds1337.c */ -#include +#include #include #include #include diff --git a/drivers/rtc/ds3231.c b/drivers/rtc/ds3231.c index bd32ed2dbf9..d6267d660d0 100644 --- a/drivers/rtc/ds3231.c +++ b/drivers/rtc/ds3231.c @@ -14,7 +14,7 @@ * copied from ds1337.c */ -#include +#include #include #include #include diff --git a/drivers/rtc/ds3232.c b/drivers/rtc/ds3232.c index 16501cfe5d3..7314ba219da 100644 --- a/drivers/rtc/ds3232.c +++ b/drivers/rtc/ds3232.c @@ -3,7 +3,6 @@ * (C) Copyright 2019, Vaisala Oyj */ -#include #include #include #include diff --git a/drivers/rtc/emul_rtc.c b/drivers/rtc/emul_rtc.c index 6f47d82522b..97a8d9bb7df 100644 --- a/drivers/rtc/emul_rtc.c +++ b/drivers/rtc/emul_rtc.c @@ -5,11 +5,11 @@ * This driver emulates a real time clock based on timer ticks. */ -#include #include #include #include #include +#include #include /** diff --git a/drivers/rtc/ht1380.c b/drivers/rtc/ht1380.c index 85fcee3e71e..c202261e999 100644 --- a/drivers/rtc/ht1380.c +++ b/drivers/rtc/ht1380.c @@ -15,7 +15,6 @@ * */ -#include #include #include #include diff --git a/drivers/rtc/i2c_rtc_emul.c b/drivers/rtc/i2c_rtc_emul.c index c307d6036dd..ea11c72c964 100644 --- a/drivers/rtc/i2c_rtc_emul.c +++ b/drivers/rtc/i2c_rtc_emul.c @@ -13,7 +13,6 @@ * time-keeping. It does not change the system time. */ -#include #include #include #include diff --git a/drivers/rtc/isl1208.c b/drivers/rtc/isl1208.c index 59a60b75b30..83db505afe9 100644 --- a/drivers/rtc/isl1208.c +++ b/drivers/rtc/isl1208.c @@ -11,7 +11,6 @@ * ISL1208 Real Time Clock (RTC). */ -#include #include #include #include diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c index 891fe09d311..7bfea9e0b31 100644 --- a/drivers/rtc/m41t62.c +++ b/drivers/rtc/m41t62.c @@ -16,7 +16,7 @@ /* #define DEBUG */ -#include +#include #include #include #include diff --git a/drivers/rtc/mc13xxx-rtc.c b/drivers/rtc/mc13xxx-rtc.c index 6c2aef89758..9e396bcdae9 100644 --- a/drivers/rtc/mc13xxx-rtc.c +++ b/drivers/rtc/mc13xxx-rtc.c @@ -3,7 +3,6 @@ * Copyright (C) 2008, Guennadi Liakhovetski */ -#include #include #include #include diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c index 03ce081d576..c0d86c6d063 100644 --- a/drivers/rtc/mc146818.c +++ b/drivers/rtc/mc146818.c @@ -8,7 +8,6 @@ * Date & Time support for the MC146818 (PIXX4) RTC */ -#include #include #include #include diff --git a/drivers/rtc/mcfrtc.c b/drivers/rtc/mcfrtc.c index d2ac889c309..b5cc6b96881 100644 --- a/drivers/rtc/mcfrtc.c +++ b/drivers/rtc/mcfrtc.c @@ -4,7 +4,6 @@ * TsiChung Liew (Tsi-Chung.Liew@freescale.com) */ -#include #include #include diff --git a/drivers/rtc/mvrtc.c b/drivers/rtc/mvrtc.c index 50240d57fa9..f070c681b94 100644 --- a/drivers/rtc/mvrtc.c +++ b/drivers/rtc/mvrtc.c @@ -8,7 +8,6 @@ * Date & Time support for Marvell Integrated RTC */ -#include #include #include #include diff --git a/drivers/rtc/mxsrtc.c b/drivers/rtc/mxsrtc.c index be899a92540..69d22a4bdcb 100644 --- a/drivers/rtc/mxsrtc.c +++ b/drivers/rtc/mxsrtc.c @@ -6,7 +6,6 @@ * on behalf of DENX Software Engineering GmbH */ -#include #include #include #include diff --git a/drivers/rtc/pcf2127.c b/drivers/rtc/pcf2127.c index 2f3fafb4968..27a340f07d6 100644 --- a/drivers/rtc/pcf2127.c +++ b/drivers/rtc/pcf2127.c @@ -5,7 +5,6 @@ /* #define DEBUG */ -#include #include #include #include diff --git a/drivers/rtc/pcf8563.c b/drivers/rtc/pcf8563.c index 91a412440b8..03bef68051b 100644 --- a/drivers/rtc/pcf8563.c +++ b/drivers/rtc/pcf8563.c @@ -10,7 +10,7 @@ /* #define DEBUG */ -#include +#include #include #include #include diff --git a/drivers/rtc/pl031.c b/drivers/rtc/pl031.c index a1d376611d6..855ee913416 100644 --- a/drivers/rtc/pl031.c +++ b/drivers/rtc/pl031.c @@ -6,7 +6,6 @@ * reference linux-2.6.20.6/drivers/rtc/rtc-pl031.c */ -#include #include #include #include diff --git a/drivers/rtc/pt7c4338.c b/drivers/rtc/pt7c4338.c index e0a7bd3662f..79df07814a6 100644 --- a/drivers/rtc/pt7c4338.c +++ b/drivers/rtc/pt7c4338.c @@ -18,7 +18,7 @@ * It has 56 bytes of nonvolatile RAM. */ -#include +#include #include #include #include diff --git a/drivers/rtc/rtc-uclass.c b/drivers/rtc/rtc-uclass.c index e5ae6ea4d5f..8f6c0c6a0a7 100644 --- a/drivers/rtc/rtc-uclass.c +++ b/drivers/rtc/rtc-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_RTC -#include #include #include #include diff --git a/drivers/rtc/rv3029.c b/drivers/rtc/rv3029.c index 3afe5b2fdd6..a82acec6f7e 100644 --- a/drivers/rtc/rv3029.c +++ b/drivers/rtc/rv3029.c @@ -7,10 +7,8 @@ * Michael Buesch */ -#include #include #include -#include #include #include #include diff --git a/drivers/rtc/rv8803.c b/drivers/rtc/rv8803.c index 06a4ae89fa9..82b43722ff5 100644 --- a/drivers/rtc/rv8803.c +++ b/drivers/rtc/rv8803.c @@ -10,7 +10,6 @@ * */ -#include #include #include #include diff --git a/drivers/rtc/rx8010sj.c b/drivers/rtc/rx8010sj.c index bf93b557748..0d778f4c328 100644 --- a/drivers/rtc/rx8010sj.c +++ b/drivers/rtc/rx8010sj.c @@ -17,7 +17,7 @@ */ #include -#include +#include #include #include #include diff --git a/drivers/rtc/rx8025.c b/drivers/rtc/rx8025.c index 1394c2306a4..c7895244283 100644 --- a/drivers/rtc/rx8025.c +++ b/drivers/rtc/rx8025.c @@ -8,7 +8,6 @@ * Epson RX8025 RTC driver. */ -#include #include #include #include diff --git a/drivers/rtc/s35392a.c b/drivers/rtc/s35392a.c index 80f55c86233..03fb9a0be91 100644 --- a/drivers/rtc/s35392a.c +++ b/drivers/rtc/s35392a.c @@ -18,7 +18,6 @@ */ #include -#include #include #include #include diff --git a/drivers/rtc/sandbox_rtc.c b/drivers/rtc/sandbox_rtc.c index 657e5c7be2c..4404501c2f6 100644 --- a/drivers/rtc/sandbox_rtc.c +++ b/drivers/rtc/sandbox_rtc.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/rtc/stm32_rtc.c b/drivers/rtc/stm32_rtc.c index ec7584c3d70..ee70c11c8bc 100644 --- a/drivers/rtc/stm32_rtc.c +++ b/drivers/rtc/stm32_rtc.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_RTC -#include #include #include #include diff --git a/drivers/rtc/zynqmp_rtc.c b/drivers/rtc/zynqmp_rtc.c index ab9b93ca979..15122a04838 100644 --- a/drivers/rtc/zynqmp_rtc.c +++ b/drivers/rtc/zynqmp_rtc.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_RTC -#include #include #include #include diff --git a/drivers/scsi/sandbox_scsi.c b/drivers/scsi/sandbox_scsi.c index a7ac33cb1c4..544a0247083 100644 --- a/drivers/scsi/sandbox_scsi.c +++ b/drivers/scsi/sandbox_scsi.c @@ -9,7 +9,6 @@ #define LOG_CATEGORY UCLASS_SCSI -#include #include #include #include diff --git a/drivers/scsi/scsi-uclass.c b/drivers/scsi/scsi-uclass.c index a7c1eaf0cf5..1ee8236c05c 100644 --- a/drivers/scsi/scsi-uclass.c +++ b/drivers/scsi/scsi-uclass.c @@ -10,7 +10,6 @@ #define LOG_CATEGORY UCLASS_SCSI -#include #include #include diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c index 79ee400d12f..73cb83548eb 100644 --- a/drivers/scsi/scsi.c +++ b/drivers/scsi/scsi.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_SCSI -#include #include #include #include diff --git a/drivers/scsi/scsi_bootdev.c b/drivers/scsi/scsi_bootdev.c index 218221fa306..28e4612f337 100644 --- a/drivers/scsi/scsi_bootdev.c +++ b/drivers/scsi/scsi_bootdev.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/scsi/scsi_emul.c b/drivers/scsi/scsi_emul.c index 6b8468f7994..d1bb926b713 100644 --- a/drivers/scsi/scsi_emul.c +++ b/drivers/scsi/scsi_emul.c @@ -11,7 +11,6 @@ #define LOG_CATEGORY UCLASS_SCSI -#include #include #include #include diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 403ab1ded68..dbe598b7406 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -65,3 +65,4 @@ obj-$(CONFIG_S5P4418_PL011_SERIAL) += serial_s5p4418_pl011.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o endif +obj-$(CONFIG_UART4_SERIAL) += serial_adi_uart4.o diff --git a/drivers/serial/altera_jtag_uart.c b/drivers/serial/altera_jtag_uart.c index 9e39da7dd24..3f706e1839f 100644 --- a/drivers/serial/altera_jtag_uart.c +++ b/drivers/serial/altera_jtag_uart.c @@ -4,7 +4,6 @@ * Scott McNutt */ -#include #include #include #include diff --git a/drivers/serial/altera_uart.c b/drivers/serial/altera_uart.c index 35920480841..3c13ef25bb4 100644 --- a/drivers/serial/altera_uart.c +++ b/drivers/serial/altera_uart.c @@ -4,7 +4,6 @@ * Scott McNutt */ -#include #include #include #include diff --git a/drivers/serial/arm_dcc.c b/drivers/serial/arm_dcc.c index a402a123b6d..66af136695d 100644 --- a/drivers/serial/arm_dcc.c +++ b/drivers/serial/arm_dcc.c @@ -15,7 +15,6 @@ * this file might be covered by the GNU General Public License. */ -#include #include #include diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index 9827c006fa8..7e45a80969e 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -5,7 +5,6 @@ * Modified to support C structur SoC access by * Andreas Bießmann */ -#include #include #include #include diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 6deb1d8ddc5..4963385dc1c 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -5,7 +5,7 @@ */ #include -#include +#include #include #include #include diff --git a/drivers/serial/sandbox.c b/drivers/serial/sandbox.c index f6ac3d22852..ec0068e33d3 100644 --- a/drivers/serial/sandbox.c +++ b/drivers/serial/sandbox.c @@ -9,7 +9,6 @@ * U-Boot. */ -#include #include #include #include diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index e4fa3933bc8..84f02f7ac76 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -5,7 +5,7 @@ #define LOG_CATEGORY UCLASS_SERIAL -#include +#include #include #include #include diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 787edd53602..dc4bb06fa99 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include diff --git a/drivers/serial/serial_adi_uart4.c b/drivers/serial/serial_adi_uart4.c new file mode 100644 index 00000000000..45f8315d0a0 --- /dev/null +++ b/drivers/serial/serial_adi_uart4.c @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Converted to driver model by Nathan Barrett-Morrison + * + * Contact: Nathan Barrett-Morrison + * Contact: Greg Malysa + * + */ + +#include +#include +#include +#include +#include +#include + +/* + * UART4 Masks + */ + +/* UART_CONTROL */ +#define UEN BIT(0) +#define LOOP_ENA BIT(1) +#define UMOD (3 << 4) +#define UMOD_UART (0 << 4) +#define UMOD_MDB BIT(4) +#define UMOD_IRDA BIT(4) +#define WLS (3 << 8) +#define WLS_5 (0 << 8) +#define WLS_6 BIT(8) +#define WLS_7 (2 << 8) +#define WLS_8 (3 << 8) +#define STB BIT(12) +#define STBH BIT(13) +#define PEN BIT(14) +#define EPS BIT(15) +#define STP BIT(16) +#define FPE BIT(17) +#define FFE BIT(18) +#define SB BIT(19) +#define FCPOL BIT(22) +#define RPOLC BIT(23) +#define TPOLC BIT(24) +#define MRTS BIT(25) +#define XOFF BIT(26) +#define ARTS BIT(27) +#define ACTS BIT(28) +#define RFIT BIT(29) +#define RFRT BIT(30) + +/* UART_STATUS */ +#define DR BIT(0) +#define OE BIT(1) +#define PE BIT(2) +#define FE BIT(3) +#define BI BIT(4) +#define THRE BIT(5) +#define TEMT BIT(7) +#define TFI BIT(8) +#define ASTKY BIT(9) +#define ADDR BIT(10) +#define RO BIT(11) +#define SCTS BIT(12) +#define CTS BIT(16) +#define RFCS BIT(17) + +/* UART_EMASK */ +#define ERBFI BIT(0) +#define ETBEI BIT(1) +#define ELSI BIT(2) +#define EDSSI BIT(3) +#define EDTPTI BIT(4) +#define ETFI BIT(5) +#define ERFCI BIT(6) +#define EAWI BIT(7) +#define ERXS BIT(8) +#define ETXS BIT(9) + +DECLARE_GLOBAL_DATA_PTR; + +struct uart4_reg { + u32 revid; + u32 control; + u32 status; + u32 scr; + u32 clock; + u32 emask; + u32 emaskst; + u32 emaskcl; + u32 rbr; + u32 thr; + u32 taip; + u32 tsr; + u32 rsr; + u32 txdiv_cnt; + u32 rxdiv_cnt; +}; + +struct adi_uart4_platdata { + // Hardware registers + struct uart4_reg *regs; + + // Enable divide-by-one baud rate setting + bool edbo; +}; + +static int adi_uart4_set_brg(struct udevice *dev, int baudrate) +{ + struct adi_uart4_platdata *plat = dev_get_plat(dev); + struct uart4_reg *regs = plat->regs; + u32 divisor, uart_base_clk_rate; + struct clk uart_base_clk; + + if (clk_get_by_index(dev, 0, &uart_base_clk)) { + dev_err(dev, "Could not get UART base clock\n"); + return -1; + } + + uart_base_clk_rate = clk_get_rate(&uart_base_clk); + + if (plat->edbo) { + u16 divisor16 = (uart_base_clk_rate + (baudrate / 2)) / baudrate; + + divisor = divisor16 | BIT(31); + } else { + // Divisor is only 16 bits + divisor = 0x0000ffff & ((uart_base_clk_rate + (baudrate * 8)) / (baudrate * 16)); + } + + writel(divisor, ®s->clock); + return 0; +} + +static int adi_uart4_pending(struct udevice *dev, bool input) +{ + struct adi_uart4_platdata *plat = dev_get_plat(dev); + struct uart4_reg *regs = plat->regs; + + if (input) + return (readl(®s->status) & DR) ? 1 : 0; + else + return (readl(®s->status) & THRE) ? 0 : 1; +} + +static int adi_uart4_getc(struct udevice *dev) +{ + struct adi_uart4_platdata *plat = dev_get_plat(dev); + struct uart4_reg *regs = plat->regs; + int uart_rbr_val; + + if (!adi_uart4_pending(dev, true)) + return -EAGAIN; + + uart_rbr_val = readl(®s->rbr); + writel(-1, ®s->status); + + return uart_rbr_val; +} + +static int adi_uart4_putc(struct udevice *dev, const char ch) +{ + struct adi_uart4_platdata *plat = dev_get_plat(dev); + struct uart4_reg *regs = plat->regs; + + if (adi_uart4_pending(dev, false)) + return -EAGAIN; + + writel(ch, ®s->thr); + return 0; +} + +static const struct dm_serial_ops adi_uart4_serial_ops = { + .setbrg = adi_uart4_set_brg, + .getc = adi_uart4_getc, + .putc = adi_uart4_putc, + .pending = adi_uart4_pending, +}; + +static int adi_uart4_of_to_plat(struct udevice *dev) +{ + struct adi_uart4_platdata *plat = dev_get_plat(dev); + fdt_addr_t addr; + + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->regs = (struct uart4_reg *)addr; + plat->edbo = dev_read_bool(dev, "adi,enable-edbo"); + + return 0; +} + +static int adi_uart4_probe(struct udevice *dev) +{ + struct adi_uart4_platdata *plat = dev_get_plat(dev); + struct uart4_reg *regs = plat->regs; + + /* always enable UART to 8-bit mode */ + writel(UEN | UMOD_UART | WLS_8, ®s->control); + + writel(-1, ®s->status); + + return 0; +} + +static const struct udevice_id adi_uart4_serial_ids[] = { + { .compatible = "adi,uart4" }, + { } +}; + +U_BOOT_DRIVER(serial_adi_uart4) = { + .name = "serial_adi_uart4", + .id = UCLASS_SERIAL, + .of_match = adi_uart4_serial_ids, + .of_to_plat = adi_uart4_of_to_plat, + .plat_auto = sizeof(struct adi_uart4_platdata), + .probe = adi_uart4_probe, + .ops = &adi_uart4_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/serial/serial_ar933x.c b/drivers/serial/serial_ar933x.c index 4f916349762..4d92752690f 100644 --- a/drivers/serial/serial_ar933x.c +++ b/drivers/serial/serial_ar933x.c @@ -3,7 +3,6 @@ * Copyright (C) 2015-2016 Wills Wang */ -#include #include #include #include diff --git a/drivers/serial/serial_arc.c b/drivers/serial/serial_arc.c index c2fc8a901e2..c0930cf7334 100644 --- a/drivers/serial/serial_arc.c +++ b/drivers/serial/serial_arc.c @@ -7,7 +7,6 @@ * */ -#include #include #include #include diff --git a/drivers/serial/serial_bcm283x_mu.c b/drivers/serial/serial_bcm283x_mu.c index 7585f790d22..7fa26244b1c 100644 --- a/drivers/serial/serial_bcm283x_mu.c +++ b/drivers/serial/serial_bcm283x_mu.c @@ -14,7 +14,6 @@ /* Simple U-Boot driver for the BCM283x mini UART */ -#include #include #include #include diff --git a/drivers/serial/serial_bcm283x_pl011.c b/drivers/serial/serial_bcm283x_pl011.c index 09a9868a38f..2abc1c4658f 100644 --- a/drivers/serial/serial_bcm283x_pl011.c +++ b/drivers/serial/serial_bcm283x_pl011.c @@ -3,7 +3,6 @@ * Copyright (c) 2018 Alexander Graf */ -#include #include #include #include diff --git a/drivers/serial/serial_coreboot.c b/drivers/serial/serial_coreboot.c index 23066e4d054..b1f69f6998c 100644 --- a/drivers/serial/serial_coreboot.c +++ b/drivers/serial/serial_coreboot.c @@ -7,7 +7,6 @@ #define LOG_CATGEGORY UCLASS_SERIAL -#include #include #include #include diff --git a/drivers/serial/serial_cortina.c b/drivers/serial/serial_cortina.c index 6dc81a775d3..3ae8fb46584 100644 --- a/drivers/serial/serial_cortina.c +++ b/drivers/serial/serial_cortina.c @@ -5,7 +5,6 @@ * */ -#include #include #include #include diff --git a/drivers/serial/serial_efi.c b/drivers/serial/serial_efi.c index 0067576389d..5733eaaf9d4 100644 --- a/drivers/serial/serial_efi.c +++ b/drivers/serial/serial_efi.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/serial/serial_htif.c b/drivers/serial/serial_htif.c index 5d2bf0aaeba..2a93bbbcc9f 100644 --- a/drivers/serial/serial_htif.c +++ b/drivers/serial/serial_htif.c @@ -3,7 +3,6 @@ * Copyright (C) 2022 Ventana Micro Systems Inc. */ -#include #include #include #include diff --git a/drivers/serial/serial_intel_mid.c b/drivers/serial/serial_intel_mid.c index bbf19057c4d..4b528e45292 100644 --- a/drivers/serial/serial_intel_mid.c +++ b/drivers/serial/serial_intel_mid.c @@ -3,7 +3,6 @@ * Copyright (c) 2017 Intel Corporation */ -#include #include #include #include diff --git a/drivers/serial/serial_linflexuart.c b/drivers/serial/serial_linflexuart.c index b449e55a650..ff66e69b9d7 100644 --- a/drivers/serial/serial_linflexuart.c +++ b/drivers/serial/serial_linflexuart.c @@ -3,7 +3,6 @@ * (C) Copyright 2013-2016 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index 3f2be72b830..a06e6dc2505 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -4,7 +4,6 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/drivers/serial/serial_mcf.c b/drivers/serial/serial_mcf.c index bb2afd0d8cd..76143575fa9 100644 --- a/drivers/serial/serial_mcf.c +++ b/drivers/serial/serial_mcf.c @@ -15,7 +15,6 @@ * as serial console interface. */ -#include #include #include #include diff --git a/drivers/serial/serial_meson.c b/drivers/serial/serial_meson.c index be5f380f850..bb79b972957 100644 --- a/drivers/serial/serial_meson.c +++ b/drivers/serial/serial_meson.c @@ -3,7 +3,6 @@ * (C) Copyright 2016 Beniamino Galvani */ -#include #include #include #include diff --git a/drivers/serial/serial_mpc8xx.c b/drivers/serial/serial_mpc8xx.c index d82760c7f10..9ce3fc3d9ec 100644 --- a/drivers/serial/serial_mpc8xx.c +++ b/drivers/serial/serial_mpc8xx.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index a472e0b3683..757e5eaf974 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -8,7 +8,6 @@ * Based on Linux driver. */ -#include #include #include #include diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c index 5260474fb9a..cb6c09fdd09 100644 --- a/drivers/serial/serial_msm_geni.c +++ b/drivers/serial/serial_msm_geni.c @@ -9,7 +9,6 @@ #include #include -#include #include #include #include diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c index f146f2b006e..3f569c68f22 100644 --- a/drivers/serial/serial_mtk.c +++ b/drivers/serial/serial_mtk.c @@ -7,7 +7,7 @@ */ #include -#include +#include #include #include #include diff --git a/drivers/serial/serial_mvebu_a3700.c b/drivers/serial/serial_mvebu_a3700.c index b2017c64556..1a0b85e170a 100644 --- a/drivers/serial/serial_mvebu_a3700.c +++ b/drivers/serial/serial_mvebu_a3700.c @@ -4,7 +4,6 @@ * Copyright (C) 2021 Pali Rohár */ -#include #include #include #include diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index cc85a502726..c5fd740be4d 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -3,7 +3,6 @@ * (c) 2007 Sascha Hauer */ -#include #include #include #include diff --git a/drivers/serial/serial_mxs.c b/drivers/serial/serial_mxs.c index 3659948b872..071bd09fef6 100644 --- a/drivers/serial/serial_mxs.c +++ b/drivers/serial/serial_mxs.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2023 Marek Vasut */ -#include #include #include #include diff --git a/drivers/serial/serial_npcm.c b/drivers/serial/serial_npcm.c index 6bf3a943a2f..661daf1aefa 100644 --- a/drivers/serial/serial_npcm.c +++ b/drivers/serial/serial_npcm.c @@ -3,7 +3,6 @@ * Copyright (c) 2021 Nuvoton Technology Corp. */ -#include #include #include #include diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c index 4014f682040..577864bc219 100644 --- a/drivers/serial/serial_ns16550.c +++ b/drivers/serial/serial_ns16550.c @@ -4,7 +4,7 @@ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. */ -#include +#include #include #include #include diff --git a/drivers/serial/serial_nulldev.c b/drivers/serial/serial_nulldev.c index f3ca7f52559..78a9e0b195f 100644 --- a/drivers/serial/serial_nulldev.c +++ b/drivers/serial/serial_nulldev.c @@ -3,7 +3,6 @@ * Copyright (c) 2015 National Instruments */ -#include #include #include diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c index 49ced8f9fae..94672655c28 100644 --- a/drivers/serial/serial_omap.c +++ b/drivers/serial/serial_omap.c @@ -6,7 +6,7 @@ * Lokesh Vutla */ -#include +#include #include #include #include diff --git a/drivers/serial/serial_owl.c b/drivers/serial/serial_owl.c index 3b795785f78..8ce8aa32a21 100644 --- a/drivers/serial/serial_owl.c +++ b/drivers/serial/serial_owl.c @@ -6,7 +6,6 @@ * Copyright (C) 2018 Manivannan Sadhasivam */ -#include #include #include #include diff --git a/drivers/serial/serial_pic32.c b/drivers/serial/serial_pic32.c index 0a03a9a2549..a49c4139b5a 100644 --- a/drivers/serial/serial_pic32.c +++ b/drivers/serial/serial_pic32.c @@ -3,7 +3,6 @@ * (c) 2015 Paul Thacker * */ -#include #include #include #include diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index f04c21e0826..80c35963b8f 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -10,7 +10,6 @@ /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */ -#include #include /* For get_bus_freq() */ #include diff --git a/drivers/serial/serial_rockchip.c b/drivers/serial/serial_rockchip.c index f4e9422ed91..8a15173f238 100644 --- a/drivers/serial/serial_rockchip.c +++ b/drivers/serial/serial_rockchip.c @@ -3,7 +3,6 @@ * Copyright (c) 2015 Google, Inc */ -#include #include #include #include diff --git a/drivers/serial/serial_s5p4418_pl011.c b/drivers/serial/serial_s5p4418_pl011.c index e4492e662e9..1fb954e80c2 100644 --- a/drivers/serial/serial_s5p4418_pl011.c +++ b/drivers/serial/serial_s5p4418_pl011.c @@ -3,7 +3,6 @@ * Copyright (C) 2022 Stefan Bosch */ -#include #include #include #include diff --git a/drivers/serial/serial_semihosting.c b/drivers/serial/serial_semihosting.c index cfa1ec3148c..56a5ec72428 100644 --- a/drivers/serial/serial_semihosting.c +++ b/drivers/serial/serial_semihosting.c @@ -3,7 +3,6 @@ * Copyright (C) 2022 Sean Anderson */ -#include #include #include #include diff --git a/drivers/serial/serial_sifive.c b/drivers/serial/serial_sifive.c index c449f3fd02d..e47828e4d6a 100644 --- a/drivers/serial/serial_sifive.c +++ b/drivers/serial/serial_sifive.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Anup Patel */ -#include #include #include #include diff --git a/drivers/serial/serial_sti_asc.c b/drivers/serial/serial_sti_asc.c index 40381b57b08..ef68e585dd6 100644 --- a/drivers/serial/serial_sti_asc.c +++ b/drivers/serial/serial_sti_asc.c @@ -6,7 +6,6 @@ * Author(s): Patrice Chotard, for STMicroelectronics. */ -#include #include #include #include diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c index fb039546a41..1ee58142b3f 100644 --- a/drivers/serial/serial_stm32.c +++ b/drivers/serial/serial_stm32.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_SERIAL -#include #include #include #include diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c index 27e4b92c399..a566ba7a47d 100644 --- a/drivers/serial/serial_uniphier.c +++ b/drivers/serial/serial_uniphier.c @@ -5,7 +5,6 @@ * Author: Masahiro Yamada */ -#include #include #include #include diff --git a/drivers/serial/serial_xen.c b/drivers/serial/serial_xen.c index ab318b06462..e05805f6372 100644 --- a/drivers/serial/serial_xen.c +++ b/drivers/serial/serial_xen.c @@ -3,7 +3,6 @@ * (C) 2018 NXP * (C) 2020 EPAM Systems Inc. */ -#include #include #include #include diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c index 35df413321f..eb234108746 100644 --- a/drivers/serial/serial_xuartlite.c +++ b/drivers/serial/serial_xuartlite.c @@ -8,7 +8,6 @@ */ #include -#include #include #include #include diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 1847d1f6ecd..55f13c00ddf 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/drivers/serial/usbtty.c b/drivers/serial/usbtty.c index ecb6ba853df..ae3ac8070d3 100644 --- a/drivers/serial/usbtty.c +++ b/drivers/serial/usbtty.c @@ -7,7 +7,6 @@ * Bryan O'Donoghue, bodonoghue@codehermit.ie */ -#include #include #include #include diff --git a/drivers/sm/meson-sm.c b/drivers/sm/meson-sm.c index 15b3b0e2672..87eba1486db 100644 --- a/drivers/sm/meson-sm.c +++ b/drivers/sm/meson-sm.c @@ -5,7 +5,6 @@ * Author: Alexey Romanov */ -#include #include #include #include diff --git a/drivers/sm/sandbox-sm.c b/drivers/sm/sandbox-sm.c index 109ddb2af55..a95e685494c 100644 --- a/drivers/sm/sandbox-sm.c +++ b/drivers/sm/sandbox-sm.c @@ -5,7 +5,6 @@ * Author: Alexey Romanov */ -#include #include #include #include diff --git a/drivers/sm/sm-uclass.c b/drivers/sm/sm-uclass.c index 6a8b7026293..abca0052e29 100644 --- a/drivers/sm/sm-uclass.c +++ b/drivers/sm/sm-uclass.c @@ -5,7 +5,6 @@ * Author: Alexey Romanov */ -#include #include #include #include diff --git a/drivers/smem/msm_smem.c b/drivers/smem/msm_smem.c index 17ee6c837c6..ccd145f9afb 100644 --- a/drivers/smem/msm_smem.c +++ b/drivers/smem/msm_smem.c @@ -5,7 +5,6 @@ * Copyright (c) 2018, Ramon Fried */ -#include #include #include #include diff --git a/drivers/smem/sandbox_smem.c b/drivers/smem/sandbox_smem.c index 7397e4407ad..fec98e5611d 100644 --- a/drivers/smem/sandbox_smem.c +++ b/drivers/smem/sandbox_smem.c @@ -3,7 +3,6 @@ * Copyright (c) 2018 Ramon Fried */ -#include #include #include #include diff --git a/drivers/smem/smem-uclass.c b/drivers/smem/smem-uclass.c index 8469076915e..4dea5cc4bf1 100644 --- a/drivers/smem/smem-uclass.c +++ b/drivers/smem/smem-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_SMEM -#include #include #include diff --git a/drivers/soc/soc-uclass.c b/drivers/soc/soc-uclass.c index 8b3044fed8d..744cdda2e18 100644 --- a/drivers/soc/soc-uclass.c +++ b/drivers/soc/soc-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_SOC -#include #include #include #include diff --git a/drivers/soc/soc_sandbox.c b/drivers/soc/soc_sandbox.c index 15fdd9930cb..8d621e88f56 100644 --- a/drivers/soc/soc_sandbox.c +++ b/drivers/soc/soc_sandbox.c @@ -6,7 +6,6 @@ * Dave Gerlach */ -#include #include #include diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c index 3a4e58bba67..b585e47d46f 100644 --- a/drivers/soc/soc_ti_k3.c +++ b/drivers/soc/soc_ti_k3.c @@ -4,7 +4,6 @@ * Dave Gerlach */ -#include #include #include diff --git a/drivers/soc/soc_xilinx_versal.c b/drivers/soc/soc_xilinx_versal.c index 3d8c25c19bb..7427f8432c8 100644 --- a/drivers/soc/soc_xilinx_versal.c +++ b/drivers/soc/soc_xilinx_versal.c @@ -5,7 +5,6 @@ * Copyright (C) 2021 Xilinx, Inc. */ -#include #include #include #include diff --git a/drivers/soc/soc_xilinx_versal_net.c b/drivers/soc/soc_xilinx_versal_net.c index 146d068bb4a..d64fc366a6d 100644 --- a/drivers/soc/soc_xilinx_versal_net.c +++ b/drivers/soc/soc_xilinx_versal_net.c @@ -5,7 +5,6 @@ * Copyright (C) 2022, Advanced Micro Devices, Inc. */ -#include #include #include #include diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c index d8b4f172a39..a2d5b82fd34 100644 --- a/drivers/soc/soc_xilinx_zynqmp.c +++ b/drivers/soc/soc_xilinx_zynqmp.c @@ -9,7 +9,6 @@ * Stefan Herbrechtsmeier */ -#include #include #include #include diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c index ed39ff2fa4c..d3f3d4761c2 100644 --- a/drivers/soc/ti/k3-navss-ringacc.c +++ b/drivers/soc/ti/k3-navss-ringacc.c @@ -5,7 +5,6 @@ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com */ -#include #include #include #include diff --git a/drivers/soc/ti/keystone_serdes.c b/drivers/soc/ti/keystone_serdes.c index 0e1bf8ff39d..b19617997e1 100644 --- a/drivers/soc/ti/keystone_serdes.c +++ b/drivers/soc/ti/keystone_serdes.c @@ -7,7 +7,6 @@ */ #include -#include #include #include #include diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c index 461390925d2..e3bb2ede554 100644 --- a/drivers/soc/ti/pruss.c +++ b/drivers/soc/ti/pruss.c @@ -5,7 +5,6 @@ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ */ -#include #include #include #include @@ -205,6 +204,7 @@ static int pruss_probe(struct udevice *dev) static const struct udevice_id pruss_ids[] = { { .compatible = "ti,am654-icssg"}, + { .compatible = "ti,am642-icssg"}, {} }; diff --git a/drivers/sound/broadwell_i2s.c b/drivers/sound/broadwell_i2s.c index 7f754e65676..bc44b5ec7e1 100644 --- a/drivers/sound/broadwell_i2s.c +++ b/drivers/sound/broadwell_i2s.c @@ -9,7 +9,6 @@ #define LOG_CATEGORY UCLASS_I2S -#include #include #include #include diff --git a/drivers/sound/broadwell_sound.c b/drivers/sound/broadwell_sound.c index 6e083fe1f69..473f8d8f977 100644 --- a/drivers/sound/broadwell_sound.c +++ b/drivers/sound/broadwell_sound.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_SOUND -#include #include #include #include diff --git a/drivers/sound/codec-uclass.c b/drivers/sound/codec-uclass.c index 2cb233bd306..1c1560619ea 100644 --- a/drivers/sound/codec-uclass.c +++ b/drivers/sound/codec-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_AUDIO_CODEC -#include #include #include diff --git a/drivers/sound/da7219.c b/drivers/sound/da7219.c index c1edef44360..5b9b3f65263 100644 --- a/drivers/sound/da7219.c +++ b/drivers/sound/da7219.c @@ -6,7 +6,6 @@ * Parts taken from coreboot */ -#include #include #include #include diff --git a/drivers/sound/hda_codec.c b/drivers/sound/hda_codec.c index af6148ef724..da8bde67de6 100644 --- a/drivers/sound/hda_codec.c +++ b/drivers/sound/hda_codec.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY UCLASS_SOUND -#include #include #include #include diff --git a/drivers/sound/i2s-uclass.c b/drivers/sound/i2s-uclass.c index fc4f686b516..6263c4d7071 100644 --- a/drivers/sound/i2s-uclass.c +++ b/drivers/sound/i2s-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_I2S -#include #include #include diff --git a/drivers/sound/i8254_beep.c b/drivers/sound/i8254_beep.c index 5572dc4d265..7234ad4a07e 100644 --- a/drivers/sound/i8254_beep.c +++ b/drivers/sound/i8254_beep.c @@ -3,7 +3,6 @@ * Copyright 2018 Google LLC */ -#include #include #include #include diff --git a/drivers/sound/ivybridge_sound.c b/drivers/sound/ivybridge_sound.c index d982219e06d..aeeba1d267e 100644 --- a/drivers/sound/ivybridge_sound.c +++ b/drivers/sound/ivybridge_sound.c @@ -12,7 +12,6 @@ #define LOG_CATEGORY UCLASS_SOUND -#include #include #include #include diff --git a/drivers/sound/max98088.c b/drivers/sound/max98088.c index c0463b8e8a6..d9037641ca4 100644 --- a/drivers/sound/max98088.c +++ b/drivers/sound/max98088.c @@ -8,7 +8,6 @@ * following the changes made in max98095.c */ -#include #include #include #include diff --git a/drivers/sound/max98090.c b/drivers/sound/max98090.c index a798762f1ee..18a3ffa85c8 100644 --- a/drivers/sound/max98090.c +++ b/drivers/sound/max98090.c @@ -5,7 +5,6 @@ * Copyright 2011 Maxim Integrated Products */ -#include #include #include #include diff --git a/drivers/sound/max98095.c b/drivers/sound/max98095.c index d0f701aaf10..96e772cff21 100644 --- a/drivers/sound/max98095.c +++ b/drivers/sound/max98095.c @@ -7,7 +7,6 @@ * Modified for U-Boot by R. Chandrasekar (rcsekar@samsung.com) */ -#include #include #include #include diff --git a/drivers/sound/max98357a.c b/drivers/sound/max98357a.c index bdf6dc236ec..da56ffdd6bb 100644 --- a/drivers/sound/max98357a.c +++ b/drivers/sound/max98357a.c @@ -6,7 +6,6 @@ * Parts taken from coreboot */ -#include #include #include #include diff --git a/drivers/sound/maxim_codec.c b/drivers/sound/maxim_codec.c index 6553d959047..98f094c0e9a 100644 --- a/drivers/sound/maxim_codec.c +++ b/drivers/sound/maxim_codec.c @@ -5,7 +5,6 @@ * Copyright 2011 Maxim Integrated Products */ -#include #include #include #include diff --git a/drivers/sound/rockchip_i2s.c b/drivers/sound/rockchip_i2s.c index 4e9e68aaac8..5078dfbed07 100644 --- a/drivers/sound/rockchip_i2s.c +++ b/drivers/sound/rockchip_i2s.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY UCLASS_I2S -#include #include #include #include diff --git a/drivers/sound/rockchip_sound.c b/drivers/sound/rockchip_sound.c index 94058e603d7..418d2efd452 100644 --- a/drivers/sound/rockchip_sound.c +++ b/drivers/sound/rockchip_sound.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_SOUND -#include #include #include #include diff --git a/drivers/sound/rt5677.c b/drivers/sound/rt5677.c index b655bb40b64..b5c997c6dd5 100644 --- a/drivers/sound/rt5677.c +++ b/drivers/sound/rt5677.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_SOUND -#include #include #include #include diff --git a/drivers/sound/samsung-i2s.c b/drivers/sound/samsung-i2s.c index dc5a2789aee..42175fd7d28 100644 --- a/drivers/sound/samsung-i2s.c +++ b/drivers/sound/samsung-i2s.c @@ -4,11 +4,11 @@ * R. Chandrasekar */ -#include #include #include #include #include +#include #include #include #include diff --git a/drivers/sound/samsung_sound.c b/drivers/sound/samsung_sound.c index 473cedf7e97..9150ad4a63b 100644 --- a/drivers/sound/samsung_sound.c +++ b/drivers/sound/samsung_sound.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/sound/sandbox.c b/drivers/sound/sandbox.c index c6cbd81fdbc..31ae153530e 100644 --- a/drivers/sound/sandbox.c +++ b/drivers/sound/sandbox.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_SOUND -#include #include #include #include diff --git a/drivers/sound/sound-uclass.c b/drivers/sound/sound-uclass.c index 2ffc4fc7c1d..b8a3dab447d 100644 --- a/drivers/sound/sound-uclass.c +++ b/drivers/sound/sound-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_SOUND -#include #include #include #include diff --git a/drivers/sound/sound.c b/drivers/sound/sound.c index c0fc50c99da..4fde2989e04 100644 --- a/drivers/sound/sound.c +++ b/drivers/sound/sound.c @@ -4,9 +4,9 @@ * R. Chandrasekar */ -#include #include #include +#include void sound_create_square_wave(uint sample_rate, unsigned short *data, int size, uint freq, uint channels) diff --git a/drivers/sound/tegra_ahub.c b/drivers/sound/tegra_ahub.c index 495a29c5137..8f1b0c009a8 100644 --- a/drivers/sound/tegra_ahub.c +++ b/drivers/sound/tegra_ahub.c @@ -7,11 +7,11 @@ #define LOG_CATEGORY UCLASS_MISC -#include #include #include #include #include +#include #include #include #include diff --git a/drivers/sound/tegra_i2s.c b/drivers/sound/tegra_i2s.c index 932f737900e..357aac36cea 100644 --- a/drivers/sound/tegra_i2s.c +++ b/drivers/sound/tegra_i2s.c @@ -5,7 +5,6 @@ */ #define LOG_CATEGORY UCLASS_I2S -#include #include #include #include diff --git a/drivers/sound/tegra_sound.c b/drivers/sound/tegra_sound.c index aef6a2eb147..152c929146f 100644 --- a/drivers/sound/tegra_sound.c +++ b/drivers/sound/tegra_sound.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_I2S -#include #include #include #include diff --git a/drivers/sound/wm8994.c b/drivers/sound/wm8994.c index fd646479b31..6b3091aa5de 100644 --- a/drivers/sound/wm8994.c +++ b/drivers/sound/wm8994.c @@ -3,7 +3,6 @@ * Copyright (C) 2012 Samsung Electronics * R. Chandrasekar */ -#include #include #include #include diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c index 989679e881b..8e227d187b0 100644 --- a/drivers/spi/altera_spi.c +++ b/drivers/spi/altera_spi.c @@ -6,7 +6,6 @@ * Copyright (c) 2005-2008 Analog Devices Inc. * Copyright (C) 2010 Thomas Chou */ -#include #include #include #include diff --git a/drivers/spi/apple_spi.c b/drivers/spi/apple_spi.c index f35f5af1f6f..5f94e9f7a74 100644 --- a/drivers/spi/apple_spi.c +++ b/drivers/spi/apple_spi.c @@ -4,7 +4,6 @@ * Copyright The Asahi Linux Contributors */ -#include #include #include #include diff --git a/drivers/spi/atcspi200_spi.c b/drivers/spi/atcspi200_spi.c index 70cb242cd31..929bf90458c 100644 --- a/drivers/spi/atcspi200_spi.c +++ b/drivers/spi/atcspi200_spi.c @@ -6,7 +6,6 @@ * Author: Rick Chen (rick@andestech.com) */ -#include #include #include #include diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c index 205567ef54d..faefac71260 100644 --- a/drivers/spi/ath79_spi.c +++ b/drivers/spi/ath79_spi.c @@ -3,7 +3,6 @@ * Copyright (C) 2015-2016 Wills Wang */ -#include #include #include #include diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index bd73e4fddf1..3efb661803b 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c index d4f0c4c4483..79f01001318 100644 --- a/drivers/spi/atmel_spi.c +++ b/drivers/spi/atmel_spi.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2007 Atmel Corporation */ -#include #include #include #include diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c index 23ac5bb76c0..1aa43fd3a23 100644 --- a/drivers/spi/bcm63xx_hsspi.c +++ b/drivers/spi/bcm63xx_hsspi.c @@ -7,7 +7,6 @@ * Copyright (C) 2012-2013 Jonas Gorski */ -#include #include #include #include diff --git a/drivers/spi/bcm63xx_spi.c b/drivers/spi/bcm63xx_spi.c index 889ac1f966e..595b41c8ab8 100644 --- a/drivers/spi/bcm63xx_spi.c +++ b/drivers/spi/bcm63xx_spi.c @@ -7,7 +7,6 @@ * Copyright (C) 2010 Tanguy Bouzeloc */ -#include #include #include #include diff --git a/drivers/spi/bcmbca_hsspi.c b/drivers/spi/bcmbca_hsspi.c index af45882db0a..eff9e1117d3 100644 --- a/drivers/spi/bcmbca_hsspi.c +++ b/drivers/spi/bcmbca_hsspi.c @@ -8,7 +8,6 @@ * Copyright (C) 2021 Broadcom Ltd */ -#include #include #include #include diff --git a/drivers/spi/ca_sflash.c b/drivers/spi/ca_sflash.c index 38bddd38619..a99a8a4485a 100644 --- a/drivers/spi/ca_sflash.c +++ b/drivers/spi/ca_sflash.c @@ -7,7 +7,6 @@ * Author: PengPeng Chen */ -#include #include #include #include diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index c2be307f1d8..222f828f54e 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index f4593c47b8c..75e52232010 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -4,7 +4,6 @@ * Altera Corporation */ -#include #include #include #include diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index fb905322178..93ab2b5635f 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -25,7 +25,6 @@ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include #include #include #include diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c index 1a841b5dcef..8234468b1d4 100644 --- a/drivers/spi/cf_spi.c +++ b/drivers/spi/cf_spi.c @@ -13,7 +13,6 @@ * TODO: fsl_dspi.c should work as a driver for the DSPI module. */ -#include #include #include #include diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index 25f5e9fdebd..04c134be9ed 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -8,7 +8,7 @@ * Copyright (C) 2007 Atmel Corporation */ -#include +#include #include #include #include diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 22a79da2333..6bd48b1b373 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -11,7 +11,6 @@ */ #define LOG_CATEGORY UCLASS_SPI -#include #include #include #include diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c index 1bcc3ad318d..1b9bf004b7c 100644 --- a/drivers/spi/exynos_spi.c +++ b/drivers/spi/exynos_spi.c @@ -4,7 +4,6 @@ * Padmavathi Venna */ -#include #include #include #include diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c index 9b3d5a94817..1d4d90ce5aa 100644 --- a/drivers/spi/fsl_dspi.c +++ b/drivers/spi/fsl_dspi.c @@ -11,7 +11,6 @@ #include #include -#include #include #include #include diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index b1d964d79d0..2638ed25200 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -8,7 +8,7 @@ * Chuanhua Han (chuanhua.han@nxp.com) */ -#include +#include #include #include #include diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 3f97730bad0..8a0a53cb372 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -23,7 +23,6 @@ * Transition to spi-mem in spi-fsl-qspi.c */ -#include #include #include #include diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 9142ffd2387..e48ca65fe72 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY UCLASS_SPI -#include #include #include #include diff --git a/drivers/spi/iproc_qspi.c b/drivers/spi/iproc_qspi.c index b5c274314b5..09f30c22702 100644 --- a/drivers/spi/iproc_qspi.c +++ b/drivers/spi/iproc_qspi.c @@ -3,7 +3,6 @@ * Copyright 2020-2021 Broadcom */ -#include #include #include #include diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index 2bb7390bbfb..095cbea0fca 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -7,7 +7,7 @@ * Derived from drivers/spi/mpc8xxx_spi.c */ -#include +#include #include #include #include diff --git a/drivers/spi/meson_spifc.c b/drivers/spi/meson_spifc.c index d99a151406e..d7ebb6bf1ac 100644 --- a/drivers/spi/meson_spifc.c +++ b/drivers/spi/meson_spifc.c @@ -7,7 +7,6 @@ * Amlogic Meson SPI Flash Controller driver */ -#include #include #include #include diff --git a/drivers/spi/microchip_coreqspi.c b/drivers/spi/microchip_coreqspi.c index 5fe0c8e1237..234b1688272 100644 --- a/drivers/spi/microchip_coreqspi.c +++ b/drivers/spi/microchip_coreqspi.c @@ -5,7 +5,6 @@ * Naga Sureshkumar Relli */ -#include #include #include #include diff --git a/drivers/spi/mpc8xx_spi.c b/drivers/spi/mpc8xx_spi.c index e1448cc6196..7e72fb9e23d 100644 --- a/drivers/spi/mpc8xx_spi.c +++ b/drivers/spi/mpc8xx_spi.c @@ -16,7 +16,6 @@ * */ -#include #include #include #include diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c index 7d15390c56b..cd624f4d6f0 100644 --- a/drivers/spi/mpc8xxx_spi.c +++ b/drivers/spi/mpc8xxx_spi.c @@ -4,7 +4,6 @@ * With help from the common/soft_spi and arch/powerpc/cpu/mpc8260 drivers */ -#include #include #include #include diff --git a/drivers/spi/mscc_bb_spi.c b/drivers/spi/mscc_bb_spi.c index 95bea0da1b3..ad4daeba3cd 100644 --- a/drivers/spi/mscc_bb_spi.c +++ b/drivers/spi/mscc_bb_spi.c @@ -5,7 +5,6 @@ * Copyright (c) 2018 Microsemi Corporation */ -#include #include #include #include diff --git a/drivers/spi/mt7621_spi.c b/drivers/spi/mt7621_spi.c index 3d008099862..e46942de2e3 100644 --- a/drivers/spi/mt7621_spi.c +++ b/drivers/spi/mt7621_spi.c @@ -8,7 +8,6 @@ * Copyright (C) 2014-2015 Felix Fietkau */ -#include #include #include #include diff --git a/drivers/spi/mtk_snfi_spi.c b/drivers/spi/mtk_snfi_spi.c index 3decb3744de..830424b31d6 100644 --- a/drivers/spi/mtk_snfi_spi.c +++ b/drivers/spi/mtk_snfi_spi.c @@ -5,7 +5,6 @@ * Author: Weijie Gao */ -#include #include #include #include diff --git a/drivers/spi/mtk_snor.c b/drivers/spi/mtk_snor.c index 4b7d4a6e074..f202b2f49f5 100644 --- a/drivers/spi/mtk_snor.c +++ b/drivers/spi/mtk_snor.c @@ -7,7 +7,6 @@ // Some parts are based on drivers/spi/spi-mtk-nor.c of linux version #include -#include #include #include #include diff --git a/drivers/spi/mvebu_a3700_spi.c b/drivers/spi/mvebu_a3700_spi.c index bba2383a111..fde9b142fb8 100644 --- a/drivers/spi/mvebu_a3700_spi.c +++ b/drivers/spi/mvebu_a3700_spi.c @@ -5,7 +5,6 @@ * Copyright (C) 2016 Stefan Roese */ -#include #include #include #include diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index e291092c481..ff61a14f095 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -3,7 +3,7 @@ * Copyright (C) 2008, Guennadi Liakhovetski */ -#include +#include #include #include #include diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index 773e26bbed7..ad9e490faa9 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -12,7 +12,6 @@ * GPIO driven chipselects are not supported. */ -#include #include #include #include diff --git a/drivers/spi/npcm_pspi.c b/drivers/spi/npcm_pspi.c index c9441304f5a..7708a96971c 100644 --- a/drivers/spi/npcm_pspi.c +++ b/drivers/spi/npcm_pspi.c @@ -3,7 +3,6 @@ * Copyright (c) 2021 Nuvoton Technology. */ -#include #include #include #include diff --git a/drivers/spi/nxp_fspi.c b/drivers/spi/nxp_fspi.c index 5db27f9ae2c..fefdaaa9e90 100644 --- a/drivers/spi/nxp_fspi.c +++ b/drivers/spi/nxp_fspi.c @@ -33,7 +33,6 @@ * Frieder Schrempf */ -#include #include #include #include diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index 5cce6baa621..3d82fc74ff5 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -16,9 +16,9 @@ * Modified by Ruslan Araslanov */ -#include #include #include +#include #include #include #include diff --git a/drivers/spi/pic32_spi.c b/drivers/spi/pic32_spi.c index 45f07f083da..e11ae7fc7a4 100644 --- a/drivers/spi/pic32_spi.c +++ b/drivers/spi/pic32_spi.c @@ -6,7 +6,6 @@ * Purna Chandra Mandal */ -#include #include #include #include diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c index e2b49ebd149..1e20701d0d3 100644 --- a/drivers/spi/pl022_spi.c +++ b/drivers/spi/pl022_spi.c @@ -10,7 +10,6 @@ */ #include -#include #include #include #include diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index 8aff2238645..e6b602cf7b4 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut */ -#include #include #include #include diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c index c8694fdff95..4571dc9f9b6 100644 --- a/drivers/spi/rk_spi.c +++ b/drivers/spi/rk_spi.c @@ -10,7 +10,6 @@ * Peter, Software Engineering, . */ -#include #include #include #include diff --git a/drivers/spi/sandbox_spi.c b/drivers/spi/sandbox_spi.c index f844597d04c..4cc016138b1 100644 --- a/drivers/spi/sandbox_spi.c +++ b/drivers/spi/sandbox_spi.c @@ -10,7 +10,6 @@ #define LOG_CATEGORY UCLASS_SPI -#include #include #include #include diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c index 72594993853..b7364a61929 100644 --- a/drivers/spi/sh_qspi.c +++ b/drivers/spi/sh_qspi.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_SPI -#include #include #include #include diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c index 0fa14339bdc..9bdb4a5bff9 100644 --- a/drivers/spi/soft_spi.c +++ b/drivers/spi/soft_spi.c @@ -9,7 +9,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c index 7d5f101a766..d91d58da459 100644 --- a/drivers/spi/spi-aspeed-smc.c +++ b/drivers/spi/spi-aspeed-smc.c @@ -12,7 +12,6 @@ #include #include -#include #include #include #include diff --git a/drivers/spi/spi-emul-uclass.c b/drivers/spi/spi-emul-uclass.c index 64bc19c0011..d92f36bd20e 100644 --- a/drivers/spi/spi-emul-uclass.c +++ b/drivers/spi/spi-emul-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_SPI_EMUL -#include #include #include #include diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index b7eca583595..3579b7d7db5 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -13,7 +13,6 @@ #include #include "internals.h" #else -#include #include #include #include diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c index f663b9dcbb1..b98bcd9b6ba 100644 --- a/drivers/spi/spi-mxic.c +++ b/drivers/spi/spi-mxic.c @@ -6,7 +6,6 @@ * zhengxunli */ -#include #include #include #include diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index 572cef1694c..836c550b0bb 100644 --- a/drivers/spi/spi-qup.c +++ b/drivers/spi/spi-qup.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c index ea372a05f83..0c8666c05f9 100644 --- a/drivers/spi/spi-sifive.c +++ b/drivers/spi/spi-sifive.c @@ -6,7 +6,6 @@ * SiFive SPI controller driver (master mode only) */ -#include #include #include #include diff --git a/drivers/spi/spi-sn-f-ospi.c b/drivers/spi/spi-sn-f-ospi.c index e3633a52608..fc82791006e 100644 --- a/drivers/spi/spi-sn-f-ospi.c +++ b/drivers/spi/spi-sn-f-ospi.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c index 9ec6b359e22..13725ee7a2d 100644 --- a/drivers/spi/spi-sunxi.c +++ b/drivers/spi/spi-sunxi.c @@ -18,7 +18,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include #include #include #include diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c index 553f9687e3b..eb522fd7b3d 100644 --- a/drivers/spi/spi-synquacer.c +++ b/drivers/spi/spi-synquacer.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index f4795e68672..6e281725239 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_SPI -#include #include #include #include diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 22910de0dd9..50a076a98be 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -3,7 +3,6 @@ * Copyright (c) 2011 The Chromium OS Authors. */ -#include #include #include #include diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c index 2ffa201a66e..2812a4da411 100644 --- a/drivers/spi/stm32_qspi.c +++ b/drivers/spi/stm32_qspi.c @@ -9,7 +9,6 @@ #define LOG_CATEGORY UCLASS_SPI -#include #include #include #include diff --git a/drivers/spi/stm32_spi.c b/drivers/spi/stm32_spi.c index ddb410a94c0..97b83b17167 100644 --- a/drivers/spi/stm32_spi.c +++ b/drivers/spi/stm32_spi.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY UCLASS_SPI -#include #include #include #include diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c index f0256d8e664..57f1a8fc703 100644 --- a/drivers/spi/tegra114_spi.c +++ b/drivers/spi/tegra114_spi.c @@ -5,7 +5,6 @@ * Copyright (c) 2010-2013 NVIDIA Corporation */ -#include #include #include #include diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c index 10e38cf839d..19114808e9d 100644 --- a/drivers/spi/tegra20_sflash.c +++ b/drivers/spi/tegra20_sflash.c @@ -5,7 +5,6 @@ * With more help from omap3_spi SPI driver */ -#include #include #include #include diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c index d0e788539e0..d54a5049205 100644 --- a/drivers/spi/tegra20_slink.c +++ b/drivers/spi/tegra20_slink.c @@ -5,7 +5,6 @@ * Copyright (c) 2010-2013 NVIDIA Corporation */ -#include #include #include #include diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c index 5c8c1859cc9..b969a7993d4 100644 --- a/drivers/spi/tegra210_qspi.c +++ b/drivers/spi/tegra210_qspi.c @@ -6,7 +6,6 @@ * */ -#include #include #include #include diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 99acb108823..a16412ec6fb 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -5,7 +5,6 @@ * Copyright (C) 2013, Texas Instruments, Incorporated */ -#include #include #include #include diff --git a/drivers/spi/uniphier_spi.c b/drivers/spi/uniphier_spi.c index 6402acbf14a..8f2c0fb4b8e 100644 --- a/drivers/spi/uniphier_spi.c +++ b/drivers/spi/uniphier_spi.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 94ddf4967ea..0e7fa3a4525 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -13,7 +13,6 @@ */ #include -#include #include #include #include diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index cb52c0f3072..b71b9a6fd6c 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -7,7 +7,6 @@ */ #include -#include #include #include #include diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index b3e0858eb94..ebcb5b6cc88 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -6,7 +6,6 @@ * Xilinx Zynq PS SPI controller driver (master mode only) */ -#include #include #include #include diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index a323994fb2d..61349a4da53 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY UCLASS_SPI -#include #include #include #include diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c index 244de69b359..b0d6226041e 100644 --- a/drivers/spmi/spmi-msm.c +++ b/drivers/spmi/spmi-msm.c @@ -7,7 +7,6 @@ * Loosely based on Little Kernel driver */ -#include #include #include #include diff --git a/drivers/spmi/spmi-sandbox.c b/drivers/spmi/spmi-sandbox.c index f6772946bca..992b08dd612 100644 --- a/drivers/spmi/spmi-sandbox.c +++ b/drivers/spmi/spmi-sandbox.c @@ -7,7 +7,6 @@ * (C) Copyright 2015 Mateusz Kulikowski */ -#include #include #include #include diff --git a/drivers/spmi/spmi-uclass.c b/drivers/spmi/spmi-uclass.c index 9d9f46a37d8..34fe8f6644c 100644 --- a/drivers/spmi/spmi-uclass.c +++ b/drivers/spmi/spmi-uclass.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY UCLASS_SPMI -#include #include #include #include diff --git a/drivers/sysinfo/gazerbeam.c b/drivers/sysinfo/gazerbeam.c index c1fae6ccf2a..a3c9d5354dd 100644 --- a/drivers/sysinfo/gazerbeam.c +++ b/drivers/sysinfo/gazerbeam.c @@ -4,7 +4,6 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ -#include #include #include #include diff --git a/drivers/sysinfo/gpio.c b/drivers/sysinfo/gpio.c index 82f90303bb7..aaca318419b 100644 --- a/drivers/sysinfo/gpio.c +++ b/drivers/sysinfo/gpio.c @@ -3,7 +3,6 @@ * Copyright (C) 2021 Sean Anderson */ -#include #include #include #include diff --git a/drivers/sysinfo/rcar3.c b/drivers/sysinfo/rcar3.c index 7b127986da7..37e2cccd9af 100644 --- a/drivers/sysinfo/rcar3.c +++ b/drivers/sysinfo/rcar3.c @@ -3,7 +3,6 @@ * Copyright (C) 2021 Marek Vasut */ -#include #include #include #include diff --git a/drivers/sysinfo/sandbox.c b/drivers/sysinfo/sandbox.c index d270a26aa43..d39720958f0 100644 --- a/drivers/sysinfo/sandbox.c +++ b/drivers/sysinfo/sandbox.c @@ -4,7 +4,6 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ -#include #include #include diff --git a/drivers/sysinfo/smbios.c b/drivers/sysinfo/smbios.c index 80ebd1921d8..a7ac8e3f072 100644 --- a/drivers/sysinfo/smbios.c +++ b/drivers/sysinfo/smbios.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include diff --git a/drivers/sysinfo/sysinfo-uclass.c b/drivers/sysinfo/sysinfo-uclass.c index 10194d0e14c..d77d1e3ee44 100644 --- a/drivers/sysinfo/sysinfo-uclass.c +++ b/drivers/sysinfo/sysinfo-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_SYSINFO -#include #include #include diff --git a/drivers/sysreset/poweroff_gpio.c b/drivers/sysreset/poweroff_gpio.c index ad04e4b1a85..d9220024f47 100644 --- a/drivers/sysreset/poweroff_gpio.c +++ b/drivers/sysreset/poweroff_gpio.c @@ -11,7 +11,6 @@ * Copyright (C) 2012 Jamie Lentin */ -#include #include #include #include diff --git a/drivers/sysreset/sysreset-ti-sci.c b/drivers/sysreset/sysreset-ti-sci.c index 0de132633a8..451fc5de735 100644 --- a/drivers/sysreset/sysreset-ti-sci.c +++ b/drivers/sysreset/sysreset-ti-sci.c @@ -6,7 +6,6 @@ * Andreas Dannenberg */ -#include #include #include #include diff --git a/drivers/sysreset/sysreset-uclass.c b/drivers/sysreset/sysreset-uclass.c index 6151b5fe03e..0abb4042e0f 100644 --- a/drivers/sysreset/sysreset-uclass.c +++ b/drivers/sysreset/sysreset-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_SYSRESET -#include #include #include #include diff --git a/drivers/sysreset/sysreset_ast.c b/drivers/sysreset/sysreset_ast.c index 92fad96871b..ef09440bbef 100644 --- a/drivers/sysreset/sysreset_ast.c +++ b/drivers/sysreset/sysreset_ast.c @@ -3,7 +3,6 @@ * (C) Copyright 2016 Google, Inc */ -#include #include #include #include diff --git a/drivers/sysreset/sysreset_at91.c b/drivers/sysreset/sysreset_at91.c index fc85f31ebf0..457042c7aae 100644 --- a/drivers/sysreset/sysreset_at91.c +++ b/drivers/sysreset/sysreset_at91.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/sysreset/sysreset_gpio.c b/drivers/sysreset/sysreset_gpio.c index de42b593542..47018844a51 100644 --- a/drivers/sysreset/sysreset_gpio.c +++ b/drivers/sysreset/sysreset_gpio.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Xilinx, Inc. - Michal Simek */ -#include #include #include #include diff --git a/drivers/sysreset/sysreset_microblaze.c b/drivers/sysreset/sysreset_microblaze.c index 83a7f77ac41..b81d82f046b 100644 --- a/drivers/sysreset/sysreset_microblaze.c +++ b/drivers/sysreset/sysreset_microblaze.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Xilinx, Inc. - Michal Simek */ -#include #include #include #include diff --git a/drivers/sysreset/sysreset_mpc83xx.c b/drivers/sysreset/sysreset_mpc83xx.c index ca48328f7b5..dca49299f77 100644 --- a/drivers/sysreset/sysreset_mpc83xx.c +++ b/drivers/sysreset/sysreset_mpc83xx.c @@ -4,7 +4,6 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ -#include #include #include #include diff --git a/drivers/sysreset/sysreset_octeon.c b/drivers/sysreset/sysreset_octeon.c index ebdea6ab66e..c16223720e5 100644 --- a/drivers/sysreset/sysreset_octeon.c +++ b/drivers/sysreset/sysreset_octeon.c @@ -3,7 +3,6 @@ * Copyright (C) 2020 Stefan Roese */ -#include #include #include #include diff --git a/drivers/sysreset/sysreset_psci.c b/drivers/sysreset/sysreset_psci.c index aa09d0b8827..89b4f2dcaec 100644 --- a/drivers/sysreset/sysreset_psci.c +++ b/drivers/sysreset/sysreset_psci.c @@ -3,7 +3,6 @@ * Copyright (C) 2017 Masahiro Yamada */ -#include #include #include #include diff --git a/drivers/sysreset/sysreset_resetctl.c b/drivers/sysreset/sysreset_resetctl.c index 25bd5c9a7ff..fbe3999b960 100644 --- a/drivers/sysreset/sysreset_resetctl.c +++ b/drivers/sysreset/sysreset_resetctl.c @@ -5,7 +5,6 @@ * Author: Weijie Gao */ -#include #include #include #include diff --git a/drivers/sysreset/sysreset_rockchip.c b/drivers/sysreset/sysreset_rockchip.c index f353f9b4c79..00308f9a33b 100644 --- a/drivers/sysreset/sysreset_rockchip.c +++ b/drivers/sysreset/sysreset_rockchip.c @@ -3,7 +3,6 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/drivers/sysreset/sysreset_sandbox.c b/drivers/sysreset/sysreset_sandbox.c index c12eda81d03..93179f90bbb 100644 --- a/drivers/sysreset/sysreset_sandbox.c +++ b/drivers/sysreset/sysreset_sandbox.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/sysreset/sysreset_sbi.c b/drivers/sysreset/sysreset_sbi.c index 5e8090d62bf..458191206b2 100644 --- a/drivers/sysreset/sysreset_sbi.c +++ b/drivers/sysreset/sysreset_sbi.c @@ -3,7 +3,6 @@ * Copyright 2021, Heinrich Schuchardt */ -#include #include #include #include diff --git a/drivers/sysreset/sysreset_socfpga.c b/drivers/sysreset/sysreset_socfpga.c index 9b62dd5eab0..a07b0f4fd55 100644 --- a/drivers/sysreset/sysreset_socfpga.c +++ b/drivers/sysreset/sysreset_socfpga.c @@ -4,7 +4,6 @@ * Simon Goldschmidt */ -#include #include #include #include diff --git a/drivers/sysreset/sysreset_socfpga_soc64.c b/drivers/sysreset/sysreset_socfpga_soc64.c index 9837aadf64b..6f44792abb0 100644 --- a/drivers/sysreset/sysreset_socfpga_soc64.c +++ b/drivers/sysreset/sysreset_socfpga_soc64.c @@ -4,7 +4,6 @@ * Simon Goldschmidt */ -#include #include #include #include diff --git a/drivers/sysreset/sysreset_sti.c b/drivers/sysreset/sysreset_sti.c index edd90aab061..110b7e23afa 100644 --- a/drivers/sysreset/sysreset_sti.c +++ b/drivers/sysreset/sysreset_sti.c @@ -4,7 +4,6 @@ * Author(s): Patrice Chotard, for STMicroelectronics. */ -#include #include #include #include diff --git a/drivers/sysreset/sysreset_syscon.c b/drivers/sysreset/sysreset_syscon.c index e468dac0e90..57144fa1e3b 100644 --- a/drivers/sysreset/sysreset_syscon.c +++ b/drivers/sysreset/sysreset_syscon.c @@ -7,7 +7,6 @@ * Author: Feng Kan */ -#include #include #include #include diff --git a/drivers/sysreset/sysreset_watchdog.c b/drivers/sysreset/sysreset_watchdog.c index 6db5aa75b54..49c061e0880 100644 --- a/drivers/sysreset/sysreset_watchdog.c +++ b/drivers/sysreset/sysreset_watchdog.c @@ -3,7 +3,6 @@ * Copyright (C) 2017 Álvaro Fernández Rojas */ -#include #include #include #include diff --git a/drivers/sysreset/sysreset_x86.c b/drivers/sysreset/sysreset_x86.c index dc772b5ff9e..c2f28c65280 100644 --- a/drivers/sysreset/sysreset_x86.c +++ b/drivers/sysreset/sysreset_x86.c @@ -5,7 +5,6 @@ * Generic reset driver for x86 processor */ -#include #include #include #include diff --git a/drivers/sysreset/sysreset_xtfpga.c b/drivers/sysreset/sysreset_xtfpga.c index 84fbc79016a..ab71ea11a0b 100644 --- a/drivers/sysreset/sysreset_xtfpga.c +++ b/drivers/sysreset/sysreset_xtfpga.c @@ -5,7 +5,7 @@ * (C) Copyright 2016 Cadence Design Systems Inc. */ -#include +#include #include #include #include diff --git a/drivers/thermal/imx_scu_thermal.c b/drivers/thermal/imx_scu_thermal.c index 3ec131cbc6e..fc2b0e227b2 100644 --- a/drivers/thermal/imx_scu_thermal.c +++ b/drivers/thermal/imx_scu_thermal.c @@ -4,7 +4,6 @@ */ #include -#include #include #include #include diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c index 2f6343e7a18..ea1fcc3dcb2 100644 --- a/drivers/thermal/imx_thermal.c +++ b/drivers/thermal/imx_thermal.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c index ea6c8329c0a..70d002aee25 100644 --- a/drivers/thermal/imx_tmu.c +++ b/drivers/thermal/imx_tmu.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/drivers/thermal/thermal-uclass.c b/drivers/thermal/thermal-uclass.c index 700df8af254..f0fe912e313 100644 --- a/drivers/thermal/thermal-uclass.c +++ b/drivers/thermal/thermal-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_THERMAL -#include #include #include #include diff --git a/drivers/thermal/thermal_sandbox.c b/drivers/thermal/thermal_sandbox.c index 7dc0d108b8c..9af0d0247cb 100644 --- a/drivers/thermal/thermal_sandbox.c +++ b/drivers/thermal/thermal_sandbox.c @@ -6,7 +6,6 @@ * Sandbox driver for the thermal uclass. */ -#include #include #include diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 60519c3b536..6b1de82ae38 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -50,6 +50,14 @@ config TIMER_EARLY use an early timer. These functions must be supported by your timer driver: timer_early_get_count() and timer_early_get_rate(). +config ADI_SC5XX_TIMER + bool "ADI ADSP-SC5xx Timer Support" + depends on TIMER && (SC57X || SC58X || SC59X || SC59X_64) + help + gptimer based timer support on ADI's ADSP-SC5xx platforms. Available + but not required on sc59x-64-based platforms (598 and similar). + Required on 32-bit platforms (sc57x, sc58x, sc594 and earlier). + config ALTERA_TIMER bool "Altera timer support" depends on TIMER diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index b93145e8d43..fb95c8899e3 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -3,6 +3,7 @@ # Copyright (C) 2015 Thomas Chou obj-y += timer-uclass.o +obj-$(CONFIG_ADI_SC5XX_TIMER) += adi_sc5xx_timer.o obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o obj-$(CONFIG_$(SPL_)ANDES_PLMT_TIMER) += andes_plmt_timer.o obj-$(CONFIG_ARC_TIMER) += arc_timer.o diff --git a/drivers/timer/adi_sc5xx_timer.c b/drivers/timer/adi_sc5xx_timer.c new file mode 100644 index 00000000000..11c098434a8 --- /dev/null +++ b/drivers/timer/adi_sc5xx_timer.c @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Converted to driver model by Nathan Barrett-Morrison + * + * Author: Greg Malysa + * Additional Contact: Nathan Barrett-Morrison + * + * dm timer implementation for ADI ADSP-SC5xx SoCs + * + */ + +#include +#include +#include +#include +#include +#include + +/* + * Timer Configuration Register Bits + */ +#define TIMER_OUT_DIS 0x0800 +#define TIMER_PULSE_HI 0x0080 +#define TIMER_MODE_PWM_CONT 0x000c + +#define __BFP(m) u16 m; u16 __pad_##m + +struct gptimer3 { + __BFP(config); + u32 counter; + u32 period; + u32 width; + u32 delay; +}; + +struct gptimer3_group_regs { + __BFP(run); + __BFP(enable); + __BFP(disable); + __BFP(stop_cfg); + __BFP(stop_cfg_set); + __BFP(stop_cfg_clr); + __BFP(data_imsk); + __BFP(stat_imsk); + __BFP(tr_msk); + __BFP(tr_ie); + __BFP(data_ilat); + __BFP(stat_ilat); + __BFP(err_status); + __BFP(bcast_per); + __BFP(bcast_wid); + __BFP(bcast_dly); +}; + +#define MAX_TIM_LOAD 0xFFFFFFFF + +struct adi_gptimer_priv { + struct gptimer3_group_regs __iomem *timer_group; + struct gptimer3 __iomem *timer_base; + u32 prev; + u64 upper; +}; + +static u64 adi_gptimer_get_count(struct udevice *udev) +{ + struct adi_gptimer_priv *priv = dev_get_priv(udev); + + u32 now = readl(&priv->timer_base->counter); + + if (now < priv->prev) + priv->upper += (1ull << 32); + + priv->prev = now; + + return (priv->upper + (u64)now); +} + +static const struct timer_ops adi_gptimer_ops = { + .get_count = adi_gptimer_get_count, +}; + +static int adi_gptimer_probe(struct udevice *udev) +{ + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(udev); + struct adi_gptimer_priv *priv = dev_get_priv(udev); + struct clk clk; + u16 imask; + int ret; + + priv->timer_group = dev_remap_addr_index(udev, 0); + priv->timer_base = dev_remap_addr_index(udev, 1); + priv->upper = 0; + priv->prev = 0; + + if (!priv->timer_group || !priv->timer_base) { + dev_err(udev, "Missing timer_group or timer_base reg entries\n"); + return -ENODEV; + } + + ret = clk_get_by_index(udev, 0, &clk); + if (ret < 0) { + dev_err(udev, "Missing clock reference for timer\n"); + return ret; + } + + ret = clk_enable(&clk); + if (ret) { + dev_err(udev, "Failed to enable clock\n"); + return ret; + } + + uc_priv->clock_rate = clk_get_rate(&clk); + + /* Enable timer */ + writew(TIMER_OUT_DIS | TIMER_MODE_PWM_CONT | TIMER_PULSE_HI, + &priv->timer_base->config); + writel(MAX_TIM_LOAD, &priv->timer_base->period); + writel(MAX_TIM_LOAD - 1, &priv->timer_base->width); + + /* We only use timer 0 in uboot */ + imask = readw(&priv->timer_group->data_imsk); + imask &= ~(1 << 0); + writew(imask, &priv->timer_group->data_imsk); + writew((1 << 0), &priv->timer_group->enable); + + return 0; +} + +static const struct udevice_id adi_gptimer_ids[] = { + { .compatible = "adi,sc5xx-gptimer" }, + { }, +}; + +U_BOOT_DRIVER(adi_gptimer) = { + .name = "adi_gptimer", + .id = UCLASS_TIMER, + .of_match = adi_gptimer_ids, + .priv_auto = sizeof(struct adi_gptimer_priv), + .probe = adi_gptimer_probe, + .ops = &adi_gptimer_ops, +}; diff --git a/drivers/timer/altera_timer.c b/drivers/timer/altera_timer.c index 040dc65f48a..ece246c23d2 100644 --- a/drivers/timer/altera_timer.c +++ b/drivers/timer/altera_timer.c @@ -7,7 +7,6 @@ * Scott McNutt */ -#include #include #include #include diff --git a/drivers/timer/andes_plmt_timer.c b/drivers/timer/andes_plmt_timer.c index 42dd4b62317..20baaf61307 100644 --- a/drivers/timer/andes_plmt_timer.c +++ b/drivers/timer/andes_plmt_timer.c @@ -8,7 +8,6 @@ * associated with timer tick. */ -#include #include #include #include diff --git a/drivers/timer/arc_timer.c b/drivers/timer/arc_timer.c index 497f8a04155..413bcc32f01 100644 --- a/drivers/timer/arc_timer.c +++ b/drivers/timer/arc_timer.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Synopsys, Inc. All rights reserved. */ -#include #include #include #include diff --git a/drivers/timer/arm_global_timer.c b/drivers/timer/arm_global_timer.c index 2e50d9fbc58..b8057929f99 100644 --- a/drivers/timer/arm_global_timer.c +++ b/drivers/timer/arm_global_timer.c @@ -6,7 +6,7 @@ * ARM Cortext A9 global timer driver */ -#include +#include #include #include #include diff --git a/drivers/timer/arm_twd_timer.c b/drivers/timer/arm_twd_timer.c index 40ccd165874..2b2f3591173 100644 --- a/drivers/timer/arm_twd_timer.c +++ b/drivers/timer/arm_twd_timer.c @@ -27,7 +27,6 @@ * Alex Zuepke */ -#include #include #include #include diff --git a/drivers/timer/ast_timer.c b/drivers/timer/ast_timer.c index 78adc96cc59..6601cab7b16 100644 --- a/drivers/timer/ast_timer.c +++ b/drivers/timer/ast_timer.c @@ -3,7 +3,6 @@ * Copyright 2016 Google Inc. */ -#include #include #include #include diff --git a/drivers/timer/atmel_pit_timer.c b/drivers/timer/atmel_pit_timer.c index 5cf46f224ab..0a367a5a7f4 100644 --- a/drivers/timer/atmel_pit_timer.c +++ b/drivers/timer/atmel_pit_timer.c @@ -4,7 +4,6 @@ * Wenyou.Yang */ -#include #include #include #include diff --git a/drivers/timer/atmel_tcb_timer.c b/drivers/timer/atmel_tcb_timer.c index 8c17987c7d7..3a328b2f6c7 100644 --- a/drivers/timer/atmel_tcb_timer.c +++ b/drivers/timer/atmel_tcb_timer.c @@ -5,7 +5,6 @@ * Author: Clément Léger */ -#include #include #include #include diff --git a/drivers/timer/cadence-ttc.c b/drivers/timer/cadence-ttc.c index 2eff45060ad..3cffb1bb88d 100644 --- a/drivers/timer/cadence-ttc.c +++ b/drivers/timer/cadence-ttc.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Xilinx, Inc. (Michal Simek) */ -#include #include #include #include diff --git a/drivers/timer/dw-apb-timer.c b/drivers/timer/dw-apb-timer.c index 0607f751ca7..77ccb98cb8d 100644 --- a/drivers/timer/dw-apb-timer.c +++ b/drivers/timer/dw-apb-timer.c @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut */ -#include #include #include #include diff --git a/drivers/timer/fttmr010_timer.c b/drivers/timer/fttmr010_timer.c index b6289e64610..c41bbfc1d57 100644 --- a/drivers/timer/fttmr010_timer.c +++ b/drivers/timer/fttmr010_timer.c @@ -5,7 +5,6 @@ * * 23/08/2022 Port to DM */ -#include #include #include #include diff --git a/drivers/timer/imx-gpt-timer.c b/drivers/timer/imx-gpt-timer.c index 9c3b64ae5b1..07b9fdb5e18 100644 --- a/drivers/timer/imx-gpt-timer.c +++ b/drivers/timer/imx-gpt-timer.c @@ -4,7 +4,7 @@ * Author(s): Giulio Benetti */ -#include +#include #include #include #include diff --git a/drivers/timer/mchp-pit64b-timer.c b/drivers/timer/mchp-pit64b-timer.c index c9806d7eeeb..1a5b2e6a0dc 100644 --- a/drivers/timer/mchp-pit64b-timer.c +++ b/drivers/timer/mchp-pit64b-timer.c @@ -7,7 +7,6 @@ * Author: Claudiu Beznea */ -#include #include #include #include diff --git a/drivers/timer/mpc83xx_timer.c b/drivers/timer/mpc83xx_timer.c index 7814cb6a5d6..9da74479aaa 100644 --- a/drivers/timer/mpc83xx_timer.c +++ b/drivers/timer/mpc83xx_timer.c @@ -4,7 +4,7 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ -#include +#include #include #include #include diff --git a/drivers/timer/mtk_timer.c b/drivers/timer/mtk_timer.c index 223e63f6c1a..8216c289837 100644 --- a/drivers/timer/mtk_timer.c +++ b/drivers/timer/mtk_timer.c @@ -7,7 +7,6 @@ */ #include -#include #include #include #include diff --git a/drivers/timer/nomadik-mtu-timer.c b/drivers/timer/nomadik-mtu-timer.c index 4d24de14ae6..9a05582c0d5 100644 --- a/drivers/timer/nomadik-mtu-timer.c +++ b/drivers/timer/nomadik-mtu-timer.c @@ -12,7 +12,6 @@ * Copyright (C) 2010 Linus Walleij for ST-Ericsson */ -#include #include #include #include diff --git a/drivers/timer/npcm-timer.c b/drivers/timer/npcm-timer.c index 4562a6f2311..9463fd29ce8 100644 --- a/drivers/timer/npcm-timer.c +++ b/drivers/timer/npcm-timer.c @@ -3,7 +3,6 @@ * Copyright (c) 2022 Nuvoton Technology Corp. */ -#include #include #include #include diff --git a/drivers/timer/omap-timer.c b/drivers/timer/omap-timer.c index 9b6d97dae67..fda6356fdba 100644 --- a/drivers/timer/omap-timer.c +++ b/drivers/timer/omap-timer.c @@ -5,7 +5,6 @@ * Copyright (C) 2015, Texas Instruments, Incorporated */ -#include #include #include #include diff --git a/drivers/timer/orion-timer.c b/drivers/timer/orion-timer.c index 9cab27f2e48..821b681a232 100644 --- a/drivers/timer/orion-timer.c +++ b/drivers/timer/orion-timer.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ #include -#include +#include #include #include #include diff --git a/drivers/timer/ostm_timer.c b/drivers/timer/ostm_timer.c index 3bf0d4647b5..314f956cdfb 100644 --- a/drivers/timer/ostm_timer.c +++ b/drivers/timer/ostm_timer.c @@ -5,7 +5,6 @@ * Copyright (C) 2019 Marek Vasut */ -#include #include #include #include diff --git a/drivers/timer/riscv_aclint_timer.c b/drivers/timer/riscv_aclint_timer.c index 73fb8791285..35da1ea2fd2 100644 --- a/drivers/timer/riscv_aclint_timer.c +++ b/drivers/timer/riscv_aclint_timer.c @@ -4,7 +4,7 @@ * Copyright (C) 2018, Bin Meng */ -#include +#include #include #include #include diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c index 169c03dcb5c..1f4980ceb38 100644 --- a/drivers/timer/riscv_timer.c +++ b/drivers/timer/riscv_timer.c @@ -10,7 +10,7 @@ * This driver provides generic timer support for S-mode U-Boot. */ -#include +#include #include #include #include diff --git a/drivers/timer/rockchip_timer.c b/drivers/timer/rockchip_timer.c index e66c49aa6bb..96c010f4dcc 100644 --- a/drivers/timer/rockchip_timer.c +++ b/drivers/timer/rockchip_timer.c @@ -3,7 +3,6 @@ * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH */ -#include #include #include #include diff --git a/drivers/timer/sandbox_timer.c b/drivers/timer/sandbox_timer.c index 1da7e0c3a76..e8b54a02965 100644 --- a/drivers/timer/sandbox_timer.c +++ b/drivers/timer/sandbox_timer.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Thomas Chou */ -#include #include #include #include diff --git a/drivers/timer/sp804_timer.c b/drivers/timer/sp804_timer.c index 8fd4afb15a5..a254e295cbf 100644 --- a/drivers/timer/sp804_timer.c +++ b/drivers/timer/sp804_timer.c @@ -4,7 +4,6 @@ * Copyright (C) 2022 Arm Ltd. */ -#include #include #include #include diff --git a/drivers/timer/starfive-timer.c b/drivers/timer/starfive-timer.c index 6ac7d7f1d0e..6b79c8858b5 100644 --- a/drivers/timer/starfive-timer.c +++ b/drivers/timer/starfive-timer.c @@ -4,7 +4,6 @@ * Author: Kuan Lim Lee */ -#include #include #include #include diff --git a/drivers/timer/stm32_timer.c b/drivers/timer/stm32_timer.c index 1213a14ef19..1dc21c5c1be 100644 --- a/drivers/timer/stm32_timer.c +++ b/drivers/timer/stm32_timer.c @@ -6,7 +6,7 @@ #define LOG_CATEGORY UCLASS_TIMER -#include +#include #include #include #include diff --git a/drivers/timer/tegra-timer.c b/drivers/timer/tegra-timer.c index a867c649c3a..3545424889d 100644 --- a/drivers/timer/tegra-timer.c +++ b/drivers/timer/tegra-timer.c @@ -3,7 +3,6 @@ * Copyright (C) 2022 Svyatoslav Ryhel */ -#include #include #include #include diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c index 60ff65529ab..8305f06d318 100644 --- a/drivers/timer/timer-uclass.c +++ b/drivers/timer/timer-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_TIMER -#include #include #include #include diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c index f86a0b86921..80c084f380d 100644 --- a/drivers/timer/tsc_timer.c +++ b/drivers/timer/tsc_timer.c @@ -6,7 +6,6 @@ * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c */ -#include #include #include #include diff --git a/drivers/timer/xilinx-timer.c b/drivers/timer/xilinx-timer.c index 172fd9f9296..54148aa1689 100644 --- a/drivers/timer/xilinx-timer.c +++ b/drivers/timer/xilinx-timer.c @@ -7,7 +7,6 @@ * Michal SIMEK */ -#include #include #include #include diff --git a/drivers/tpm/cr50_i2c.c b/drivers/tpm/cr50_i2c.c index acf4c7859a9..08ec179346e 100644 --- a/drivers/tpm/cr50_i2c.c +++ b/drivers/tpm/cr50_i2c.c @@ -7,12 +7,12 @@ #define LOG_CATEGORY UCLASS_TPM -#include #include #include #include #include #include +#include #include #include #include diff --git a/drivers/tpm/sandbox_common.c b/drivers/tpm/sandbox_common.c index 7e0b2502e35..596e0156389 100644 --- a/drivers/tpm/sandbox_common.c +++ b/drivers/tpm/sandbox_common.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY UCLASS_TPM -#include #include #include #include diff --git a/drivers/tpm/tpm-uclass.c b/drivers/tpm/tpm-uclass.c index b2286f7e7ed..0fade2dcc0a 100644 --- a/drivers/tpm/tpm-uclass.c +++ b/drivers/tpm/tpm-uclass.c @@ -6,9 +6,9 @@ #define LOG_CATEGORY UCLASS_TPM -#include #include #include +#include #include #include #include diff --git a/drivers/tpm/tpm2_ftpm_tee.c b/drivers/tpm/tpm2_ftpm_tee.c index c61ff2c2af6..f2ced50c4eb 100644 --- a/drivers/tpm/tpm2_ftpm_tee.c +++ b/drivers/tpm/tpm2_ftpm_tee.c @@ -13,7 +13,6 @@ * https://github.com/microsoft/ms-tpm-20-ref/tree/master/Samples/ARM32-FirmwareTPM/optee_ta/fTPM */ -#include #include #include #include diff --git a/drivers/tpm/tpm2_tis_core.c b/drivers/tpm/tpm2_tis_core.c index 81b9210056d..680a6409433 100644 --- a/drivers/tpm/tpm2_tis_core.c +++ b/drivers/tpm/tpm2_tis_core.c @@ -5,8 +5,8 @@ * Based on the Linux TIS core interface and U-Boot original SPI TPM driver */ -#include #include +#include #include #include #include diff --git a/drivers/tpm/tpm2_tis_i2c.c b/drivers/tpm/tpm2_tis_i2c.c index 99d1cf218da..93efccc7757 100644 --- a/drivers/tpm/tpm2_tis_i2c.c +++ b/drivers/tpm/tpm2_tis_i2c.c @@ -3,7 +3,6 @@ * Copyright 2022 IBM Corp. */ -#include #include #include #include diff --git a/drivers/tpm/tpm2_tis_mmio.c b/drivers/tpm/tpm2_tis_mmio.c index a646ce41ff4..dee5503c055 100644 --- a/drivers/tpm/tpm2_tis_mmio.c +++ b/drivers/tpm/tpm2_tis_mmio.c @@ -5,7 +5,6 @@ * Specifications at www.trustedcomputinggroup.org */ -#include #include #include #include diff --git a/drivers/tpm/tpm2_tis_sandbox.c b/drivers/tpm/tpm2_tis_sandbox.c index d15a28d9fc8..50e308e7116 100644 --- a/drivers/tpm/tpm2_tis_sandbox.c +++ b/drivers/tpm/tpm2_tis_sandbox.c @@ -4,7 +4,6 @@ * Author: Miquel Raynal */ -#include #include #include #include diff --git a/drivers/tpm/tpm2_tis_spi.c b/drivers/tpm/tpm2_tis_spi.c index de9cf8f21e0..28079b5039a 100644 --- a/drivers/tpm/tpm2_tis_spi.c +++ b/drivers/tpm/tpm2_tis_spi.c @@ -13,11 +13,11 @@ * It is based on the U-Boot driver tpm_tis_infineon_i2c.c. */ -#include #include #include #include #include +#include #include #include #include diff --git a/drivers/tpm/tpm_atmel_twi.c b/drivers/tpm/tpm_atmel_twi.c index fd2a45d34b0..05dd66525c7 100644 --- a/drivers/tpm/tpm_atmel_twi.c +++ b/drivers/tpm/tpm_atmel_twi.c @@ -5,11 +5,11 @@ * Written by Dirk Eibach */ -#include #include #include #include #include +#include #include #include diff --git a/drivers/tpm/tpm_tis_infineon.c b/drivers/tpm/tpm_tis_infineon.c index 16f4af0e331..e2f6238cbc7 100644 --- a/drivers/tpm/tpm_tis_infineon.c +++ b/drivers/tpm/tpm_tis_infineon.c @@ -19,11 +19,11 @@ * Version: 2.1.1 */ -#include #include #include #include #include +#include #include #include #include diff --git a/drivers/tpm/tpm_tis_lpc.c b/drivers/tpm/tpm_tis_lpc.c index 13a133d58eb..dec7acb0c7b 100644 --- a/drivers/tpm/tpm_tis_lpc.c +++ b/drivers/tpm/tpm_tis_lpc.c @@ -12,7 +12,6 @@ * slb9635), so this driver provides access to locality 0 only. */ -#include #include #include #include diff --git a/drivers/tpm/tpm_tis_sandbox.c b/drivers/tpm/tpm_tis_sandbox.c index 7350e1c4d52..2bc7dc87ed3 100644 --- a/drivers/tpm/tpm_tis_sandbox.c +++ b/drivers/tpm/tpm_tis_sandbox.c @@ -3,7 +3,6 @@ * Copyright (c) 2013 Google, Inc */ -#include #include #include #include diff --git a/drivers/tpm/tpm_tis_st33zp24_i2c.c b/drivers/tpm/tpm_tis_st33zp24_i2c.c index e0eeabb9337..1a265b28b22 100644 --- a/drivers/tpm/tpm_tis_st33zp24_i2c.c +++ b/drivers/tpm/tpm_tis_st33zp24_i2c.c @@ -12,7 +12,6 @@ * STMicroelectronics Protocol Stack Specification version 1.2.0. */ -#include #include #include #include diff --git a/drivers/tpm/tpm_tis_st33zp24_spi.c b/drivers/tpm/tpm_tis_st33zp24_spi.c index f0de8a65b09..2cf690328d8 100644 --- a/drivers/tpm/tpm_tis_st33zp24_spi.c +++ b/drivers/tpm/tpm_tis_st33zp24_spi.c @@ -12,7 +12,6 @@ * STMicroelectronics Protocol Stack Specification version 1.2.0. */ -#include #include #include #include diff --git a/drivers/ufs/cdns-platform.c b/drivers/ufs/cdns-platform.c index d1f346937c5..510a6a6aa5d 100644 --- a/drivers/ufs/cdns-platform.c +++ b/drivers/ufs/cdns-platform.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/drivers/ufs/ti-j721e-ufs.c b/drivers/ufs/ti-j721e-ufs.c index 1860e0dca29..c5c08610ffd 100644 --- a/drivers/ufs/ti-j721e-ufs.c +++ b/drivers/ufs/ti-j721e-ufs.c @@ -5,7 +5,6 @@ #include #include -#include #include #include #include diff --git a/drivers/ufs/ufs-pci.c b/drivers/ufs/ufs-pci.c index ad41358727a..871f3f50f5c 100644 --- a/drivers/ufs/ufs-pci.c +++ b/drivers/ufs/ufs-pci.c @@ -4,7 +4,6 @@ * Author: Bin Meng */ -#include #include #include #include diff --git a/drivers/ufs/ufs-uclass.c b/drivers/ufs/ufs-uclass.c index 92fcdf4e6cb..334bfcfa06a 100644 --- a/drivers/ufs/ufs-uclass.c +++ b/drivers/ufs/ufs-uclass.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY UCLASS_UFS -#include #include "ufs.h" #include diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c index e4400f319a7..be64bf971f1 100644 --- a/drivers/ufs/ufs.c +++ b/drivers/ufs/ufs.c @@ -10,7 +10,6 @@ #include #include -#include #include #include #include diff --git a/drivers/ufs/ufs.h b/drivers/ufs/ufs.h index 816a5ce0caf..43042c294bb 100644 --- a/drivers/ufs/ufs.h +++ b/drivers/ufs/ufs.h @@ -2,6 +2,7 @@ #ifndef __UFS_H #define __UFS_H +#include #include "unipro.h" struct udevice; diff --git a/drivers/usb/cdns3/cdns3-ti.c b/drivers/usb/cdns3/cdns3-ti.c index 2e44aadea47..ac072260c30 100644 --- a/drivers/usb/cdns3/cdns3-ti.c +++ b/drivers/usb/cdns3/cdns3-ti.c @@ -5,7 +5,6 @@ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com */ -#include #include #include #include diff --git a/drivers/usb/cdns3/core.c b/drivers/usb/cdns3/core.c index 12a741c6ea7..b4e931646b8 100644 --- a/drivers/usb/cdns3/core.c +++ b/drivers/usb/cdns3/core.c @@ -11,7 +11,6 @@ * Roger Quadros */ -#include #include #include #include diff --git a/drivers/usb/common/common.c b/drivers/usb/common/common.c index 7137a569d97..13e9a61072a 100644 --- a/drivers/usb/common/common.c +++ b/drivers/usb/common/common.c @@ -6,7 +6,6 @@ * Texas Instruments Incorporated, */ -#include #include #include #include diff --git a/drivers/usb/common/fsl-dt-fixup.c b/drivers/usb/common/fsl-dt-fixup.c index 00b8cd368b1..6a68bd76c27 100644 --- a/drivers/usb/common/fsl-dt-fixup.c +++ b/drivers/usb/common/fsl-dt-fixup.c @@ -7,7 +7,6 @@ * Author: Tor Krill tor@excito.com */ -#include #include #include #include diff --git a/drivers/usb/common/fsl-errata.c b/drivers/usb/common/fsl-errata.c index 9eb1d230672..89ae73f2ba4 100644 --- a/drivers/usb/common/fsl-errata.c +++ b/drivers/usb/common/fsl-errata.c @@ -5,7 +5,6 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 96e850b7170..c443d56746d 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -13,7 +13,6 @@ * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA */ -#include #include #include #include diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 7a00529a2a8..8db678eb85d 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -7,7 +7,6 @@ * Based on dwc3-omap.c. */ -#include #include #include #include diff --git a/drivers/usb/dwc3/dwc3-layerscape.c b/drivers/usb/dwc3/dwc3-layerscape.c index c32df2396d7..ff83bf71e89 100644 --- a/drivers/usb/dwc3/dwc3-layerscape.c +++ b/drivers/usb/dwc3/dwc3-layerscape.c @@ -7,7 +7,6 @@ * Based on dwc3-generic.c. */ -#include #include #include #include diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c index 1a3e9350c46..21e4f637bb1 100644 --- a/drivers/usb/dwc3/dwc3-meson-g12a.c +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c @@ -6,7 +6,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/drivers/usb/dwc3/dwc3-meson-gxl.c b/drivers/usb/dwc3/dwc3-meson-gxl.c index 2ce915701a8..3e693c5ff31 100644 --- a/drivers/usb/dwc3/dwc3-meson-gxl.c +++ b/drivers/usb/dwc3/dwc3-meson-gxl.c @@ -7,7 +7,6 @@ */ #define DEBUG -#include #include #include #include diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c index 53c4d4826b4..4b219c35eb3 100644 --- a/drivers/usb/dwc3/dwc3-omap.c +++ b/drivers/usb/dwc3/dwc3-omap.c @@ -13,7 +13,6 @@ * commit 7ee2566ff5 : usb: dwc3: dwc3-omap: get rid of ->prepare()/->complete() */ -#include #include #include #include diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c index 1133cf82b1a..117d38a0340 100644 --- a/drivers/usb/dwc3/ep0.c +++ b/drivers/usb/dwc3/ep0.c @@ -12,7 +12,6 @@ * * commit c00552ebaf : Merge 3.18-rc7 into usb-next */ -#include #include #include #include diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 39c19d94de1..fab32575647 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -13,7 +13,6 @@ * commit 8e74475b0e : usb: dwc3: gadget: use udc-core's reset notifier */ -#include #include #include #include diff --git a/drivers/usb/dwc3/samsung_usb_phy.c b/drivers/usb/dwc3/samsung_usb_phy.c index abbd4136890..0a771308163 100644 --- a/drivers/usb/dwc3/samsung_usb_phy.c +++ b/drivers/usb/dwc3/samsung_usb_phy.c @@ -7,7 +7,7 @@ * Author: Joonyoung Shim */ -#include +#include #include #include #include diff --git a/drivers/usb/dwc3/ti_usb_phy.c b/drivers/usb/dwc3/ti_usb_phy.c index 8ae130860f7..f0ecdea958a 100644 --- a/drivers/usb/dwc3/ti_usb_phy.c +++ b/drivers/usb/dwc3/ti_usb_phy.c @@ -16,7 +16,6 @@ * and remove" for phy-omap-usb2.c */ -#include #include #include #include diff --git a/drivers/usb/emul/sandbox_flash.c b/drivers/usb/emul/sandbox_flash.c index 7c5c1ab3de7..24420e3d51e 100644 --- a/drivers/usb/emul/sandbox_flash.c +++ b/drivers/usb/emul/sandbox_flash.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_USB -#include #include #include #include diff --git a/drivers/usb/emul/sandbox_hub.c b/drivers/usb/emul/sandbox_hub.c index 084cc16cc68..3b3e59f978f 100644 --- a/drivers/usb/emul/sandbox_hub.c +++ b/drivers/usb/emul/sandbox_hub.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/usb/emul/sandbox_keyb.c b/drivers/usb/emul/sandbox_keyb.c index 5ec1e98e4ed..db769883ba3 100644 --- a/drivers/usb/emul/sandbox_keyb.c +++ b/drivers/usb/emul/sandbox_keyb.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/usb/emul/usb-emul-uclass.c b/drivers/usb/emul/usb-emul-uclass.c index b31dc950e3a..cdc18d6cbb9 100644 --- a/drivers/usb/emul/usb-emul-uclass.c +++ b/drivers/usb/emul/usb-emul-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_USB_EMUL -#include #include #include #include diff --git a/drivers/usb/eth/asix.c b/drivers/usb/eth/asix.c index 26dd312b7d0..c5a01ec922b 100644 --- a/drivers/usb/eth/asix.c +++ b/drivers/usb/eth/asix.c @@ -5,7 +5,6 @@ * Patched for AX88772B by Antmicro Ltd */ -#include #include #include #include diff --git a/drivers/usb/eth/asix88179.c b/drivers/usb/eth/asix88179.c index 2e737e60668..7bfd285b3aa 100644 --- a/drivers/usb/eth/asix88179.c +++ b/drivers/usb/eth/asix88179.c @@ -5,7 +5,6 @@ * from the Linux AX88179_178a driver */ -#include #include #include #include diff --git a/drivers/usb/eth/mcs7830.c b/drivers/usb/eth/mcs7830.c index d94204f22d5..199fb7a5d08 100644 --- a/drivers/usb/eth/mcs7830.c +++ b/drivers/usb/eth/mcs7830.c @@ -9,7 +9,6 @@ * MOSCHIP MCS7830 based (7730/7830/7832) USB 2.0 Ethernet Devices */ -#include #include #include #include diff --git a/drivers/usb/eth/r8152.c b/drivers/usb/eth/r8152.c index 3c866f4f1e2..e3f20e08c33 100644 --- a/drivers/usb/eth/r8152.c +++ b/drivers/usb/eth/r8152.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/drivers/usb/eth/r8152_fw.c b/drivers/usb/eth/r8152_fw.c index a41abed3069..3159f301060 100644 --- a/drivers/usb/eth/r8152_fw.c +++ b/drivers/usb/eth/r8152_fw.c @@ -3,7 +3,6 @@ * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved. * */ -#include #include #include #include diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c index de6586e6263..b4fcb2c2bb0 100644 --- a/drivers/usb/eth/smsc95xx.c +++ b/drivers/usb/eth/smsc95xx.c @@ -6,7 +6,6 @@ * Copyright (C) 2007-2008 SMSC (Steve Glendinning) */ -#include #include #include #include diff --git a/drivers/usb/eth/usb_ether.c b/drivers/usb/eth/usb_ether.c index 2e9af54fd63..8bba3e0974e 100644 --- a/drivers/usb/eth/usb_ether.c +++ b/drivers/usb/eth/usb_ether.c @@ -3,7 +3,6 @@ * Copyright (c) 2011 The Chromium OS Authors. */ -#include #include #include #include diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c index e573a03477b..86b2cbf3f6a 100644 --- a/drivers/usb/gadget/at91_udc.c +++ b/drivers/usb/gadget/at91_udc.c @@ -13,7 +13,6 @@ #undef VERBOSE_DEBUG #undef PACKET_TRACE -#include #include #include #include diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c index 4c420747b0b..f99553df8d4 100644 --- a/drivers/usb/gadget/atmel_usba_udc.c +++ b/drivers/usb/gadget/atmel_usba_udc.c @@ -7,7 +7,6 @@ * Bo Shen */ -#include #include #include #include diff --git a/drivers/usb/gadget/bcm_udc_otg_phy.c b/drivers/usb/gadget/bcm_udc_otg_phy.c index c89cd57c253..9875191091c 100644 --- a/drivers/usb/gadget/bcm_udc_otg_phy.c +++ b/drivers/usb/gadget/bcm_udc_otg_phy.c @@ -4,7 +4,6 @@ */ #include -#include #include #include #include diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 750d4714879..bbe03cfff1f 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -7,7 +7,6 @@ * Murray.Jensen@cmst.csiro.au, 27-Jan-01. */ -#include #include #include #include diff --git a/drivers/usb/gadget/config.c b/drivers/usb/gadget/config.c index e96782644f3..1363ef9e73d 100644 --- a/drivers/usb/gadget/config.c +++ b/drivers/usb/gadget/config.c @@ -8,7 +8,6 @@ * Remy Bohmer */ -#include #include #include #include diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c index 27082f5152c..6bd395a6235 100644 --- a/drivers/usb/gadget/dwc2_udc_otg.c +++ b/drivers/usb/gadget/dwc2_udc_otg.c @@ -17,7 +17,6 @@ * Lukasz Majewski */ #undef DEBUG -#include #include #include #include diff --git a/drivers/usb/gadget/dwc2_udc_otg_phy.c b/drivers/usb/gadget/dwc2_udc_otg_phy.c index 7f8e9564b9e..c7eea7b3442 100644 --- a/drivers/usb/gadget/dwc2_udc_otg_phy.c +++ b/drivers/usb/gadget/dwc2_udc_otg_phy.c @@ -17,7 +17,6 @@ * Lukasz Majewski */ -#include #include #include #include diff --git a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c index 1c34b753511..16b2a03f9e4 100644 --- a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c +++ b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c @@ -17,7 +17,6 @@ * Lukasz Majewski */ -#include #include #include #include diff --git a/drivers/usb/gadget/ep0.c b/drivers/usb/gadget/ep0.c index c256cc31fbd..9d08640ff23 100644 --- a/drivers/usb/gadget/ep0.c +++ b/drivers/usb/gadget/ep0.c @@ -36,7 +36,6 @@ * XXX */ -#include #include #include diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c index bb0d2971d06..0a70035ce04 100644 --- a/drivers/usb/gadget/epautoconf.c +++ b/drivers/usb/gadget/epautoconf.c @@ -8,7 +8,6 @@ * Remy Bohmer */ -#include #include #include #include diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c index 36618f0bdf3..b8b29d399b1 100644 --- a/drivers/usb/gadget/ether.c +++ b/drivers/usb/gadget/ether.c @@ -7,7 +7,6 @@ * Copyright (C) 2008 Nokia Corporation */ -#include #include #include #include diff --git a/drivers/usb/gadget/f_acm.c b/drivers/usb/gadget/f_acm.c index ba216128ab2..f18c6a0a761 100644 --- a/drivers/usb/gadget/f_acm.c +++ b/drivers/usb/gadget/f_acm.c @@ -10,7 +10,6 @@ */ #include -#include #include #include #include diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c index 44877df4ec6..ca8b36e077b 100644 --- a/drivers/usb/gadget/f_dfu.c +++ b/drivers/usb/gadget/f_dfu.c @@ -16,7 +16,6 @@ #include #include -#include #include #include diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index 09e740cc962..8df0e3f331d 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -11,7 +11,6 @@ */ #include #include -#include #include #include #include diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c index ef90c7ec7fb..89a96dbb7a7 100644 --- a/drivers/usb/gadget/f_mass_storage.c +++ b/drivers/usb/gadget/f_mass_storage.c @@ -244,7 +244,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/usb/gadget/f_rockusb.c b/drivers/usb/gadget/f_rockusb.c index 98a7ffa2a75..d679cdae97c 100644 --- a/drivers/usb/gadget/f_rockusb.c +++ b/drivers/usb/gadget/f_rockusb.c @@ -6,7 +6,6 @@ */ #include #include -#include #include #include #include diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c index ca2760c00d0..89496917a61 100644 --- a/drivers/usb/gadget/f_sdp.c +++ b/drivers/usb/gadget/f_sdp.c @@ -17,7 +17,6 @@ */ #include -#include #include #include #include diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c index 0e7529dcdbb..54372118348 100644 --- a/drivers/usb/gadget/f_thor.c +++ b/drivers/usb/gadget/f_thor.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c index afb7b74f305..b5b5f5d8c11 100644 --- a/drivers/usb/gadget/g_dnl.c +++ b/drivers/usb/gadget/g_dnl.c @@ -6,7 +6,6 @@ * Lukasz Majewski */ -#include #include #include diff --git a/drivers/usb/gadget/max3420_udc.c b/drivers/usb/gadget/max3420_udc.c index fa655c98dcc..5a227c0ffd9 100644 --- a/drivers/usb/gadget/max3420_udc.c +++ b/drivers/usb/gadget/max3420_udc.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/drivers/usb/gadget/rndis.c b/drivers/usb/gadget/rndis.c index e7276ccd37a..5e6e5a054ca 100644 --- a/drivers/usb/gadget/rndis.c +++ b/drivers/usb/gadget/rndis.c @@ -18,7 +18,6 @@ * updates to merge with Linux 2.6, better match RNDIS spec */ -#include #include #include #include diff --git a/drivers/usb/gadget/udc/udc-core.c b/drivers/usb/gadget/udc/udc-core.c index ba658d92296..6bb419ae2ab 100644 --- a/drivers/usb/gadget/udc/udc-core.c +++ b/drivers/usb/gadget/udc/udc-core.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/usb/gadget/udc/udc-uclass.c b/drivers/usb/gadget/udc/udc-uclass.c index 30ee1cab066..5dc23a55bb5 100644 --- a/drivers/usb/gadget/udc/udc-uclass.c +++ b/drivers/usb/gadget/udc/udc-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_USB_GADGET_GENERIC -#include #include #include #include diff --git a/drivers/usb/gadget/usbstring.c b/drivers/usb/gadget/usbstring.c index e2464ad923f..4617a95bd0a 100644 --- a/drivers/usb/gadget/usbstring.c +++ b/drivers/usb/gadget/usbstring.c @@ -6,7 +6,6 @@ * Remy Bohmer */ -#include #include #include #include diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c index 637eb2dd06f..a9dbb85f4e6 100644 --- a/drivers/usb/host/dwc2.c +++ b/drivers/usb/host/dwc2.c @@ -4,7 +4,6 @@ * Copyright (C) 2014 Marek Vasut */ -#include #include #include #include diff --git a/drivers/usb/host/dwc3-of-simple.c b/drivers/usb/host/dwc3-of-simple.c index f9df59d2e5d..d52e7d22d1a 100644 --- a/drivers/usb/host/dwc3-of-simple.c +++ b/drivers/usb/host/dwc3-of-simple.c @@ -10,7 +10,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/drivers/usb/host/dwc3-sti-glue.c b/drivers/usb/host/dwc3-sti-glue.c index 4a3ab611127..3e6834e38e3 100644 --- a/drivers/usb/host/dwc3-sti-glue.c +++ b/drivers/usb/host/dwc3-sti-glue.c @@ -6,7 +6,6 @@ * Author(s): Patrice Chotard, for STMicroelectronics. */ -#include #include #include #include diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c index c6d50fd4551..ee751224463 100644 --- a/drivers/usb/host/ehci-atmel.c +++ b/drivers/usb/host/ehci-atmel.c @@ -5,7 +5,6 @@ * Written-by: Bo Shen */ -#include #include #include #include diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c index c1cdd4b0889..1e4a5a0b6f6 100644 --- a/drivers/usb/host/ehci-exynos.c +++ b/drivers/usb/host/ehci-exynos.c @@ -6,7 +6,6 @@ * Vivek Gautam */ -#include #include #include #include diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 0569dd54fff..ee3eb065b14 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -7,7 +7,6 @@ * Author: Tor Krill tor@excito.com */ -#include #include #include #include diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c index 936e30438d9..23c3ed25554 100644 --- a/drivers/usb/host/ehci-generic.c +++ b/drivers/usb/host/ehci-generic.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Alexey Brodkin */ -#include #include #include #include diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 9839aa17492..7d5519c65a9 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -6,7 +6,6 @@ * * All rights reserved. */ -#include #include #include #include diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c index 6093c8fb0b6..ca0ab57d49c 100644 --- a/drivers/usb/host/ehci-marvell.c +++ b/drivers/usb/host/ehci-marvell.c @@ -5,7 +5,6 @@ * Written-by: Prafulla Wadaskar */ -#include #include #include #include diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c index 98fe7bc3bcb..a081f71b187 100644 --- a/drivers/usb/host/ehci-msm.c +++ b/drivers/usb/host/ehci-msm.c @@ -7,7 +7,6 @@ * Based on Linux driver */ -#include #include #include #include diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c index c11279867c7..fb912654097 100644 --- a/drivers/usb/host/ehci-mx5.c +++ b/drivers/usb/host/ehci-mx5.c @@ -4,7 +4,6 @@ * Copyright (C) 2010 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index a35fcca43a2..31cd8a50f4a 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -4,7 +4,6 @@ * Copyright (C) 2010 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/drivers/usb/host/ehci-mxs.c b/drivers/usb/host/ehci-mxs.c index ddf7cc2d00a..95af5c9254c 100644 --- a/drivers/usb/host/ehci-mxs.c +++ b/drivers/usb/host/ehci-mxs.c @@ -6,7 +6,6 @@ * on behalf of DENX Software Engineering GmbH */ -#include #include #include #include diff --git a/drivers/usb/host/ehci-npcm.c b/drivers/usb/host/ehci-npcm.c index 357a5614edb..d2a9965b4b4 100644 --- a/drivers/usb/host/ehci-npcm.c +++ b/drivers/usb/host/ehci-npcm.c @@ -3,7 +3,6 @@ * Copyright (c) 2021 Nuvoton Technology Corp. */ -#include #include #include #include diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c index 765336a3c42..a95fcad0213 100644 --- a/drivers/usb/host/ehci-omap.c +++ b/drivers/usb/host/ehci-omap.c @@ -10,8 +10,8 @@ * */ -#include #include +#include #include #include #include diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index e98ab312618..572686580cd 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c @@ -4,7 +4,6 @@ * All rights reserved. */ -#include #include #include #include diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index 2cf16256703..343893b9f19 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -5,7 +5,6 @@ * Copyright (c) 2013 Lucas Stach */ -#include #include #include #include diff --git a/drivers/usb/host/ehci-vf.c b/drivers/usb/host/ehci-vf.c index 648e136447d..5afe28ea303 100644 --- a/drivers/usb/host/ehci-vf.c +++ b/drivers/usb/host/ehci-vf.c @@ -6,7 +6,6 @@ * Based on ehci-mx6 driver */ -#include #include #include #include diff --git a/drivers/usb/host/ehci-zynq.c b/drivers/usb/host/ehci-zynq.c index f7e458cb15a..dfaff5c60f4 100644 --- a/drivers/usb/host/ehci-zynq.c +++ b/drivers/usb/host/ehci-zynq.c @@ -5,7 +5,6 @@ * USB Low level initialization(Specific to zynq) */ -#include #include #include #include diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c index 9b955c1bd67..b170f26e6c6 100644 --- a/drivers/usb/host/ohci-at91.c +++ b/drivers/usb/host/ohci-at91.c @@ -4,7 +4,6 @@ * DENX Software Engineering */ -#include #include int usb_cpu_init(void) diff --git a/drivers/usb/host/ohci-da8xx.c b/drivers/usb/host/ohci-da8xx.c index d3d73d23844..d321d147c2f 100644 --- a/drivers/usb/host/ohci-da8xx.c +++ b/drivers/usb/host/ohci-da8xx.c @@ -3,7 +3,6 @@ * Copyright (C) 2012 Sughosh Ganu */ -#include #include #include #include diff --git a/drivers/usb/host/ohci-generic.c b/drivers/usb/host/ohci-generic.c index ceed1911a95..f1325cd4953 100644 --- a/drivers/usb/host/ohci-generic.c +++ b/drivers/usb/host/ohci-generic.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Alexey Brodkin */ -#include #include #include #include diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 3f4418198cc..c020d13c43d 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -27,7 +27,7 @@ * to activate workaround for bug #41 or this driver will NOT work! */ -#include +#include #include #include #include diff --git a/drivers/usb/host/ohci-lpc32xx.c b/drivers/usb/host/ohci-lpc32xx.c index a04b2961b96..ed04cae7afe 100644 --- a/drivers/usb/host/ohci-lpc32xx.c +++ b/drivers/usb/host/ohci-lpc32xx.c @@ -7,7 +7,6 @@ * Copyright (c) 2015 Tyco Fire Protection Products. */ -#include #include #include #include diff --git a/drivers/usb/host/ohci-npcm.c b/drivers/usb/host/ohci-npcm.c index 9e1d5298809..ffeb6bc206a 100644 --- a/drivers/usb/host/ohci-npcm.c +++ b/drivers/usb/host/ohci-npcm.c @@ -3,7 +3,6 @@ * Copyright (c) 2021 Nuvoton Technology Corp. */ -#include #include #include #include diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c index f061aec2896..f10f1092420 100644 --- a/drivers/usb/host/ohci-pci.c +++ b/drivers/usb/host/ohci-pci.c @@ -5,7 +5,6 @@ * */ -#include #include #include #include diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c index 3ccbc16da37..f0b18bffba4 100644 --- a/drivers/usb/host/r8a66597-hcd.c +++ b/drivers/usb/host/r8a66597-hcd.c @@ -5,7 +5,6 @@ * Copyright (C) 2008 Yoshihiro Shimoda */ -#include #include #include #include diff --git a/drivers/usb/host/usb-sandbox.c b/drivers/usb/host/usb-sandbox.c index 3d4f8d653b5..e26f0b292ed 100644 --- a/drivers/usb/host/usb-sandbox.c +++ b/drivers/usb/host/usb-sandbox.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c index a1cd0ad2d66..cd3a07e4c37 100644 --- a/drivers/usb/host/usb-uclass.c +++ b/drivers/usb/host/usb-uclass.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_USB -#include #include #include #include diff --git a/drivers/usb/host/usb_bootdev.c b/drivers/usb/host/usb_bootdev.c index 7fa1c601dff..362b46dc466 100644 --- a/drivers/usb/host/usb_bootdev.c +++ b/drivers/usb/host/usb_bootdev.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/usb/host/xhci-brcm.c b/drivers/usb/host/xhci-brcm.c index fe17924028c..2ffad148dea 100644 --- a/drivers/usb/host/xhci-brcm.c +++ b/drivers/usb/host/xhci-brcm.c @@ -3,7 +3,6 @@ * Copyright (C) 2019 Broadcom. */ -#include #include #include #include diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c index 6cebe1cc30c..e3e0ceff43e 100644 --- a/drivers/usb/host/xhci-dwc3.c +++ b/drivers/usb/host/xhci-dwc3.c @@ -8,7 +8,6 @@ */ #include -#include #include #include #include diff --git a/drivers/usb/host/xhci-exynos5.c b/drivers/usb/host/xhci-exynos5.c index 270be934e7f..6a2d422c4b8 100644 --- a/drivers/usb/host/xhci-exynos5.c +++ b/drivers/usb/host/xhci-exynos5.c @@ -12,7 +12,6 @@ * exynos5 specific PHY-init sequence. */ -#include #include #include #include diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c index e67e09e31e4..3484ae1d21e 100644 --- a/drivers/usb/host/xhci-fsl.c +++ b/drivers/usb/host/xhci-fsl.c @@ -7,7 +7,6 @@ * Author: Ramneek Mehresh */ -#include #include #include #include diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c index 72b75306265..045b0fba812 100644 --- a/drivers/usb/host/xhci-mem.c +++ b/drivers/usb/host/xhci-mem.c @@ -13,7 +13,6 @@ * Vikas Sajjan */ -#include #include #include #include diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c index 63dfb793c6b..7e288f0575b 100644 --- a/drivers/usb/host/xhci-mtk.c +++ b/drivers/usb/host/xhci-mtk.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/drivers/usb/host/xhci-mvebu.c b/drivers/usb/host/xhci-mvebu.c index 46b89de85d1..1338b1021c6 100644 --- a/drivers/usb/host/xhci-mvebu.c +++ b/drivers/usb/host/xhci-mvebu.c @@ -5,7 +5,6 @@ * MVEBU USB HOST xHCI Controller */ -#include #include #include #include diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c index 501129d769a..66da94c0709 100644 --- a/drivers/usb/host/xhci-omap.c +++ b/drivers/usb/host/xhci-omap.c @@ -8,7 +8,6 @@ * Author: Dan Murphy */ -#include #include #include #include diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index 11f1c02000a..f6972af7963 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -5,7 +5,6 @@ * All rights reserved. */ -#include #include #include #include diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c index fedcf786929..38c5928faed 100644 --- a/drivers/usb/host/xhci-rcar.c +++ b/drivers/usb/host/xhci-rcar.c @@ -5,7 +5,6 @@ * Renesas RCar USB HOST xHCI Controller */ -#include #include #include #include diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 910c5f3352b..1360a5940fa 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -13,7 +13,6 @@ * Vikas Sajjan */ -#include #include #include #include diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index 741e186ee05..d30725d3fca 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -19,7 +19,6 @@ * The quirk devices support hasn't been given yet. */ -#include #include #include #include diff --git a/drivers/usb/isp1760/isp1760-hcd.c b/drivers/usb/isp1760/isp1760-hcd.c index a6c4d97aee3..96c483fb9af 100644 --- a/drivers/usb/isp1760/isp1760-hcd.c +++ b/drivers/usb/isp1760/isp1760-hcd.c @@ -7,7 +7,6 @@ */ #include -#include #include #include #include diff --git a/drivers/usb/isp1760/isp1760-if.c b/drivers/usb/isp1760/isp1760-if.c index c96ab459f93..54246b49d5f 100644 --- a/drivers/usb/isp1760/isp1760-if.c +++ b/drivers/usb/isp1760/isp1760-if.c @@ -6,7 +6,6 @@ * (c) 2007 Sebastian Siewior */ -#include #include #include #include diff --git a/drivers/usb/isp1760/isp1760-uboot.c b/drivers/usb/isp1760/isp1760-uboot.c index 203500a4cb7..8dcb7768a2c 100644 --- a/drivers/usb/isp1760/isp1760-uboot.c +++ b/drivers/usb/isp1760/isp1760-uboot.c @@ -6,7 +6,6 @@ * */ -#include #include #include #include diff --git a/drivers/usb/mtu3/mtu3_plat.c b/drivers/usb/mtu3/mtu3_plat.c index b1b22b9357c..ca86b58dfcd 100644 --- a/drivers/usb/mtu3/mtu3_plat.c +++ b/drivers/usb/mtu3/mtu3_plat.c @@ -5,7 +5,6 @@ * Author: Chunfeng Yun */ -#include #include #include diff --git a/drivers/usb/musb-new/am35x.c b/drivers/usb/musb-new/am35x.c index 0a52e09e19f..42bc816e4f1 100644 --- a/drivers/usb/musb-new/am35x.c +++ b/drivers/usb/musb-new/am35x.c @@ -24,7 +24,6 @@ #include #else -#include #include #include #include diff --git a/drivers/usb/musb-new/da8xx.c b/drivers/usb/musb-new/da8xx.c index 68fc0c36146..7caf03cc2e1 100644 --- a/drivers/usb/musb-new/da8xx.c +++ b/drivers/usb/musb-new/da8xx.c @@ -13,7 +13,6 @@ * */ -#include #include #include #include diff --git a/drivers/usb/musb-new/mt85xx.c b/drivers/usb/musb-new/mt85xx.c index 1e632dca046..14b28bbae6b 100644 --- a/drivers/usb/musb-new/mt85xx.c +++ b/drivers/usb/musb-new/mt85xx.c @@ -9,7 +9,6 @@ * * This file is part of the Inventra Controller Driver for Linux. */ -#include #include #include #include diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c index 00da554982f..257e7685cfa 100644 --- a/drivers/usb/musb-new/musb_core.c +++ b/drivers/usb/musb-new/musb_core.c @@ -79,7 +79,6 @@ #include #include #else -#include #include #include #include diff --git a/drivers/usb/musb-new/musb_dsps.c b/drivers/usb/musb-new/musb_dsps.c index a8ff7434c9f..b73f3531ce2 100644 --- a/drivers/usb/musb-new/musb_dsps.c +++ b/drivers/usb/musb-new/musb_dsps.c @@ -31,7 +31,6 @@ #include #else -#include #include #include #include diff --git a/drivers/usb/musb-new/musb_gadget.c b/drivers/usb/musb-new/musb_gadget.c index c6083963ede..29e225aa0f1 100644 --- a/drivers/usb/musb-new/musb_gadget.c +++ b/drivers/usb/musb-new/musb_gadget.c @@ -22,7 +22,6 @@ #include #include #else -#include #include #include #include diff --git a/drivers/usb/musb-new/musb_gadget_ep0.c b/drivers/usb/musb-new/musb_gadget_ep0.c index 55ce8de99bb..63eee31a6b3 100644 --- a/drivers/usb/musb-new/musb_gadget_ep0.c +++ b/drivers/usb/musb-new/musb_gadget_ep0.c @@ -18,7 +18,6 @@ #include #include #else -#include #include #include #include diff --git a/drivers/usb/musb-new/musb_host.c b/drivers/usb/musb-new/musb_host.c index e5905d90d66..2f2fc7c1359 100644 --- a/drivers/usb/musb-new/musb_host.c +++ b/drivers/usb/musb-new/musb_host.c @@ -21,7 +21,6 @@ #include #include #else -#include #include #include #include diff --git a/drivers/usb/musb-new/musb_uboot.c b/drivers/usb/musb-new/musb_uboot.c index 7cea9a2ed65..43ab3245e5c 100644 --- a/drivers/usb/musb-new/musb_uboot.c +++ b/drivers/usb/musb-new/musb_uboot.c @@ -1,4 +1,3 @@ -#include #include #include #include diff --git a/drivers/usb/musb-new/omap2430.c b/drivers/usb/musb-new/omap2430.c index 308eff832c9..c8dd73050b2 100644 --- a/drivers/usb/musb-new/omap2430.c +++ b/drivers/usb/musb-new/omap2430.c @@ -8,7 +8,6 @@ * * This file is part of the Inventra Controller Driver for Linux. */ -#include #include #include #include diff --git a/drivers/usb/musb-new/pic32.c b/drivers/usb/musb-new/pic32.c index 4ed5e6e90c6..0b25e5893b3 100644 --- a/drivers/usb/musb-new/pic32.c +++ b/drivers/usb/musb-new/pic32.c @@ -9,7 +9,6 @@ * Based on the dsps "glue layer" code. */ -#include #include #include #include diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index 778b01b22ea..b577ba41878 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -15,7 +15,6 @@ * * This file is part of the Inventra Controller Driver for Linux. */ -#include #include #include #include diff --git a/drivers/usb/musb-new/ti-musb.c b/drivers/usb/musb-new/ti-musb.c index ed5e5194d8c..76e8b88369e 100644 --- a/drivers/usb/musb-new/ti-musb.c +++ b/drivers/usb/musb-new/ti-musb.c @@ -5,7 +5,6 @@ * (C) Copyright 2016 * Texas Instruments Incorporated, */ -#include #include #include #include diff --git a/drivers/usb/musb-new/ux500.c b/drivers/usb/musb-new/ux500.c index 57c7d5630d3..6b4ef3c8578 100644 --- a/drivers/usb/musb-new/ux500.c +++ b/drivers/usb/musb-new/ux500.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* Copyright (C) 2019 Stephan Gerhold */ -#include #include #include #include diff --git a/drivers/usb/musb/am35x.c b/drivers/usb/musb/am35x.c index f945f1f5e2c..2c23043d40e 100644 --- a/drivers/usb/musb/am35x.c +++ b/drivers/usb/musb/am35x.c @@ -9,7 +9,6 @@ * Copyright (c) 2010 Texas Instruments Incorporated */ -#include #include #include "am35x.h" diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c index 9651f074a49..260552e4dbd 100644 --- a/drivers/usb/musb/musb_core.c +++ b/drivers/usb/musb/musb_core.c @@ -8,7 +8,6 @@ * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments */ -#include #include #include "musb_core.h" diff --git a/drivers/usb/musb/musb_hcd.c b/drivers/usb/musb/musb_hcd.c index 4676cabae0a..c95c6a48281 100644 --- a/drivers/usb/musb/musb_hcd.c +++ b/drivers/usb/musb/musb_hcd.c @@ -7,7 +7,6 @@ * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments */ -#include #include #include #include diff --git a/drivers/usb/musb/musb_udc.c b/drivers/usb/musb/musb_udc.c index 2ffcb7caaad..696855ee3a6 100644 --- a/drivers/usb/musb/musb_udc.c +++ b/drivers/usb/musb/musb_udc.c @@ -37,7 +37,6 @@ * ------------------------------------------------------------------------- */ -#include #include #include #include diff --git a/drivers/usb/phy/rockchip_usb2_phy.c b/drivers/usb/phy/rockchip_usb2_phy.c index c46ad86d3d6..9ec5b2d172b 100644 --- a/drivers/usb/phy/rockchip_usb2_phy.c +++ b/drivers/usb/phy/rockchip_usb2_phy.c @@ -3,7 +3,6 @@ * Copyright 2016 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/drivers/usb/ulpi/omap-ulpi-viewport.c b/drivers/usb/ulpi/omap-ulpi-viewport.c index 1b01cd4c559..6f0c3eb154e 100644 --- a/drivers/usb/ulpi/omap-ulpi-viewport.c +++ b/drivers/usb/ulpi/omap-ulpi-viewport.c @@ -7,7 +7,6 @@ * Author: Govindraj R */ -#include #include #include #include diff --git a/drivers/usb/ulpi/ulpi-viewport.c b/drivers/usb/ulpi/ulpi-viewport.c index 55a62808384..bac20a02f01 100644 --- a/drivers/usb/ulpi/ulpi-viewport.c +++ b/drivers/usb/ulpi/ulpi-viewport.c @@ -13,7 +13,6 @@ * Copyright (C) 2011 Google, Inc. */ -#include #include #include #include diff --git a/drivers/usb/ulpi/ulpi.c b/drivers/usb/ulpi/ulpi.c index b5d2c2c2d1c..128adcbde13 100644 --- a/drivers/usb/ulpi/ulpi.c +++ b/drivers/usb/ulpi/ulpi.c @@ -19,7 +19,6 @@ * Freescale Semiconductors */ -#include #include #include #include diff --git a/drivers/video/anx9804.c b/drivers/video/anx9804.c index 52b5988ba5f..a149e6f5b95 100644 --- a/drivers/video/anx9804.c +++ b/drivers/video/anx9804.c @@ -9,7 +9,6 @@ * interface for driving eDP TFT displays. */ -#include #include #include #include "anx98xx-edp.h" diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c index 652ba141801..89bc0eeb680 100644 --- a/drivers/video/atmel_hlcdfb.c +++ b/drivers/video/atmel_hlcdfb.c @@ -5,7 +5,6 @@ * Copyright (C) 2012 Atmel Corporation */ -#include #include #include #include diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c index 5a7a54ada70..281c3a1d663 100644 --- a/drivers/video/atmel_lcdfb.c +++ b/drivers/video/atmel_lcdfb.c @@ -5,7 +5,6 @@ * Copyright (C) 2007 Atmel Corporation */ -#include #include #include #include diff --git a/drivers/video/backlight-uclass.c b/drivers/video/backlight-uclass.c index c14996d003c..2a09b2da910 100644 --- a/drivers/video/backlight-uclass.c +++ b/drivers/video/backlight-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_PANEL_BACKLIGHT -#include #include #include diff --git a/drivers/video/backlight_gpio.c b/drivers/video/backlight_gpio.c index eea824ab5e1..b26fa9a8acf 100644 --- a/drivers/video/backlight_gpio.c +++ b/drivers/video/backlight_gpio.c @@ -4,7 +4,6 @@ * Author: Patrick Delaunay */ -#include #include #include #include diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c index 63efa762db1..0c81e606622 100644 --- a/drivers/video/bcm2835.c +++ b/drivers/video/bcm2835.c @@ -3,7 +3,6 @@ * (C) Copyright 2012 Stephen Warren */ -#include #include #include #include diff --git a/drivers/video/bmp.c b/drivers/video/bmp.c index bab6fa7265a..291ed36440c 100644 --- a/drivers/video/bmp.c +++ b/drivers/video/bmp.c @@ -8,7 +8,6 @@ * BMP handling routines */ -#include #include #include #include diff --git a/drivers/video/bochs.c b/drivers/video/bochs.c index 022ea38d4cf..00e673a4db0 100644 --- a/drivers/video/bochs.c +++ b/drivers/video/bochs.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_VIDEO -#include #include #include #include diff --git a/drivers/video/bridge/anx6345.c b/drivers/video/bridge/anx6345.c index 93fa25f16e3..8cee4c958bd 100644 --- a/drivers/video/bridge/anx6345.c +++ b/drivers/video/bridge/anx6345.c @@ -3,7 +3,6 @@ * Copyright (C) 2017 Vasily Khoruzhick */ -#include #include #include #include diff --git a/drivers/video/bridge/ps862x.c b/drivers/video/bridge/ps862x.c index d1d22a6e235..efd03752281 100644 --- a/drivers/video/bridge/ps862x.c +++ b/drivers/video/bridge/ps862x.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/video/bridge/ptn3460.c b/drivers/video/bridge/ptn3460.c index 4760f04108f..5851e1ef15e 100644 --- a/drivers/video/bridge/ptn3460.c +++ b/drivers/video/bridge/ptn3460.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/video/bridge/ssd2825.c b/drivers/video/bridge/ssd2825.c index f0ef3dafb93..f978021c860 100644 --- a/drivers/video/bridge/ssd2825.c +++ b/drivers/video/bridge/ssd2825.c @@ -3,7 +3,6 @@ * Copyright (c) 2022 Svyatoslav Ryhel */ -#include #include #include #include diff --git a/drivers/video/bridge/video-bridge-uclass.c b/drivers/video/bridge/video-bridge-uclass.c index f389bc6b147..2084a2e03ee 100644 --- a/drivers/video/bridge/video-bridge-uclass.c +++ b/drivers/video/bridge/video-bridge-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_VIDEO_BRIDGE -#include #include #include #include diff --git a/drivers/video/broadwell_igd.c b/drivers/video/broadwell_igd.c index 83b6c908a8d..a26154ab588 100644 --- a/drivers/video/broadwell_igd.c +++ b/drivers/video/broadwell_igd.c @@ -5,12 +5,12 @@ * Copyright (C) 2016 Google, Inc */ -#include #include #include #include #include #include +#include #include #include #include diff --git a/drivers/video/console_normal.c b/drivers/video/console_normal.c index 34ef5a52294..6f4194a1814 100644 --- a/drivers/video/console_normal.c +++ b/drivers/video/console_normal.c @@ -6,7 +6,6 @@ * (C) Copyright 2023 Dzmitry Sankouski */ -#include #include #include #include diff --git a/drivers/video/console_rotate.c b/drivers/video/console_rotate.c index e4303dfb364..dc969836274 100644 --- a/drivers/video/console_rotate.c +++ b/drivers/video/console_rotate.c @@ -6,7 +6,6 @@ * (C) Copyright 2023 Dzmitry Sankouski */ -#include #include #include #include diff --git a/drivers/video/console_truetype.c b/drivers/video/console_truetype.c index 28665a32757..c435162d3f9 100644 --- a/drivers/video/console_truetype.c +++ b/drivers/video/console_truetype.c @@ -3,7 +3,6 @@ * Copyright (c) 2016 Google, Inc */ -#include #include #include #include diff --git a/drivers/video/coreboot.c b/drivers/video/coreboot.c index 5b718ae3e5a..9aede262642 100644 --- a/drivers/video/coreboot.c +++ b/drivers/video/coreboot.c @@ -3,7 +3,6 @@ * Copyright (C) 2016, Bin Meng */ -#include #include #include #include diff --git a/drivers/video/display-uclass.c b/drivers/video/display-uclass.c index 2da3d1d14e9..61a73e1bc2a 100644 --- a/drivers/video/display-uclass.c +++ b/drivers/video/display-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_DISPLAY -#include #include #include #include diff --git a/drivers/video/dsi-host-uclass.c b/drivers/video/dsi-host-uclass.c index 6e5256eb126..fde275ad7e2 100644 --- a/drivers/video/dsi-host-uclass.c +++ b/drivers/video/dsi-host-uclass.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY UCLASS_DSI_HOST -#include #include #include diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c index c217af97878..35559cef229 100644 --- a/drivers/video/dw_hdmi.c +++ b/drivers/video/dw_hdmi.c @@ -5,13 +5,14 @@ * Copyright 2017 Jernej Skrabec */ -#include #include #include #include #include #include +#include #include +#include #include "dw_hdmi.h" struct tmds_n_cts { diff --git a/drivers/video/dw_mipi_dsi.c b/drivers/video/dw_mipi_dsi.c index a7e0784596a..c74fe678d12 100644 --- a/drivers/video/dw_mipi_dsi.c +++ b/drivers/video/dw_mipi_dsi.c @@ -9,7 +9,6 @@ * the Linux Kernel driver drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c. */ -#include #include #include #include diff --git a/drivers/video/efi.c b/drivers/video/efi.c index 28ac15ff61b..78d123fad4b 100644 --- a/drivers/video/efi.c +++ b/drivers/video/efi.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY LOGC_EFI -#include #include #include #include diff --git a/drivers/video/endeavoru-panel.c b/drivers/video/endeavoru-panel.c index 1bff641434e..d4ba4d8b6da 100644 --- a/drivers/video/endeavoru-panel.c +++ b/drivers/video/endeavoru-panel.c @@ -3,7 +3,6 @@ * Copyright (c) 2022 Svyatoslav Ryhel */ -#include #include #include #include diff --git a/drivers/video/exynos/exynos_dp.c b/drivers/video/exynos/exynos_dp.c index 59838da6c92..b0afb2338fb 100644 --- a/drivers/video/exynos/exynos_dp.c +++ b/drivers/video/exynos/exynos_dp.c @@ -5,7 +5,6 @@ * Author: Donghwa Lee */ -#include #include #include #include diff --git a/drivers/video/exynos/exynos_dp_lowlevel.c b/drivers/video/exynos/exynos_dp_lowlevel.c index ae500a70280..f007b319b20 100644 --- a/drivers/video/exynos/exynos_dp_lowlevel.c +++ b/drivers/video/exynos/exynos_dp_lowlevel.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/drivers/video/exynos/exynos_fb.c b/drivers/video/exynos/exynos_fb.c index 86970a6d5d2..0407a3f51b0 100644 --- a/drivers/video/exynos/exynos_fb.c +++ b/drivers/video/exynos/exynos_fb.c @@ -7,7 +7,6 @@ */ #include -#include #include #include #include diff --git a/drivers/video/exynos/exynos_mipi_dsi.c b/drivers/video/exynos/exynos_mipi_dsi.c index 804fcd0b248..edeb0a87bbb 100644 --- a/drivers/video/exynos/exynos_mipi_dsi.c +++ b/drivers/video/exynos/exynos_mipi_dsi.c @@ -6,7 +6,6 @@ * Author: Donghwa Lee */ -#include #include #include #include diff --git a/drivers/video/exynos/exynos_mipi_dsi_common.c b/drivers/video/exynos/exynos_mipi_dsi_common.c index be67cebae7f..fc2767adc38 100644 --- a/drivers/video/exynos/exynos_mipi_dsi_common.c +++ b/drivers/video/exynos/exynos_mipi_dsi_common.c @@ -6,7 +6,6 @@ * Author: Donghwa Lee */ -#include #include #include #include diff --git a/drivers/video/exynos/exynos_mipi_dsi_lowlevel.c b/drivers/video/exynos/exynos_mipi_dsi_lowlevel.c index 8111acd9a0b..9f18b5da102 100644 --- a/drivers/video/exynos/exynos_mipi_dsi_lowlevel.c +++ b/drivers/video/exynos/exynos_mipi_dsi_lowlevel.c @@ -6,7 +6,6 @@ * Author: Donghwa Lee */ -#include #include #include #include diff --git a/drivers/video/himax-hx8394.c b/drivers/video/himax-hx8394.c index 63637b4db02..cb7f93e9c99 100644 --- a/drivers/video/himax-hx8394.c +++ b/drivers/video/himax-hx8394.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2022 Ondrej Jirman */ -#include #include #include #include diff --git a/drivers/video/hitachi_tx18d42vm_lcd.c b/drivers/video/hitachi_tx18d42vm_lcd.c index 95984fe3d3d..68f7b75eef9 100644 --- a/drivers/video/hitachi_tx18d42vm_lcd.c +++ b/drivers/video/hitachi_tx18d42vm_lcd.c @@ -5,7 +5,6 @@ * (C) Copyright 2015 Hans de Goede */ -#include #include #include diff --git a/drivers/video/hx8238d.c b/drivers/video/hx8238d.c index 6ee97cb4ff3..2491a32810e 100644 --- a/drivers/video/hx8238d.c +++ b/drivers/video/hx8238d.c @@ -12,7 +12,6 @@ * */ -#include #include #include #include diff --git a/drivers/video/ihs_video_out.c b/drivers/video/ihs_video_out.c index 73b8f4bd1c9..bf4d4995c36 100644 --- a/drivers/video/ihs_video_out.c +++ b/drivers/video/ihs_video_out.c @@ -9,7 +9,6 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.de */ -#include #include #include #include diff --git a/drivers/video/imx/ipu_common.c b/drivers/video/imx/ipu_common.c index b0a99c9cd5d..d582fb8ad9d 100644 --- a/drivers/video/imx/ipu_common.c +++ b/drivers/video/imx/ipu_common.c @@ -11,7 +11,7 @@ */ /* #define DEBUG */ -#include +#include #include #include #include diff --git a/drivers/video/imx/ipu_disp.c b/drivers/video/imx/ipu_disp.c index 144322e4e26..aaba7d135a4 100644 --- a/drivers/video/imx/ipu_disp.c +++ b/drivers/video/imx/ipu_disp.c @@ -12,7 +12,6 @@ /* #define DEBUG */ -#include #include #include #include diff --git a/drivers/video/imx/mxc_ipuv3_fb.c b/drivers/video/imx/mxc_ipuv3_fb.c index 7e60385bcfa..039b22086a9 100644 --- a/drivers/video/imx/mxc_ipuv3_fb.c +++ b/drivers/video/imx/mxc_ipuv3_fb.c @@ -10,7 +10,6 @@ * (C) Copyright 2004-2010 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/drivers/video/ivybridge_igd.c b/drivers/video/ivybridge_igd.c index c2cc976618a..ad688640733 100644 --- a/drivers/video/ivybridge_igd.c +++ b/drivers/video/ivybridge_igd.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Google, Inc */ -#include #include #include #include diff --git a/drivers/video/lm3533_backlight.c b/drivers/video/lm3533_backlight.c index 00297a09b7f..6b51fa0628e 100644 --- a/drivers/video/lm3533_backlight.c +++ b/drivers/video/lm3533_backlight.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_PANEL_BACKLIGHT #include -#include #include #include #include diff --git a/drivers/video/logicore_dp_tx.c b/drivers/video/logicore_dp_tx.c index 624084d38bc..643a77a0f4e 100644 --- a/drivers/video/logicore_dp_tx.c +++ b/drivers/video/logicore_dp_tx.c @@ -9,7 +9,6 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */ -#include #include #include #include diff --git a/drivers/video/mali_dp.c b/drivers/video/mali_dp.c index dbb2f538617..c8921267462 100644 --- a/drivers/video/mali_dp.c +++ b/drivers/video/mali_dp.c @@ -5,7 +5,6 @@ * */ #define DEBUG -#include #include #include #include diff --git a/drivers/video/mcde_simple.c b/drivers/video/mcde_simple.c index 0924ceee309..2ba5d0de152 100644 --- a/drivers/video/mcde_simple.c +++ b/drivers/video/mcde_simple.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* Copyright (C) 2019 Stephan Gerhold */ -#include #include #include #include diff --git a/drivers/video/meson/meson_canvas.c b/drivers/video/meson/meson_canvas.c index eccac2f8f24..dd4c546222d 100644 --- a/drivers/video/meson/meson_canvas.c +++ b/drivers/video/meson/meson_canvas.c @@ -6,7 +6,6 @@ * Author: Neil Armstrong */ -#include #include #include diff --git a/drivers/video/meson/meson_dw_hdmi.c b/drivers/video/meson/meson_dw_hdmi.c index 259af1b4571..587df7beb9b 100644 --- a/drivers/video/meson/meson_dw_hdmi.c +++ b/drivers/video/meson/meson_dw_hdmi.c @@ -4,7 +4,6 @@ * Author: Jorge Ramirez-Ortiz */ -#include #include #include #include diff --git a/drivers/video/meson/meson_plane.c b/drivers/video/meson/meson_plane.c index e3f784ecfe4..899ce22d067 100644 --- a/drivers/video/meson/meson_plane.c +++ b/drivers/video/meson/meson_plane.c @@ -6,7 +6,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/drivers/video/meson/meson_vclk.c b/drivers/video/meson/meson_vclk.c index e718a0074ed..4761ff661e4 100644 --- a/drivers/video/meson/meson_vclk.c +++ b/drivers/video/meson/meson_vclk.c @@ -6,7 +6,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/drivers/video/meson/meson_venc.c b/drivers/video/meson/meson_venc.c index e7366dd2fde..1bc6aaf7305 100644 --- a/drivers/video/meson/meson_venc.c +++ b/drivers/video/meson/meson_venc.c @@ -6,7 +6,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/drivers/video/meson/meson_vpu.c b/drivers/video/meson/meson_vpu.c index 67d4ce7b3b4..ca627728743 100644 --- a/drivers/video/meson/meson_vpu.c +++ b/drivers/video/meson/meson_vpu.c @@ -6,7 +6,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/drivers/video/meson/meson_vpu_init.c b/drivers/video/meson/meson_vpu_init.c index c9808e1c631..0e34cefd100 100644 --- a/drivers/video/meson/meson_vpu_init.c +++ b/drivers/video/meson/meson_vpu_init.c @@ -8,7 +8,6 @@ #define DEBUG -#include #include #include #include diff --git a/drivers/video/mipi_dsi.c b/drivers/video/mipi_dsi.c index ecacea1dbeb..dc949c8ae61 100644 --- a/drivers/video/mipi_dsi.c +++ b/drivers/video/mipi_dsi.c @@ -32,7 +32,6 @@ * */ -#include #include #include #include diff --git a/drivers/video/mvebu_lcd.c b/drivers/video/mvebu_lcd.c index d3d07e5f833..3fc5640b71e 100644 --- a/drivers/video/mvebu_lcd.c +++ b/drivers/video/mvebu_lcd.c @@ -5,7 +5,6 @@ * Initialization of LCD interface and setup of SPLASH screen image */ -#include #include #include #include diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index 515363f6a49..792d6314d15 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -4,7 +4,6 @@ * * Copyright (C) 2011-2013 Marek Vasut */ -#include #include #include #include diff --git a/drivers/video/nexell/s5pxx18_dp.c b/drivers/video/nexell/s5pxx18_dp.c index 2248f479057..16a489b88dc 100644 --- a/drivers/video/nexell/s5pxx18_dp.c +++ b/drivers/video/nexell/s5pxx18_dp.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/drivers/video/nexell/s5pxx18_dp_hdmi.c b/drivers/video/nexell/s5pxx18_dp_hdmi.c index 3f1fb8a5757..109d9f28bb0 100644 --- a/drivers/video/nexell/s5pxx18_dp_hdmi.c +++ b/drivers/video/nexell/s5pxx18_dp_hdmi.c @@ -6,7 +6,6 @@ */ #include -#include #include #include diff --git a/drivers/video/nexell/s5pxx18_dp_lvds.c b/drivers/video/nexell/s5pxx18_dp_lvds.c index f8ea63fdf1b..5db8d2b73b1 100644 --- a/drivers/video/nexell/s5pxx18_dp_lvds.c +++ b/drivers/video/nexell/s5pxx18_dp_lvds.c @@ -6,8 +6,8 @@ */ #include -#include #include +#include #include #include diff --git a/drivers/video/nexell/s5pxx18_dp_mipi.c b/drivers/video/nexell/s5pxx18_dp_mipi.c index 670272b2680..58493a82598 100644 --- a/drivers/video/nexell/s5pxx18_dp_mipi.c +++ b/drivers/video/nexell/s5pxx18_dp_mipi.c @@ -6,7 +6,6 @@ */ #include -#include #include #include diff --git a/drivers/video/nexell/s5pxx18_dp_rgb.c b/drivers/video/nexell/s5pxx18_dp_rgb.c index 44e8edb02a2..6abb8b5e216 100644 --- a/drivers/video/nexell/s5pxx18_dp_rgb.c +++ b/drivers/video/nexell/s5pxx18_dp_rgb.c @@ -6,8 +6,8 @@ */ #include -#include #include +#include #include diff --git a/drivers/video/nexell/soc/s5pxx18_soc_disptop.h b/drivers/video/nexell/soc/s5pxx18_soc_disptop.h index c7bf5043e60..4ad353256eb 100644 --- a/drivers/video/nexell/soc/s5pxx18_soc_disptop.h +++ b/drivers/video/nexell/soc/s5pxx18_soc_disptop.h @@ -8,6 +8,7 @@ #ifndef _S5PXX18_SOC_DISPTOP_H_ #define _S5PXX18_SOC_DISPTOP_H_ +#include #include "s5pxx18_soc_disptype.h" #define NUMBER_OF_DISPTOP_MODULE 1 diff --git a/drivers/video/nexell_display.c b/drivers/video/nexell_display.c index af2698ffca8..7bda33fb16e 100644 --- a/drivers/video/nexell_display.c +++ b/drivers/video/nexell_display.c @@ -8,7 +8,6 @@ */ #include -#include #include #include #include diff --git a/drivers/video/omap3_dss.c b/drivers/video/omap3_dss.c index 432b16bfbfe..0b7ce348d5a 100644 --- a/drivers/video/omap3_dss.c +++ b/drivers/video/omap3_dss.c @@ -25,7 +25,6 @@ * MA 02111-1307 USA */ -#include #include #include diff --git a/drivers/video/orisetech_otm8009a.c b/drivers/video/orisetech_otm8009a.c index 848f174b6e4..a29e909decc 100644 --- a/drivers/video/orisetech_otm8009a.c +++ b/drivers/video/orisetech_otm8009a.c @@ -7,7 +7,6 @@ * This otm8009a panel driver is inspired from the Linux Kernel driver * drivers/gpu/drm/panel/panel-orisetech-otm8009a.c. */ -#include #include #include #include diff --git a/drivers/video/panel-uclass.c b/drivers/video/panel-uclass.c index 1f7e20e0b50..52a3466dc8c 100644 --- a/drivers/video/panel-uclass.c +++ b/drivers/video/panel-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_PANEL -#include #include #include diff --git a/drivers/video/pwm_backlight.c b/drivers/video/pwm_backlight.c index 1c747d98d7a..a4576c888cf 100644 --- a/drivers/video/pwm_backlight.c +++ b/drivers/video/pwm_backlight.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_PANEL_BACKLIGHT -#include #include #include #include diff --git a/drivers/video/raydium-rm68200.c b/drivers/video/raydium-rm68200.c index f1fce55a2cb..b8662ca22bf 100644 --- a/drivers/video/raydium-rm68200.c +++ b/drivers/video/raydium-rm68200.c @@ -7,7 +7,6 @@ * This rm68200 panel driver is inspired from the Linux Kernel driver * drivers/gpu/drm/panel/panel-raydium-rm68200.c. */ -#include #include #include #include diff --git a/drivers/video/renesas-r61307.c b/drivers/video/renesas-r61307.c index 3f5859055c9..a3697bce5ee 100644 --- a/drivers/video/renesas-r61307.c +++ b/drivers/video/renesas-r61307.c @@ -5,7 +5,6 @@ * Copyright (c) 2022 Svyatoslav Ryhel */ -#include #include #include #include diff --git a/drivers/video/renesas-r69328.c b/drivers/video/renesas-r69328.c index 082f5bc3d0a..9861c3fef11 100644 --- a/drivers/video/renesas-r69328.c +++ b/drivers/video/renesas-r69328.c @@ -5,7 +5,6 @@ * Copyright (c) 2022 Svyatoslav Ryhel */ -#include #include #include #include diff --git a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c index fb784636e87..fa512173510 100644 --- a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c +++ b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c @@ -24,7 +24,6 @@ #include #include -#include #include #include #include diff --git a/drivers/video/rockchip/rk3288_hdmi.c b/drivers/video/rockchip/rk3288_hdmi.c index efa87540340..3d39f31a5ad 100644 --- a/drivers/video/rockchip/rk3288_hdmi.c +++ b/drivers/video/rockchip/rk3288_hdmi.c @@ -3,7 +3,6 @@ * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH */ -#include #include #include #include diff --git a/drivers/video/rockchip/rk3288_mipi.c b/drivers/video/rockchip/rk3288_mipi.c index 9d42119c826..850fe310754 100644 --- a/drivers/video/rockchip/rk3288_mipi.c +++ b/drivers/video/rockchip/rk3288_mipi.c @@ -4,7 +4,6 @@ * Author: Eric Gao */ -#include #include #include #include diff --git a/drivers/video/rockchip/rk3288_vop.c b/drivers/video/rockchip/rk3288_vop.c index a4683852ea0..282831eaac4 100644 --- a/drivers/video/rockchip/rk3288_vop.c +++ b/drivers/video/rockchip/rk3288_vop.c @@ -5,7 +5,6 @@ * Copyright 2014 Rockchip Inc. */ -#include #include #include #include diff --git a/drivers/video/rockchip/rk3399_hdmi.c b/drivers/video/rockchip/rk3399_hdmi.c index 5f3f5d26886..c7630ccf555 100644 --- a/drivers/video/rockchip/rk3399_hdmi.c +++ b/drivers/video/rockchip/rk3399_hdmi.c @@ -3,7 +3,6 @@ * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH */ -#include #include #include #include diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c index b62d8086674..57e36eed6a9 100644 --- a/drivers/video/rockchip/rk3399_mipi.c +++ b/drivers/video/rockchip/rk3399_mipi.c @@ -4,7 +4,6 @@ * Author: Eric Gao */ -#include #include #include #include diff --git a/drivers/video/rockchip/rk3399_vop.c b/drivers/video/rockchip/rk3399_vop.c index cb589c7537e..17e1601e814 100644 --- a/drivers/video/rockchip/rk3399_vop.c +++ b/drivers/video/rockchip/rk3399_vop.c @@ -5,7 +5,6 @@ * Copyright 2014 Rockchip Inc. */ -#include #include #include #include diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c index 5f68a610e4a..eb881ba4b0e 100644 --- a/drivers/video/rockchip/rk_edp.c +++ b/drivers/video/rockchip/rk_edp.c @@ -4,7 +4,6 @@ * Copyright 2014 Rockchip Inc. */ -#include #include #include #include diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c index d31f6a4ff81..0ac0a3a1ecd 100644 --- a/drivers/video/rockchip/rk_hdmi.c +++ b/drivers/video/rockchip/rk_hdmi.c @@ -5,7 +5,6 @@ * Copyright 2014 Rockchip Inc. */ -#include #include #include #include diff --git a/drivers/video/rockchip/rk_lvds.c b/drivers/video/rockchip/rk_lvds.c index d0a015e31ee..c969dae30b6 100644 --- a/drivers/video/rockchip/rk_lvds.c +++ b/drivers/video/rockchip/rk_lvds.c @@ -3,7 +3,6 @@ * Copyright 2016 Rockchip Inc. */ -#include #include #include #include diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c index f14cbc6dbf7..0a603083ba9 100644 --- a/drivers/video/rockchip/rk_mipi.c +++ b/drivers/video/rockchip/rk_mipi.c @@ -4,7 +4,6 @@ * Author: Eric Gao */ -#include #include #include #include diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c index acc02e5d7c7..17dfe62c9da 100644 --- a/drivers/video/rockchip/rk_vop.c +++ b/drivers/video/rockchip/rk_vop.c @@ -4,7 +4,6 @@ * Copyright 2014 Rockchip Inc. */ -#include #include #include #include diff --git a/drivers/video/sandbox_dsi_host.c b/drivers/video/sandbox_dsi_host.c index c84a27ee3be..7025ac986e3 100644 --- a/drivers/video/sandbox_dsi_host.c +++ b/drivers/video/sandbox_dsi_host.c @@ -3,7 +3,6 @@ * Copyright (C) 2019, STMicroelectronics - All Rights Reserved */ -#include #include #include #include diff --git a/drivers/video/sandbox_osd.c b/drivers/video/sandbox_osd.c index 2a854d3958b..bedc32b7c80 100644 --- a/drivers/video/sandbox_osd.c +++ b/drivers/video/sandbox_osd.c @@ -3,7 +3,6 @@ * (C) Copyright 2018 * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ -#include #include #include #include diff --git a/drivers/video/sandbox_sdl.c b/drivers/video/sandbox_sdl.c index 9081c7da62e..69dfa930273 100644 --- a/drivers/video/sandbox_sdl.c +++ b/drivers/video/sandbox_sdl.c @@ -3,7 +3,6 @@ * Copyright (c) 2013 Google, Inc */ -#include #include #include #include diff --git a/drivers/video/seps525.c b/drivers/video/seps525.c index 74c8721e1e1..86cd301c4b9 100644 --- a/drivers/video/seps525.c +++ b/drivers/video/seps525.c @@ -6,7 +6,6 @@ * Copyright (C) 2020 Xilinx Inc. */ -#include #include #include #include diff --git a/drivers/video/simple_panel.c b/drivers/video/simple_panel.c index 76a30427a59..b6c5b058b2e 100644 --- a/drivers/video/simple_panel.c +++ b/drivers/video/simple_panel.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/video/simplefb.c b/drivers/video/simplefb.c index 33bb78bc3a3..cb518b149cb 100644 --- a/drivers/video/simplefb.c +++ b/drivers/video/simplefb.c @@ -3,7 +3,6 @@ * (C) Copyright 2017 Rob Clark */ -#include #include #include #include diff --git a/drivers/video/ssd2828.c b/drivers/video/ssd2828.c index 948f5e74d0f..4334bbd7235 100644 --- a/drivers/video/ssd2828.c +++ b/drivers/video/ssd2828.c @@ -9,7 +9,6 @@ * interface for driving a MIPI compatible TFT display. */ -#include #include #include #include diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c index a18c1e027a8..438ed41e8d5 100644 --- a/drivers/video/stm32/stm32_dsi.c +++ b/drivers/video/stm32/stm32_dsi.c @@ -10,7 +10,6 @@ #define LOG_CATEGORY UCLASS_VIDEO_BRIDGE -#include #include #include #include diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c index 4f60ba8ebee..0a062c8939d 100644 --- a/drivers/video/stm32/stm32_ltdc.c +++ b/drivers/video/stm32/stm32_ltdc.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY UCLASS_VIDEO -#include #include #include #include diff --git a/drivers/video/sunxi/lcdc.c b/drivers/video/sunxi/lcdc.c index 73033c3b858..264d775c125 100644 --- a/drivers/video/sunxi/lcdc.c +++ b/drivers/video/sunxi/lcdc.c @@ -7,7 +7,6 @@ * (C) Copyright 2017 Jernej Skrabec */ -#include #include #include diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c index e02d359cd25..154641b9a69 100644 --- a/drivers/video/sunxi/sunxi_de2.c +++ b/drivers/video/sunxi/sunxi_de2.c @@ -5,7 +5,6 @@ * (C) Copyright 2017 Jernej Skrabec */ -#include #include #include #include diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c index 8da44a1bb6d..4a6a89ef9d2 100644 --- a/drivers/video/sunxi/sunxi_display.c +++ b/drivers/video/sunxi/sunxi_display.c @@ -6,7 +6,7 @@ * (C) Copyright 2014-2015 Hans de Goede */ -#include +#include #include #include #include diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index a5e8d39e98f..b9c03ea0386 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/drivers/video/sunxi/sunxi_lcd.c b/drivers/video/sunxi/sunxi_lcd.c index 7a01cc343ca..953233fcd68 100644 --- a/drivers/video/sunxi/sunxi_lcd.c +++ b/drivers/video/sunxi/sunxi_lcd.c @@ -5,7 +5,6 @@ * (C) Copyright 2017 Vasily Khoruzhick */ -#include #include #include #include diff --git a/drivers/video/sunxi/tve_common.c b/drivers/video/sunxi/tve_common.c index 35251371d14..7bc2b3b2909 100644 --- a/drivers/video/sunxi/tve_common.c +++ b/drivers/video/sunxi/tve_common.c @@ -7,7 +7,6 @@ * (C) Copyright 2017 Jernej Skrabec */ -#include #include #include diff --git a/drivers/video/tda19988.c b/drivers/video/tda19988.c index 24487439045..ebc8521c6ed 100644 --- a/drivers/video/tda19988.c +++ b/drivers/video/tda19988.c @@ -5,7 +5,6 @@ * Based on the Linux driver, (C) 2012 Texas Instruments */ -#include #include #include #include diff --git a/drivers/video/tdo-tl070wsh30.c b/drivers/video/tdo-tl070wsh30.c index 273672db024..d772958f46e 100644 --- a/drivers/video/tdo-tl070wsh30.c +++ b/drivers/video/tdo-tl070wsh30.c @@ -3,7 +3,6 @@ * Copyright (C) 2020 BayLibre, SAS * Author: Neil Armstrong */ -#include #include #include #include diff --git a/drivers/video/tegra124/display.c b/drivers/video/tegra124/display.c index 9261cc9384a..abe31e27d84 100644 --- a/drivers/video/tegra124/display.c +++ b/drivers/video/tegra124/display.c @@ -5,7 +5,6 @@ * Extracted from Chromium coreboot commit 3f59b13d */ -#include #include #include #include @@ -14,6 +13,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/video/tegra124/dp.c b/drivers/video/tegra124/dp.c index b27b1633bab..763f7ee39fc 100644 --- a/drivers/video/tegra124/dp.c +++ b/drivers/video/tegra124/dp.c @@ -4,12 +4,12 @@ * Copyright 2014 Google Inc. */ -#include #include #include #include #include #include +#include #include #include #include diff --git a/drivers/video/tegra124/sor.c b/drivers/video/tegra124/sor.c index 258685182c7..1ce5330c6bc 100644 --- a/drivers/video/tegra124/sor.c +++ b/drivers/video/tegra124/sor.c @@ -3,7 +3,6 @@ * Copyright (c) 2011-2013, NVIDIA Corporation. */ -#include #include #include #include diff --git a/drivers/video/tegra20/mipi-phy.c b/drivers/video/tegra20/mipi-phy.c index c3ebc4074b5..576262e405d 100644 --- a/drivers/video/tegra20/mipi-phy.c +++ b/drivers/video/tegra20/mipi-phy.c @@ -3,7 +3,6 @@ * Copyright (C) 2013 NVIDIA Corporation */ -#include #include #include "mipi-phy.h" diff --git a/drivers/video/tegra20/tegra-dsi.c b/drivers/video/tegra20/tegra-dsi.c index 13dae37806f..35a8e6c176b 100644 --- a/drivers/video/tegra20/tegra-dsi.c +++ b/drivers/video/tegra20/tegra-dsi.c @@ -4,7 +4,6 @@ * Copyright (c) 2022 Svyatoslav Ryhel */ -#include #include #include #include diff --git a/drivers/video/tegra20/tegra-pwm-backlight.c b/drivers/video/tegra20/tegra-pwm-backlight.c index 5f93f57fe90..79d8a021a3a 100644 --- a/drivers/video/tegra20/tegra-pwm-backlight.c +++ b/drivers/video/tegra20/tegra-pwm-backlight.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_PANEL_BACKLIGHT #include -#include #include #include #include diff --git a/drivers/video/ti/tilcdc-panel.c b/drivers/video/ti/tilcdc-panel.c index df95086a515..d4076523060 100644 --- a/drivers/video/ti/tilcdc-panel.c +++ b/drivers/video/ti/tilcdc-panel.c @@ -5,7 +5,6 @@ * Copyright (C) 2020 Dario Binacchi */ -#include #include #include #include diff --git a/drivers/video/ti/tilcdc.c b/drivers/video/ti/tilcdc.c index 2734754ecde..493e2f18cd2 100644 --- a/drivers/video/ti/tilcdc.c +++ b/drivers/video/ti/tilcdc.c @@ -3,7 +3,6 @@ * Copyright (C) 2020 Dario Binacchi */ -#include #include #include #include diff --git a/drivers/video/tidss/tidss_drv.c b/drivers/video/tidss/tidss_drv.c index 1380c6b6937..865d4bddb7f 100644 --- a/drivers/video/tidss/tidss_drv.c +++ b/drivers/video/tidss/tidss_drv.c @@ -9,7 +9,6 @@ * Author: Tomi Valkeinen */ -#include #include #include #include diff --git a/drivers/video/vesa.c b/drivers/video/vesa.c index 50912c5c8bc..ab756ac8ea1 100644 --- a/drivers/video/vesa.c +++ b/drivers/video/vesa.c @@ -3,7 +3,6 @@ * Copyright (C) 2016, Bin Meng */ -#include #include #include #include diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c index 5d06e51ff23..80e7adf6a1a 100644 --- a/drivers/video/vidconsole-uclass.c +++ b/drivers/video/vidconsole-uclass.c @@ -9,7 +9,6 @@ #define LOG_CATEGORY UCLASS_VIDEO_CONSOLE -#include #include #include #include diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index 7b5d1dfbb3b..ff1382f4a43 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_VIDEO -#include #include #include #include diff --git a/drivers/video/video_bmp.c b/drivers/video/video_bmp.c index 45f003c8251..ad512d99a1b 100644 --- a/drivers/video/video_bmp.c +++ b/drivers/video/video_bmp.c @@ -3,7 +3,6 @@ * Copyright (c) 2015 Google, Inc */ -#include #include #include #include diff --git a/drivers/video/video_osd-uclass.c b/drivers/video/video_osd-uclass.c index 0d3aae4d827..923686345ff 100644 --- a/drivers/video/video_osd-uclass.c +++ b/drivers/video/video_osd-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_VIDEO_OSD -#include #include #include diff --git a/drivers/video/videomodes.c b/drivers/video/videomodes.c index 35955a5df7d..d86d8679841 100644 --- a/drivers/video/videomodes.c +++ b/drivers/video/videomodes.c @@ -55,7 +55,6 @@ "myvideo" and setting the variable "videomode=myvideo".. ****************************************************************************/ -#include #include #include #include diff --git a/drivers/video/zynqmp/zynqmp_dpsub.c b/drivers/video/zynqmp/zynqmp_dpsub.c index def4dcf6261..1405b29cb8b 100644 --- a/drivers/video/zynqmp/zynqmp_dpsub.c +++ b/drivers/video/zynqmp/zynqmp_dpsub.c @@ -6,7 +6,6 @@ * Xilinx displayport(DP) Tx Subsytem driver */ -#include #include #include #include diff --git a/drivers/virtio/virtio-uclass.c b/drivers/virtio/virtio-uclass.c index c5420162735..1dbc1a56aa2 100644 --- a/drivers/virtio/virtio-uclass.c +++ b/drivers/virtio/virtio-uclass.c @@ -17,7 +17,6 @@ #define LOG_CATEGORY UCLASS_VIRTIO -#include #include #include #include diff --git a/drivers/virtio/virtio_blk.c b/drivers/virtio/virtio_blk.c index 95810582867..3404f61eba5 100644 --- a/drivers/virtio/virtio_blk.c +++ b/drivers/virtio/virtio_blk.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_VIRTIO -#include #include #include #include diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c index 78c15c821b4..1cd737aca24 100644 --- a/drivers/virtio/virtio_mmio.c +++ b/drivers/virtio/virtio_mmio.c @@ -7,7 +7,6 @@ * Ported from Linux drivers/virtio/virtio_mmio.c */ -#include #include #include #include diff --git a/drivers/virtio/virtio_net.c b/drivers/virtio/virtio_net.c index 1794f73a8de..0e5367a085e 100644 --- a/drivers/virtio/virtio_net.c +++ b/drivers/virtio/virtio_net.c @@ -4,7 +4,6 @@ * Copyright (C) 2018, Bin Meng */ -#include #include #include #include diff --git a/drivers/virtio/virtio_pci_legacy.c b/drivers/virtio/virtio_pci_legacy.c index aa89604ae84..15f8c6e7d25 100644 --- a/drivers/virtio/virtio_pci_legacy.c +++ b/drivers/virtio/virtio_pci_legacy.c @@ -6,7 +6,6 @@ * Ported from Linux drivers/virtio/virtio_pci*.c */ -#include #include #include #include diff --git a/drivers/virtio/virtio_pci_modern.c b/drivers/virtio/virtio_pci_modern.c index 3cdc2d2d6fd..5850e0c18c6 100644 --- a/drivers/virtio/virtio_pci_modern.c +++ b/drivers/virtio/virtio_pci_modern.c @@ -6,7 +6,6 @@ * Ported from Linux drivers/virtio/virtio_pci*.c */ -#include #include #include #include diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index c9adcce5c09..306fa5b3f68 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -7,7 +7,6 @@ */ #include -#include #include #include #include diff --git a/drivers/virtio/virtio_rng.c b/drivers/virtio/virtio_rng.c index 786359a6e36..90a371a59cc 100644 --- a/drivers/virtio/virtio_rng.c +++ b/drivers/virtio/virtio_rng.c @@ -3,7 +3,6 @@ * Copyright (c) 2019, Linaro Limited */ -#include #include #include #include diff --git a/drivers/virtio/virtio_sandbox.c b/drivers/virtio/virtio_sandbox.c index b34f1d60455..0f1ebef22e5 100644 --- a/drivers/virtio/virtio_sandbox.c +++ b/drivers/virtio/virtio_sandbox.c @@ -5,7 +5,6 @@ * VirtIO Sandbox transport driver, for testing purpose only */ -#include #include #include #include diff --git a/drivers/w1-eeprom/ds24xxx.c b/drivers/w1-eeprom/ds24xxx.c index 4be378b43d0..413d8bc5881 100644 --- a/drivers/w1-eeprom/ds24xxx.c +++ b/drivers/w1-eeprom/ds24xxx.c @@ -7,7 +7,6 @@ * */ -#include #include #include #include diff --git a/drivers/w1-eeprom/ds2502.c b/drivers/w1-eeprom/ds2502.c index a67f5edd0fe..db9f41e9726 100644 --- a/drivers/w1-eeprom/ds2502.c +++ b/drivers/w1-eeprom/ds2502.c @@ -20,7 +20,6 @@ * Martin Fuzzey */ -#include #include #include #include diff --git a/drivers/w1-eeprom/eep_sandbox.c b/drivers/w1-eeprom/eep_sandbox.c index 27c7f9f1b6b..2a69ca27de7 100644 --- a/drivers/w1-eeprom/eep_sandbox.c +++ b/drivers/w1-eeprom/eep_sandbox.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/drivers/w1-eeprom/w1-eeprom-uclass.c b/drivers/w1-eeprom/w1-eeprom-uclass.c index 70ba537243f..3919aad3c8a 100644 --- a/drivers/w1-eeprom/w1-eeprom-uclass.c +++ b/drivers/w1-eeprom/w1-eeprom-uclass.c @@ -12,7 +12,6 @@ #define LOG_CATEGORY UCLASS_W1_EEPROM -#include #include #include #include diff --git a/drivers/w1/mxc_w1.c b/drivers/w1/mxc_w1.c index b96c1a00bf2..9ebfc13c83a 100644 --- a/drivers/w1/mxc_w1.c +++ b/drivers/w1/mxc_w1.c @@ -17,7 +17,6 @@ * Martin Fuzzey */ -#include #include #include #include diff --git a/drivers/w1/w1-gpio.c b/drivers/w1/w1-gpio.c index 9346f810ce1..759f94e224e 100644 --- a/drivers/w1/w1-gpio.c +++ b/drivers/w1/w1-gpio.c @@ -7,7 +7,6 @@ * */ -#include #include #include #include diff --git a/drivers/w1/w1-uclass.c b/drivers/w1/w1-uclass.c index a4247ecd623..9637ed24257 100644 --- a/drivers/w1/w1-uclass.c +++ b/drivers/w1/w1-uclass.c @@ -14,7 +14,6 @@ #define LOG_CATEGORY UCLASS_W1 -#include #include #include #include diff --git a/drivers/watchdog/armada-37xx-wdt.c b/drivers/watchdog/armada-37xx-wdt.c index e09f5ac9e34..4b51178e1b8 100644 --- a/drivers/watchdog/armada-37xx-wdt.c +++ b/drivers/watchdog/armada-37xx-wdt.c @@ -5,7 +5,6 @@ * Marek Behún */ -#include #include #include #include diff --git a/drivers/watchdog/ast2600_wdt.c b/drivers/watchdog/ast2600_wdt.c index bc9842089be..190490f3692 100644 --- a/drivers/watchdog/ast2600_wdt.c +++ b/drivers/watchdog/ast2600_wdt.c @@ -3,7 +3,6 @@ * Copyright (c) 2020 Aspeed Technology, Inc */ -#include #include #include #include diff --git a/drivers/watchdog/ast_wdt.c b/drivers/watchdog/ast_wdt.c index f7b5a1adc10..e61e13fdc49 100644 --- a/drivers/watchdog/ast_wdt.c +++ b/drivers/watchdog/ast_wdt.c @@ -3,7 +3,6 @@ * Copyright 2017 Google, Inc */ -#include #include #include #include diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c index 647ae325e9a..c809a8936b8 100644 --- a/drivers/watchdog/at91sam9_wdt.c +++ b/drivers/watchdog/at91sam9_wdt.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/watchdog/bcm6345_wdt.c b/drivers/watchdog/bcm6345_wdt.c index 677b1347ca7..6ebe901c2b8 100644 --- a/drivers/watchdog/bcm6345_wdt.c +++ b/drivers/watchdog/bcm6345_wdt.c @@ -7,7 +7,6 @@ * Copyright (C) 2008 Florian Fainelli */ -#include #include #include #include diff --git a/drivers/watchdog/cdns_wdt.c b/drivers/watchdog/cdns_wdt.c index 743ab6487bc..cb5a786c589 100644 --- a/drivers/watchdog/cdns_wdt.c +++ b/drivers/watchdog/cdns_wdt.c @@ -6,7 +6,6 @@ * Author(s): Shreenidhi Shedi */ -#include #include #include #include diff --git a/drivers/watchdog/cortina_wdt.c b/drivers/watchdog/cortina_wdt.c index 7ab9d7b2db9..9f09ac0e15f 100644 --- a/drivers/watchdog/cortina_wdt.c +++ b/drivers/watchdog/cortina_wdt.c @@ -4,7 +4,6 @@ * */ -#include #include #include #include diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c index b22e0ee06a4..bd9d7105366 100644 --- a/drivers/watchdog/designware_wdt.c +++ b/drivers/watchdog/designware_wdt.c @@ -4,7 +4,6 @@ */ #include -#include #include #include #include diff --git a/drivers/watchdog/ftwdt010_wdt.c b/drivers/watchdog/ftwdt010_wdt.c index 1f5f301b125..4769b967e52 100644 --- a/drivers/watchdog/ftwdt010_wdt.c +++ b/drivers/watchdog/ftwdt010_wdt.c @@ -14,7 +14,6 @@ * 22/08/2022 Port to DM */ -#include #include #include #include diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c index 894158b304a..ea770217e59 100644 --- a/drivers/watchdog/imx_watchdog.c +++ b/drivers/watchdog/imx_watchdog.c @@ -4,7 +4,6 @@ * Licensed under the GPL-2 or later. */ -#include #include #include #include diff --git a/drivers/watchdog/mcf_wdt.c b/drivers/watchdog/mcf_wdt.c index b36488bb5b9..5092a256af0 100644 --- a/drivers/watchdog/mcf_wdt.c +++ b/drivers/watchdog/mcf_wdt.c @@ -6,7 +6,7 @@ * */ -#include +#include #include #include #include diff --git a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c index f28636ca901..036ff690d3f 100644 --- a/drivers/watchdog/mpc8xxx_wdt.c +++ b/drivers/watchdog/mpc8xxx_wdt.c @@ -3,7 +3,6 @@ * Copyright 2017 CS Systemes d'Information */ -#include #include #include #include diff --git a/drivers/watchdog/mt7621_wdt.c b/drivers/watchdog/mt7621_wdt.c index f7d201b921a..6308d9632a8 100644 --- a/drivers/watchdog/mt7621_wdt.c +++ b/drivers/watchdog/mt7621_wdt.c @@ -9,7 +9,6 @@ * Copyright (C) 2013 John Crispin */ -#include #include #include #include diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index 368b36849c8..706deb9da84 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -6,7 +6,6 @@ * Author: Ryder Lee */ -#include #include #include #include diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c index f0e57b4f728..5fd02ddf564 100644 --- a/drivers/watchdog/omap_wdt.c +++ b/drivers/watchdog/omap_wdt.c @@ -36,7 +36,6 @@ * Use the driver model and standard identifiers; handle bigger timeouts. */ -#include #include #include #include diff --git a/drivers/watchdog/orion_wdt.c b/drivers/watchdog/orion_wdt.c index 127766df58a..4562b2a37e3 100644 --- a/drivers/watchdog/orion_wdt.c +++ b/drivers/watchdog/orion_wdt.c @@ -12,7 +12,6 @@ * warranty of any kind, whether express or implied. */ -#include #include #include #include diff --git a/drivers/watchdog/rti_wdt.c b/drivers/watchdog/rti_wdt.c index 8d93f19b984..99168d0cad0 100644 --- a/drivers/watchdog/rti_wdt.c +++ b/drivers/watchdog/rti_wdt.c @@ -8,7 +8,6 @@ * Derived from linux/drivers/watchdog/rti_wdt.c */ -#include #include #include #include diff --git a/drivers/watchdog/s5p_wdt.c b/drivers/watchdog/s5p_wdt.c index 80524a00101..c244f15a895 100644 --- a/drivers/watchdog/s5p_wdt.c +++ b/drivers/watchdog/s5p_wdt.c @@ -4,7 +4,6 @@ * Minkyu Kang */ -#include #include #include #include diff --git a/drivers/watchdog/sandbox_alarm-wdt.c b/drivers/watchdog/sandbox_alarm-wdt.c index 71bb5d924ea..8dbbfc249e7 100644 --- a/drivers/watchdog/sandbox_alarm-wdt.c +++ b/drivers/watchdog/sandbox_alarm-wdt.c @@ -1,4 +1,3 @@ -#include #include #include #include diff --git a/drivers/watchdog/sandbox_wdt.c b/drivers/watchdog/sandbox_wdt.c index 535614f04d6..cd5eadbfd21 100644 --- a/drivers/watchdog/sandbox_wdt.c +++ b/drivers/watchdog/sandbox_wdt.c @@ -3,7 +3,6 @@ * Copyright 2017 Google, Inc */ -#include #include #include #include diff --git a/drivers/watchdog/sbsa_gwdt.c b/drivers/watchdog/sbsa_gwdt.c index 96d04665d52..03585529bb6 100644 --- a/drivers/watchdog/sbsa_gwdt.c +++ b/drivers/watchdog/sbsa_gwdt.c @@ -7,7 +7,6 @@ #include #include -#include #include #include #include diff --git a/drivers/watchdog/sl28cpld-wdt.c b/drivers/watchdog/sl28cpld-wdt.c index af5a6b1a28a..c5b4f8a9f66 100644 --- a/drivers/watchdog/sl28cpld-wdt.c +++ b/drivers/watchdog/sl28cpld-wdt.c @@ -5,7 +5,6 @@ * Copyright (c) 2021 Michael Walle */ -#include #include #include #include diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c index 6d58fd3cfda..10fe3e28232 100644 --- a/drivers/watchdog/sp805_wdt.c +++ b/drivers/watchdog/sp805_wdt.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/watchdog/stm32mp_wdt.c b/drivers/watchdog/stm32mp_wdt.c index 7ebcd255266..97ab8cfe7ab 100644 --- a/drivers/watchdog/stm32mp_wdt.c +++ b/drivers/watchdog/stm32mp_wdt.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_WDT -#include #include #include #include diff --git a/drivers/watchdog/tangier_wdt.c b/drivers/watchdog/tangier_wdt.c index bdc65597dcf..8fbfac31b1e 100644 --- a/drivers/watchdog/tangier_wdt.c +++ b/drivers/watchdog/tangier_wdt.c @@ -2,7 +2,6 @@ /* * Copyright (c) 2017 Intel Corporation */ -#include #include #include #include diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c index 0eea04ed2c6..83f19dc0e86 100644 --- a/drivers/watchdog/ulp_wdog.c +++ b/drivers/watchdog/ulp_wdog.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c index 417e8d7eef9..c88312ec721 100644 --- a/drivers/watchdog/wdt-uclass.c +++ b/drivers/watchdog/wdt-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_WDT -#include #include #include #include diff --git a/drivers/watchdog/xilinx_tb_wdt.c b/drivers/watchdog/xilinx_tb_wdt.c index b38c4000161..8a8e55370a0 100644 --- a/drivers/watchdog/xilinx_tb_wdt.c +++ b/drivers/watchdog/xilinx_tb_wdt.c @@ -8,7 +8,6 @@ * Copyright (c) 2011-2018 Xilinx Inc. */ -#include #include #include #include diff --git a/drivers/watchdog/xilinx_wwdt.c b/drivers/watchdog/xilinx_wwdt.c index 963ab22fb45..41eff1a4645 100644 --- a/drivers/watchdog/xilinx_wwdt.c +++ b/drivers/watchdog/xilinx_wwdt.c @@ -9,7 +9,6 @@ */ #include -#include #include #include #include diff --git a/drivers/xen/events.c b/drivers/xen/events.c index 2ebe20dbf26..fa8b13d2c61 100644 --- a/drivers/xen/events.c +++ b/drivers/xen/events.c @@ -14,7 +14,6 @@ * * [1] - http://xenbits.xen.org/gitweb/?p=mini-os.git;a=summary */ -#include #include #include diff --git a/drivers/xen/gnttab.c b/drivers/xen/gnttab.c index 31e96e2939c..005694a5c62 100644 --- a/drivers/xen/gnttab.c +++ b/drivers/xen/gnttab.c @@ -14,7 +14,6 @@ * * [1] - http://xenbits.xen.org/gitweb/?p=mini-os.git;a=summary */ -#include #include #include #include diff --git a/drivers/xen/hypervisor.c b/drivers/xen/hypervisor.c index 0b2311ba267..d28df823c68 100644 --- a/drivers/xen/hypervisor.c +++ b/drivers/xen/hypervisor.c @@ -8,7 +8,6 @@ * Copyright (c) 2005, Grzegorz Milos, gm281@cam.ac.uk,Intel Research Cambridge * Copyright (c) 2020, EPAM Systems Inc. */ -#include #include #include #include diff --git a/drivers/xen/pvblock.c b/drivers/xen/pvblock.c index 9fc51d203e5..0e47ffb46a8 100644 --- a/drivers/xen/pvblock.c +++ b/drivers/xen/pvblock.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY UCLASS_PVBLOCK #include -#include #include #include #include diff --git a/drivers/xen/xenbus.c b/drivers/xen/xenbus.c index 177d144723c..36de5255099 100644 --- a/drivers/xen/xenbus.c +++ b/drivers/xen/xenbus.c @@ -15,7 +15,6 @@ * [1] - http://xenbits.xen.org/gitweb/?p=mini-os.git;a=summary */ -#include #include #include diff --git a/env/Kconfig b/env/Kconfig index 1f8e90af55e..9641abe371a 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -312,7 +312,7 @@ config ENV_IS_IN_NVRAM config ENV_IS_IN_ONENAND bool "Environment is in OneNAND" - depends on !CHAIN_OF_TRUST + depends on !CHAIN_OF_TRUST && CMD_ONENAND help Define this if you want to put your local device's environment in OneNAND. diff --git a/env/attr.c b/env/attr.c index a958c714828..fed5b212e2f 100644 --- a/env/attr.c +++ b/env/attr.c @@ -4,13 +4,13 @@ * Joe Hershberger, National Instruments, joe.hershberger@ni.com */ +#include #ifdef USE_HOSTCC /* Eliminate "ANSI does not permit..." warnings */ #include -#include #include #else -#include #include +#include #endif #include diff --git a/env/callback.c b/env/callback.c index 98ddba035ea..b7cbccd1175 100644 --- a/env/callback.c +++ b/env/callback.c @@ -4,7 +4,6 @@ * Joe Hershberger, National Instruments, joe.hershberger@ni.com */ -#include #include #include #include diff --git a/env/common.c b/env/common.c index 48a565107c1..d8c276dddfd 100644 --- a/env/common.c +++ b/env/common.c @@ -7,7 +7,6 @@ * Andreas Heppel */ -#include #include #include #include diff --git a/env/eeprom.c b/env/eeprom.c index 7ce7e9972b2..b290b1013e1 100644 --- a/env/eeprom.c +++ b/env/eeprom.c @@ -7,7 +7,6 @@ * Andreas Heppel */ -#include #include #include #include diff --git a/env/env.c b/env/env.c index bae3f6482ae..bcc189e14db 100644 --- a/env/env.c +++ b/env/env.c @@ -4,13 +4,13 @@ * Written by Simon Glass */ -#include #include #include #include #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/env/ext4.c b/env/ext4.c index f21939186f0..d92c844ea6c 100644 --- a/env/ext4.c +++ b/env/ext4.c @@ -18,7 +18,6 @@ * Manjunatha C Achar */ -#include #include #include diff --git a/env/fat.c b/env/fat.c index d87a47b1001..f3f8b7301ee 100644 --- a/env/fat.c +++ b/env/fat.c @@ -6,7 +6,6 @@ * Maximilian Schwerin */ -#include #include #include #include diff --git a/env/flags.c b/env/flags.c index e2866361dfe..233fd460d84 100644 --- a/env/flags.c +++ b/env/flags.c @@ -8,9 +8,9 @@ #include #include +#include #ifdef USE_HOSTCC /* Eliminate "ANSI does not permit..." warnings */ #include -#include #include "fw_env_private.h" #include "fw_env.h" #include @@ -18,7 +18,7 @@ #define env_get fw_getenv #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) #else -#include +#include #include #endif diff --git a/env/flash.c b/env/flash.c index 1e75f8c004e..1bd6e7003d6 100644 --- a/env/flash.c +++ b/env/flash.c @@ -9,7 +9,6 @@ /* #define DEBUG */ -#include #include #include #include diff --git a/env/mmc.c b/env/mmc.c index 7afb733e890..776df0786be 100644 --- a/env/mmc.c +++ b/env/mmc.c @@ -5,7 +5,6 @@ /* #define DEBUG */ -#include #include #include diff --git a/env/nand.c b/env/nand.c index df300b13179..fef5697ec39 100644 --- a/env/nand.c +++ b/env/nand.c @@ -13,7 +13,6 @@ * Andreas Heppel */ -#include #include #include #include diff --git a/env/nowhere.c b/env/nowhere.c index 9ebc357dbd7..326f27db2e9 100644 --- a/env/nowhere.c +++ b/env/nowhere.c @@ -7,7 +7,6 @@ * Andreas Heppel */ -#include #include #include #include diff --git a/env/nvram.c b/env/nvram.c index 229c34f5367..d49cd0f337a 100644 --- a/env/nvram.c +++ b/env/nvram.c @@ -7,7 +7,6 @@ * Andreas Heppel */ -#include #include #include #include diff --git a/env/onenand.c b/env/onenand.c index 1faa2cb62a3..8c349ef5ce6 100644 --- a/env/onenand.c +++ b/env/onenand.c @@ -7,7 +7,6 @@ * Kyungmin Park */ -#include #include #include #include diff --git a/env/remote.c b/env/remote.c index 166bebf52b5..0cc383c2360 100644 --- a/env/remote.c +++ b/env/remote.c @@ -5,10 +5,10 @@ /* #define DEBUG */ -#include #include #include #include +#include #include #include diff --git a/env/sf.c b/env/sf.c index 8f5c03b00d3..c747e175e31 100644 --- a/env/sf.c +++ b/env/sf.c @@ -8,7 +8,6 @@ * * (C) Copyright 2008 Atmel Corporation */ -#include #include #include #include diff --git a/env/ubi.c b/env/ubi.c index 445d34fedb8..0c3e93c2bf2 100644 --- a/env/ubi.c +++ b/env/ubi.c @@ -4,7 +4,6 @@ * Joe Hershberger */ -#include #include #include diff --git a/examples/api/demo.c b/examples/api/demo.c index d586174ce8c..677d13b307a 100644 --- a/examples/api/demo.c +++ b/examples/api/demo.c @@ -5,7 +5,7 @@ * Written by: Rafal Jaworowski */ -#include +#include #include #include #include diff --git a/examples/api/glue.c b/examples/api/glue.c index 075d307ae26..08c21a8cb9c 100644 --- a/examples/api/glue.c +++ b/examples/api/glue.c @@ -3,7 +3,6 @@ * (C) Copyright 2007-2008 Semihalf, Rafal Jaworowski */ -#include #include #include #include diff --git a/examples/api/libgenwrap.c b/examples/api/libgenwrap.c index 3aa222866ff..bfd88e100d6 100644 --- a/examples/api/libgenwrap.c +++ b/examples/api/libgenwrap.c @@ -9,7 +9,6 @@ * existing code e.g. operations on strings and similar. */ -#include #include #include #include diff --git a/examples/standalone/atmel_df_pow2.c b/examples/standalone/atmel_df_pow2.c index dcb25da9498..ed0d7aeaadc 100644 --- a/examples/standalone/atmel_df_pow2.c +++ b/examples/standalone/atmel_df_pow2.c @@ -6,7 +6,6 @@ * Licensed under the 2-clause BSD. */ -#include #include #include #include diff --git a/examples/standalone/sched.c b/examples/standalone/sched.c index 1c529607132..d507163f6f3 100644 --- a/examples/standalone/sched.c +++ b/examples/standalone/sched.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include /* diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c index 65115570e8e..04e8acb8abe 100644 --- a/examples/standalone/stubs.c +++ b/examples/standalone/stubs.c @@ -1,4 +1,3 @@ -#include #include #include diff --git a/fs/btrfs/dev.c b/fs/btrfs/dev.c index cb3b9713a5f..e27a032c9f6 100644 --- a/fs/btrfs/dev.c +++ b/fs/btrfs/dev.c @@ -5,7 +5,6 @@ * 2017 Marek Behún, CZ.NIC, kabel@kernel.org */ -#include #include #include #include diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c index 7eaa7e94960..e5bfaf461c2 100644 --- a/fs/btrfs/disk-io.c +++ b/fs/btrfs/disk-io.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/fs/btrfs/volumes.c b/fs/btrfs/volumes.c index 7d4095d9ca8..8ec545eded7 100644 --- a/fs/btrfs/volumes.c +++ b/fs/btrfs/volumes.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ #include -#include +#include #include #include "ctree.h" #include "disk-io.h" diff --git a/fs/cbfs/cbfs.c b/fs/cbfs/cbfs.c index 714f4baafc9..ad5583233bb 100644 --- a/fs/cbfs/cbfs.c +++ b/fs/cbfs/cbfs.c @@ -3,10 +3,10 @@ * Copyright (c) 2011 The Chromium OS Authors. All rights reserved. */ -#include #include #include #include +#include #include /* Offset of master header from the start of a coreboot ROM */ diff --git a/fs/cramfs/cramfs.c b/fs/cramfs/cramfs.c index abb2de34eb0..22148ff8fe2 100644 --- a/fs/cramfs/cramfs.c +++ b/fs/cramfs/cramfs.c @@ -24,7 +24,7 @@ * The actual compression is based on zlib, see the other files. */ -#include +#include #include #include #include diff --git a/fs/cramfs/uncompress.c b/fs/cramfs/uncompress.c index 0d071b69f4c..2141edf22e4 100644 --- a/fs/cramfs/uncompress.c +++ b/fs/cramfs/uncompress.c @@ -20,7 +20,7 @@ * then is used by multiple filesystems. */ -#include +#include #include #include #include diff --git a/fs/ext4/dev.c b/fs/ext4/dev.c index 168443de1ff..3fd8980b1d6 100644 --- a/fs/ext4/dev.c +++ b/fs/ext4/dev.c @@ -22,7 +22,6 @@ * fs/ext2/dev.c file in uboot. */ -#include #include #include #include diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c index 2ff0dca2495..857c15d878e 100644 --- a/fs/ext4/ext4_common.c +++ b/fs/ext4/ext4_common.c @@ -18,7 +18,6 @@ * ext4write : Based on generic ext4 protocol. */ -#include #include #include #include diff --git a/fs/ext4/ext4_journal.c b/fs/ext4/ext4_journal.c index e80f797c8dc..02c4ac2cb93 100644 --- a/fs/ext4/ext4_journal.c +++ b/fs/ext4/ext4_journal.c @@ -13,7 +13,6 @@ * Copyright 1998-2000 Red Hat, Inc --- All Rights Reserved */ -#include #include #include #include diff --git a/fs/ext4/ext4_write.c b/fs/ext4/ext4_write.c index d057f6b5a79..38da3923c47 100644 --- a/fs/ext4/ext4_write.c +++ b/fs/ext4/ext4_write.c @@ -21,7 +21,6 @@ */ -#include #include #include #include diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c index 33e200ffa3c..da59cb008fc 100644 --- a/fs/ext4/ext4fs.c +++ b/fs/ext4/ext4fs.c @@ -20,7 +20,6 @@ * ext4write : Based on generic ext4 protocol. */ -#include #include #include #include diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 2dd9d4e72dc..e2570e81676 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -10,7 +10,6 @@ #define LOG_CATEGORY LOGC_FS -#include #include #include #include diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c index c8e0fbf1a3b..ea877ee9171 100644 --- a/fs/fat/fat_write.c +++ b/fs/fat/fat_write.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY LOGC_FS -#include #include #include #include diff --git a/fs/fs.c b/fs/fs.c index acf465bdd80..bed1f7242f4 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -21,6 +20,7 @@ #include #include #include +#include #include #include #include diff --git a/fs/fs_internal.c b/fs/fs_internal.c index 111f91b355d..51c1719361b 100644 --- a/fs/fs_internal.c +++ b/fs/fs_internal.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY LOGC_CORE -#include #include #include #include diff --git a/fs/jffs2/compr_zlib.c b/fs/jffs2/compr_zlib.c index d306b6dc4cf..e1e3c15e75e 100644 --- a/fs/jffs2/compr_zlib.c +++ b/fs/jffs2/compr_zlib.c @@ -35,8 +35,6 @@ * */ -#include -#include #include #include diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c index 49ba82ef959..5b7d7f4ae88 100644 --- a/fs/jffs2/jffs2_1pass.c +++ b/fs/jffs2/jffs2_1pass.c @@ -111,7 +111,6 @@ */ -#include #include #include #include diff --git a/fs/jffs2/mergesort.c b/fs/jffs2/mergesort.c index fca77aa6511..495937d792d 100644 --- a/fs/jffs2/mergesort.c +++ b/fs/jffs2/mergesort.c @@ -7,7 +7,6 @@ * http://www.chiark.greenend.org.uk/~sgtatham/algorithms/listsort.html */ -#include #include "jffs2_private.h" int sort_list(struct b_list *list) diff --git a/fs/sandbox/host_bootdev.c b/fs/sandbox/host_bootdev.c index 3ef53627608..3f74972a9f8 100644 --- a/fs/sandbox/host_bootdev.c +++ b/fs/sandbox/host_bootdev.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/fs/sandbox/sandboxfs.c b/fs/sandbox/sandboxfs.c index 4ae41d5b4db..773b583fa43 100644 --- a/fs/sandbox/sandboxfs.c +++ b/fs/sandbox/sandboxfs.c @@ -3,7 +3,7 @@ * Copyright (c) 2012, Google Inc. */ -#include +#include #include #include #include diff --git a/fs/semihostingfs.c b/fs/semihostingfs.c index 3592338a686..77e39ca407e 100644 --- a/fs/semihostingfs.c +++ b/fs/semihostingfs.c @@ -4,7 +4,7 @@ * Copyright (c) 2012, Google Inc. */ -#include +#include #include #include #include diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c index 3e7160352e6..788f88f0495 100644 --- a/fs/ubifs/super.c +++ b/fs/ubifs/super.c @@ -29,7 +29,6 @@ #include #else -#include #include #include #include diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c index a509584e5d7..75de01e95f7 100644 --- a/fs/ubifs/ubifs.c +++ b/fs/ubifs/ubifs.c @@ -11,7 +11,6 @@ * Adrian Hunter */ -#include #include #include #include diff --git a/fs/yaffs2/yaffs_mtdif.c b/fs/yaffs2/yaffs_mtdif.c index 50fed2d4b15..0eec22bc4a5 100644 --- a/fs/yaffs2/yaffs_mtdif.c +++ b/fs/yaffs2/yaffs_mtdif.c @@ -12,7 +12,6 @@ */ /* XXX U-BOOT XXX */ -#include #include "yportenv.h" diff --git a/fs/yaffs2/yaffs_mtdif2.c b/fs/yaffs2/yaffs_mtdif2.c index 81a4d964f3e..2bf171f99f1 100644 --- a/fs/yaffs2/yaffs_mtdif2.c +++ b/fs/yaffs2/yaffs_mtdif2.c @@ -14,7 +14,6 @@ /* mtd interface for YAFFS2 */ /* XXX U-BOOT XXX */ -#include #include #include diff --git a/fs/yaffs2/yaffs_uboot_glue.c b/fs/yaffs2/yaffs_uboot_glue.c index 0a920561149..deddbaac51e 100644 --- a/fs/yaffs2/yaffs_uboot_glue.c +++ b/fs/yaffs2/yaffs_uboot_glue.c @@ -19,7 +19,6 @@ * This version now uses the ydevconfig mechanism to set up partitions. */ -#include #include #include #include diff --git a/fs/zfs/dev.c b/fs/zfs/dev.c index fcd9893b3ac..722c6a86176 100644 --- a/fs/zfs/dev.c +++ b/fs/zfs/dev.c @@ -8,7 +8,6 @@ */ -#include #include #include #include diff --git a/fs/zfs/zfs.c b/fs/zfs/zfs.c index 113b428a938..9906d553fa6 100644 --- a/fs/zfs/zfs.c +++ b/fs/zfs/zfs.c @@ -10,7 +10,6 @@ * Copyright 2004 Sun Microsystems, Inc. */ -#include #include #include #include diff --git a/fs/zfs/zfs_fletcher.c b/fs/zfs/zfs_fletcher.c index 008a303ec79..b06c335626a 100644 --- a/fs/zfs/zfs_fletcher.c +++ b/fs/zfs/zfs_fletcher.c @@ -8,7 +8,6 @@ * Use is subject to license terms. */ -#include #include #include #include diff --git a/fs/zfs/zfs_lzjb.c b/fs/zfs/zfs_lzjb.c index b42d4980129..e79c5b4278f 100644 --- a/fs/zfs/zfs_lzjb.c +++ b/fs/zfs/zfs_lzjb.c @@ -8,7 +8,6 @@ * Use is subject to license terms. */ -#include #include #include #include diff --git a/fs/zfs/zfs_sha256.c b/fs/zfs/zfs_sha256.c index cb5b1c06834..602d75254ff 100644 --- a/fs/zfs/zfs_sha256.c +++ b/fs/zfs/zfs_sha256.c @@ -8,7 +8,6 @@ * Use is subject to license terms. */ -#include #include #include #include diff --git a/include/acpi/acpi_s3.h b/include/acpi/acpi_s3.h index d3f271f948e..f7bea941855 100644 --- a/include/acpi/acpi_s3.h +++ b/include/acpi/acpi_s3.h @@ -37,6 +37,9 @@ #ifndef __ASSEMBLY__ +#include +#include + extern char __wakeup[]; extern int __wakeup_size; diff --git a/include/adc.h b/include/adc.h index 0d1a666908f..15e4cdb7dce 100644 --- a/include/adc.h +++ b/include/adc.h @@ -7,6 +7,8 @@ #ifndef _ADC_H_ #define _ADC_H_ +#include + /* ADC_CHANNEL() - ADC channel bit mask, to select only required channels */ #define ADC_CHANNEL(x) (1 << x) diff --git a/include/android_ab.h b/include/android_ab.h index 1fee7582b90..dbf20343da6 100644 --- a/include/android_ab.h +++ b/include/android_ab.h @@ -6,6 +6,8 @@ #ifndef __ANDROID_AB_H #define __ANDROID_AB_H +#include + struct blk_desc; struct disk_partition; diff --git a/include/api_public.h b/include/api_public.h index 5a4465ea893..e89572c00a4 100644 --- a/include/api_public.h +++ b/include/api_public.h @@ -8,6 +8,8 @@ #ifndef _API_PUBLIC_H_ #define _API_PUBLIC_H_ +#include + #define API_EINVAL 1 /* invalid argument(s) */ #define API_ENODEV 2 /* no device */ #define API_ENOMEM 3 /* no memory */ diff --git a/include/atf_common.h b/include/atf_common.h index d69892fac6c..5ae45090252 100644 --- a/include/atf_common.h +++ b/include/atf_common.h @@ -74,6 +74,8 @@ #ifndef __ASSEMBLY__ +#include + /******************************************************************************* * Structure used for telling the next BL how much of a particular type of * memory is available for its use and how much is already used. diff --git a/include/audio_codec.h b/include/audio_codec.h index a81a3151576..a87b76c6f9e 100644 --- a/include/audio_codec.h +++ b/include/audio_codec.h @@ -7,6 +7,8 @@ #ifndef __AUDIO_CODEC_H__ #define __AUDIO_CODEC_H__ +#include + struct udevice; /* diff --git a/include/autoboot.h b/include/autoboot.h index eb204995d07..c68bd79f8dc 100644 --- a/include/autoboot.h +++ b/include/autoboot.h @@ -12,6 +12,7 @@ #define __AUTOBOOT_H #include +#include #ifdef CONFIG_SANDBOX diff --git a/include/axi.h b/include/axi.h index 59fb0b2e458..133a06ee271 100644 --- a/include/axi.h +++ b/include/axi.h @@ -7,6 +7,8 @@ #ifndef _AXI_H_ #define _AXI_H_ +#include + struct udevice; /** diff --git a/include/bmp_layout.h b/include/bmp_layout.h index a5c9498dc9f..eabbd25a330 100644 --- a/include/bmp_layout.h +++ b/include/bmp_layout.h @@ -10,6 +10,8 @@ #ifndef _BMP_H_ #define _BMP_H_ +#include + struct __packed bmp_color_table_entry { __u8 blue; __u8 green; diff --git a/include/bootmeth.h b/include/bootmeth.h index 0fc36104ece..cd9517321c0 100644 --- a/include/bootmeth.h +++ b/include/bootmeth.h @@ -7,6 +7,8 @@ #ifndef __bootmeth_h #define __bootmeth_h +#include + struct blk_desc; struct bootflow; struct bootflow_iter; diff --git a/include/bootstd.h b/include/bootstd.h index 99ce7b64e7c..ac756e98d84 100644 --- a/include/bootstd.h +++ b/include/bootstd.h @@ -10,6 +10,8 @@ #define __bootstd_h #include +#include +#include struct udevice; diff --git a/include/cedit.h b/include/cedit.h index f43cafa5aa2..a31b4245247 100644 --- a/include/cedit.h +++ b/include/cedit.h @@ -7,12 +7,15 @@ #ifndef __CEDIT_H #define __CEDIT_H +#include #include +#include struct abuf; struct expo; struct scene; struct video_priv; +struct udevice; enum { /* size increment for writing FDT */ diff --git a/include/common.h b/include/common.h deleted file mode 100644 index a79c2bb4993..00000000000 --- a/include/common.h +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Common header file for U-Boot - * - * This file still includes quite a few headers that should be included - * individually as needed. Patches to remove things are welcome. - * - * (C) Copyright 2000-2009 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#ifndef __COMMON_H_ -#define __COMMON_H_ 1 - -#ifndef __ASSEMBLY__ /* put C only stuff in this section */ -#include -#include -#include -#include -#include -#include -#include -#include -#include /* boot information for Linux kernel */ -#include -#endif /* __ASSEMBLY__ */ - -/* Pull in stuff for the build system */ -#ifdef DO_DEPS_ONLY -# include -#endif - -#endif /* __COMMON_H_ */ diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h index bf2bc2d45c0..e6dba707195 100644 --- a/include/configs/mt7621.h +++ b/include/configs/mt7621.h @@ -14,9 +14,6 @@ #define CFG_SYS_INIT_SP_OFFSET 0x800000 -/* MMC */ -#define MMC_SUPPORTS_TUNING - /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) #define CFG_SYS_NS16550_CLK 50000000 diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h index fca234a1dc7..6f42cd32d80 100644 --- a/include/configs/mt7623.h +++ b/include/configs/mt7623.h @@ -11,9 +11,6 @@ #include -/* MMC */ -#define MMC_SUPPORTS_TUNING - /* DRAM */ #define CFG_SYS_SDRAM_BASE 0x80000000 diff --git a/include/configs/octeontx2_common.h b/include/configs/octeontx2_common.h index c4db38562d8..f415dffddbe 100644 --- a/include/configs/octeontx2_common.h +++ b/include/configs/octeontx2_common.h @@ -19,9 +19,4 @@ "loadaddr=20080000\0" \ "ethrotate=yes\0" -#if defined(CONFIG_MMC_OCTEONTX) -#define MMC_SUPPORTS_TUNING -/** EMMC specific defines */ -#endif - #endif /* __OCTEONTX2_COMMON_H__ */ diff --git a/include/ddr_spd.h b/include/ddr_spd.h index fe163da43e5..c4d199fd7e1 100644 --- a/include/ddr_spd.h +++ b/include/ddr_spd.h @@ -6,6 +6,8 @@ #ifndef _DDR_SPD_H_ #define _DDR_SPD_H_ +#include + /* * Format from "JEDEC Standard No. 21-C, * Appendix D: Rev 1.0: SPD's for DDR SDRAM diff --git a/include/display.h b/include/display.h index 3d012176441..e8d8aaa15fb 100644 --- a/include/display.h +++ b/include/display.h @@ -6,6 +6,8 @@ #ifndef _DISPLAY_H #define _DISPLAY_H +#include + struct udevice; struct display_timing; diff --git a/include/dm/of.h b/include/dm/of.h index b1c934f610d..b7404c139d1 100644 --- a/include/dm/of.h +++ b/include/dm/of.h @@ -7,7 +7,6 @@ #ifndef _DM_OF_H #define _DM_OF_H -#include #include /* integer value within a device tree property which references another node */ diff --git a/include/dm/test.h b/include/dm/test.h index b5937509212..02737411a16 100644 --- a/include/dm/test.h +++ b/include/dm/test.h @@ -6,6 +6,8 @@ #ifndef __DM_TEST_H #define __DM_TEST_H +#include + struct udevice; /** diff --git a/include/dt-bindings/clock/adi-sc5xx-clock.h b/include/dt-bindings/clock/adi-sc5xx-clock.h new file mode 100644 index 00000000000..4a5373d1141 --- /dev/null +++ b/include/dt-bindings/clock/adi-sc5xx-clock.h @@ -0,0 +1,271 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison + * Contact: Greg Malysa + * + */ + +#ifndef DT_BINDINGS_CLOCK_ADI_SC5XX_CLOCK_H +#define DT_BINDINGS_CLOCK_ADI_SC5XX_CLOCK_H + +//ADSP-SC594 +#define ADSP_SC594_CLK_DUMMY 0 +#define ADSP_SC594_CLK_SYS_CLKIN0 1 +#define ADSP_SC594_CLK_SYS_CLKIN1 2 +#define ADSP_SC594_CLK_CGU1_IN 3 +#define ADSP_SC594_CLK_CGU0_PLL_IN 4 +#define ADSP_SC594_CLK_CGU1_PLL_IN 5 +#define ADSP_SC594_CLK_CGU0_VCO_OUT 6 +#define ADSP_SC594_CLK_CGU1_VCO_OUT 7 +#define ADSP_SC594_CLK_CGU0_PLLCLK 8 +#define ADSP_SC594_CLK_CGU1_PLLCLK 9 +#define ADSP_SC594_CLK_CGU0_CDIV 10 +#define ADSP_SC594_CLK_CGU0_SYSCLK 11 +#define ADSP_SC594_CLK_CGU0_DDIV 12 +#define ADSP_SC594_CLK_CGU0_ODIV 13 +#define ADSP_SC594_CLK_CGU0_S0SELDIV 14 +#define ADSP_SC594_CLK_CGU0_S1SELDIV 15 +#define ADSP_SC594_CLK_CGU0_S1SELEXDIV 16 +#define ADSP_SC594_CLK_CGU0_S1SEL 17 +#define ADSP_SC594_CLK_CGU1_CDIV 18 +#define ADSP_SC594_CLK_CGU1_SYSCLK 19 +#define ADSP_SC594_CLK_CGU1_DDIV 20 +#define ADSP_SC594_CLK_CGU1_ODIV 21 +#define ADSP_SC594_CLK_CGU1_S0SELDIV 22 +#define ADSP_SC594_CLK_CGU1_S1SELDIV 23 +#define ADSP_SC594_CLK_CGU1_S1SELEXDIV 24 +#define ADSP_SC594_CLK_CGU1_S1SEL 25 +#define ADSP_SC594_CLK_CGU0_CCLK0 26 +#define ADSP_SC594_CLK_CGU0_CCLK1 27 +#define ADSP_SC594_CLK_CGU0_OCLK 28 +#define ADSP_SC594_CLK_CGU0_DCLK 29 +#define ADSP_SC594_CLK_CGU0_SCLK1 30 +#define ADSP_SC594_CLK_CGU0_SCLK0 31 +#define ADSP_SC594_CLK_CGU1_CCLK0 32 +#define ADSP_SC594_CLK_CGU1_CCLK1 33 +#define ADSP_SC594_CLK_CGU1_OCLK 34 +#define ADSP_SC594_CLK_CGU1_DCLK 35 +#define ADSP_SC594_CLK_CGU1_SCLK1 36 +#define ADSP_SC594_CLK_CGU1_SCLK0 37 +#define ADSP_SC594_CLK_SHARC0_SEL 38 +#define ADSP_SC594_CLK_SHARC1_SEL 39 +#define ADSP_SC594_CLK_ARM_SEL 40 +#define ADSP_SC594_CLK_CDU_DDR_SEL 41 +#define ADSP_SC594_CLK_CAN_SEL 42 +#define ADSP_SC594_CLK_SPDIF_SEL 43 +#define ADSP_SC594_CLK_RESERVED_SEL 44 +#define ADSP_SC594_CLK_GIGE_SEL 45 +#define ADSP_SC594_CLK_LP_SEL 46 +#define ADSP_SC594_CLK_LPDDR_SEL 47 +#define ADSP_SC594_CLK_OSPI_SEL 48 +#define ADSP_SC594_CLK_TRACE_SEL 49 +#define ADSP_SC594_CLK_SHARC0 50 +#define ADSP_SC594_CLK_SHARC1 51 +#define ADSP_SC594_CLK_ARM 52 +#define ADSP_SC594_CLK_CDU_DDR 53 +#define ADSP_SC594_CLK_CAN 54 +#define ADSP_SC594_CLK_SPDIF 55 +#define ADSP_SC594_CLK_SPI 56 +#define ADSP_SC594_CLK_GIGE 57 +#define ADSP_SC594_CLK_LP 58 +#define ADSP_SC594_CLK_LPDDR 59 +#define ADSP_SC594_CLK_OSPI 60 +#define ADSP_SC594_CLK_TRACE 61 +#define ADSP_SC594_CLK_END 62 + +//ADSP-SC598 +#define ADSP_SC598_CLK_DUMMY 0 +#define ADSP_SC598_CLK_SYS_CLKIN0 1 +#define ADSP_SC598_CLK_SYS_CLKIN1 2 +#define ADSP_SC598_CLK_CGU0_PLL_IN 3 +#define ADSP_SC598_CLK_CGU0_VCO_OUT 4 +#define ADSP_SC598_CLK_CGU0_PLLCLK 5 +#define ADSP_SC598_CLK_CGU1_IN 6 +#define ADSP_SC598_CLK_CGU1_PLL_IN 7 +#define ADSP_SC598_CLK_CGU1_VCO_OUT 8 +#define ADSP_SC598_CLK_CGU1_PLLCLK 9 +#define ADSP_SC598_CLK_CGU0_CDIV 10 +#define ADSP_SC598_CLK_CGU0_SYSCLK 11 +#define ADSP_SC598_CLK_CGU0_DDIV 12 +#define ADSP_SC598_CLK_CGU0_ODIV 13 +#define ADSP_SC598_CLK_CGU0_S0SELDIV 14 +#define ADSP_SC598_CLK_CGU0_S1SELDIV 15 +#define ADSP_SC598_CLK_CGU0_S1SELEXDIV 16 +#define ADSP_SC598_CLK_CGU0_S1SEL 17 +#define ADSP_SC598_CLK_CGU1_CDIV 18 +#define ADSP_SC598_CLK_CGU1_SYSCLK 19 +#define ADSP_SC598_CLK_CGU1_DDIV 20 +#define ADSP_SC598_CLK_CGU1_ODIV 21 +#define ADSP_SC598_CLK_CGU1_S0SELDIV 22 +#define ADSP_SC598_CLK_CGU1_S1SELDIV 23 +#define ADSP_SC598_CLK_CGU1_S0SELEXDIV 24 +#define ADSP_SC598_CLK_CGU1_S1SELEXDIV 25 +#define ADSP_SC598_CLK_CGU1_S0SEL 26 +#define ADSP_SC598_CLK_CGU1_S1SEL 27 +#define ADSP_SC598_CLK_CGU0_CCLK2 28 +#define ADSP_SC598_CLK_CGU0_CCLK0 29 +#define ADSP_SC598_CLK_CGU0_OCLK 30 +#define ADSP_SC598_CLK_CGU0_DCLK 31 +#define ADSP_SC598_CLK_CGU0_SCLK1 32 +#define ADSP_SC598_CLK_CGU0_SCLK0 33 +#define ADSP_SC598_CLK_CGU1_CCLK0 34 +#define ADSP_SC598_CLK_CGU1_OCLK 35 +#define ADSP_SC598_CLK_CGU1_DCLK 36 +#define ADSP_SC598_CLK_CGU1_SCLK1 37 +#define ADSP_SC598_CLK_CGU1_SCLK0 38 +#define ADSP_SC598_CLK_CGU1_CCLK2 39 +#define ADSP_SC598_CLK_DCLK0_HALF 40 +#define ADSP_SC598_CLK_DCLK1_HALF 41 +#define ADSP_SC598_CLK_CGU1_SCLK1_HALF 42 +#define ADSP_SC598_CLK_SHARC0_SEL 43 +#define ADSP_SC598_CLK_SHARC1_SEL 44 +#define ADSP_SC598_CLK_ARM_SEL 45 +#define ADSP_SC598_CLK_CDU_DDR_SEL 46 +#define ADSP_SC598_CLK_CAN_SEL 47 +#define ADSP_SC598_CLK_SPDIF_SEL 48 +#define ADSP_SC598_CLK_SPI_SEL 49 +#define ADSP_SC598_CLK_GIGE_SEL 50 +#define ADSP_SC598_CLK_LP_SEL 51 +#define ADSP_SC598_CLK_LP_DDR_SEL 52 +#define ADSP_SC598_CLK_OSPI_REFCLK_SEL 53 +#define ADSP_SC598_CLK_TRACE_SEL 54 +#define ADSP_SC598_CLK_EMMC_SEL 55 +#define ADSP_SC598_CLK_EMMC_TIMER_QMC_SEL 56 +#define ADSP_SC598_CLK_SHARC0 57 +#define ADSP_SC598_CLK_SHARC1 58 +#define ADSP_SC598_CLK_ARM 59 +#define ADSP_SC598_CLK_CDU_DDR 60 +#define ADSP_SC598_CLK_CAN 61 +#define ADSP_SC598_CLK_SPDIF 62 +#define ADSP_SC598_CLK_SPI 63 +#define ADSP_SC598_CLK_GIGE 64 +#define ADSP_SC598_CLK_LP 65 +#define ADSP_SC598_CLK_LP_DDR 66 +#define ADSP_SC598_CLK_OSPI_REFCLK 67 +#define ADSP_SC598_CLK_TRACE 68 +#define ADSP_SC598_CLK_EMMC 69 +#define ADSP_SC598_CLK_EMMC_TIMER_QMC 70 +#define ADSP_SC598_CLK_3PLL_PLL_IN 71 +#define ADSP_SC598_CLK_3PLL_VCO_OUT 72 +#define ADSP_SC598_CLK_3PLL_PLLCLK 73 +#define ADSP_SC598_CLK_3PLL_DDIV 74 +#define ADSP_SC598_CLK_DDR 75 +#define ADSP_SC598_CLK_END 76 + +//ADSP-SC58X +#define ADSP_SC58X_CLK_DUMMY 0 +#define ADSP_SC58X_CLK_SYS_CLKIN0 1 +#define ADSP_SC58X_CLK_SYS_CLKIN1 2 +#define ADSP_SC58X_CLK_CGU0_PLL_IN 3 +#define ADSP_SC58X_CLK_CGU0_VCO_OUT 4 +#define ADSP_SC58X_CLK_CGU0_PLLCLK 5 +#define ADSP_SC58X_CLK_CGU1_IN 6 +#define ADSP_SC58X_CLK_CGU1_PLL_IN 7 +#define ADSP_SC58X_CLK_CGU1_VCO_OUT 8 +#define ADSP_SC58X_CLK_CGU1_PLLCLK 9 +#define ADSP_SC58X_CLK_CGU0_CDIV 10 +#define ADSP_SC58X_CLK_CGU0_SYSCLK 11 +#define ADSP_SC58X_CLK_CGU0_DDIV 12 +#define ADSP_SC58X_CLK_CGU0_ODIV 13 +#define ADSP_SC58X_CLK_CGU0_S0SELDIV 14 +#define ADSP_SC58X_CLK_CGU0_S1SELDIV 15 +#define ADSP_SC58X_CLK_CGU1_CDIV 16 +#define ADSP_SC58X_CLK_CGU1_SYSCLK 17 +#define ADSP_SC58X_CLK_CGU1_DDIV 18 +#define ADSP_SC58X_CLK_CGU1_ODIV 19 +#define ADSP_SC58X_CLK_CGU1_S0SELDIV 20 +#define ADSP_SC58X_CLK_CGU1_S1SELDIV 21 +#define ADSP_SC58X_CLK_CGU0_CCLK0 22 +#define ADSP_SC58X_CLK_CGU0_CCLK1 23 +#define ADSP_SC58X_CLK_CGU0_OCLK 24 +#define ADSP_SC58X_CLK_CGU0_DCLK 25 +#define ADSP_SC58X_CLK_CGU0_SCLK1 26 +#define ADSP_SC58X_CLK_CGU0_SCLK0 27 +#define ADSP_SC58X_CLK_CGU1_CCLK0 28 +#define ADSP_SC58X_CLK_CGU1_CCLK1 29 +#define ADSP_SC58X_CLK_CGU1_OCLK 30 +#define ADSP_SC58X_CLK_CGU1_DCLK 31 +#define ADSP_SC58X_CLK_CGU1_SCLK1 32 +#define ADSP_SC58X_CLK_CGU1_SCLK0 33 +#define ADSP_SC58X_CLK_OCLK0_HALF 34 +#define ADSP_SC58X_CLK_CCLK1_1_HALF 35 +#define ADSP_SC58X_CLK_SHARC0_SEL 36 +#define ADSP_SC58X_CLK_SHARC1_SEL 37 +#define ADSP_SC58X_CLK_ARM_SEL 38 +#define ADSP_SC58X_CLK_CDU_DDR_SEL 39 +#define ADSP_SC58X_CLK_CAN_SEL 40 +#define ADSP_SC58X_CLK_SPDIF_SEL 41 +#define ADSP_SC58X_CLK_RESERVED_SEL 42 +#define ADSP_SC58X_CLK_GIGE_SEL 43 +#define ADSP_SC58X_CLK_LP_SEL 44 +#define ADSP_SC58X_CLK_SDIO_SEL 45 +#define ADSP_SC58X_CLK_SHARC0 46 +#define ADSP_SC58X_CLK_SHARC1 47 +#define ADSP_SC58X_CLK_ARM 48 +#define ADSP_SC58X_CLK_CDU_DDR 49 +#define ADSP_SC58X_CLK_CAN 50 +#define ADSP_SC58X_CLK_SPDIF 51 +#define ADSP_SC58X_CLK_RESERVED 52 +#define ADSP_SC58X_CLK_GIGE 53 +#define ADSP_SC58X_CLK_LP 54 +#define ADSP_SC58X_CLK_SDIO 55 +#define ADSP_SC58X_CLK_END 56 + +//ADSP-SC57X +#define ADSP_SC57X_CLK_DUMMY 0 +#define ADSP_SC57X_CLK_SYS_CLKIN0 1 +#define ADSP_SC57X_CLK_SYS_CLKIN1 2 +#define ADSP_SC57X_CLK_CGU0_PLL_IN 3 +#define ADSP_SC57X_CLK_CGU0_PLLCLK 4 +#define ADSP_SC57X_CLK_CGU1_IN 5 +#define ADSP_SC57X_CLK_CGU1_PLL_IN 6 +#define ADSP_SC57X_CLK_CGU1_PLLCLK 7 +#define ADSP_SC57X_CLK_CGU0_CDIV 8 +#define ADSP_SC57X_CLK_CGU0_SYSCLK 9 +#define ADSP_SC57X_CLK_CGU0_DDIV 10 +#define ADSP_SC57X_CLK_CGU0_ODIV 11 +#define ADSP_SC57X_CLK_CGU0_S0SELDIV 12 +#define ADSP_SC57X_CLK_CGU0_S1SELDIV 13 +#define ADSP_SC57X_CLK_CGU1_CDIV 14 +#define ADSP_SC57X_CLK_CGU1_SYSCLK 15 +#define ADSP_SC57X_CLK_CGU1_DDIV 16 +#define ADSP_SC57X_CLK_CGU1_ODIV 17 +#define ADSP_SC57X_CLK_CGU1_S0SELDIV 18 +#define ADSP_SC57X_CLK_CGU1_S1SELDIV 19 +#define ADSP_SC57X_CLK_CGU0_CCLK0 20 +#define ADSP_SC57X_CLK_CGU0_CCLK1 21 +#define ADSP_SC57X_CLK_CGU0_OCLK 22 +#define ADSP_SC57X_CLK_CGU0_DCLK 23 +#define ADSP_SC57X_CLK_CGU0_SCLK1 24 +#define ADSP_SC57X_CLK_CGU0_SCLK0 25 +#define ADSP_SC57X_CLK_CGU1_CCLK0 26 +#define ADSP_SC57X_CLK_CGU1_CCLK1 27 +#define ADSP_SC57X_CLK_CGU1_OCLK 28 +#define ADSP_SC57X_CLK_CGU1_DCLK 29 +#define ADSP_SC57X_CLK_CGU1_SCLK1 30 +#define ADSP_SC57X_CLK_CGU1_SCLK0 31 +#define ADSP_SC57X_CLK_OCLK0_HALF 32 +#define ADSP_SC57X_CLK_CCLK1_1_HALF 33 +#define ADSP_SC57X_CLK_SHARC0_SEL 34 +#define ADSP_SC57X_CLK_SHARC1_SEL 35 +#define ADSP_SC57X_CLK_ARM_SEL 36 +#define ADSP_SC57X_CLK_CDU_DDR_SEL 37 +#define ADSP_SC57X_CLK_CAN_SEL 38 +#define ADSP_SC57X_CLK_SPDIF_SEL 39 +#define ADSP_SC57X_CLK_GIGE_SEL 40 +#define ADSP_SC57X_CLK_SDIO_SEL 41 +#define ADSP_SC57X_CLK_SHARC0 42 +#define ADSP_SC57X_CLK_SHARC1 43 +#define ADSP_SC57X_CLK_ARM 44 +#define ADSP_SC57X_CLK_CDU_DDR 45 +#define ADSP_SC57X_CLK_CAN 46 +#define ADSP_SC57X_CLK_SPDIF 47 +#define ADSP_SC57X_CLK_GIGE 48 +#define ADSP_SC57X_CLK_SDIO 49 +#define ADSP_SC57X_CLK_END 50 + +#endif diff --git a/include/eeprom.h b/include/eeprom.h index f9c6542ba76..e223e4c7670 100644 --- a/include/eeprom.h +++ b/include/eeprom.h @@ -8,6 +8,8 @@ #define __EEPROM_LEGACY_H #if defined(CONFIG_CMD_EEPROM) || defined(CONFIG_ENV_IS_IN_EEPROM) +#include + void eeprom_init(int bus); int eeprom_read(uint dev_addr, uint offset, uchar *buffer, uint cnt); int eeprom_write(uint dev_addr, uint offset, uchar *buffer, uint cnt); diff --git a/include/env/adi/adi_boot.env b/include/env/adi/adi_boot.env new file mode 100644 index 00000000000..d56b14f5172 --- /dev/null +++ b/include/env/adi/adi_boot.env @@ -0,0 +1,122 @@ +/* + * A target board needs to set these variables for the commands below to work: + * + * - adi_stage2_offset, the location of stage2-boot.ldr on the SPI flash + * - adi_image_offset, location of the fitImage on the SPI flash + * - adi_rfs_offset, location of the RFS on the SPI flash + * - loadaddr, where you want to load things + * - jffs2file, name of the jffs2 file for update, ex adsp-sc5xx-tiny-adsp-sc573.jffs2 + */ + +#ifdef CONFIG_SC59X_64 +#define EARLY_PRINTK earlycon=adi_uart,0x31003000 +#else +#define EARLY_PRINTK earlyprintk=serial,uart0,CONFIG_BAUDRATE +#endif + +/* Config options */ +imagefile=fitImage +ethaddr=02:80:ad:20:31:e8 +eth1addr=02:80:ad:20:31:e9 +uart_console=CONFIG_UART_CONSOLE +#ifdef CONFIG_SC59X_64 +fdt_high=0xffffffffffffffff +initrd_high=0xffffffffffffffff +#else +fdt_high=0xffffffff +initrd_high=0xffffffff +#endif + +/* Helper routines */ +init_ethernet=mii info; + dhcp; + setenv serverip ${tftpserverip} + +/* Args for each boot mode */ +adi_bootargs=EARLY_PRINTK console=ttySC0,CONFIG_BAUDRATE vmalloc=512M +ramargs=setenv bootargs ${adi_bootargs} + +addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off + +/* Boot modes are selectable and should be defined in the board env before including */ +#if defined(USE_NFS) +// rootpath is set by CONFIG_ROOTPATH +nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}${rootpath},tcp,nfsvers=3 ${adi_bootargs} +nfsboot=run init_ethernet; + tftp ${loadaddr} ${tftp_dir_prefix}${imagefile}; + run nfsargs; + run addip; + bootm ${loadaddr} +#endif + +#if defined(USE_MMC) +mmcargs=setenv bootargs root=/dev/mmcblk0p1 rw rootfstype=ext4 rootwait ${adi_bootargs} +mmcboot=mmc rescan; + ext4load mmc 0:1 ${loadaddr} /boot/${imagefile}; + run mmcargs; + bootm ${loadaddr} +#endif + +#if defined(USE_SPI) || defined(USE_OSPI) +spiargs=setenv bootargs root=/dev/mtdblock4 rw rootfstype=jffs2 ${adi_bootargs} +spiboot=run spiargs; + sf probe ${sfdev}; + sf read ${loadaddr} ${adi_image_offset} ${imagesize}; + bootm ${loadaddr} +#endif + +#if defined(USE_OSPI) +ospiboot=run spiboot +#endif + +#if defined(USE_RAM) +ramboot=run init_ethernet; + tftp ${loadaddr} ${tfpt_dir_prefix}${imagefile}; + run ramargs; + bootm ${loadaddr} +#endif + +/* Update commands */ +stage1file=stage1-boot.ldr +stage2file=stage2-boot.ldr + +#if defined(USE_SPI) || defined(USE_OSPI) +update_spi_uboot_stage1=tftp ${loadaddr} ${tftp_dir_prefix}${stage1file}; + sf probe ${sfdev}; + sf update ${loadaddr} 0x0 ${filesize} +update_spi_uboot_stage2=tftp ${loadaddr} ${tftp_dir_prefix}${stage2file}; + sf probe ${sfdev}; + sf update ${loadaddr} ${adi_stage2_offset} ${filesize} +update_spi_uboot=run update_spi_uboot_stage1; + run update_spi_uboot_stage2; +update_spi_fit=tftp ${loadaddr} ${tftp_dir_prefix}${imagefile}; + sf probe ${sfdev}; + sf update ${loadaddr} ${adi_image_offset} ${filesize}; + setenv imagesize ${filesize} +update_spi_rfs=tftp ${loadaddr} ${tftp_dir_prefix}${jffs2file}; + sf probe ${sfdev}; + sf update ${loadaddr} ${adi_rfs_offset} ${filesize} + +start_update_spi=run init_ethernet; + run update_spi_uboot; + run update_spi_fit; + run update_spi_rfs; +start_update_spi_uboot_only=run init_ethernet; + run update_spi_uboot; +#endif + +#if defined(USE_SPI) +update_spi=setenv sfdev CONFIG_SC_BOOT_SPI_BUS:CONFIG_SC_BOOT_SPI_SSEL; + setenv bootcmd run spiboot; + setenv argscmd spiargs; + run start_update_spi; + saveenv +#endif + +#if defined(USE_OSPI) +update_ospi=setenv sfdev CONFIG_SC_BOOT_OSPI_BUS:CONFIG_SC_BOOT_OSPI_SSEL; + setenv bootcmd run ospiboot; + setenv argscmd spiargs; + run start_update_spi; + saveenv +#endif diff --git a/include/env_callback.h b/include/env_callback.h index 23bc650c162..8e500aaaf80 100644 --- a/include/env_callback.h +++ b/include/env_callback.h @@ -7,6 +7,7 @@ #ifndef __ENV_CALLBACK_H__ #define __ENV_CALLBACK_H__ +#include #include #include #include diff --git a/include/env_default.h b/include/env_default.h index 8ee500d1709..076ffdd44e9 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -7,6 +7,7 @@ * Andreas Heppel */ +#include #include #include diff --git a/include/env_flags.h b/include/env_flags.h index d785f87cdcb..2476043b0e3 100644 --- a/include/env_flags.h +++ b/include/env_flags.h @@ -7,6 +7,8 @@ #ifndef __ENV_FLAGS_H__ #define __ENV_FLAGS_H__ +#include + enum env_flags_vartype { env_flags_vartype_string, env_flags_vartype_decimal, diff --git a/include/extension_board.h b/include/extension_board.h index 3b75b5ba9f7..87d404c0074 100644 --- a/include/extension_board.h +++ b/include/extension_board.h @@ -7,6 +7,8 @@ #ifndef __EXTENSION_SUPPORT_H #define __EXTENSION_SUPPORT_H +#include + struct extension { struct list_head list; char name[32]; diff --git a/include/flash.h b/include/flash.h index 3710a2731b7..0f736977411 100644 --- a/include/flash.h +++ b/include/flash.h @@ -7,6 +7,8 @@ #ifndef _FLASH_H_ #define _FLASH_H_ +#include + /*----------------------------------------------------------------------- * FLASH Info: contains chip specific data, per FLASH bank */ diff --git a/include/fsl_errata.h b/include/fsl_errata.h index 44547645df8..9f070726acb 100644 --- a/include/fsl_errata.h +++ b/include/fsl_errata.h @@ -7,7 +7,7 @@ #define _FSL_ERRATA_H #if defined(CONFIG_PPC) -#include +#include #elif defined(CONFIG_ARCH_LS1021A) #include #elif defined(CONFIG_FSL_LAYERSCAPE) diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index f9a0a7017d4..4991d932200 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -12,6 +12,8 @@ #include #ifdef CONFIG_ARM #include +#else +#include #endif #define FSL_IFC_V1_1_0 0x01010000 diff --git a/include/fsl_immap.h b/include/fsl_immap.h index 5297c0b3f9b..54d6e0ab377 100644 --- a/include/fsl_immap.h +++ b/include/fsl_immap.h @@ -7,6 +7,9 @@ #ifndef __FSL_IMMAP_H #define __FSL_IMMAP_H + +#include + /* * DDR memory controller registers * This structure works for mpc83xx (DDR2 and DDR3), mpc85xx, mpc86xx. diff --git a/include/fuse.h b/include/fuse.h index d48dcdfa647..4519821af7e 100644 --- a/include/fuse.h +++ b/include/fuse.h @@ -11,6 +11,8 @@ #ifndef _FUSE_H_ #define _FUSE_H_ +#include + /* * Read/Sense/Program/Override interface: * bank: Fuse bank diff --git a/include/gzip.h b/include/gzip.h index e578b283edc..5e0d0ec07fb 100644 --- a/include/gzip.h +++ b/include/gzip.h @@ -7,6 +7,8 @@ #ifndef __GZIP_H #define __GZIP_H +#include + struct blk_desc; /** diff --git a/include/handoff.h b/include/handoff.h index 0104b834f2c..c0ae7b19a75 100644 --- a/include/handoff.h +++ b/include/handoff.h @@ -10,6 +10,7 @@ #if CONFIG_IS_ENABLED(HANDOFF) +#include #include /** diff --git a/include/i2c_eeprom.h b/include/i2c_eeprom.h index cba991e3574..1fe32d2dd68 100644 --- a/include/i2c_eeprom.h +++ b/include/i2c_eeprom.h @@ -7,6 +7,7 @@ #define __I2C_EEPROM #include +#include struct udevice; diff --git a/include/init.h b/include/init.h index 630d86729c4..2c10171359c 100644 --- a/include/init.h +++ b/include/init.h @@ -401,6 +401,8 @@ void bdinfo_print_size(const char *name, uint64_t size); /* Show arch-specific information for the 'bd' command */ void arch_print_bdinfo(void); +struct cmd_tbl; + int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); #endif /* __ASSEMBLY__ */ diff --git a/include/jffs2/load_kernel.h b/include/jffs2/load_kernel.h index 9346d7ee9f1..fa4600e84fc 100644 --- a/include/jffs2/load_kernel.h +++ b/include/jffs2/load_kernel.h @@ -10,6 +10,7 @@ *-----------------------------------------------------------------------*/ #include +#include /* mtd device types */ #define MTD_DEV_TYPE_NOR 0x0001 diff --git a/include/libata.h b/include/libata.h index a55e9315a73..fa39d21a44a 100644 --- a/include/libata.h +++ b/include/libata.h @@ -10,6 +10,7 @@ #ifndef __LIBATA_H__ #define __LIBATA_H__ +#include enum { /* various global constants */ diff --git a/include/linux/compat.h b/include/linux/compat.h index f8e3570d1ad..62381451617 100644 --- a/include/linux/compat.h +++ b/include/linux/compat.h @@ -5,6 +5,7 @@ #include #include #include +#include #include diff --git a/include/linux/mtd/omap_gpmc.h b/include/linux/mtd/omap_gpmc.h index f08e700a1da..2dbf988863f 100644 --- a/include/linux/mtd/omap_gpmc.h +++ b/include/linux/mtd/omap_gpmc.h @@ -8,6 +8,8 @@ #ifndef __ASM_OMAP_GPMC_H #define __ASM_OMAP_GPMC_H +#include + /* Maximum Number of Chip Selects */ #define GPMC_CS_NUM 8 diff --git a/include/mailbox.h b/include/mailbox.h index 323b6c2bc5d..e70266fb61c 100644 --- a/include/mailbox.h +++ b/include/mailbox.h @@ -6,6 +6,8 @@ #ifndef _MAILBOX_H #define _MAILBOX_H +#include + /** * A mailbox is a hardware mechanism for transferring small fixed-size messages * and/or notifications between the CPU on which U-Boot runs and some other diff --git a/include/mmc.h b/include/mmc.h index 4b8327f1f93..7f1900363b9 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -18,13 +18,6 @@ struct bd_info; -#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) -#define MMC_SUPPORTS_TUNING -#endif -#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) -#define MMC_SUPPORTS_TUNING -#endif - /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */ #define SD_VERSION_SD (1U << 31) #define MMC_VERSION_MMC (1U << 30) @@ -485,7 +478,7 @@ struct dm_mmc_ops { */ int (*get_wp)(struct udevice *dev); -#ifdef MMC_SUPPORTS_TUNING +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) /** * execute_tuning() - Start the tuning process * diff --git a/include/mpc85xx.h b/include/mpc85xx.h index 636734dd3c6..ff86c7c12e0 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -6,6 +6,7 @@ #ifndef __MPC85xx_H__ #define __MPC85xx_H__ +#include #if defined(CONFIG_E500) #include #endif diff --git a/include/nand.h b/include/nand.h index 220ffa202ef..cdba7384ad1 100644 --- a/include/nand.h +++ b/include/nand.h @@ -8,8 +8,6 @@ #ifndef _NAND_H_ #define _NAND_H_ -#include - extern void nand_init(void); void nand_reinit(void); unsigned long nand_size(void); diff --git a/include/netdev.h b/include/netdev.h index 2a7f40e5040..2a06d9a261b 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -10,9 +10,12 @@ #ifndef _NETDEV_H_ #define _NETDEV_H_ + +#include #include struct udevice; +struct bd_info; /* * Board and CPU-specific initialization functions diff --git a/include/pci.h b/include/pci.h index aad233769a3..ea3b73923d6 100644 --- a/include/pci.h +++ b/include/pci.h @@ -520,6 +520,7 @@ #ifndef __ASSEMBLY__ +#include #include #ifdef CONFIG_SYS_PCI_64BIT diff --git a/include/phy_interface.h b/include/phy_interface.h index 31be3228c7c..b74f4ccd84a 100644 --- a/include/phy_interface.h +++ b/include/phy_interface.h @@ -11,6 +11,7 @@ #define _PHY_INTERFACE_H #include +#include typedef enum { PHY_INTERFACE_MODE_NA, /* don't touch */ diff --git a/include/ram.h b/include/ram.h index 2fc971df465..3600bb57a6c 100644 --- a/include/ram.h +++ b/include/ram.h @@ -7,6 +7,8 @@ #ifndef __RAM_H #define __RAM_H +#include + struct udevice; struct ram_info { diff --git a/include/s_record.h b/include/s_record.h index 3ece695941d..aab09d9c3c8 100644 --- a/include/s_record.h +++ b/include/s_record.h @@ -4,6 +4,8 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include + /*-------------------------------------------------------------------------- * * Motorola S-Record Format: diff --git a/include/sm.h b/include/sm.h index afa9c89055e..fbc156ad68a 100644 --- a/include/sm.h +++ b/include/sm.h @@ -19,7 +19,7 @@ * implementation of the driver you are using. */ -#include +#include #include struct udevice; diff --git a/include/splash.h b/include/splash.h index c3922375987..83c6fa9767f 100644 --- a/include/splash.h +++ b/include/splash.h @@ -23,6 +23,7 @@ #define _SPLASH_H_ #include +#include enum splash_storage { SPLASH_STORAGE_NAND, diff --git a/include/u-boot/sha1.h b/include/u-boot/sha1.h index 09fee594d26..c1e9f67068d 100644 --- a/include/u-boot/sha1.h +++ b/include/u-boot/sha1.h @@ -14,6 +14,8 @@ #ifndef _SHA1_H #define _SHA1_H +#include + #ifdef __cplusplus extern "C" { #endif diff --git a/include/u-boot/sha256.h b/include/u-boot/sha256.h index 9aa1251789a..a4fe176c0b4 100644 --- a/include/u-boot/sha256.h +++ b/include/u-boot/sha256.h @@ -1,6 +1,8 @@ #ifndef _SHA256_H #define _SHA256_H +#include + #define SHA256_SUM_LEN 32 #define SHA256_DER_LEN 19 diff --git a/include/u-boot/sha512.h b/include/u-boot/sha512.h index 516729d7750..90bd96a3f8c 100644 --- a/include/u-boot/sha512.h +++ b/include/u-boot/sha512.h @@ -1,6 +1,8 @@ #ifndef _SHA512_H #define _SHA512_H +#include + #define SHA384_SUM_LEN 48 #define SHA384_DER_LEN 19 #define SHA512_SUM_LEN 64 diff --git a/include/virtio.h b/include/virtio.h index 8113a59d795..17f894a79e3 100644 --- a/include/virtio.h +++ b/include/virtio.h @@ -24,6 +24,7 @@ #include #include #include +#include #define VIRTIO_ID_NET 1 /* virtio net */ #define VIRTIO_ID_BLOCK 2 /* virtio block */ #define VIRTIO_ID_RNG 4 /* virtio rng */ diff --git a/include/xen/events.h b/include/xen/events.h index 82bd18b48c8..f0a8ef32d00 100644 --- a/include/xen/events.h +++ b/include/xen/events.h @@ -15,6 +15,7 @@ #ifndef _EVENTS_H_ #define _EVENTS_H_ +#include #include #include diff --git a/net/arp.c b/net/arp.c index 37848ad32fb..bc1e25f941f 100644 --- a/net/arp.c +++ b/net/arp.c @@ -9,10 +9,10 @@ * Copyright 2000-2002 Wolfgang Denk, wd@denx.de */ -#include #include #include #include +#include #include #include "arp.h" diff --git a/net/bootp.c b/net/bootp.c index 86c56803c76..9dfb50749b4 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -8,7 +8,6 @@ * Copyright 2000-2004 Wolfgang Denk, wd@denx.de */ -#include #include #include #include diff --git a/net/cdp.c b/net/cdp.c index a8f890e7522..d4cfc587ee3 100644 --- a/net/cdp.c +++ b/net/cdp.c @@ -9,7 +9,6 @@ * Copyright 2000-2002 Wolfgang Denk, wd@denx.de */ -#include #include #include "cdp.h" diff --git a/net/dhcpv6.c b/net/dhcpv6.c index 4aea779f6f2..54619ee6983 100644 --- a/net/dhcpv6.c +++ b/net/dhcpv6.c @@ -7,7 +7,6 @@ /* Simple DHCP6 network layer implementation. */ -#include #include #include #include diff --git a/net/dns.c b/net/dns.c index 5b1fe5b0103..c2f0ab98c8d 100644 --- a/net/dns.c +++ b/net/dns.c @@ -22,7 +22,6 @@ * this stuff is worth it, you can buy me a beer in return. */ -#include #include #include #include diff --git a/net/eth-uclass.c b/net/eth-uclass.c index 193218a328b..e34d7af0229 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY UCLASS_ETH -#include #include #include #include diff --git a/net/eth_bootdev.c b/net/eth_bootdev.c index 869adf8cbbd..6ee54e3c790 100644 --- a/net/eth_bootdev.c +++ b/net/eth_bootdev.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_BOOTSTD -#include #include #include #include diff --git a/net/eth_common.c b/net/eth_common.c index 14d4c07b695..89b5bb37189 100644 --- a/net/eth_common.c +++ b/net/eth_common.c @@ -5,7 +5,6 @@ * Joe Hershberger, National Instruments */ -#include #include #include #include diff --git a/net/fastboot_tcp.c b/net/fastboot_tcp.c index 2eb52ea2567..d1fccbc7238 100644 --- a/net/fastboot_tcp.c +++ b/net/fastboot_tcp.c @@ -3,7 +3,6 @@ * Copyright (C) 2023 The Android Open Source Project */ -#include #include #include #include diff --git a/net/fastboot_udp.c b/net/fastboot_udp.c index 6fee441ab3b..d1479510d61 100644 --- a/net/fastboot_udp.c +++ b/net/fastboot_udp.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 The Android Open Source Project */ -#include #include #include #include diff --git a/net/link_local.c b/net/link_local.c index 8aec3c79969..179721333ff 100644 --- a/net/link_local.c +++ b/net/link_local.c @@ -11,7 +11,6 @@ * Licensed under the GPL v2 or later */ -#include #include #include #include diff --git a/net/mdio-mux-uclass.c b/net/mdio-mux-uclass.c index 94b90e06576..ee188b504d1 100644 --- a/net/mdio-mux-uclass.c +++ b/net/mdio-mux-uclass.c @@ -4,7 +4,6 @@ * Alex Marginean, NXP */ -#include #include #include #include diff --git a/net/mdio-uclass.c b/net/mdio-uclass.c index 0ebfb2f1343..4f052ae432c 100644 --- a/net/mdio-uclass.c +++ b/net/mdio-uclass.c @@ -4,7 +4,6 @@ * Alex Marginean, NXP */ -#include #include #include #include diff --git a/net/ndisc.c b/net/ndisc.c index d1cec0601c8..d417c5987ac 100644 --- a/net/ndisc.c +++ b/net/ndisc.c @@ -9,7 +9,6 @@ /* Neighbour Discovery for IPv6 */ -#include #include #include #include diff --git a/net/net.c b/net/net.c index 0fb2d250773..23b5d3356af 100644 --- a/net/net.c +++ b/net/net.c @@ -81,7 +81,6 @@ */ -#include #include #include #include diff --git a/net/net6.c b/net/net6.c index 2dd64c0e161..4cff98df15c 100644 --- a/net/net6.c +++ b/net/net6.c @@ -9,12 +9,12 @@ /* Simple IPv6 network layer implementation */ -#include #include #include #include #include #include +#include /* NULL IPv6 address */ struct in6_addr const net_null_addr_ip6 = ZERO_IPV6_ADDR; diff --git a/net/nfs.c b/net/nfs.c index c18282448cc..acc7106f10d 100644 --- a/net/nfs.c +++ b/net/nfs.c @@ -30,7 +30,6 @@ * September 27, 2018. As of now, NFSv3 is the default choice. If the server * does not support NFSv3, we fall back to versions 2 or 1. */ -#include #include #include #ifdef CONFIG_SYS_DIRECT_FLASH_NFS diff --git a/net/pcap.c b/net/pcap.c index 4036d8a3fa5..c959e3e4e51 100644 --- a/net/pcap.c +++ b/net/pcap.c @@ -3,10 +3,10 @@ * Copyright 2019 Ramon Fried */ -#include #include #include #include +#include #include #define LINKTYPE_ETHERNET 1 diff --git a/net/ping6.c b/net/ping6.c index 4882a17f510..2479e08fd82 100644 --- a/net/ping6.c +++ b/net/ping6.c @@ -9,7 +9,6 @@ /* Simple ping6 implementation */ -#include #include #include #include "ndisc.h" diff --git a/net/rarp.c b/net/rarp.c index 231b6233c07..a6b564e314d 100644 --- a/net/rarp.c +++ b/net/rarp.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include diff --git a/net/sntp.c b/net/sntp.c index dac0f8ceea1..73d1d87d38b 100644 --- a/net/sntp.c +++ b/net/sntp.c @@ -5,7 +5,6 @@ * */ -#include #include #include #include diff --git a/net/tcp.c b/net/tcp.c index a713e1dd609..b0cc8a1fe3e 100644 --- a/net/tcp.c +++ b/net/tcp.c @@ -17,7 +17,6 @@ * - TCP application (eg wget) * Next Step HTTPS? */ -#include #include #include #include diff --git a/net/tftp.c b/net/tftp.c index 2e335413492..6b16bdcbe4c 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -5,7 +5,6 @@ * Copyright 2011 Comelit Group SpA, * Luca Ceresoli */ -#include #include #include #include diff --git a/net/udp.c b/net/udp.c index a93822f511c..37162260d17 100644 --- a/net/udp.c +++ b/net/udp.c @@ -3,7 +3,6 @@ * Copyright (C) 2020 Philippe Reynes */ -#include #include #include diff --git a/net/wget.c b/net/wget.c index abab371e58e..f1dd7abeff6 100644 --- a/net/wget.c +++ b/net/wget.c @@ -6,7 +6,6 @@ #include #include -#include #include #include #include diff --git a/net/wol.c b/net/wol.c index 0a625668a99..96478ba5751 100644 --- a/net/wol.c +++ b/net/wol.c @@ -3,7 +3,6 @@ * Copyright 2018 Lothar Felten, lothar.felten@gmail.com */ -#include #include #include #include diff --git a/post/cpu/mpc83xx/ecc.c b/post/cpu/mpc83xx/ecc.c index 68da8ff4171..766eafa00e7 100644 --- a/post/cpu/mpc83xx/ecc.c +++ b/post/cpu/mpc83xx/ecc.c @@ -8,7 +8,7 @@ * Dave Liu */ -#include +#include #include #include #include diff --git a/post/drivers/flash.c b/post/drivers/flash.c index a1fcf1f135d..21e2f940fe9 100644 --- a/post/drivers/flash.c +++ b/post/drivers/flash.c @@ -7,7 +7,7 @@ */ #if CFG_POST & CFG_SYS_POST_FLASH -#include +#include #include #include #include diff --git a/post/drivers/i2c.c b/post/drivers/i2c.c index 557d6329a4f..11c3c832352 100644 --- a/post/drivers/i2c.c +++ b/post/drivers/i2c.c @@ -21,7 +21,7 @@ * #endif */ -#include +#include #include #include #include diff --git a/post/drivers/memory.c b/post/drivers/memory.c index 1be2b41df45..8d4ae6fc6f1 100644 --- a/post/drivers/memory.c +++ b/post/drivers/memory.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include diff --git a/post/drivers/rtc.c b/post/drivers/rtc.c index cc7a49847cc..030954ef3dc 100644 --- a/post/drivers/rtc.c +++ b/post/drivers/rtc.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include /* * RTC test diff --git a/post/lib_powerpc/andi.c b/post/lib_powerpc/andi.c index 4f302166880..3f525f51676 100644 --- a/post/lib_powerpc/andi.c +++ b/post/lib_powerpc/andi.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/b.c b/post/lib_powerpc/b.c index 0ec032dcb15..9c9931c4f3a 100644 --- a/post/lib_powerpc/b.c +++ b/post/lib_powerpc/b.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/cmp.c b/post/lib_powerpc/cmp.c index 57f2b9694c3..9237dd53997 100644 --- a/post/lib_powerpc/cmp.c +++ b/post/lib_powerpc/cmp.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/cmpi.c b/post/lib_powerpc/cmpi.c index 6e2bd636d74..6436586b291 100644 --- a/post/lib_powerpc/cmpi.c +++ b/post/lib_powerpc/cmpi.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/complex.c b/post/lib_powerpc/complex.c index 751bce67378..2899dece2c1 100644 --- a/post/lib_powerpc/complex.c +++ b/post/lib_powerpc/complex.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/cpu.c b/post/lib_powerpc/cpu.c index 98a8c6392c3..e41e6b3b97b 100644 --- a/post/lib_powerpc/cpu.c +++ b/post/lib_powerpc/cpu.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/cr.c b/post/lib_powerpc/cr.c index 3c7b6113846..1e011f12159 100644 --- a/post/lib_powerpc/cr.c +++ b/post/lib_powerpc/cr.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/fpu/20001122-1.c b/post/lib_powerpc/fpu/20001122-1.c index 9c1c886fc4f..d6b7bc656f6 100644 --- a/post/lib_powerpc/fpu/20001122-1.c +++ b/post/lib_powerpc/fpu/20001122-1.c @@ -7,7 +7,7 @@ * This file is originally a part of the GCC testsuite. */ -#include +#include #include diff --git a/post/lib_powerpc/fpu/20010114-2.c b/post/lib_powerpc/fpu/20010114-2.c index 01bac500383..5e79c4c6984 100644 --- a/post/lib_powerpc/fpu/20010114-2.c +++ b/post/lib_powerpc/fpu/20010114-2.c @@ -7,7 +7,7 @@ * This file is originally a part of the GCC testsuite. */ -#include +#include #include diff --git a/post/lib_powerpc/fpu/20010226-1.c b/post/lib_powerpc/fpu/20010226-1.c index cc4aa0dca64..a65ffcedb49 100644 --- a/post/lib_powerpc/fpu/20010226-1.c +++ b/post/lib_powerpc/fpu/20010226-1.c @@ -7,7 +7,7 @@ * This file is originally a part of the GCC testsuite. */ -#include +#include #include diff --git a/post/lib_powerpc/fpu/980619-1.c b/post/lib_powerpc/fpu/980619-1.c index 111a2013fb5..8ad256efa9f 100644 --- a/post/lib_powerpc/fpu/980619-1.c +++ b/post/lib_powerpc/fpu/980619-1.c @@ -7,7 +7,7 @@ * This file is originally a part of the GCC testsuite. */ -#include +#include #include diff --git a/post/lib_powerpc/fpu/acc1.c b/post/lib_powerpc/fpu/acc1.c index 63cc3eeafc3..408c391ce42 100644 --- a/post/lib_powerpc/fpu/acc1.c +++ b/post/lib_powerpc/fpu/acc1.c @@ -7,7 +7,7 @@ * This file is originally a part of the GCC testsuite. */ -#include +#include #include diff --git a/post/lib_powerpc/fpu/compare-fp-1.c b/post/lib_powerpc/fpu/compare-fp-1.c index 4b4589664f1..4b8537ea3db 100644 --- a/post/lib_powerpc/fpu/compare-fp-1.c +++ b/post/lib_powerpc/fpu/compare-fp-1.c @@ -9,7 +9,7 @@ * This file is originally a part of the GCC testsuite. */ -#include +#include #include diff --git a/post/lib_powerpc/fpu/fpu.c b/post/lib_powerpc/fpu/fpu.c index 59109f71e36..2afe27ab355 100644 --- a/post/lib_powerpc/fpu/fpu.c +++ b/post/lib_powerpc/fpu/fpu.c @@ -6,7 +6,7 @@ * Author: Sergei Poselenov */ -#include +#include /* * FPU test diff --git a/post/lib_powerpc/fpu/mul-subnormal-single-1.c b/post/lib_powerpc/fpu/mul-subnormal-single-1.c index 891aa95685f..6b86e55e409 100644 --- a/post/lib_powerpc/fpu/mul-subnormal-single-1.c +++ b/post/lib_powerpc/fpu/mul-subnormal-single-1.c @@ -9,7 +9,7 @@ * numbers) are rounded to within 0.5 ulp. PR other/14354. */ -#include +#include #include diff --git a/post/lib_powerpc/load.c b/post/lib_powerpc/load.c index e4ac6bf186f..0a2a4222846 100644 --- a/post/lib_powerpc/load.c +++ b/post/lib_powerpc/load.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/multi.c b/post/lib_powerpc/multi.c index 4df45790ab6..6f991443741 100644 --- a/post/lib_powerpc/multi.c +++ b/post/lib_powerpc/multi.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include diff --git a/post/lib_powerpc/rlwimi.c b/post/lib_powerpc/rlwimi.c index da219132257..35a9e9b83bf 100644 --- a/post/lib_powerpc/rlwimi.c +++ b/post/lib_powerpc/rlwimi.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/rlwinm.c b/post/lib_powerpc/rlwinm.c index b0b976f98af..2995eb358ef 100644 --- a/post/lib_powerpc/rlwinm.c +++ b/post/lib_powerpc/rlwinm.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/rlwnm.c b/post/lib_powerpc/rlwnm.c index 22cd4568fc8..3ba3a7607ab 100644 --- a/post/lib_powerpc/rlwnm.c +++ b/post/lib_powerpc/rlwnm.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/srawi.c b/post/lib_powerpc/srawi.c index a103df75eb1..bd59ac4f36b 100644 --- a/post/lib_powerpc/srawi.c +++ b/post/lib_powerpc/srawi.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/store.c b/post/lib_powerpc/store.c index 71a4b6aba43..470ea37e77d 100644 --- a/post/lib_powerpc/store.c +++ b/post/lib_powerpc/store.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/string.c b/post/lib_powerpc/string.c index 21e02bcb266..c4ea5cf9ba9 100644 --- a/post/lib_powerpc/string.c +++ b/post/lib_powerpc/string.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/three.c b/post/lib_powerpc/three.c index 68339b05ef2..e65d7f023f9 100644 --- a/post/lib_powerpc/three.c +++ b/post/lib_powerpc/three.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/threei.c b/post/lib_powerpc/threei.c index 885dd8cb095..0c3a2e6674b 100644 --- a/post/lib_powerpc/threei.c +++ b/post/lib_powerpc/threei.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/threex.c b/post/lib_powerpc/threex.c index 62ac713ecff..24ebc98d48d 100644 --- a/post/lib_powerpc/threex.c +++ b/post/lib_powerpc/threex.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/two.c b/post/lib_powerpc/two.c index 7985669ba6e..28c70ec8897 100644 --- a/post/lib_powerpc/two.c +++ b/post/lib_powerpc/two.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/twox.c b/post/lib_powerpc/twox.c index 33d1a1d8d91..7f6a898d639 100644 --- a/post/lib_powerpc/twox.c +++ b/post/lib_powerpc/twox.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/post.c b/post/post.c index 946d9094d45..705f94ccc91 100644 --- a/post/post.c +++ b/post/post.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include diff --git a/post/tests.c b/post/tests.c index 8cea428fcdc..208710a48ba 100644 --- a/post/tests.c +++ b/post/tests.c @@ -4,7 +4,8 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include +#include #include diff --git a/scripts/Makefile.autoconf b/scripts/Makefile.autoconf index 8208ffe2274..b42f9b525fe 100644 --- a/scripts/Makefile.autoconf +++ b/scripts/Makefile.autoconf @@ -45,7 +45,7 @@ c_flags := $(KBUILD_CFLAGS) $(KBUILD_CPPFLAGS) $(PLATFORM_CPPFLAGS) \ quiet_cmd_autoconf_dep = GEN $@ cmd_autoconf_dep = $(CC) -x c -DDO_DEPS_ONLY -M -MP $(c_flags) \ - -MQ include/config/auto.conf $(srctree)/include/common.h > $@ || { \ + -MQ include/config/auto.conf include/config.h > $@ || { \ rm $@; false; \ } include/autoconf.mk.dep: include/config.h FORCE @@ -70,7 +70,7 @@ quiet_cmd_autoconf = GEN $@ quiet_cmd_u_boot_cfg = CFG $@ cmd_u_boot_cfg = \ - $(CPP) $(c_flags) $2 -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && { \ + $(CPP) $(c_flags) $2 -DDO_DEPS_ONLY -dM include/config.h > $@.tmp && { \ grep 'define CONFIG_' $@.tmp | \ sed '/define CONFIG_IS_ENABLED(/d;/define CONFIG_IF_ENABLED_INT(/d;/define CONFIG_VAL(/d;' > $@; \ rm $@.tmp; \ diff --git a/scripts/gen_ll_addressable_symbols.sh b/scripts/gen_ll_addressable_symbols.sh index d0864804aaf..13f670ae0ef 100755 --- a/scripts/gen_ll_addressable_symbols.sh +++ b/scripts/gen_ll_addressable_symbols.sh @@ -10,6 +10,6 @@ set -e -echo '#include ' +echo '#include ' $@ 2>/dev/null | grep -oe '_u_boot_list_2_[a-zA-Z0-9_]*_2_[a-zA-Z0-9_]*' | \ sort -u | sed -e 's/^\(.*\)/extern char \1[];\n__ADDRESSABLE(\1);/' diff --git a/test/bloblist.c b/test/bloblist.c index 1c60bbac36c..7c63682908a 100644 --- a/test/bloblist.c +++ b/test/bloblist.c @@ -3,7 +3,6 @@ * Copyright (c) 2018, Google Inc. All rights reserved. */ -#include #include #include #include diff --git a/test/boot/bootdev.c b/test/boot/bootdev.c index 0702fccdae6..6e940002f84 100644 --- a/test/boot/bootdev.c +++ b/test/boot/bootdev.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c index 674d4c05f83..4511cfa7f9b 100644 --- a/test/boot/bootflow.c +++ b/test/boot/bootflow.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/boot/bootmeth.c b/test/boot/bootmeth.c index e498eee036e..113b789ea79 100644 --- a/test/boot/bootmeth.c +++ b/test/boot/bootmeth.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/boot/bootstd_common.c b/test/boot/bootstd_common.c index cc97e255e5c..e50539500a0 100644 --- a/test/boot/bootstd_common.c +++ b/test/boot/bootstd_common.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/boot/cedit.c b/test/boot/cedit.c index aa417190486..fd19da0a0c0 100644 --- a/test/boot/cedit.c +++ b/test/boot/cedit.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/boot/expo.c b/test/boot/expo.c index 714fdfa415d..6ea0184373d 100644 --- a/test/boot/expo.c +++ b/test/boot/expo.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/boot/image.c b/test/boot/image.c index 2844b057859..0894e30587f 100644 --- a/test/boot/image.c +++ b/test/boot/image.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/boot/measurement.c b/test/boot/measurement.c index 9db2ed324c2..29be495412d 100644 --- a/test/boot/measurement.c +++ b/test/boot/measurement.c @@ -6,7 +6,6 @@ * Written by Eddie James */ -#include #include #include #include diff --git a/test/boot/vbe_fixup.c b/test/boot/vbe_fixup.c index eba5c4ebe6c..540816e42b0 100644 --- a/test/boot/vbe_fixup.c +++ b/test/boot/vbe_fixup.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/boot/vbe_simple.c b/test/boot/vbe_simple.c index 5e61840652c..3672b744e5f 100644 --- a/test/boot/vbe_simple.c +++ b/test/boot/vbe_simple.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/bootm.c b/test/bootm.c index 4bb3ca0655c..26c15552bf6 100644 --- a/test/bootm.c +++ b/test/bootm.c @@ -5,7 +5,6 @@ * Copyright 2020 Google LLC */ -#include #include #include #include diff --git a/test/cmd/addrmap.c b/test/cmd/addrmap.c index 1eb5955db17..7b8f49fd375 100644 --- a/test/cmd/addrmap.c +++ b/test/cmd/addrmap.c @@ -5,7 +5,6 @@ * Copyright (C) 2021, Bin Meng */ -#include #include #include #include diff --git a/test/cmd/armffa.c b/test/cmd/armffa.c index 9a44a397e8a..38f40b72f5e 100644 --- a/test/cmd/armffa.c +++ b/test/cmd/armffa.c @@ -8,7 +8,6 @@ * Abdellatif El Khlifi */ -#include #include #include #include diff --git a/test/cmd/bdinfo.c b/test/cmd/bdinfo.c index 4977d01f62d..027848c3e24 100644 --- a/test/cmd/bdinfo.c +++ b/test/cmd/bdinfo.c @@ -5,7 +5,6 @@ * Copyright 2023 Marek Vasut */ -#include #include #include #include diff --git a/test/cmd/exit.c b/test/cmd/exit.c index 7e160f7e4bb..d310ec8531b 100644 --- a/test/cmd/exit.c +++ b/test/cmd/exit.c @@ -5,7 +5,6 @@ * Copyright 2022 Marek Vasut */ -#include #include #include #include diff --git a/test/cmd/fdt.c b/test/cmd/fdt.c index 54708552175..a0faf5aca90 100644 --- a/test/cmd/fdt.c +++ b/test/cmd/fdt.c @@ -5,7 +5,6 @@ * Copyright 2022 Google LLC */ -#include #include #include #include diff --git a/test/cmd/font.c b/test/cmd/font.c index 1fe05c1ead5..a8905ce617e 100644 --- a/test/cmd/font.c +++ b/test/cmd/font.c @@ -5,7 +5,6 @@ * Copyright 2022 Google LLC */ -#include #include #include #include diff --git a/test/cmd/history.c b/test/cmd/history.c index 06517fcdbb5..6964bfa9e1e 100644 --- a/test/cmd/history.c +++ b/test/cmd/history.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/cmd/loadm.c b/test/cmd/loadm.c index 41e005ac592..dff8a97d139 100644 --- a/test/cmd/loadm.c +++ b/test/cmd/loadm.c @@ -9,7 +9,6 @@ * Rui Miguel Silva */ -#include #include #include #include diff --git a/test/cmd/mem.c b/test/cmd/mem.c index d76f47cf311..f1bbab6055b 100644 --- a/test/cmd/mem.c +++ b/test/cmd/mem.c @@ -5,7 +5,6 @@ * Copyright 2020 Google LLC */ -#include #include #include #include diff --git a/test/cmd/mem_search.c b/test/cmd/mem_search.c index f80c9c40687..55ad2fac1e3 100644 --- a/test/cmd/mem_search.c +++ b/test/cmd/mem_search.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/cmd/pci_mps.c b/test/cmd/pci_mps.c index fd96f4fba6c..2a64143eecd 100644 --- a/test/cmd/pci_mps.c +++ b/test/cmd/pci_mps.c @@ -7,7 +7,6 @@ * Written by Stephen Carlson */ -#include #include #include #include diff --git a/test/cmd/pinmux.c b/test/cmd/pinmux.c index df40bb77435..4253baa5646 100644 --- a/test/cmd/pinmux.c +++ b/test/cmd/pinmux.c @@ -5,7 +5,6 @@ * Copyright (C) 2021, STMicroelectronics - All Rights Reserved */ -#include #include #include #include diff --git a/test/cmd/rw.c b/test/cmd/rw.c index 98302bf047b..edd762e4d58 100644 --- a/test/cmd/rw.c +++ b/test/cmd/rw.c @@ -3,7 +3,6 @@ * Tests for read and write commands */ -#include #include #include #include diff --git a/test/cmd/seama.c b/test/cmd/seama.c index b1b56930c64..b60f6550b13 100644 --- a/test/cmd/seama.c +++ b/test/cmd/seama.c @@ -5,7 +5,6 @@ * Copyright (C) 2021 Linus Walleij */ -#include #include #include #include diff --git a/test/cmd/setexpr.c b/test/cmd/setexpr.c index ee329e94b85..d50ce5803c3 100644 --- a/test/cmd/setexpr.c +++ b/test/cmd/setexpr.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/cmd/temperature.c b/test/cmd/temperature.c index 2a1ea0611dc..364972626b1 100644 --- a/test/cmd/temperature.c +++ b/test/cmd/temperature.c @@ -5,7 +5,6 @@ * Copyright (C) 2022 Sartura Ltd. */ -#include #include #include #include diff --git a/test/cmd/test_echo.c b/test/cmd/test_echo.c index 091e4f823c9..cde74ebeb61 100644 --- a/test/cmd/test_echo.c +++ b/test/cmd/test_echo.c @@ -5,7 +5,6 @@ * Copyright 2020, Heinrich Schuchadt */ -#include #include #include #include diff --git a/test/cmd/test_pause.c b/test/cmd/test_pause.c index 2b85cce3271..3703290350b 100644 --- a/test/cmd/test_pause.c +++ b/test/cmd/test_pause.c @@ -5,7 +5,6 @@ * Copyright 2022, Samuel Dionne-Riel */ -#include #include #include #include diff --git a/test/cmd/wget.c b/test/cmd/wget.c index ed83fc94a5e..356a4dcd8fa 100644 --- a/test/cmd/wget.c +++ b/test/cmd/wget.c @@ -6,7 +6,6 @@ * Ying-Chun Liu (PaulLiu) */ -#include #include #include #include diff --git a/test/cmd_ut.c b/test/cmd_ut.c index 0677ce0cd17..4e4aa8f1cb2 100644 --- a/test/cmd_ut.c +++ b/test/cmd_ut.c @@ -4,9 +4,9 @@ * Joe Hershberger, National Instruments, joe.hershberger@ni.com */ -#include #include #include +#include #include #include #include diff --git a/test/command_ut.c b/test/command_ut.c index a74bd109e15..2b8d28d7ae3 100644 --- a/test/command_ut.c +++ b/test/command_ut.c @@ -5,7 +5,6 @@ #define DEBUG -#include #include #include #include diff --git a/test/common/cmd_ut_common.c b/test/common/cmd_ut_common.c index 2c0267801b2..2f03a58af47 100644 --- a/test/common/cmd_ut_common.c +++ b/test/common/cmd_ut_common.c @@ -6,7 +6,6 @@ * Unit tests for common functions */ -#include #include #include #include diff --git a/test/common/cread.c b/test/common/cread.c index 4edc7739604..e159caed041 100644 --- a/test/common/cread.c +++ b/test/common/cread.c @@ -3,8 +3,8 @@ * Copyright 2023 Google LLC */ -#include #include +#include #include #include #include diff --git a/test/common/cyclic.c b/test/common/cyclic.c index 6e758e89dbd..461f8cf91f4 100644 --- a/test/common/cyclic.c +++ b/test/common/cyclic.c @@ -3,7 +3,6 @@ * Copyright (C) 2022 Stefan Roese */ -#include #include #include #include diff --git a/test/common/event.c b/test/common/event.c index b462694fc3b..de433d34f22 100644 --- a/test/common/event.c +++ b/test/common/event.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/common/test_autoboot.c b/test/common/test_autoboot.c index 42a1e4ab1fa..4ba1dcc8091 100644 --- a/test/common/test_autoboot.c +++ b/test/common/test_autoboot.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/test/compression.c b/test/compression.c index 3df90819a1f..aa1d38bb7bc 100644 --- a/test/compression.c +++ b/test/compression.c @@ -3,7 +3,6 @@ * Copyright (c) 2013, The Chromium Authors */ -#include #include #include #include diff --git a/test/dm/acpi.c b/test/dm/acpi.c index f14b3962f84..4db2171a4b1 100644 --- a/test/dm/acpi.c +++ b/test/dm/acpi.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/dm/acpi_dp.c b/test/dm/acpi_dp.c index 44bcabda6bc..87bd8ae6749 100644 --- a/test/dm/acpi_dp.c +++ b/test/dm/acpi_dp.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c index 15b2b6f64a0..7113219792e 100644 --- a/test/dm/acpigen.c +++ b/test/dm/acpigen.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/dm/adc.c b/test/dm/adc.c index 740167e16b8..a26a677074a 100644 --- a/test/dm/adc.c +++ b/test/dm/adc.c @@ -6,7 +6,6 @@ * Przemyslaw Marczak */ -#include #include #include #include diff --git a/test/dm/audio.c b/test/dm/audio.c index add15ae20e0..3d1d821f323 100644 --- a/test/dm/audio.c +++ b/test/dm/audio.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/dm/axi.c b/test/dm/axi.c index dc029df5e44..0900a9b5485 100644 --- a/test/dm/axi.c +++ b/test/dm/axi.c @@ -4,7 +4,6 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ -#include #include #include #include diff --git a/test/dm/blk.c b/test/dm/blk.c index 799f1e4dc75..d03aec32f6c 100644 --- a/test/dm/blk.c +++ b/test/dm/blk.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Google, Inc */ -#include #include #include #include diff --git a/test/dm/blkmap.c b/test/dm/blkmap.c index 7a163d6eaef..7581e62df3b 100644 --- a/test/dm/blkmap.c +++ b/test/dm/blkmap.c @@ -4,7 +4,6 @@ * Author: Tobias Waldekranz */ -#include #include #include #include diff --git a/test/dm/bootcount.c b/test/dm/bootcount.c index b77b472d1f2..9cfc7d48aac 100644 --- a/test/dm/bootcount.c +++ b/test/dm/bootcount.c @@ -3,7 +3,6 @@ * (C) 2018 Theobroma Systems Design und Consulting GmbH */ -#include #include #include #include diff --git a/test/dm/bus.c b/test/dm/bus.c index 89a6aa6554c..a338c7f567c 100644 --- a/test/dm/bus.c +++ b/test/dm/bus.c @@ -3,7 +3,6 @@ * Copyright (c) 2014 Google, Inc */ -#include #ifdef CONFIG_SANDBOX #include #include diff --git a/test/dm/button.c b/test/dm/button.c index 830d96fbef3..9157ec92878 100644 --- a/test/dm/button.c +++ b/test/dm/button.c @@ -5,7 +5,6 @@ * Based on led.c */ -#include #include #include #include diff --git a/test/dm/cache.c b/test/dm/cache.c index bbd8f98d007..d2f3bfe2caf 100644 --- a/test/dm/cache.c +++ b/test/dm/cache.c @@ -3,7 +3,6 @@ * Copyright (C) 2019 Intel Corporation */ -#include #include #include diff --git a/test/dm/clk.c b/test/dm/clk.c index 57fabbdce08..a966471dbd9 100644 --- a/test/dm/clk.c +++ b/test/dm/clk.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Google, Inc */ -#include #include #include #include diff --git a/test/dm/clk_ccf.c b/test/dm/clk_ccf.c index 61dad8d8527..15fba31b962 100644 --- a/test/dm/clk_ccf.c +++ b/test/dm/clk_ccf.c @@ -4,7 +4,6 @@ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de */ -#include #include #include #include diff --git a/test/dm/core.c b/test/dm/core.c index 7f3f8d183bc..4741c81bcc1 100644 --- a/test/dm/core.c +++ b/test/dm/core.c @@ -5,7 +5,6 @@ * Copyright (c) 2013 Google, Inc */ -#include #include #include #include diff --git a/test/dm/cpu.c b/test/dm/cpu.c index 5734cd0a92d..acba8105996 100644 --- a/test/dm/cpu.c +++ b/test/dm/cpu.c @@ -4,7 +4,6 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ -#include #include #include #include diff --git a/test/dm/cros_ec.c b/test/dm/cros_ec.c index 30cb70e0882..ac0055f0acd 100644 --- a/test/dm/cros_ec.c +++ b/test/dm/cros_ec.c @@ -3,7 +3,6 @@ * Copyright 2021 Google LLC */ -#include #include #include #include diff --git a/test/dm/cros_ec_pwm.c b/test/dm/cros_ec_pwm.c index f8d6e1e6c40..f68ee6f33b8 100644 --- a/test/dm/cros_ec_pwm.c +++ b/test/dm/cros_ec_pwm.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/test/dm/devres.c b/test/dm/devres.c index 3df0f64362d..95a470b9f1c 100644 --- a/test/dm/devres.c +++ b/test/dm/devres.c @@ -5,7 +5,6 @@ * Copyright 2019 Google LLC */ -#include #include #include #include diff --git a/test/dm/dma.c b/test/dm/dma.c index cce47cb2180..949710fdb4e 100644 --- a/test/dm/dma.c +++ b/test/dm/dma.c @@ -6,7 +6,6 @@ * Grygorii Strashko */ -#include #include #include #include diff --git a/test/dm/dsi_host.c b/test/dm/dsi_host.c index 6e0a5df704f..68686a40d9f 100644 --- a/test/dm/dsi_host.c +++ b/test/dm/dsi_host.c @@ -4,7 +4,6 @@ * Author(s): Yannick Fertre for STMicroelectronics. */ -#include #include #include #include diff --git a/test/dm/efi_media.c b/test/dm/efi_media.c index e343a0e9c85..9d0ed0f0755 100644 --- a/test/dm/efi_media.c +++ b/test/dm/efi_media.c @@ -5,7 +5,6 @@ * Copyright 2021 Google LLC */ -#include #include #include #include diff --git a/test/dm/eth.c b/test/dm/eth.c index bb3dcc6b954..820b8cbfc29 100644 --- a/test/dm/eth.c +++ b/test/dm/eth.c @@ -6,7 +6,6 @@ * Joe Hershberger */ -#include #include #include #include diff --git a/test/dm/fastboot.c b/test/dm/fastboot.c index 758538d0e85..5d938eb7f12 100644 --- a/test/dm/fastboot.c +++ b/test/dm/fastboot.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Google, Inc */ -#include #include #include #include diff --git a/test/dm/fdtdec.c b/test/dm/fdtdec.c index 087d4846da8..b484414f5f0 100644 --- a/test/dm/fdtdec.c +++ b/test/dm/fdtdec.c @@ -3,7 +3,6 @@ * Copyright 2020 NXP */ -#include #include #include #include diff --git a/test/dm/ffa.c b/test/dm/ffa.c index 6912666bb46..fa6d54d00d6 100644 --- a/test/dm/ffa.c +++ b/test/dm/ffa.c @@ -8,7 +8,6 @@ * Abdellatif El Khlifi */ -#include #include #include #include diff --git a/test/dm/firmware.c b/test/dm/firmware.c index f37bccfe4a8..ec68e816999 100644 --- a/test/dm/firmware.c +++ b/test/dm/firmware.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Xilinx, Inc. */ -#include #include #include #include diff --git a/test/dm/fwu_mdata.c b/test/dm/fwu_mdata.c index 52018f610fe..43ce3d0a9d8 100644 --- a/test/dm/fwu_mdata.c +++ b/test/dm/fwu_mdata.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/test/dm/gpio.c b/test/dm/gpio.c index 0d88ec24bda..957ab25c8d3 100644 --- a/test/dm/gpio.c +++ b/test/dm/gpio.c @@ -3,7 +3,6 @@ * Copyright (C) 2013 Google, Inc */ -#include #include #include #include diff --git a/test/dm/host.c b/test/dm/host.c index ca05a36b313..e514f8409cf 100644 --- a/test/dm/host.c +++ b/test/dm/host.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/dm/hwspinlock.c b/test/dm/hwspinlock.c index 995759d4d7e..a05b183b8bc 100644 --- a/test/dm/hwspinlock.c +++ b/test/dm/hwspinlock.c @@ -3,7 +3,6 @@ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved */ -#include #include #include #include diff --git a/test/dm/i2c.c b/test/dm/i2c.c index b46a22e79b1..e9cf9f7819a 100644 --- a/test/dm/i2c.c +++ b/test/dm/i2c.c @@ -5,7 +5,6 @@ * Note: Test coverage does not include 10-bit addressing */ -#include #include #include #include diff --git a/test/dm/i2s.c b/test/dm/i2s.c index c2bf4d5604b..a3d3a31b6fb 100644 --- a/test/dm/i2s.c +++ b/test/dm/i2s.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/dm/iommu.c b/test/dm/iommu.c index 62d38f1214a..acea5f28971 100644 --- a/test/dm/iommu.c +++ b/test/dm/iommu.c @@ -3,7 +3,6 @@ * Copyright (C) 2021 Mark Kettenis */ -#include #include #include #include diff --git a/test/dm/irq.c b/test/dm/irq.c index 51dd5e4abb4..d22772ab769 100644 --- a/test/dm/irq.c +++ b/test/dm/irq.c @@ -5,7 +5,6 @@ * Copyright 2019 Google LLC */ -#include #include #include #include diff --git a/test/dm/k210_pll.c b/test/dm/k210_pll.c index 354720f61e2..2a581499634 100644 --- a/test/dm/k210_pll.c +++ b/test/dm/k210_pll.c @@ -3,7 +3,6 @@ * Copyright (C) 2020 Sean Anderson */ -#include /* For DIV_ROUND_DOWN_ULL, defined in linux/kernel.h */ #include #include diff --git a/test/dm/led.c b/test/dm/led.c index eed3f4654c5..c28fa044f45 100644 --- a/test/dm/led.c +++ b/test/dm/led.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Google, Inc */ -#include #include #include #include diff --git a/test/dm/mailbox.c b/test/dm/mailbox.c index 7ad8a1cbba2..14f72d58d1c 100644 --- a/test/dm/mailbox.c +++ b/test/dm/mailbox.c @@ -3,7 +3,6 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ -#include #include #include #include diff --git a/test/dm/mdio.c b/test/dm/mdio.c index f863c52645b..7ececf37ccc 100644 --- a/test/dm/mdio.c +++ b/test/dm/mdio.c @@ -4,7 +4,6 @@ * Alex Marginean, NXP */ -#include #include #include #include diff --git a/test/dm/mdio_mux.c b/test/dm/mdio_mux.c index bfe3518221f..33a7e972609 100644 --- a/test/dm/mdio_mux.c +++ b/test/dm/mdio_mux.c @@ -4,7 +4,6 @@ * Alex Marginean, NXP */ -#include #include #include #include diff --git a/test/dm/misc.c b/test/dm/misc.c index 8bdd8c64bca..ad856fd01b6 100644 --- a/test/dm/misc.c +++ b/test/dm/misc.c @@ -4,7 +4,6 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ -#include #include #include #include diff --git a/test/dm/mmc.c b/test/dm/mmc.c index b1eb8bee2f9..c0abea797d9 100644 --- a/test/dm/mmc.c +++ b/test/dm/mmc.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Google, Inc */ -#include #include #include #include diff --git a/test/dm/mux-cmd.c b/test/dm/mux-cmd.c index 11c237b5da9..d4bb8befa38 100644 --- a/test/dm/mux-cmd.c +++ b/test/dm/mux-cmd.c @@ -3,7 +3,6 @@ * Copyright (C) 2020 Texas Instruments Inc. * Pratyush Yadav */ -#include #include #include #include @@ -13,6 +12,7 @@ #include #include #include +#include #define BUF_SIZE 256 diff --git a/test/dm/mux-emul.c b/test/dm/mux-emul.c index c6aeeb7e1f1..febd521104a 100644 --- a/test/dm/mux-emul.c +++ b/test/dm/mux-emul.c @@ -3,7 +3,6 @@ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * Pratyush Yadav */ -#include #include #include #include diff --git a/test/dm/mux-mmio.c b/test/dm/mux-mmio.c index 27c881dabde..3a871a19c7e 100644 --- a/test/dm/mux-mmio.c +++ b/test/dm/mux-mmio.c @@ -4,7 +4,6 @@ * Jean-Jacques Hiblot */ -#include #include #include #include diff --git a/test/dm/nop.c b/test/dm/nop.c index f7d9a0f3df3..0c79431d9d8 100644 --- a/test/dm/nop.c +++ b/test/dm/nop.c @@ -6,7 +6,6 @@ * Jean-Jacques Hiblot */ -#include #include #include #include diff --git a/test/dm/nvmxip.c b/test/dm/nvmxip.c index f0ad47d4efe..537959a0930 100644 --- a/test/dm/nvmxip.c +++ b/test/dm/nvmxip.c @@ -8,7 +8,6 @@ * Abdellatif El Khlifi */ -#include #include #include #include diff --git a/test/dm/of_extra.c b/test/dm/of_extra.c index ac2d886892d..3c31bfcd31f 100644 --- a/test/dm/of_extra.c +++ b/test/dm/of_extra.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/dm/of_platdata.c b/test/dm/of_platdata.c index a241c427936..d4939e88516 100644 --- a/test/dm/of_platdata.c +++ b/test/dm/of_platdata.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c index a5bc43aea4e..39191d7f52b 100644 --- a/test/dm/ofnode.c +++ b/test/dm/ofnode.c @@ -16,7 +16,6 @@ * behaviour of each ofnode function, since that is done by the normal ones. */ -#include #include #include #include diff --git a/test/dm/ofread.c b/test/dm/ofread.c index 3523860d2b3..69d03c49107 100644 --- a/test/dm/ofread.c +++ b/test/dm/ofread.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include #include #include #include diff --git a/test/dm/osd.c b/test/dm/osd.c index 6279b391ca5..cf4a3a545ed 100644 --- a/test/dm/osd.c +++ b/test/dm/osd.c @@ -4,7 +4,6 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ -#include #include #include #include diff --git a/test/dm/p2sb.c b/test/dm/p2sb.c index df24709141a..3ada1fcb362 100644 --- a/test/dm/p2sb.c +++ b/test/dm/p2sb.c @@ -5,7 +5,6 @@ * Copyright 2019 Google LLC */ -#include #include #include #include diff --git a/test/dm/panel.c b/test/dm/panel.c index 4d435a0d255..8be7c397a46 100644 --- a/test/dm/panel.c +++ b/test/dm/panel.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/dm/part.c b/test/dm/part.c index d6e43458127..cabb31d18ca 100644 --- a/test/dm/part.c +++ b/test/dm/part.c @@ -3,7 +3,6 @@ * Copyright (C) 2020 Sean Anderson */ -#include #include #include #include diff --git a/test/dm/pch.c b/test/dm/pch.c index 53f7bbf180c..b37b856d5da 100644 --- a/test/dm/pch.c +++ b/test/dm/pch.c @@ -3,7 +3,6 @@ * Copyright 2018 Google LLC */ -#include #include #include #include diff --git a/test/dm/pci.c b/test/dm/pci.c index 8c5e7da9e62..9b97f2e0544 100644 --- a/test/dm/pci.c +++ b/test/dm/pci.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Google, Inc */ -#include #include #include #include diff --git a/test/dm/pci_ep.c b/test/dm/pci_ep.c index 9941abd4ceb..e82fc53f84b 100644 --- a/test/dm/pci_ep.c +++ b/test/dm/pci_ep.c @@ -3,7 +3,6 @@ * Copyright (C) 2019 Ramon Fried */ -#include #include #include #include diff --git a/test/dm/phy.c b/test/dm/phy.c index 0cf3689fdec..d14117f6f7a 100644 --- a/test/dm/phy.c +++ b/test/dm/phy.c @@ -4,7 +4,6 @@ * Written by Jean-Jacques Hiblot */ -#include #include #include #include diff --git a/test/dm/phys2bus.c b/test/dm/phys2bus.c index 342f2fa8eba..1ee2150482c 100644 --- a/test/dm/phys2bus.c +++ b/test/dm/phys2bus.c @@ -3,7 +3,6 @@ * Copyright (c) 2020 Nicolas Saenz Julienne */ -#include #include #include #include diff --git a/test/dm/pinmux.c b/test/dm/pinmux.c index 6880b2d2cd9..cfbe3ef5d1e 100644 --- a/test/dm/pinmux.c +++ b/test/dm/pinmux.c @@ -3,7 +3,6 @@ * Copyright (C) 2020 Sean Anderson */ -#include #include #include #include diff --git a/test/dm/pmc.c b/test/dm/pmc.c index e70227e7800..bbad1ee2741 100644 --- a/test/dm/pmc.c +++ b/test/dm/pmc.c @@ -5,7 +5,6 @@ * Copyright 2019 Google LLC */ -#include #include #include #include diff --git a/test/dm/pmic.c b/test/dm/pmic.c index ce671202fbc..53a6f0369e8 100644 --- a/test/dm/pmic.c +++ b/test/dm/pmic.c @@ -6,7 +6,6 @@ * Przemyslaw Marczak */ -#include #include #include #include diff --git a/test/dm/power-domain.c b/test/dm/power-domain.c index 8604b5d72dc..120a9059c8e 100644 --- a/test/dm/power-domain.c +++ b/test/dm/power-domain.c @@ -3,7 +3,6 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ -#include #include #include #include diff --git a/test/dm/pwm.c b/test/dm/pwm.c index dff626c771a..80133347ec7 100644 --- a/test/dm/pwm.c +++ b/test/dm/pwm.c @@ -3,7 +3,6 @@ * Copyright (C) 2017 Google, Inc */ -#include #include #include #include diff --git a/test/dm/qfw.c b/test/dm/qfw.c index f3f35689830..3c354163ef3 100644 --- a/test/dm/qfw.c +++ b/test/dm/qfw.c @@ -3,7 +3,6 @@ * Copyright 2021 Asherah Connor */ -#include #include #include #include diff --git a/test/dm/ram.c b/test/dm/ram.c index f624343138d..188c7c32758 100644 --- a/test/dm/ram.c +++ b/test/dm/ram.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Google, Inc */ -#include #include #include #include diff --git a/test/dm/read.c b/test/dm/read.c index 7768aa29688..4ecf18110d0 100644 --- a/test/dm/read.c +++ b/test/dm/read.c @@ -3,7 +3,6 @@ * Copyright (c) 2020 Nicolas Saenz Julienne */ -#include #include #include #include diff --git a/test/dm/reboot-mode.c b/test/dm/reboot-mode.c index fbb9c3a5426..160b4da07f2 100644 --- a/test/dm/reboot-mode.c +++ b/test/dm/reboot-mode.c @@ -3,7 +3,6 @@ * (C) 2018 Theobroma Systems Design und Consulting GmbH */ -#include #include #include #include diff --git a/test/dm/regmap.c b/test/dm/regmap.c index 8560f2afc2d..1398f8f6573 100644 --- a/test/dm/regmap.c +++ b/test/dm/regmap.c @@ -3,13 +3,13 @@ * Copyright (C) 2015 Google, Inc */ -#include #include #include #include #include #include #include +#include #include #include #include diff --git a/test/dm/regulator.c b/test/dm/regulator.c index 86f4862d9dd..9e45fd177b9 100644 --- a/test/dm/regulator.c +++ b/test/dm/regulator.c @@ -6,7 +6,6 @@ * Przemyslaw Marczak */ -#include #include #include #include diff --git a/test/dm/remoteproc.c b/test/dm/remoteproc.c index f6f9e509e27..ef9e8e5a0df 100644 --- a/test/dm/remoteproc.c +++ b/test/dm/remoteproc.c @@ -3,7 +3,8 @@ * (C) Copyright 2015 * Texas Instruments Incorporated - https://www.ti.com/ */ -#include + +#include #include #include #include diff --git a/test/dm/reset.c b/test/dm/reset.c index e2d6f456230..d3158bf4a72 100644 --- a/test/dm/reset.c +++ b/test/dm/reset.c @@ -3,7 +3,6 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ -#include #include #include #include diff --git a/test/dm/rkmtd.c b/test/dm/rkmtd.c index 3c3e8efa92f..3dc9ca1add1 100644 --- a/test/dm/rkmtd.c +++ b/test/dm/rkmtd.c @@ -8,7 +8,6 @@ * Copyright (C) 2023 Johan Jonker */ -#include #include #include #include diff --git a/test/dm/rng.c b/test/dm/rng.c index 6d1f68848d5..c8ed6cadf58 100644 --- a/test/dm/rng.c +++ b/test/dm/rng.c @@ -3,7 +3,6 @@ * Copyright (c) 2019, Linaro Limited */ -#include #include #include #include diff --git a/test/dm/rtc.c b/test/dm/rtc.c index bf97dbbd2f9..a8aa41955c2 100644 --- a/test/dm/rtc.c +++ b/test/dm/rtc.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/dm/scmi.c b/test/dm/scmi.c index adf36ffaab1..69fc900e342 100644 --- a/test/dm/scmi.c +++ b/test/dm/scmi.c @@ -12,7 +12,6 @@ * unknown SCMI protocol ID. */ -#include #include #include #include diff --git a/test/dm/scsi.c b/test/dm/scsi.c index 380cfc88bab..5180159fb27 100644 --- a/test/dm/scsi.c +++ b/test/dm/scsi.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Google, Inc */ -#include #include #include #include diff --git a/test/dm/serial.c b/test/dm/serial.c index 34b783e062e..34c0d4db879 100644 --- a/test/dm/serial.c +++ b/test/dm/serial.c @@ -3,7 +3,6 @@ * Copyright (c) 2018, STMicroelectronics */ -#include #include #include #include diff --git a/test/dm/sf.c b/test/dm/sf.c index 17d43fef3bc..0e3a0f13f9e 100644 --- a/test/dm/sf.c +++ b/test/dm/sf.c @@ -3,7 +3,6 @@ * Copyright (C) 2013 Google, Inc */ -#include #include #include #include diff --git a/test/dm/simple-bus.c b/test/dm/simple-bus.c index 3530b47fac2..8a730ba2fce 100644 --- a/test/dm/simple-bus.c +++ b/test/dm/simple-bus.c @@ -3,7 +3,6 @@ * Copyright (C) 2021, Bin Meng */ -#include #include #include #include diff --git a/test/dm/simple-pm-bus.c b/test/dm/simple-pm-bus.c index 792c7450580..9949cb34d59 100644 --- a/test/dm/simple-pm-bus.c +++ b/test/dm/simple-pm-bus.c @@ -3,7 +3,6 @@ * Copyright (C) 2020 Sean Anderson */ -#include #include #include #include diff --git a/test/dm/sm.c b/test/dm/sm.c index 7ebb0c9c85e..4d95c2ad75b 100644 --- a/test/dm/sm.c +++ b/test/dm/sm.c @@ -5,7 +5,6 @@ * Author: Alexey Romanov */ -#include #include #include #include diff --git a/test/dm/smem.c b/test/dm/smem.c index 289fb59ba13..adcbfe574ab 100644 --- a/test/dm/smem.c +++ b/test/dm/smem.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Ramon Fried */ -#include #include #include #include diff --git a/test/dm/soc.c b/test/dm/soc.c index 8f6c97fa790..cb0ac1545f7 100644 --- a/test/dm/soc.c +++ b/test/dm/soc.c @@ -6,7 +6,6 @@ * Dave Gerlach */ -#include #include #include #include diff --git a/test/dm/sound.c b/test/dm/sound.c index 15d545ab5a3..f4e6215e683 100644 --- a/test/dm/sound.c +++ b/test/dm/sound.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/dm/spi.c b/test/dm/spi.c index 325799bbf10..1ab2dd78324 100644 --- a/test/dm/spi.c +++ b/test/dm/spi.c @@ -3,7 +3,6 @@ * Copyright (C) 2013 Google, Inc */ -#include #include #include #include diff --git a/test/dm/spmi.c b/test/dm/spmi.c index 97bb0eb30fc..e10ae8db4d3 100644 --- a/test/dm/spmi.c +++ b/test/dm/spmi.c @@ -3,7 +3,6 @@ * (C) Copyright 2015 Mateusz Kulikowski */ -#include #include #include #include diff --git a/test/dm/syscon-reset.c b/test/dm/syscon-reset.c index eeaddf88392..ba19504573f 100644 --- a/test/dm/syscon-reset.c +++ b/test/dm/syscon-reset.c @@ -3,7 +3,6 @@ * Copyright (C) 2020 Sean Anderson */ -#include #include #include #include diff --git a/test/dm/syscon.c b/test/dm/syscon.c index be232972336..04d324e87d4 100644 --- a/test/dm/syscon.c +++ b/test/dm/syscon.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Google, Inc */ -#include #include #include #include diff --git a/test/dm/sysinfo-gpio.c b/test/dm/sysinfo-gpio.c index 2e494b3f341..24a99dafb15 100644 --- a/test/dm/sysinfo-gpio.c +++ b/test/dm/sysinfo-gpio.c @@ -3,7 +3,6 @@ * Copyright (C) 2021 Sean Anderson */ -#include #include #include #include diff --git a/test/dm/sysinfo.c b/test/dm/sysinfo.c index 96b3a8ebaba..7444a580df6 100644 --- a/test/dm/sysinfo.c +++ b/test/dm/sysinfo.c @@ -4,7 +4,6 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ -#include #include #include #include diff --git a/test/dm/sysreset.c b/test/dm/sysreset.c index 5aa69e04618..f3a859be787 100644 --- a/test/dm/sysreset.c +++ b/test/dm/sysreset.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Google, Inc */ -#include #include #include #include diff --git a/test/dm/tag.c b/test/dm/tag.c index 8ae8a1fcd65..bce8a35acfb 100644 --- a/test/dm/tag.c +++ b/test/dm/tag.c @@ -6,7 +6,6 @@ * Author: AKASHI Takahiro */ -#include #include #include /* DM_TEST() */ #include /* struct unit_test_state */ diff --git a/test/dm/tee.c b/test/dm/tee.c index 7a11bf89138..bb02a9b3c98 100644 --- a/test/dm/tee.c +++ b/test/dm/tee.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Linaro Limited */ -#include #include #include #include diff --git a/test/dm/test-dm.c b/test/dm/test-dm.c index e73a1dd8f81..4bc2c45db61 100644 --- a/test/dm/test-dm.c +++ b/test/dm/test-dm.c @@ -3,7 +3,6 @@ * Copyright (c) 2013 Google, Inc */ -#include #include #include diff --git a/test/dm/test-driver.c b/test/dm/test-driver.c index 02cb974b0f7..851177c3018 100644 --- a/test/dm/test-driver.c +++ b/test/dm/test-driver.c @@ -6,7 +6,6 @@ * Pavel Herrmann */ -#include #include #include #include diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c index 72d0eb57e21..18c89eef43f 100644 --- a/test/dm/test-fdt.c +++ b/test/dm/test-fdt.c @@ -3,7 +3,6 @@ * Copyright (c) 2013 Google, Inc */ -#include #include #include #include diff --git a/test/dm/test-uclass.c b/test/dm/test-uclass.c index 067701734a0..9a80cc63667 100644 --- a/test/dm/test-uclass.c +++ b/test/dm/test-uclass.c @@ -6,7 +6,6 @@ * Pavel Herrmann */ -#include #include #include #include diff --git a/test/dm/timer.c b/test/dm/timer.c index 9f94d476920..7fcefc42e59 100644 --- a/test/dm/timer.c +++ b/test/dm/timer.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Thomas Chou */ -#include #include #include #include diff --git a/test/dm/tpm.c b/test/dm/tpm.c index cde933ab284..0e413c0eedd 100644 --- a/test/dm/tpm.c +++ b/test/dm/tpm.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/dm/usb.c b/test/dm/usb.c index 7671ef156d8..9a571938b81 100644 --- a/test/dm/usb.c +++ b/test/dm/usb.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Google, Inc */ -#include #include #include #include diff --git a/test/dm/video.c b/test/dm/video.c index d907f681600..7dfbeb9555d 100644 --- a/test/dm/video.c +++ b/test/dm/video.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/dm/virtio.c b/test/dm/virtio.c index 3e108cdc35d..3efd7c74f42 100644 --- a/test/dm/virtio.c +++ b/test/dm/virtio.c @@ -3,7 +3,6 @@ * Copyright (C) 2018, Bin Meng */ -#include #include #include #include diff --git a/test/dm/virtio_device.c b/test/dm/virtio_device.c index fdda4da4178..63dc53415b7 100644 --- a/test/dm/virtio_device.c +++ b/test/dm/virtio_device.c @@ -3,7 +3,6 @@ * Copyright (C) 2018, Bin Meng */ -#include #include #include #include diff --git a/test/dm/virtio_rng.c b/test/dm/virtio_rng.c index 8b9a04b1fde..ab7d862d79e 100644 --- a/test/dm/virtio_rng.c +++ b/test/dm/virtio_rng.c @@ -4,7 +4,6 @@ * Written by Andrew Scull */ -#include #include #include #include diff --git a/test/dm/wdt.c b/test/dm/wdt.c index 2bbebcdbf28..1df2da23c6c 100644 --- a/test/dm/wdt.c +++ b/test/dm/wdt.c @@ -3,9 +3,9 @@ * Copyright 2017 Google, Inc */ -#include #include #include +#include #include #include #include diff --git a/test/env/attr.c b/test/env/attr.c index 8d5c0f1c3df..de5d5d4ee27 100644 --- a/test/env/attr.c +++ b/test/env/attr.c @@ -4,7 +4,6 @@ * Joe Hershberger, National Instruments, joe.hershberger@ni.com */ -#include #include #include #include diff --git a/test/env/cmd_ut_env.c b/test/env/cmd_ut_env.c index d65a32179ce..13e0998341e 100644 --- a/test/env/cmd_ut_env.c +++ b/test/env/cmd_ut_env.c @@ -4,7 +4,6 @@ * Joe Hershberger, National Instruments, joe.hershberger@ni.com */ -#include #include #include #include diff --git a/test/env/fdt.c b/test/env/fdt.c index 30bfa88c355..c495ac7b307 100644 --- a/test/env/fdt.c +++ b/test/env/fdt.c @@ -1,4 +1,3 @@ -#include #include #include #include diff --git a/test/env/hashtable.c b/test/env/hashtable.c index 70102f9121c..ccdf0138c4b 100644 --- a/test/env/hashtable.c +++ b/test/env/hashtable.c @@ -4,11 +4,11 @@ * Roman Kapl, SYSGO, rka@sysgo.com */ -#include #include #include #include #include +#include #include #include diff --git a/test/fuzz/cmd_fuzz.c b/test/fuzz/cmd_fuzz.c index d0bc7b8d7b7..faa140433ff 100644 --- a/test/fuzz/cmd_fuzz.c +++ b/test/fuzz/cmd_fuzz.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include diff --git a/test/fuzz/virtio.c b/test/fuzz/virtio.c index 8a47667e778..836eb9a2f66 100644 --- a/test/fuzz/virtio.c +++ b/test/fuzz/virtio.c @@ -4,7 +4,6 @@ * Written by Andrew Scull */ -#include #include #include #include diff --git a/test/image/spl_load.c b/test/image/spl_load.c index e1036eff28c..7cbad40ea0c 100644 --- a/test/image/spl_load.c +++ b/test/image/spl_load.c @@ -3,7 +3,6 @@ * Copyright (C) 2023 Sean Anderson */ -#include #include #include #include diff --git a/test/image/spl_load_fs.c b/test/image/spl_load_fs.c index a89189e1124..935078bf67b 100644 --- a/test/image/spl_load_fs.c +++ b/test/image/spl_load_fs.c @@ -3,7 +3,6 @@ * Copyright (C) 2023 Sean Anderson */ -#include #include #include #include diff --git a/test/image/spl_load_net.c b/test/image/spl_load_net.c index 9d067a7a592..4af6e21b8b9 100644 --- a/test/image/spl_load_net.c +++ b/test/image/spl_load_net.c @@ -3,7 +3,6 @@ * Copyright (C) 2023 Sean Anderson */ -#include #include #include #include diff --git a/test/image/spl_load_nor.c b/test/image/spl_load_nor.c index de5686343b9..f53a6724e27 100644 --- a/test/image/spl_load_nor.c +++ b/test/image/spl_load_nor.c @@ -3,7 +3,6 @@ * Copyright (C) 2023 Sean Anderson */ -#include #include #include #include diff --git a/test/image/spl_load_os.c b/test/image/spl_load_os.c index 26228a8a4a9..7d5fb9b07e0 100644 --- a/test/image/spl_load_os.c +++ b/test/image/spl_load_os.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/image/spl_load_spi.c b/test/image/spl_load_spi.c index 54a95465e23..80836dc0dff 100644 --- a/test/image/spl_load_spi.c +++ b/test/image/spl_load_spi.c @@ -3,7 +3,6 @@ * Copyright (C) 2023 Sean Anderson */ -#include #include #include #include diff --git a/test/lib/abuf.c b/test/lib/abuf.c index 42803b20e2a..7c0481ab610 100644 --- a/test/lib/abuf.c +++ b/test/lib/abuf.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/lib/asn1.c b/test/lib/asn1.c index a66cdd77df0..4842b7058ac 100644 --- a/test/lib/asn1.c +++ b/test/lib/asn1.c @@ -6,7 +6,6 @@ * Unit test for asn1 compiler and asn1 decoder function via various parsers */ -#include #include #include #include diff --git a/test/lib/cmd_ut_lib.c b/test/lib/cmd_ut_lib.c index f1ac015b2c8..f98cb9b3c57 100644 --- a/test/lib/cmd_ut_lib.c +++ b/test/lib/cmd_ut_lib.c @@ -5,7 +5,6 @@ * Unit tests for library functions */ -#include #include #include #include diff --git a/test/lib/efi_device_path.c b/test/lib/efi_device_path.c index 24e2f23c5af..290c8768fa4 100644 --- a/test/lib/efi_device_path.c +++ b/test/lib/efi_device_path.c @@ -5,7 +5,6 @@ * Copyright (c) 2020 Heinrich Schuchardt */ -#include #include #include #include diff --git a/test/lib/efi_image_region.c b/test/lib/efi_image_region.c index 0b888f84337..3ca49dc4a2e 100644 --- a/test/lib/efi_image_region.c +++ b/test/lib/efi_image_region.c @@ -3,7 +3,6 @@ * (C) Copyright 2020, Heinrich Schuchardt */ -#include #include #include #include diff --git a/test/lib/getopt.c b/test/lib/getopt.c index 3c68b93c8a5..388a076200b 100644 --- a/test/lib/getopt.c +++ b/test/lib/getopt.c @@ -6,7 +6,6 @@ * posix/tst-getopt-cancel.c */ -#include #include #include #include diff --git a/test/lib/hexdump.c b/test/lib/hexdump.c index 5dccf438866..d531a830398 100644 --- a/test/lib/hexdump.c +++ b/test/lib/hexdump.c @@ -4,7 +4,6 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ -#include #include #include #include diff --git a/test/lib/kconfig.c b/test/lib/kconfig.c index 3914f699659..0c463bb794a 100644 --- a/test/lib/kconfig.c +++ b/test/lib/kconfig.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/lib/kconfig_spl.c b/test/lib/kconfig_spl.c index 8f8a3411b14..3bd8abdf4b8 100644 --- a/test/lib/kconfig_spl.c +++ b/test/lib/kconfig_spl.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/lib/lmb.c b/test/lib/lmb.c index 7e4368de22e..4b5b6e5e209 100644 --- a/test/lib/lmb.c +++ b/test/lib/lmb.c @@ -3,7 +3,6 @@ * (C) Copyright 2018 Simon Goldschmidt */ -#include #include #include #include diff --git a/test/lib/longjmp.c b/test/lib/longjmp.c index 201367a5a3a..79d889bdd5f 100644 --- a/test/lib/longjmp.c +++ b/test/lib/longjmp.c @@ -5,7 +5,6 @@ * Copyright (c) 2021, Heinrich Schuchardt */ -#include #include #include #include diff --git a/test/lib/rsa.c b/test/lib/rsa.c index 44f8ade226f..40f70010c78 100644 --- a/test/lib/rsa.c +++ b/test/lib/rsa.c @@ -6,7 +6,6 @@ * Unit test for rsa_verify() function */ -#include #include #include #include diff --git a/test/lib/sscanf.c b/test/lib/sscanf.c index 772e4b92042..9fe5521749f 100644 --- a/test/lib/sscanf.c +++ b/test/lib/sscanf.c @@ -9,7 +9,6 @@ * Unit tests for sscanf() function */ -#include #include #include #include diff --git a/test/lib/string.c b/test/lib/string.c index 5dcf4d6db00..d08dbca9291 100644 --- a/test/lib/string.c +++ b/test/lib/string.c @@ -9,7 +9,6 @@ * This has to be considered in testing. */ -#include #include #include #include diff --git a/test/lib/strlcat.c b/test/lib/strlcat.c index d8453fe78e2..d1a0293271b 100644 --- a/test/lib/strlcat.c +++ b/test/lib/strlcat.c @@ -6,7 +6,6 @@ * These tests adapted from glibc's string/test-strncat.c */ -#include #include #include #include diff --git a/test/lib/test_aes.c b/test/lib/test_aes.c index cbc712f7eda..cfd9d8ca5a9 100644 --- a/test/lib/test_aes.c +++ b/test/lib/test_aes.c @@ -5,7 +5,6 @@ * Unit tests for aes functions */ -#include #include #include #include diff --git a/test/lib/test_crypt.c b/test/lib/test_crypt.c index fb21edf9748..dcdadd992c1 100644 --- a/test/lib/test_crypt.c +++ b/test/lib/test_crypt.c @@ -5,7 +5,6 @@ * Unit test for crypt-style password hashing */ -#include #include #include #include diff --git a/test/lib/test_errno_str.c b/test/lib/test_errno_str.c index 8a9f1fd9805..67f76442b27 100644 --- a/test/lib/test_errno_str.c +++ b/test/lib/test_errno_str.c @@ -9,7 +9,6 @@ * This has to be considered in testing. */ -#include #include #include #include diff --git a/test/lib/test_print.c b/test/lib/test_print.c index 79b67c77932..c7fc50a1de1 100644 --- a/test/lib/test_print.c +++ b/test/lib/test_print.c @@ -5,7 +5,6 @@ * Copyright 2020, Heinrich Schuchadt */ -#include #include #include #include diff --git a/test/lib/uuid.c b/test/lib/uuid.c index e24331a1366..0914f2c47e7 100644 --- a/test/lib/uuid.c +++ b/test/lib/uuid.c @@ -8,7 +8,6 @@ * Abdellatif El Khlifi */ -#include #include #include #include diff --git a/test/log/cont_test.c b/test/log/cont_test.c index de7b7f064cd..036d44b9d73 100644 --- a/test/log/cont_test.c +++ b/test/log/cont_test.c @@ -5,7 +5,6 @@ * Test continuation of log messages. */ -#include #include #include #include diff --git a/test/log/log_filter.c b/test/log/log_filter.c index b644b40a850..9cc891dc48c 100644 --- a/test/log/log_filter.c +++ b/test/log/log_filter.c @@ -3,7 +3,6 @@ * Copyright (C) 2020 Sean Anderson */ -#include #include #include #include diff --git a/test/log/log_test.c b/test/log/log_test.c index c5abff80d11..855353a9c40 100644 --- a/test/log/log_test.c +++ b/test/log/log_test.c @@ -6,7 +6,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/log/log_ut.c b/test/log/log_ut.c index 5aa3a184004..6617ed8b152 100644 --- a/test/log/log_ut.c +++ b/test/log/log_ut.c @@ -5,7 +5,6 @@ * Logging function tests. */ -#include #include #include #include diff --git a/test/log/nolog_ndebug.c b/test/log/nolog_ndebug.c index bd9a4f408e7..b714a16d2e7 100644 --- a/test/log/nolog_ndebug.c +++ b/test/log/nolog_ndebug.c @@ -5,7 +5,6 @@ * Logging function tests for CONFIG_LOG=n without #define DEBUG */ -#include #include #include #include diff --git a/test/log/nolog_test.c b/test/log/nolog_test.c index 4e52e5bed82..c4c0fa6cf81 100644 --- a/test/log/nolog_test.c +++ b/test/log/nolog_test.c @@ -8,7 +8,6 @@ /* Needed for testing log_debug() */ #define DEBUG 1 -#include #include #include #include diff --git a/test/log/pr_cont_test.c b/test/log/pr_cont_test.c index df4520d2807..30f30d98fe1 100644 --- a/test/log/pr_cont_test.c +++ b/test/log/pr_cont_test.c @@ -5,7 +5,6 @@ * Test continuation of log messages using pr_cont(). */ -#include #include #include #include diff --git a/test/log/syslog_test.c b/test/log/syslog_test.c index 4db649db822..c4180f775b9 100644 --- a/test/log/syslog_test.c +++ b/test/log/syslog_test.c @@ -10,7 +10,6 @@ /* Override CONFIG_LOG_MAX_LEVEL */ #define LOG_DEBUG -#include #include #include #include diff --git a/test/log/syslog_test_ndebug.c b/test/log/syslog_test_ndebug.c index 4438791044d..b10e636812b 100644 --- a/test/log/syslog_test_ndebug.c +++ b/test/log/syslog_test_ndebug.c @@ -7,7 +7,6 @@ * Invoke the test with: ./u-boot -d arch/sandbox/dts/test.dtb */ -#include #include #include #include diff --git a/test/optee/cmd_ut_optee.c b/test/optee/cmd_ut_optee.c index c3887ab11d9..c6f50e0995a 100644 --- a/test/optee/cmd_ut_optee.c +++ b/test/optee/cmd_ut_optee.c @@ -3,7 +3,6 @@ * Copyright (C) 2019, Theobroma Systems Design und Consulting GmbH */ -#include #include #include #include diff --git a/test/overlay/cmd_ut_overlay.c b/test/overlay/cmd_ut_overlay.c index 56a3df17138..bcb29a26e21 100644 --- a/test/overlay/cmd_ut_overlay.c +++ b/test/overlay/cmd_ut_overlay.c @@ -4,7 +4,6 @@ * Copyright (c) 2016 Free Electrons */ -#include #include #include #include diff --git a/test/print_ut.c b/test/print_ut.c index bb844d2542b..bded2b6ebe5 100644 --- a/test/print_ut.c +++ b/test/print_ut.c @@ -3,7 +3,6 @@ * Copyright (c) 2012, The Chromium Authors */ -#include #include #include #include diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py index 26b6de07f88..3e01be11029 100644 --- a/test/py/u_boot_console_base.py +++ b/test/py/u_boot_console_base.py @@ -17,7 +17,6 @@ import u_boot_spawn # Regexes for text we expect U-Boot to send to the console. pattern_u_boot_spl_signon = re.compile('(U-Boot SPL \\d{4}\\.\\d{2}[^\r\n]*\\))') -pattern_u_boot_spl2_signon = re.compile('(U-Boot SPL \\d{4}\\.\\d{2}[^\r\n]*\\))') pattern_u_boot_main_signon = re.compile('(U-Boot \\d{4}\\.\\d{2}[^\r\n]*\\))') pattern_stop_autoboot_prompt = re.compile('Hit any key to stop autoboot: ') pattern_unknown_command = re.compile('Unknown command \'.*\' - try \'help\'') @@ -29,7 +28,6 @@ PAT_RE = 1 bad_pattern_defs = ( ('spl_signon', pattern_u_boot_spl_signon), - ('spl2_signon', pattern_u_boot_spl2_signon), ('main_signon', pattern_u_boot_main_signon), ('stop_autoboot_prompt', pattern_stop_autoboot_prompt), ('unknown_command', pattern_unknown_command), @@ -152,25 +150,20 @@ class ConsoleBase(object): """ try: bcfg = self.config.buildconfig - config_spl = bcfg.get('config_spl', 'n') == 'y' config_spl_serial = bcfg.get('config_spl_serial', 'n') == 'y' env_spl_skipped = self.config.env.get('env__spl_skipped', False) - env_spl2_skipped = self.config.env.get('env__spl2_skipped', True) + env_spl_banner_times = self.config.env.get('env__spl_banner_times', 1) while loop_num > 0: loop_num -= 1 - if config_spl and config_spl_serial and not env_spl_skipped: + while config_spl_serial and not env_spl_skipped and env_spl_banner_times > 0: m = self.p.expect([pattern_u_boot_spl_signon] + self.bad_patterns) if m != 0: raise Exception('Bad pattern found on SPL console: ' + self.bad_pattern_ids[m - 1]) - if not env_spl2_skipped: - m = self.p.expect([pattern_u_boot_spl2_signon] + - self.bad_patterns) - if m != 0: - raise Exception('Bad pattern found on SPL2 console: ' + - self.bad_pattern_ids[m - 1]) + env_spl_banner_times -= 1 + m = self.p.expect([pattern_u_boot_main_signon] + self.bad_patterns) if m != 0: raise Exception('Bad pattern found on console: ' + diff --git a/test/stdint/int-types.c b/test/stdint/int-types.c index f6d09e8643d..9051e32c7ce 100644 --- a/test/stdint/int-types.c +++ b/test/stdint/int-types.c @@ -1,4 +1,4 @@ -#include +#include int test_types(void) { diff --git a/test/str_ut.c b/test/str_ut.c index fa9328ede50..389779859a3 100644 --- a/test/str_ut.c +++ b/test/str_ut.c @@ -3,7 +3,6 @@ * Copyright 2020 Google LLC */ -#include #include #include #include diff --git a/test/test-main.c b/test/test-main.c index b7015d9f38d..3fa6f6e32ec 100644 --- a/test/test-main.c +++ b/test/test-main.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/time_ut.c b/test/time_ut.c index 80b82dbfd83..149c4b58f4a 100644 --- a/test/time_ut.c +++ b/test/time_ut.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/test/unicode_ut.c b/test/unicode_ut.c index 47c3f52774c..13e29c9b9e3 100644 --- a/test/unicode_ut.c +++ b/test/unicode_ut.c @@ -5,7 +5,6 @@ * Copyright (c) 2018 Heinrich Schuchardt */ -#include #include #include #include diff --git a/test/ut.c b/test/ut.c index 628e9dc9805..ae99831ac8f 100644 --- a/test/ut.c +++ b/test/ut.c @@ -5,7 +5,6 @@ * Copyright (c) 2013 Google, Inc */ -#include #include #include #ifdef CONFIG_SANDBOX diff --git a/tools/dtoc/dtb_platdata.py b/tools/dtoc/dtb_platdata.py index 39f416cfd80..89066e6403f 100644 --- a/tools/dtoc/dtb_platdata.py +++ b/tools/dtoc/dtb_platdata.py @@ -835,7 +835,6 @@ class DtbPlatdata(): def generate_uclasses(self): self.out('\n') - self.out('#include \n') self.out('#include \n') self.out('#include \n') self.out('\n') @@ -1059,7 +1058,6 @@ class DtbPlatdata(): self.out('/* Allow use of U_BOOT_DRVINFO() in this file */\n') self.out('#define DT_PLAT_C\n') self.out('\n') - self.out('#include \n') self.out('#include \n') self.out('#include \n') self.out('\n') @@ -1092,7 +1090,6 @@ class DtbPlatdata(): See the documentation in doc/driver-model/of-plat.rst for more information. """ - self.out('#include \n') self.out('#include \n') self.out('#include \n') self.out('\n') diff --git a/tools/dtoc/test_dtoc.py b/tools/dtoc/test_dtoc.py index 597c93e8a87..c4a0889aebe 100755 --- a/tools/dtoc/test_dtoc.py +++ b/tools/dtoc/test_dtoc.py @@ -63,7 +63,6 @@ C_HEADER = C_HEADER_PRE + ''' /* Allow use of U_BOOT_DRVINFO() in this file */ #define DT_PLAT_C -#include #include #include ''' @@ -417,7 +416,6 @@ U_BOOT_DRVINFO(spl_test3) = { ''' uclass_text_inst = ''' -#include #include #include @@ -521,7 +519,6 @@ DM_UCLASS_INST(testfdt) = { * This was generated by dtoc from a .dtb (device tree binary) file. */ -#include #include #include From 1bfce599dc68fac4285b0a4fbe247793fd82c156 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Wed, 15 May 2024 09:36:11 +0200 Subject: [PATCH 038/383] Makefile: refactor ubootrelease target Instead of duplicating the contents of the filechk_uboot.release variable, use it directly. This is preparation for the next patch which will modify filechk_uboot.release, and reflects what the linux kernel does nowadays: kernelrelease: @$(filechk_kernel.release) Signed-off-by: Rasmus Villemoes --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 44deb339af1..efaf24e58e7 100644 --- a/Makefile +++ b/Makefile @@ -2426,7 +2426,7 @@ checkstack: $(PERL) $(src)/scripts/checkstack.pl $(ARCH) ubootrelease: - @echo "$(UBOOTVERSION)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))" + @$(filechk_uboot.release) ubootversion: @echo $(UBOOTVERSION) From 5c02350fa03d60ca41a76aca36e788db86cfabf9 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Wed, 15 May 2024 09:36:12 +0200 Subject: [PATCH 039/383] scripts/setlocalversion: sync with linux v6.9 The changes upstream since the last sync (2ed1b242ab2 "scripts/setlocalversion: sync with linux 5.8") are (5) 548b8b5168c9 scripts/setlocalversion: make git describe output more reliable 77a88274dc1a kbuild: replace LANG=C with LC_ALL=C 2a73cce2dad3 scripts/setlocalversion: remove mercurial, svn and git-svn supports a2be76a352f1 scripts/setlocalversion: remove workaround for old make-kpkg ffaf62a8050b scripts/setlocalversion: add more comments to -dirty flag detection 630ff0faf84e scripts/setlocalversion: factor out 12-chars hash construction 042da426f8eb scripts/setlocalversion: simplify the short version part 5df99bec210a scripts/setlocalversion: fix a bug when LOCALVERSION is empty (1) 7d153696e5db kbuild: do not include include/config/auto.conf from shell scripts (2) 129ab0d2d9f3 kbuild: do not quote string values in include/config/auto.conf f6e09b07cc12 kbuild: do not put .scmversion into the source tarball 992ebfab2a75 setlocalversion: simplify the construction of the short version 75280bdf49b2 setlocalversion: make indentation shallower (3) ec31f868ec67 setlocalversion: absorb $(KERNELVERSION) eed36d775177 setlocalversion: clean up the construction of version output (4) 6ab7e1f95e96 setlocalversion: use only the correct release tag for git-describe 05e96e96a315 kbuild: use git-archive for source package creation 3354c64d4184 scripts/setlocalversion: clean up stale comment 01e89a4acefc scripts/setlocalversion: also consider annotated tags of the form vx.y.z-${file_localversion} The only thing U-Boot has been applying on top was to deal with not sourcing include/config/auto.conf but instead using awk to extract the right value. Commit (1) did a very similar thing upstream, so we no longer need to do that. However, upstream then went a step further (2) and changed the convention for what goes into auto.conf, so RHS no longer contain double-quotes. That commit thus changed the sed pattern to no longer match those quotes, but as U-Boot has not yet adopted that change, we have to deal with that. In order to be a little forward-compatible, I did that in a way that should work both ways: # version string from CONFIG_LOCALVERSION -config_localversion=$(sed -n 's/^CONFIG_LOCALVERSION=\(.*\)$/\1/p' include/config/auto.conf) +config_localversion=$(sed -n 's/^CONFIG_LOCALVERSION=\(.*\)$/\1/p' include/config/auto.conf | tr -d '"') Furthermore, (3) now requires that there is an appropriate KERNELVERSION environment variable set. One way to deal with that would be to just modify the script to use UBOOTVERSION instead, but for now I've instead opted to let the Makefile provide KERNELVERSION=$(UBOOTVERSION) to keep the setlocalversion changes minimal. That variable is further put to use in (4). Note that the logic for mapping *VERSION -> [upstream annotated tag to look for] works unchanged in U-Boot for the current versioning scheme 20XX.YY(-rcN)?. My motivation for wanting to do this sync is to get (4) and (5), in order to get the setlocalversion output both more predictable and consistent across different build environments, i.e. independent of random local .gitconfig settings, total number of git objects and/or existence of unrelated tags (possibly from some tracked fork). Signed-off-by: Rasmus Villemoes --- Makefile | 5 +- scripts/setlocalversion | 236 ++++++++++++++++++++-------------------- 2 files changed, 121 insertions(+), 120 deletions(-) diff --git a/Makefile b/Makefile index efaf24e58e7..14acea9c6b9 100644 --- a/Makefile +++ b/Makefile @@ -1898,8 +1898,11 @@ $(filter-out tools, $(u-boot-dirs)): tools # is "yes"), so compile examples after U-Boot is compiled. examples: $(filter-out examples, $(u-boot-dirs)) +# The setlocalversion script comes from linux and expects a +# KERNELVERSION variable in the environment for figuring out which +# annotated tags are relevant. Pass UBOOTVERSION. define filechk_uboot.release - echo "$(UBOOTVERSION)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))" + KERNELVERSION=$(UBOOTVERSION) $(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree) endef # Store (new) UBOOTRELEASE string in include/config/uboot.release diff --git a/scripts/setlocalversion b/scripts/setlocalversion index 4a631437067..dbe048210d6 100755 --- a/scripts/setlocalversion +++ b/scripts/setlocalversion @@ -2,7 +2,7 @@ # SPDX-License-Identifier: GPL-2.0 # # This scripts adds local version information from the version -# control systems git, mercurial (hg) and subversion (svn). +# control system git. # # If something goes wrong, send a mail the kernel build mailinglist # (see MAINTAINERS) and CC Nico Schottelius @@ -11,16 +11,17 @@ # usage() { - echo "Usage: $0 [--save-scmversion] [srctree]" >&2 + echo "Usage: $0 [--no-local] [srctree]" >&2 exit 1 } -scm_only=false -srctree=. -if test "$1" = "--save-scmversion"; then - scm_only=true +no_local=false +if test "$1" = "--no-local"; then + no_local=true shift fi + +srctree=. if test $# -gt 0; then srctree=$1 shift @@ -31,97 +32,99 @@ fi scm_version() { - local short - short=false + local short=false + local no_dirty=false + local tag + + while [ $# -gt 0 ]; + do + case "$1" in + --short) + short=true;; + --no-dirty) + no_dirty=true;; + esac + shift + done cd "$srctree" - if test -e .scmversion; then - cat .scmversion - return - fi - if test "$1" = "--short"; then - short=true - fi - # Check for git and a git repo. - if test -z "$(git rev-parse --show-cdup 2>/dev/null)" && - head=$(git rev-parse --verify --short HEAD 2>/dev/null); then - - # If we are at a tagged commit (like "v2.6.30-rc6"), we ignore - # it, because this version is defined in the top level Makefile. - if [ -z "$(git describe --exact-match 2>/dev/null)" ]; then - - # If only the short version is requested, don't bother - # running further git commands - if $short; then - echo "+" - return - fi - # If we are past a tagged commit (like - # "v2.6.30-rc5-302-g72357d5"), we pretty print it. - if atag="$(git describe 2>/dev/null)"; then - echo "$atag" | awk -F- '{printf("-%05d-%s", $(NF-1),$(NF))}' - - # If we don't have a tag at all we print -g{commitish}. - else - printf '%s%s' -g $head - fi - fi - - # Is this git on svn? - if git config --get svn-remote.svn.url >/dev/null; then - printf -- '-svn%s' "$(git svn find-rev $head)" - fi - - # Check for uncommitted changes. - # First, with git-status, but --no-optional-locks is only - # supported in git >= 2.14, so fall back to git-diff-index if - # it fails. Note that git-diff-index does not refresh the - # index, so it may give misleading results. See - # git-update-index(1), git-diff-index(1), and git-status(1). - if { - git --no-optional-locks status -uno --porcelain 2>/dev/null || - git diff-index --name-only HEAD - } | grep -qvE '^(.. )?scripts/package'; then - printf '%s' -dirty - fi - - # All done with git + if test -n "$(git rev-parse --show-cdup 2>/dev/null)"; then return fi - # Check for mercurial and a mercurial repo. - if test -d .hg && hgid=$(hg id 2>/dev/null); then - # Do we have an tagged version? If so, latesttagdistance == 1 - if [ "$(hg log -r . --template '{latesttagdistance}')" = "1" ]; then - id=$(hg log -r . --template '{latesttag}') - printf '%s%s' -hg "$id" - else - tag=$(printf '%s' "$hgid" | cut -d' ' -f2) - if [ -z "$tag" -o "$tag" = tip ]; then - id=$(printf '%s' "$hgid" | sed 's/[+ ].*//') - printf '%s%s' -hg "$id" - fi - fi - - # Are there uncommitted changes? - # These are represented by + after the changeset id. - case "$hgid" in - *+|*+\ *) printf '%s' -dirty ;; - esac - - # All done with mercurial + if ! head=$(git rev-parse --verify HEAD 2>/dev/null); then return fi - # Check for svn and a svn repo. - if rev=$(LANG= LC_ALL= LC_MESSAGES=C svn info 2>/dev/null | grep '^Last Changed Rev'); then - rev=$(echo $rev | awk '{print $NF}') - printf -- '-svn%s' "$rev" + # mainline kernel: 6.2.0-rc5 -> v6.2-rc5 + # stable kernel: 6.1.7 -> v6.1.7 + version_tag=v$(echo "${KERNELVERSION}" | sed -E 's/^([0-9]+\.[0-9]+)\.0(.*)$/\1\2/') - # All done with svn + # If a localversion* file exists, and the corresponding + # annotated tag exists and is an ancestor of HEAD, use + # it. This is the case in linux-next. + tag=${file_localversion#-} + desc= + if [ -n "${tag}" ]; then + desc=$(git describe --match=$tag 2>/dev/null) + fi + + # Otherwise, if a localversion* file exists, and the tag + # obtained by appending it to the tag derived from + # KERNELVERSION exists and is an ancestor of HEAD, use + # it. This is e.g. the case in linux-rt. + if [ -z "${desc}" ] && [ -n "${file_localversion}" ]; then + tag="${version_tag}${file_localversion}" + desc=$(git describe --match=$tag 2>/dev/null) + fi + + # Otherwise, default to the annotated tag derived from KERNELVERSION. + if [ -z "${desc}" ]; then + tag="${version_tag}" + desc=$(git describe --match=$tag 2>/dev/null) + fi + + # If we are at the tagged commit, we ignore it because the version is + # well-defined. + if [ "${tag}" != "${desc}" ]; then + + # If only the short version is requested, don't bother + # running further git commands + if $short; then + echo "+" + return + fi + # If we are past the tagged commit, we pretty print it. + # (like 6.1.0-14595-g292a089d78d3) + if [ -n "${desc}" ]; then + echo "${desc}" | awk -F- '{printf("-%05d", $(NF-1))}' + fi + + # Add -g and exactly 12 hex chars. + printf '%s%s' -g "$(echo $head | cut -c1-12)" + fi + + if ${no_dirty}; then return fi + + # Check for uncommitted changes. + # This script must avoid any write attempt to the source tree, which + # might be read-only. + # You cannot use 'git describe --dirty' because it tries to create + # .git/index.lock . + # First, with git-status, but --no-optional-locks is only supported in + # git >= 2.14, so fall back to git-diff-index if it fails. Note that + # git-diff-index does not refresh the index, so it may give misleading + # results. + # See git-update-index(1), git-diff-index(1), and git-status(1). + if { + git --no-optional-locks status -uno --porcelain 2>/dev/null || + git diff-index --name-only HEAD + } | read dummy; then + printf '%s' -dirty + fi } collect_files() @@ -141,48 +144,43 @@ collect_files() echo "$res" } -if $scm_only; then - if test ! -e .scmversion; then - res=$(scm_version) - echo "$res" >.scmversion - fi - exit -fi - -if test -e include/config/auto.conf; then - # We are interested only in CONFIG_LOCALVERSION and - # CONFIG_LOCALVERSION_AUTO, so extract these in a safe - # way (i.e. w/o sourcing auto.conf) - # xargs echo removes quotes - CONFIG_LOCALVERSION=`cat include/config/auto.conf | awk -F '=' '/^CONFIG_LOCALVERSION=/ {print $2}' | xargs echo` - CONFIG_LOCALVERSION_AUTO=`cat include/config/auto.conf | awk -F '=' '/^CONFIG_LOCALVERSION_AUTO=/ {print $2}' | xargs echo` -else - echo "Error: kernelrelease not valid - run 'make prepare' to update it" >&2 +if [ -z "${KERNELVERSION}" ]; then + echo "KERNELVERSION is not set" >&2 exit 1 fi # localversion* files in the build and source directory -res="$(collect_files localversion*)" +file_localversion="$(collect_files localversion*)" if test ! "$srctree" -ef .; then - res="$res$(collect_files "$srctree"/localversion*)" + file_localversion="${file_localversion}$(collect_files "$srctree"/localversion*)" fi -# CONFIG_LOCALVERSION and LOCALVERSION (if set) -res="${res}${CONFIG_LOCALVERSION}${LOCALVERSION}" +if ${no_local}; then + echo "${KERNELVERSION}$(scm_version --no-dirty)" + exit 0 +fi -# scm version string if not at a tagged commit -if test "$CONFIG_LOCALVERSION_AUTO" = "y"; then +if ! test -e include/config/auto.conf; then + echo "Error: kernelrelease not valid - run 'make prepare' to update it" >&2 + exit 1 +fi + +# version string from CONFIG_LOCALVERSION +config_localversion=$(sed -n 's/^CONFIG_LOCALVERSION=\(.*\)$/\1/p' include/config/auto.conf | tr -d '"') + +# scm version string if not at the kernel version tag or at the file_localversion +if grep -q "^CONFIG_LOCALVERSION_AUTO=y$" include/config/auto.conf; then # full scm version string - res="$res$(scm_version)" -else - # append a plus sign if the repository is not in a clean - # annotated or signed tagged state (as git describe only - # looks at signed or annotated tags - git tag -a/-s) and - # LOCALVERSION= is not specified - if test "${LOCALVERSION+set}" != "set"; then - scm=$(scm_version --short) - res="$res${scm:++}" - fi + scm_version="$(scm_version)" +elif [ "${LOCALVERSION+set}" != "set" ]; then + # If the variable LOCALVERSION is not set, append a plus + # sign if the repository is not in a clean annotated or + # signed tagged state (as git describe only looks at signed + # or annotated tags - git tag -a/-s). + # + # If the variable LOCALVERSION is set (including being set + # to an empty string), we don't want to append a plus sign. + scm_version="$(scm_version --short)" fi -echo "$res" +echo "${KERNELVERSION}${file_localversion}${config_localversion}${LOCALVERSION}${scm_version}" From d9e9e699becf20d9fd06c3067b52c78b1e4d6d59 Mon Sep 17 00:00:00 2001 From: Raymond Mao Date: Thu, 16 May 2024 14:11:49 -0700 Subject: [PATCH 040/383] image: remove redundant hash includes Remove the redundant includes of u-boot/md5.h, u-boot/sha1.h, u-boot/sha256.h and u-boot/sha512.h Signed-off-by: Raymond Mao Reviewed-by: Tom Rini Reviewed-by: Igor Opaniuk Reviewed-by: Ilias Apalodimas --- boot/image-fit.c | 4 ---- boot/image.c | 2 -- 2 files changed, 6 deletions(-) diff --git a/boot/image-fit.c b/boot/image-fit.c index fb03cab831b..f6464bcf620 100644 --- a/boot/image-fit.c +++ b/boot/image-fit.c @@ -37,10 +37,6 @@ DECLARE_GLOBAL_DATA_PTR; #include #include #include -#include -#include -#include -#include /*****************************************************************************/ /* New uImage format routines */ diff --git a/boot/image.c b/boot/image.c index eb12e4be04a..bacf5146e13 100644 --- a/boot/image.c +++ b/boot/image.c @@ -25,8 +25,6 @@ #endif #include -#include -#include #include #include From 329bb6677bf9cee18d4b87cb067ee832d0bb8e7b Mon Sep 17 00:00:00 2001 From: Raymond Mao Date: Thu, 16 May 2024 14:11:50 -0700 Subject: [PATCH 041/383] efi_loader: remove redundant hash includes Remove the redundant includes of u-boot/sha1.h, u-boot/sha256.h and u-boot/sha512.h Signed-off-by: Raymond Mao Reviewed-by: Tom Rini Reviewed-by: Ilias Apalodimas --- lib/efi_loader/efi_signature.c | 1 - lib/efi_loader/efi_tcg2.c | 3 --- 2 files changed, 4 deletions(-) diff --git a/lib/efi_loader/efi_signature.c b/lib/efi_loader/efi_signature.c index f338e732759..184eac8cddb 100644 --- a/lib/efi_loader/efi_signature.c +++ b/lib/efi_loader/efi_signature.c @@ -17,7 +17,6 @@ #include #include #include -#include const efi_guid_t efi_guid_sha256 = EFI_CERT_SHA256_GUID; const efi_guid_t efi_guid_cert_rsa2048 = EFI_CERT_RSA2048_GUID; diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c index b07e0099c27..ac056dcfc55 100644 --- a/lib/efi_loader/efi_tcg2.c +++ b/lib/efi_loader/efi_tcg2.c @@ -19,9 +19,6 @@ #include #include #include -#include -#include -#include #include #include #include From 0fe031dd722079cd076cc120d45e1711eb108fe3 Mon Sep 17 00:00:00 2001 From: Raymond Mao Date: Thu, 16 May 2024 14:11:51 -0700 Subject: [PATCH 042/383] md5: Use typedef for MD5 context Use of typedef is beneficial for porting with other crypto libs without changing the API callers. Secondly, it is for the code consistency with other digest libs. SHA1, SHA256 and SHA512 are all using typedef for their context. Signed-off-by: Raymond Mao Reviewed-by: Tom Rini Reviewed-by: Ilias Apalodimas --- drivers/crypto/hash/hash_sw.c | 8 ++++---- include/u-boot/md5.h | 10 +++++----- lib/md5.c | 10 +++++----- 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/crypto/hash/hash_sw.c b/drivers/crypto/hash/hash_sw.c index ffd4ab149ff..4590e225481 100644 --- a/drivers/crypto/hash/hash_sw.c +++ b/drivers/crypto/hash/hash_sw.c @@ -50,17 +50,17 @@ static void hash_finish_crc32(void *ctx, void *obuf) /* MD5 */ static void hash_init_md5(void *ctx) { - MD5Init((struct MD5Context *)ctx); + MD5Init((MD5Context *)ctx); } static void hash_update_md5(void *ctx, const void *ibuf, uint32_t ilen) { - MD5Update((struct MD5Context *)ctx, ibuf, ilen); + MD5Update((MD5Context *)ctx, ibuf, ilen); } static void hash_finish_md5(void *ctx, void *obuf) { - MD5Final(obuf, (struct MD5Context *)ctx); + MD5Final(obuf, (MD5Context *)ctx); } /* SHA1 */ @@ -158,7 +158,7 @@ static struct sw_hash_impl sw_hash_impl[HASH_ALGO_NUM] = { .init = hash_init_md5, .update = hash_update_md5, .finish = hash_finish_md5, - .ctx_alloc_sz = sizeof(struct MD5Context), + .ctx_alloc_sz = sizeof(MD5Context), }, [HASH_ALGO_SHA1] = { diff --git a/include/u-boot/md5.h b/include/u-boot/md5.h index d61364c0ae3..c465925ea8d 100644 --- a/include/u-boot/md5.h +++ b/include/u-boot/md5.h @@ -10,18 +10,18 @@ #define MD5_SUM_LEN 16 -struct MD5Context { +typedef struct MD5Context { __u32 buf[4]; __u32 bits[2]; union { unsigned char in[64]; __u32 in32[16]; }; -}; +} MD5Context; -void MD5Init(struct MD5Context *ctx); -void MD5Update(struct MD5Context *ctx, unsigned char const *buf, unsigned len); -void MD5Final(unsigned char digest[16], struct MD5Context *ctx); +void MD5Init(MD5Context *ctx); +void MD5Update(MD5Context *ctx, unsigned char const *buf, unsigned int len); +void MD5Final(unsigned char digest[16], MD5Context *ctx); /* * Calculate and store in 'output' the MD5 digest of 'len' bytes at diff --git a/lib/md5.c b/lib/md5.c index faf3f78ab1e..34343cf8e23 100644 --- a/lib/md5.c +++ b/lib/md5.c @@ -55,7 +55,7 @@ byteReverse(unsigned char *buf, unsigned longs) * initialization constants. */ void -MD5Init(struct MD5Context *ctx) +MD5Init(MD5Context *ctx) { ctx->buf[0] = 0x67452301; ctx->buf[1] = 0xefcdab89; @@ -71,7 +71,7 @@ MD5Init(struct MD5Context *ctx) * of bytes. */ void -MD5Update(struct MD5Context *ctx, unsigned char const *buf, unsigned len) +MD5Update(MD5Context *ctx, unsigned char const *buf, unsigned int len) { register __u32 t; @@ -120,7 +120,7 @@ MD5Update(struct MD5Context *ctx, unsigned char const *buf, unsigned len) * 1 0* (64-bit count of bits processed, MSB-first) */ void -MD5Final(unsigned char digest[16], struct MD5Context *ctx) +MD5Final(unsigned char digest[16], MD5Context *ctx) { unsigned int count; unsigned char *p; @@ -269,7 +269,7 @@ MD5Transform(__u32 buf[4], __u32 const in[16]) void md5 (unsigned char *input, int len, unsigned char output[16]) { - struct MD5Context context; + MD5Context context; MD5Init(&context); MD5Update(&context, input, len); @@ -286,7 +286,7 @@ void md5_wd(const unsigned char *input, unsigned int len, unsigned char output[16], unsigned int chunk_sz) { - struct MD5Context context; + MD5Context context; #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) const unsigned char *end, *curr; int chunk; From cb73fe9eeae0d71a74eef811b0ba34aaf5513dbe Mon Sep 17 00:00:00 2001 From: Raymond Mao Date: Thu, 16 May 2024 14:11:52 -0700 Subject: [PATCH 043/383] include: Move snprintf to stdio.h Move snprintf to stdio.h since it is needed by exteranl libraries. Signed-off-by: Raymond Mao Reviewed-by: Tom Rini Reviewed-by: Ilias Apalodimas --- arch/arc/lib/cpu.c | 2 +- board/Synology/common/legacy.c | 1 + board/ti/common/fdt_ops.c | 2 +- cmd/part.c | 1 + common/button_cmd.c | 2 +- drivers/cpu/mpc83xx_cpu.c | 2 +- include/stdio.h | 17 +++++++++++++++++ include/vsprintf.h | 17 ----------------- lib/display_options.c | 1 + lib/fwu_updates/fwu_mtd.c | 2 +- lib/hexdump.c | 2 +- lib/vsprintf.c | 1 + test/dm/scmi.c | 2 +- test/print_ut.c | 1 + 14 files changed, 29 insertions(+), 24 deletions(-) diff --git a/arch/arc/lib/cpu.c b/arch/arc/lib/cpu.c index 593950449f2..269b4dbdd15 100644 --- a/arch/arc/lib/cpu.c +++ b/arch/arc/lib/cpu.c @@ -7,7 +7,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/Synology/common/legacy.c b/board/Synology/common/legacy.c index a0bace7b46c..2e3aa660eaa 100644 --- a/board/Synology/common/legacy.c +++ b/board/Synology/common/legacy.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/board/ti/common/fdt_ops.c b/board/ti/common/fdt_ops.c index eb917be9e0d..8a3300993ed 100644 --- a/board/ti/common/fdt_ops.c +++ b/board/ti/common/fdt_ops.c @@ -6,7 +6,7 @@ */ #include -#include +#include #include "fdt_ops.h" void ti_set_fdt_env(const char *board_name, struct ti_fdt_map *fdt_map) diff --git a/cmd/part.c b/cmd/part.c index d140a1eddb9..db7bc5819c0 100644 --- a/cmd/part.c +++ b/cmd/part.c @@ -19,6 +19,7 @@ #include #include #include +#include #include enum cmd_part_info { diff --git a/common/button_cmd.c b/common/button_cmd.c index 8642c26735c..72dac1f9ef6 100644 --- a/common/button_cmd.c +++ b/common/button_cmd.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include /* Some sane limit "just in case" */ #define MAX_BTN_CMDS 32 diff --git a/drivers/cpu/mpc83xx_cpu.c b/drivers/cpu/mpc83xx_cpu.c index 9a7b5fd7c42..127d3c3af08 100644 --- a/drivers/cpu/mpc83xx_cpu.c +++ b/drivers/cpu/mpc83xx_cpu.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include "mpc83xx_cpu.h" diff --git a/include/stdio.h b/include/stdio.h index 3241e2d493f..7b999a519ba 100644 --- a/include/stdio.h +++ b/include/stdio.h @@ -46,6 +46,23 @@ static inline int vprintf(const char *fmt, va_list args) } #endif +/** + * Format a string and place it in a buffer + * + * @buf: The buffer to place the result into + * @size: The size of the buffer, including the trailing null space + * @fmt: The format string to use + * @...: Arguments for the format string + * Return: the number of characters which would be + * generated for the given input, excluding the trailing null, + * as per ISO C99. If the return is greater than or equal to + * @size, the resulting string is truncated. + * + * See the vsprintf() documentation for format string extensions over C99. + */ +int snprintf(char *buf, size_t size, const char *fmt, ...) + __attribute__ ((format (__printf__, 3, 4))); + /* * FILE based functions (can only be used AFTER relocation!) */ diff --git a/include/vsprintf.h b/include/vsprintf.h index ed8a060ee17..fe951471426 100644 --- a/include/vsprintf.h +++ b/include/vsprintf.h @@ -218,23 +218,6 @@ char *simple_itoa(ulong val); */ char *simple_xtoa(ulong num); -/** - * Format a string and place it in a buffer - * - * @buf: The buffer to place the result into - * @size: The size of the buffer, including the trailing null space - * @fmt: The format string to use - * @...: Arguments for the format string - * Return: the number of characters which would be - * generated for the given input, excluding the trailing null, - * as per ISO C99. If the return is greater than or equal to - * @size, the resulting string is truncated. - * - * See the vsprintf() documentation for format string extensions over C99. - */ -int snprintf(char *buf, size_t size, const char *fmt, ...) - __attribute__ ((format (__printf__, 3, 4))); - /** * Format a string and place it in a buffer * diff --git a/lib/display_options.c b/lib/display_options.c index d6b93553dcb..d5df53ab15f 100644 --- a/lib/display_options.c +++ b/lib/display_options.c @@ -12,6 +12,7 @@ #include #include #include +#include #include char *display_options_get_banner_priv(bool newlines, const char *build_tag, diff --git a/lib/fwu_updates/fwu_mtd.c b/lib/fwu_updates/fwu_mtd.c index 69cd3d7001f..4a52834b61a 100644 --- a/lib/fwu_updates/fwu_mtd.c +++ b/lib/fwu_updates/fwu_mtd.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include diff --git a/lib/hexdump.c b/lib/hexdump.c index 33e3e6e5182..2bc508ff504 100644 --- a/lib/hexdump.c +++ b/lib/hexdump.c @@ -10,7 +10,7 @@ #include #include -#include +#include #include #include #include diff --git a/lib/vsprintf.c b/lib/vsprintf.c index 27ea9c907a3..cfd1f1914ed 100644 --- a/lib/vsprintf.c +++ b/lib/vsprintf.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include diff --git a/test/dm/scmi.c b/test/dm/scmi.c index 69fc900e342..c9a03523184 100644 --- a/test/dm/scmi.c +++ b/test/dm/scmi.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/test/print_ut.c b/test/print_ut.c index bded2b6ebe5..53d3354ea69 100644 --- a/test/print_ut.c +++ b/test/print_ut.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include From bc6beae7c55f3adc1fc520ff8c3f4ec986f7c2ef Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 21 May 2024 12:48:23 +0200 Subject: [PATCH 044/383] binman: Add nxp_imx8mcst etype for i.MX8M flash.bin signing Add new binman etype which allows signing both the SPL and fitImage sections of i.MX8M flash.bin using CST. There are multiple DT properties which govern the signing process, nxp,loader-address is the only mandatory one which sets the SPL signature start address without the imx8mimage header, this should be SPL text base. The key material can be configured using optional DT properties nxp,srk-table, nxp,csf-crt, nxp,img-crt, all of which default the key material names generated by CST tool scripts. The nxp,unlock property can be used to unlock CAAM access in SPL section. Reviewed-by: Tim Harvey Signed-off-by: Marek Vasut --- .gitignore | 2 + Makefile | 2 +- tools/binman/btool/cst.py | 48 +++++++++ tools/binman/etype/nxp_imx8mcst.py | 164 +++++++++++++++++++++++++++++ 4 files changed, 215 insertions(+), 1 deletion(-) create mode 100644 tools/binman/btool/cst.py create mode 100644 tools/binman/etype/nxp_imx8mcst.py diff --git a/.gitignore b/.gitignore index 37f71c275c3..502a7e6ec70 100644 --- a/.gitignore +++ b/.gitignore @@ -73,6 +73,8 @@ fit-dtb.blob* /capsule.*.efi-capsule /capsule*.map /keep-syms-lto.* +/*imx8mimage* +/*imx8mcst* # # Generated include files diff --git a/Makefile b/Makefile index e3a0eaff942..c014b0d4b91 100644 --- a/Makefile +++ b/Makefile @@ -2213,7 +2213,7 @@ MRPROPER_DIRS += include/config include/generated spl tpl vpl \ # Remove include/asm symlink created by U-Boot before v2014.01 MRPROPER_FILES += .config .config.old include/autoconf.mk* include/config.h \ ctags etags tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \ - drivers/video/fonts/*.S include/asm + drivers/video/fonts/*.S include/asm *imx8mimage* *imx8mcst* # clean - Delete most, but leave enough to build external modules # diff --git a/tools/binman/btool/cst.py b/tools/binman/btool/cst.py new file mode 100644 index 00000000000..30e78bdbbd9 --- /dev/null +++ b/tools/binman/btool/cst.py @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright 2024 Marek Vasut +# +"""Bintool implementation for cst""" + +import re + +from binman import bintool + +class Bintoolcst(bintool.Bintool): + """Image generation for U-Boot + + This bintool supports running `cst` with some basic parameters as + needed by binman. + """ + def __init__(self, name): + super().__init__(name, 'Sign NXP i.MX image') + + # pylint: disable=R0913 + def run(self, output_fname=None): + """Run cst + + Args: + output_fname: Output filename to write to + """ + args = [] + if output_fname: + args += ['-o', output_fname] + return self.run_cmd(*args) + + def fetch(self, method): + """Fetch handler for cst + + This installs cst using the apt utility. + + Args: + method (FETCH_...): Method to use + + Returns: + True if the file was fetched and now installed, None if a method + other than FETCH_BIN was requested + + Raises: + Valuerror: Fetching could not be completed + """ + if method != bintool.FETCH_BIN: + return None + return self.apt_install('imx-code-signing-tool') diff --git a/tools/binman/etype/nxp_imx8mcst.py b/tools/binman/etype/nxp_imx8mcst.py new file mode 100644 index 00000000000..8221517b0c4 --- /dev/null +++ b/tools/binman/etype/nxp_imx8mcst.py @@ -0,0 +1,164 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright 2023-2024 Marek Vasut +# Written with much help from Simon Glass +# +# Entry-type module for generating the i.MX8M code signing tool +# input configuration file and invocation of cst on generated +# input configuration file and input data to be signed. +# + +import configparser +import os +import struct + +from collections import OrderedDict + +from binman.entry import Entry +from binman.etype.mkimage import Entry_mkimage +from binman.etype.section import Entry_section +from binman import elf +from dtoc import fdt_util +from u_boot_pylib import tools + +MAGIC_NXP_IMX_IVT = 0x412000d1 +MAGIC_FITIMAGE = 0xedfe0dd0 + +csf_config_template = """ +[Header] + Version = 4.3 + Hash Algorithm = sha256 + Engine = CAAM + Engine Configuration = 0 + Certificate Format = X509 + Signature Format = CMS + +[Install SRK] + File = "SRK_1_2_3_4_table.bin" + Source index = 0 + +[Install CSFK] + File = "CSF1_1_sha256_4096_65537_v3_usr_crt.pem" + +[Authenticate CSF] + +[Unlock] + Engine = CAAM + Features = MID + +[Install Key] + Verification index = 0 + Target Index = 2 + File = "IMG1_1_sha256_4096_65537_v3_usr_crt.pem" + +[Authenticate Data] + Verification index = 2 + Blocks = 0x1234 0x78 0xabcd "data.bin" +""" + +class Entry_nxp_imx8mcst(Entry_mkimage): + """NXP i.MX8M CST .cfg file generator and cst invoker + + Properties / Entry arguments: + - nxp,loader-address - loader address (SPL text base) + """ + + def __init__(self, section, etype, node): + super().__init__(section, etype, node) + self.required_props = ['nxp,loader-address'] + + def ReadNode(self): + super().ReadNode() + self.loader_address = fdt_util.GetInt(self._node, 'nxp,loader-address') + self.srk_table = os.getenv('SRK_TABLE', fdt_util.GetString(self._node, 'nxp,srk-table', 'SRK_1_2_3_4_table.bin')) + self.csf_crt = os.getenv('CSF_KEY', fdt_util.GetString(self._node, 'nxp,csf-crt', 'CSF1_1_sha256_4096_65537_v3_usr_crt.pem')) + self.img_crt = os.getenv('IMG_KEY', fdt_util.GetString(self._node, 'nxp,img-crt', 'IMG1_1_sha256_4096_65537_v3_usr_crt.pem')) + self.unlock = fdt_util.GetBool(self._node, 'nxp,unlock') + self.ReadEntries() + + def BuildSectionData(self, required): + data, input_fname, uniq = self.collect_contents_to_file( + self._entries.values(), 'input') + + # Parse the input data and figure out what it is that is being signed. + # - If it is mkimage'd imx8mimage, then extract to be signed data size + # from imx8mimage header, and calculate CSF blob offset right past + # the SPL from this information. + # - If it is fitImage, then pad the image to 4k, add generated IVT and + # sign the whole payload, then append CSF blob at the end right past + # the IVT. + signtype = struct.unpack(' Date: Tue, 21 May 2024 12:48:24 +0200 Subject: [PATCH 045/383] ARM: dts: imx: Introduce SPL and FIT labels to i.MX8M DTs binman nodes Add binman_imx_spl and binman_imx_fit labels to nxp-imx8mimage {} and fit {} nodes respectively, so they can be referened in board DTs no matter how deep in the top level binman image description they are. Update current board DTs to use those labels. Reviewed-by: Tim Harvey Signed-off-by: Marek Vasut --- arch/arm/dts/imx8mm-u-boot.dtsi | 4 +- .../dts/imx8mm-verdin-wifi-dev-u-boot.dtsi | 8 +- arch/arm/dts/imx8mn-u-boot.dtsi | 4 +- arch/arm/dts/imx8mp-dhcom-u-boot.dtsi | 120 +++++++++--------- arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi | 24 ++-- arch/arm/dts/imx8mp-u-boot.dtsi | 4 +- arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi | 10 +- arch/arm/dts/imx8mq-u-boot.dtsi | 4 +- 8 files changed, 81 insertions(+), 97 deletions(-) diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi index 6ab8f66256e..b9b1193823a 100644 --- a/arch/arm/dts/imx8mm-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-u-boot.dtsi @@ -54,7 +54,7 @@ }; #endif - nxp-imx8mimage { + binman_imx_spl: nxp-imx8mimage { filename = "u-boot-spl-mkimage.bin"; nxp,boot-from = "sd"; nxp,rom-version = <1>; @@ -98,7 +98,7 @@ }; }; - fit { + binman_imx_fit: fit { description = "Configuration to load ATF before U-Boot"; #ifndef CONFIG_IMX_HAB fit,external-offset = ; diff --git a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi index 90183aff8bc..183de46f66a 100644 --- a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi @@ -35,12 +35,8 @@ bootph-pre-ram; }; -&binman { - section { - fit { - offset = <0x5fc00>; - }; - }; +&binman_imx_fit { + offset = <0x5fc00>; }; &gpio1 { diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi index ba9967dbe4a..c9fb33cfb73 100644 --- a/arch/arm/dts/imx8mn-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-u-boot.dtsi @@ -103,7 +103,7 @@ }; #endif - nxp-imx8mimage { + binman_imx_spl: nxp-imx8mimage { filename = "u-boot-spl-mkimage.bin"; nxp,boot-from = "sd"; nxp,rom-version = <2>; @@ -169,7 +169,7 @@ }; }; - fit { + binman_imx_fit: fit { description = "Configuration to load ATF before U-Boot"; #ifndef CONFIG_IMX_HAB fit,external-offset = ; diff --git a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi index cb37e28f28f..c065fb82994 100644 --- a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi @@ -135,73 +135,69 @@ bootph-pre-ram; }; -&binman { - section { - fit { - images { - fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast { - description = "imx8mp-dhcom-som-overlay-eth1xfast"; - type = "flat_dt"; - compression = "none"; +&binman_imx_fit { + images { + fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast { + description = "imx8mp-dhcom-som-overlay-eth1xfast"; + type = "flat_dt"; + compression = "none"; - blob-ext { - filename = "imx8mp-dhcom-som-overlay-eth1xfast.dtbo"; - }; - }; - - fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast { - description = "imx8mp-dhcom-som-overlay-eth2xfast"; - type = "flat_dt"; - compression = "none"; - - blob-ext { - filename = "imx8mp-dhcom-som-overlay-eth2xfast.dtbo"; - }; - }; - - fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast { - description = "imx8mp-dhcom-pdk-overlay-eth2xfast"; - type = "flat_dt"; - compression = "none"; - - blob-ext { - filename = "imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo"; - }; - }; - - fdt-dto-imx8mp-dhcom-som-overlay-rev100 { - description = "imx8mp-dhcom-som-overlay-rev100"; - type = "flat_dt"; - compression = "none"; - - blob-ext { - filename = "imx8mp-dhcom-som-overlay-rev100.dtbo"; - }; - }; - - fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100 { - description = "imx8mp-dhcom-pdk3-overlay-rev100"; - type = "flat_dt"; - compression = "none"; - - blob-ext { - filename = "imx8mp-dhcom-pdk3-overlay-rev100.dtbo"; - }; - }; + blob-ext { + filename = "imx8mp-dhcom-som-overlay-eth1xfast.dtbo"; }; + }; - configurations { - default = "@config-DEFAULT-SEQ"; + fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast { + description = "imx8mp-dhcom-som-overlay-eth2xfast"; + type = "flat_dt"; + compression = "none"; - @config-SEQ { - fdt = "fdt-1", - "fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast", - "fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast", - "fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast", - "fdt-dto-imx8mp-dhcom-som-overlay-rev100", - "fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100"; - }; + blob-ext { + filename = "imx8mp-dhcom-som-overlay-eth2xfast.dtbo"; + }; + }; + + fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast { + description = "imx8mp-dhcom-pdk-overlay-eth2xfast"; + type = "flat_dt"; + compression = "none"; + + blob-ext { + filename = "imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo"; + }; + }; + + fdt-dto-imx8mp-dhcom-som-overlay-rev100 { + description = "imx8mp-dhcom-som-overlay-rev100"; + type = "flat_dt"; + compression = "none"; + + blob-ext { + filename = "imx8mp-dhcom-som-overlay-rev100.dtbo"; + }; + }; + + fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100 { + description = "imx8mp-dhcom-pdk3-overlay-rev100"; + type = "flat_dt"; + compression = "none"; + + blob-ext { + filename = "imx8mp-dhcom-pdk3-overlay-rev100.dtbo"; }; }; }; + + configurations { + default = "@config-DEFAULT-SEQ"; + + @config-SEQ { + fdt = "fdt-1", + "fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast", + "fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast", + "fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast", + "fdt-dto-imx8mp-dhcom-som-overlay-rev100", + "fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100"; + }; + }; }; diff --git a/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi index aff5dcf615d..21eff6d6ad4 100644 --- a/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi @@ -135,21 +135,17 @@ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; }; -&binman { - section { - fit { - images { - fip { - description = "Trusted Firmware FIP"; - type = "firmware"; - arch = "arm64"; - compression = "none"; - load = <0x40310000>; +&binman_imx_fit { + images { + fip { + description = "Trusted Firmware FIP"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <0x40310000>; - fip_blob: blob-ext{ - filename = "fip.bin"; - }; - }; + fip_blob: blob-ext{ + filename = "fip.bin"; }; }; }; diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index c4c1a177102..8b5ac3faf1c 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -86,7 +86,7 @@ section { pad-byte = <0x00>; - nxp-imx8mimage { + binman_imx_spl: nxp-imx8mimage { filename = "u-boot-spl-mkimage.bin"; nxp,boot-from = "sd"; nxp,rom-version = <2>; @@ -129,7 +129,7 @@ }; }; - fit { + binman_imx_fit: fit { description = "Configuration to load ATF before U-Boot"; #ifndef CONFIG_IMX_HAB fit,external-offset = ; diff --git a/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi index 1a4568dac65..98da015a444 100644 --- a/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi @@ -10,14 +10,10 @@ bootph-pre-ram; }; -&binman { +&binman_imx_spl { section { - nxp-imx8mimage { - section { - signed-hdmi-imx8m { - filename = "signed_dp_imx8m.bin"; - }; - }; + signed-hdmi-imx8m { + filename = "signed_dp_imx8m.bin"; }; }; }; diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi index 48dbe94f0c4..72da674d245 100644 --- a/arch/arm/dts/imx8mq-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-u-boot.dtsi @@ -38,7 +38,7 @@ section { pad-byte = <0x00>; - nxp-imx8mimage { + binman_imx_spl: nxp-imx8mimage { filename = "u-boot-spl-mkimage.bin"; nxp,boot-from = "sd"; nxp,rom-version = <1>; @@ -87,7 +87,7 @@ }; }; - fit { + binman_imx_fit: fit { description = "Configuration to load ATF before U-Boot"; #ifndef CONFIG_IMX_HAB fit,external-offset = ; From d415a48b405ea218da37f1a9e9d02151a07862be Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 21 May 2024 12:48:25 +0200 Subject: [PATCH 046/383] ARM: dts: imx: Wrap i.MX8M binman SPL and FIT nodes in CST node if IMX_HAB enabled In case CONFIG_IMX_HAB is enabled, extend the binman image description for all of i.MX8M{Q,M,N,P} with CST wrapper node. This way, if CONFIG_IMX_HAB is enabled, binman will be automatically used to sign SPL and fitImage. Reviewed-by: Tim Harvey Signed-off-by: Marek Vasut --- arch/arm/dts/imx8mm-u-boot.dtsi | 211 +++++++++++++++------------- arch/arm/dts/imx8mn-u-boot.dtsi | 239 ++++++++++++++++++-------------- arch/arm/dts/imx8mp-u-boot.dtsi | 190 +++++++++++++------------ arch/arm/dts/imx8mq-u-boot.dtsi | 184 +++++++++++++----------- 4 files changed, 457 insertions(+), 367 deletions(-) diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi index b9b1193823a..c02e11def5f 100644 --- a/arch/arm/dts/imx8mm-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-u-boot.dtsi @@ -54,126 +54,151 @@ }; #endif - binman_imx_spl: nxp-imx8mimage { - filename = "u-boot-spl-mkimage.bin"; - nxp,boot-from = "sd"; - nxp,rom-version = <1>; +#ifdef CONFIG_IMX_HAB + nxp-imx8mcst@0 { + filename = "u-boot-spl-mkimage.signed.bin"; nxp,loader-address = ; + nxp,unlock; args; /* Needed by mkimage etype superclass */ +#endif - section { - align = <4>; - align-size = <4>; - filename = "u-boot-spl-ddr.bin"; - pad-byte = <0xff>; + binman_imx_spl: nxp-imx8mimage { + filename = "u-boot-spl-mkimage.bin"; + nxp,boot-from = "sd"; + nxp,rom-version = <1>; + nxp,loader-address = ; + args; /* Needed by mkimage etype superclass */ - u-boot-spl { - align-end = <4>; - filename = "u-boot-spl.bin"; - }; + section { + align = <4>; + align-size = <4>; + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; - ddr-1d-imem-fw { - filename = "lpddr4_pmu_train_1d_imem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + u-boot-spl { + align-end = <4>; + filename = "u-boot-spl.bin"; + }; - ddr-1d-dmem-fw { - filename = "lpddr4_pmu_train_1d_dmem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + ddr-1d-imem-fw { + filename = "lpddr4_pmu_train_1d_imem.bin"; + align-end = <4>; + type = "blob-ext"; + }; - ddr-2d-imem-fw { - filename = "lpddr4_pmu_train_2d_imem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + ddr-1d-dmem-fw { + filename = "lpddr4_pmu_train_1d_dmem.bin"; + align-end = <4>; + type = "blob-ext"; + }; - ddr-2d-dmem-fw { - filename = "lpddr4_pmu_train_2d_dmem.bin"; - align-end = <4>; - type = "blob-ext"; + ddr-2d-imem-fw { + filename = "lpddr4_pmu_train_2d_imem.bin"; + align-end = <4>; + type = "blob-ext"; + }; + + ddr-2d-dmem-fw { + filename = "lpddr4_pmu_train_2d_dmem.bin"; + align-end = <4>; + type = "blob-ext"; + }; }; }; +#ifdef CONFIG_IMX_HAB }; - binman_imx_fit: fit { - description = "Configuration to load ATF before U-Boot"; -#ifndef CONFIG_IMX_HAB - fit,external-offset = ; -#endif - fit,fdt-list = "of-list"; - #address-cells = <1>; + nxp-imx8mcst@1 { + filename = "u-boot-fit.signed.bin"; + nxp,loader-address = ; #ifdef CONFIG_FSPI_CONF_HEADER offset = <0x58C00>; #else offset = <0x57c00>; #endif - images { - uboot { - arch = "arm64"; - compression = "none"; - description = "U-Boot (64-bit)"; - load = ; - type = "standalone"; - - uboot-blob { - filename = "u-boot-nodtb.bin"; - type = "blob-ext"; - }; - }; - -#ifndef CONFIG_ARMV8_PSCI - atf { - arch = "arm64"; - compression = "none"; - description = "ARM Trusted Firmware"; - entry = <0x920000>; - load = <0x920000>; - type = "firmware"; - - atf-blob { - filename = "bl31.bin"; - type = "atf-bl31"; - }; - }; + args; /* Needed by mkimage etype superclass */ #endif - binman_fip: fip { - arch = "arm64"; - compression = "none"; - description = "Trusted Firmware FIP"; - load = <0x40310000>; - type = "firmware"; + binman_imx_fit: fit { + description = "Configuration to load ATF before U-Boot"; +#ifndef CONFIG_IMX_HAB + fit,external-offset = ; +#endif + fit,fdt-list = "of-list"; + #address-cells = <1>; +#ifdef CONFIG_FSPI_CONF_HEADER + offset = <0x58C00>; +#else + offset = <0x57c00>; +#endif + + images { + uboot { + arch = "arm64"; + compression = "none"; + description = "U-Boot (64-bit)"; + load = ; + type = "standalone"; + + uboot-blob { + filename = "u-boot-nodtb.bin"; + type = "blob-ext"; + }; + }; + +#ifndef CONFIG_ARMV8_PSCI + atf { + arch = "arm64"; + compression = "none"; + description = "ARM Trusted Firmware"; + entry = <0x920000>; + load = <0x920000>; + type = "firmware"; + + atf-blob { + filename = "bl31.bin"; + type = "atf-bl31"; + }; + }; +#endif + + binman_fip: fip { + arch = "arm64"; + compression = "none"; + description = "Trusted Firmware FIP"; + load = <0x40310000>; + type = "firmware"; + }; + + @fdt-SEQ { + compression = "none"; + description = "NAME"; + type = "flat_dt"; + + uboot-fdt-blob { + filename = "u-boot.dtb"; + type = "blob-ext"; + }; + }; }; - @fdt-SEQ { - compression = "none"; - description = "NAME"; - type = "flat_dt"; + configurations { + default = "@config-DEFAULT-SEQ"; - uboot-fdt-blob { - filename = "u-boot.dtb"; - type = "blob-ext"; + @config-SEQ { + description = "NAME"; + fdt = "fdt-SEQ"; + firmware = "uboot"; +#ifndef CONFIG_ARMV8_PSCI + loadables = "atf"; +#endif }; }; }; - - configurations { - default = "@config-DEFAULT-SEQ"; - - @config-SEQ { - description = "NAME"; - fdt = "fdt-SEQ"; - firmware = "uboot"; -#ifndef CONFIG_ARMV8_PSCI - loadables = "atf"; -#endif - }; - }; +#ifdef CONFIG_IMX_HAB }; +#endif }; }; diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi index c9fb33cfb73..732191f5205 100644 --- a/arch/arm/dts/imx8mn-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-u-boot.dtsi @@ -103,147 +103,172 @@ }; #endif - binman_imx_spl: nxp-imx8mimage { - filename = "u-boot-spl-mkimage.bin"; - nxp,boot-from = "sd"; - nxp,rom-version = <2>; +#ifdef CONFIG_IMX_HAB + nxp-imx8mcst@0 { + filename = "u-boot-spl-mkimage.signed.bin"; nxp,loader-address = ; + nxp,unlock; args; /* Needed by mkimage etype superclass */ - - section { - filename = "u-boot-spl-ddr.bin"; - pad-byte = <0xff>; - align-size = <4>; - align = <4>; - - u-boot-spl { - align-end = <4>; - filename = "u-boot-spl.bin"; - }; - - ddr-1d-imem-fw { -#ifdef CONFIG_IMX8M_LPDDR4 - filename = "lpddr4_pmu_train_1d_imem.bin"; -#elif CONFIG_IMX8M_DDR4 - filename = "ddr4_imem_1d_201810.bin"; -#else - filename = "ddr3_imem_1d.bin"; #endif - type = "blob-ext"; - align-end = <4>; - }; - ddr-1d-dmem-fw { + binman_imx_spl: nxp-imx8mimage { + filename = "u-boot-spl-mkimage.bin"; + nxp,boot-from = "sd"; + nxp,rom-version = <2>; + nxp,loader-address = ; + args; /* Needed by mkimage etype superclass */ + + section { + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + align-size = <4>; + align = <4>; + + u-boot-spl { + align-end = <4>; + filename = "u-boot-spl.bin"; + }; + + ddr-1d-imem-fw { #ifdef CONFIG_IMX8M_LPDDR4 - filename = "lpddr4_pmu_train_1d_dmem.bin"; + filename = "lpddr4_pmu_train_1d_imem.bin"; #elif CONFIG_IMX8M_DDR4 - filename = "ddr4_dmem_1d_201810.bin"; + filename = "ddr4_imem_1d_201810.bin"; #else - filename = "ddr3_dmem_1d.bin"; + filename = "ddr3_imem_1d.bin"; #endif - type = "blob-ext"; - align-end = <4>; - }; + type = "blob-ext"; + align-end = <4>; + }; + + ddr-1d-dmem-fw { +#ifdef CONFIG_IMX8M_LPDDR4 + filename = "lpddr4_pmu_train_1d_dmem.bin"; +#elif CONFIG_IMX8M_DDR4 + filename = "ddr4_dmem_1d_201810.bin"; +#else + filename = "ddr3_dmem_1d.bin"; +#endif + type = "blob-ext"; + align-end = <4>; + }; #if defined(CONFIG_IMX8M_LPDDR4) || defined(CONFIG_IMX8M_DDR4) - ddr-2d-imem-fw { + ddr-2d-imem-fw { #ifdef CONFIG_IMX8M_LPDDR4 - filename = "lpddr4_pmu_train_2d_imem.bin"; + filename = "lpddr4_pmu_train_2d_imem.bin"; #else - filename = "ddr4_imem_2d_201810.bin"; + filename = "ddr4_imem_2d_201810.bin"; #endif - type = "blob-ext"; - align-end = <4>; - }; + type = "blob-ext"; + align-end = <4>; + }; - ddr-2d-dmem-fw { + ddr-2d-dmem-fw { #ifdef CONFIG_IMX8M_LPDDR4 - filename = "lpddr4_pmu_train_2d_dmem.bin"; + filename = "lpddr4_pmu_train_2d_dmem.bin"; #else - filename = "ddr4_dmem_2d_201810.bin"; + filename = "ddr4_dmem_2d_201810.bin"; +#endif + type = "blob-ext"; + align-end = <4>; + }; #endif - type = "blob-ext"; - align-end = <4>; }; -#endif }; + +#ifdef CONFIG_IMX_HAB }; - binman_imx_fit: fit { - description = "Configuration to load ATF before U-Boot"; -#ifndef CONFIG_IMX_HAB - fit,external-offset = ; -#endif - fit,fdt-list = "of-list"; - #address-cells = <1>; + nxp-imx8mcst@1 { + filename = "u-boot-fit.signed.bin"; + nxp,loader-address = ; #ifdef CONFIG_FSPI_CONF_HEADER offset = <0x59000>; #else offset = <0x58000>; #endif - - images { - uboot { - arch = "arm64"; - compression = "none"; - description = "U-Boot (64-bit)"; - load = ; - type = "standalone"; - - uboot-blob { - filename = "u-boot-nodtb.bin"; - type = "blob-ext"; - }; - }; - -#ifndef CONFIG_ARMV8_PSCI - atf { - arch = "arm64"; - compression = "none"; - description = "ARM Trusted Firmware"; - entry = <0x960000>; - load = <0x960000>; - type = "firmware"; - - atf-blob { - filename = "bl31.bin"; - type = "atf-bl31"; - }; - }; + args; /* Needed by mkimage etype superclass */ #endif - binman_fip: fip { - arch = "arm64"; - compression = "none"; - description = "Trusted Firmware FIP"; - load = <0x40310000>; - type = "firmware"; + binman_imx_fit: fit { + description = "Configuration to load ATF before U-Boot"; +#ifndef CONFIG_IMX_HAB + fit,external-offset = ; +#endif + fit,fdt-list = "of-list"; + #address-cells = <1>; +#ifdef CONFIG_FSPI_CONF_HEADER + offset = <0x59000>; +#else + offset = <0x58000>; +#endif + + images { + uboot { + arch = "arm64"; + compression = "none"; + description = "U-Boot (64-bit)"; + load = ; + type = "standalone"; + + uboot-blob { + filename = "u-boot-nodtb.bin"; + type = "blob-ext"; + }; + }; + +#ifndef CONFIG_ARMV8_PSCI + atf { + arch = "arm64"; + compression = "none"; + description = "ARM Trusted Firmware"; + entry = <0x960000>; + load = <0x960000>; + type = "firmware"; + + atf-blob { + filename = "bl31.bin"; + type = "atf-bl31"; + }; + }; +#endif + + binman_fip: fip { + arch = "arm64"; + compression = "none"; + description = "Trusted Firmware FIP"; + load = <0x40310000>; + type = "firmware"; + }; + + @fdt-SEQ { + compression = "none"; + description = "NAME"; + type = "flat_dt"; + + uboot-fdt-blob { + filename = "u-boot.dtb"; + type = "blob-ext"; + }; + }; }; - @fdt-SEQ { - compression = "none"; - description = "NAME"; - type = "flat_dt"; + configurations { + default = "@config-DEFAULT-SEQ"; - uboot-fdt-blob { - filename = "u-boot.dtb"; - type = "blob-ext"; + @config-SEQ { + description = "NAME"; + fdt = "fdt-SEQ"; + firmware = "uboot"; +#ifndef CONFIG_ARMV8_PSCI + loadables = "atf"; +#endif }; }; }; - - configurations { - default = "@config-DEFAULT-SEQ"; - - @config-SEQ { - description = "NAME"; - fdt = "fdt-SEQ"; - firmware = "uboot"; -#ifndef CONFIG_ARMV8_PSCI - loadables = "atf"; -#endif - }; - }; +#ifdef CONFIG_IMX_HAB }; +#endif }; }; diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index 8b5ac3faf1c..f2655a4d0c8 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -86,110 +86,130 @@ section { pad-byte = <0x00>; - binman_imx_spl: nxp-imx8mimage { - filename = "u-boot-spl-mkimage.bin"; - nxp,boot-from = "sd"; - nxp,rom-version = <2>; +#ifdef CONFIG_IMX_HAB + nxp-imx8mcst@0 { + filename = "u-boot-spl-mkimage.signed.bin"; nxp,loader-address = ; + nxp,unlock; args; /* Needed by mkimage etype superclass */ +#endif - section { - filename = "u-boot-spl-ddr.bin"; - pad-byte = <0xff>; - align-size = <4>; - align = <4>; + binman_imx_spl: nxp-imx8mimage { + filename = "u-boot-spl-mkimage.bin"; + nxp,boot-from = "sd"; + nxp,rom-version = <2>; + nxp,loader-address = ; + args; /* Needed by mkimage etype superclass */ - u-boot-spl { - align-end = <4>; - }; + section { + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + align-size = <4>; + align = <4>; - ddr-1d-imem-fw { - filename = "lpddr4_pmu_train_1d_imem_202006.bin"; - type = "blob-ext"; - align-end = <4>; - }; + u-boot-spl { + align-end = <4>; + }; - ddr-1d-dmem-fw { - filename = "lpddr4_pmu_train_1d_dmem_202006.bin"; - type = "blob-ext"; - align-end = <4>; - }; + ddr-1d-imem-fw { + filename = "lpddr4_pmu_train_1d_imem_202006.bin"; + type = "blob-ext"; + align-end = <4>; + }; - ddr-2d-imem-fw { - filename = "lpddr4_pmu_train_2d_imem_202006.bin"; - type = "blob-ext"; - align-end = <4>; - }; + ddr-1d-dmem-fw { + filename = "lpddr4_pmu_train_1d_dmem_202006.bin"; + type = "blob-ext"; + align-end = <4>; + }; - ddr-2d-dmem-fw { - filename = "lpddr4_pmu_train_2d_dmem_202006.bin"; - type = "blob-ext"; - align-end = <4>; + ddr-2d-imem-fw { + filename = "lpddr4_pmu_train_2d_imem_202006.bin"; + type = "blob-ext"; + align-end = <4>; + }; + + ddr-2d-dmem-fw { + filename = "lpddr4_pmu_train_2d_dmem_202006.bin"; + type = "blob-ext"; + align-end = <4>; + }; }; }; +#ifdef CONFIG_IMX_HAB }; - binman_imx_fit: fit { - description = "Configuration to load ATF before U-Boot"; -#ifndef CONFIG_IMX_HAB - fit,external-offset = ; -#endif - fit,fdt-list = "of-list"; - #address-cells = <1>; + nxp-imx8mcst@1 { + filename = "u-boot-fit.signed.bin"; + nxp,loader-address = ; offset = <0x58000>; - - images { - uboot { - description = "U-Boot (64-bit)"; - type = "standalone"; - arch = "arm64"; - compression = "none"; - load = ; - - uboot_blob: blob-ext { - filename = "u-boot-nodtb.bin"; - }; - }; - -#ifndef CONFIG_ARMV8_PSCI - atf { - description = "ARM Trusted Firmware"; - type = "firmware"; - arch = "arm64"; - compression = "none"; - load = <0x970000>; - entry = <0x970000>; - - atf_blob: atf-blob { - filename = "bl31.bin"; - type = "atf-bl31"; - }; - }; + args; /* Needed by mkimage etype superclass */ #endif - @fdt-SEQ { - description = "NAME"; - type = "flat_dt"; - compression = "none"; + binman_imx_fit: fit { + description = "Configuration to load ATF before U-Boot"; +#ifndef CONFIG_IMX_HAB + fit,external-offset = ; +#endif + fit,fdt-list = "of-list"; + #address-cells = <1>; + offset = <0x58000>; - blob-ext { - filename = "u-boot.dtb"; + images { + uboot { + description = "U-Boot (64-bit)"; + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = ; + + uboot_blob: blob-ext { + filename = "u-boot-nodtb.bin"; + }; + }; + +#ifndef CONFIG_ARMV8_PSCI + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <0x970000>; + entry = <0x970000>; + + atf_blob: atf-blob { + filename = "bl31.bin"; + type = "atf-bl31"; + }; + }; +#endif + + @fdt-SEQ { + description = "NAME"; + type = "flat_dt"; + compression = "none"; + + blob-ext { + filename = "u-boot.dtb"; + }; + }; + }; + + configurations { + default = "@config-DEFAULT-SEQ"; + + @config-SEQ { + description = "NAME"; + fdt = "fdt-SEQ"; + firmware = "uboot"; +#ifndef CONFIG_ARMV8_PSCI + loadables = "atf"; +#endif }; }; }; - - configurations { - default = "@config-DEFAULT-SEQ"; - - @config-SEQ { - description = "NAME"; - fdt = "fdt-SEQ"; - firmware = "uboot"; -#ifndef CONFIG_ARMV8_PSCI - loadables = "atf"; -#endif - }; - }; +#ifdef CONFIG_IMX_HAB }; +#endif }; }; diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi index 72da674d245..e1cd6f8996d 100644 --- a/arch/arm/dts/imx8mq-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-u-boot.dtsi @@ -38,116 +38,136 @@ section { pad-byte = <0x00>; - binman_imx_spl: nxp-imx8mimage { - filename = "u-boot-spl-mkimage.bin"; - nxp,boot-from = "sd"; - nxp,rom-version = <1>; +#ifdef CONFIG_IMX_HAB + nxp-imx8mcst@0 { + filename = "u-boot-spl-mkimage.signed.bin"; nxp,loader-address = ; + nxp,unlock; args; /* Needed by mkimage etype superclass */ +#endif - section { - align = <4>; - align-size = <4>; - filename = "u-boot-spl-ddr.bin"; - pad-byte = <0xff>; + binman_imx_spl: nxp-imx8mimage { + filename = "u-boot-spl-mkimage.bin"; + nxp,boot-from = "sd"; + nxp,rom-version = <1>; + nxp,loader-address = ; + args; /* Needed by mkimage etype superclass */ - u-boot-spl { - align-end = <4>; - filename = "u-boot-spl.bin"; - }; + section { + align = <4>; + align-size = <4>; + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; - ddr-1d-imem-fw { - filename = "lpddr4_pmu_train_1d_imem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + u-boot-spl { + align-end = <4>; + filename = "u-boot-spl.bin"; + }; - ddr-1d-dmem-fw { - filename = "lpddr4_pmu_train_1d_dmem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + ddr-1d-imem-fw { + filename = "lpddr4_pmu_train_1d_imem.bin"; + align-end = <4>; + type = "blob-ext"; + }; - ddr-2d-imem-fw { - filename = "lpddr4_pmu_train_2d_imem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + ddr-1d-dmem-fw { + filename = "lpddr4_pmu_train_1d_dmem.bin"; + align-end = <4>; + type = "blob-ext"; + }; - ddr-2d-dmem-fw { - filename = "lpddr4_pmu_train_2d_dmem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + ddr-2d-imem-fw { + filename = "lpddr4_pmu_train_2d_imem.bin"; + align-end = <4>; + type = "blob-ext"; + }; - signed-hdmi-imx8m { - filename = "signed_hdmi_imx8m.bin"; - type = "blob-ext"; + ddr-2d-dmem-fw { + filename = "lpddr4_pmu_train_2d_dmem.bin"; + align-end = <4>; + type = "blob-ext"; + }; + + signed-hdmi-imx8m { + filename = "signed_hdmi_imx8m.bin"; + type = "blob-ext"; + }; }; }; +#ifdef CONFIG_IMX_HAB }; - binman_imx_fit: fit { - description = "Configuration to load ATF before U-Boot"; + nxp-imx8mcst@1 { + filename = "u-boot-fit.signed.bin"; + nxp,loader-address = ; + offset = <0x58000>; + args; /* Needed by mkimage etype superclass */ +#endif + + binman_imx_fit: fit { + description = "Configuration to load ATF before U-Boot"; #ifndef CONFIG_IMX_HAB - fit,external-offset = ; + fit,external-offset = ; #endif - #address-cells = <1>; + #address-cells = <1>; - images { - uboot { - arch = "arm64"; - compression = "none"; - description = "U-Boot (64-bit)"; - load = ; - type = "standalone"; + images { + uboot { + arch = "arm64"; + compression = "none"; + description = "U-Boot (64-bit)"; + load = ; + type = "standalone"; - uboot-blob { - filename = "u-boot-nodtb.bin"; - type = "blob-ext"; + uboot-blob { + filename = "u-boot-nodtb.bin"; + type = "blob-ext"; + }; }; - }; #ifndef CONFIG_ARMV8_PSCI - atf { - arch = "arm64"; - compression = "none"; - description = "ARM Trusted Firmware"; - entry = <0x910000>; - load = <0x910000>; - type = "firmware"; + atf { + arch = "arm64"; + compression = "none"; + description = "ARM Trusted Firmware"; + entry = <0x910000>; + load = <0x910000>; + type = "firmware"; - atf-blob { - filename = "bl31.bin"; - type = "blob-ext"; + atf-blob { + filename = "bl31.bin"; + type = "blob-ext"; + }; }; - }; #endif - fdt { - compression = "none"; - description = "NAME"; - type = "flat_dt"; + fdt { + compression = "none"; + description = "NAME"; + type = "flat_dt"; - uboot-fdt-blob { - filename = "u-boot.dtb"; - type = "blob-ext"; + uboot-fdt-blob { + filename = "u-boot.dtb"; + type = "blob-ext"; + }; + }; + }; + + configurations { + default = "conf"; + + conf { + description = "NAME"; + fdt = "fdt"; + firmware = "uboot"; +#ifndef CONFIG_ARMV8_PSCI + loadables = "atf"; +#endif }; }; }; - - configurations { - default = "conf"; - - conf { - description = "NAME"; - fdt = "fdt"; - firmware = "uboot"; -#ifndef CONFIG_ARMV8_PSCI - loadables = "atf"; -#endif - }; - }; +#ifdef CONFIG_IMX_HAB }; +#endif }; }; From 52dc74feab49f5f0641b9662a06fe98a66a5c437 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 21 May 2024 12:48:26 +0200 Subject: [PATCH 047/383] imx: hab: Use nxp_imx8mcst etype for i.MX8M flash.bin signing Update documentation and use nxp_imx8mcst binman etype for signing of flash.bin instead of previous horrible shell scripting. Reviewed-by: Tim Harvey Signed-off-by: Marek Vasut --- doc/imx/habv4/csf_examples/mx8m/csf.sh | 92 ---------------- doc/imx/habv4/csf_examples/mx8m/csf_fit.txt | 30 ----- doc/imx/habv4/csf_examples/mx8m/csf_spl.txt | 33 ------ doc/imx/habv4/guides/mx8m_spl_secure_boot.txt | 104 +++++------------- 4 files changed, 29 insertions(+), 230 deletions(-) delete mode 100644 doc/imx/habv4/csf_examples/mx8m/csf.sh delete mode 100644 doc/imx/habv4/csf_examples/mx8m/csf_fit.txt delete mode 100644 doc/imx/habv4/csf_examples/mx8m/csf_spl.txt diff --git a/doc/imx/habv4/csf_examples/mx8m/csf.sh b/doc/imx/habv4/csf_examples/mx8m/csf.sh deleted file mode 100644 index cd3b2614a2f..00000000000 --- a/doc/imx/habv4/csf_examples/mx8m/csf.sh +++ /dev/null @@ -1,92 +0,0 @@ -#!/bin/sh - -# 0) Generate keys -# -# WARNING: ECDSA keys are only supported by HAB 4.5 and newer (i.e. i.MX8M Plus) -# -# cd /path/to/cst-3.3.1/keys/ -# ./hab4_pki_tree.sh -existing-ca n -use-ecc n -kl 4096 -duration 10 -num-srk 4 -srk-ca y -# cd /path/to/cst-3.3.1/crts/ -# ../linux64/bin/srktool -h 4 -t SRK_1_2_3_4_table.bin -e SRK_1_2_3_4_fuse.bin -d sha256 -c ./SRK1_sha256_4096_65537_v3_ca_crt.pem,./SRK2_sha256_4096_65537_v3_ca_crt.pem,./SRK3_sha256_4096_65537_v3_ca_crt.pem,./SRK4_sha256_4096_65537_v3_ca_crt.pem -f 1 - -# 1) Build U-Boot (e.g. for i.MX8MM) -# -# cp -Lv /path/to/arm-trusted-firmware/build/imx8mm/release/bl31.bin . -# cp -Lv /path/to/firmware-imx-8.14/firmware/ddr/synopsys/ddr3* . -# make -j imx8mm_board_defconfig -# make -j`nproc` flash.bin - -# 2) Sign SPL and DRAM blobs - -cp doc/imx/habv4/csf_examples/mx8m/csf_spl.txt csf_spl.tmp -cp doc/imx/habv4/csf_examples/mx8m/csf_fit.txt csf_fit.tmp - -# update File Paths from env vars -if ! [ -r $CSF_KEY ]; then - echo "Error: \$CSF_KEY not found" - exit 1 -fi -if ! [ -r $IMG_KEY ]; then - echo "Error: \$IMG_KEY not found" - exit 1 -fi -if ! [ -r $SRK_TABLE ]; then - echo "Error: \$SRK_TABLE not found" - exit 1 -fi -sed -i "s:\$CSF_KEY:$CSF_KEY:" csf_spl.tmp -sed -i "s:\$IMG_KEY:$IMG_KEY:" csf_spl.tmp -sed -i "s:\$SRK_TABLE:$SRK_TABLE:" csf_spl.tmp -sed -i "s:\$CSF_KEY:$CSF_KEY:" csf_fit.tmp -sed -i "s:\$IMG_KEY:$IMG_KEY:" csf_fit.tmp -sed -i "s:\$SRK_TABLE:$SRK_TABLE:" csf_fit.tmp - -# update SPL Blocks -spl_block_base=$(printf "0x%x" $(( $(sed -n "/CONFIG_SPL_TEXT_BASE=/ s@.*=@@p" .config) - 0x40)) ) -spl_block_size=$(printf "0x%x" $(stat -tc %s u-boot-spl-ddr.bin)) -sed -i "/Blocks = / s@.*@ Blocks = $spl_block_base 0x0 $spl_block_size \"flash.bin\"@" csf_spl.tmp - -# Generate CSF blob -cst -i csf_spl.tmp -o csf_spl.bin - -# Patch CSF blob into flash.bin -spl_csf_offset=$(xxd -s 24 -l 4 -e flash.bin | cut -d " " -f 2 | sed "s@^@0x@") -spl_bin_offset=$(xxd -s 4 -l 4 -e flash.bin | cut -d " " -f 2 | sed "s@^@0x@") -spl_dd_offset=$((${spl_csf_offset} - ${spl_bin_offset} + 0x40)) -dd if=csf_spl.bin of=flash.bin bs=1 seek=${spl_dd_offset} conv=notrunc - -# 3) Sign u-boot.itb - -# fitImage -fit_block_base=$(printf "0x%x" $(sed -n "/CONFIG_SPL_LOAD_FIT_ADDRESS=/ s@.*=@@p" .config) ) -fit_block_offset=$(printf "0x%s" $(fdtget -t x u-boot.dtb /binman/imx-boot/uboot offset)) -fit_block_size=$(printf "0x%x" $(( ( ( $(stat -tc %s u-boot.itb) + 0x1000 - 0x1 ) & ~(0x1000 - 0x1)) + 0x20 )) ) -sed -i "/Blocks = / s@.*@ Blocks = $fit_block_base $fit_block_offset $fit_block_size \"flash.bin\"@" csf_fit.tmp - -# IVT -ivt_ptr_base=$(printf "%08x" ${fit_block_base} | sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@") -ivt_block_base=$(printf "%08x" $(( ${fit_block_base} + ${fit_block_size} - 0x20 )) | sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@") -csf_block_base=$(printf "%08x" $(( ${fit_block_base} + ${fit_block_size} )) | sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@") -ivt_block_offset=$((${fit_block_offset} + ${fit_block_size} - 0x20)) -csf_block_offset=$((${ivt_block_offset} + 0x20)) - -echo "0xd1002041 ${ivt_block_base} 0x00000000 0x00000000 0x00000000 ${ivt_block_base} ${csf_block_base} 0x00000000" | xxd -r -p > ivt.bin -dd if=ivt.bin of=flash.bin bs=1 seek=${ivt_block_offset} conv=notrunc - -# Generate CSF blob -cst -i csf_fit.tmp -o csf_fit.bin - -# When loading flash.bin via USB, we must ensure that the file being -# served is as large as the target expects (see -# board_spl_fit_size_align()), otherwise the target will hang in -# rom_api_download_image() waiting for the remaining bytes. -# -# Note that in order for dd to actually extend the file, one must not -# pass conv=notrunc here. With a non-zero seek= argument, dd is -# documented to preserve the contents of the file seeked past; in -# particular, dd does not open the file with O_TRUNC. -CSF_SIZE=$(sed -n "/CONFIG_CSF_SIZE=/ s@.*=@@p" .config) -dd if=/dev/null of=csf_fit.bin bs=1 seek=$((CSF_SIZE - 0x20)) count=0 - -# Patch CSF blob into flash.bin -dd if=csf_fit.bin of=flash.bin bs=1 seek=${csf_block_offset} conv=notrunc diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt b/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt deleted file mode 100644 index 97f3eea573b..00000000000 --- a/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt +++ /dev/null @@ -1,30 +0,0 @@ -[Header] - Version = 4.3 - Hash Algorithm = sha256 - Engine = CAAM - Engine Configuration = 0 - Certificate Format = X509 - Signature Format = CMS - -[Install SRK] - # SRK_TABLE is full path to SRK_1_2_3_4_table.bin - File = "$SRK_TABLE" - Source index = 0 - -[Install CSFK] - # CSF_KEY is full path to CSF1_1_sha256_4096_65537_v3_usr_crt.pem - File = "$CSF_KEY" - -[Authenticate CSF] - -[Install Key] - Verification index = 0 - Target Index = 2 - # IMG_KEY is full path to IMG1_1_sha256_4096_65537_v3_usr_crt.pem - File = "$IMG_KEY" - -[Authenticate Data] - Verification index = 2 - # FIXME: - # Line 1 -- fitImage - Blocks = CONFIG_SPL_LOAD_FIT_ADDRESS 0x57c00 0xffff "flash.bin" diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt b/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt deleted file mode 100644 index 88fa420a5fa..00000000000 --- a/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt +++ /dev/null @@ -1,33 +0,0 @@ -[Header] - Version = 4.3 - Hash Algorithm = sha256 - Engine = CAAM - Engine Configuration = 0 - Certificate Format = X509 - Signature Format = CMS - -[Install SRK] - # SRK_TABLE is full path to SRK_1_2_3_4_table.bin - File = "$SRK_TABLE" - Source index = 0 - -[Install CSFK] - # CSF_KEY is full path to CSF1_1_sha256_4096_65537_v3_usr_crt.pem - File = "$CSF_KEY" - -[Authenticate CSF] - -[Unlock] - Engine = CAAM - Features = MID - -[Install Key] - Verification index = 0 - Target Index = 2 - # IMG_KEY is full path to IMG1_1_sha256_4096_65537_v3_usr_crt.pem - File = "$IMG_KEY" - -[Authenticate Data] - Verification index = 2 - # FIXME: Adjust start (first column) and size (third column) here - Blocks = 0x7e0fc0 0x0 0x306f0 "flash.bin" diff --git a/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt b/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt index e16e5410bd9..257ffb45656 100644 --- a/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt +++ b/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt @@ -121,6 +121,9 @@ build configuration: - Defconfig: CONFIG_IMX_HAB=y + CONFIG_FSL_CAAM=y + CONFIG_ARCH_MISC_INIT=y + CONFIG_SPL_CRYPTO=y - Kconfig: @@ -131,91 +134,42 @@ build configuration: The CSF contains all the commands that the HAB executes during the secure boot. These commands instruct the HAB code on which memory areas of the image -to authenticate, which keys to install, use and etc. +to authenticate, which keys to install, use and etc. The CSF is generated +using the CST Code Signing Tool based on input configuration file. This tool +input configuration file is generated using binman, and the tool is invoked +from binman as well. -CSF examples are available under doc/imx/habv4/csf_examples/ directory. +The SPL and fitImage sections of the generated image are signed separately. +The signing is activated by wrapping SPL and fitImage sections into nxp-imx8mcst +etype, which is done automatically in arch/arm/dts/imx8m{m,n,p,q}-u-boot.dtsi +in case CONFIG_IMX_HAB Kconfig symbol is enabled. -CSF "Blocks" line for csf_spl.txt can be generated as follows: +Build of flash.bin target then produces a signed flash.bin automatically. -``` -spl_block_base=$(printf "0x%x" $(( $(sed -n "/CONFIG_SPL_TEXT_BASE=/ s@.*=@@p" .config) - 0x40)) ) -spl_block_size=$(printf "0x%x" $(stat -tc %s u-boot-spl-ddr.bin)) -sed -i "/Blocks = / s@.*@ Blocks = $spl_block_base 0x0 $spl_block_size \"flash.bin\"@" csf_spl.txt -``` +The nxp-imx8mcst etype is configurable using either DT properties or environment +variables. The following DT properties and environment variables are supported. +Note that environment variables override DT properties. -The resulting line looks as follows: -``` - Blocks = 0x7e0fc0 0x0 0x306f0 "flash.bin" -``` ++--------------------+-----------+------------------------------------------------------------------+ +| DT property | Variable | Description | ++====================+===========+==================================================================+ +| nxp,loader-address | | SPL base address | ++--------------------+-----------+------------------------------------------------------------------+ +| nxp,srk-table | SRK_TABLE | full path to SRK_1_2_3_4_table.bin | ++--------------------+-----------+------------------------------------------------------------------+ +| nxp,csf-crt | CSF_KEY | full path to the CSF Key CSF1_1_sha256_4096_65537_v3_usr_crt.pem | ++--------------------+-----------+------------------------------------------------------------------+ +| nxp,img-crt | IMG_KEY | full path to the IMG Key IMG1_1_sha256_4096_65537_v3_usr_crt.pem | ++--------------------+-----------+------------------------------------------------------------------+ -The columns mean: - - CONFIG_SPL_TEXT_BASE - 0x40 -- Start address of signed data, in DRAM - - 0x0 -- Start address of signed data, in "flash.bin" - - 0x306f0 -- Length of signed data, in "flash.bin" - - Filename -- "flash.bin" - -To generate signature for the SPL part of flash.bin container, use CST: -``` -cst -i csf_spl.tmp -o csf_spl.bin -``` - -The newly generated CST blob has to be patched into existing flash.bin -container. Conveniently, flash.bin IVT contains physical address of the -CSF blob. Remember, the SPL part of flash.bin container is loaded by the -BootROM at CONFIG_SPL_TEXT_BASE - 0x40 , so the offset of CSF blob in -the fitImage can be calculated and inserted into the flash.bin in the -correct location as follows: -``` -# offset = IVT_HEADER[6 = CSF address] - CONFIG_SPL_TEXT_BASE - 0x40 -spl_csf_offset=$(xxd -s 24 -l 4 -e flash.bin | cut -d " " -f 2 | sed "s@^@0x@") -spl_bin_offset=$(xxd -s 4 -l 4 -e flash.bin | cut -d " " -f 2 | sed "s@^@0x@") -spl_dd_offset=$((${spl_csf_offset} - ${spl_bin_offset} + 0x40)) -dd if=csf_spl.bin of=flash.bin bs=1 seek=${spl_dd_offset} conv=notrunc -``` - -CSF "Blocks" line for csf_fit.txt can be generated as follows: -``` -# fitImage -fit_block_base=$(printf "0x%x" $(sed -n "/CONFIG_SPL_LOAD_FIT_ADDRESS=/ s@.*=@@p" .config) ) -fit_block_offset=$(printf "0x%s" $(fdtget -t x u-boot.dtb /binman/imx-boot/uboot offset)) -fit_block_size=$(printf "0x%x" $(( ( ( $(stat -tc %s u-boot.itb) + 0x1000 - 0x1 ) & ~(0x1000 - 0x1)) + 0x20 )) ) -sed -i "/Blocks = / s@.*@ Blocks = $fit_block_base $fit_block_offset $fit_block_size \"flash.bin\"@" csf_fit.tmp -``` - -The fitImage part of flash.bin requires separate IVT. Generate the IVT and -patch it into the correct aligned location of flash.bin as follows: -``` -# IVT -ivt_ptr_base=$(printf "%08x" ${fit_block_base} | sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@") -ivt_block_base=$(printf "%08x" $(( ${fit_block_base} + ${fit_block_size} - 0x20 )) | sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@") -csf_block_base=$(printf "%08x" $(( ${fit_block_base} + ${fit_block_size} )) | sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@") -ivt_block_offset=$((${fit_block_offset} + ${fit_block_size} - 0x20)) -csf_block_offset=$((${ivt_block_offset} + 0x20)) - -echo "0xd1002041 ${ivt_block_base} 0x00000000 0x00000000 0x00000000 ${ivt_block_base} ${csf_block_base} 0x00000000" | xxd -r -p > ivt.bin -dd if=ivt.bin of=flash.bin bs=1 seek=${ivt_block_offset} conv=notrunc -``` - -To generate CSF signature for the fitImage part of flash.bin container, use CST: -``` -cst -i csf_fit.tmp -o csf_fit.bin -``` - -Finally, patch the CSF signature into the fitImage right past the IVT: -``` -dd if=csf_fit.bin of=flash.bin bs=1 seek=${csf_block_offset} conv=notrunc -``` - -The entire script is available in doc/imx/habv4/csf_examples/mx8m/csf.sh -and can be used as follows to modify flash.bin to be signed -(adjust paths as needed): +Environment variables can be set as follows to point the build process +to external key material: ``` export CST_DIR=/usr/src/cst-3.3.1/ export CSF_KEY=$CST_DIR/crts/CSF1_1_sha256_4096_65537_v3_usr_crt.pem export IMG_KEY=$CST_DIR/crts/IMG1_1_sha256_4096_65537_v3_usr_crt.pem export SRK_TABLE=$CST_DIR/crts/SRK_1_2_3_4_table.bin -export PATH=$CST_DIR/linux64/bin:$PATH -/bin/sh doc/imx/habv4/csf_examples/mx8m/csf.sh +make flash.bin ``` 1.4 Closing the device From 198b3ce737fab0f53e4e4e11f80a6634ec068b11 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 13 May 2024 05:28:06 +0200 Subject: [PATCH 048/383] ARM: imx: Add doc/imx/ to i.MX MAINTAINERS entry Make sure i.MX maintainers are CCed on doc/imx/ patches. Signed-off-by: Marek Vasut Reviewed-by: Fabio Estevam --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 6d021763a62..8e7a8ddaddf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -306,6 +306,7 @@ F: arch/arm/include/asm/mach-imx/ F: board/freescale/*mx*/ F: board/freescale/common/ F: common/spl/spl_imx_container.c +F: doc/imx/ F: drivers/serial/serial_mxc.c F: include/imx_container.h From 146d353b7303a059961fb501eaecc92916577e3d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 21 May 2024 11:39:38 +0200 Subject: [PATCH 049/383] ARM: imx: Increase PHY auto-negotiation timeout to 20s on MX8Menlo The ethernet PHY on MX8Menlo board takes a while to come out of reset, increase the auto-negotiation timeout to prevent it from timing out in case the ethernet is used right after the board was reset. Signed-off-by: Marek Vasut --- include/configs/imx8mm-mx8menlo.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/imx8mm-mx8menlo.h b/include/configs/imx8mm-mx8menlo.h index a86bd76a3c7..5cc60af91e5 100644 --- a/include/configs/imx8mm-mx8menlo.h +++ b/include/configs/imx8mm-mx8menlo.h @@ -8,6 +8,9 @@ #include +/* PHY needs a longer autoneg timeout */ +#define PHY_ANEG_TIMEOUT 20000 + /* Custom initial environment variables */ #undef CFG_EXTRA_ENV_SETTINGS #define CFG_EXTRA_ENV_SETTINGS \ From a1136831cb7c2790ff13a3e5f1c0239715b96467 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 21 May 2024 11:40:45 +0200 Subject: [PATCH 050/383] ARM: dts: imx8mm: Update iMX8MM Menlo board configuration Synchronize Toradex Verdin iMX8MM based MX8Menlo board configuration with Toradex Verdin iMX8MM and enable convenience commands like cat, hexdump, xxd. Signed-off-by: Marek Vasut Reviewed-by: Peng Fan --- configs/imx8mm-mx8menlo_defconfig | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig index e9b18ac1be7..68b24ce3fb0 100644 --- a/configs/imx8mm-mx8menlo_defconfig +++ b/configs/imx8mm-mx8menlo_defconfig @@ -25,15 +25,19 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL=y CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_ENV_OFFSET_REDUND=0xFFFFDE00 +CONFIG_IMX_BOOTAUX=y CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_SYS_MEMTEST_START=0x40000000 CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTDELAY=1 CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTCOMMAND="mmc partconf 0 distro_bootpart && load ${devtype} ${devnum}:${distro_bootpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset" +CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="imx8mm-mx8menlo.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2081 @@ -57,19 +61,26 @@ CONFIG_SYS_PROMPT="Verdin iMX8MM # " # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_ASKENV=y # CONFIG_CMD_EXPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MD5SUM=y +CONFIG_MD5SUM_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_READ=y CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CAT=y +CONFIG_CMD_XXD=y CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y CONFIG_CMD_UUID=y +CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_BTRFS=y CONFIG_CMD_EXT4_WRITE=y @@ -84,8 +95,9 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FEC" +CONFIG_ETHPRIME="eth0" CONFIG_VERSION_VARIABLE=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_SPL_DM=y @@ -96,16 +108,26 @@ CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MM=y CONFIG_CLK_IMX8MM=y CONFIG_GPIO_HOG=y +CONFIG_SPL_GPIO_HOG=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_SPL_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_PHY_FIXED=y +CONFIG_DM_MDIO=y CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_SPL_PHY=y @@ -128,6 +150,7 @@ CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y CONFIG_USB_EHCI_HCD=y @@ -143,3 +166,4 @@ CONFIG_SDP_LOADADDR=0x40400000 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_IMX_WATCHDOG=y +CONFIG_HEXDUMP=y From 4095df4634b4791d83cf86ad94e43b83057830f4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 21 May 2024 11:42:06 +0200 Subject: [PATCH 051/383] ARM: imx: mx5: Enable BMODE command on MX53 Menlo board The board can do primary/secondary boot switching, enable the bmode command. Signed-off-by: Marek Vasut Reviewed-by: Peng Fan --- configs/m53menlo_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index 0ebda79f65c..67805b14fa0 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -22,6 +22,7 @@ CONFIG_SPL=y CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_ENV_OFFSET_REDUND=0x180000 CONFIG_SYS_LOAD_ADDR=0x70800000 +CONFIG_CMD_BMODE=y CONFIG_FIT=y CONFIG_BOOTDELAY=1 CONFIG_OF_BOARD_SETUP=y From 5838b3f751bd28319f8c016f7537a88842e548a6 Mon Sep 17 00:00:00 2001 From: Olaf Mandel Date: Tue, 21 May 2024 12:49:38 +0200 Subject: [PATCH 052/383] ARM: imx: mx5: Simplify TFTP server layout on MX53 Menlo board By removing the "boot" directory in the "m53menlo/boot/fitImage" path, we simplify the TFTP server directory layout a bit. This also requires a change to the mmcload command as it (mis-)uses the same variable as the TFTP boot. Signed-off-by: Olaf Mandel Signed-off-by: Marek Vasut --- configs/m53menlo_defconfig | 2 +- include/configs/m53menlo.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index 67805b14fa0..db3a5b9f206 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -72,7 +72,7 @@ CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="boot/fitImage" +CONFIG_BOOTFILE="fitImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC0" CONFIG_USE_HOSTNAME=y diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 1ecbba1b58f..9cf46b2c362 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -119,7 +119,7 @@ "addargs=run addcons addmisc addmtd\0" \ "mmcload=" \ "mmc rescan || reset ; load mmc ${mmcdev}:${mmcpart} " \ - "${kernel_addr_r} ${bootfile} || reset\0" \ + "${kernel_addr_r} boot/${bootfile} || reset\0" \ "miscargs=nohlt panic=1\0" \ "mmcargs=setenv bootargs root=/dev/mmcblk0p${mmcpart} rw " \ "rootwait\0" \ From 7457dc6f183303aaf2d58fff0a622e6791aba33c Mon Sep 17 00:00:00 2001 From: Claudius Heine Date: Thu, 16 May 2024 10:36:14 +0200 Subject: [PATCH 053/383] imx: hab: add documentation about the required keys/certs For CST to find the certificates and keys for signing, some keys and certs need to be copied into the u-boot build directory. Signed-off-by: Claudius Heine --- doc/imx/habv4/guides/mx8m_spl_secure_boot.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt b/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt index 257ffb45656..1bea091344d 100644 --- a/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt +++ b/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt @@ -144,6 +144,23 @@ The signing is activated by wrapping SPL and fitImage sections into nxp-imx8mcst etype, which is done automatically in arch/arm/dts/imx8m{m,n,p,q}-u-boot.dtsi in case CONFIG_IMX_HAB Kconfig symbol is enabled. +Per default the HAB keys and certificates need to be located in the build +directory, this means creating a symbolic link or copying the following files +from the HAB keys directory flat (e.g. removing the `keys` and `cert` +subdirectory) into the u-boot build directory for the CST Code Signing Tool to +locate them: + +- `crts/SRK_1_2_3_4_table.bin` +- `crts/CSF1_1_sha256_4096_65537_v3_usr_crt.pem` +- `keys/CSF1_1_sha256_4096_65537_v3_usr_key.pem` +- `crts/IMG1_1_sha256_4096_65537_v3_usr_crt.pem` +- `keys/IMG1_1_sha256_4096_65537_v3_usr_key.pem` +- `keys/key_pass.txt` + +The paths to the SRK table and the certificates can be modified via changes to +the nxp_imx8mcst device tree node(s), however the other files are required by +the CST tools as well, and will be searched for in relation to them. + Build of flash.bin target then produces a signed flash.bin automatically. The nxp-imx8mcst etype is configurable using either DT properties or environment From f4cac999821764de726978549406614b6726c8fa Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Fri, 22 Mar 2024 16:27:14 +0530 Subject: [PATCH 054/383] configs: fwu: remove FWU configs for metadata V2 support Support is to be added in the following commits for the FWU metadata version 2. Disable the FWU feature on platforms that enable it for the V2 addition work. Signed-off-by: Sughosh Ganu Reviewed-by: Ilias Apalodimas Tested-by: Michal Simek --- configs/corstone1000_defconfig | 2 -- configs/sandbox64_defconfig | 1 - configs/synquacer_developerbox_defconfig | 4 ---- 3 files changed, 7 deletions(-) diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig index 8b2f77f6485..29d7550afb6 100644 --- a/configs/corstone1000_defconfig +++ b/configs/corstone1000_defconfig @@ -24,7 +24,6 @@ CONFIG_LOGLEVEL=7 CONFIG_BOARD_LATE_INIT=y CONFIG_SYS_PROMPT="corstone1000# " # CONFIG_CMD_CONSOLE is not set -CONFIG_CMD_FWU_METADATA=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_XIMG is not set CONFIG_CMD_GPT=y @@ -67,4 +66,3 @@ CONFIG_FFA_SHARED_MM_BUF_OFFSET=0 CONFIG_FFA_SHARED_MM_BUF_ADDR=0x02000000 CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_IGNORE_OSINDICATIONS=y -CONFIG_FWU_MULTI_BANK_UPDATE=y diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 3be9a00a857..7e8200e70cb 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -272,7 +272,6 @@ CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_EFI_SECURE_BOOT=y CONFIG_TEST_FDTDEC=y -CONFIG_FWU_MULTI_BANK_UPDATE=y CONFIG_UNIT_TEST=y CONFIG_UT_TIME=y CONFIG_UT_DM=y diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig index 2a0407de407..616d4100744 100644 --- a/configs/synquacer_developerbox_defconfig +++ b/configs/synquacer_developerbox_defconfig @@ -11,14 +11,12 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="synquacer-sc2a11-developerbox" CONFIG_SYS_LOAD_ADDR=0x80000000 CONFIG_TARGET_DEVELOPERBOX=y -CONFIG_FWU_NUM_IMAGES_PER_BANK=1 CONFIG_AHCI=y CONFIG_FIT=y CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_BOOTSTAGE_STASH_SIZE=4096 CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=128 -CONFIG_CMD_FWU_METADATA=y CONFIG_CMD_IMLS=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_NVEDIT_EFI=y @@ -53,7 +51,6 @@ CONFIG_DFU_TFTP=y CONFIG_DFU_MTD=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y -CONFIG_FWU_MDATA_MTD=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_SYNQUACER=y CONFIG_MMC_SDHCI=y @@ -96,4 +93,3 @@ CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_IGNORE_OSINDICATIONS=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y -CONFIG_FWU_MULTI_BANK_UPDATE=y From d99127a69ebf65cd35c33896ea6f4b45b77b8c82 Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Fri, 22 Mar 2024 16:27:15 +0530 Subject: [PATCH 055/383] tools: mkfwumdata: fix the size parameter to the fwrite call The fwrite call returns the number of bytes transferred as part of the write only when the size parameter is 1. Pass the size parameter to the library call as 1 so that the correct number of bytes transferred are returned. Fixes: fdd56bfd3ad ("tools: Add mkfwumdata tool for FWU metadata image") Signed-off-by: Sughosh Ganu Tested-by: Michal Simek --- tools/mkfwumdata.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/mkfwumdata.c b/tools/mkfwumdata.c index 9732a8ddc5a..b2d90ca7c94 100644 --- a/tools/mkfwumdata.c +++ b/tools/mkfwumdata.c @@ -259,7 +259,7 @@ fwu_make_mdata(size_t images, size_t banks, char *uuids[], char *output) goto done_make; } - ret = fwrite(mobj->mdata, mobj->size, 1, file); + ret = fwrite(mobj->mdata, 1, mobj->size, file); if (ret != mobj->size) ret = -errno; else From f42a61f57f69c9fac1e21cbfde3f40ebdadc518b Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Fri, 22 Mar 2024 16:27:16 +0530 Subject: [PATCH 056/383] drivers: fwu: add the size parameter to the metadata access API's In version 2 of the metadata structure, the size of the structure cannot be determined statically at build time. The structure is now broken into the top level structure which contains a field indicating the total size of the structure. Add a size parameter to the metadata access API functions to indicate the number of bytes to be accessed. This is then used to either read the entire structure, or only the top level structure. Signed-off-by: Sughosh Ganu Tested-by: Michal Simek --- drivers/fwu-mdata/fwu-mdata-uclass.c | 10 ++++++---- drivers/fwu-mdata/gpt_blk.c | 23 +++++++++++++---------- drivers/fwu-mdata/raw_mtd.c | 10 ++++++---- include/fwu.h | 14 ++++++++++---- 4 files changed, 35 insertions(+), 22 deletions(-) diff --git a/drivers/fwu-mdata/fwu-mdata-uclass.c b/drivers/fwu-mdata/fwu-mdata-uclass.c index 0a8edaaa418..145479bab0f 100644 --- a/drivers/fwu-mdata/fwu-mdata-uclass.c +++ b/drivers/fwu-mdata/fwu-mdata-uclass.c @@ -20,7 +20,8 @@ * * Return: 0 if OK, -ve on error */ -int fwu_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary) +int fwu_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary, + uint32_t size) { const struct fwu_mdata_ops *ops = device_get_ops(dev); @@ -29,7 +30,7 @@ int fwu_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary) return -ENOSYS; } - return ops->read_mdata(dev, mdata, primary); + return ops->read_mdata(dev, mdata, primary, size); } /** @@ -37,7 +38,8 @@ int fwu_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary) * * Return: 0 if OK, -ve on error */ -int fwu_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary) +int fwu_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary, + uint32_t size) { const struct fwu_mdata_ops *ops = device_get_ops(dev); @@ -46,7 +48,7 @@ int fwu_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary) return -ENOSYS; } - return ops->write_mdata(dev, mdata, primary); + return ops->write_mdata(dev, mdata, primary, size); } UCLASS_DRIVER(fwu_mdata) = { diff --git a/drivers/fwu-mdata/gpt_blk.c b/drivers/fwu-mdata/gpt_blk.c index c7284916c4e..97eac3611f7 100644 --- a/drivers/fwu-mdata/gpt_blk.c +++ b/drivers/fwu-mdata/gpt_blk.c @@ -81,15 +81,14 @@ static int gpt_get_mdata_disk_part(struct blk_desc *desc, return -ENOENT; } -static int gpt_read_write_mdata(struct blk_desc *desc, - struct fwu_mdata *mdata, - u8 access, u32 part_num) +static int gpt_read_write_mdata(struct blk_desc *desc, struct fwu_mdata *mdata, + u8 access, u32 part_num, u32 size) { int ret; u32 len, blk_start, blkcnt; struct disk_partition info; - ALLOC_CACHE_ALIGN_BUFFER_PAD(struct fwu_mdata, mdata_aligned, 1, + ALLOC_CACHE_ALIGN_BUFFER_PAD(u8, mdata_aligned, size, desc->blksz); if (!mdata) @@ -101,7 +100,7 @@ static int gpt_read_write_mdata(struct blk_desc *desc, return -ENOENT; } - len = sizeof(*mdata); + len = size; blkcnt = BLOCK_CNT(len, desc); if (blkcnt > info.size) { log_debug("Block count exceeds FWU metadata partition size\n"); @@ -114,7 +113,7 @@ static int gpt_read_write_mdata(struct blk_desc *desc, log_debug("Error reading FWU metadata from the device\n"); return -EIO; } - memcpy(mdata, mdata_aligned, sizeof(struct fwu_mdata)); + memcpy(mdata, mdata_aligned, size); } else { if (blk_dwrite(desc, blk_start, blkcnt, mdata) != blkcnt) { log_debug("Error writing FWU metadata to the device\n"); @@ -164,7 +163,7 @@ static int fwu_mdata_gpt_blk_probe(struct udevice *dev) } static int fwu_gpt_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, - bool primary) + bool primary, u32 size) { struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev); struct blk_desc *desc = dev_get_uclass_plat(priv->blk_dev); @@ -177,11 +176,13 @@ static int fwu_gpt_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, } return gpt_read_write_mdata(desc, mdata, MDATA_READ, - primary ? g_mdata_part[0] : g_mdata_part[1]); + primary ? + g_mdata_part[0] : g_mdata_part[1], + size); } static int fwu_gpt_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, - bool primary) + bool primary, u32 size) { struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev); struct blk_desc *desc = dev_get_uclass_plat(priv->blk_dev); @@ -194,7 +195,9 @@ static int fwu_gpt_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, } return gpt_read_write_mdata(desc, mdata, MDATA_WRITE, - primary ? g_mdata_part[0] : g_mdata_part[1]); + primary ? + g_mdata_part[0] : g_mdata_part[1], + size); } static const struct fwu_mdata_ops fwu_gpt_blk_ops = { diff --git a/drivers/fwu-mdata/raw_mtd.c b/drivers/fwu-mdata/raw_mtd.c index 17e45179738..9f3f1dc2131 100644 --- a/drivers/fwu-mdata/raw_mtd.c +++ b/drivers/fwu-mdata/raw_mtd.c @@ -97,22 +97,24 @@ lock: return ret; } -static int fwu_mtd_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary) +static int fwu_mtd_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, + bool primary, u32 size) { struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev); struct mtd_info *mtd = mtd_priv->mtd; u32 offs = primary ? mtd_priv->pri_offset : mtd_priv->sec_offset; - return mtd_io_data(mtd, offs, sizeof(struct fwu_mdata), mdata, FWU_MTD_READ); + return mtd_io_data(mtd, offs, size, mdata, FWU_MTD_READ); } -static int fwu_mtd_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary) +static int fwu_mtd_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, + bool primary, u32 size) { struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev); struct mtd_info *mtd = mtd_priv->mtd; u32 offs = primary ? mtd_priv->pri_offset : mtd_priv->sec_offset; - return mtd_io_data(mtd, offs, sizeof(struct fwu_mdata), mdata, FWU_MTD_WRITE); + return mtd_io_data(mtd, offs, size, mdata, FWU_MTD_WRITE); } static int flash_partition_offset(struct udevice *dev, const char *part_name, fdt_addr_t *offset) diff --git a/include/fwu.h b/include/fwu.h index eb5638f4f3a..1815bd0064c 100644 --- a/include/fwu.h +++ b/include/fwu.h @@ -32,20 +32,24 @@ struct fwu_mdata_ops { * @dev: FWU metadata device * @mdata: Output FWU mdata read * @primary: If primary or secondary copy of metadata is to be read + * @size: Size in bytes of the metadata to be read * * Return: 0 if OK, -ve on error */ - int (*read_mdata)(struct udevice *dev, struct fwu_mdata *mdata, bool primary); + int (*read_mdata)(struct udevice *dev, struct fwu_mdata *mdata, + bool primary, uint32_t size); /** * write_mdata() - Write the given FWU metadata copy * @dev: FWU metadata device * @mdata: Copy of the FWU metadata to write * @primary: If primary or secondary copy of metadata is to be written + * @size: Size in bytes of the metadata to be written * * Return: 0 if OK, -ve on error */ - int (*write_mdata)(struct udevice *dev, struct fwu_mdata *mdata, bool primary); + int (*write_mdata)(struct udevice *dev, struct fwu_mdata *mdata, + bool primary, uint32_t size); }; #define FWU_MDATA_VERSION 0x1 @@ -80,12 +84,14 @@ struct fwu_mdata_ops { /** * fwu_read_mdata() - Wrapper around fwu_mdata_ops.read_mdata() */ -int fwu_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary); +int fwu_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, + bool primary, uint32_t size); /** * fwu_write_mdata() - Wrapper around fwu_mdata_ops.write_mdata() */ -int fwu_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary); +int fwu_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, + bool primary, uint32_t size); /** * fwu_get_mdata() - Read, verify and return the FWU metadata From e67c0b76d8e80856cd88256ef1d6ac5da904f503 Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Fri, 22 Mar 2024 16:27:17 +0530 Subject: [PATCH 057/383] drivers: fwu: mtd: allocate buffer for image info dynamically The FWU metadata access driver for MTD partitioned devices currently uses a statically allocated array for storing the updatable image information. This array depends on the number of banks and images per bank. With migration of the FWU metadata to version 2, these parameters are now obtained at runtime from the metadata. Make changes to the FWU metadata access driver for MTD devices to allocate memory for the image information dynamically in the driver's probe function, after having obtained the number of banks and images per bank by reading the metadata. Move the image information as part of the driver's private structure, instead of using a global variable. Signed-off-by: Sughosh Ganu Tested-by: Michal Simek --- drivers/fwu-mdata/raw_mtd.c | 68 +++++++++++++++++++++++-------------- include/fwu.h | 9 +++++ 2 files changed, 52 insertions(+), 25 deletions(-) diff --git a/drivers/fwu-mdata/raw_mtd.c b/drivers/fwu-mdata/raw_mtd.c index 9f3f1dc2131..78a709f766c 100644 --- a/drivers/fwu-mdata/raw_mtd.c +++ b/drivers/fwu-mdata/raw_mtd.c @@ -12,22 +12,11 @@ #include #include -/* Internal helper structure to move data around */ -struct fwu_mdata_mtd_priv { - struct mtd_info *mtd; - char pri_label[50]; - char sec_label[50]; - u32 pri_offset; - u32 sec_offset; -}; - enum fwu_mtd_op { FWU_MTD_READ, FWU_MTD_WRITE, }; -extern struct fwu_mtd_image_info fwu_mtd_images[]; - static bool mtd_is_aligned_with_block_size(struct mtd_info *mtd, u64 size) { return !do_div(size, mtd->erasesize); @@ -134,7 +123,7 @@ static int flash_partition_offset(struct udevice *dev, const char *part_name, fd return (int)size; } -static int fwu_mdata_mtd_of_to_plat(struct udevice *dev) +static int get_fwu_mdata_dev(struct udevice *dev) { struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev); const fdt32_t *phandle_p = NULL; @@ -144,8 +133,6 @@ static int fwu_mdata_mtd_of_to_plat(struct udevice *dev) fdt_addr_t offset; int ret, size; u32 phandle; - ofnode bank; - int off_img; /* Find the FWU mdata storage device */ phandle_p = ofnode_get_property(dev_ofnode(dev), @@ -199,8 +186,28 @@ static int fwu_mdata_mtd_of_to_plat(struct udevice *dev) return ret; mtd_priv->sec_offset = offset; - off_img = 0; + return 0; +} +static int fwu_mtd_image_info_populate(struct udevice *dev, u8 nbanks, + u16 nimages) +{ + struct fwu_mtd_image_info *mtd_images; + struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev); + struct udevice *mtd_dev = mtd_priv->mtd->dev; + fdt_addr_t offset; + ofnode bank; + int off_img; + u32 total_images; + + total_images = nbanks * nimages; + mtd_priv->fwu_mtd_images = malloc(sizeof(struct fwu_mtd_image_info) * + total_images); + if (!mtd_priv->fwu_mtd_images) + return -ENOMEM; + + off_img = 0; + mtd_images = mtd_priv->fwu_mtd_images; ofnode_for_each_subnode(bank, dev_ofnode(dev)) { int bank_num, bank_offset, bank_size; const char *bank_name; @@ -219,8 +226,7 @@ static int fwu_mdata_mtd_of_to_plat(struct udevice *dev) int image_num, image_offset, image_size; const char *uuid; - if (off_img == CONFIG_FWU_NUM_BANKS * - CONFIG_FWU_NUM_IMAGES_PER_BANK) { + if (off_img == total_images) { log_err("DT provides more images than configured!\n"); break; } @@ -230,11 +236,11 @@ static int fwu_mdata_mtd_of_to_plat(struct udevice *dev) ofnode_read_u32(image, "offset", &image_offset); ofnode_read_u32(image, "size", &image_size); - fwu_mtd_images[off_img].start = bank_offset + image_offset; - fwu_mtd_images[off_img].size = image_size; - fwu_mtd_images[off_img].bank_num = bank_num; - fwu_mtd_images[off_img].image_num = image_num; - strcpy(fwu_mtd_images[off_img].uuidbuf, uuid); + mtd_images[off_img].start = bank_offset + image_offset; + mtd_images[off_img].size = image_size; + mtd_images[off_img].bank_num = bank_num; + mtd_images[off_img].image_num = image_num; + strcpy(mtd_images[off_img].uuidbuf, uuid); log_debug("\tImage%d: %s @0x%x\n\n", image_num, uuid, bank_offset + image_offset); off_img++; @@ -246,8 +252,21 @@ static int fwu_mdata_mtd_of_to_plat(struct udevice *dev) static int fwu_mdata_mtd_probe(struct udevice *dev) { - /* Ensure the metadata can be read. */ - return fwu_get_mdata(NULL); + u8 nbanks; + u16 nimages; + int ret; + + ret = get_fwu_mdata_dev(dev); + if (ret) + return ret; + + nbanks = CONFIG_FWU_NUM_BANKS; + nimages = CONFIG_FWU_NUM_IMAGES_PER_BANK; + ret = fwu_mtd_image_info_populate(dev, nbanks, nimages); + if (ret) + return ret; + + return 0; } static struct fwu_mdata_ops fwu_mtd_ops = { @@ -266,6 +285,5 @@ U_BOOT_DRIVER(fwu_mdata_mtd) = { .of_match = fwu_mdata_ids, .ops = &fwu_mtd_ops, .probe = fwu_mdata_mtd_probe, - .of_to_plat = fwu_mdata_mtd_of_to_plat, .priv_auto = sizeof(struct fwu_mdata_mtd_priv), }; diff --git a/include/fwu.h b/include/fwu.h index 1815bd0064c..6c4d218e13a 100644 --- a/include/fwu.h +++ b/include/fwu.h @@ -26,6 +26,15 @@ struct fwu_mtd_image_info { char uuidbuf[UUID_STR_LEN + 1]; }; +struct fwu_mdata_mtd_priv { + struct mtd_info *mtd; + char pri_label[50]; + char sec_label[50]; + u32 pri_offset; + u32 sec_offset; + struct fwu_mtd_image_info *fwu_mtd_images; +}; + struct fwu_mdata_ops { /** * read_mdata() - Populate the asked FWU metadata copy From 48d9325303d97751e47c6f8abed2cd59a0edc2a6 Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Fri, 22 Mar 2024 16:27:18 +0530 Subject: [PATCH 058/383] fwu: metadata: add support for version 2 of the structure Add support for version 2 of the FWU metadata structure. The top level structure is kept separate through a config symbol. Most of the fields, primarily used for providing information on updatable images are common across the two versions. Also change a few existing structure members used for image identification to reflect the fact that these are GUIDs, and not UUIDs. Signed-off-by: Sughosh Ganu Tested-by: Michal Simek --- include/fwu_mdata.h | 71 +++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 65 insertions(+), 6 deletions(-) diff --git a/include/fwu_mdata.h b/include/fwu_mdata.h index 56189e2f40a..d2521f39b42 100644 --- a/include/fwu_mdata.h +++ b/include/fwu_mdata.h @@ -11,7 +11,7 @@ /** * struct fwu_image_bank_info - firmware image information - * @image_uuid: Guid value of the image in this bank + * @image_guid: Guid value of the image in this bank * @accepted: Acceptance status of the image * @reserved: Reserved * @@ -20,15 +20,15 @@ * acceptance status */ struct fwu_image_bank_info { - efi_guid_t image_uuid; + efi_guid_t image_guid; uint32_t accepted; uint32_t reserved; } __packed; /** * struct fwu_image_entry - information for a particular type of image - * @image_type_uuid: Guid value for identifying the image type - * @location_uuid: Guid of the storage volume where the image is located + * @image_type_guid: Guid value for identifying the image type + * @location_guid: Guid of the storage volume where the image is located * @img_bank_info: Array containing properties of images * * This structure contains information on various types of updatable @@ -36,11 +36,35 @@ struct fwu_image_bank_info { * information per bank. */ struct fwu_image_entry { - efi_guid_t image_type_uuid; - efi_guid_t location_uuid; + efi_guid_t image_type_guid; + efi_guid_t location_guid; struct fwu_image_bank_info img_bank_info[CONFIG_FWU_NUM_BANKS]; } __packed; +/** + * struct fwu_fw_store_desc - FWU updatable image information + * @num_banks: Number of firmware banks + * @num_images: Number of images per bank + * @img_entry_size: The size of the img_entry array + * @bank_info_entry_size: The size of the img_bank_info array + * @img_entry: Array of image entries each giving information on a image + * + * This image descriptor structure contains information on the number of + * updatable banks and images per bank. It also gives the total sizes of + * the fwu_image_entry and fwu_image_bank_info arrays. This structure is + * only present in version 2 of the metadata structure. + */ +struct fwu_fw_store_desc { + uint8_t num_banks; + uint8_t reserved; + uint16_t num_images; + uint16_t img_entry_size; + uint16_t bank_info_entry_size; + + struct fwu_image_entry img_entry[CONFIG_FWU_NUM_IMAGES_PER_BANK]; +} __packed; + +#if defined(CONFIG_FWU_MDATA_V1) /** * struct fwu_mdata - FWU metadata structure for multi-bank updates * @crc32: crc32 value for the FWU metadata @@ -65,4 +89,39 @@ struct fwu_mdata { struct fwu_image_entry img_entry[CONFIG_FWU_NUM_IMAGES_PER_BANK]; } __packed; +#else /* CONFIG_FWU_MDATA_V1 */ +/** + * struct fwu_mdata - FWU metadata structure for multi-bank updates + * @crc32: crc32 value for the FWU metadata + * @version: FWU metadata version + * @active_index: Index of the bank currently used for booting images + * @previous_active_inde: Index of the bank used before the current bank + * being used for booting + * @metadata_size: Size of the entire metadata structure, including the + * image descriptors + * @desc_offset: The offset from the start of this structure where the + * image descriptor structure starts. 0 if absent + * @bank_state: State of each bank, valid, invalid or accepted + * @fw_desc: The structure describing the FWU updatable images + * + * This is the top level structure used to store all information for performing + * multi bank updates on the platform. This contains info on the bank being + * used to boot along with the information on state of individual banks. + */ +struct fwu_mdata { + uint32_t crc32; + uint32_t version; + uint32_t active_index; + uint32_t previous_active_index; + uint32_t metadata_size; + uint16_t desc_offset; + uint16_t reserved1; + uint8_t bank_state[4]; + uint32_t reserved2; + + // struct fwu_fw_store_desc fw_desc; +} __packed; + +#endif /* CONFIG_FWU_MDATA_V1 */ + #endif /* _FWU_MDATA_H_ */ From 1cafc2ab8d1e9da4d253442aa719895131c0901e Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Fri, 22 Mar 2024 16:27:19 +0530 Subject: [PATCH 059/383] fwu: metadata: add a version agnostic structure The FWU specification now has two versions of the FWU metadata structure, and both are to be supported. Introduce a version agnostic structure for storing information about the FWU updatable images. This allows for a split of common version agnostic FWU code and version specific code. The version specific code is then responsible for arranging the data as per the corresponding metadata structure before it gets written to the metadata partitions. Signed-off-by: Sughosh Ganu Tested-by: Michal Simek --- include/fwu.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/include/fwu.h b/include/fwu.h index 6c4d218e13a..e681e910274 100644 --- a/include/fwu.h +++ b/include/fwu.h @@ -8,6 +8,7 @@ #include #include +#include #include #include @@ -35,6 +36,23 @@ struct fwu_mdata_mtd_priv { struct fwu_mtd_image_info *fwu_mtd_images; }; +struct fwu_data { + uint32_t crc32; + uint32_t version; + uint32_t active_index; + uint32_t previous_active_index; + uint32_t metadata_size; + uint32_t boot_index; + uint32_t num_banks; + uint32_t num_images; + uint8_t bank_state[4]; + bool trial_state; + + struct fwu_mdata *fwu_mdata; + + struct fwu_image_entry fwu_images[CONFIG_FWU_NUM_IMAGES_PER_BANK]; +}; + struct fwu_mdata_ops { /** * read_mdata() - Populate the asked FWU metadata copy From fba5b3fa7c473fb356ce206ad2dbfe1c3917edfa Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Fri, 22 Mar 2024 16:27:20 +0530 Subject: [PATCH 060/383] fwu: metadata: add functions for handling version specific metadata fields Support is being added in U-Boot for version 2 of the FWU metadata. Support for this version is to co-exist with version 1 support. To achieve this, a common, version agnostic structure has been added to keep information provided by the FWU metadata structure. Add API's to handle the version specific FWU metadata fields. The version agnostic structure gets initialized at boot by reading the FWU metadata. Updates to the FWU metadata result in the API's getting called to populate the version specific fields of the strucure, before the metadata gets written to the storage media. Signed-off-by: Sughosh Ganu Tested-by: Michal Simek --- include/fwu.h | 57 +++++++++ lib/fwu_updates/fwu_v1.c | 167 +++++++++++++++++++++++++ lib/fwu_updates/fwu_v2.c | 260 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 484 insertions(+) create mode 100644 lib/fwu_updates/fwu_v1.c create mode 100644 lib/fwu_updates/fwu_v2.c diff --git a/include/fwu.h b/include/fwu.h index e681e910274..082b5481d1e 100644 --- a/include/fwu.h +++ b/include/fwu.h @@ -313,4 +313,61 @@ int fwu_gen_alt_info_from_mtd(char *buf, size_t len, struct mtd_info *mtd); */ int fwu_mtd_get_alt_num(efi_guid_t *image_guid, u8 *alt_num, const char *mtd_dev); +/** + * fwu_populate_mdata_image_info() - Populate the image information + * of the metadata + * @data: Version agnostic FWU metadata information + * + * Populate the image information in the FWU metadata by copying it + * from the version agnostic structure. This is done before the + * metadata gets written to the storage media. + * + * Return: None + */ +void fwu_populate_mdata_image_info(struct fwu_data *data); + +/** + * fwu_get_mdata_size() - Get the FWU metadata size + * @mdata_size: Size of the metadata structure + * + * Get the size of the FWU metadata from the structure. This is later used + * to allocate memory for the structure. + * + * Return: 0 if OK, -ve on error + */ +int fwu_get_mdata_size(uint32_t *mdata_size); + +/** + * fwu_state_machine_updates() - Update FWU state of the platform + * @trial_state: Is platform transitioning into Trial State + * @update_index: Bank number to which images have been updated + * + * On successful completion of updates, transition the platform to + * either Trial State or Regular State. + * + * To transition the platform to Trial State, start the + * TrialStateCtr counter, followed by setting the value of bank_state + * field of the metadata to Valid state(applicable only in version 2 + * of metadata). + * + * In case, the platform is to transition directly to Regular State, + * update the bank_state field of the metadata to Accepted + * state(applicable only in version 2 of metadata). + * + * Return: 0 if OK, -ve on error + */ +int fwu_state_machine_updates(bool trial_state, uint32_t update_index); + +/** + * fwu_init() - FWU specific initialisations + * + * Carry out some FWU specific initialisations including allocation + * of memory for the metadata copies, and reading the FWU metadata + * copies into the allocated memory. The metadata fields are then + * copied into a version agnostic structure. + * + * Return: 0 if OK, -ve on error + */ +int fwu_init(void); + #endif /* _FWU_H_ */ diff --git a/lib/fwu_updates/fwu_v1.c b/lib/fwu_updates/fwu_v1.c new file mode 100644 index 00000000000..efb8d515008 --- /dev/null +++ b/lib/fwu_updates/fwu_v1.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2024, Linaro Limited + */ + +#include +#include + +#include + +#define FWU_MDATA_VERSION 0x1U + +static uint32_t fwu_check_trial_state(struct fwu_mdata *mdata, uint32_t bank) +{ + u32 i; + struct fwu_image_entry *img_entry; + struct fwu_image_bank_info *img_bank_info; + + img_entry = &mdata->img_entry[0]; + for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) { + img_bank_info = &img_entry[i].img_bank_info[bank]; + if (!img_bank_info->accepted) { + return 1; + } + } + + return 0; +} + +static void fwu_data_init(void) +{ + size_t image_info_size; + void *dst_img_info, *src_img_info; + struct fwu_data *data = fwu_get_data(); + struct fwu_mdata *mdata = data->fwu_mdata; + + data->crc32 = mdata->crc32; + data->version = mdata->version; + data->active_index = mdata->active_index; + data->previous_active_index = mdata->previous_active_index; + + data->metadata_size = sizeof(struct fwu_mdata); + data->num_banks = CONFIG_FWU_NUM_BANKS; + data->num_images = CONFIG_FWU_NUM_IMAGES_PER_BANK; + fwu_plat_get_bootidx(&data->boot_index); + data->trial_state = fwu_check_trial_state(mdata, data->boot_index); + + src_img_info = &mdata->img_entry[0]; + dst_img_info = &data->fwu_images[0]; + image_info_size = sizeof(data->fwu_images); + + memcpy(dst_img_info, src_img_info, image_info_size); +} + +static int fwu_trial_state_update(bool trial_state) +{ + int ret; + struct fwu_data *data = fwu_get_data(); + + if (trial_state) { + ret = fwu_trial_state_ctr_start(); + if (ret) + return ret; + } + + data->trial_state = trial_state; + + return 0; +} + +/** + * fwu_populate_mdata_image_info() - Populate the image information + * of the metadata + * @data: Version agnostic FWU metadata information + * + * Populate the image information in the FWU metadata by copying it + * from the version agnostic structure. This is done before the + * metadata gets written to the storage media. + * + * Return: None + */ +void fwu_populate_mdata_image_info(struct fwu_data *data) +{ + size_t image_info_size; + void *dst_img_info, *src_img_info; + struct fwu_mdata *mdata = data->fwu_mdata; + + image_info_size = sizeof(data->fwu_images); + dst_img_info = &mdata->img_entry[0]; + src_img_info = &data->fwu_images[0]; + + memcpy(dst_img_info, src_img_info, image_info_size); +} + +/** + * fwu_state_machine_updates() - Update FWU state of the platform + * @trial_state: Is platform transitioning into Trial State + * @update_index: Bank number to which images have been updated + * + * On successful completion of updates, transition the platform to + * either Trial State or Regular State. + * + * To transition the platform to Trial State, start the + * TrialStateCtr counter, followed by setting the value of bank_state + * field of the metadata to Valid state(applicable only in version 2 + * of metadata). + * + * In case, the platform is to transition directly to Regular State, + * update the bank_state field of the metadata to Accepted + * state(applicable only in version 2 of metadata). + * + * Return: 0 if OK, -ve on error + */ +int fwu_state_machine_updates(bool trial_state, + __maybe_unused uint32_t update_index) +{ + return fwu_trial_state_update(trial_state); +} + +/** + * fwu_get_mdata_size() - Get the FWU metadata size + * @mdata_size: Size of the metadata structure + * + * Get the size of the FWU metadata. + * + * Return: 0 if OK, -ve on error + */ +int fwu_get_mdata_size(uint32_t *mdata_size) +{ + *mdata_size = sizeof(struct fwu_mdata); + + return 0; +} + +/** + * fwu_init() - FWU specific initialisations + * + * Carry out some FWU specific initialisations including allocation + * of memory for the metadata copies, and reading the FWU metadata + * copies into the allocated memory. The metadata fields are then + * copied into a version agnostic structure. + * + * Return: 0 if OK, -ve on error + */ +int fwu_init(void) +{ + int ret; + uint32_t mdata_size; + + fwu_get_mdata_size(&mdata_size); + + ret = fwu_mdata_copies_allocate(mdata_size); + if (ret) + return ret; + + /* + * Now read the entire structure, both copies, and + * validate that the copies. + */ + ret = fwu_get_mdata(NULL); + if (ret) + return ret; + + fwu_data_init(); + + return 0; +} diff --git a/lib/fwu_updates/fwu_v2.c b/lib/fwu_updates/fwu_v2.c new file mode 100644 index 00000000000..108bc9bb4ac --- /dev/null +++ b/lib/fwu_updates/fwu_v2.c @@ -0,0 +1,260 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2024, Linaro Limited + */ + +#include +#include +#include + +#include + +#define FWU_MDATA_VERSION 0x2U + +static inline struct fwu_fw_store_desc *fwu_get_fw_desc(struct fwu_mdata *mdata) +{ + return (struct fwu_fw_store_desc *)((u8 *)mdata + sizeof(*mdata)); +} + +static uint32_t fwu_check_trial_state(struct fwu_mdata *mdata, uint32_t bank) +{ + return mdata->bank_state[bank] == FWU_BANK_VALID ? 1 : 0; +} + +static void fwu_data_init(void) +{ + int i; + size_t image_info_size; + void *dst_img_info, *src_img_info; + struct fwu_data *data = fwu_get_data(); + struct fwu_mdata *mdata = data->fwu_mdata; + + data->crc32 = mdata->crc32; + data->version = mdata->version; + data->active_index = mdata->active_index; + data->previous_active_index = mdata->previous_active_index; + data->metadata_size = mdata->metadata_size; + fwu_plat_get_bootidx(&data->boot_index); + data->trial_state = fwu_check_trial_state(mdata, data->boot_index); + + data->num_banks = fwu_get_fw_desc(mdata)->num_banks; + data->num_images = fwu_get_fw_desc(mdata)->num_images; + + for (i = 0; i < 4; i++) { + data->bank_state[i] = mdata->bank_state[i]; + } + + image_info_size = sizeof(data->fwu_images); + src_img_info = &fwu_get_fw_desc(mdata)->img_entry[0]; + dst_img_info = &data->fwu_images[0]; + + memcpy(dst_img_info, src_img_info, image_info_size); +} + +static int fwu_mdata_sanity_checks(void) +{ + uint8_t num_banks; + uint16_t num_images; + struct fwu_data *data = fwu_get_data(); + struct fwu_mdata *mdata = data->fwu_mdata; + + if (mdata->version != FWU_MDATA_VERSION) { + log_err("FWU metadata version %u. Expected value of %u\n", + mdata->version, FWU_MDATA_VERSION); + return -EINVAL; + } + + if (!mdata->desc_offset) { + log_err("No image information provided with the Metadata. "); + log_err("Image information expected in the metadata\n"); + return -EINVAL; + } + + if (mdata->desc_offset != 0x20) { + log_err("Descriptor Offset(0x%x) in the FWU Metadata not equal to 0x20\n", + mdata->desc_offset); + return -EINVAL; + } + + num_banks = fwu_get_fw_desc(mdata)->num_banks; + num_images = fwu_get_fw_desc(mdata)->num_images; + + if (num_banks != CONFIG_FWU_NUM_BANKS) { + log_err("Number of Banks(%u) in FWU Metadata different from the configured value(%d)", + num_banks, CONFIG_FWU_NUM_BANKS); + return -EINVAL; + } + + if (num_images != CONFIG_FWU_NUM_IMAGES_PER_BANK) { + log_err("Number of Images(%u) in FWU Metadata different from the configured value(%d)", + num_images, CONFIG_FWU_NUM_IMAGES_PER_BANK); + return -EINVAL; + } + + return 0; +} + +static int fwu_bank_state_update(bool trial_state, uint32_t bank) +{ + int ret; + struct fwu_data *data = fwu_get_data(); + struct fwu_mdata *mdata = data->fwu_mdata; + + mdata->bank_state[bank] = data->bank_state[bank] = trial_state ? + FWU_BANK_VALID : FWU_BANK_ACCEPTED; + + ret = fwu_sync_mdata(mdata, BOTH_PARTS); + if (ret) + log_err("Unable to set bank_state for bank %u\n", bank); + else + data->trial_state = trial_state; + + return ret; +} + +static int fwu_trial_state_start(uint update_index) +{ + int ret; + + ret = fwu_trial_state_ctr_start(); + if (ret) + return ret; + + ret = fwu_bank_state_update(1, update_index); + if (ret) + return ret; + + return 0; +} + +/** + * fwu_populate_mdata_image_info() - Populate the image information + * of the metadata + * @data: Version agnostic FWU metadata information + * + * Populate the image information in the FWU metadata by copying it + * from the version agnostic structure. This is done before the + * metadata gets written to the storage media. + * + * Return: None + */ +void fwu_populate_mdata_image_info(struct fwu_data *data) +{ + size_t image_info_size; + struct fwu_mdata *mdata = data->fwu_mdata; + void *dst_img_info, *src_img_info; + + image_info_size = sizeof(data->fwu_images); + dst_img_info = &fwu_get_fw_desc(mdata)->img_entry[0]; + src_img_info = &data->fwu_images[0]; + + memcpy(dst_img_info, src_img_info, image_info_size); +} + +/** + * fwu_state_machine_updates() - Update FWU state of the platform + * @trial_state: Is platform transitioning into Trial State + * @update_index: Bank number to which images have been updated + * + * On successful completion of updates, transition the platform to + * either Trial State or Regular State. + * + * To transition the platform to Trial State, start the + * TrialStateCtr counter, followed by setting the value of bank_state + * field of the metadata to Valid state(applicable only in version 2 + * of metadata). + * + * In case, the platform is to transition directly to Regular State, + * update the bank_state field of the metadata to Accepted + * state(applicable only in version 2 of metadata). + * + * Return: 0 if OK, -ve on error + */ +int fwu_state_machine_updates(bool trial_state, uint32_t update_index) +{ + return trial_state ? fwu_trial_state_start(update_index) : + fwu_bank_state_update(0, update_index); +} + +/** + * fwu_get_mdata_size() - Get the FWU metadata size + * @mdata_size: Size of the metadata structure + * + * Get the size of the FWU metadata from the structure. This is later used + * to allocate memory for the structure. + * + * Return: 0 if OK, -ve on error + */ +int fwu_get_mdata_size(uint32_t *mdata_size) +{ + int ret = 0; + struct fwu_mdata mdata = { 0 }; + struct fwu_data *data = fwu_get_data(); + struct udevice *fwu_dev = fwu_get_dev(); + + if (data->metadata_size) { + *mdata_size = data->metadata_size; + return 0; + } + + ret = fwu_read_mdata(fwu_dev, &mdata, 1, + sizeof(struct fwu_mdata)); + if (ret) { + log_err("FWU metadata read failed\n"); + return ret; + } + + *mdata_size = mdata.metadata_size; + if (!*mdata_size) + return -EINVAL; + + return 0; +} + +/** + * fwu_init() - FWU specific initialisations + * + * Carry out some FWU specific initialisations including allocation + * of memory for the metadata copies, and reading the FWU metadata + * copies into the allocated memory. The metadata fields are then + * copied into a version agnostic structure. + * + * Return: 0 if OK, -ve on error + */ +int fwu_init(void) +{ + int ret; + struct fwu_mdata mdata = { 0 }; + struct udevice *fwu_dev = fwu_get_dev(); + + /* + * First we read only the top level structure + * and get the size of the complete structure. + */ + ret = fwu_read_mdata(fwu_dev, &mdata, 1, + sizeof(struct fwu_mdata)); + if (ret) { + log_err("FWU metadata read failed\n"); + return ret; + } + + ret = fwu_mdata_copies_allocate(mdata.metadata_size); + if (ret) + return ret; + + /* + * Now read the entire structure, both copies, and + * validate that the copies. + */ + ret = fwu_get_mdata(NULL); + if (ret) + return ret; + + ret = fwu_mdata_sanity_checks(); + if (ret) + return ret; + + fwu_data_init(); + + return 0; +} From ac62e0b62e02be0bb8c5f0d0dd49fa9bda91d5c5 Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Fri, 22 Mar 2024 16:27:21 +0530 Subject: [PATCH 061/383] fwu: make changes to access version agnostic structure fields With addition of support for version 2 of the FWU metadata structure, the metadata information is collected into a version agnostic structure. Make changes to the FWU functions so that the information that was earlier obtained by reading the metadata structure is now obtained through this version agnostic structure. Signed-off-by: Sughosh Ganu Tested-by: Michal Simek --- include/fwu.h | 49 +++++++++- lib/fwu_updates/fwu.c | 204 ++++++++++++++++++++++++++++-------------- 2 files changed, 186 insertions(+), 67 deletions(-) diff --git a/include/fwu.h b/include/fwu.h index 082b5481d1e..77ec65e6180 100644 --- a/include/fwu.h +++ b/include/fwu.h @@ -79,9 +79,18 @@ struct fwu_mdata_ops { bool primary, uint32_t size); }; -#define FWU_MDATA_VERSION 0x1 #define FWU_IMAGE_ACCEPTED 0x1 +#define FWU_BANK_INVALID (uint8_t)0xFF +#define FWU_BANK_VALID (uint8_t)0xFE +#define FWU_BANK_ACCEPTED (uint8_t)0xFC + +enum { + PRIMARY_PART = 1, + SECONDARY_PART, + BOTH_PARTS, +}; + /* * GUID value defined in the FWU specification for identification * of the FWU metadata partition. @@ -313,6 +322,44 @@ int fwu_gen_alt_info_from_mtd(char *buf, size_t len, struct mtd_info *mtd); */ int fwu_mtd_get_alt_num(efi_guid_t *image_guid, u8 *alt_num, const char *mtd_dev); +/** + * fwu_mdata_copies_allocate() - Allocate memory for metadata + * @mdata_size: Size of the metadata structure + * + * Allocate memory for storing both the copies of the FWU metadata. The + * copies are then used as a cache for storing FWU metadata contents. + * + * Return: 0 if OK, -ve on error + */ +int fwu_mdata_copies_allocate(u32 mdata_size); + +/** + * fwu_get_dev() - Return the FWU metadata device + * + * Return the pointer to the FWU metadata device. + * + * Return: Pointer to the FWU metadata dev + */ +struct udevice *fwu_get_dev(void); + +/** + * fwu_get_data() - Return the version agnostic FWU structure + * + * Return the pointer to the version agnostic FWU structure. + * + * Return: Pointer to the FWU data structure + */ +struct fwu_data *fwu_get_data(void); + +/** + * fwu_sync_mdata() - Update given meta-data partition(s) with the copy provided + * @data: FWU Data structure + * @part: Bitmask of FWU metadata partitions to be written to + * + * Return: 0 if OK, -ve on error + */ +int fwu_sync_mdata(struct fwu_mdata *mdata, int part); + /** * fwu_populate_mdata_image_info() - Populate the image information * of the metadata diff --git a/lib/fwu_updates/fwu.c b/lib/fwu_updates/fwu.c index 86518108c2d..5dfea2a4d8d 100644 --- a/lib/fwu_updates/fwu.c +++ b/lib/fwu_updates/fwu.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -17,7 +18,7 @@ #include -static struct fwu_mdata g_mdata; /* = {0} makes uninit crc32 always invalid */ +struct fwu_data g_fwu_data; static struct udevice *g_dev; static u8 in_trial; static u8 boottime_check; @@ -27,12 +28,6 @@ enum { IMAGE_ACCEPT_CLEAR, }; -enum { - PRIMARY_PART = 1, - SECONDARY_PART, - BOTH_PARTS, -}; - static int trial_counter_update(u16 *trial_state_ctr) { bool delete; @@ -106,23 +101,9 @@ out: return ret; } -static int in_trial_state(struct fwu_mdata *mdata) +static u32 in_trial_state(void) { - u32 i, active_bank; - struct fwu_image_entry *img_entry; - struct fwu_image_bank_info *img_bank_info; - - active_bank = mdata->active_index; - img_entry = &mdata->img_entry[0]; - for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) { - img_bank_info = &img_entry[i].img_bank_info[active_bank]; - if (!img_bank_info->accepted) { - log_info("System booting in Trial State\n"); - return 1; - } - } - - return 0; + return g_fwu_data.trial_state; } static int fwu_get_image_type_id(u8 image_index, efi_guid_t *image_type_id) @@ -141,17 +122,70 @@ static int fwu_get_image_type_id(u8 image_index, efi_guid_t *image_type_id) return -ENOENT; } +static int mdata_crc_check(struct fwu_mdata *mdata) +{ + int ret; + u32 calc_crc32; + uint32_t mdata_size; + void *buf = &mdata->version; + + ret = fwu_get_mdata_size(&mdata_size); + if (ret) + return ret; + + calc_crc32 = crc32(0, buf, mdata_size - sizeof(u32)); + return calc_crc32 == mdata->crc32 ? 0 : -EINVAL; +} + +static void fwu_data_crc_update(uint32_t crc32) +{ + g_fwu_data.crc32 = crc32; +} + +/** + * fwu_get_data() - Return the version agnostic FWU structure + * + * Return the pointer to the version agnostic FWU structure. + * + * Return: Pointer to the FWU data structure + */ +struct fwu_data *fwu_get_data(void) +{ + return &g_fwu_data; +} + +static void fwu_populate_mdata_bank_index(struct fwu_data *fwu_data) +{ + struct fwu_mdata *mdata = fwu_data->fwu_mdata; + + mdata->active_index = fwu_data->active_index; + mdata->previous_active_index = fwu_data->previous_active_index; +} + +/** + * fwu_get_dev() - Return the FWU metadata device + * + * Return the pointer to the FWU metadata device. + * + * Return: Pointer to the FWU metadata dev + */ +struct udevice *fwu_get_dev(void) +{ + return g_dev; +} + /** * fwu_sync_mdata() - Update given meta-data partition(s) with the copy provided - * @mdata: FWU metadata structure + * @data: FWU Data structure * @part: Bitmask of FWU metadata partitions to be written to * * Return: 0 if OK, -ve on error */ -static int fwu_sync_mdata(struct fwu_mdata *mdata, int part) +int fwu_sync_mdata(struct fwu_mdata *mdata, int part) { - void *buf = &mdata->version; int err; + uint mdata_size; + void *buf = &mdata->version; if (part == BOTH_PARTS) { err = fwu_sync_mdata(mdata, SECONDARY_PART); @@ -160,32 +194,53 @@ static int fwu_sync_mdata(struct fwu_mdata *mdata, int part) part = PRIMARY_PART; } + err = fwu_get_mdata_size(&mdata_size); + if (err) + return err; + /* * Calculate the crc32 for the updated FWU metadata * and put the updated value in the FWU metadata crc32 * field */ - mdata->crc32 = crc32(0, buf, sizeof(*mdata) - sizeof(u32)); + mdata->crc32 = crc32(0, buf, mdata_size - sizeof(u32)); + fwu_data_crc_update(mdata->crc32); - err = fwu_write_mdata(g_dev, mdata, part == PRIMARY_PART); + err = fwu_write_mdata(g_dev, mdata, part == PRIMARY_PART, mdata_size); if (err) { log_err("Unable to write %s mdata\n", part == PRIMARY_PART ? "primary" : "secondary"); return err; } - /* update the cached copy of meta-data */ - memcpy(&g_mdata, mdata, sizeof(struct fwu_mdata)); - return 0; } -static inline int mdata_crc_check(struct fwu_mdata *mdata) +/** + * fwu_mdata_copies_allocate() - Allocate memory for metadata + * @mdata_size: Size of the metadata structure + * + * Allocate memory for storing both the copies of the FWU metadata. The + * copies are then used as a cache for storing FWU metadata contents. + * + * Return: 0 if OK, -ve on error + */ +int fwu_mdata_copies_allocate(u32 mdata_size) { - void *buf = &mdata->version; - u32 calc_crc32 = crc32(0, buf, sizeof(*mdata) - sizeof(u32)); + if (g_fwu_data.fwu_mdata) + return 0; - return calc_crc32 == mdata->crc32 ? 0 : -EINVAL; + /* + * Allocate the total memory that would be needed for both + * the copies. + */ + g_fwu_data.fwu_mdata = calloc(2, mdata_size); + if (!g_fwu_data.fwu_mdata) { + log_err("Unable to allocate space for FWU metadata\n"); + return -ENOMEM; + } + + return 0; } /** @@ -201,21 +256,33 @@ static inline int mdata_crc_check(struct fwu_mdata *mdata) int fwu_get_mdata(struct fwu_mdata *mdata) { int err; + uint32_t mdata_size; bool parts_ok[2] = { false }; - struct fwu_mdata s, *parts_mdata[2]; + struct fwu_mdata *parts_mdata[2]; - parts_mdata[0] = &g_mdata; - parts_mdata[1] = &s; + err = fwu_get_mdata_size(&mdata_size); + if (err) + return err; + + parts_mdata[0] = g_fwu_data.fwu_mdata; + if (!parts_mdata[0]) { + log_err("Memory not allocated for the FWU Metadata copies\n"); + return -ENOMEM; + } + + parts_mdata[1] = (struct fwu_mdata *)((char *)parts_mdata[0] + + mdata_size); /* if mdata already read and ready */ err = mdata_crc_check(parts_mdata[0]); if (!err) goto ret_mdata; - /* else read, verify and, if needed, fix mdata */ + + /* else read, verify and, if needed, fix mdata */ for (int i = 0; i < 2; i++) { parts_ok[i] = false; - err = fwu_read_mdata(g_dev, parts_mdata[i], !i); + err = fwu_read_mdata(g_dev, parts_mdata[i], !i, mdata_size); if (!err) { err = mdata_crc_check(parts_mdata[i]); if (!err) @@ -230,7 +297,7 @@ int fwu_get_mdata(struct fwu_mdata *mdata) * Before returning, check that both the * FWU metadata copies are the same. */ - err = memcmp(parts_mdata[0], parts_mdata[1], sizeof(struct fwu_mdata)); + err = memcmp(parts_mdata[0], parts_mdata[1], mdata_size); if (!err) goto ret_mdata; @@ -247,7 +314,7 @@ int fwu_get_mdata(struct fwu_mdata *mdata) if (parts_ok[i]) continue; - memcpy(parts_mdata[i], parts_mdata[1 - i], sizeof(struct fwu_mdata)); + memcpy(parts_mdata[i], parts_mdata[1 - i], mdata_size); err = fwu_sync_mdata(parts_mdata[i], i ? SECONDARY_PART : PRIMARY_PART); if (err) { log_debug("mdata : %s write failed\n", i ? "secondary" : "primary"); @@ -257,7 +324,7 @@ int fwu_get_mdata(struct fwu_mdata *mdata) ret_mdata: if (!err && mdata) - memcpy(mdata, parts_mdata[0], sizeof(struct fwu_mdata)); + memcpy(mdata, parts_mdata[0], mdata_size); return err; } @@ -275,13 +342,13 @@ ret_mdata: int fwu_get_active_index(uint *active_idx) { int ret = 0; - struct fwu_mdata *mdata = &g_mdata; + struct fwu_data *data = &g_fwu_data; /* * Found the FWU metadata partition, now read the active_index * value */ - *active_idx = mdata->active_index; + *active_idx = data->active_index; if (*active_idx >= CONFIG_FWU_NUM_BANKS) { log_debug("Active index value read is incorrect\n"); ret = -EINVAL; @@ -302,7 +369,7 @@ int fwu_get_active_index(uint *active_idx) int fwu_set_active_index(uint active_idx) { int ret; - struct fwu_mdata *mdata = &g_mdata; + struct fwu_data *data = &g_fwu_data; if (active_idx >= CONFIG_FWU_NUM_BANKS) { log_debug("Invalid active index value\n"); @@ -313,14 +380,16 @@ int fwu_set_active_index(uint active_idx) * Update the active index and previous_active_index fields * in the FWU metadata */ - mdata->previous_active_index = mdata->active_index; - mdata->active_index = active_idx; + data->previous_active_index = data->active_index; + data->active_index = active_idx; + + fwu_populate_mdata_bank_index(data); /* * Now write this updated FWU metadata to both the * FWU metadata partitions */ - ret = fwu_sync_mdata(mdata, BOTH_PARTS); + ret = fwu_sync_mdata(data->fwu_mdata, BOTH_PARTS); if (ret) { log_debug("Failed to update FWU metadata partitions\n"); ret = -EIO; @@ -346,7 +415,7 @@ int fwu_get_dfu_alt_num(u8 image_index, u8 *alt_num) int ret, i; uint update_bank; efi_guid_t *image_guid, image_type_id; - struct fwu_mdata *mdata = &g_mdata; + struct fwu_data *data = &g_fwu_data; struct fwu_image_entry *img_entry; struct fwu_image_bank_info *img_bank_info; @@ -365,15 +434,15 @@ int fwu_get_dfu_alt_num(u8 image_index, u8 *alt_num) ret = -EINVAL; /* - * The FWU metadata has been read. Now get the image_uuid for the + * The FWU metadata has been read. Now get the image_guid for the * image with the update_bank. */ for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) { if (!guidcmp(&image_type_id, - &mdata->img_entry[i].image_type_uuid)) { - img_entry = &mdata->img_entry[i]; + &data->fwu_images[i].image_type_guid)) { + img_entry = &data->fwu_images[i]; img_bank_info = &img_entry->img_bank_info[update_bank]; - image_guid = &img_bank_info->image_uuid; + image_guid = &img_bank_info->image_guid; ret = fwu_plat_get_alt_num(g_dev, image_guid, alt_num); if (ret) log_debug("alt_num not found for partition with GUID %pUs\n", @@ -407,21 +476,23 @@ int fwu_revert_boot_index(void) { int ret; u32 cur_active_index; - struct fwu_mdata *mdata = &g_mdata; + struct fwu_data *data = &g_fwu_data; /* * Swap the active index and previous_active_index fields * in the FWU metadata */ - cur_active_index = mdata->active_index; - mdata->active_index = mdata->previous_active_index; - mdata->previous_active_index = cur_active_index; + cur_active_index = data->active_index; + data->active_index = data->previous_active_index; + data->previous_active_index = cur_active_index; + + fwu_populate_mdata_bank_index(data); /* * Now write this updated FWU metadata to both the * FWU metadata partitions */ - ret = fwu_sync_mdata(mdata, BOTH_PARTS); + ret = fwu_sync_mdata(data->fwu_mdata, BOTH_PARTS); if (ret) { log_debug("Failed to update FWU metadata partitions\n"); ret = -EIO; @@ -448,20 +519,21 @@ int fwu_revert_boot_index(void) static int fwu_clrset_image_accept(efi_guid_t *img_type_id, u32 bank, u8 action) { int ret, i; - struct fwu_mdata *mdata = &g_mdata; + struct fwu_data *data = &g_fwu_data; struct fwu_image_entry *img_entry; struct fwu_image_bank_info *img_bank_info; - img_entry = &mdata->img_entry[0]; + img_entry = &data->fwu_images[0]; for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) { - if (!guidcmp(&img_entry[i].image_type_uuid, img_type_id)) { + if (!guidcmp(&img_entry[i].image_type_guid, img_type_id)) { img_bank_info = &img_entry[i].img_bank_info[bank]; if (action == IMAGE_ACCEPT_SET) img_bank_info->accepted |= FWU_IMAGE_ACCEPTED; else img_bank_info->accepted = 0; - ret = fwu_sync_mdata(mdata, BOTH_PARTS); + fwu_populate_mdata_image_info(data); + ret = fwu_sync_mdata(data->fwu_mdata, BOTH_PARTS); goto out; } } @@ -627,9 +699,9 @@ static int fwu_boottime_checks(void) return 0; } - ret = fwu_get_mdata(NULL); + ret = fwu_init(); if (ret) { - log_debug("Unable to read meta-data\n"); + log_debug("fwu_init() failed\n"); return ret; } @@ -665,7 +737,7 @@ static int fwu_boottime_checks(void) if (efi_init_obj_list() != EFI_SUCCESS) return 0; - in_trial = in_trial_state(&g_mdata); + in_trial = in_trial_state(); if (!in_trial || (ret = fwu_trial_count_update()) > 0) ret = trial_counter_update(NULL); From 5a5c4dedd3b15f75f3dae490c79b1691adc085e4 Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Fri, 22 Mar 2024 16:27:22 +0530 Subject: [PATCH 062/383] capsule: fwu: transition the platform state on a successful update Transition the platform to either Trial State or Regular State on a successful update. Do this by calling the fwu_state_machine_updates() API function. For version 1 of the FWU metadata, the transition to Trial State is done by starting the Trial State counter, while for version 2, in addition to the counter, the bank_state field of the FWU metadata is also updated to Valid. For transitioning the platform to Regular State, no action is needed with version 1 of the FWU metadata structure, while for version 2, the bank_state field is set to Accepted. Signed-off-by: Sughosh Ganu Tested-by: Michal Simek --- lib/efi_loader/efi_capsule.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c index de0d49ebebd..0937800e588 100644 --- a/lib/efi_loader/efi_capsule.c +++ b/lib/efi_loader/efi_capsule.c @@ -480,6 +480,11 @@ static __maybe_unused efi_status_t fwu_empty_capsule_process( if (ret != EFI_SUCCESS) log_err("Unable to set the Accept bit for the image %pUs\n", image_guid); + + status = fwu_state_machine_updates(0, active_idx); + if (status < 0) + ret = EFI_DEVICE_ERROR; + } return ret; @@ -521,11 +526,10 @@ static __maybe_unused efi_status_t fwu_post_update_process(bool fw_accept_os) log_err("Failed to update FWU metadata index values\n"); } else { log_debug("Successfully updated the active_index\n"); - if (fw_accept_os) { - status = fwu_trial_state_ctr_start(); - if (status < 0) - ret = EFI_DEVICE_ERROR; - } + status = fwu_state_machine_updates(fw_accept_os ? 1 : 0, + update_index); + if (status < 0) + ret = EFI_DEVICE_ERROR; } return ret; From 222cd230e1644b8d327f921b820964e74ba0f1a4 Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Fri, 22 Mar 2024 16:27:23 +0530 Subject: [PATCH 063/383] fwu: add config symbols for enabling FWU metadata versions Support has been added for version 2 of the FWU metadata structure. Add config symbols to enable either of the two versions. Signed-off-by: Sughosh Ganu Tested-by: Michal Simek --- lib/fwu_updates/Kconfig | 14 ++++++++++++++ lib/fwu_updates/Makefile | 2 ++ 2 files changed, 16 insertions(+) diff --git a/lib/fwu_updates/Kconfig b/lib/fwu_updates/Kconfig index d35247d0e5d..51b7fbbefd3 100644 --- a/lib/fwu_updates/Kconfig +++ b/lib/fwu_updates/Kconfig @@ -31,4 +31,18 @@ config FWU_TRIAL_STATE_CNT the platform is allowed to boot in Trial State after an update. +config FWU_MDATA_V1 + bool "Enable support FWU Metadata version 1" + help + The FWU specification supports two versions of the + metadata structure. This option enables support for FWU + Metadata version 1 access. + +config FWU_MDATA_V2 + bool "Enable support FWU Metadata version 2" + help + The FWU specification supports two versions of the + metadata structure. This option enables support for FWU + Metadata version 2 access. + endif diff --git a/lib/fwu_updates/Makefile b/lib/fwu_updates/Makefile index c9e3c06b489..3681bef46cd 100644 --- a/lib/fwu_updates/Makefile +++ b/lib/fwu_updates/Makefile @@ -6,3 +6,5 @@ obj-$(CONFIG_FWU_MULTI_BANK_UPDATE) += fwu.o obj-$(CONFIG_FWU_MDATA_GPT_BLK) += fwu_gpt.o obj-$(CONFIG_FWU_MDATA_MTD) += fwu_mtd.o +obj-$(CONFIG_FWU_MDATA_V1) += fwu_v1.o +obj-$(CONFIG_FWU_MDATA_V2) += fwu_v2.o From 840afae16f10a6f440b70488fdbf7ab59bf5686d Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Fri, 22 Mar 2024 16:27:24 +0530 Subject: [PATCH 064/383] fwu: mtd: remove unused argument from function call The third argument passed to the function gen_image_alt_info() is not used and is superfluous. Remove this unused argument from the function call. Fixes: 4898679e190 (FWU: Add FWU metadata access driver for MTD storage regions) Signed-off-by: Sughosh Ganu Tested-by: Michal Simek --- lib/fwu_updates/fwu_mtd.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/lib/fwu_updates/fwu_mtd.c b/lib/fwu_updates/fwu_mtd.c index 69cd3d7001f..d48de19009b 100644 --- a/lib/fwu_updates/fwu_mtd.c +++ b/lib/fwu_updates/fwu_mtd.c @@ -107,7 +107,7 @@ __weak int fwu_plat_get_alt_num(struct udevice *dev, efi_guid_t *image_id, return fwu_mtd_get_alt_num(image_id, alt_num, "nor1"); } -static int gen_image_alt_info(char *buf, size_t len, int sidx, +static int gen_image_alt_info(char *buf, size_t len, struct fwu_image_entry *img, struct mtd_info *mtd) { char *p = buf, *end = buf + len; @@ -168,8 +168,7 @@ int fwu_gen_alt_info_from_mtd(char *buf, size_t len, struct mtd_info *mtd) } for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) { - ret = gen_image_alt_info(buf, len, i * CONFIG_FWU_NUM_BANKS, - &mdata.img_entry[i], mtd); + ret = gen_image_alt_info(buf, len, &mdata.img_entry[i], mtd); if (ret) break; From 1bef7198cd8f747ccd91cc103613afde96d4199f Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Fri, 22 Mar 2024 16:27:25 +0530 Subject: [PATCH 065/383] fwu: mtd: get MTD partition specific info from driver Information about FWU images on MTD partitions is now stored with the corresponding driver instead of a global variable. Get this information from the driver. Signed-off-by: Sughosh Ganu Tested-by: Michal Simek --- lib/fwu_updates/fwu_mtd.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/lib/fwu_updates/fwu_mtd.c b/lib/fwu_updates/fwu_mtd.c index d48de19009b..f4e0e3107be 100644 --- a/lib/fwu_updates/fwu_mtd.c +++ b/lib/fwu_updates/fwu_mtd.c @@ -15,16 +15,21 @@ #include -struct fwu_mtd_image_info -fwu_mtd_images[CONFIG_FWU_NUM_BANKS * CONFIG_FWU_NUM_IMAGES_PER_BANK]; - static struct fwu_mtd_image_info *mtd_img_by_uuid(const char *uuidbuf) { - int num_images = ARRAY_SIZE(fwu_mtd_images); + int num_images; + struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(fwu_get_dev()); + struct fwu_mtd_image_info *image_info = mtd_priv->fwu_mtd_images; + + if (!image_info) + return NULL; + + num_images = CONFIG_FWU_NUM_BANKS * + CONFIG_FWU_NUM_IMAGES_PER_BANK; for (int i = 0; i < num_images; i++) - if (!strcmp(uuidbuf, fwu_mtd_images[i].uuidbuf)) - return &fwu_mtd_images[i]; + if (!strcmp(uuidbuf, image_info[i].uuidbuf)) + return &image_info[i]; return NULL; } From 8ee8b9c900e350464ab2337ce0b0a7b2aa71f0f3 Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Fri, 22 Mar 2024 16:27:26 +0530 Subject: [PATCH 066/383] fwu: mtd: obtain image information from version agnostic structure Make changes to the functions used for generating the DFU's alt variable so that the FWU image information is obtained from the common version agnostic structure instead of reading the metadata. While here, also update the name of the field used for storing the image GUID in the FWU metadata. Signed-off-by: Sughosh Ganu Tested-by: Michal Simek --- lib/fwu_updates/fwu_mtd.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/lib/fwu_updates/fwu_mtd.c b/lib/fwu_updates/fwu_mtd.c index f4e0e3107be..e8211dd5baf 100644 --- a/lib/fwu_updates/fwu_mtd.c +++ b/lib/fwu_updates/fwu_mtd.c @@ -136,7 +136,7 @@ static int gen_image_alt_info(char *buf, size_t len, /* Query a partition by image UUID */ bank = &img->img_bank_info[i]; - uuid_bin_to_str(bank->image_uuid.b, uuidbuf, UUID_STR_FORMAT_STD); + uuid_bin_to_str(bank->image_guid.b, uuidbuf, UUID_STR_FORMAT_STD); mtd_img_info = mtd_img_by_uuid(uuidbuf); if (!mtd_img_info) { @@ -163,17 +163,13 @@ static int gen_image_alt_info(char *buf, size_t len, int fwu_gen_alt_info_from_mtd(char *buf, size_t len, struct mtd_info *mtd) { - struct fwu_mdata mdata; int i, l, ret; - - ret = fwu_get_mdata(&mdata); - if (ret < 0) { - log_err("Failed to get the FWU mdata.\n"); - return ret; - } + struct fwu_data *data = fwu_get_data(); + struct fwu_image_entry *img_entry; for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) { - ret = gen_image_alt_info(buf, len, &mdata.img_entry[i], mtd); + img_entry = &data->fwu_images[i]; + ret = gen_image_alt_info(buf, len, img_entry, mtd); if (ret) break; From 7cfe0d8a4885ec62b21d3173da4863420f2a9b00 Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Fri, 22 Mar 2024 16:27:27 +0530 Subject: [PATCH 067/383] cmd: fwu: make changes for supporting FWU metadata version 2 Add support for displaying data specific to FWU metadata version 2. Because the size of the v2 metadata structure is read from the structure itself, allocate memory for the metadata structure by first getting the size of the structure. Signed-off-by: Sughosh Ganu Tested-by: Michal Simek --- cmd/fwu_mdata.c | 39 ++++++++++++++++++--------------------- 1 file changed, 18 insertions(+), 21 deletions(-) diff --git a/cmd/fwu_mdata.c b/cmd/fwu_mdata.c index 5ecda455df6..3c8be576ac7 100644 --- a/cmd/fwu_mdata.c +++ b/cmd/fwu_mdata.c @@ -13,27 +13,33 @@ #include -static void print_mdata(struct fwu_mdata *mdata) +static void print_mdata(struct fwu_data *data) { int i, j; struct fwu_image_entry *img_entry; struct fwu_image_bank_info *img_info; printf("\tFWU Metadata\n"); - printf("crc32: %#x\n", mdata->crc32); - printf("version: %#x\n", mdata->version); - printf("active_index: %#x\n", mdata->active_index); - printf("previous_active_index: %#x\n", mdata->previous_active_index); + printf("crc32: %#x\n", data->crc32); + printf("version: %#x\n", data->version); + printf("active_index: %#x\n", data->active_index); + printf("previous_active_index: %#x\n", data->previous_active_index); + + if (data->version == 2) { + for (i = 0; i < 4; i++) + printf("bank_state[%d]: %#x\n", + i, data->bank_state[i]); + } printf("\tImage Info\n"); for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) { - img_entry = &mdata->img_entry[i]; + img_entry = &data->fwu_images[i]; printf("\nImage Type Guid: %pUL\n", - &img_entry->image_type_uuid); - printf("Location Guid: %pUL\n", &img_entry->location_uuid); + &img_entry->image_type_guid); + printf("Location Guid: %pUL\n", &img_entry->location_guid); for (j = 0; j < CONFIG_FWU_NUM_BANKS; j++) { img_info = &img_entry->img_bank_info[j]; - printf("Image Guid: %pUL\n", &img_info->image_uuid); + printf("Image Guid: %pUL\n", &img_info->image_guid); printf("Image Acceptance: %s\n", img_info->accepted == 0x1 ? "yes" : "no"); } @@ -43,20 +49,11 @@ static void print_mdata(struct fwu_mdata *mdata) int do_fwu_mdata_read(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) { - int ret = CMD_RET_SUCCESS, res; - struct fwu_mdata mdata; + struct fwu_data *data = fwu_get_data(); - res = fwu_get_mdata(&mdata); - if (res < 0) { - log_err("Unable to get valid FWU metadata\n"); - ret = CMD_RET_FAILURE; - goto out; - } + print_mdata(data); - print_mdata(&mdata); - -out: - return ret; + return CMD_RET_SUCCESS; } U_BOOT_CMD( From df42d684961fbb9a79e6ae81234d97799d3efbbb Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Fri, 22 Mar 2024 16:27:28 +0530 Subject: [PATCH 068/383] tools: mkfwumdata: add support for metadata version 2 Add support for generating the FWU metadata version 2. The tool now requires the version to be provided as a command-line option. Make corresponding changes to the tool's manpage. Signed-off-by: Sughosh Ganu Tested-by: Michal Simek --- doc/mkfwumdata.1 | 9 ++- tools/mkfwumdata.c | 148 ++++++++++++++++++++++++++++++++++++--------- 2 files changed, 127 insertions(+), 30 deletions(-) diff --git a/doc/mkfwumdata.1 b/doc/mkfwumdata.1 index 7dd718b26e2..5e61c615ead 100644 --- a/doc/mkfwumdata.1 +++ b/doc/mkfwumdata.1 @@ -6,6 +6,7 @@ mkfwumdata \- create FWU metadata image . .SH SYNOPSIS .SY mkfwumdata +.OP \-v version .OP \-a activeidx .OP \-p previousidx .OP \-g @@ -28,6 +29,12 @@ creates metadata info to be used with FWU. Print usage information and exit. . .TP +.B \-v +Set +.IR version +as the metadata version to generate. Valid values 1 or 2. +. +.TP .B \-a Set .IR activeidx @@ -81,7 +88,7 @@ Create a metadata image with 2 banks and 1 image/bank, BankAct=0, BankPrev=1: .EX .in +4 $ \c -.B mkfwumdata \-a 0 \-p 1 \-b 2 \-i 1 \\\\\& +.B mkfwumdata \-v 2 \-a 0 \-p 1 \-b 2 \-i 1 \\\\\& .in +6 .B 17e86d77-41f9-4fd7-87ec-a55df9842de5,\\\\\& .B 10c36d7d-ca52-b843-b7b9-f9d6c501d108,\\\\\& diff --git a/tools/mkfwumdata.c b/tools/mkfwumdata.c index b2d90ca7c94..634453d421e 100644 --- a/tools/mkfwumdata.c +++ b/tools/mkfwumdata.c @@ -10,28 +10,35 @@ #include #include #include -#include #include +#include +#include #include -/* This will dynamically allocate the fwu_mdata */ -#define CONFIG_FWU_NUM_BANKS 0 -#define CONFIG_FWU_NUM_IMAGES_PER_BANK 0 - -/* Since we can not include fwu.h, redefine version here. */ -#define FWU_MDATA_VERSION 1 - typedef uint8_t u8; typedef int16_t s16; typedef uint16_t u16; typedef uint32_t u32; typedef uint64_t u64; +#undef CONFIG_FWU_NUM_BANKS +#undef CONFIG_FWU_NUM_IMAGES_PER_BANK + +/* This will dynamically allocate the fwu_mdata */ +#define CONFIG_FWU_NUM_BANKS 0 +#define CONFIG_FWU_NUM_IMAGES_PER_BANK 0 + +/* version 2 supports maximum of 4 banks */ +#define MAX_BANKS_V2 4 + +#define BANK_INVALID (u8)0xFF +#define BANK_ACCEPTED (u8)0xFC + #include /* TODO: Endianness conversion may be required for some arch. */ -static const char *opts_short = "b:i:a:p:gh"; +static const char *opts_short = "b:i:a:p:v:gh"; static struct option options[] = { {"banks", required_argument, NULL, 'b'}, @@ -39,6 +46,7 @@ static struct option options[] = { {"guid", required_argument, NULL, 'g'}, {"active-bank", required_argument, NULL, 'a'}, {"previous-bank", required_argument, NULL, 'p'}, + {"version", required_argument, NULL, 'v'}, {"help", no_argument, NULL, 'h'}, {NULL, 0, NULL, 0}, }; @@ -49,6 +57,7 @@ static void print_usage(void) fprintf(stderr, "Options:\n" "\t-i, --images Number of images (mandatory)\n" "\t-b, --banks Number of banks (mandatory)\n" + "\t-v, --version Metadata version (mandatory)\n" "\t-a, --active-bank Active bank (default=0)\n" "\t-p, --previous-bank Previous active bank (default=active_bank - 1)\n" "\t-g, --guid Use GUID instead of UUID\n" @@ -70,13 +79,26 @@ struct fwu_mdata_object { size_t images; size_t banks; size_t size; + u8 version; struct fwu_mdata *mdata; }; static int previous_bank, active_bank; static bool __use_guid; -static struct fwu_mdata_object *fwu_alloc_mdata(size_t images, size_t banks) +static bool supported_mdata_version(unsigned long version) +{ + switch (version) { + case 1: + case 2: + return true; + default: + return false; + } +} + +static struct fwu_mdata_object *fwu_alloc_mdata(size_t images, size_t banks, + u8 version) { struct fwu_mdata_object *mobj; @@ -84,11 +106,20 @@ static struct fwu_mdata_object *fwu_alloc_mdata(size_t images, size_t banks) if (!mobj) return NULL; - mobj->size = sizeof(struct fwu_mdata) + - (sizeof(struct fwu_image_entry) + - sizeof(struct fwu_image_bank_info) * banks) * images; + if (version == 1) { + mobj->size = sizeof(struct fwu_mdata) + + (sizeof(struct fwu_image_entry) + + sizeof(struct fwu_image_bank_info) * banks) * images; + } else { + mobj->size = sizeof(struct fwu_mdata) + + sizeof(struct fwu_fw_store_desc) + + (sizeof(struct fwu_image_entry) + + sizeof(struct fwu_image_bank_info) * banks) * images; + } + mobj->images = images; mobj->banks = banks; + mobj->version = version; mobj->mdata = calloc(1, mobj->size); if (!mobj->mdata) { @@ -104,9 +135,18 @@ fwu_get_image(struct fwu_mdata_object *mobj, size_t idx) { size_t offset; - offset = sizeof(struct fwu_mdata) + - (sizeof(struct fwu_image_entry) + - sizeof(struct fwu_image_bank_info) * mobj->banks) * idx; + if (mobj->version == 1) { + offset = sizeof(struct fwu_mdata) + + (sizeof(struct fwu_image_entry) + + sizeof(struct fwu_image_bank_info) * mobj->banks) * + idx; + } else { + offset = sizeof(struct fwu_mdata) + + sizeof(struct fwu_fw_store_desc) + + (sizeof(struct fwu_image_entry) + + sizeof(struct fwu_image_bank_info) * mobj->banks) * + idx; + } return (struct fwu_image_entry *)((char *)mobj->mdata + offset); } @@ -116,11 +156,20 @@ fwu_get_bank(struct fwu_mdata_object *mobj, size_t img_idx, size_t bnk_idx) { size_t offset; - offset = sizeof(struct fwu_mdata) + - (sizeof(struct fwu_image_entry) + - sizeof(struct fwu_image_bank_info) * mobj->banks) * img_idx + - sizeof(struct fwu_image_entry) + - sizeof(struct fwu_image_bank_info) * bnk_idx; + if (mobj->version == 1) { + offset = sizeof(struct fwu_mdata) + + (sizeof(struct fwu_image_entry) + + sizeof(struct fwu_image_bank_info) * mobj->banks) * + img_idx + sizeof(struct fwu_image_entry) + + sizeof(struct fwu_image_bank_info) * bnk_idx; + } else { + offset = sizeof(struct fwu_mdata) + + sizeof(struct fwu_fw_store_desc) + + (sizeof(struct fwu_image_entry) + + sizeof(struct fwu_image_bank_info) * mobj->banks) * + img_idx + sizeof(struct fwu_image_entry) + + sizeof(struct fwu_image_bank_info) * bnk_idx; + } return (struct fwu_image_bank_info *)((char *)mobj->mdata + offset); } @@ -188,7 +237,7 @@ fwu_parse_fill_image_uuid(struct fwu_mdata_object *mobj, return -EINVAL; if (strcmp(uuid, "0") && - uuid_guid_parse(uuid, (unsigned char *)&image->location_uuid) < 0) + uuid_guid_parse(uuid, (unsigned char *)&image->location_guid) < 0) return -EINVAL; /* Image type UUID */ @@ -196,7 +245,7 @@ fwu_parse_fill_image_uuid(struct fwu_mdata_object *mobj, if (!uuid) return -EINVAL; - if (uuid_guid_parse(uuid, (unsigned char *)&image->image_type_uuid) < 0) + if (uuid_guid_parse(uuid, (unsigned char *)&image->image_type_guid) < 0) return -EINVAL; /* Fill bank image-UUID */ @@ -210,22 +259,52 @@ fwu_parse_fill_image_uuid(struct fwu_mdata_object *mobj, return -EINVAL; if (strcmp(uuid, "0") && - uuid_guid_parse(uuid, (unsigned char *)&bank->image_uuid) < 0) + uuid_guid_parse(uuid, (unsigned char *)&bank->image_guid) < 0) return -EINVAL; } return 0; } +#if defined(CONFIG_FWU_MDATA_V1) +static void fwu_fill_version_specific_mdata(struct fwu_mdata_object *mobj) +{ +} +#else +static void fwu_fill_version_specific_mdata(struct fwu_mdata_object *mobj) +{ + int i; + struct fwu_fw_store_desc *fw_desc; + struct fwu_mdata *mdata = mobj->mdata; + + mdata->metadata_size = mobj->size; + mdata->desc_offset = sizeof(struct fwu_mdata); + + for (i = 0; i < MAX_BANKS_V2; i++) + mdata->bank_state[i] = i < mobj->banks ? + BANK_ACCEPTED : BANK_INVALID; + + fw_desc = (struct fwu_fw_store_desc *)((u8 *)mdata + sizeof(*mdata)); + fw_desc->num_banks = mobj->banks; + fw_desc->num_images = mobj->images; + fw_desc->img_entry_size = sizeof(struct fwu_image_entry) + + (sizeof(struct fwu_image_bank_info) * mobj->banks); + fw_desc->bank_info_entry_size = + sizeof(struct fwu_image_bank_info); +} +#endif /* CONFIG_FWU_MDATA_V1 */ + /* Caller must ensure that @uuids[] has @mobj->images entries. */ static int fwu_parse_fill_uuids(struct fwu_mdata_object *mobj, char *uuids[]) { struct fwu_mdata *mdata = mobj->mdata; int i, ret; - mdata->version = FWU_MDATA_VERSION; + mdata->version = mobj->version; mdata->active_index = active_bank; mdata->previous_active_index = previous_bank; + fwu_fill_version_specific_mdata(mobj); + for (i = 0; i < mobj->images; i++) { ret = fwu_parse_fill_image_uuid(mobj, i, uuids[i]); if (ret < 0) @@ -239,13 +318,14 @@ static int fwu_parse_fill_uuids(struct fwu_mdata_object *mobj, char *uuids[]) } static int -fwu_make_mdata(size_t images, size_t banks, char *uuids[], char *output) +fwu_make_mdata(size_t images, size_t banks, u8 version, char *uuids[], + char *output) { struct fwu_mdata_object *mobj; FILE *file; int ret; - mobj = fwu_alloc_mdata(images, banks); + mobj = fwu_alloc_mdata(images, banks, version); if (!mobj) return -ENOMEM; @@ -276,7 +356,7 @@ done_make: int main(int argc, char *argv[]) { - unsigned long banks = 0, images = 0; + unsigned long banks = 0, images = 0, version = 0; int c, ret; /* Explicitly initialize defaults */ @@ -305,6 +385,9 @@ int main(int argc, char *argv[]) case 'a': active_bank = strtoul(optarg, NULL, 0); break; + case 'v': + version = strtoul(optarg, NULL, 0); + break; } } while (c != -1); @@ -313,6 +396,12 @@ int main(int argc, char *argv[]) return -EINVAL; } + if (!version || !supported_mdata_version(version)) { + fprintf(stderr, "Error: Version value can only be either 1 or 2, not %ld.\n", + version); + return -EINVAL; + } + /* This command takes UUIDs * images and output file. */ if (optind + images + 1 != argc) { fprintf(stderr, "Error: UUID list or output file is not specified or too much.\n"); @@ -325,7 +414,8 @@ int main(int argc, char *argv[]) previous_bank = active_bank > 0 ? active_bank - 1 : banks - 1; } - ret = fwu_make_mdata(images, banks, argv + optind, argv[argc - 1]); + ret = fwu_make_mdata(images, banks, (u8)version, argv + optind, + argv[argc - 1]); if (ret < 0) fprintf(stderr, "Error: Failed to parse and write image: %s\n", strerror(-ret)); From cb9ae40a16f0e9adae594526435de976afeedaf2 Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Fri, 22 Mar 2024 16:27:29 +0530 Subject: [PATCH 069/383] tools: mkfwumdata: add logic to append vendor data to the FWU metadata The version 2 of the FWU metadata allows for appending opaque vendor specific data to the metadata structure. Add support for appending this data to the metadata. The vendor specific data needs to be provided through a file, passed through a command-line parameter. Make corresponding changes to the tool's manpage. Signed-off-by: Sughosh Ganu Tested-by: Michal Simek --- doc/mkfwumdata.1 | 7 ++++ tools/mkfwumdata.c | 101 ++++++++++++++++++++++++++++++++++++++------- 2 files changed, 92 insertions(+), 16 deletions(-) diff --git a/doc/mkfwumdata.1 b/doc/mkfwumdata.1 index 5e61c615ead..2ed0fb100b8 100644 --- a/doc/mkfwumdata.1 +++ b/doc/mkfwumdata.1 @@ -10,6 +10,7 @@ mkfwumdata \- create FWU metadata image .OP \-a activeidx .OP \-p previousidx .OP \-g +.OP \-V vendor-file .BI \-i\~ imagecount .BI \-b\~ bankcount .I UUIDs @@ -57,6 +58,12 @@ Convert the as GUIDs before use. . .TP +.B \-V +Pass +.IR vendor-file +for appending vendor data to the metadata. Supported only with version 2. +. +.TP .B \-i Specify there are .IR imagecount diff --git a/tools/mkfwumdata.c b/tools/mkfwumdata.c index 634453d421e..fbc2067bc12 100644 --- a/tools/mkfwumdata.c +++ b/tools/mkfwumdata.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include #include #include @@ -36,9 +38,7 @@ typedef uint64_t u64; #include -/* TODO: Endianness conversion may be required for some arch. */ - -static const char *opts_short = "b:i:a:p:v:gh"; +static const char *opts_short = "b:i:a:p:v:V:gh"; static struct option options[] = { {"banks", required_argument, NULL, 'b'}, @@ -47,6 +47,7 @@ static struct option options[] = { {"active-bank", required_argument, NULL, 'a'}, {"previous-bank", required_argument, NULL, 'p'}, {"version", required_argument, NULL, 'v'}, + {"vendor-file", required_argument, NULL, 'V'}, {"help", no_argument, NULL, 'h'}, {NULL, 0, NULL, 0}, }; @@ -61,6 +62,7 @@ static void print_usage(void) "\t-a, --active-bank Active bank (default=0)\n" "\t-p, --previous-bank Previous active bank (default=active_bank - 1)\n" "\t-g, --guid Use GUID instead of UUID\n" + "\t-V, --vendor-file Vendor data file to append to the metadata\n" "\t-h, --help print a help message\n" ); fprintf(stderr, " UUIDs list syntax:\n" @@ -80,6 +82,8 @@ struct fwu_mdata_object { size_t banks; size_t size; u8 version; + size_t vsize; + void *vbuf; struct fwu_mdata *mdata; }; @@ -98,7 +102,7 @@ static bool supported_mdata_version(unsigned long version) } static struct fwu_mdata_object *fwu_alloc_mdata(size_t images, size_t banks, - u8 version) + u8 version, size_t vendor_size) { struct fwu_mdata_object *mobj; @@ -115,6 +119,9 @@ static struct fwu_mdata_object *fwu_alloc_mdata(size_t images, size_t banks, sizeof(struct fwu_fw_store_desc) + (sizeof(struct fwu_image_entry) + sizeof(struct fwu_image_bank_info) * banks) * images; + + mobj->size += vendor_size; + mobj->vsize = vendor_size; } mobj->images = images; @@ -122,12 +129,21 @@ static struct fwu_mdata_object *fwu_alloc_mdata(size_t images, size_t banks, mobj->version = version; mobj->mdata = calloc(1, mobj->size); - if (!mobj->mdata) { - free(mobj); - return NULL; + if (!mobj->mdata) + goto alloc_err; + + if (vendor_size) { + mobj->vbuf = calloc(1, mobj->vsize); + if (!mobj->vbuf) + goto alloc_err; } return mobj; + +alloc_err: + free(mobj->mdata); + free(mobj); + return NULL; } static struct fwu_image_entry * @@ -297,6 +313,7 @@ static void fwu_fill_version_specific_mdata(struct fwu_mdata_object *mobj) static int fwu_parse_fill_uuids(struct fwu_mdata_object *mobj, char *uuids[]) { struct fwu_mdata *mdata = mobj->mdata; + char *vdata; int i, ret; mdata->version = mobj->version; @@ -311,24 +328,65 @@ static int fwu_parse_fill_uuids(struct fwu_mdata_object *mobj, char *uuids[]) return ret; } + if (mobj->vsize) { + vdata = (char *)mobj->mdata + (mobj->size - mobj->vsize); + memcpy(vdata, mobj->vbuf, mobj->vsize); + } + mdata->crc32 = crc32(0, (const unsigned char *)&mdata->version, mobj->size - sizeof(uint32_t)); return 0; } -static int -fwu_make_mdata(size_t images, size_t banks, u8 version, char *uuids[], - char *output) +static int fwu_read_vendor_data(struct fwu_mdata_object *mobj, + const char *vendor_file) { - struct fwu_mdata_object *mobj; - FILE *file; - int ret; + int ret = 0; + FILE *vfile = NULL; - mobj = fwu_alloc_mdata(images, banks, version); + vfile = fopen(vendor_file, "r"); + if (!vfile) { + ret = -1; + goto out; + } + + if (fread(mobj->vbuf, 1, mobj->vsize, vfile) != mobj->vsize) + ret = -1; + +out: + fclose(vfile); + return ret; +} + +static int fwu_make_mdata(size_t images, size_t banks, u8 version, + const char *vendor_file, char *uuids[], + char *output) +{ + int ret; + FILE *file; + struct stat sbuf; + size_t vendor_size = 0; + struct fwu_mdata_object *mobj; + + if (vendor_file) { + ret = stat(vendor_file, &sbuf); + if (ret) + return -errno; + + vendor_size = sbuf.st_size; + } + + mobj = fwu_alloc_mdata(images, banks, version, vendor_size); if (!mobj) return -ENOMEM; + if (vendor_file) { + ret = fwu_read_vendor_data(mobj, vendor_file); + if (ret) + goto done_make; + } + ret = fwu_parse_fill_uuids(mobj, uuids); if (ret < 0) goto done_make; @@ -349,6 +407,7 @@ fwu_make_mdata(size_t images, size_t banks, u8 version, char *uuids[], done_make: free(mobj->mdata); + free(mobj->vbuf); free(mobj); return ret; @@ -358,11 +417,13 @@ int main(int argc, char *argv[]) { unsigned long banks = 0, images = 0, version = 0; int c, ret; + const char *vendor_file; /* Explicitly initialize defaults */ active_bank = 0; __use_guid = false; previous_bank = INT_MAX; + vendor_file = NULL; do { c = getopt_long(argc, argv, opts_short, options, NULL); @@ -388,6 +449,9 @@ int main(int argc, char *argv[]) case 'v': version = strtoul(optarg, NULL, 0); break; + case 'V': + vendor_file = optarg; + break; } } while (c != -1); @@ -402,6 +466,11 @@ int main(int argc, char *argv[]) return -EINVAL; } + if (version == 1 && vendor_file) { + fprintf(stderr, "Error: Vendor Data can only be appended in version 2 of FWU Metadata.\n"); + return -EINVAL; + } + /* This command takes UUIDs * images and output file. */ if (optind + images + 1 != argc) { fprintf(stderr, "Error: UUID list or output file is not specified or too much.\n"); @@ -414,8 +483,8 @@ int main(int argc, char *argv[]) previous_bank = active_bank > 0 ? active_bank - 1 : banks - 1; } - ret = fwu_make_mdata(images, banks, (u8)version, argv + optind, - argv[argc - 1]); + ret = fwu_make_mdata(images, banks, (u8)version, vendor_file, + argv + optind, argv[argc - 1]); if (ret < 0) fprintf(stderr, "Error: Failed to parse and write image: %s\n", strerror(-ret)); From cdc4b465021da17cb2a375411f8b5408088a8893 Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Fri, 22 Mar 2024 16:27:30 +0530 Subject: [PATCH 070/383] test: fwu: make changes to the FWU metadata access test Make changes to the FWU metadata access tests corresponding to the changes in the FWU metadata access code. Signed-off-by: Sughosh Ganu Tested-by: Michal Simek --- test/dm/fwu_mdata.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/test/dm/fwu_mdata.c b/test/dm/fwu_mdata.c index 52018f610fe..621ba647d96 100644 --- a/test/dm/fwu_mdata.c +++ b/test/dm/fwu_mdata.c @@ -93,6 +93,10 @@ static int dm_test_fwu_mdata_read(struct unit_test_state *uts) struct udevice *dev; struct fwu_mdata mdata = { 0 }; + ut_assertok(setup_blk_device(uts)); + ut_assertok(populate_mmc_disk_image(uts)); + ut_assertok(write_mmc_blk_device(uts)); + /* * Trigger lib/fwu_updates/fwu.c fwu_boottime_checks() * to populate g_dev global pointer in that library. @@ -100,9 +104,7 @@ static int dm_test_fwu_mdata_read(struct unit_test_state *uts) event_notify_null(EVT_MAIN_LOOP); ut_assertok(uclass_first_device_err(UCLASS_FWU_MDATA, &dev)); - ut_assertok(setup_blk_device(uts)); - ut_assertok(populate_mmc_disk_image(uts)); - ut_assertok(write_mmc_blk_device(uts)); + ut_assertok(fwu_init()); ut_assertok(fwu_get_mdata(&mdata)); @@ -118,18 +120,20 @@ static int dm_test_fwu_mdata_write(struct unit_test_state *uts) struct udevice *dev; struct fwu_mdata mdata = { 0 }; + ut_assertok(setup_blk_device(uts)); + ut_assertok(populate_mmc_disk_image(uts)); + ut_assertok(write_mmc_blk_device(uts)); + /* * Trigger lib/fwu_updates/fwu.c fwu_boottime_checks() * to populate g_dev global pointer in that library. */ event_notify_null(EVT_MAIN_LOOP); - ut_assertok(setup_blk_device(uts)); - ut_assertok(populate_mmc_disk_image(uts)); - ut_assertok(write_mmc_blk_device(uts)); ut_assertok(uclass_first_device_err(UCLASS_FWU_MDATA, &dev)); + ut_assertok(fwu_init()); ut_assertok(fwu_get_mdata(&mdata)); active_idx = (mdata.active_index + 1) % CONFIG_FWU_NUM_BANKS; From 7ef84369708993aeb523ae6a6abd5e5aab66196b Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Fri, 22 Mar 2024 16:27:31 +0530 Subject: [PATCH 071/383] doc: fwu: make changes to reflect support for FWU metadata v2 The FWU Update Agent in U-Boot supports both versions of the FWU metadata. Make changes in the documentation to reflect this. Signed-off-by: Sughosh Ganu Tested-by: Michal Simek --- doc/board/socionext/developerbox.rst | 7 +++++-- doc/develop/uefi/fwu_updates.rst | 20 +++++++++++++++----- 2 files changed, 20 insertions(+), 7 deletions(-) diff --git a/doc/board/socionext/developerbox.rst b/doc/board/socionext/developerbox.rst index 46712c379b6..863761c6e27 100644 --- a/doc/board/socionext/developerbox.rst +++ b/doc/board/socionext/developerbox.rst @@ -116,6 +116,7 @@ configs/synquacer_developerbox_defconfig enables default FWU configuration :: CONFIG_FWU_NUM_BANKS=2 CONFIG_FWU_NUM_IMAGES_PER_BANK=1 CONFIG_CMD_FWU_METADATA=y + CONFIG_FWU_MDATA_V2=y And build it:: @@ -129,7 +130,9 @@ And build it:: By default, the CONFIG_FWU_NUM_BANKS and CONFIG_FWU_NUM_IMAGES_PER_BANKS are set to 2 and 1 respectively. This uses FIP (Firmware Image Package) type image which contains TF-A, U-Boot and OP-TEE (the OP-TEE is optional). -You can use fiptool to compose the FIP image from those firmware images. +You can use fiptool to compose the FIP image from those firmware +images. There are two versions of the FWU metadata, of which the +platform enables version 2 by default. Rebuild SCP firmware -------------------- @@ -194,7 +197,7 @@ following UUIDs. These UUIDs are used for making a FWU metadata image. -u-boot$ ./tools/mkfwumdata -i 1 -b 2 \ +u-boot$ ./tools/mkfwumdata -v 2 -i 1 -b 2 \ 17e86d77-41f9-4fd7-87ec-a55df9842de5,10c36d7d-ca52-b843-b7b9-f9d6c501d108,5a66a702-99fd-4fef-a392-c26e261a2828,a8f868a1-6e5c-4757-878d-ce63375ef2c0 \ ../devbox-fwu-mdata.img diff --git a/doc/develop/uefi/fwu_updates.rst b/doc/develop/uefi/fwu_updates.rst index e4709d82b41..51e8a28efe1 100644 --- a/doc/develop/uefi/fwu_updates.rst +++ b/doc/develop/uefi/fwu_updates.rst @@ -46,6 +46,8 @@ The feature can be enabled by specifying the following configs:: CONFIG_FWU_NUM_BANKS= CONFIG_FWU_NUM_IMAGES_PER_BANK= + CONFIG_FWU_MDATA_V1=y or CONFIG_FWU_MDATA_V2=y + in the .config file By enabling the CONFIG_CMD_FWU_METADATA config option, the @@ -58,6 +60,14 @@ enable the FWU Multi Bank Update functionality. Please refer to the section :ref:`uefi_capsule_update_ref` for more details on generation of the UEFI capsule. +FWU Metadata +------------ + +U-Boot supports both versions(1 and 2) of the FWU metadata defined in +the two revisions of the specification. Support can be enabled for +either of the two versions through a config flag. The mkfwumdata tool +can generate metadata for both the supported versions. + Setting up the device for GPT partitioned storage ------------------------------------------------- @@ -94,12 +104,12 @@ of. Each GPT partition entry in the GPT header has two GUIDs:: * UniquePartitionGUID The PartitionTypeGUID value should correspond to the -``image_type_uuid`` field of the FWU metadata. This field is used to +``image_type_guid`` field of the FWU metadata. This field is used to identify a given type of updatable firmware image, e.g. U-Boot, OP-TEE, FIP etc. This GUID should also be used for specifying the `--guid` parameter when generating the capsule. -The UniquePartitionGUID value should correspond to the ``image_uuid`` +The UniquePartitionGUID value should correspond to the ``image_guid`` field in the FWU metadata. This GUID is used to identify images of a given image type in different banks. @@ -108,8 +118,8 @@ metadata partitions. This would be the PartitionTypeGUID for the metadata partitions. Similarly, the UEFI specification defines the ESP GUID to be be used. -When generating the metadata, the ``image_type_uuid`` and the -``image_uuid`` values should match the *PartitionTypeGUID* and the +When generating the metadata, the ``image_type_guid`` and the +``image_guid`` values should match the *PartitionTypeGUID* and the *UniquePartitionGUID* values respectively. Performing the Update @@ -181,5 +191,5 @@ empty capsule would be:: Links ----- -* [1] https://developer.arm.com/documentation/den0118/a/ - FWU Specification +* [1] https://developer.arm.com/documentation/den0118/ - FWU Specification * [2] https://git.codelinaro.org/linaro/dependable-boot/mbfw/uploads/6f7ddfe3be24e18d4319e108a758d02e/mbfw.pdf - Dependable Boot Specification From 7b98f1e617f8d06897f85a87817e9bfde3067e1a Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Fri, 22 Mar 2024 16:27:32 +0530 Subject: [PATCH 072/383] MAINTAINERS: add entry for FWU multi bank update feature Add an entry for the FWU Multi Bank Update feature. Signed-off-by: Sughosh Ganu Reviewed-by: Ilias Apalodimas Tested-by: Michal Simek --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8b316c8550e..860725bef78 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1149,6 +1149,14 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq.git F: drivers/watchdog/sp805_wdt.c F: drivers/watchdog/sbsa_gwdt.c +FWU Multi Bank Update +M: Sughosh Ganu +S: Maintained +T: git https://source.denx.de/u-boot/custodians/u-boot-efi.git +F: lib/fwu_updates/* +F: drivers/fwu-mdata/* +F: tools/mkfwumdata.c + GATEWORKS_SC M: Tim Harvey S: Maintained From e32c15d6041e9298673c75b26cc6af1266046dc5 Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Fri, 22 Mar 2024 16:27:33 +0530 Subject: [PATCH 073/383] configs: fwu: re-enable FWU configs Now that support for FWU metadata version 2 has been added, the feature can be enabled on platforms which had enabled it. A new config symbol for selecting the metadata version for the platform is also being added. Signed-off-by: Sughosh Ganu Tested-by: Michal Simek --- configs/corstone1000_defconfig | 3 +++ configs/sandbox64_defconfig | 2 ++ configs/synquacer_developerbox_defconfig | 4 ++++ 3 files changed, 9 insertions(+) diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig index 29d7550afb6..ab4e0fefc90 100644 --- a/configs/corstone1000_defconfig +++ b/configs/corstone1000_defconfig @@ -24,6 +24,7 @@ CONFIG_LOGLEVEL=7 CONFIG_BOARD_LATE_INIT=y CONFIG_SYS_PROMPT="corstone1000# " # CONFIG_CMD_CONSOLE is not set +CONFIG_CMD_FWU_METADATA=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_XIMG is not set CONFIG_CMD_GPT=y @@ -66,3 +67,5 @@ CONFIG_FFA_SHARED_MM_BUF_OFFSET=0 CONFIG_FFA_SHARED_MM_BUF_ADDR=0x02000000 CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_IGNORE_OSINDICATIONS=y +CONFIG_FWU_MULTI_BANK_UPDATE=y +CONFIG_FWU_MDATA_V1=y diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 7e8200e70cb..7b316f0d80b 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -272,6 +272,8 @@ CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_EFI_SECURE_BOOT=y CONFIG_TEST_FDTDEC=y +CONFIG_FWU_MULTI_BANK_UPDATE=y +CONFIG_FWU_MDATA_V1=y CONFIG_UNIT_TEST=y CONFIG_UT_TIME=y CONFIG_UT_DM=y diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig index 616d4100744..7e1aeac217c 100644 --- a/configs/synquacer_developerbox_defconfig +++ b/configs/synquacer_developerbox_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_BOOTSTAGE_STASH_SIZE=4096 CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=128 +CONFIG_CMD_FWU_METADATA=y CONFIG_CMD_IMLS=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_NVEDIT_EFI=y @@ -51,6 +52,7 @@ CONFIG_DFU_TFTP=y CONFIG_DFU_MTD=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y +CONFIG_FWU_MDATA_MTD=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_SYNQUACER=y CONFIG_MMC_SDHCI=y @@ -93,3 +95,5 @@ CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_IGNORE_OSINDICATIONS=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_FWU_MULTI_BANK_UPDATE=y +CONFIG_FWU_MDATA_V2=y From 56f668e25eb1432601528a55069ecfd01adab081 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 May 2024 20:00:25 +0200 Subject: [PATCH 074/383] ARM: dts: renesas: Switch to using upstream DT on Renesas R8A779H0 V4M Enable OF_UPSTREAM to use upstream DT and add renesas/ prefix to the DEFAULT_DEVICE_TREE. And thereby directly build DTB from dts/upstream/src/ including *-u-boot.dtsi files from arch/$(ARCH)/dts/ directory. This patch finalizes OF_UPSTREAM conversion of R8A779H0 V4M which DTs landed in Linux 6.9 . Signed-off-by: Marek Vasut Acked-by: Sumit Garg --- configs/r8a779h0_grayhawk_defconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/configs/r8a779h0_grayhawk_defconfig b/configs/r8a779h0_grayhawk_defconfig index 6bd872f063f..a986a09b8e0 100644 --- a/configs/r8a779h0_grayhawk_defconfig +++ b/configs/r8a779h0_grayhawk_defconfig @@ -5,7 +5,7 @@ CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xFFFE0000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="r8a779h0-gray-hawk" +CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a779h0-gray-hawk-single" CONFIG_RCAR_GEN4=y CONFIG_TARGET_GRAYHAWK=y CONFIG_SYS_MONITOR_LEN=1048576 @@ -39,7 +39,6 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y -# CONFIG_OF_UPSTREAM is not set CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=2 From 63da3a795e86dcf0906beb99865e3d4139114872 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 May 2024 20:00:26 +0200 Subject: [PATCH 075/383] ARM: dts: renesas: Drop R8A779H0 V4M DTs with OF_UPSTREAM counterparts Remove R8A779H0 V4M DTs which are now replaced by OF_UPSTREAM counterparts. No functional change expected. This patch finalizes OF_UPSTREAM conversion of R8A779H0 V4M which DTs landed in Linux 6.9 . Signed-off-by: Marek Vasut Acked-by: Sumit Garg --- arch/arm/dts/Makefile | 3 - arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi | 166 ------- arch/arm/dts/r8a779h0-gray-hawk-csi-dsi.dtsi | 15 - arch/arm/dts/r8a779h0-gray-hawk-ethernet.dtsi | 15 - arch/arm/dts/r8a779h0-gray-hawk-u-boot.dtsi | 41 -- arch/arm/dts/r8a779h0-gray-hawk.dts | 25 - arch/arm/dts/r8a779h0-u-boot.dtsi | 27 - arch/arm/dts/r8a779h0.dtsi | 460 ------------------ 8 files changed, 752 deletions(-) delete mode 100644 arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi delete mode 100644 arch/arm/dts/r8a779h0-gray-hawk-csi-dsi.dtsi delete mode 100644 arch/arm/dts/r8a779h0-gray-hawk-ethernet.dtsi delete mode 100644 arch/arm/dts/r8a779h0-gray-hawk-u-boot.dtsi delete mode 100644 arch/arm/dts/r8a779h0-gray-hawk.dts delete mode 100644 arch/arm/dts/r8a779h0-u-boot.dtsi delete mode 100644 arch/arm/dts/r8a779h0.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f7032f1e175..6d5ff1bc27b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -958,9 +958,6 @@ dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \ imxrt1020-evk.dtb \ imxrt1170-evk.dtb \ -dtb-$(CONFIG_RCAR_GEN4) += \ - r8a779h0-gray-hawk.dtb - dtb-$(CONFIG_TARGET_RZG2L) += \ r9a07g044l2-smarc.dts diff --git a/arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi b/arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi deleted file mode 100644 index c8a46219826..00000000000 --- a/arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the Gray Hawk CPU board - * - * Copyright (C) 2023 Renesas Electronics Corp. - */ - -#include -#include - -#include "r8a779h0.dtsi" - -/ { - model = "Renesas Gray Hawk CPU board"; - compatible = "renesas,grayhawk-cpu", "renesas,r8a779h0"; - - aliases { - ethernet0 = &avb0; - serial0 = &hscif0; - }; - - chosen { - bootargs = "ignore_loglevel"; - stdout-path = "serial0:921600n8"; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@480000000 { - device_type = "memory"; - reg = <0x4 0x80000000 0x1 0x80000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&avb0 { - pinctrl-0 = <&avb0_pins>; - pinctrl-names = "default"; - phy-handle = <&phy0>; - tx-internal-delay-ps = <2000>; - status = "okay"; - - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id0022.1622", - "ethernet-phy-ieee802.3-c22"; - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio7>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; - }; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&hscif0 { - uart-has-rtscts; - status = "okay"; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - eeprom@50 { - compatible = "rohm,br24g01", "atmel,24c01"; - label = "cpu-board"; - reg = <0x50>; - pagesize = <8>; - }; -}; - -&mmc0 { - pinctrl-0 = <&mmc_pins>; - pinctrl-1 = <&mmc_pins>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - bus-width = <8>; - no-sd; - no-sdio; - non-removable; - full-pwr-cycle-in-suspend; - status = "okay"; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - avb0_pins: avb0 { - mux { - groups = "avb0_link", "avb0_mdio", "avb0_rgmii", - "avb0_txcrefclk"; - function = "avb0"; - }; - - pins_mdio { - groups = "avb0_mdio"; - drive-strength = <21>; - }; - - pins_mii { - groups = "avb0_rgmii"; - drive-strength = <21>; - }; - }; - - hscif0_pins: hscif0 { - groups = "hscif0_data", "hscif0_ctrl"; - function = "hscif0"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - mmc_pins: mmc { - groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; - function = "mmc"; - power-source = <1800>; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; -}; - -&scif_clk { - clock-frequency = <24000000>; -}; diff --git a/arch/arm/dts/r8a779h0-gray-hawk-csi-dsi.dtsi b/arch/arm/dts/r8a779h0-gray-hawk-csi-dsi.dtsi deleted file mode 100644 index fcdd8eb8d54..00000000000 --- a/arch/arm/dts/r8a779h0-gray-hawk-csi-dsi.dtsi +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the R-Car V4M Gray Hawk CSI/DSI sub-board - * - * Copyright (C) 2023 Renesas Electronics Corp. - */ - -&i2c0 { - eeprom@52 { - compatible = "rohm,br24g01", "atmel,24c01"; - label = "csi-dsi-sub-board-id"; - reg = <0x52>; - pagesize = <8>; - }; -}; diff --git a/arch/arm/dts/r8a779h0-gray-hawk-ethernet.dtsi b/arch/arm/dts/r8a779h0-gray-hawk-ethernet.dtsi deleted file mode 100644 index 5a8e598c986..00000000000 --- a/arch/arm/dts/r8a779h0-gray-hawk-ethernet.dtsi +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the R-Car V4M Gray Hawk Ethernet sub-board - * - * Copyright (C) 2023 Renesas Electronics Corp. - */ - -&i2c0 { - eeprom@53 { - compatible = "rohm,br24g01", "atmel,24c01"; - label = "ethernet-sub-board-id"; - reg = <0x53>; - pagesize = <8>; - }; -}; diff --git a/arch/arm/dts/r8a779h0-gray-hawk-u-boot.dtsi b/arch/arm/dts/r8a779h0-gray-hawk-u-boot.dtsi deleted file mode 100644 index 92c13151613..00000000000 --- a/arch/arm/dts/r8a779h0-gray-hawk-u-boot.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot for the Gray Hawk board - * - * Copyright (C) 2023 Renesas Electronics Corp. - */ - -#include "r8a779h0-u-boot.dtsi" - -/ { - aliases { - spi0 = &rpc; - }; -}; - -&pfc { - qspi0_pins: qspi0 { - groups = "qspi0_ctrl", "qspi0_data4"; - function = "qspi0"; - }; -}; - -&rpc { - pinctrl-0 = <&qspi0_pins>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - spi-max-frequency = <40000000>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "s25fs512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; - }; -}; diff --git a/arch/arm/dts/r8a779h0-gray-hawk.dts b/arch/arm/dts/r8a779h0-gray-hawk.dts deleted file mode 100644 index 59e5e493ad1..00000000000 --- a/arch/arm/dts/r8a779h0-gray-hawk.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the Gray Hawk CPU and BreakOut boards - * - * Copyright (C) 2023 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a779h0-gray-hawk-cpu.dtsi" -#include "r8a779h0-gray-hawk-csi-dsi.dtsi" -#include "r8a779h0-gray-hawk-ethernet.dtsi" - -/ { - model = "Renesas Gray Hawk CPU and Breakout boards based on r8a779h0"; - compatible = "renesas,gray-hawk-breakout", "renesas,gray-hawk-cpu", "renesas,r8a779h0"; -}; - -&i2c0 { - eeprom@51 { - compatible = "rohm,br24g01", "atmel,24c01"; - label = "breakout-board"; - reg = <0x51>; - pagesize = <8>; - }; -}; diff --git a/arch/arm/dts/r8a779h0-u-boot.dtsi b/arch/arm/dts/r8a779h0-u-boot.dtsi deleted file mode 100644 index b2f7e054eef..00000000000 --- a/arch/arm/dts/r8a779h0-u-boot.dtsi +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car R8A779H0 SoC - * - * Copyright (C) 2023 Renesas Electronics Corp. - */ - -#include "r8a779x-u-boot.dtsi" -/ { - soc { - rpc: spi@ee200000 { - compatible = "renesas,r8a779h0-rpc-if", "renesas,rcar-gen4-rpc-if"; - reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>; - interrupts = ; - clocks = <&cpg CPG_MOD 629>; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 629>; - bank-width = <2>; - num-cs = <1>; - status = "disabled"; - }; - }; -}; - -&extalr_clk { - bootph-all; -}; diff --git a/arch/arm/dts/r8a779h0.dtsi b/arch/arm/dts/r8a779h0.dtsi deleted file mode 100644 index a896bc27f5a..00000000000 --- a/arch/arm/dts/r8a779h0.dtsi +++ /dev/null @@ -1,460 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the R-Car V4M (R8A779H0) SoC - * - * Copyright (C) 2023 Renesas Electronics Corp. - */ - -#include -#include -#include - -/ { - compatible = "renesas,r8a779h0"; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a76_0: cpu@0 { - compatible = "arm,cortex-a76"; - reg = <0>; - device_type = "cpu"; - power-domains = <&sysc R8A779H0_PD_A1E0D0C0>; - }; - }; - - extal_clk: extal-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - pmu-a76 { - compatible = "arm,cortex-a76-pmu"; - interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc: soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - pfc: pinctrl@e6050000 { - compatible = "renesas,pfc-r8a779h0"; - reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, - <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, - <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, - <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>; - }; - - gpio0: gpio@e6050180 { - compatible = "renesas,gpio-r8a779h0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6050180 0 0x54>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 19>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 915>; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 915>; - }; - - gpio1: gpio@e6050980 { - compatible = "renesas,gpio-r8a779h0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6050980 0 0x54>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 30>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 915>; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 915>; - }; - - gpio2: gpio@e6058180 { - compatible = "renesas,gpio-r8a779h0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6058180 0 0x54>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 20>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 916>; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 916>; - }; - - gpio3: gpio@e6058980 { - compatible = "renesas,gpio-r8a779h0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6058980 0 0x54>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 916>; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 916>; - }; - - gpio4: gpio@e6060180 { - compatible = "renesas,gpio-r8a779h0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6060180 0 0x54>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 25>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 917>; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 917>; - }; - - gpio5: gpio@e6060980 { - compatible = "renesas,gpio-r8a779h0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6060980 0 0x54>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 21>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 917>; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 917>; - }; - - gpio6: gpio@e6061180 { - compatible = "renesas,gpio-r8a779h0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6061180 0 0x54>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 21>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 917>; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 917>; - }; - - gpio7: gpio@e6061980 { - compatible = "renesas,gpio-r8a779h0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6061980 0 0x54>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 21>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 917>; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 917>; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a779h0-cpg-mssr"; - reg = <0 0xe6150000 0 0x4000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a779h0-rst"; - reg = <0 0xe6160000 0 0x4000>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a779h0-sysc"; - reg = <0 0xe6180000 0 0x4000>; - #power-domain-cells = <1>; - }; - - i2c0: i2c@e6500000 { - compatible = "renesas,i2c-r8a779h0", - "renesas,rcar-gen4-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 518>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - compatible = "renesas,i2c-r8a779h0", - "renesas,rcar-gen4-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 519>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - compatible = "renesas,i2c-r8a779h0", - "renesas,rcar-gen4-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 520>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - compatible = "renesas,i2c-r8a779h0", - "renesas,rcar-gen4-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 521>; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 521>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a779h0", - "renesas,rcar-gen4-hscif", "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 514>, - <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 514>; - status = "disabled"; - }; - - avb0: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a779h0", - "renesas,etheravb-rcar-gen4"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 211>; - power-domains = <&sysc R8A779H0_PD_C4>; - resets = <&cpg 211>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - tx-internal-delay-ps = <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - avb1: ethernet@e6810000 { - compatible = "renesas,etheravb-r8a779h0", - "renesas,etheravb-rcar-gen4"; - reg = <0 0xe6810000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 212>; - power-domains = <&sysc R8A779H0_PD_C4>; - resets = <&cpg 212>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - tx-internal-delay-ps = <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - avb2: ethernet@e6820000 { - compatible = "renesas,etheravb-r8a779h0", - "renesas,etheravb-rcar-gen4"; - reg = <0 0xe6820000 0 0x1000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 213>; - power-domains = <&sysc R8A779H0_PD_C4>; - resets = <&cpg 213>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - tx-internal-delay-ps = <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mmc0: mmc@ee140000 { - compatible = "renesas,sdhi-r8a779h0", - "renesas,rcar-gen4-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 706>, - <&cpg CPG_CORE R8A779H0_CLK_SD0H>; - clock-names = "core", "clkh"; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 706>; - max-frequency = <200000000>; - status = "disabled"; - }; - - gic: interrupt-controller@f1000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1000000 0 0x20000>, - <0x0 0xf1060000 0 0x110000>; - interrupts = ; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; - }; -}; From 3ca48ec85d15759d875d42cc318c3e8ae8cde514 Mon Sep 17 00:00:00 2001 From: Emanuele Ghidoli Date: Tue, 28 May 2024 11:59:37 +0200 Subject: [PATCH 076/383] board: toradex: verdin-imx8mm: add 4 GB lpddr4 memory support Add support for MT53E512M32D1ZW-046 IT:C memory. This 4 GB memory has 17 row bits instead of 16 and requires 380 ns of tRFC (tRFCab) instead of 280 ns due to increased channel density to 16 Gb. Both modifications are retro-compatible with previous memories. Signed-off-by: Emanuele Ghidoli --- board/toradex/verdin-imx8mm/lpddr4_timing.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/board/toradex/verdin-imx8mm/lpddr4_timing.c b/board/toradex/verdin-imx8mm/lpddr4_timing.c index 4dfec679b11..eece226b513 100644 --- a/board/toradex/verdin-imx8mm/lpddr4_timing.c +++ b/board/toradex/verdin-imx8mm/lpddr4_timing.c @@ -18,7 +18,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d400000, 0xa1080020}, {0x3d400020, 0x202}, {0x3d400024, 0x3a980}, - {0x3d400064, 0x2d00d2}, + {0x3d400064, 0x2d011d}, {0x3d4000d0, 0xc00305ba}, {0x3d4000d4, 0x940000}, {0x3d4000dc, 0xd4002d}, @@ -34,7 +34,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d40011c, 0x402}, {0x3d400130, 0x20600}, {0x3d400134, 0xc100002}, - {0x3d400138, 0xd8}, + {0x3d400138, 0x123}, {0x3d400144, 0x96004b}, {0x3d400180, 0x2ee0017}, {0x3d400184, 0x2605b8e}, @@ -56,7 +56,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d400204, 0x80808}, {0x3d400214, 0x7070707}, {0x3d400218, 0x7070707}, - {0x3d40021c, 0xf0f}, + {0x3d40021c, 0xf07}, {0x3d400250, 0x29001701}, {0x3d400254, 0x2c}, {0x3d40025c, 0x4000030}, @@ -71,7 +71,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d402020, 0x0}, {0x3d402024, 0x7d00}, {0x3d402050, 0x20d040}, - {0x3d402064, 0x6001c}, + {0x3d402064, 0x60026}, {0x3d4020dc, 0x840000}, {0x3d4020e0, 0x310000}, {0x3d4020e8, 0x66004d}, @@ -86,7 +86,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d40211c, 0x302}, {0x3d402130, 0x20300}, {0x3d402134, 0xa100002}, - {0x3d402138, 0x1d}, + {0x3d402138, 0x27}, {0x3d402144, 0x14000a}, {0x3d402180, 0x640004}, {0x3d402190, 0x3818200}, @@ -96,7 +96,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d403020, 0x0}, {0x3d403024, 0x1f40}, {0x3d403050, 0x20d040}, - {0x3d403064, 0x30007}, + {0x3d403064, 0x3000A}, {0x3d4030dc, 0x840000}, {0x3d4030e0, 0x310000}, {0x3d4030e8, 0x66004d}, @@ -111,7 +111,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d40311c, 0x302}, {0x3d403130, 0x20300}, {0x3d403134, 0xa100002}, - {0x3d403138, 0x8}, + {0x3d403138, 0xA}, {0x3d403144, 0x50003}, {0x3d403180, 0x190004}, {0x3d403190, 0x3818200}, From 2884e5df697b49c98b8766b5f1964d6573eadfe5 Mon Sep 17 00:00:00 2001 From: Emanuele Ghidoli Date: Tue, 28 May 2024 11:59:38 +0200 Subject: [PATCH 077/383] board: toradex: verdin-imx8mm: increase maximum addressable ram to 4GB Add support for SKUs with higher memory sizes. Actual memory size is auto-detected. Signed-off-by: Emanuele Ghidoli --- board/toradex/verdin-imx8mm/verdin-imx8mm.c | 2 +- include/configs/verdin-imx8mm.h | 6 ++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index 020ee677480..3659316e23b 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -117,7 +117,7 @@ int board_phys_sdram_size(phys_size_t *size) if (!size) return -EINVAL; - *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE); return 0; } diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 34238d3b505..12d2b682305 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -58,8 +58,10 @@ #define CFG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ -#define PHYS_SDRAM 0x40000000 -#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE (long)(SZ_2G + SZ_1G) +#define PHYS_SDRAM_2 0x100000000 +#define PHYS_SDRAM_2_SIZE (long)(SZ_1G) /* USB Configs */ #define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) From 76a24b0f106f18b40f17295eb9570aed2002cca4 Mon Sep 17 00:00:00 2001 From: Emanuele Ghidoli Date: Tue, 28 May 2024 11:59:39 +0200 Subject: [PATCH 078/383] toradex: tdx-cfg-block: add aquila am69 sku 0088 pid4 Add new PID4 0088 Aquila AM69 Octa 32GB WB IT to config block handling. Signed-off-by: Emanuele Ghidoli --- board/toradex/common/tdx-cfg-block.c | 1 + board/toradex/common/tdx-cfg-block.h | 1 + 2 files changed, 2 insertions(+) diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 2225cefec16..16e897d1463 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -158,6 +158,7 @@ const struct toradex_som toradex_modules[] = { [85] = { "Apalis iMX6Q 2GB IT", TARGET_IS_ENABLED(APALIS_IMX6) }, [86] = { "Verdin iMX8M Mini DualLite 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, [87] = { "Verdin iMX8M Mini Quad 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, + [88] = { "Aquila AM69 Octa 32GB WB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, }; struct pid4list { diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index 183ee0f2dc9..277f8bc6bb4 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -113,6 +113,7 @@ enum { APALIS_IMX6Q_IT_NOWINCE, /* 85 */ VERDIN_IMX8MMDL_2G_IT, VERDIN_IMX8MMQ_2G_IT_NO_CAN, + AQUILA_AM69O_32G_WIFI_BT_IT, }; enum { From ce53f46f33b43f550e47ca50d7827f5b7b6d2ca5 Mon Sep 17 00:00:00 2001 From: Emanuele Ghidoli Date: Tue, 28 May 2024 11:59:40 +0200 Subject: [PATCH 079/383] toradex: tdx-cfg-block: add verdin imx95 sku 0089 pid4 Add new PID4 0089 Verdin iMX95 Hexa 16GB WB IT to config block handling. Signed-off-by: Emanuele Ghidoli --- board/toradex/common/tdx-cfg-block.c | 1 + board/toradex/common/tdx-cfg-block.h | 1 + 2 files changed, 2 insertions(+) diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 16e897d1463..941653a4e38 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -159,6 +159,7 @@ const struct toradex_som toradex_modules[] = { [86] = { "Verdin iMX8M Mini DualLite 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, [87] = { "Verdin iMX8M Mini Quad 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, [88] = { "Aquila AM69 Octa 32GB WB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, + [89] = { "Verdin iMX95 Hexa 16GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX95) }, }; struct pid4list { diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index 277f8bc6bb4..122a7aceabd 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -114,6 +114,7 @@ enum { VERDIN_IMX8MMDL_2G_IT, VERDIN_IMX8MMQ_2G_IT_NO_CAN, AQUILA_AM69O_32G_WIFI_BT_IT, + VERDIN_IMX95H_16G_WIFI_BT_IT, }; enum { From a4e37613bd06e0496e0ee2d162573702d22cf69b Mon Sep 17 00:00:00 2001 From: Emanuele Ghidoli Date: Tue, 28 May 2024 11:59:41 +0200 Subject: [PATCH 080/383] toradex: tdx-cfg-block: add verdin i.mx8m mini 0090 pid4 Add new PID4 0090 Verdin iMX8M Mini Quad 4GB WB ET to support the new hardware variant. Signed-off-by: Emanuele Ghidoli --- board/toradex/common/tdx-cfg-block.c | 1 + board/toradex/common/tdx-cfg-block.h | 1 + board/toradex/verdin-imx8mm/verdin-imx8mm.c | 3 ++- 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 941653a4e38..a6e3c6afae8 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -160,6 +160,7 @@ const struct toradex_som toradex_modules[] = { [87] = { "Verdin iMX8M Mini Quad 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, [88] = { "Aquila AM69 Octa 32GB WB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, [89] = { "Verdin iMX95 Hexa 16GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX95) }, + [90] = { "Verdin iMX8M Mini Quad 4GB WB ET", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, }; struct pid4list { diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index 122a7aceabd..0d6dd1c3a72 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -115,6 +115,7 @@ enum { VERDIN_IMX8MMQ_2G_IT_NO_CAN, AQUILA_AM69O_32G_WIFI_BT_IT, VERDIN_IMX95H_16G_WIFI_BT_IT, + VERDIN_IMX8MMQ_4G_WIFI_BT_ET, /* 90 */ }; enum { diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index 3659316e23b..4230f417d19 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -84,7 +84,8 @@ static void select_dt_from_module_version(void) */ is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT) || (tdx_hw_tag.prodid == VERDIN_IMX8MMDL_WIFI_BT_IT) || - (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN); + (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN) || + (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_4G_WIFI_BT_ET); } switch (get_pcb_revision()) { From c16aa668fd9fc8e98c74e19cd7cd95aef3873dbd Mon Sep 17 00:00:00 2001 From: Yannic Moog Date: Tue, 28 May 2024 13:24:59 +0200 Subject: [PATCH 081/383] arm: imx8mm-phycore: move to OF_UPSTREAM The PHYCORE_IMX8MM is used by the phyBOARD-Polis and the phyGATE-Tauri-L. Migrate both boards to OF_UPSTREAM. Linux kernel device trees for both boards can be used as is, corresponding U-Boot device tree files are removed. U-Boot tweaks are kept unchanged. Signed-off-by: Yannic Moog Reviewed-by: Fabio Estevam Acked-by: Teresa Remmet --- arch/arm/dts/Makefile | 2 - arch/arm/dts/imx8mm-phyboard-polis-rdk.dts | 460 ------------------- arch/arm/dts/imx8mm-phycore-som.dtsi | 440 ------------------ arch/arm/dts/imx8mm-phygate-tauri-l.dts | 489 --------------------- arch/arm/mach-imx/imx8m/Kconfig | 1 + board/phytec/phycore_imx8mm/MAINTAINERS | 3 - configs/imx8mm-phygate-tauri-l_defconfig | 2 +- configs/phycore-imx8mm_defconfig | 2 +- 8 files changed, 3 insertions(+), 1396 deletions(-) delete mode 100644 arch/arm/dts/imx8mm-phyboard-polis-rdk.dts delete mode 100644 arch/arm/dts/imx8mm-phycore-som.dtsi delete mode 100644 arch/arm/dts/imx8mm-phygate-tauri-l.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f7032f1e175..6f0ef4c5602 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -926,8 +926,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-kontron-bl-osm-s.dtb \ imx8mm-mx8menlo.dtb \ imx8mm-phg.dtb \ - imx8mm-phyboard-polis-rdk.dtb \ - imx8mm-phygate-tauri-l.dtb \ imx8mn-bsh-smm-s2.dtb \ imx8mn-bsh-smm-s2pro.dtb \ imx8mq-cm.dtb \ diff --git a/arch/arm/dts/imx8mm-phyboard-polis-rdk.dts b/arch/arm/dts/imx8mm-phyboard-polis-rdk.dts deleted file mode 100644 index 03e7679217b..00000000000 --- a/arch/arm/dts/imx8mm-phyboard-polis-rdk.dts +++ /dev/null @@ -1,460 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2022 PHYTEC Messtechnik GmbH - * Author: Teresa Remmet - */ - -/dts-v1/; - -#include -#include -#include -#include "imx8mm-phycore-som.dtsi" - -/ { - model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK"; - compatible = "phytec,imx8mm-phyboard-polis-rdk", - "phytec,imx8mm-phycore-som", "fsl,imx8mm"; - - chosen { - stdout-path = &uart3; - }; - - bt_osc_32k: bt-lp-clock { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "bt_osc_32k"; - #clock-cells = <0>; - }; - - can_osc_40m: can-clock { - compatible = "fixed-clock"; - clock-frequency = <40000000>; - clock-output-names = "can_osc_40m"; - #clock-cells = <0>; - }; - - fan { - compatible = "gpio-fan"; - gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0 - 13000 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fan>; - #cooling-cells = <2>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-0 { - color = ; - function = LED_FUNCTION_DISK; - gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc2"; - }; - - led-1 { - color = ; - function = LED_FUNCTION_DISK; - gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - }; - - led-2 { - color = ; - function = LED_FUNCTION_CPU; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - usdhc1_pwrseq: pwr-seq { - compatible = "mmc-pwrseq-simple"; - post-power-on-delay-ms = <100>; - power-off-delay-us = <60>; - reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; - }; - - reg_can_en: regulator-can-en { - compatible = "regulator-fixed"; - gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_en>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "CAN_EN"; - startup-delay-us = <20>; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1 { - compatible = "regulator-fixed"; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1pwrgrp>; - regulator-name = "usb_otg1_vbus"; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - off-on-delay-us = <20000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "VSD_3V3"; - }; - - reg_vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "VCC_3V3"; - }; -}; - -/* SPI - CAN MCP251XFD */ -&ecspi1 { - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - can0: can@0 { - compatible = "microchip,mcp251xfd"; - clocks = <&can_osc_40m>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_int>; - reg = <0>; - spi-max-frequency = <20000000>; - xceiver-supply = <®_can_en>; - }; -}; - -&gpio1 { - gpio-line-names = "nINT_ETHPHY", "LED_RED", "WDOG_INT", "X_RTC_INT", - "", "", "", "RESET_ETHPHY", - "CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "", - "USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE"; -}; - -&gpio2 { - gpio-line-names = "", "", "", "", - "", "", "BT_REG_ON", "WL_REG_ON", - "BT_DEV_WAKE", "BT_HOST_WAKE", "", "", - "X_SD2_CD_B", "", "", "", - "", "", "", "SD2_RESET_B"; -}; - -&gpio4 { - gpio-line-names = "", "", "", "", - "", "", "", "", - "FAN", "miniPCIe_nPERST", "", "", - "COEX1", "COEX2"; -}; - -&gpio5 { - gpio-line-names = "", "", "", "", - "", "", "", "", - "", "ECSPI1_SS0"; -}; - -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; -}; - -/* PCIe */ -&pcie0 { - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_250M>; - assigned-clock-rates = <10000000>, <250000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pcie_phy { - clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; - fsl,clkreq-unsupported; - fsl,refclk-pad-mode = ; - fsl,tx-deemph-gen1 = <0x2d>; - fsl,tx-deemph-gen2 = <0xf>; - status = "okay"; -}; - -&rv3028 { - trickle-resistor-ohms = <3000>; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -/* UART - RS232/RS485 */ -&uart1 { - assigned-clocks = <&clk IMX8MM_CLK_UART1>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -/* UART - Sterling-LWB Bluetooth */ -&uart2 { - assigned-clocks = <&clk IMX8MM_CLK_UART2>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; - fsl,dte-mode; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_bt>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&bt_osc_32k>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; - interrupt-names = "host-wakeup"; - interrupt-parent = <&gpio2>; - interrupts = <9 IRQ_TYPE_EDGE_BOTH>; - max-speed = <2000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bt>; - shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; - vddio-supply = <®_vcc_3v3>; - }; -}; - -/* UART - console */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -/* USB */ -&usbotg1 { - adp-disable; - dr_mode = "otg"; - over-current-active-low; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - srp-disable; - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - disable-over-current; - dr_mode = "host"; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - status = "okay"; -}; - -/* SDIO - Sterling-LWB Wifi */ -&usdhc1 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; - assigned-clock-rates = <200000000>; - bus-width = <4>; - mmc-pwrseq = <&usdhc1_pwrseq>; - non-removable; - no-1-8-v; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - }; -}; - -/* SD-Card */ -&usdhc2 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - bus-width = <4>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - vmmc-supply = <®_usdhc2_vmmc>; - vqmmc-supply = <®_nvcc_sd2>; - status = "okay"; -}; - -&iomuxc { - pinctrl_bt: btgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00 - MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00 - MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00 - >; - }; - - pinctrl_can_en: can-engrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00 - >; - }; - - pinctrl_can_int: can-intgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x80 - MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x80 - MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x80 - MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00 - >; - }; - - pinctrl_fan: fan0grp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2 - >; - }; - - pinctrl_leds: leds1grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16 - MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16 - MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x00 - MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12 - MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x12 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00 - MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x00 - MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x00 - MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x00 - >; - }; - - pinctrl_uart2_bt: uart2btgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x00 - MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x00 - MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x00 - MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x00 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40 - >; - }; - - pinctrl_usbotg1pwrgrp: usbotg1pwrgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - >; - }; - - pinctrl_wlan: wlangrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-phycore-som.dtsi b/arch/arm/dts/imx8mm-phycore-som.dtsi deleted file mode 100644 index 92616bc4f71..00000000000 --- a/arch/arm/dts/imx8mm-phycore-som.dtsi +++ /dev/null @@ -1,440 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2022 PHYTEC Messtechnik GmbH - * Author: Teresa Remmet - */ - -#include "imx8mm.dtsi" -#include - -/ { - model = "PHYTEC phyCORE-i.MX8MM"; - compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm"; - - aliases { - rtc0 = &rv3028; - rtc1 = &snvs_rtc; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - reg_vdd_3v3_s: regulator-vdd-3v3-s { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "VDD_3V3_S"; - }; -}; - -&A53_0 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_1 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_2 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_3 { - cpu-supply = <®_vdd_arm>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25000000 { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750000000 { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - -/* Ethernet */ -&fec1 { - fsl,magic-packet; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - enet-phy-lane-no-swap; - ti,clk-output-sel = ; - ti,fifo-depth = ; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - reg = <0>; - reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - reset-assert-us = <1000>; - reset-deassert-us = <1000>; - }; - }; -}; - -/* SPI Flash */ -&flexspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi0>; - status = "okay"; - - som_flash: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <80000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - }; -}; - -&gpio1 { - gpio-line-names = "nINT_ETHPHY", "", "WDOG_INT", "X_RTC_INT", - "", "", "", "RESET_ETHPHY", - "", "", "nENABLE_FLATLINK"; -}; - -/* I2C1 */ -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default","gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - pmic@8 { - compatible = "nxp,pf8121a"; - reg = <0x08>; - - regulators { - reg_nvcc_sd1: ldo1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "NVCC_SD1 (LDO1)"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - reg_nvcc_sd2: ldo2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1800000>; - regulator-name = "NVCC_SD2 (LDO2)"; - vselect-en; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - reg_vcc_enet: ldo3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <2500000>; - regulator-min-microvolt = <1500000>; - regulator-name = "VCC_ENET_2V5 (LDO3)"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - reg_vdda_1v8: ldo4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1500000>; - regulator-name = "VDDA_1V8 (LDO4)"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-min-microvolt = <1500000>; - regulator-suspend-max-microvolt = <1500000>; - }; - }; - - reg_soc_vdda_phy: buck1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <900000>; - regulator-min-microvolt = <400000>; - regulator-name = "VDD_SOC_VDDA_PHY_0P8 (BUCK1)"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-min-microvolt = <400000>; - regulator-suspend-max-microvolt = <400000>; - }; - }; - - reg_vdd_gpu_dram: buck2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1000000>; - regulator-min-microvolt = <1000000>; - regulator-name = "VDD_GPU_DRAM (BUCK2)"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <1000000>; - regulator-suspend-min-microvolt = <1000000>; - }; - }; - - reg_vdd_gpu: buck3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1000000>; - regulator-min-microvolt = <400000>; - regulator-name = "VDD_VPU (BUCK3)"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - reg_vdd_mipi: buck4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1050000>; - regulator-min-microvolt = <900000>; - regulator-name = "VDD_MIPI_0P9 (BUCK4)"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - reg_vdd_arm: buck5 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1050000>; - regulator-min-microvolt = <400000>; - regulator-name = "VDD_ARM (BUCK5)"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - reg_vdd_1v8: buck6 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "VDD_1V8 (BUCK6)"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <1800000>; - regulator-suspend-min-microvolt = <1800000>; - }; - }; - - reg_nvcc_dram: buck7 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1100000>; - regulator-min-microvolt = <1100000>; - regulator-name = "NVCC_DRAM_1P1V (BUCK7)"; - }; - - reg_vsnvs: vsnvs { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "NVCC_SNVS_1P8 (VSNVS)"; - }; - }; - }; - - sn65dsi83: bridge@2d { - compatible = "ti,sn65dsi83"; - enable-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sn65dsi83>; - reg = <0x2d>; - status = "disabled"; - }; - - eeprom@51 { - compatible = "atmel,24c32"; - pagesize = <32>; - reg = <0x51>; - vcc-supply = <®_vdd_3v3_s>; - }; - - rv3028: rtc@52 { - compatible = "microcrystal,rv3028"; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc>; - reg = <0x52>; - }; -}; - -/* EMMC */ -&usdhc3 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - keep-power-in-suspend; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - non-removable; - status = "okay"; -}; - -/* Watchdog */ -&wdog1 { - fsl,ext-reset-output; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x2 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90 - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90 - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90 - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16 - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16 - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16 - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x10 - >; - }; - - pinctrl_flexspi0: flexspi0grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 - MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 - MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 - MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 - MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 - MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c0 - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c0 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1e0 - MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1e0 - >; - }; - - pinctrl_rtc: rtcgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 - >; - }; - - pinctrl_sn65dsi83: sn65dsi83grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x26 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-phygate-tauri-l.dts b/arch/arm/dts/imx8mm-phygate-tauri-l.dts deleted file mode 100644 index 968f475b9a9..00000000000 --- a/arch/arm/dts/imx8mm-phygate-tauri-l.dts +++ /dev/null @@ -1,489 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 PHYTEC Messtechnik GmbH - */ - -/dts-v1/; - -#include -#include -#include "imx8mm-phycore-som.dtsi" - -/ { - model = "PHYTEC phyGATE-Tauri-L-iMX8MM"; - compatible = "phytec,imx8mm-phygate-tauri-l", - "phytec,imx8mm-phycore-som", "fsl,imx8mm"; - - chosen { - stdout-path = &uart3; - }; - - can_osc_40m: clock-can { - compatible = "fixed-clock"; - clock-frequency = <40000000>; - clock-output-names = "can_osc_40m"; - #clock-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - - key { - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - label = "KEY-A"; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-1 { - color = ; - gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - }; - - led-2 { - color = ; - gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - }; - }; - - usdhc1_pwrseq: pwr-seq { - compatible = "mmc-pwrseq-simple"; - post-power-on-delay-ms = <100>; - power-off-delay-us = <60>; - reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; - }; - - reg_usb_hub_vbus: regulator-hub-otg1 { - compatible = "regulator-fixed"; - gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbhubpwr>; - regulator-name = "usb_hub_vbus"; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1 { - compatible = "regulator-fixed"; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1pwr>; - regulator-name = "usb_otg1_vbus"; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - off-on-delay-us = <20000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "VSD_3V3"; - }; -}; - -&ecspi1 { - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, - <&gpio5 13 GPIO_ACTIVE_LOW>, - <&gpio5 2 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - /* CAN MCP251XFD */ - can0: can@0 { - compatible = "microchip,mcp251xfd"; - reg = <0>; - clocks = <&can_osc_40m>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_int>; - spi-max-frequency = <10000000>; - }; - - tpm: tpm@1 { - compatible = "tcg,tpm_tis-spi"; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tpm>; - reg = <1>; - spi-max-frequency = <38000000>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - temp_sense0: temperature-sensor@49 { - compatible = "ti,tmp102"; - reg = <0x49>; - interrupt-parent = <&gpio4>; - interrupts = <31 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tempsense>; - #thermal-sensor-cells = <1>; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4_gpio>; - scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -/* PCIe */ -&pcie0 { - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_PHY>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_100M>, - <&clk IMX8MM_SYS_PLL2_250M>; - assigned-clock-rates = <10000000>, <100000000>, <250000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -/* RTC */ -&rv3028 { - trickle-resistor-ohms = <3000>; -}; - -&uart1 { - assigned-clocks = <&clk IMX8MM_CLK_UART1>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* UART2 - RS232 */ -&uart2 { - assigned-clocks = <&clk IMX8MM_CLK_UART2>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -/* UART - console */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -/* USB */ -&usbotg1 { - adp-disable; - dr_mode = "otg"; - over-current-active-low; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - srp-disable; - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - disable-over-current; - dr_mode = "host"; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - vbus-supply = <®_usb_hub_vbus>; - status = "okay"; -}; - -/* SD-Card */ -&usdhc2 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - bus-width = <4>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - vmmc-supply = <®_usdhc2_vmmc>; - vqmmc-supply = <®_nvcc_sd2>; - status = "okay"; -}; - -&iomuxc { - pinctrl_can_int: can-intgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 - MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 - MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 - >; - }; - - pinctrl_ecspi1_cs: ecspi1csgrp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00 - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x00 - MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x00 - >; - }; - - pinctrl_gpiokeys: keygrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1e0 - MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1e0 - >; - }; - - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1e0 - MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1e0 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2 - >; - }; - - pinctrl_i2c4_gpio: i2c4gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1e0 - MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1e0 - >; - }; - - pinctrl_leds: leds1grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x00 - MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x00 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - /* COEX2 */ - MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x00 - /* COEX1 */ - MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x40 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x40 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x40 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 - >; - }; - - pinctrl_tempsense: tempsensegrp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x00 - >; - }; - - pinctrl_tpm: tpmgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x00 - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x00 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00 - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 - >; - }; - - pinctrl_usbhubpwr: usbhubpwrgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x00 - >; - }; - - pinctrl_usbotg1pwr: usbotg1pwrgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00 - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x80 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - >; - }; -}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 23d9217fcc2..f81be42d5b0 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -296,6 +296,7 @@ config TARGET_PHYCORE_IMX8MM select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 + imply OF_UPSTREAM config TARGET_PHYCORE_IMX8MP bool "PHYTEC PHYCORE i.MX8MP" diff --git a/board/phytec/phycore_imx8mm/MAINTAINERS b/board/phytec/phycore_imx8mm/MAINTAINERS index e46e3691bac..58c5e2d0af9 100644 --- a/board/phytec/phycore_imx8mm/MAINTAINERS +++ b/board/phytec/phycore_imx8mm/MAINTAINERS @@ -2,10 +2,7 @@ phyCORE-i.MX8M Mini M: Teresa Remmet W: https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-mini-nano/ S: Maintained -F: arch/arm/dts/imx8mm-phyboard-polis-rdk.dts -F: arch/arm/dts/imx8mm-phycore-som.dtsi F: arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi -F: arch/arm/dts/imx8mm-phygate-tauri-l.dts F: arch/arm/dts/imx8mm-phygate-tauri-l-u-boot.dtsi F: board/phytec/phycore_imx8mm/ F: configs/imx8mm-phygate-tauri-l_defconfig diff --git a/configs/imx8mm-phygate-tauri-l_defconfig b/configs/imx8mm-phygate-tauri-l_defconfig index cb292dde4cb..41765f1ddc5 100644 --- a/configs/imx8mm-phygate-tauri-l_defconfig +++ b/configs/imx8mm-phygate-tauri-l_defconfig @@ -8,7 +8,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x3C0000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mm-phygate-tauri-l" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-phygate-tauri-l" CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_PHYCORE_IMX8MM=y CONFIG_SYS_MONITOR_LEN=524288 diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index 22d419024f6..f9fd7255df7 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -9,7 +9,7 @@ CONFIG_SF_DEFAULT_SPEED=80000000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x3C0000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mm-phyboard-polis-rdk" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-phyboard-polis-rdk" CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_PHYCORE_IMX8MM=y CONFIG_SYS_MONITOR_LEN=524288 From 518c40dfa059bfcde78828898b133615efb4c402 Mon Sep 17 00:00:00 2001 From: Yannic Moog Date: Tue, 28 May 2024 13:25:00 +0200 Subject: [PATCH 082/383] arm: imx8mp-phycore: move to OF_UPSTREAM The PHYCORE_IMX8MP is used by the phyBOARD-Pollux. Migrate board to OF_UPSTREAM. Linux kernel device tree for the board can be used as is, corresponding U-Boot device tree files are removed. U-Boot tweaks are kept unchanged. Signed-off-by: Yannic Moog Reviewed-by: Fabio Estevam Acked-by: Teresa Remmet --- arch/arm/dts/Makefile | 1 - arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts | 361 -------------------- arch/arm/dts/imx8mp-phycore-som.dtsi | 323 ------------------ arch/arm/mach-imx/imx8m/Kconfig | 1 + board/phytec/phycore_imx8mp/MAINTAINERS | 1 - configs/phycore-imx8mp_defconfig | 2 +- 6 files changed, 2 insertions(+), 687 deletions(-) delete mode 100644 arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts delete mode 100644 arch/arm/dts/imx8mp-phycore-som.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 6f0ef4c5602..1fc36c0f01d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -943,7 +943,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mp-dhcom-pdk3-overlay-rev100.dtbo \ imx8mp-icore-mx8mp-edimm2.2.dtb \ imx8mp-msc-sm2s.dtb \ - imx8mp-phyboard-pollux-rdk.dtb \ imx8mq-pico-pi.dtb \ imx8mq-kontron-pitx-imx8m.dtb \ imx8mq-librem5-r4.dtb diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts b/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts deleted file mode 100644 index c8640cac3ed..00000000000 --- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts +++ /dev/null @@ -1,361 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020 PHYTEC Messtechnik GmbH - * Author: Teresa Remmet - */ - -/dts-v1/; - -#include -#include -#include "imx8mp-phycore-som.dtsi" - -/ { - model = "PHYTEC phyBOARD-Pollux i.MX8MP"; - compatible = "phytec,imx8mp-phyboard-pollux-rdk", - "phytec,imx8mp-phycore-som", "fsl,imx8mp"; - - chosen { - stdout-path = &uart1; - }; - - reg_can1_stby: regulator-can1-stby { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1_reg>; - gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "can1-stby"; - }; - - reg_can2_stby: regulator-can2-stby { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2_reg>; - gpio = <&gpio3 21 GPIO_ACTIVE_LOW>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "can2-stby"; - }; - - reg_usb1_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1_vbus>; - gpio = <&gpio1 12 GPIO_ACTIVE_LOW>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "usb1_host_vbus"; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100>; - off-on-delay-us = <12000>; - }; -}; - -&eqos { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - ti,clk-output-sel = ; - enet-phy-lane-no-swap; - }; - }; -}; - -/* CAN FD */ -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can1_stby>; - status = "okay"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_stby>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - leds@62 { - compatible = "nxp,pca9533"; - reg = <0x62>; - - led-1 { - type = ; - }; - - led-2 { - type = ; - }; - - led-3 { - type = ; - }; - }; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -/* debug console */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* USB1 Host mode Type-A */ -&usb3_phy0 { - vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&usb_dwc3_0 { - dr_mode = "host"; - status = "okay"; -}; - -/* USB2 4-port USB3.0 HUB */ -&usb3_phy1 { - status = "okay"; -}; - -&usb3_1 { - fsl,permanently-attached; - fsl,disable-port-power-control; - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -/* RS232/RS485 */ -&uart2 { - assigned-clocks = <&clk IMX8MP_CLK_UART2>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -/* SD-Card */ -&usdhc2 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - bus-width = <4>; - status = "okay"; -}; - -&gpio1 { - gpio-line-names = "", "", "X_PMIC_WDOG_B", "", - "PMIC_SD_VSEL", "", "", "", "", "", - "", "", "USB1_OTG_PWR", "", "", "X_nETHPHY_INT"; -}; - -&gpio2 { - gpio-line-names = "", "", "", "", - "", "", "", "", "", "", - "", "", "X_SD2_CD_B", "", "", "", - "", "", "", "SD2_RESET_B"; -}; - -&gpio3 { - gpio-line-names = "", "", "", "", - "", "", "", "", "", "", - "", "", "", "", "", "", - "", "", "", "", "nCAN1_EN", "nCAN2_EN"; -}; - -&gpio4 { - gpio-line-names = "", "", "", "", - "", "", "", "", "", "", - "", "", "", "", "", "", - "", "", "X_PMIC_IRQ_B", "", "nENET0_INT_PWDN"; -}; - -&iomuxc { - pinctrl_eqos: eqosgrp { - fsl,pins = < - MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 - MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 - MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 - MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 - MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 - MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 - MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 - MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 - MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154 - MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 - MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 - >; - }; - - pinctrl_flexcan1_reg: flexcan1reggrp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x154 - >; - }; - - pinctrl_flexcan2_reg: flexcan2reggrp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x154 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2 - MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40 - MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40 - >; - }; - - pinctrl_usb1_vbus: usb1vbusgrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x10 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 - MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x140 - MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x140 - >; - }; - - pinctrl_usdhc2_pins: usdhc2-gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-phycore-som.dtsi b/arch/arm/dts/imx8mp-phycore-som.dtsi deleted file mode 100644 index 79b290a002c..00000000000 --- a/arch/arm/dts/imx8mp-phycore-som.dtsi +++ /dev/null @@ -1,323 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020 PHYTEC Messtechnik GmbH - * Author: Teresa Remmet - */ - -#include -#include "imx8mp.dtsi" - -/ { - model = "PHYTEC phyCORE-i.MX8MP"; - compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp"; - - aliases { - rtc0 = &rv3028; - rtc1 = &snvs_rtc; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; -}; - -&A53_0 { - cpu-supply = <&buck2>; -}; - -&A53_1 { - cpu-supply = <&buck2>; -}; - -&A53_2 { - cpu-supply = <&buck2>; -}; - -&A53_3 { - cpu-supply = <&buck2>; -}; - -/* ethernet 1 */ -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy1>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - ti,clk-output-sel = ; - ti,min-output-impedance; - enet-phy-lane-no-swap; - }; - }; -}; - -&flexspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi0>; - status = "okay"; - - som_flash: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <80000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - pmic: pmic@25 { - reg = <0x25>; - compatible = "nxp,pca9450c"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio4>; - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; - - regulators { - buck1: BUCK1 { - regulator-compatible = "BUCK1"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - buck2: BUCK2 { - regulator-compatible = "BUCK2"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - }; - - buck4: BUCK4 { - regulator-compatible = "BUCK4"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5: BUCK5 { - regulator-compatible = "BUCK5"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6: BUCK6 { - regulator-compatible = "BUCK6"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: LDO1 { - regulator-compatible = "LDO1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2: LDO2 { - regulator-compatible = "LDO2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3: LDO3 { - regulator-compatible = "LDO3"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4: LDO4 { - regulator-compatible = "LDO4"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo5: LDO5 { - regulator-compatible = "LDO5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - pagesize = <32>; - }; - - rv3028: rtc@52 { - compatible = "microcrystal,rv3028"; - reg = <0x52>; - trickle-resistor-ohms = <3000>; - }; -}; - -/* eMMC */ -&usdhc3 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec: fecgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 - MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 - MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 - MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 - MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 - MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 - MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 - MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 - MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12 - MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12 - MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14 - MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14 - MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14 - MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14 - MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x11 - >; - }; - - pinctrl_flexspi0: flexspi0grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 - MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 - MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 - MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 - MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 - MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e3 - MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e3 - >; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x141 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xe6 - >; - }; -}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index f81be42d5b0..046c78547b2 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -303,6 +303,7 @@ config TARGET_PHYCORE_IMX8MP select IMX8MP select SUPPORT_SPL select IMX8M_LPDDR4 + imply OF_UPSTREAM config TARGET_IMX8MM_CL_IOT_GATE bool "CompuLab iot-gate-imx8" diff --git a/board/phytec/phycore_imx8mp/MAINTAINERS b/board/phytec/phycore_imx8mp/MAINTAINERS index d3beb978d3a..645476ae30a 100644 --- a/board/phytec/phycore_imx8mp/MAINTAINERS +++ b/board/phytec/phycore_imx8mp/MAINTAINERS @@ -2,7 +2,6 @@ phyCORE-i.MX8M Plus M: Teresa Remmet W: https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-plus/ S: Maintained -F: arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts F: arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi F: board/phytec/phycore_imx8mp/ F: configs/phycore-imx8mp_defconfig diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 9f42edd7232..7b16e8ef58e 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -9,7 +9,7 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x3C0000 CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mp-phyboard-pollux-rdk" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-phyboard-pollux-rdk" CONFIG_SPL_TEXT_BASE=0x920000 CONFIG_TARGET_PHYCORE_IMX8MP=y CONFIG_PHYTEC_SOM_DETECTION=y From 7d1895bd4bdb0788017555e4209bf030dcf39354 Mon Sep 17 00:00:00 2001 From: Teresa Remmet Date: Tue, 28 May 2024 15:35:12 +0200 Subject: [PATCH 083/383] board: phytec: phycore-imx8mp: spl: Fix syle issue Use tabs instead of spaces. Signed-off-by: Teresa Remmet --- board/phytec/phycore_imx8mp/spl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index 352f803e454..cffa0a57fe6 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -24,8 +24,8 @@ DECLARE_GLOBAL_DATA_PTR; -#define EEPROM_ADDR 0x51 -#define EEPROM_ADDR_FALLBACK 0x59 +#define EEPROM_ADDR 0x51 +#define EEPROM_ADDR_FALLBACK 0x59 int spl_board_boot_device(enum boot_device boot_dev_spl) { From cff451e03ff3c9612723c8ab2b8b5be525538936 Mon Sep 17 00:00:00 2001 From: Teresa Remmet Date: Tue, 28 May 2024 15:35:13 +0200 Subject: [PATCH 084/383] board: phytec: phycore_imx8mp: Add support for different RAM sizes Add support for different RAM sizes and speed grades on the phyCORE-i.MX8MP. Add support for 1GB 1.5GHz, 1GB 2GHz, 4GB 1.5GHz, 4GB 2GHz and 8GB 2GHz RAM. The RAM size and speed grade is detected by the information stored in the EEPROM on the SoM. Co-developed-by: Benjamin Hahn Signed-off-by: Benjamin Hahn Co-developed-by: Yannic Moog Signed-off-by: Yannic Moog Co-developed-by: Yashwanth Varakala Signed-off-by: Yashwanth Varakala Signed-off-by: Teresa Remmet --- board/phytec/phycore_imx8mp/lpddr4_timing.c | 153 +++++++++++++++++++ board/phytec/phycore_imx8mp/lpddr4_timing.h | 16 ++ board/phytec/phycore_imx8mp/phycore-imx8mp.c | 11 ++ board/phytec/phycore_imx8mp/spl.c | 100 +++++------- include/configs/phycore_imx8mp.h | 4 +- 5 files changed, 224 insertions(+), 60 deletions(-) create mode 100644 board/phytec/phycore_imx8mp/lpddr4_timing.h diff --git a/board/phytec/phycore_imx8mp/lpddr4_timing.c b/board/phytec/phycore_imx8mp/lpddr4_timing.c index f2707b85960..9984b6c2601 100644 --- a/board/phytec/phycore_imx8mp/lpddr4_timing.c +++ b/board/phytec/phycore_imx8mp/lpddr4_timing.c @@ -1839,3 +1839,156 @@ struct dram_timing_info dram_timing = { .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), .fsp_table = { 3000, 400, 100, }, }; + +void set_dram_timings_2ghz_2gb(void) +{ + dram_timing.ddrc_cfg[3].val = 0x1323; + dram_timing.ddrc_cfg[4].val = 0x1e84800; + dram_timing.ddrc_cfg[5].val = 0x7a0118; + dram_timing.ddrc_cfg[8].val = 0xc00307a3; + dram_timing.ddrc_cfg[9].val = 0xc50000; + dram_timing.ddrc_cfg[10].val = 0xf4003f; + dram_timing.ddrc_cfg[11].val = 0xf30000; + dram_timing.ddrc_cfg[14].val = 0x2028222a; + dram_timing.ddrc_cfg[15].val = 0x8083f; + dram_timing.ddrc_cfg[16].val = 0xe0e000; + dram_timing.ddrc_cfg[17].val = 0x12040a12; + dram_timing.ddrc_cfg[18].val = 0x2050f0f; + dram_timing.ddrc_cfg[19].val = 0x1010009; + dram_timing.ddrc_cfg[20].val = 0x502; + dram_timing.ddrc_cfg[21].val = 0x20800; + dram_timing.ddrc_cfg[22].val = 0xe100002; + dram_timing.ddrc_cfg[23].val = 0x120; + dram_timing.ddrc_cfg[24].val = 0xc80064; + dram_timing.ddrc_cfg[25].val = 0x3e8001e; + dram_timing.ddrc_cfg[26].val = 0x3207a12; + dram_timing.ddrc_cfg[28].val = 0x4a3820e; + dram_timing.ddrc_cfg[30].val = 0x230e; + dram_timing.ddrc_cfg[37].val = 0x799; + dram_timing.ddrc_cfg[38].val = 0x9141d1c; + dram_timing.ddrc_cfg[74].val = 0x302; + dram_timing.ddrc_cfg[83].val = 0x599; + dram_timing.ddrc_cfg[99].val = 0x302; + dram_timing.ddrc_cfg[108].val = 0x599; + dram_timing.ddrphy_cfg[66].val = 0x18; + dram_timing.ddrphy_cfg[75].val = 0x1e3; + dram_timing.ddrphy_cfg[77].val = 0x1e3; + dram_timing.ddrphy_cfg[79].val = 0x1e3; + dram_timing.ddrphy_cfg[145].val = 0x3e8; + dram_timing.fsp_msg[0].drate = 4000; + dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0; + dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4; + dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3; + dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4; + dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3; + dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400; + dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f; + dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400; + dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f; + dram_timing.fsp_msg[3].drate = 4000; + dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xfa0; + dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4; + dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3; + dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4; + dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3; + dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400; + dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f; + dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400; + dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f; + dram_timing.ddrphy_pie[480].val = 0x465; + dram_timing.ddrphy_pie[481].val = 0xfa; + dram_timing.ddrphy_pie[482].val = 0x9c4; + dram_timing.fsp_table[0] = 4000; +} + +void set_dram_timings_1_5ghz_1gb(void) +{ + dram_timing.ddrc_cfg[3].val = 0x1233; + dram_timing.ddrc_cfg[5].val = 0x5b0087; + dram_timing.ddrc_cfg[6].val = 0x61027f10; + dram_timing.ddrc_cfg[7].val = 0x7b0; + dram_timing.ddrc_cfg[11].val = 0xf30000; + dram_timing.ddrc_cfg[23].val = 0x8d; + dram_timing.ddrc_cfg[45].val = 0xf070707; + dram_timing.ddrc_cfg[59].val = 0x1031; + dram_timing.ddrc_cfg[62].val = 0xc0012; + dram_timing.ddrc_cfg[77].val = 0x13; + dram_timing.ddrc_cfg[84].val = 0x1031; + dram_timing.ddrc_cfg[87].val = 0x30005; + dram_timing.ddrc_cfg[102].val = 0x5; + dram_timing.ddrphy_cfg[75].val = 0x1e3; + dram_timing.ddrphy_cfg[77].val = 0x1e3; + dram_timing.ddrphy_cfg[79].val = 0x1e3; + dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3; + dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3; + dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf32d; + dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf32d; + dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3; + dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3; + dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf32d; + dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf32d; +} + +void set_dram_timings_2ghz_1gb(void) +{ + set_dram_timings_2ghz_2gb(); + dram_timing.ddrc_cfg[5].val = 0x7a00b4; + dram_timing.ddrc_cfg[23].val = 0xbc; + dram_timing.ddrc_cfg[45].val = 0xf070707; + dram_timing.ddrc_cfg[62].val = 0xc0012; + dram_timing.ddrc_cfg[77].val = 0x13; + dram_timing.ddrc_cfg[87].val = 0x30005; + dram_timing.ddrc_cfg[102].val = 0x5; +} + +void set_dram_timings_1_5ghz_4gb(void) +{ + dram_timing.ddrc_cfg[2].val = 0xa3080020; + dram_timing.ddrc_cfg[39].val = 0x17; + dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x310; + dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x3; + dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x3; + dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x3; + dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3; +} + +void set_dram_timings_2ghz_4gb(void) +{ + set_dram_timings_2ghz_2gb(); + dram_timing.ddrc_cfg[2].val = 0xa3080020; + dram_timing.ddrc_cfg[39].val = 0x17; + dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x310; + dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x3; + dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x3; + dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x3; + dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3; +} + +void set_dram_timings_2ghz_8gb(void) +{ + set_dram_timings_2ghz_2gb(); + dram_timing.ddrc_cfg[2].val = 0xa3080020; + dram_timing.ddrc_cfg[5].val = 0x7a017c; + dram_timing.ddrc_cfg[23].val = 0x184; + dram_timing.ddrc_cfg[39].val = 0x18; + dram_timing.ddrc_cfg[46].val = 0xf07; + dram_timing.ddrc_cfg[62].val = 0xc0026; + dram_timing.ddrc_cfg[77].val = 0x27; + dram_timing.ddrc_cfg[87].val = 0x3000a; + dram_timing.ddrc_cfg[102].val = 0xa; + + dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x310; + dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x3; + dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x3; + dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x3; + dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3; +} diff --git a/board/phytec/phycore_imx8mp/lpddr4_timing.h b/board/phytec/phycore_imx8mp/lpddr4_timing.h new file mode 100644 index 00000000000..1c10e085a92 --- /dev/null +++ b/board/phytec/phycore_imx8mp/lpddr4_timing.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + */ + +#ifndef __LPDDR4_TIMING_H__ +#define __LPDDR4_TIMING_H__ + +void set_dram_timings_2ghz_2gb(void); +void set_dram_timings_2ghz_1gb(void); +void set_dram_timings_2ghz_4gb(void); +void set_dram_timings_1_5ghz_1gb(void); +void set_dram_timings_1_5ghz_4gb(void); +void set_dram_timings_2ghz_8gb(void); + +#endif /* __LPDDR4_TIMING_H__ */ diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c b/board/phytec/phycore_imx8mp/phycore-imx8mp.c index 35683591433..ef951361844 100644 --- a/board/phytec/phycore_imx8mp/phycore-imx8mp.c +++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c @@ -9,6 +9,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -55,3 +56,13 @@ int board_late_init(void) return 0; } + +int board_phys_sdram_size(phys_size_t *size) +{ + if (!size) + return -EINVAL; + + *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE); + + return 0; +} diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index cffa0a57fe6..855aa1a9009 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -20,6 +20,7 @@ #include #include +#include "lpddr4_timing.h" #include "../common/imx8m_som_detection.h" DECLARE_GLOBAL_DATA_PTR; @@ -32,9 +33,19 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) return BOOT_DEVICE_BOOTROM; } +enum phytec_imx8mp_ddr_eeprom_code { + PHYTEC_IMX8MP_DDR_1GB = 2, + PHYTEC_IMX8MP_DDR_2GB = 3, + PHYTEC_IMX8MP_DDR_4GB = 5, + PHYTEC_IMX8MP_DDR_8GB = 7, + PHYTEC_IMX8MP_DDR_4GB_2GHZ = 8, +}; + void spl_dram_init(void) { int ret; + bool use_2ghz_timings = false; + enum phytec_imx8mp_ddr_eeprom_code size = PHYTEC_EEPROM_INVAL; ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR, EEPROM_ADDR_FALLBACK); @@ -48,67 +59,38 @@ void spl_dram_init(void) u8 rev = phytec_get_rev(NULL); u8 somtype = phytec_get_som_type(NULL); - if (rev != PHYTEC_EEPROM_INVAL && (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1))) { - dram_timing.ddrc_cfg[3].val = 0x1323; - dram_timing.ddrc_cfg[4].val = 0x1e84800; - dram_timing.ddrc_cfg[5].val = 0x7a0118; - dram_timing.ddrc_cfg[8].val = 0xc00307a3; - dram_timing.ddrc_cfg[9].val = 0xc50000; - dram_timing.ddrc_cfg[10].val = 0xf4003f; - dram_timing.ddrc_cfg[11].val = 0xf30000; - dram_timing.ddrc_cfg[14].val = 0x2028222a; - dram_timing.ddrc_cfg[15].val = 0x8083f; - dram_timing.ddrc_cfg[16].val = 0xe0e000; - dram_timing.ddrc_cfg[17].val = 0x12040a12; - dram_timing.ddrc_cfg[18].val = 0x2050f0f; - dram_timing.ddrc_cfg[19].val = 0x1010009; - dram_timing.ddrc_cfg[20].val = 0x502; - dram_timing.ddrc_cfg[21].val = 0x20800; - dram_timing.ddrc_cfg[22].val = 0xe100002; - dram_timing.ddrc_cfg[23].val = 0x120; - dram_timing.ddrc_cfg[24].val = 0xc80064; - dram_timing.ddrc_cfg[25].val = 0x3e8001e; - dram_timing.ddrc_cfg[26].val = 0x3207a12; - dram_timing.ddrc_cfg[28].val = 0x4a3820e; - dram_timing.ddrc_cfg[30].val = 0x230e; - dram_timing.ddrc_cfg[37].val = 0x799; - dram_timing.ddrc_cfg[38].val = 0x9141d1c; - dram_timing.ddrc_cfg[74].val = 0x302; - dram_timing.ddrc_cfg[83].val = 0x599; - dram_timing.ddrc_cfg[99].val = 0x302; - dram_timing.ddrc_cfg[108].val = 0x599; - dram_timing.ddrphy_cfg[66].val = 0x18; - dram_timing.ddrphy_cfg[75].val = 0x1e3; - dram_timing.ddrphy_cfg[77].val = 0x1e3; - dram_timing.ddrphy_cfg[79].val = 0x1e3; - dram_timing.ddrphy_cfg[145].val = 0x3e8; - dram_timing.fsp_msg[0].drate = 4000; - dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0; - dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4; - dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3; - dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4; - dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3; - dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400; - dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f; - dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400; - dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f; - dram_timing.fsp_msg[3].drate = 4000; - dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xfa0; - dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4; - dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3; - dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4; - dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3; - dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400; - dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f; - dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400; - dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f; - dram_timing.ddrphy_pie[480].val = 0x465; - dram_timing.ddrphy_pie[481].val = 0xfa; - dram_timing.ddrphy_pie[482].val = 0x9c4; - dram_timing.fsp_table[0] = 4000; - } + if (rev != PHYTEC_EEPROM_INVAL && (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1))) + use_2ghz_timings = true; + size = phytec_get_imx8m_ddr_size(NULL); + + switch (size) { + case PHYTEC_IMX8MP_DDR_1GB: + if (use_2ghz_timings) + set_dram_timings_2ghz_1gb(); + else + set_dram_timings_1_5ghz_1gb(); + break; + case PHYTEC_IMX8MP_DDR_2GB: + if (use_2ghz_timings) + set_dram_timings_2ghz_2gb(); + break; + case PHYTEC_IMX8MP_DDR_4GB: + set_dram_timings_1_5ghz_4gb(); + break; + case PHYTEC_IMX8MP_DDR_4GB_2GHZ: + set_dram_timings_2ghz_4gb(); + break; + case PHYTEC_IMX8MP_DDR_8GB: + set_dram_timings_2ghz_8gb(); + break; + default: + goto out; + } + ddr_init(&dram_timing); + return; out: + printf("Could not detect correct RAM size. Fallback to default.\n"); ddr_init(&dram_timing); } diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 206c4d50d27..299fabc6a99 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -22,6 +22,8 @@ #define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 -#define PHYS_SDRAM_SIZE 0x80000000 +#define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G) /* 3GB */ +#define PHYS_SDRAM_2 0x100000000 +#define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G) /* 5GB */ #endif /* __PHYCORE_IMX8MP_H */ From 8869c2324d6ba982a607f0ed367396a9b51b896c Mon Sep 17 00:00:00 2001 From: Teresa Remmet Date: Tue, 28 May 2024 15:35:14 +0200 Subject: [PATCH 085/383] board: phytec: phycore_imx8mp: Make RAM size configuration fix We might not be able to always rely on the EEPROM introspection data. So add a config option alternative which configures the RAM size to a fix value. We still try to read the EEPROM introspection data at this point. So we can print the SoM information if available. Signed-off-by: Teresa Remmet --- board/phytec/phycore_imx8mp/Kconfig | 48 +++++++++++++++++++++++++++++ board/phytec/phycore_imx8mp/spl.c | 30 ++++++++++++++---- 2 files changed, 72 insertions(+), 6 deletions(-) diff --git a/board/phytec/phycore_imx8mp/Kconfig b/board/phytec/phycore_imx8mp/Kconfig index f846d10bad9..5ede39abc52 100644 --- a/board/phytec/phycore_imx8mp/Kconfig +++ b/board/phytec/phycore_imx8mp/Kconfig @@ -12,5 +12,53 @@ config SYS_CONFIG_NAME config IMX_CONFIG default "board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg" +config PHYCORE_IMX8MP_RAM_SIZE_FIX + bool "Set phyCORE-i.MX8MP RAM size fix instead of detecting" + default false + help + RAM size is automatic being detected with the help of + the EEPROM introspection data. Set RAM size to a fix value + instead. + +choice + prompt "phyCORE-i.MX8MP RAM size" + depends on PHYCORE_IMX8MP_RAM_SIZE_FIX + default PHYCORE_IMX8MP_RAM_SIZE_2GB + +config PHYCORE_IMX8MP_RAM_SIZE_1GB + bool "1GB RAM" + help + Set RAM size fix to 1GB for phyCORE-i.MX8MP. + RAM frequency is configured independent. + +config PHYCORE_IMX8MP_RAM_SIZE_2GB + bool "2GB RAM" + help + Set RAM size fix to 2GB for phyCORE-i.MX8MP. + RAM frequency is configured independent. + +config PHYCORE_IMX8MP_RAM_SIZE_4GB + bool "4GB RAM" + help + Set RAM size fix to 4GB for phyCORE-i.MX8MP. + RAM frequency is configured independent. + +config PHYCORE_IMX8MP_RAM_SIZE_8GB + bool "8GB RAM" + select PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS + help + Set RAM size fix to 8GB for phyCORE-i.MX8MP. + Only 2GHz RAMs are supported. + +endchoice + +config PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS + bool "Use 2GHz RAM timings" + depends on PHYCORE_IMX8MP_RAM_SIZE_FIX + default false + help + Use fix 2GHz RAM timings for phyCORE-i.MX8MP instead of + 1.5GHz timings. + source "board/phytec/common/Kconfig" endif diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index 855aa1a9009..7fdb96f1c14 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -49,20 +49,38 @@ void spl_dram_init(void) ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR, EEPROM_ADDR_FALLBACK); - if (ret) + if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_FIX)) goto out; ret = phytec_imx8m_detect(NULL); if (!ret) phytec_print_som_info(NULL); - u8 rev = phytec_get_rev(NULL); - u8 somtype = phytec_get_som_type(NULL); + if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_FIX)) { + if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_1GB)) + size = PHYTEC_IMX8MP_DDR_1GB; + else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_2GB)) + size = PHYTEC_IMX8MP_DDR_2GB; + else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_4GB)) + size = PHYTEC_IMX8MP_DDR_4GB; + else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_8GB)) + size = PHYTEC_IMX8MP_DDR_8GB; + if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS)) { + if (size == PHYTEC_IMX8MP_DDR_4GB) + size = PHYTEC_IMX8MP_DDR_4GB_2GHZ; + else + use_2ghz_timings = true; + } + } else { + u8 rev = phytec_get_rev(NULL); + u8 somtype = phytec_get_som_type(NULL); - if (rev != PHYTEC_EEPROM_INVAL && (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1))) - use_2ghz_timings = true; + if (rev != PHYTEC_EEPROM_INVAL && + (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1))) + use_2ghz_timings = true; - size = phytec_get_imx8m_ddr_size(NULL); + size = phytec_get_imx8m_ddr_size(NULL); + } switch (size) { case PHYTEC_IMX8MP_DDR_1GB: From 95cf918f16ddaf7e6e4b1b4dfacecb9d9609d6f7 Mon Sep 17 00:00:00 2001 From: Benjamin Hahn Date: Tue, 28 May 2024 15:35:15 +0200 Subject: [PATCH 086/383] board: phycore_imx8mp: enable setting 2GHz timings without RAM size make it possible to set the RAM timing frequency statically independent from the RAM size. Fixed RAM timing frequency can be used while the RAM size is still determined by the EEPROM image. Signed-off-by: Benjamin Hahn Signed-off-by: Teresa Remmet --- board/phytec/phycore_imx8mp/Kconfig | 23 +++++++++++++++++++++-- board/phytec/phycore_imx8mp/spl.c | 12 ++++++++++-- 2 files changed, 31 insertions(+), 4 deletions(-) diff --git a/board/phytec/phycore_imx8mp/Kconfig b/board/phytec/phycore_imx8mp/Kconfig index 5ede39abc52..bdf9e97beaa 100644 --- a/board/phytec/phycore_imx8mp/Kconfig +++ b/board/phytec/phycore_imx8mp/Kconfig @@ -52,13 +52,32 @@ config PHYCORE_IMX8MP_RAM_SIZE_8GB endchoice +config PHYCORE_IMX8MP_RAM_FREQ_FIX + bool "Set phyCORE-i.MX8MP RAM frequency fix instead of detecting" + default false + help + RAM frequency is automatic being detected with the help of + the EEPROM introspection data. Set RAM frequency to a fix value + instead. + +choice + prompt "phyCORE-i.MX8MP RAM frequency" + depends on PHYCORE_IMX8MP_RAM_FREQ_FIX + default PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS + config PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS bool "Use 2GHz RAM timings" - depends on PHYCORE_IMX8MP_RAM_SIZE_FIX - default false help Use fix 2GHz RAM timings for phyCORE-i.MX8MP instead of 1.5GHz timings. +config PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS + depends on !PHYCORE_IMX8MP_RAM_SIZE_8GB + bool "Use 1.5GHz RAM timings" + help + Use fix 1.5GHz RAM timings for phyCORE-i.MX8MP instead of + 2GHz timings. +endchoice + source "board/phytec/common/Kconfig" endif diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index 7fdb96f1c14..0610d8bbd0b 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -65,11 +65,21 @@ void spl_dram_init(void) size = PHYTEC_IMX8MP_DDR_4GB; else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_8GB)) size = PHYTEC_IMX8MP_DDR_8GB; + } else { + size = phytec_get_imx8m_ddr_size(NULL); + } + + if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_FREQ_FIX)) { if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS)) { if (size == PHYTEC_IMX8MP_DDR_4GB) size = PHYTEC_IMX8MP_DDR_4GB_2GHZ; else use_2ghz_timings = true; + } else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS)) { + if (size == PHYTEC_IMX8MP_DDR_4GB_2GHZ) + size = PHYTEC_IMX8MP_DDR_4GB; + else + use_2ghz_timings = false; } } else { u8 rev = phytec_get_rev(NULL); @@ -78,8 +88,6 @@ void spl_dram_init(void) if (rev != PHYTEC_EEPROM_INVAL && (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1))) use_2ghz_timings = true; - - size = phytec_get_imx8m_ddr_size(NULL); } switch (size) { From 93bfb458f4f6b2ed5aafe418a34793c0209d2c8b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 28 May 2024 16:15:09 -0300 Subject: [PATCH 087/383] imx8mm-cl-iot-gate: Add support for Samsung 4GB DDR Newer versions of the imx8mm-cl-iot-gate boards may come populated with a Samsung 4GB DDR model. Add support for it. Signed-off-by: Fabio Estevam --- board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c index 99d3bf3af3b..6a3d816a48a 100644 --- a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c @@ -46,7 +46,9 @@ struct lpddr4_desc { static const struct lpddr4_desc lpddr4_array[] = { { .name = "Nanya", .id = 0x05000010, .subind = 0xff, .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010}, - { .name = "Samsung", .id = 0x01061010, .subind = 0xff, + { .name = "Samsung", .id = 0x01061010, .subind = 0x04, + .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110}, + { .name = "Samsung", .id = 0x01061010, .subind = 0x02, .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010}, { .name = "Kingston", .id = 0xff000010, .subind = 0x04, .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110}, From fb95661116fb4269883721afd80578e6d88ce043 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 28 May 2024 16:15:10 -0300 Subject: [PATCH 088/383] imx8mm-cl-iot-gate: Add support for the Realtek RTL8211E PHY Newer imx8mm-cl-iot-gate versions are populated with a Realtek RTL8211E PHY instead of the Atheros AR8033. Adapted Compulab's patch from: https://github.com/compulab-yokneam/meta-bsp-imx8mm/blob/iot-gate-imx8_5.10.72/recipes-bsp/u-boot/compulab/imx8mm/0125-imx8mm-net-enable-phy-Realtek-RTL8211E.patch to support both PHYs in U-Boot. Signed-off-by: Fabio Estevam --- .../imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c | 106 +++++++++++++++++- include/configs/imx8mm-cl-iot-gate.h | 2 +- 2 files changed, 104 insertions(+), 4 deletions(-) diff --git a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c index ba158734142..bda7aac5be4 100644 --- a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c +++ b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -30,6 +31,8 @@ DECLARE_GLOBAL_DATA_PTR; +static int fec_phyaddr = -1; + #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) struct efi_fw_image fw_images[] = { #if defined(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) @@ -109,10 +112,72 @@ static int setup_fec(void) return 0; } +#define FDT_PHYADDR "/soc@0/bus@30800000/ethernet@30be0000/mdio/ethernet-phy@0" +#define FLIP_32B(val) (((val >> 24) & 0xff) | ((val << 8) & 0xff0000) | ((val >> 8) & 0xff00) | ((val << 24) & 0xff000000)) +static int fdt_set_fec_phy_addr(void *blob) +{ + u32 val; + + if (fec_phyaddr < 0) + return -EINVAL; + + val = FLIP_32B(fec_phyaddr); + return fdt_find_and_setprop(blob, FDT_PHYADDR, "reg", (const void *)&val, + sizeof(val), 0); +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + fdt_set_fec_phy_addr(blob); + return 0; +} + +/* + * These are specific ID, purposed to distiguish between PHY vendors. + * These values are not equal to real vendors' OUI (half of MAC address) + */ +#define OUI_PHY_ATHEROS 0x1374 +#define OUI_PHY_REALTEK 0x0732 + int board_phy_config(struct phy_device *phydev) { - if (IS_ENABLED(CONFIG_FEC_MXC)) { + unsigned int model, rev, oui; + int phyid1, phyid2; + unsigned int reg; + + if (!IS_ENABLED(CONFIG_FEC_MXC)) + return 0; + + phyid1 = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID1); + if (phyid1 < 0) { + printf("%s: PHYID1 registry read fail %i\n", __func__, phyid1); + return phyid1; + } + + phyid2 = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID2); + if (phyid2 < 0) { + printf("%s: PHYID2 registry read fail %i\n", __func__, phyid2); + return phyid2; + } + + reg = phyid2 | phyid1 << 16; + if (reg == 0xffff) { + printf("%s: There is no device @%i\n", __func__, phydev->addr); + return -ENODEV; + } + + rev = reg & 0xf; + reg >>= 4; + model = reg & 0x3f; + reg >>= 6; + oui = reg; + debug("%s: PHY @0x%x OUI 0x%06x model 0x%x rev 0x%x\n", + __func__, phydev->addr, oui, model, rev); + + switch (oui) { + case OUI_PHY_ATHEROS: /* enable rgmii rxc skew and phy mode select to RGMII copper */ + printf("phy: AR803x@%x\t", phydev->addr); phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); @@ -120,10 +185,45 @@ int board_phy_config(struct phy_device *phydev) phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + break; + case OUI_PHY_REALTEK: + printf("phy: RTL8211E@%x\t", phydev->addr); + /* RTL8211E-VB-CG - add TX and RX delay */ + unsigned short val; - if (phydev->drv->config) - phydev->drv->config(phydev); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x07); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0xa4); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1c); + val |= (0x1 << 13) | (0x1 << 12) | (0x1 << 11); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1c, val); + /* LEDs: set to extension page */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0007); + /* extension Page44 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x002c); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1c, 0x0430);//LCR + phy_write(phydev, MDIO_DEVAD_NONE, 0x1a, 0x0010);//LACR + /* + * To disable EEE LED mode (blinking .4s/2s) + * Extension Page5 + */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0005); + phy_write(phydev, MDIO_DEVAD_NONE, 0x05, 0x8b82);//magic const + phy_write(phydev, MDIO_DEVAD_NONE, 0x06, 0x052b);//magic const + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x00);// Back to Page0 + + break; + default: + printf("%s: ERROR: unknown PHY @0x%x OUI 0x%06x model 0x%x rev 0x%x\n", + __func__, phydev->addr, oui, model, rev); + return -ENOSYS; } + + fec_phyaddr = phydev->addr; + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; } diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index 09d87cf214b..0c547027ba6 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -136,7 +136,7 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 -#define CFG_FEC_MXC_PHYADDR 0 +#define CFG_FEC_MXC_PHYADDR -1 /* Auto search of PHY on MII */ /* USB Configs */ #define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) From a804c8dc5f5e3760948e5ef22f5c605af9cfc695 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Tue, 21 May 2024 09:13:25 +0200 Subject: [PATCH 089/383] common: eeprom_layout: Assign default layout methods and parameters before specific ones MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Assign the default eeprom layout parameter .data_size and methods .print() and .update() before calling eeprom_layout_assign() in eeprom_layout_setup(). This allows eeprom_layout_assign() to overwrite these if needed. Signed-off-by: Marek Behún --- common/eeprom/eeprom_layout.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/common/eeprom/eeprom_layout.c b/common/eeprom/eeprom_layout.c index 5a9be1da061..406db3f7d15 100644 --- a/common/eeprom/eeprom_layout.c +++ b/common/eeprom/eeprom_layout.c @@ -111,14 +111,14 @@ void eeprom_layout_setup(struct eeprom_layout *layout, unsigned char *buf, else layout->layout_version = layout_version; + layout->data_size = buf_size; + layout->print = eeprom_layout_print; + layout->update = eeprom_layout_update_field; + eeprom_layout_assign(layout, layout_version); layout->data = buf; for (i = 0; i < layout->num_of_fields; i++) { layout->fields[i].buf = buf; buf += layout->fields[i].size; } - - layout->data_size = buf_size; - layout->print = eeprom_layout_print; - layout->update = eeprom_layout_update_field; } From 15378a3fe1838a3c5abf2330a6eb4e92462783c1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Tue, 21 May 2024 09:13:26 +0200 Subject: [PATCH 090/383] common: eeprom_layout: Split field finding code from the field update function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Split the eeprom layout field finding code from the eeprom_layout_update_field() function in order to make it usable in alternative implementations of update method. Signed-off-by: Marek Behún --- common/eeprom/eeprom_layout.c | 46 +++++++++++++++++++++++------------ include/eeprom_layout.h | 4 +++ 2 files changed, 35 insertions(+), 15 deletions(-) diff --git a/common/eeprom/eeprom_layout.c b/common/eeprom/eeprom_layout.c index 406db3f7d15..801e90d38d0 100644 --- a/common/eeprom/eeprom_layout.c +++ b/common/eeprom/eeprom_layout.c @@ -56,6 +56,28 @@ static void eeprom_layout_print(const struct eeprom_layout *layout) fields[i].print(&fields[i]); } +/* + * eeprom_layout_find_field() - finds a layout field by name + * @layout: A pointer to an existing struct layout. + * @field_name: The name of the field to update. + * @warn: Whether to print a warning if the field is not found. + * + * Returns: a pointer to the found field or NULL on failure. + */ +struct eeprom_field *eeprom_layout_find_field(struct eeprom_layout *layout, + char *field_name, bool warn) +{ + for (int i = 0; i < layout->num_of_fields; i++) + if (layout->fields[i].name != RESERVED_FIELDS && + !strcmp(layout->fields[i].name, field_name)) + return &layout->fields[i]; + + if (warn) + printf("No such field '%s'\n", field_name); + + return NULL; +} + /* * eeprom_layout_update_field() - update a single field in the layout data. * @layout: A pointer to an existing struct layout. @@ -67,8 +89,8 @@ static void eeprom_layout_print(const struct eeprom_layout *layout) static int eeprom_layout_update_field(struct eeprom_layout *layout, char *field_name, char *new_data) { - int i, err; - struct eeprom_field *fields = layout->fields; + struct eeprom_field *field; + int err; if (new_data == NULL) return 0; @@ -76,21 +98,15 @@ static int eeprom_layout_update_field(struct eeprom_layout *layout, if (field_name == NULL) return -1; - for (i = 0; i < layout->num_of_fields; i++) { - if (fields[i].name == RESERVED_FIELDS || - strcmp(fields[i].name, field_name)) - continue; + field = eeprom_layout_find_field(layout, field_name, true); + if (field == NULL) + return -1; - err = fields[i].update(&fields[i], new_data); - if (err) - printf("Invalid data for field %s\n", field_name); + err = field->update(field, new_data); + if (err) + printf("Invalid data for field %s\n", field_name); - return err; - } - - printf("No such field '%s'\n", field_name); - - return -1; + return err; } /* diff --git a/include/eeprom_layout.h b/include/eeprom_layout.h index 730d963ab96..b1d62205958 100644 --- a/include/eeprom_layout.h +++ b/include/eeprom_layout.h @@ -9,6 +9,8 @@ #ifndef _LAYOUT_ #define _LAYOUT_ +#include + #define RESERVED_FIELDS NULL #define LAYOUT_VERSION_UNRECOGNIZED -1 #define LAYOUT_VERSION_AUTODETECT -2 @@ -24,6 +26,8 @@ struct eeprom_layout { char *new_data); }; +struct eeprom_field *eeprom_layout_find_field(struct eeprom_layout *layout, + char *field_name, bool warn); void eeprom_layout_setup(struct eeprom_layout *layout, unsigned char *buf, unsigned int buf_size, int layout_version); __weak void __eeprom_layout_assign(struct eeprom_layout *layout, From 96dfa5869da586eb1c8d84c22164a2bf399968a1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Tue, 21 May 2024 09:13:27 +0200 Subject: [PATCH 091/383] common: eeprom_field: Fix updating binary field MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The __eeprom_field_update_bin() function is expected to parse a hex string into bytes (potentially in reverse order), but the simple_strtoul() function is given 0 as base. This does not work since the string does not contain '0x' prefix. Add explicit base 16. Signed-off-by: Marek Behún --- common/eeprom/eeprom_field.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/eeprom/eeprom_field.c b/common/eeprom/eeprom_field.c index f56eebe679f..9b831414a4b 100644 --- a/common/eeprom/eeprom_field.c +++ b/common/eeprom/eeprom_field.c @@ -55,7 +55,7 @@ static int __eeprom_field_update_bin(struct eeprom_field *field, tmp[k] = value[reverse ? i - 1 + k : i + k]; } - byte = simple_strtoul(tmp, &endptr, 0); + byte = simple_strtoul(tmp, &endptr, 16); if (*endptr != '\0' || byte < 0) return -1; From 951dc4e077b2ba5eadaba3beb9b61f131ffa6fdc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Tue, 21 May 2024 09:13:28 +0200 Subject: [PATCH 092/383] common: eeprom_field: Drop unnecessary comparison MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The byte variable is of type unsigned char, it is never less than zero. The error case is handled by *endptr, so drop the comparison altogether. Signed-off-by: Marek Behún --- common/eeprom/eeprom_field.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/eeprom/eeprom_field.c b/common/eeprom/eeprom_field.c index 9b831414a4b..26f6041e548 100644 --- a/common/eeprom/eeprom_field.c +++ b/common/eeprom/eeprom_field.c @@ -56,7 +56,7 @@ static int __eeprom_field_update_bin(struct eeprom_field *field, } byte = simple_strtoul(tmp, &endptr, 16); - if (*endptr != '\0' || byte < 0) + if (*endptr != '\0') return -1; field->buf[j] = byte; From 642ec48c76e6469c9a14f5c0359363af25bdaafb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Tue, 21 May 2024 09:13:29 +0200 Subject: [PATCH 093/383] cmd: eeprom: Fix usage help for the eeprom command MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The bus and devaddr arguments of the eeprom command are optional, and if only one is given, it is assumed to be devaddr. Change the usage help from to [[bus] [devaddr] Signed-off-by: Marek Behún --- cmd/eeprom.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/cmd/eeprom.c b/cmd/eeprom.c index 322765ad02a..0d604832e44 100644 --- a/cmd/eeprom.c +++ b/cmd/eeprom.c @@ -418,14 +418,14 @@ int do_eeprom(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) U_BOOT_CMD( eeprom, 8, 1, do_eeprom, "EEPROM sub-system", - "read addr off cnt\n" - "eeprom write addr off cnt\n" + "read [[bus] devaddr] addr off cnt\n" + "eeprom write [[bus] devaddr] addr off cnt\n" " - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'" #ifdef CONFIG_CMD_EEPROM_LAYOUT "\n" - "eeprom print [-l ] \n" + "eeprom print [-l ] [[bus] devaddr]\n" " - Print layout fields and their data in human readable format\n" - "eeprom update [-l ] field_name field_value\n" + "eeprom update [-l ] [[bus] devaddr] field_name field_value\n" " - Update a specific eeprom field with new data.\n" " The new data must be written in the same human readable format as shown by the print command.\n" "\n" From 2d49dafe4ac572228fe4309cf0445b5f82ff2fd5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Tue, 21 May 2024 09:13:30 +0200 Subject: [PATCH 094/383] cmd: eeprom: Hide eeprom layout versioning behind a Kconfig option MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a new Kconfig option EEPROM_LAYOUT_VERSIONS, and hide eeprom layout versionsing code behind it. Only print the relevant help in 'eeprom' command usage if this option is enabled. Enable this new option for cm_fx6_defconfig and cm_t43_defconfig. These are the only boards using EEPROM layout versioning. Signed-off-by: Marek Behún --- cmd/Kconfig | 9 ++++++++- cmd/eeprom.c | 20 +++++++++++++++----- configs/cm_fx6_defconfig | 1 + configs/cm_t43_defconfig | 1 + 4 files changed, 25 insertions(+), 6 deletions(-) diff --git a/cmd/Kconfig b/cmd/Kconfig index b026439c773..8c370993f67 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -803,9 +803,16 @@ config CMD_EEPROM_LAYOUT types of eeprom fields. Can be used for defining custom layouts. +config EEPROM_LAYOUT_VERSIONS + bool "Support specifying eeprom layout version" + depends on CMD_EEPROM_LAYOUT + help + Support specifying eeprom layout version in the 'eeprom' command + via the -l option. + config EEPROM_LAYOUT_HELP_STRING string "Tells user what layout names are supported" - depends on CMD_EEPROM_LAYOUT + depends on EEPROM_LAYOUT_VERSIONS default "" help Help printed with the LAYOUT VERSIONS part of the 'eeprom' diff --git a/cmd/eeprom.c b/cmd/eeprom.c index 0d604832e44..d610dc99317 100644 --- a/cmd/eeprom.c +++ b/cmd/eeprom.c @@ -252,10 +252,12 @@ static int parse_i2c_bus_addr(int *i2c_bus, ulong *i2c_addr, int argc, #ifdef CONFIG_CMD_EEPROM_LAYOUT +#ifdef CONFIG_EEPROM_LAYOUT_VERSIONS __weak int eeprom_parse_layout_version(char *str) { return LAYOUT_VERSION_UNRECOGNIZED; } +#endif static unsigned char eeprom_buf[CONFIG_SYS_EEPROM_SIZE]; @@ -359,7 +361,7 @@ int do_eeprom(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) if (action == EEPROM_ACTION_INVALID) return CMD_RET_USAGE; -#ifdef CONFIG_CMD_EEPROM_LAYOUT +#ifdef CONFIG_EEPROM_LAYOUT_VERSIONS if (action == EEPROM_PRINT || action == EEPROM_UPDATE) { if (!strcmp(argv[index], "-l")) { NEXT_PARAM(argc, index); @@ -415,6 +417,12 @@ int do_eeprom(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) field_name, field_value, addr, off, cnt); } +#ifdef CONFIG_EEPROM_LAYOUT_VERSIONS +#define EEPROM_LAYOUT_SPEC "[-l ] " +#else +#define EEPROM_LAYOUT_SPEC "" +#endif + U_BOOT_CMD( eeprom, 8, 1, do_eeprom, "EEPROM sub-system", @@ -423,16 +431,18 @@ U_BOOT_CMD( " - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'" #ifdef CONFIG_CMD_EEPROM_LAYOUT "\n" - "eeprom print [-l ] [[bus] devaddr]\n" + "eeprom print " EEPROM_LAYOUT_SPEC "[[bus] devaddr]\n" " - Print layout fields and their data in human readable format\n" - "eeprom update [-l ] [[bus] devaddr] field_name field_value\n" + "eeprom update " EEPROM_LAYOUT_SPEC "[[bus] devaddr] field_name field_value\n" " - Update a specific eeprom field with new data.\n" - " The new data must be written in the same human readable format as shown by the print command.\n" - "\n" + " The new data must be written in the same human readable format as shown by the print command." +#ifdef CONFIG_EEPROM_LAYOUT_VERSIONS + "\n\n" "LAYOUT VERSIONS\n" "The -l option can be used to force the command to interpret the EEPROM data using the chosen layout.\n" "If the -l option is omitted, the command will auto detect the layout based on the data in the EEPROM.\n" "The values which can be provided with the -l option are:\n" CONFIG_EEPROM_LAYOUT_HELP_STRING"\n" #endif +#endif ); diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index a4d5f91b35f..386616cc420 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -46,6 +46,7 @@ CONFIG_SYS_MAXARGS=32 CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_EEPROM_LAYOUT=y +CONFIG_EEPROM_LAYOUT_VERSIONS=y CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3" CONFIG_SYS_I2C_EEPROM_BUS=2 CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig index 93e667292c8..32f126a5174 100644 --- a/configs/cm_t43_defconfig +++ b/configs/cm_t43_defconfig @@ -50,6 +50,7 @@ CONFIG_SYS_PROMPT="CM-T43 # " CONFIG_CMD_ASKENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_EEPROM_LAYOUT=y +CONFIG_EEPROM_LAYOUT_VERSIONS=y CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3" CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 From fda747c8f1f287607ffac7c6c3b2d99c7f08540e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Tue, 21 May 2024 09:13:31 +0200 Subject: [PATCH 095/383] cmd: eeprom: Deduplicate parse_i2c_bus_addr() calls MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Deduplicate the calls to parse_i2c_bus_addr(). Signed-off-by: Marek Behún --- cmd/eeprom.c | 36 +++++++++++++++++------------------- 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/cmd/eeprom.c b/cmd/eeprom.c index d610dc99317..12902e812e4 100644 --- a/cmd/eeprom.c +++ b/cmd/eeprom.c @@ -339,6 +339,21 @@ static int eeprom_execute_command(enum eeprom_action action, int i2c_bus, return rcode; } +static int eeprom_action_expected_argc(enum eeprom_action action) +{ + switch (action) { + case EEPROM_READ: + case EEPROM_WRITE: + return 3; + case EEPROM_PRINT: + return 0; + case EEPROM_UPDATE: + return 2; + default: + return CMD_RET_USAGE; + } +} + #define NEXT_PARAM(argc, index) { (argc)--; (index)++; } int do_eeprom(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -371,25 +386,8 @@ int do_eeprom(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) } #endif - switch (action) { - case EEPROM_READ: - case EEPROM_WRITE: - ret = parse_i2c_bus_addr(&i2c_bus, &i2c_addr, argc, - argv + index, 3); - break; - case EEPROM_PRINT: - ret = parse_i2c_bus_addr(&i2c_bus, &i2c_addr, argc, - argv + index, 0); - break; - case EEPROM_UPDATE: - ret = parse_i2c_bus_addr(&i2c_bus, &i2c_addr, argc, - argv + index, 2); - break; - default: - /* Get compiler to stop whining */ - return CMD_RET_USAGE; - } - + ret = parse_i2c_bus_addr(&i2c_bus, &i2c_addr, argc, argv + index, + eeprom_action_expected_argc(action)); if (ret == CMD_RET_USAGE) return ret; From 15f0536f293e9c75ee5f5e70201593f83654710e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Tue, 21 May 2024 09:13:32 +0200 Subject: [PATCH 096/383] cmd: eeprom: Refactor eeprom device specifier parsing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In preparation for allowing to access eeprom by driver-model device name, refactor the eeprom device specifier parsing. Instead of filling two parameters (i2c_bus, i2c_addr), the parsing function now fills one parameter of type struct eeprom_dev_spec. Signed-off-by: Marek Behún --- cmd/eeprom.c | 77 ++++++++++++++++++++++++++++------------------------ 1 file changed, 41 insertions(+), 36 deletions(-) diff --git a/cmd/eeprom.c b/cmd/eeprom.c index 12902e812e4..e29639780de 100644 --- a/cmd/eeprom.c +++ b/cmd/eeprom.c @@ -208,41 +208,42 @@ static long parse_numeric_param(char *str) return (*endptr != '\0') ? -1 : value; } +struct eeprom_dev_spec { + int i2c_bus; + ulong i2c_addr; +}; + /** - * parse_i2c_bus_addr - parse the i2c bus and i2c devaddr parameters + * parse_eeprom_dev_spec - parse the eeprom device specifier * - * @i2c_bus: address to store the i2c bus - * @i2c_addr: address to store the device i2c address - * @argc: count of command line arguments left to parse + * @dev: pointer to eeprom device specifier + * @argc: count of command line arguments that can be used to parse + * the device specifier * @argv: command line arguments left to parse - * @argc_no_bus_addr: argc value we expect to see when bus & addr aren't given * * @returns: number of arguments parsed or CMD_RET_USAGE if error */ -static int parse_i2c_bus_addr(int *i2c_bus, ulong *i2c_addr, int argc, - char *const argv[], int argc_no_bus_addr) +static int parse_eeprom_dev_spec(struct eeprom_dev_spec *dev, int argc, + char *const argv[]) { - int argc_no_bus = argc_no_bus_addr + 1; - int argc_bus_addr = argc_no_bus_addr + 2; - #ifdef CONFIG_SYS_I2C_EEPROM_ADDR - if (argc == argc_no_bus_addr) { - *i2c_bus = -1; - *i2c_addr = CONFIG_SYS_I2C_EEPROM_ADDR; + if (argc == 0) { + dev->i2c_bus = -1; + dev->i2c_addr = CONFIG_SYS_I2C_EEPROM_ADDR; return 0; } #endif - if (argc == argc_no_bus) { - *i2c_bus = -1; - *i2c_addr = parse_numeric_param(argv[0]); + if (argc == 1) { + dev->i2c_bus = -1; + dev->i2c_addr = parse_numeric_param(argv[0]); return 1; } - if (argc == argc_bus_addr) { - *i2c_bus = parse_numeric_param(argv[0]); - *i2c_addr = parse_numeric_param(argv[1]); + if (argc == 2) { + dev->i2c_bus = parse_numeric_param(argv[0]); + dev->i2c_addr = parse_numeric_param(argv[1]); return 2; } @@ -287,9 +288,10 @@ static enum eeprom_action parse_action(char *cmd) return EEPROM_ACTION_INVALID; } -static int eeprom_execute_command(enum eeprom_action action, int i2c_bus, - ulong i2c_addr, int layout_ver, char *key, - char *value, ulong addr, ulong off, ulong cnt) +static int eeprom_execute_command(enum eeprom_action action, + struct eeprom_dev_spec *dev, + int layout_ver, char *key, char *value, + ulong addr, ulong off, ulong cnt) { int rcode = 0; const char *const fmt = @@ -301,25 +303,26 @@ static int eeprom_execute_command(enum eeprom_action action, int i2c_bus, if (action == EEPROM_ACTION_INVALID) return CMD_RET_USAGE; - eeprom_init(i2c_bus); + eeprom_init(dev->i2c_bus); if (action == EEPROM_READ) { - printf(fmt, i2c_addr, "read", addr, off, cnt); + printf(fmt, dev->i2c_addr, "read", addr, off, cnt); - rcode = eeprom_read(i2c_addr, off, (uchar *)addr, cnt); + rcode = eeprom_read(dev->i2c_addr, off, (uchar *)addr, cnt); puts("done\n"); return rcode; } else if (action == EEPROM_WRITE) { - printf(fmt, i2c_addr, "write", addr, off, cnt); + printf(fmt, dev->i2c_addr, "write", addr, off, cnt); - rcode = eeprom_write(i2c_addr, off, (uchar *)addr, cnt); + rcode = eeprom_write(dev->i2c_addr, off, (uchar *)addr, cnt); puts("done\n"); return rcode; } #ifdef CONFIG_CMD_EEPROM_LAYOUT - rcode = eeprom_read(i2c_addr, 0, eeprom_buf, CONFIG_SYS_EEPROM_SIZE); + rcode = eeprom_read(dev->i2c_addr, 0, eeprom_buf, + CONFIG_SYS_EEPROM_SIZE); if (rcode < 0) return rcode; @@ -333,7 +336,8 @@ static int eeprom_execute_command(enum eeprom_action action, int i2c_bus, layout.update(&layout, key, value); - rcode = eeprom_write(i2c_addr, 0, layout.data, CONFIG_SYS_EEPROM_SIZE); + rcode = eeprom_write(dev->i2c_addr, 0, layout.data, + CONFIG_SYS_EEPROM_SIZE); #endif return rcode; @@ -359,9 +363,9 @@ int do_eeprom(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { int layout_ver = LAYOUT_VERSION_AUTODETECT; enum eeprom_action action = EEPROM_ACTION_INVALID; - int i2c_bus = -1, index = 0; - ulong i2c_addr = -1, addr = 0, cnt = 0, off = 0; - int ret; + struct eeprom_dev_spec dev; + ulong addr = 0, cnt = 0, off = 0; + int ret, index = 0; char *field_name = ""; char *field_value = ""; @@ -386,8 +390,9 @@ int do_eeprom(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) } #endif - ret = parse_i2c_bus_addr(&i2c_bus, &i2c_addr, argc, argv + index, - eeprom_action_expected_argc(action)); + ret = parse_eeprom_dev_spec(&dev, + argc - eeprom_action_expected_argc(action), + argv + index); if (ret == CMD_RET_USAGE) return ret; @@ -411,8 +416,8 @@ int do_eeprom(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) } #endif - return eeprom_execute_command(action, i2c_bus, i2c_addr, layout_ver, - field_name, field_value, addr, off, cnt); + return eeprom_execute_command(action, &dev, layout_ver, field_name, + field_value, addr, off, cnt); } #ifdef CONFIG_EEPROM_LAYOUT_VERSIONS From e9774afedd20bfe8a18b20a63010c1d18cd16cd7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Tue, 21 May 2024 09:13:33 +0200 Subject: [PATCH 097/383] cmd: eeprom: Refactor command execution into function by action MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Refactor the eeprom_execute_command() function into separate functions do_eeprom_rw(), do_eeprom_print() and do_eeprom_update(). Signed-off-by: Marek Behún --- cmd/eeprom.c | 123 ++++++++++++++++++++++++++++++++------------------- 1 file changed, 77 insertions(+), 46 deletions(-) diff --git a/cmd/eeprom.c b/cmd/eeprom.c index e29639780de..c76cf431578 100644 --- a/cmd/eeprom.c +++ b/cmd/eeprom.c @@ -288,61 +288,75 @@ static enum eeprom_action parse_action(char *cmd) return EEPROM_ACTION_INVALID; } -static int eeprom_execute_command(enum eeprom_action action, - struct eeprom_dev_spec *dev, - int layout_ver, char *key, char *value, - ulong addr, ulong off, ulong cnt) +static int do_eeprom_rw(struct eeprom_dev_spec *dev, bool read, + ulong addr, ulong off, ulong cnt) { - int rcode = 0; const char *const fmt = "\nEEPROM @0x%lX %s: addr 0x%08lx off 0x%04lx count %ld ... "; -#ifdef CONFIG_CMD_EEPROM_LAYOUT - struct eeprom_layout layout; -#endif + uchar *memloc = (uchar *)addr; + int ret; - if (action == EEPROM_ACTION_INVALID) - return CMD_RET_USAGE; + printf(fmt, dev->i2c_addr, read ? "read" : "write", addr, off, cnt); + if (read) + ret = eeprom_read(dev->i2c_addr, off, memloc, cnt); + else + ret = eeprom_write(dev->i2c_addr, off, memloc, cnt); + puts("done\n"); - eeprom_init(dev->i2c_bus); - if (action == EEPROM_READ) { - printf(fmt, dev->i2c_addr, "read", addr, off, cnt); - - rcode = eeprom_read(dev->i2c_addr, off, (uchar *)addr, cnt); - - puts("done\n"); - return rcode; - } else if (action == EEPROM_WRITE) { - printf(fmt, dev->i2c_addr, "write", addr, off, cnt); - - rcode = eeprom_write(dev->i2c_addr, off, (uchar *)addr, cnt); - - puts("done\n"); - return rcode; - } + return ret; +} #ifdef CONFIG_CMD_EEPROM_LAYOUT - rcode = eeprom_read(dev->i2c_addr, 0, eeprom_buf, - CONFIG_SYS_EEPROM_SIZE); - if (rcode < 0) - return rcode; - eeprom_layout_setup(&layout, eeprom_buf, CONFIG_SYS_EEPROM_SIZE, +static int do_eeprom_layout(struct eeprom_dev_spec *dev, int layout_ver, + struct eeprom_layout *layout) +{ + int ret; + + ret = eeprom_read(dev->i2c_addr, 0, eeprom_buf, CONFIG_SYS_EEPROM_SIZE); + if (ret) + return ret; + + eeprom_layout_setup(layout, eeprom_buf, CONFIG_SYS_EEPROM_SIZE, layout_ver); - if (action == EEPROM_PRINT) { - layout.print(&layout); - return 0; - } - - layout.update(&layout, key, value); - - rcode = eeprom_write(dev->i2c_addr, 0, layout.data, - CONFIG_SYS_EEPROM_SIZE); -#endif - - return rcode; + return 0; } +static int do_eeprom_print(struct eeprom_dev_spec *dev, int layout_ver) +{ + struct eeprom_layout layout; + int ret; + + ret = do_eeprom_layout(dev, layout_ver, &layout); + if (ret) + return ret; + + layout.print(&layout); + + return 0; +} + +static int do_eeprom_update(struct eeprom_dev_spec *dev, int layout_ver, + char *key, char *value) +{ + struct eeprom_layout layout; + int ret; + + ret = do_eeprom_layout(dev, layout_ver, &layout); + if (ret) + return ret; + + ret = layout.update(&layout, key, value); + if (ret) + return CMD_RET_FAILURE; + + return eeprom_write(dev->i2c_addr, 0, layout.data, + CONFIG_SYS_EEPROM_SIZE); +} + +#endif + static int eeprom_action_expected_argc(enum eeprom_action action) { switch (action) { @@ -361,13 +375,15 @@ static int eeprom_action_expected_argc(enum eeprom_action action) #define NEXT_PARAM(argc, index) { (argc)--; (index)++; } int do_eeprom(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - int layout_ver = LAYOUT_VERSION_AUTODETECT; enum eeprom_action action = EEPROM_ACTION_INVALID; struct eeprom_dev_spec dev; ulong addr = 0, cnt = 0, off = 0; int ret, index = 0; +#ifdef CONFIG_CMD_EEPROM_LAYOUT char *field_name = ""; char *field_value = ""; + int layout_ver = LAYOUT_VERSION_AUTODETECT; +#endif if (argc <= 1) return CMD_RET_USAGE; @@ -416,8 +432,23 @@ int do_eeprom(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) } #endif - return eeprom_execute_command(action, &dev, layout_ver, field_name, - field_value, addr, off, cnt); + eeprom_init(dev.i2c_bus); + + switch (action) { + case EEPROM_READ: + case EEPROM_WRITE: + return do_eeprom_rw(&dev, action == EEPROM_READ, + addr, off, cnt); +#ifdef CONFIG_CMD_EEPROM_LAYOUT + case EEPROM_PRINT: + return do_eeprom_print(&dev, layout_ver); + case EEPROM_UPDATE: + return do_eeprom_update(&dev, layout_ver, + field_name, field_value); +#endif + default: + return CMD_RET_USAGE; + } } #ifdef CONFIG_EEPROM_LAYOUT_VERSIONS From e5dbc80fe0e87d8a6e5226c4b3329d648fd89386 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Tue, 21 May 2024 09:13:34 +0200 Subject: [PATCH 098/383] cmd: eeprom: Don't read/write whole EEPROM if not necessary MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Don't read/write whole EEPROM if not necessary when printing / updating EEPROM layout fields. Only read/write layout.data_size bytes. Signed-off-by: Marek Behún --- cmd/eeprom.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/cmd/eeprom.c b/cmd/eeprom.c index c76cf431578..9c4af88738e 100644 --- a/cmd/eeprom.c +++ b/cmd/eeprom.c @@ -311,16 +311,10 @@ static int do_eeprom_rw(struct eeprom_dev_spec *dev, bool read, static int do_eeprom_layout(struct eeprom_dev_spec *dev, int layout_ver, struct eeprom_layout *layout) { - int ret; - - ret = eeprom_read(dev->i2c_addr, 0, eeprom_buf, CONFIG_SYS_EEPROM_SIZE); - if (ret) - return ret; - eeprom_layout_setup(layout, eeprom_buf, CONFIG_SYS_EEPROM_SIZE, layout_ver); - return 0; + return eeprom_read(dev->i2c_addr, 0, eeprom_buf, layout->data_size); } static int do_eeprom_print(struct eeprom_dev_spec *dev, int layout_ver) @@ -351,8 +345,7 @@ static int do_eeprom_update(struct eeprom_dev_spec *dev, int layout_ver, if (ret) return CMD_RET_FAILURE; - return eeprom_write(dev->i2c_addr, 0, layout.data, - CONFIG_SYS_EEPROM_SIZE); + return eeprom_write(dev->i2c_addr, 0, layout.data, layout.data_size); } #endif From 57a9e8d86fde5732f77577adf52dcb62fcdc068a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Tue, 21 May 2024 09:13:35 +0200 Subject: [PATCH 099/383] cmd: eeprom: Extend to EEPROMs probed via driver model MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Extend the 'eeprom' command to allow accessing EEPROMs probed via driver model, uclass UCLASS_I2C_EEPROM. When the CONFIG_I2C_EEPROM config option is enabled (and so the i2c-eeprom driver is built), the 'eeprom' command now accepts driver model device name as EEPROM specifier for the 'eeprom' command, in addition to the legacy [[bus] devaddr] specifier. Moreover if no device specifier is given, then the first UCLASS_I2C_EEPROM device is used, if found. Signed-off-by: Marek Behún --- cmd/eeprom.c | 122 ++++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 112 insertions(+), 10 deletions(-) diff --git a/cmd/eeprom.c b/cmd/eeprom.c index 9c4af88738e..a39fc5ffdcb 100644 --- a/cmd/eeprom.c +++ b/cmd/eeprom.c @@ -22,8 +22,10 @@ #include #include #include +#include #include #include +#include #include #include @@ -209,10 +211,41 @@ static long parse_numeric_param(char *str) } struct eeprom_dev_spec { +#if CONFIG_IS_ENABLED(I2C_EEPROM) + struct udevice *dev; +#endif int i2c_bus; ulong i2c_addr; }; +static void eeprom_dev_spec_init(struct eeprom_dev_spec *dev) +{ +#if CONFIG_IS_ENABLED(I2C_EEPROM) + if (!dev->dev) +#endif + eeprom_init(dev->i2c_bus); +} + +static int eeprom_dev_spec_read(struct eeprom_dev_spec *dev, + unsigned offset, uchar *buffer, unsigned cnt) +{ +#if CONFIG_IS_ENABLED(I2C_EEPROM) + if (dev->dev) + return i2c_eeprom_read(dev->dev, offset, buffer, cnt); +#endif + return eeprom_read(dev->i2c_addr, offset, buffer, cnt); +} + +static int eeprom_dev_spec_write(struct eeprom_dev_spec *dev, + unsigned offset, uchar *buffer, unsigned cnt) +{ +#if CONFIG_IS_ENABLED(I2C_EEPROM) + if (dev->dev) + return i2c_eeprom_write(dev->dev, offset, buffer, cnt); +#endif + return eeprom_write(dev->i2c_addr, offset, buffer, cnt); +} + /** * parse_eeprom_dev_spec - parse the eeprom device specifier * @@ -226,6 +259,28 @@ struct eeprom_dev_spec { static int parse_eeprom_dev_spec(struct eeprom_dev_spec *dev, int argc, char *const argv[]) { +#if CONFIG_IS_ENABLED(I2C_EEPROM) + if (argc == 0) { + if (!uclass_first_device_err(UCLASS_I2C_EEPROM, &dev->dev)) + return 0; + } + + if (argc == 1) { + if (!uclass_get_device_by_name(UCLASS_I2C_EEPROM, argv[0], + &dev->dev)) + return 1; + + /* + * If we could not find the device by name and the parameter is + * not numeric (and so won't be handled later), fail. + */ + if (parse_numeric_param(argv[0]) == -1) { + printf("Can't get eeprom device: %s\n", argv[0]); + return CMD_RET_USAGE; + } + } +#endif + #ifdef CONFIG_SYS_I2C_EEPROM_ADDR if (argc == 0) { dev->i2c_bus = -1; @@ -265,6 +320,7 @@ static unsigned char eeprom_buf[CONFIG_SYS_EEPROM_SIZE]; #endif enum eeprom_action { + EEPROM_LIST, EEPROM_READ, EEPROM_WRITE, EEPROM_PRINT, @@ -274,6 +330,10 @@ enum eeprom_action { static enum eeprom_action parse_action(char *cmd) { +#if CONFIG_IS_ENABLED(I2C_EEPROM) + if (!strncmp(cmd, "list", 4)) + return EEPROM_LIST; +#endif if (!strncmp(cmd, "read", 4)) return EEPROM_READ; if (!strncmp(cmd, "write", 5)) @@ -288,6 +348,24 @@ static enum eeprom_action parse_action(char *cmd) return EEPROM_ACTION_INVALID; } +#if CONFIG_IS_ENABLED(I2C_EEPROM) +static int do_eeprom_list(void) +{ + struct udevice *dev; + struct uclass *uc; + int err; + + err = uclass_get(UCLASS_I2C_EEPROM, &uc); + if (err) + return CMD_RET_FAILURE; + + uclass_foreach_dev(dev, uc) + printf("%s (%s)\n", dev->name, dev->driver->name); + + return CMD_RET_SUCCESS; +} +#endif + static int do_eeprom_rw(struct eeprom_dev_spec *dev, bool read, ulong addr, ulong off, ulong cnt) { @@ -298,9 +376,9 @@ static int do_eeprom_rw(struct eeprom_dev_spec *dev, bool read, printf(fmt, dev->i2c_addr, read ? "read" : "write", addr, off, cnt); if (read) - ret = eeprom_read(dev->i2c_addr, off, memloc, cnt); + ret = eeprom_dev_spec_read(dev, off, memloc, cnt); else - ret = eeprom_write(dev->i2c_addr, off, memloc, cnt); + ret = eeprom_dev_spec_write(dev, off, memloc, cnt); puts("done\n"); return ret; @@ -314,7 +392,7 @@ static int do_eeprom_layout(struct eeprom_dev_spec *dev, int layout_ver, eeprom_layout_setup(layout, eeprom_buf, CONFIG_SYS_EEPROM_SIZE, layout_ver); - return eeprom_read(dev->i2c_addr, 0, eeprom_buf, layout->data_size); + return eeprom_dev_spec_read(dev, 0, eeprom_buf, layout->data_size); } static int do_eeprom_print(struct eeprom_dev_spec *dev, int layout_ver) @@ -345,7 +423,7 @@ static int do_eeprom_update(struct eeprom_dev_spec *dev, int layout_ver, if (ret) return CMD_RET_FAILURE; - return eeprom_write(dev->i2c_addr, 0, layout.data, layout.data_size); + return eeprom_dev_spec_write(dev, 0, layout.data, layout.data_size); } #endif @@ -353,6 +431,8 @@ static int do_eeprom_update(struct eeprom_dev_spec *dev, int layout_ver, static int eeprom_action_expected_argc(enum eeprom_action action) { switch (action) { + case EEPROM_LIST: + return 0; case EEPROM_READ: case EEPROM_WRITE: return 3; @@ -389,6 +469,11 @@ int do_eeprom(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) if (action == EEPROM_ACTION_INVALID) return CMD_RET_USAGE; +#if CONFIG_IS_ENABLED(I2C_EEPROM) + if (action == EEPROM_LIST) + return do_eeprom_list(); +#endif + #ifdef CONFIG_EEPROM_LAYOUT_VERSIONS if (action == EEPROM_PRINT || action == EEPROM_UPDATE) { if (!strcmp(argv[index], "-l")) { @@ -425,7 +510,7 @@ int do_eeprom(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) } #endif - eeprom_init(dev.i2c_bus); + eeprom_dev_spec_init(&dev); switch (action) { case EEPROM_READ: @@ -450,19 +535,37 @@ int do_eeprom(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) #define EEPROM_LAYOUT_SPEC "" #endif +#if CONFIG_IS_ENABLED(I2C_EEPROM) +# define EEPROM_DEV_SPEC "[device_specifier]" +#else +# define EEPROM_DEV_SPEC "[[bus] devaddr]" +#endif + U_BOOT_CMD( eeprom, 8, 1, do_eeprom, "EEPROM sub-system", - "read [[bus] devaddr] addr off cnt\n" - "eeprom write [[bus] devaddr] addr off cnt\n" +#if CONFIG_IS_ENABLED(I2C_EEPROM) + "list\n" + "eeprom " +#endif + "read " EEPROM_DEV_SPEC " addr off cnt\n" + "eeprom write " EEPROM_DEV_SPEC " addr off cnt\n" " - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'" #ifdef CONFIG_CMD_EEPROM_LAYOUT "\n" - "eeprom print " EEPROM_LAYOUT_SPEC "[[bus] devaddr]\n" + "eeprom print " EEPROM_LAYOUT_SPEC EEPROM_DEV_SPEC "\n" " - Print layout fields and their data in human readable format\n" - "eeprom update " EEPROM_LAYOUT_SPEC "[[bus] devaddr] field_name field_value\n" + "eeprom update " EEPROM_LAYOUT_SPEC EEPROM_DEV_SPEC " field_name field_value\n" " - Update a specific eeprom field with new data.\n" " The new data must be written in the same human readable format as shown by the print command." +#endif +#if CONFIG_IS_ENABLED(I2C_EEPROM) + "\n\n" + "DEVICE SPECIFIER - the eeprom device can be specified\n" + " [dev_name] - by device name (devices can listed with the eeprom list command)\n" + " [[bus] devaddr] - or by I2C bus and I2C device address\n" + "If no device specifier is given, the first driver-model found device is used." +#endif #ifdef CONFIG_EEPROM_LAYOUT_VERSIONS "\n\n" "LAYOUT VERSIONS\n" @@ -471,5 +574,4 @@ U_BOOT_CMD( "The values which can be provided with the -l option are:\n" CONFIG_EEPROM_LAYOUT_HELP_STRING"\n" #endif -#endif ); From 3bdc12856579666d74bf0f93a75c0b152ed56eea Mon Sep 17 00:00:00 2001 From: Emanuele Ghidoli Date: Wed, 15 May 2024 10:00:57 +0200 Subject: [PATCH 100/383] arm: dts: k3-am625-verdin: Update autogenerated LPDDR4 configuration Update the autogenerated LPDDR4 configuration using the latest available SysConfig tool. This changes are cosmetic and are made to track the last used tool version. Signed-off-by: Emanuele Ghidoli --- arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi index 841541bb243..ca883ae82c7 100644 --- a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi +++ b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * This file was generated with the - * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.10 - * Mon Dec 11 2023 17:07:35 GMT+0100 (Central European Standard Time) + * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.10.01 + * Tue May 14 2024 12:55:28 GMT+0200 (Central European Summer Time) * DDR Type: LPDDR4 * F0 = 50MHz F1 = NA F2 = 800MHz * Density (per channel): 16Gb @@ -10,9 +10,11 @@ * Number of Ranks: 1 */ + #define DDRSS_PLL_FHS_CNT 3 #define DDRSS_PLL_FREQUENCY_1 400000000 #define DDRSS_PLL_FREQUENCY_2 400000000 +#define DDRSS_SDRAM_IDX 15 #define DDRSS_CTL_0_DATA 0x00000B00 From 54c93718b38c58160a018bb6a267a6b8b47469c4 Mon Sep 17 00:00:00 2001 From: Emanuele Ghidoli Date: Wed, 15 May 2024 10:00:58 +0200 Subject: [PATCH 101/383] arm: dts: k3-am625-verdin: Enable LPDDR4 WDQS control Manually, since SysConfig tool do not have the relevant option, set PHY_LP4_WDQS_OE_EXTEND to 1. Since WDQS control mode is required on our modules LPDDR4, this enables WDQS control mode 1. Signed-off-by: Emanuele Ghidoli --- arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi index ca883ae82c7..5062447547b 100644 --- a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi +++ b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi @@ -850,7 +850,7 @@ #define DDRSS_PHY_62_DATA 0x00000000 #define DDRSS_PHY_63_DATA 0x00000000 #define DDRSS_PHY_64_DATA 0x00000000 -#define DDRSS_PHY_65_DATA 0x00000004 +#define DDRSS_PHY_65_DATA 0x00000104 #define DDRSS_PHY_66_DATA 0x00000000 #define DDRSS_PHY_67_DATA 0x00000000 #define DDRSS_PHY_68_DATA 0x00000000 @@ -1106,7 +1106,7 @@ #define DDRSS_PHY_318_DATA 0x00000000 #define DDRSS_PHY_319_DATA 0x00000000 #define DDRSS_PHY_320_DATA 0x00000000 -#define DDRSS_PHY_321_DATA 0x00000004 +#define DDRSS_PHY_321_DATA 0x00000104 #define DDRSS_PHY_322_DATA 0x00000000 #define DDRSS_PHY_323_DATA 0x00000000 #define DDRSS_PHY_324_DATA 0x00000000 From 69060c71dde39fd783013dd0db0a46e5f04389ca Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Mon, 20 May 2024 15:29:14 +0530 Subject: [PATCH 102/383] arm: dts: k3-j721e-r5*: Introduce k3-j721e-r5.dtsi Introduce k3-j721e-r5.dtsi to be used by board R5 DTS files. This helps sync SoC changes across boards. Signed-off-by: Neha Malcom Francis Reviewed-by: Manorit Chawdhry --- arch/arm/dts/k3-j721e-r5-beagleboneai64.dts | 78 +----------------- .../arm/dts/k3-j721e-r5-common-proc-board.dts | 75 +---------------- arch/arm/dts/k3-j721e-r5-sk.dts | 75 +---------------- arch/arm/dts/k3-j721e-r5.dtsi | 80 +++++++++++++++++++ 4 files changed, 83 insertions(+), 225 deletions(-) create mode 100644 arch/arm/dts/k3-j721e-r5.dtsi diff --git a/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts b/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts index 43da4dafba8..4f97af4fd94 100644 --- a/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts +++ b/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts @@ -12,84 +12,8 @@ #include "k3-j721e-ddr.dtsi" #include "k3-j721e-beagleboneai64-u-boot.dtsi" +#include "k3-j721e-r5.dtsi" -/ { - aliases { - remoteproc0 = &sysctrler; - remoteproc1 = &a72_0; - }; - - chosen { - tick-timer = &mcu_timer0; - }; - - a72_0: a72@0 { - compatible = "ti,am654-rproc"; - reg = <0x0 0x00a90000 0x0 0x10>; - power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; - resets = <&k3_reset 202 0>; - clocks = <&k3_clks 61 1>; - assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>; - assigned-clock-rates = <2000000000>, <200000000>; - ti,sci = <&dmsc>; - ti,sci-proc-id = <32>; - ti,sci-host-id = <10>; - bootph-pre-ram; - }; - - dm_tifs: dm-tifs { - compatible = "ti,j721e-dm-sci"; - ti,host-id = <3>; - ti,secure-host; - mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_mcu 21>, - <&secure_proxy_mcu 23>; - bootph-pre-ram; - }; -}; - -&dmsc { - mboxes= <&secure_proxy_mcu 6>, - <&secure_proxy_mcu 8>, - <&secure_proxy_mcu 5>; - mbox-names = "rx", "tx", "notify"; - ti,host-id = <4>; - ti,secure-host; -}; - -&mcu_timer0 { - status = "okay"; - bootph-pre-ram; -}; - -&secure_proxy_mcu { - bootph-pre-ram; - /* We require this for boot handshake */ - status = "okay"; -}; - -&cbass_mcu_wakeup { - sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; - mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>; - mbox-names = "tx", "rx"; - bootph-pre-ram; - }; -}; - -&mcu_ringacc { - ti,sci = <&dm_tifs>; -}; - -&mcu_udmap { - ti,sci = <&dm_tifs>; -}; - -&wkup_uart0_pins_default { - bootph-pre-ram; -}; &wkup_i2c0 { bootph-pre-ram; diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index 9655ca21d02..c7e344350c8 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -10,76 +10,7 @@ #include "k3-j721e-ddr.dtsi" #include "k3-j721e-common-proc-board-u-boot.dtsi" -/ { - chosen { - tick-timer = &mcu_timer0; - }; - - aliases { - remoteproc0 = &sysctrler; - remoteproc1 = &a72_0; - }; - - a72_0: a72@0 { - compatible = "ti,am654-rproc"; - reg = <0x0 0x00a90000 0x0 0x10>; - power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; - resets = <&k3_reset 202 0>; - clocks = <&k3_clks 61 1>; - assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>; - assigned-clock-rates = <2000000000>, <200000000>; - ti,sci = <&dmsc>; - ti,sci-proc-id = <32>; - ti,sci-host-id = <10>; - bootph-pre-ram; - }; - - dm_tifs: dm-tifs { - compatible = "ti,j721e-dm-sci"; - ti,host-id = <3>; - ti,secure-host; - mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_mcu 21>, - <&secure_proxy_mcu 23>; - bootph-pre-ram; - }; -}; - -&mcu_timer0 { - status = "okay"; - bootph-pre-ram; -}; - -&dmsc { - mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>; - mbox-names = "tx", "rx", "notify"; - ti,host-id = <4>; - ti,secure-host; -}; - -&secure_proxy_mcu { - bootph-pre-ram; - status = "okay"; -}; - -&cbass_mcu_wakeup { - sysctrler: sysctrler { - bootph-pre-ram; - compatible = "ti,am654-system-controller"; - mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>; - mbox-names = "tx", "rx"; - }; -}; - -&mcu_ringacc { - ti,sci = <&dm_tifs>; -}; - -&mcu_udmap { - ti,sci = <&dm_tifs>; -}; +#include "k3-j721e-r5.dtsi" &wkup_i2c0 { bootph-pre-ram; @@ -111,10 +42,6 @@ }; }; -&wkup_uart0_pins_default { - bootph-pre-ram; -}; - &mcu_uart0_pins_default { bootph-pre-ram; }; diff --git a/arch/arm/dts/k3-j721e-r5-sk.dts b/arch/arm/dts/k3-j721e-r5-sk.dts index b0c108e9693..96a13b2cb2b 100644 --- a/arch/arm/dts/k3-j721e-r5-sk.dts +++ b/arch/arm/dts/k3-j721e-r5-sk.dts @@ -10,80 +10,7 @@ #include "k3-j721e-ddr.dtsi" #include "k3-j721e-sk-u-boot.dtsi" -/ { - chosen { - tick-timer = &mcu_timer0; - }; - - aliases { - remoteproc0 = &sysctrler; - remoteproc1 = &a72_0; - }; - - a72_0: a72@0 { - compatible = "ti,am654-rproc"; - reg = <0x0 0x00a90000 0x0 0x10>; - power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; - resets = <&k3_reset 202 0>; - clocks = <&k3_clks 61 1>; - assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>; - assigned-clock-rates = <2000000000>, <200000000>; - ti,sci = <&dmsc>; - ti,sci-proc-id = <32>; - ti,sci-host-id = <10>; - bootph-pre-ram; - }; - - dm_tifs: dm-tifs { - compatible = "ti,j721e-dm-sci"; - ti,host-id = <3>; - ti,secure-host; - mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_mcu 21>, - <&secure_proxy_mcu 23>; - bootph-pre-ram; - }; -}; - -&mcu_timer0 { - status = "okay"; - bootph-pre-ram; -}; - -&secure_proxy_mcu { - bootph-pre-ram; - status = "okay"; -}; - -&cbass_mcu_wakeup { - sysctrler: sysctrler { - bootph-pre-ram; - compatible = "ti,am654-system-controller"; - mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>; - mbox-names = "tx", "rx"; - }; -}; - -&dmsc { - mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>; - mbox-names = "tx", "rx", "notify"; - ti,host-id = <4>; - ti,secure-host; -}; - -&mcu_ringacc { - ti,sci = <&dm_tifs>; -}; - -&mcu_udmap { - ti,sci = <&dm_tifs>; -}; - -&wkup_uart0_pins_default { - bootph-pre-ram; -}; +#include "k3-j721e-r5.dtsi" &mcu_uart0_pins_default { bootph-pre-ram; diff --git a/arch/arm/dts/k3-j721e-r5.dtsi b/arch/arm/dts/k3-j721e-r5.dtsi new file mode 100644 index 00000000000..fd0d921272c --- /dev/null +++ b/arch/arm/dts/k3-j721e-r5.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/ { + chosen { + tick-timer = &mcu_timer0; + }; + + aliases { + remoteproc0 = &sysctrler; + remoteproc1 = &a72_0; + }; + + a72_0: a72@0 { + compatible = "ti,am654-rproc"; + reg = <0x0 0x00a90000 0x0 0x10>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 202 0>; + clocks = <&k3_clks 61 1>; + assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>; + assigned-clock-rates = <2000000000>, <200000000>; + ti,sci = <&dmsc>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + bootph-pre-ram; + }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <3>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_mcu 21>, + <&secure_proxy_mcu 23>; + bootph-pre-ram; + }; +}; + +&mcu_timer0 { + status = "okay"; + bootph-pre-ram; +}; + +&dmsc { + mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>; + mbox-names = "tx", "rx", "notify"; + ti,host-id = <4>; + ti,secure-host; +}; + +&secure_proxy_mcu { + bootph-pre-ram; + /* We require this for boot handshake */ + status = "okay"; +}; + +&cbass_mcu_wakeup { + sysctrler: sysctrler { + bootph-pre-ram; + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>; + mbox-names = "tx", "rx"; + }; +}; + +&mcu_ringacc { + ti,sci = <&dm_tifs>; +}; + +&mcu_udmap { + ti,sci = <&dm_tifs>; +}; + +&wkup_uart0_pins_default { + bootph-pre-ram; +}; From c9507f07a1d6c92bd1f73fd64384f8c5994be9c2 Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Mon, 20 May 2024 15:29:15 +0530 Subject: [PATCH 103/383] configs: j721e_sk: Move to separate defconfig for J721E SK board Add defconfig for J721E SK R5 and A72 configuration. This includes and modifies the J721E EVM defconfigs: j721e_evm_r5_defconfig -> j721e_sk_r5_defconfig j721e_evm_a72_defconfig -> j721e_sk_a72_defconfig Signed-off-by: Neha Malcom Francis --- arch/arm/dts/k3-j721e-binman.dtsi | 99 ++-------------------------- arch/arm/dts/k3-j721e-sk-u-boot.dtsi | 23 +++++++ board/ti/j721e/MAINTAINERS | 2 + configs/j721e_evm_a72_defconfig | 2 +- configs/j721e_evm_r5_defconfig | 2 +- configs/j721e_sk_a72_defconfig | 9 +++ configs/j721e_sk_r5_defconfig | 10 +++ 7 files changed, 52 insertions(+), 95 deletions(-) create mode 100644 configs/j721e_sk_a72_defconfig create mode 100644 configs/j721e_sk_r5_defconfig diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi index 75a6e9599b9..2867d264664 100644 --- a/arch/arm/dts/k3-j721e-binman.dtsi +++ b/arch/arm/dts/k3-j721e-binman.dtsi @@ -212,10 +212,7 @@ #ifdef CONFIG_TARGET_J721E_A72_EVM #define SPL_J721E_EVM_DTB "spl/dts/k3-j721e-common-proc-board.dtb" -#define SPL_J721E_SK_DTB "spl/dts/k3-j721e-sk.dtb" - #define J721E_EVM_DTB "u-boot.dtb" -#define J721E_SK_DTB "arch/arm/dts/k3-j721e-sk.dtb" &binman { ti-dm { @@ -361,28 +358,13 @@ arch = "arm"; compression = "none"; ti-secure { - content = <&spl_j721e_evm_dtb>; + content = <&spl_j721e_dtb>; keyfile = "custMpk.pem"; }; - spl_j721e_evm_dtb: blob-ext { + spl_j721e_dtb: blob-ext { filename = SPL_J721E_EVM_DTB; }; }; - - fdt-1 { - description = "k3-j721e-sk"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - ti-secure { - content = <&spl_j721e_sk_dtb>; - keyfile = "custMpk.pem"; - - }; - spl_j721e_sk_dtb: blob-ext { - filename = SPL_J721E_SK_DTB; - }; - }; }; configurations { @@ -394,13 +376,6 @@ loadables = "tee", "dm", "spl"; fdt = "fdt-0"; }; - - conf-1 { - description = "k3-j721e-sk"; - firmware = "atf"; - loadables = "tee", "dm", "spl"; - fdt = "fdt-1"; - }; }; }; }; @@ -422,35 +397,17 @@ arch = "arm"; compression = "none"; ti-secure { - content = <&j721e_evm_dtb>; + content = <&j721e_dtb>; keyfile = "custMpk.pem"; }; - j721e_evm_dtb: blob-ext { + j721e_dtb: blob-ext { filename = J721E_EVM_DTB; }; hash { algo = "crc32"; }; }; - - fdt-1 { - description = "k3-j721e-sk"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - ti-secure { - content = <&j721e_sk_dtb>; - keyfile = "custMpk.pem"; - - }; - j721e_sk_dtb: blob-ext { - filename = J721E_SK_DTB; - }; - hash { - algo = "crc32"; - }; - }; }; configurations { @@ -462,13 +419,6 @@ loadables = "uboot"; fdt = "fdt-0"; }; - - conf-1 { - description = "k3-j721e-sk"; - firmware = "uboot"; - loadables = "uboot"; - fdt = "fdt-1"; - }; }; }; }; @@ -491,20 +441,10 @@ type = "flat_dt"; arch = "arm"; compression = "none"; - blob { + spl_j721e_dtb_unsigned: blob { filename = SPL_J721E_EVM_DTB; }; }; - - fdt-1 { - description = "k3-j721e-sk"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - blob { - filename = SPL_J721E_SK_DTB; - }; - }; }; configurations { @@ -516,13 +456,6 @@ loadables = "tee", "dm", "spl"; fdt = "fdt-0"; }; - - conf-1 { - description = "k3-j721e-sk"; - firmware = "atf"; - loadables = "tee", "dm", "spl"; - fdt = "fdt-1"; - }; }; }; }; @@ -543,26 +476,13 @@ type = "flat_dt"; arch = "arm"; compression = "none"; - blob { + j721e_dtb_unsigned: blob { filename = J721E_EVM_DTB; }; hash { algo = "crc32"; }; }; - - fdt-1 { - description = "k3-j721e-sk"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - blob { - filename = J721E_SK_DTB; - }; - hash { - algo = "crc32"; - }; - }; }; configurations { @@ -574,13 +494,6 @@ loadables = "uboot"; fdt = "fdt-0"; }; - - conf-1 { - description = "k3-j721e-sk"; - firmware = "uboot"; - loadables = "uboot"; - fdt = "fdt-1"; - }; }; }; }; diff --git a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi index 8f4f944263e..6d0f7457ccd 100644 --- a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi @@ -155,3 +155,26 @@ bootph-all; }; }; + +#ifdef CONFIG_TARGET_J721E_A72_EVM + +#define SPL_J721E_SK_DTB "spl/dts/k3-j721e-sk.dtb" +#define J721E_SK_DTB "u-boot.dtb" + +&spl_j721e_dtb { + filename = SPL_J721E_SK_DTB; +}; + +&j721e_dtb { + filename = J721E_SK_DTB; +}; + +&spl_j721e_dtb_unsigned { + filename = SPL_J721E_SK_DTB; +}; + +&j721e_dtb_unsigned { + filename = J721E_SK_DTB; +}; + +#endif diff --git a/board/ti/j721e/MAINTAINERS b/board/ti/j721e/MAINTAINERS index f5ca7d06a34..06aba53d9b0 100644 --- a/board/ti/j721e/MAINTAINERS +++ b/board/ti/j721e/MAINTAINERS @@ -5,5 +5,7 @@ F: board/ti/j721e F: include/configs/j721e_evm.h F: configs/j721e_evm_r5_defconfig F: configs/j721e_evm_a72_defconfig +F: configs/j721e_sk_r5_defconfig +F: configs/j721e_sk_a72_defconfig F: configs/j7200_evm_r5_defconfig F: configs/j7200_evm_a72_defconfig diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 3d8e9391987..b8d7c33c45c 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -88,7 +88,7 @@ CONFIG_MMC_SPEED_MODE_SET=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="k3-j721e-common-proc-board k3-j721e-sk" +CONFIG_OF_LIST="k3-j721e-common-proc-board" CONFIG_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index cea48b26136..37d582b7750 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -81,7 +81,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_MULTI_DTB_FIT=y -CONFIG_SPL_OF_LIST="k3-j721e-r5-common-proc-board k3-j721e-r5-sk" +CONFIG_SPL_OF_LIST="k3-j721e-r5-common-proc-board" CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/j721e_sk_a72_defconfig b/configs/j721e_sk_a72_defconfig new file mode 100644 index 00000000000..8907b8ae58f --- /dev/null +++ b/configs/j721e_sk_a72_defconfig @@ -0,0 +1,9 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_J721E=y +CONFIG_TARGET_J721E_A72_EVM=y + +CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-sk" +CONFIG_OF_LIST="k3-j721e-sk" diff --git a/configs/j721e_sk_r5_defconfig b/configs/j721e_sk_r5_defconfig new file mode 100644 index 00000000000..b361c691747 --- /dev/null +++ b/configs/j721e_sk_r5_defconfig @@ -0,0 +1,10 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_J721E=y +CONFIG_TARGET_J721E_R5_EVM=y + +CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-sk" +CONFIG_SPL_OF_LIST="k3-j721e-r5-sk" +CONFIG_OF_LIST="k3-j721e-r5-sk" From 46bb1405b461c491f32a7f9c96c18768f9724b3a Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Mon, 20 May 2024 15:29:16 +0530 Subject: [PATCH 104/383] arm: dts: k3-j721e: Move to OF_UPSTREAM Move to using OF_UPSTREAM config and thus using the devicetree-rebasing subtree. Signed-off-by: Neha Malcom Francis Acked-by: Sumit Garg --- arch/arm/dts/Makefile | 4 +- arch/arm/dts/k3-j721e-binman.dtsi | 2 +- .../k3-j721e-common-proc-board-u-boot.dtsi | 14 +- arch/arm/dts/k3-j721e-common-proc-board.dts | 976 ------ arch/arm/dts/k3-j721e-main.dtsi | 2741 ----------------- arch/arm/dts/k3-j721e-mcu-wakeup.dtsi | 681 ---- arch/arm/dts/k3-j721e-sk-u-boot.dtsi | 20 +- arch/arm/dts/k3-j721e-sk.dts | 1074 ------- arch/arm/dts/k3-j721e-som-p0.dtsi | 446 --- arch/arm/dts/k3-j721e-thermal.dtsi | 75 - arch/arm/dts/k3-j721e.dtsi | 176 -- configs/j721e_evm_a72_defconfig | 5 +- configs/j721e_sk_a72_defconfig | 4 +- 13 files changed, 16 insertions(+), 6202 deletions(-) delete mode 100644 arch/arm/dts/k3-j721e-common-proc-board.dts delete mode 100644 arch/arm/dts/k3-j721e-main.dtsi delete mode 100644 arch/arm/dts/k3-j721e-mcu-wakeup.dtsi delete mode 100644 arch/arm/dts/k3-j721e-sk.dts delete mode 100644 arch/arm/dts/k3-j721e-som-p0.dtsi delete mode 100644 arch/arm/dts/k3-j721e-thermal.dtsi delete mode 100644 arch/arm/dts/k3-j721e.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 087645f3541..2186c8950db 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1226,11 +1226,9 @@ dtb-$(CONFIG_SOC_K3_AM654) += \ k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtbo \ k3-am654-icssg2.dtbo -dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ - k3-j721e-r5-common-proc-board.dtb \ +dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-r5-common-proc-board.dtb \ k3-j7200-common-proc-board.dtb \ k3-j7200-r5-common-proc-board.dtb \ - k3-j721e-sk.dtb \ k3-j721e-r5-sk.dtb \ k3-j721e-beagleboneai64.dtb \ k3-j721e-r5-beagleboneai64.dtb diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi index 2867d264664..244ea63fac2 100644 --- a/arch/arm/dts/k3-j721e-binman.dtsi +++ b/arch/arm/dts/k3-j721e-binman.dtsi @@ -211,7 +211,7 @@ #ifdef CONFIG_TARGET_J721E_A72_EVM -#define SPL_J721E_EVM_DTB "spl/dts/k3-j721e-common-proc-board.dtb" +#define SPL_J721E_EVM_DTB "spl/dts/ti/k3-j721e-common-proc-board.dtb" #define J721E_EVM_DTB "u-boot.dtb" &binman { diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index aa919b40702..1b119f27357 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -15,10 +15,10 @@ &cbass_mcu_wakeup { bootph-all; +}; - chipid@43000014 { - bootph-all; - }; +&chipid { + bootph-all; }; &mcu_navss { @@ -30,14 +30,6 @@ }; &mcu_udmap { - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x284c0000 0x0 0x4000>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x284a0000 0x0 0x4000>, - <0x0 0x2aa00000 0x0 0x40000>, - <0x0 0x28400000 0x0 0x2000>; - reg-names = "gcfg", "rchan", "rchanrt", "tchan", - "tchanrt", "rflow"; bootph-all; }; diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts b/arch/arm/dts/k3-j721e-common-proc-board.dts deleted file mode 100644 index fe5207ac7d8..00000000000 --- a/arch/arm/dts/k3-j721e-common-proc-board.dts +++ /dev/null @@ -1,976 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ - * - * Product Link: https://www.ti.com/tool/J721EXCPXEVM - */ - -/dts-v1/; - -#include "k3-j721e-som-p0.dtsi" -#include -#include -#include -#include - -/ { - compatible = "ti,j721e-evm", "ti,j721e"; - model = "Texas Instruments J721e EVM"; - - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - serial4 = &main_uart2; - serial6 = &main_uart4; - ethernet0 = &cpsw_port1; - mmc0 = &main_sdhci0; - mmc1 = &main_sdhci1; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&sw10_button_pins_default>, <&sw11_button_pins_default>; - - sw10: switch-10 { - label = "GPIO Key USER1"; - linux,code = ; - gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>; - }; - - sw11: switch-11 { - label = "GPIO Key USER2"; - linux,code = ; - gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>; - }; - }; - - evm_12v0: fixedregulator-evm12v0 { - /* main supply */ - compatible = "regulator-fixed"; - regulator-name = "evm_12v0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_3v3: fixedregulator-vsys3v3 { - /* Output of LMS140 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_5v0: fixedregulator-vsys5v0 { - /* Output of LM5140 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_mmc1: fixedregulator-sd { - compatible = "regulator-fixed"; - regulator-name = "vdd_mmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - vin-supply = <&vsys_3v3>; - gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; - }; - - vdd_sd_dv_alt: gpio-regulator-TLV71033 { - compatible = "regulator-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; - regulator-name = "tlv71033"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - vin-supply = <&vsys_5v0>; - gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0>, - <3300000 0x1>; - }; - - sound0: sound-0 { - compatible = "ti,j721e-cpb-audio"; - model = "j721e-cpb"; - - ti,cpb-mcasp = <&mcasp10>; - ti,cpb-codec = <&pcm3168a_1>; - - clocks = <&k3_clks 184 1>, - <&k3_clks 184 2>, <&k3_clks 184 4>, - <&k3_clks 157 371>, - <&k3_clks 157 400>, <&k3_clks 157 401>; - clock-names = "cpb-mcasp-auxclk", - "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100", - "cpb-codec-scki", - "cpb-codec-scki-48000", "cpb-codec-scki-44100"; - }; - - transceiver1: can-phy0 { - compatible = "ti,tcan1043"; - #phy-cells = <0>; - max-bitrate = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; - standby-gpios = <&wkup_gpio0 54 GPIO_ACTIVE_LOW>; - enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>; - }; - - transceiver2: can-phy1 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; - standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; - }; - - transceiver3: can-phy2 { - compatible = "ti,tcan1043"; - #phy-cells = <0>; - max-bitrate = <5000000>; - standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>; - enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; - }; - - transceiver4: can-phy3 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&main_mcan2_gpio_pins_default>; - standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>; - }; - - dp_pwr_3v3: regulator-dp-pwr { - compatible = "regulator-fixed"; - regulator-name = "dp-pwr"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; /* P0 - DP0_PWR_SW_EN */ - enable-active-high; - }; - - dp0: connector { - compatible = "dp-connector"; - label = "DP0"; - type = "full-size"; - dp-pwr-supply = <&dp_pwr_3v3>; - - port { - dp_connector_in: endpoint { - remote-endpoint = <&dp0_out>; - }; - }; - }; -}; - -&main_pmx0 { - main_uart0_pins_default: main-uart0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */ - J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */ - J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ - J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ - >; - }; - - main_uart1_pins_default: main-uart1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */ - J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */ - >; - }; - - main_uart2_pins_default: main-uart2-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1dc, PIN_INPUT, 3) /* (Y1) SPI1_CLK.UART2_RXD */ - J721E_IOPAD(0x1e0, PIN_OUTPUT, 3) /* (Y5) SPI1_D0.UART2_TXD */ - >; - }; - - main_uart4_pins_default: main-uart4-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x190, PIN_INPUT, 1) /* (W23) RGMII6_TD3.UART4_RXD */ - J721E_IOPAD(0x194, PIN_OUTPUT, 1) /* (W28) RGMII6_TD2.UART4_TXD */ - >; - }; - - sw10_button_pins_default: sw10-button-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */ - >; - }; - - main_mmc1_pins_default: main-mmc1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ - J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ - J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ - J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ - J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ - J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ - J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ - J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ - J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */ - >; - }; - - vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ - >; - }; - - main_usbss0_pins_default: main-usbss0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ - J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ - >; - }; - - main_usbss1_pins_default: main-usbss1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ - >; - }; - - dp0_pins_default: dp0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ - >; - }; - - main_i2c1_exp4_pins_default: main-i2c1-exp4-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */ - >; - }; - - main_i2c0_pins_default: main-i2c0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ - J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ - >; - }; - - main_i2c1_pins_default: main-i2c1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ - J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ - >; - }; - - main_i2c3_pins_default: main-i2c3-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ - J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ - >; - }; - - main_i2c6_pins_default: main-i2c6-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ - J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ - >; - }; - - mcasp10_pins_default: mcasp10-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */ - J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */ - J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */ - J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */ - J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */ - J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */ - J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */ - J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */ - J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */ - >; - }; - - audi_ext_refclk2_pins_default: audi-ext-refclk2-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */ - >; - }; - - main_mcan0_pins_default: main-mcan0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */ - J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */ - >; - }; - - main_mcan2_pins_default: main-mcan2-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x01f0, PIN_INPUT, 3) /* (AC2) MCAN2_RX.GPIO0_123 */ - J721E_IOPAD(0x01f4, PIN_OUTPUT, 3) /* (AB1) MCAN2_TX.GPIO0_124 */ - >; - }; - - main_mcan2_gpio_pins_default: main-mcan2-gpio-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ - >; - }; -}; - -&wkup_pmx0 { - wkup_uart0_pins_default: wkup-uart0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ - J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ - >; - }; - - mcu_uart0_pins_default: mcu-uart0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */ - J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */ - J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ - J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ - >; - }; - - sw11_button_pins_default: sw11-button-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */ - >; - }; - - mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */ - J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */ - J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */ - J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */ - J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */ - J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */ - J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */ - J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */ - >; - }; - - mcu_cpsw_pins_default: mcu-cpsw-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ - J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ - J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ - J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ - J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ - J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ - J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ - J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ - J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ - J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ - J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ - J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ - >; - }; - - mcu_mdio_pins_default: mcu-mdio1-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */ - J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */ - >; - }; - - mcu_mcan0_pins_default: mcu-mcan0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */ - J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */ - >; - }; - - mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* (F26) WKUP_GPIO0_0 */ - J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */ - >; - }; - - mcu_mcan1_pins_default: mcu-mcan1-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */ - J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */ - >; - }; - - mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */ - >; - }; - - wkup_gpio_pins_default: wkup-gpio-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */ - >; - }; -}; - -&wkup_uart0 { - /* Wakeup UART is used by System firmware */ - status = "reserved"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_uart0_pins_default>; -}; - -&mcu_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_uart0_pins_default>; -}; - -&main_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart0_pins_default>; - /* Shared with ATF on this platform */ - power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; -}; - -&main_uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart1_pins_default>; -}; - -&main_uart2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart2_pins_default>; -}; - -&main_uart4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart4_pins_default>; -}; - -&wkup_gpio0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_gpio_pins_default>; -}; - -&main_gpio0 { - status = "okay"; -}; - -&main_gpio1 { - status = "okay"; -}; - -&main_sdhci0 { - /* eMMC */ - status = "okay"; - non-removable; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&main_sdhci1 { - /* SD/MMC */ - status = "okay"; - vmmc-supply = <&vdd_mmc1>; - vqmmc-supply = <&vdd_sd_dv_alt>; - pinctrl-names = "default"; - pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&usb_serdes_mux { - idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */ -}; - -&serdes_ln_ctrl { - idle-states = , , - , , - , , - , , - , , - , ; -}; - -&serdes_wiz3 { - typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; - typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ -}; - -&serdes3 { - serdes3_usb_link: phy@0 { - reg = <0>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = ; - resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; - }; -}; - -&usbss0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_usbss0_pins_default>; - ti,vbus-divider; -}; - -&usb0 { - dr_mode = "otg"; - maximum-speed = "super-speed"; - phys = <&serdes3_usb_link>; - phy-names = "cdns3,usb3-phy"; -}; - -&usbss1 { - pinctrl-names = "default"; - pinctrl-0 = <&main_usbss1_pins_default>; - ti,usb2-only; -}; - -&usb1 { - dr_mode = "host"; - maximum-speed = "high-speed"; -}; - -&ospi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - spi-max-frequency = <40000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <2>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "qspi.tiboot3"; - reg = <0x0 0x80000>; - }; - - partition@80000 { - label = "qspi.tispl"; - reg = <0x80000 0x200000>; - }; - - partition@280000 { - label = "qspi.u-boot"; - reg = <0x280000 0x400000>; - }; - - partition@680000 { - label = "qspi.env"; - reg = <0x680000 0x20000>; - }; - - partition@6a0000 { - label = "qspi.env.backup"; - reg = <0x6a0000 0x20000>; - }; - - partition@6c0000 { - label = "qspi.sysfw"; - reg = <0x6c0000 0x100000>; - }; - - partition@800000 { - label = "qspi.rootfs"; - reg = <0x800000 0x37c0000>; - }; - - partition@3fe0000 { - label = "qspi.phypattern"; - reg = <0x3fe0000 0x20000>; - }; - }; - }; -}; - -&tscadc0 { - status = "okay"; - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&tscadc1 { - status = "okay"; - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&main_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - exp1: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - exp2: gpio@22 { - compatible = "ti,tca6424"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - - p09-hog { - /* P11 - MCASP/TRACE_MUX_S0 */ - gpio-hog; - gpios = <9 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "MCASP/TRACE_MUX_S0"; - }; - - p10-hog { - /* P12 - MCASP/TRACE_MUX_S1 */ - gpio-hog; - gpios = <10 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "MCASP/TRACE_MUX_S1"; - }; - }; -}; - -&main_i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_pins_default>; - clock-frequency = <400000>; - - exp4: gpio@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_exp4_pins_default>; - interrupt-parent = <&main_gpio1>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&k3_clks { - /* Confiure AUDIO_EXT_REFCLK2 pin as output */ - pinctrl-names = "default"; - pinctrl-0 = <&audi_ext_refclk2_pins_default>; -}; - -&main_i2c3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c3_pins_default>; - clock-frequency = <400000>; - - exp3: gpio@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - pcm3168a_1: audio-codec@44 { - compatible = "ti,pcm3168a"; - reg = <0x44>; - - #sound-dai-cells = <1>; - - reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>; - - /* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */ - clocks = <&k3_clks 157 371>; - clock-names = "scki"; - - /* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */ - assigned-clocks = <&k3_clks 157 371>; - assigned-clock-parents = <&k3_clks 157 400>; - assigned-clock-rates = <24576000>; /* for 48KHz */ - - VDD1-supply = <&vsys_3v3>; - VDD2-supply = <&vsys_3v3>; - VCCAD1-supply = <&vsys_5v0>; - VCCAD2-supply = <&vsys_5v0>; - VCCDA1-supply = <&vsys_5v0>; - VCCDA2-supply = <&vsys_5v0>; - }; -}; - -&main_i2c6 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c6_pins_default>; - clock-frequency = <400000>; - - exp5: gpio@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&mcu_cpsw { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; -}; - -&davinci_mdio { - phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = ; - ti,fifo-depth = ; - }; -}; - -&cpsw_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&phy0>; -}; - -&dss { - /* - * These clock assignments are chosen to enable the following outputs: - * - * VP0 - DisplayPort SST - * VP1 - DPI0 - * VP2 - DSI - * VP3 - DPI1 - */ - - assigned-clocks = <&k3_clks 152 1>, - <&k3_clks 152 4>, - <&k3_clks 152 9>, - <&k3_clks 152 13>; - assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ - <&k3_clks 152 6>, /* PLL19_HSDIV0 */ - <&k3_clks 152 11>, /* PLL18_HSDIV0 */ - <&k3_clks 152 18>; /* PLL23_HSDIV0 */ -}; - -&dss_ports { - port { - dpi0_out: endpoint { - remote-endpoint = <&dp0_in>; - }; - }; -}; - -&dp0_ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dp0_in: endpoint { - remote-endpoint = <&dpi0_out>; - }; - }; - - port@4 { - reg = <4>; - dp0_out: endpoint { - remote-endpoint = <&dp_connector_in>; - }; - }; -}; - -&mcasp10 { - status = "okay"; - #sound-dai-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&mcasp10_pins_default>; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - auxclk-fs-ratio = <256>; - - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 1 1 1 - 2 2 2 0 - >; - tx-num-evt = <0>; - rx-num-evt = <0>; -}; - -&cmn_refclk1 { - clock-frequency = <100000000>; -}; - -&wiz0_pll1_refclk { - assigned-clocks = <&wiz0_pll1_refclk>; - assigned-clock-parents = <&cmn_refclk1>; -}; - -&wiz0_refclk_dig { - assigned-clocks = <&wiz0_refclk_dig>; - assigned-clock-parents = <&cmn_refclk1>; -}; - -&wiz1_pll1_refclk { - assigned-clocks = <&wiz1_pll1_refclk>; - assigned-clock-parents = <&cmn_refclk1>; -}; - -&wiz1_refclk_dig { - assigned-clocks = <&wiz1_refclk_dig>; - assigned-clock-parents = <&cmn_refclk1>; -}; - -&wiz2_pll1_refclk { - assigned-clocks = <&wiz2_pll1_refclk>; - assigned-clock-parents = <&cmn_refclk1>; -}; - -&wiz2_refclk_dig { - assigned-clocks = <&wiz2_refclk_dig>; - assigned-clock-parents = <&cmn_refclk1>; -}; - -&serdes0 { - assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>; - assigned-clock-parents = <&wiz0_pll1_refclk>; - - serdes0_pcie_link: phy@0 { - reg = <0>; - cdns,num-lanes = <1>; - #phy-cells = <0>; - cdns,phy-type = ; - resets = <&serdes_wiz0 1>; - }; -}; - -&serdes1 { - assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>; - assigned-clock-parents = <&wiz1_pll1_refclk>; - - serdes1_pcie_link: phy@0 { - reg = <0>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = ; - resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; - }; -}; - -&serdes2 { - assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>; - assigned-clock-parents = <&wiz2_pll1_refclk>; - - serdes2_pcie_link: phy@0 { - reg = <0>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = ; - resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>; - }; -}; - -&serdes4 { - torrent_phy_dp: phy@0 { - reg = <0>; - resets = <&serdes_wiz4 1>; - cdns,phy-type = ; - cdns,num-lanes = <4>; - cdns,max-bit-rate = <5400>; - #phy-cells = <0>; - }; -}; - -&mhdp { - phys = <&torrent_phy_dp>; - phy-names = "dpphy"; - pinctrl-names = "default"; - pinctrl-0 = <&dp0_pins_default>; -}; - -&pcie0_rc { - status = "okay"; - reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <1>; -}; - -&pcie1_rc { - status = "okay"; - reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; - phys = <&serdes1_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; -}; - -&pcie2_rc { - status = "okay"; - reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>; - phys = <&serdes2_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; -}; - -&mcu_mcan0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan0_pins_default>; - phys = <&transceiver1>; -}; - -&mcu_mcan1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan1_pins_default>; - phys = <&transceiver2>; -}; - -&main_mcan0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mcan0_pins_default>; - phys = <&transceiver3>; -}; - -&main_mcan2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mcan2_pins_default>; - phys = <&transceiver4>; -}; diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi deleted file mode 100644 index 746b9f8b1c6..00000000000 --- a/arch/arm/dts/k3-j721e-main.dtsi +++ /dev/null @@ -1,2741 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J721E SoC Family Main Domain peripherals - * - * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ - */ -#include -#include -#include - -#include "k3-serdes.h" - -/ { - cmn_refclk: clock-cmnrefclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - cmn_refclk1: clock-cmnrefclk1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; -}; - -&cbass_main { - msmc_ram: sram@70000000 { - compatible = "mmio-sram"; - reg = <0x0 0x70000000 0x0 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x70000000 0x800000>; - - atf-sram@0 { - reg = <0x0 0x20000>; - }; - }; - - scm_conf: scm-conf@100000 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x00100000 0x1c000>; - - serdes_ln_ctrl: mux-controller@4080 { - compatible = "mmio-mux"; - reg = <0x00004080 0x50>; - #mux-control-cells = <1>; - mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ - <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ - <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ - <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ - <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; - /* SERDES4 lane0/1/2/3 select */ - idle-states = , , - , , - , , - , , - , , - , ; - }; - - cpsw0_phy_gmii_sel: phy@4044 { - compatible = "ti,j721e-cpsw9g-phy-gmii-sel"; - ti,qsgmii-main-ports = <2>, <2>; - reg = <0x4044 0x20>; - #phy-cells = <1>; - }; - - usb_serdes_mux: mux-controller@4000 { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ - <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ - }; - - ehrpwm_tbclk: clock-controller@4140 { - compatible = "ti,am654-ehrpwm-tbclk"; - reg = <0x4140 0x18>; - #clock-cells = <1>; - }; - }; - - main_ehrpwm0: pwm@3000000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3000000 0x00 0x100>; - power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm1: pwm@3010000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3010000 0x00 0x100>; - power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm2: pwm@3020000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3020000 0x00 0x100>; - power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm3: pwm@3030000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3030000 0x00 0x100>; - power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm4: pwm@3040000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3040000 0x00 0x100>; - power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm5: pwm@3050000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3050000 0x00 0x100>; - power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - gic500: interrupt-controller@1800000 { - compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ - <0x00 0x01900000 0x00 0x100000>, /* GICR */ - <0x00 0x6f000000 0x00 0x2000>, /* GICC */ - <0x00 0x6f010000 0x00 0x1000>, /* GICH */ - <0x00 0x6f020000 0x00 0x2000>; /* GICV */ - - /* vcpumntirq: virtual CPU interface maintenance interrupt */ - interrupts = ; - - gic_its: msi-controller@1820000 { - compatible = "arm,gic-v3-its"; - reg = <0x00 0x01820000 0x00 0x10000>; - socionext,synquacer-pre-its = <0x1000000 0x400000>; - msi-controller; - #msi-cells = <1>; - }; - }; - - main_gpio_intr: interrupt-controller@a00000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x00a00000 0x00 0x800>; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <131>; - ti,interrupt-ranges = <8 392 56>; - }; - - main_navss: bus@30000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; - dma-coherent; - dma-ranges; - - ti,sci-dev-id = <199>; - - main_navss_intr: interrupt-controller@310e0000 { - compatible = "ti,sci-intr"; - reg = <0x0 0x310e0000 0x0 0x4000>; - ti,intr-trigger-type = <4>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <213>; - ti,interrupt-ranges = <0 64 64>, - <64 448 64>, - <128 672 64>; - }; - - main_udmass_inta: interrupt-controller@33d00000 { - compatible = "ti,sci-inta"; - reg = <0x0 0x33d00000 0x0 0x100000>; - interrupt-controller; - interrupt-parent = <&main_navss_intr>; - msi-controller; - #interrupt-cells = <0>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <209>; - ti,interrupt-ranges = <0 0 256>; - }; - - secure_proxy_main: mailbox@32c00000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x00 0x32c00000 0x00 0x100000>, - <0x00 0x32400000 0x00 0x100000>, - <0x00 0x32800000 0x00 0x100000>; - interrupt-names = "rx_011"; - interrupts = ; - }; - - smmu0: iommu@36600000 { - compatible = "arm,smmu-v3"; - reg = <0x0 0x36600000 0x0 0x100000>; - interrupt-parent = <&gic500>; - interrupts = , - ; - interrupt-names = "eventq", "gerror"; - #iommu-cells = <1>; - }; - - hwspinlock: spinlock@30e00000 { - compatible = "ti,am654-hwspinlock"; - reg = <0x00 0x30e00000 0x00 0x1000>; - #hwlock-cells = <1>; - }; - - mailbox0_cluster0: mailbox@31f80000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f80000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster1: mailbox@31f81000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f81000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster2: mailbox@31f82000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f82000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster3: mailbox@31f83000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f83000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster4: mailbox@31f84000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f84000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster5: mailbox@31f85000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f85000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster6: mailbox@31f86000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f86000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster7: mailbox@31f87000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f87000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster8: mailbox@31f88000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f88000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster9: mailbox@31f89000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f89000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster10: mailbox@31f8a000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f8a000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster11: mailbox@31f8b000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f8b000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - main_ringacc: ringacc@3c000000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x3c000000 0x0 0x400000>, - <0x0 0x38000000 0x0 0x400000>, - <0x0 0x31120000 0x0 0x100>, - <0x0 0x33000000 0x0 0x40000>, - <0x0 0x31080000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; - ti,num-rings = <1024>; - ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ - ti,sci = <&dmsc>; - ti,sci-dev-id = <211>; - msi-parent = <&main_udmass_inta>; - }; - - main_udmap: dma-controller@31150000 { - compatible = "ti,j721e-navss-main-udmap"; - reg = <0x0 0x31150000 0x0 0x100>, - <0x0 0x34000000 0x0 0x100000>, - <0x0 0x35000000 0x0 0x100000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&main_udmass_inta>; - #dma-cells = <1>; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <212>; - ti,ringacc = <&main_ringacc>; - - ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ - <0x0f>, /* TX_HCHAN */ - <0x10>; /* TX_UHCHAN */ - ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ - <0x0b>, /* RX_HCHAN */ - <0x0c>; /* RX_UHCHAN */ - ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ - }; - - cpts@310d0000 { - compatible = "ti,j721e-cpts"; - reg = <0x0 0x310d0000 0x0 0x400>; - reg-names = "cpts"; - clocks = <&k3_clks 201 1>; - clock-names = "cpts"; - interrupts-extended = <&main_navss_intr 391>; - interrupt-names = "cpts"; - ti,cpts-periodic-outputs = <6>; - ti,cpts-ext-ts-inputs = <8>; - }; - }; - - cpsw0: ethernet@c000000 { - compatible = "ti,j721e-cpswxg-nuss"; - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0xc000000 0x0 0x200000>; - reg-names = "cpsw_nuss"; - ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>; - clocks = <&k3_clks 19 89>; - clock-names = "fck"; - power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; - - dmas = <&main_udmap 0xca00>, - <&main_udmap 0xca01>, - <&main_udmap 0xca02>, - <&main_udmap 0xca03>, - <&main_udmap 0xca04>, - <&main_udmap 0xca05>, - <&main_udmap 0xca06>, - <&main_udmap 0xca07>, - <&main_udmap 0x4a00>; - dma-names = "tx0", "tx1", "tx2", "tx3", - "tx4", "tx5", "tx6", "tx7", - "rx"; - - status = "disabled"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - cpsw0_port1: port@1 { - reg = <1>; - ti,mac-only; - label = "port1"; - status = "disabled"; - }; - - cpsw0_port2: port@2 { - reg = <2>; - ti,mac-only; - label = "port2"; - status = "disabled"; - }; - - cpsw0_port3: port@3 { - reg = <3>; - ti,mac-only; - label = "port3"; - status = "disabled"; - }; - - cpsw0_port4: port@4 { - reg = <4>; - ti,mac-only; - label = "port4"; - status = "disabled"; - }; - - cpsw0_port5: port@5 { - reg = <5>; - ti,mac-only; - label = "port5"; - status = "disabled"; - }; - - cpsw0_port6: port@6 { - reg = <6>; - ti,mac-only; - label = "port6"; - status = "disabled"; - }; - - cpsw0_port7: port@7 { - reg = <7>; - ti,mac-only; - label = "port7"; - status = "disabled"; - }; - - cpsw0_port8: port@8 { - reg = <8>; - ti,mac-only; - label = "port8"; - status = "disabled"; - }; - }; - - cpsw9g_mdio: mdio@f00 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x0 0xf00 0x0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 19 89>; - clock-names = "fck"; - bus_freq = <1000000>; - status = "disabled"; - }; - - cpts@3d000 { - compatible = "ti,j721e-cpts"; - reg = <0x0 0x3d000 0x0 0x400>; - clocks = <&k3_clks 19 16>; - clock-names = "cpts"; - interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cpts"; - ti,cpts-ext-ts-inputs = <4>; - ti,cpts-periodic-outputs = <2>; - }; - }; - - main_crypto: crypto@4e00000 { - compatible = "ti,j721e-sa2ul"; - reg = <0x0 0x4e00000 0x0 0x1200>; - power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; - - dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, - <&main_udmap 0x4001>; - dma-names = "tx", "rx1", "rx2"; - - rng: rng@4e10000 { - compatible = "inside-secure,safexcel-eip76"; - reg = <0x0 0x4e10000 0x0 0x7d>; - interrupts = ; - }; - }; - - main_pmx0: pinctrl@11c000 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x0 0x11c000 0x0 0x2b4>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ - main_timerio_input: pinctrl@104200 { - compatible = "pinctrl-single"; - reg = <0x00 0x104200 0x00 0x50>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x00000007>; - }; - - /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ - main_timerio_output: pinctrl@104280 { - compatible = "pinctrl-single"; - reg = <0x00 0x104280 0x00 0x20>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000001f>; - }; - - serdes_wiz0: wiz@5000000 { - compatible = "ti,j721e-wiz-16g"; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; - clock-names = "fck", "core_ref_clk", "ext_ref_clk"; - assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; - assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; - num-lanes = <2>; - #reset-cells = <1>; - ranges = <0x5000000 0x0 0x5000000 0x10000>; - - wiz0_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 292 11>, <&cmn_refclk>; - #clock-cells = <0>; - assigned-clocks = <&wiz0_pll0_refclk>; - assigned-clock-parents = <&k3_clks 292 11>; - }; - - wiz0_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 292 0>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz0_pll1_refclk>; - assigned-clock-parents = <&k3_clks 292 0>; - }; - - wiz0_refclk_dig: refclk-dig { - clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz0_refclk_dig>; - assigned-clock-parents = <&k3_clks 292 11>; - }; - - wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { - clocks = <&wiz0_refclk_dig>; - #clock-cells = <0>; - }; - - wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { - clocks = <&wiz0_pll1_refclk>; - #clock-cells = <0>; - }; - - serdes0: serdes@5000000 { - compatible = "ti,sierra-phy-t0"; - reg-names = "serdes"; - reg = <0x5000000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - resets = <&serdes_wiz0 0>; - reset-names = "sierra_reset"; - clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, - <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", - "pll0_refclk", "pll1_refclk"; - }; - }; - - serdes_wiz1: wiz@5010000 { - compatible = "ti,j721e-wiz-16g"; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; - clock-names = "fck", "core_ref_clk", "ext_ref_clk"; - assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; - assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; - num-lanes = <2>; - #reset-cells = <1>; - ranges = <0x5010000 0x0 0x5010000 0x10000>; - - wiz1_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 293 13>, <&cmn_refclk>; - #clock-cells = <0>; - assigned-clocks = <&wiz1_pll0_refclk>; - assigned-clock-parents = <&k3_clks 293 13>; - }; - - wiz1_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 293 0>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz1_pll1_refclk>; - assigned-clock-parents = <&k3_clks 293 0>; - }; - - wiz1_refclk_dig: refclk-dig { - clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz1_refclk_dig>; - assigned-clock-parents = <&k3_clks 293 13>; - }; - - wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div { - clocks = <&wiz1_refclk_dig>; - #clock-cells = <0>; - }; - - wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { - clocks = <&wiz1_pll1_refclk>; - #clock-cells = <0>; - }; - - serdes1: serdes@5010000 { - compatible = "ti,sierra-phy-t0"; - reg-names = "serdes"; - reg = <0x5010000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - resets = <&serdes_wiz1 0>; - reset-names = "sierra_reset"; - clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, - <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", - "pll0_refclk", "pll1_refclk"; - }; - }; - - serdes_wiz2: wiz@5020000 { - compatible = "ti,j721e-wiz-16g"; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; - clock-names = "fck", "core_ref_clk", "ext_ref_clk"; - assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; - assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; - num-lanes = <2>; - #reset-cells = <1>; - ranges = <0x5020000 0x0 0x5020000 0x10000>; - - wiz2_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 294 11>, <&cmn_refclk>; - #clock-cells = <0>; - assigned-clocks = <&wiz2_pll0_refclk>; - assigned-clock-parents = <&k3_clks 294 11>; - }; - - wiz2_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 294 0>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz2_pll1_refclk>; - assigned-clock-parents = <&k3_clks 294 0>; - }; - - wiz2_refclk_dig: refclk-dig { - clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz2_refclk_dig>; - assigned-clock-parents = <&k3_clks 294 11>; - }; - - wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { - clocks = <&wiz2_refclk_dig>; - #clock-cells = <0>; - }; - - wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { - clocks = <&wiz2_pll1_refclk>; - #clock-cells = <0>; - }; - - serdes2: serdes@5020000 { - compatible = "ti,sierra-phy-t0"; - reg-names = "serdes"; - reg = <0x5020000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - resets = <&serdes_wiz2 0>; - reset-names = "sierra_reset"; - clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, - <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", - "pll0_refclk", "pll1_refclk"; - }; - }; - - serdes_wiz3: wiz@5030000 { - compatible = "ti,j721e-wiz-16g"; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; - clock-names = "fck", "core_ref_clk", "ext_ref_clk"; - assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; - assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; - num-lanes = <2>; - #reset-cells = <1>; - ranges = <0x5030000 0x0 0x5030000 0x10000>; - - wiz3_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 295 9>, <&cmn_refclk>; - #clock-cells = <0>; - assigned-clocks = <&wiz3_pll0_refclk>; - assigned-clock-parents = <&k3_clks 295 9>; - }; - - wiz3_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 295 0>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz3_pll1_refclk>; - assigned-clock-parents = <&k3_clks 295 0>; - }; - - wiz3_refclk_dig: refclk-dig { - clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz3_refclk_dig>; - assigned-clock-parents = <&k3_clks 295 9>; - }; - - wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { - clocks = <&wiz3_refclk_dig>; - #clock-cells = <0>; - }; - - wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { - clocks = <&wiz3_pll1_refclk>; - #clock-cells = <0>; - }; - - serdes3: serdes@5030000 { - compatible = "ti,sierra-phy-t0"; - reg-names = "serdes"; - reg = <0x5030000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - resets = <&serdes_wiz3 0>; - reset-names = "sierra_reset"; - clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, - <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", - "pll0_refclk", "pll1_refclk"; - }; - }; - - pcie0_rc: pcie@2900000 { - compatible = "ti,j721e-pcie-host"; - reg = <0x00 0x02900000 0x00 0x1000>, - <0x00 0x02907000 0x00 0x400>, - <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x10000000 0x00 0x00001000>; - reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - interrupt-names = "link_state"; - interrupts = ; - device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 239 1>; - clock-names = "fck"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - vendor-id = <0x104c>; - device-id = <0xb00d>; - msi-map = <0x0 &gic_its 0x0 0x10000>; - dma-coherent; - ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, - <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; - dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - status = "disabled"; - }; - - pcie1_rc: pcie@2910000 { - compatible = "ti,j721e-pcie-host"; - reg = <0x00 0x02910000 0x00 0x1000>, - <0x00 0x02917000 0x00 0x400>, - <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x00001000>; - reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - interrupt-names = "link_state"; - interrupts = ; - device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 240 1>; - clock-names = "fck"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - vendor-id = <0x104c>; - device-id = <0xb00d>; - msi-map = <0x0 &gic_its 0x10000 0x10000>; - dma-coherent; - ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, - <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; - dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - status = "disabled"; - }; - - pcie2_rc: pcie@2920000 { - compatible = "ti,j721e-pcie-host"; - reg = <0x00 0x02920000 0x00 0x1000>, - <0x00 0x02927000 0x00 0x400>, - <0x00 0x0e000000 0x00 0x00800000>, - <0x44 0x00000000 0x00 0x00001000>; - reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - interrupt-names = "link_state"; - interrupts = ; - device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 241 1>; - clock-names = "fck"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - vendor-id = <0x104c>; - device-id = <0xb00d>; - msi-map = <0x0 &gic_its 0x20000 0x10000>; - dma-coherent; - ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, - <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; - dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - status = "disabled"; - }; - - pcie3_rc: pcie@2930000 { - compatible = "ti,j721e-pcie-host"; - reg = <0x00 0x02930000 0x00 0x1000>, - <0x00 0x02937000 0x00 0x400>, - <0x00 0x0e800000 0x00 0x00800000>, - <0x44 0x10000000 0x00 0x00001000>; - reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - interrupt-names = "link_state"; - interrupts = ; - device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 242 1>; - clock-names = "fck"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - vendor-id = <0x104c>; - device-id = <0xb00d>; - msi-map = <0x0 &gic_its 0x30000 0x10000>; - dma-coherent; - ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, - <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; - dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - status = "disabled"; - }; - - serdes_wiz4: wiz@5050000 { - compatible = "ti,am64-wiz-10g"; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>; - clock-names = "fck", "core_ref_clk", "ext_ref_clk"; - assigned-clocks = <&k3_clks 297 9>; - assigned-clock-parents = <&k3_clks 297 10>; - assigned-clock-rates = <19200000>; - num-lanes = <4>; - #reset-cells = <1>; - #clock-cells = <1>; - ranges = <0x05050000 0x00 0x05050000 0x010000>, - <0x0a030a00 0x00 0x0a030a00 0x40>; - - serdes4: serdes@5050000 { - /* - * Note: we also map DPTX PHY registers as the Torrent - * needs to manage those. - */ - compatible = "ti,j721e-serdes-10g"; - reg = <0x05050000 0x010000>, - <0x0a030a00 0x40>; /* DPTX PHY */ - reg-names = "torrent_phy", "dptx_phy"; - - resets = <&serdes_wiz4 0>; - reset-names = "torrent_reset"; - clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>; - clock-names = "refclk"; - assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, - <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, - <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; - assigned-clock-parents = <&k3_clks 297 9>, - <&k3_clks 297 9>, - <&k3_clks 297 9>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - main_timer0: timer@2400000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2400000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 49 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 49 1>; - assigned-clock-parents = <&k3_clks 49 2>; - power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer1: timer@2410000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2410000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 50 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>; - assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>; - power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer2: timer@2420000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2420000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 51 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 51 1>; - assigned-clock-parents = <&k3_clks 51 2>; - power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer3: timer@2430000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2430000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 52 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>; - assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>; - power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer4: timer@2440000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2440000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 53 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 53 1>; - assigned-clock-parents = <&k3_clks 53 2>; - power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer5: timer@2450000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2450000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 54 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>; - assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>; - power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer6: timer@2460000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2460000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 55 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 55 1>; - assigned-clock-parents = <&k3_clks 55 2>; - power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer7: timer@2470000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2470000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 57 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>; - assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>; - power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer8: timer@2480000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2480000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 58 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 58 1>; - assigned-clock-parents = <&k3_clks 58 2>; - power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer9: timer@2490000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2490000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 59 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>; - assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>; - power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer10: timer@24a0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24a0000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 60 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 60 1>; - assigned-clock-parents = <&k3_clks 60 2>; - power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer11: timer@24b0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24b0000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 62 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>; - assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>; - power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer12: timer@24c0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24c0000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 63 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 63 1>; - assigned-clock-parents = <&k3_clks 63 2>; - power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer13: timer@24d0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24d0000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 64 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>; - assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>; - power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer14: timer@24e0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24e0000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 65 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 65 1>; - assigned-clock-parents = <&k3_clks 65 2>; - power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer15: timer@24f0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24f0000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 66 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>; - assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>; - power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer16: timer@2500000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2500000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 67 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 67 1>; - assigned-clock-parents = <&k3_clks 67 2>; - power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer17: timer@2510000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2510000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 68 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>; - assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>; - power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer18: timer@2520000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2520000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 69 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 69 1>; - assigned-clock-parents = <&k3_clks 69 2>; - power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer19: timer@2530000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2530000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 70 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>; - assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>; - power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_uart0: serial@2800000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02800000 0x00 0x100>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 146 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart1: serial@2810000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02810000 0x00 0x100>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 278 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart2: serial@2820000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02820000 0x00 0x100>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 279 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart3: serial@2830000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02830000 0x00 0x100>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 280 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart4: serial@2840000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02840000 0x00 0x100>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 281 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart5: serial@2850000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02850000 0x00 0x100>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 282 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart6: serial@2860000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02860000 0x00 0x100>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 283 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart7: serial@2870000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02870000 0x00 0x100>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 284 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart8: serial@2880000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02880000 0x00 0x100>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 285 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart9: serial@2890000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02890000 0x00 0x100>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 286 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_gpio0: gpio@600000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00600000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <256>, <257>, <258>, <259>, - <260>, <261>, <262>, <263>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <128>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 105 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio1: gpio@601000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00601000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <288>, <289>, <290>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <36>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 106 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio2: gpio@610000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00610000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <264>, <265>, <266>, <267>, - <268>, <269>, <270>, <271>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <128>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 107 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio3: gpio@611000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00611000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <292>, <293>, <294>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <36>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 108 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio4: gpio@620000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00620000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <272>, <273>, <274>, <275>, - <276>, <277>, <278>, <279>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <128>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 109 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio5: gpio@621000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00621000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <296>, <297>, <298>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <36>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 110 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio6: gpio@630000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00630000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <280>, <281>, <282>, <283>, - <284>, <285>, <286>, <287>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <128>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 111 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio7: gpio@631000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00631000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <300>, <301>, <302>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <36>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 112 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_sdhci0: mmc@4f80000 { - compatible = "ti,j721e-sdhci-8bit"; - reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; - interrupts = ; - power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_ahb", "clk_xin"; - clocks = <&k3_clks 91 0>, <&k3_clks 91 1>; - assigned-clocks = <&k3_clks 91 1>; - assigned-clock-parents = <&k3_clks 91 2>; - bus-width = <8>; - mmc-hs200-1_8v; - mmc-ddr-1_8v; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-mmc-hs = <0x0>; - ti,otap-del-sel-ddr52 = <0x5>; - ti,otap-del-sel-hs200 = <0x6>; - ti,otap-del-sel-hs400 = <0x0>; - ti,itap-del-sel-legacy = <0x10>; - ti,itap-del-sel-mmc-hs = <0xa>; - ti,itap-del-sel-ddr52 = <0x3>; - ti,trm-icp = <0x8>; - dma-coherent; - status = "disabled"; - }; - - main_sdhci1: mmc@4fb0000 { - compatible = "ti,j721e-sdhci-4bit"; - reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; - interrupts = ; - power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_ahb", "clk_xin"; - clocks = <&k3_clks 92 5>, <&k3_clks 92 0>; - assigned-clocks = <&k3_clks 92 0>; - assigned-clock-parents = <&k3_clks 92 1>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0xf>; - ti,otap-del-sel-sdr25 = <0xf>; - ti,otap-del-sel-sdr50 = <0xc>; - ti,otap-del-sel-ddr50 = <0xc>; - ti,otap-del-sel-sdr104 = <0x5>; - ti,itap-del-sel-legacy = <0x0>; - ti,itap-del-sel-sd-hs = <0x0>; - ti,itap-del-sel-sdr12 = <0x0>; - ti,itap-del-sel-sdr25 = <0x0>; - ti,itap-del-sel-ddr50 = <0x2>; - ti,trm-icp = <0x8>; - ti,clkbuf-sel = <0x7>; - dma-coherent; - sdhci-caps-mask = <0x2 0x0>; - status = "disabled"; - }; - - main_sdhci2: mmc@4f98000 { - compatible = "ti,j721e-sdhci-4bit"; - reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; - interrupts = ; - power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_ahb", "clk_xin"; - clocks = <&k3_clks 93 5>, <&k3_clks 93 0>; - assigned-clocks = <&k3_clks 93 0>; - assigned-clock-parents = <&k3_clks 93 1>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0xf>; - ti,otap-del-sel-sdr25 = <0xf>; - ti,otap-del-sel-sdr50 = <0xc>; - ti,otap-del-sel-ddr50 = <0xc>; - ti,otap-del-sel-sdr104 = <0x5>; - ti,itap-del-sel-legacy = <0x0>; - ti,itap-del-sel-sd-hs = <0x0>; - ti,itap-del-sel-sdr12 = <0x0>; - ti,itap-del-sel-sdr25 = <0x0>; - ti,itap-del-sel-ddr50 = <0x2>; - ti,trm-icp = <0x8>; - ti,clkbuf-sel = <0x7>; - dma-coherent; - sdhci-caps-mask = <0x2 0x0>; - status = "disabled"; - }; - - usbss0: cdns-usb@4104000 { - compatible = "ti,j721e-usb"; - reg = <0x00 0x4104000 0x00 0x100>; - dma-coherent; - power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; - clock-names = "ref", "lpm"; - assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ - assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ - #address-cells = <2>; - #size-cells = <2>; - ranges; - - usb0: usb@6000000 { - compatible = "cdns,usb3"; - reg = <0x00 0x6000000 0x00 0x10000>, - <0x00 0x6010000 0x00 0x10000>, - <0x00 0x6020000 0x00 0x10000>; - reg-names = "otg", "xhci", "dev"; - interrupts = , /* irq.0 */ - , /* irq.6 */ - ; /* otgirq.0 */ - interrupt-names = "host", - "peripheral", - "otg"; - maximum-speed = "super-speed"; - dr_mode = "otg"; - }; - }; - - usbss1: cdns-usb@4114000 { - compatible = "ti,j721e-usb"; - reg = <0x00 0x4114000 0x00 0x100>; - dma-coherent; - power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; - clock-names = "ref", "lpm"; - assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ - assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ - #address-cells = <2>; - #size-cells = <2>; - ranges; - - usb1: usb@6400000 { - compatible = "cdns,usb3"; - reg = <0x00 0x6400000 0x00 0x10000>, - <0x00 0x6410000 0x00 0x10000>, - <0x00 0x6420000 0x00 0x10000>; - reg-names = "otg", "xhci", "dev"; - interrupts = , /* irq.0 */ - , /* irq.6 */ - ; /* otgirq.0 */ - interrupt-names = "host", - "peripheral", - "otg"; - maximum-speed = "super-speed"; - dr_mode = "otg"; - }; - }; - - main_i2c0: i2c@2000000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2000000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 187 0>; - power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; - status = "disabled"; - }; - - main_i2c1: i2c@2010000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2010000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 188 0>; - power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c2: i2c@2020000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2020000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 189 0>; - power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c3: i2c@2030000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2030000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 190 0>; - power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c4: i2c@2040000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2040000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 191 0>; - power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c5: i2c@2050000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2050000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 192 0>; - power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c6: i2c@2060000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2060000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 193 0>; - power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - ufs_wrapper: ufs-wrapper@4e80000 { - compatible = "ti,j721e-ufs"; - reg = <0x0 0x4e80000 0x0 0x100>; - power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 277 1>; - assigned-clocks = <&k3_clks 277 1>; - assigned-clock-parents = <&k3_clks 277 4>; - ranges; - #address-cells = <2>; - #size-cells = <2>; - - ufs@4e84000 { - compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; - reg = <0x0 0x4e84000 0x0 0x10000>; - interrupts = ; - freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; - clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; - clock-names = "core_clk", "phy_clk", "ref_clk"; - dma-coherent; - }; - }; - - mhdp: dp-bridge@a000000 { - compatible = "ti,j721e-mhdp8546"; - /* - * Note: we do not map DPTX PHY area, as that is handled by - * the PHY driver. - */ - reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */ - <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */ - reg-names = "mhdptx", "j721e-intg"; - - clocks = <&k3_clks 151 36>; - - interrupt-parent = <&gic500>; - interrupts = ; - - power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; - - dp0_ports: ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@4 { - reg = <4>; - }; - }; - }; - - dss: dss@4a00000 { - compatible = "ti,j721e-dss"; - reg = - <0x00 0x04a00000 0x00 0x10000>, /* common_m */ - <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ - <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ - <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ - - <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ - <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ - <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ - <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ - - <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ - <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ - <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ - <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ - - <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ - <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ - <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ - <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ - <0x00 0x04af0000 0x00 0x10000>; /* wb */ - - reg-names = "common_m", "common_s0", - "common_s1", "common_s2", - "vidl1", "vidl2","vid1","vid2", - "ovr1", "ovr2", "ovr3", "ovr4", - "vp1", "vp2", "vp3", "vp4", - "wb"; - - clocks = <&k3_clks 152 0>, - <&k3_clks 152 1>, - <&k3_clks 152 4>, - <&k3_clks 152 9>, - <&k3_clks 152 13>; - clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; - - power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; - - interrupts = , - , - , - ; - interrupt-names = "common_m", - "common_s0", - "common_s1", - "common_s2"; - - dss_ports: ports { - }; - }; - - mcasp0: mcasp@2b00000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b00000 0x0 0x2000>, - <0x0 0x02b08000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 174 1>; - clock-names = "fck"; - power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp1: mcasp@2b10000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b10000 0x0 0x2000>, - <0x0 0x02b18000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 175 1>; - clock-names = "fck"; - power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp2: mcasp@2b20000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b20000 0x0 0x2000>, - <0x0 0x02b28000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 176 1>; - clock-names = "fck"; - power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp3: mcasp@2b30000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b30000 0x0 0x2000>, - <0x0 0x02b38000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 177 1>; - clock-names = "fck"; - power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp4: mcasp@2b40000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b40000 0x0 0x2000>, - <0x0 0x02b48000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 178 1>; - clock-names = "fck"; - power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp5: mcasp@2b50000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b50000 0x0 0x2000>, - <0x0 0x02b58000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 179 1>; - clock-names = "fck"; - power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp6: mcasp@2b60000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b60000 0x0 0x2000>, - <0x0 0x02b68000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 180 1>; - clock-names = "fck"; - power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp7: mcasp@2b70000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b70000 0x0 0x2000>, - <0x0 0x02b78000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 181 1>; - clock-names = "fck"; - power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp8: mcasp@2b80000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b80000 0x0 0x2000>, - <0x0 0x02b88000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 182 1>; - clock-names = "fck"; - power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp9: mcasp@2b90000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b90000 0x0 0x2000>, - <0x0 0x02b98000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 183 1>; - clock-names = "fck"; - power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp10: mcasp@2ba0000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02ba0000 0x0 0x2000>, - <0x0 0x02ba8000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 184 1>; - clock-names = "fck"; - power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp11: mcasp@2bb0000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02bb0000 0x0 0x2000>, - <0x0 0x02bb8000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 185 1>; - clock-names = "fck"; - power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - watchdog0: watchdog@2200000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x0 0x2200000 0x0 0x100>; - clocks = <&k3_clks 252 1>; - power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 252 1>; - assigned-clock-parents = <&k3_clks 252 5>; - }; - - watchdog1: watchdog@2210000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x0 0x2210000 0x0 0x100>; - clocks = <&k3_clks 253 1>; - power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 253 1>; - assigned-clock-parents = <&k3_clks 253 5>; - }; - - main_r5fss0: r5fss@5c00000 { - compatible = "ti,j721e-r5fss"; - ti,cluster-mode = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5c00000 0x00 0x5c00000 0x20000>, - <0x5d00000 0x00 0x5d00000 0x20000>; - power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; - - main_r5fss0_core0: r5f@5c00000 { - compatible = "ti,j721e-r5f"; - reg = <0x5c00000 0x00008000>, - <0x5c10000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <245>; - ti,sci-proc-ids = <0x06 0xff>; - resets = <&k3_reset 245 1>; - firmware-name = "j7-main-r5f0_0-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - - main_r5fss0_core1: r5f@5d00000 { - compatible = "ti,j721e-r5f"; - reg = <0x5d00000 0x00008000>, - <0x5d10000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <246>; - ti,sci-proc-ids = <0x07 0xff>; - resets = <&k3_reset 246 1>; - firmware-name = "j7-main-r5f0_1-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - }; - - main_r5fss1: r5fss@5e00000 { - compatible = "ti,j721e-r5fss"; - ti,cluster-mode = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5e00000 0x00 0x5e00000 0x20000>, - <0x5f00000 0x00 0x5f00000 0x20000>; - power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; - - main_r5fss1_core0: r5f@5e00000 { - compatible = "ti,j721e-r5f"; - reg = <0x5e00000 0x00008000>, - <0x5e10000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <247>; - ti,sci-proc-ids = <0x08 0xff>; - resets = <&k3_reset 247 1>; - firmware-name = "j7-main-r5f1_0-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - - main_r5fss1_core1: r5f@5f00000 { - compatible = "ti,j721e-r5f"; - reg = <0x5f00000 0x00008000>, - <0x5f10000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <248>; - ti,sci-proc-ids = <0x09 0xff>; - resets = <&k3_reset 248 1>; - firmware-name = "j7-main-r5f1_1-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - }; - - c66_0: dsp@4d80800000 { - compatible = "ti,j721e-c66-dsp"; - reg = <0x4d 0x80800000 0x00 0x00048000>, - <0x4d 0x80e00000 0x00 0x00008000>, - <0x4d 0x80f00000 0x00 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <142>; - ti,sci-proc-ids = <0x03 0xff>; - resets = <&k3_reset 142 1>; - firmware-name = "j7-c66_0-fw"; - status = "disabled"; - }; - - c66_1: dsp@4d81800000 { - compatible = "ti,j721e-c66-dsp"; - reg = <0x4d 0x81800000 0x00 0x00048000>, - <0x4d 0x81e00000 0x00 0x00008000>, - <0x4d 0x81f00000 0x00 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <143>; - ti,sci-proc-ids = <0x04 0xff>; - resets = <&k3_reset 143 1>; - firmware-name = "j7-c66_1-fw"; - status = "disabled"; - }; - - c71_0: dsp@64800000 { - compatible = "ti,j721e-c71-dsp"; - reg = <0x00 0x64800000 0x00 0x00080000>, - <0x00 0x64e00000 0x00 0x0000c000>; - reg-names = "l2sram", "l1dram"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <15>; - ti,sci-proc-ids = <0x30 0xff>; - resets = <&k3_reset 15 1>; - firmware-name = "j7-c71_0-fw"; - status = "disabled"; - }; - - icssg0: icssg@b000000 { - compatible = "ti,j721e-icssg"; - reg = <0x00 0xb000000 0x00 0x80000>; - power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x0b000000 0x100000>; - - icssg0_mem: memories@0 { - reg = <0x0 0x2000>, - <0x2000 0x2000>, - <0x10000 0x10000>; - reg-names = "dram0", "dram1", - "shrdram2"; - }; - - icssg0_cfg: cfg@26000 { - compatible = "ti,pruss-cfg", "syscon"; - reg = <0x26000 0x200>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x2000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - icssg0_coreclk_mux: coreclk-mux@3c { - reg = <0x3c>; - #clock-cells = <0>; - clocks = <&k3_clks 119 24>, /* icssg0_core_clk */ - <&k3_clks 119 1>; /* icssg0_iclk */ - assigned-clocks = <&icssg0_coreclk_mux>; - assigned-clock-parents = <&k3_clks 119 1>; - }; - - icssg0_iepclk_mux: iepclk-mux@30 { - reg = <0x30>; - #clock-cells = <0>; - clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */ - <&icssg0_coreclk_mux>; /* core_clk */ - assigned-clocks = <&icssg0_iepclk_mux>; - assigned-clock-parents = <&icssg0_coreclk_mux>; - }; - }; - }; - - icssg0_mii_rt: mii-rt@32000 { - compatible = "ti,pruss-mii", "syscon"; - reg = <0x32000 0x100>; - }; - - icssg0_mii_g_rt: mii-g-rt@33000 { - compatible = "ti,pruss-mii-g", "syscon"; - reg = <0x33000 0x1000>; - }; - - icssg0_intc: interrupt-controller@20000 { - compatible = "ti,icssg-intc"; - reg = <0x20000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = , - , - , - , - , - , - , - ; - interrupt-names = "host_intr0", "host_intr1", - "host_intr2", "host_intr3", - "host_intr4", "host_intr5", - "host_intr6", "host_intr7"; - }; - - pru0_0: pru@34000 { - compatible = "ti,j721e-pru"; - reg = <0x34000 0x3000>, - <0x22000 0x100>, - <0x22400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-pru0_0-fw"; - }; - - rtu0_0: rtu@4000 { - compatible = "ti,j721e-rtu"; - reg = <0x4000 0x2000>, - <0x23000 0x100>, - <0x23400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-rtu0_0-fw"; - }; - - tx_pru0_0: txpru@a000 { - compatible = "ti,j721e-tx-pru"; - reg = <0xa000 0x1800>, - <0x25000 0x100>, - <0x25400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-txpru0_0-fw"; - }; - - pru0_1: pru@38000 { - compatible = "ti,j721e-pru"; - reg = <0x38000 0x3000>, - <0x24000 0x100>, - <0x24400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-pru0_1-fw"; - }; - - rtu0_1: rtu@6000 { - compatible = "ti,j721e-rtu"; - reg = <0x6000 0x2000>, - <0x23800 0x100>, - <0x23c00 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-rtu0_1-fw"; - }; - - tx_pru0_1: txpru@c000 { - compatible = "ti,j721e-tx-pru"; - reg = <0xc000 0x1800>, - <0x25800 0x100>, - <0x25c00 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-txpru0_1-fw"; - }; - - icssg0_mdio: mdio@32400 { - compatible = "ti,davinci_mdio"; - reg = <0x32400 0x100>; - clocks = <&k3_clks 119 1>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <0>; - bus_freq = <1000000>; - status = "disabled"; - }; - }; - - icssg1: icssg@b100000 { - compatible = "ti,j721e-icssg"; - reg = <0x00 0xb100000 0x00 0x80000>; - power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x0b100000 0x100000>; - - icssg1_mem: memories@b100000 { - reg = <0x0 0x2000>, - <0x2000 0x2000>, - <0x10000 0x10000>; - reg-names = "dram0", "dram1", - "shrdram2"; - }; - - icssg1_cfg: cfg@26000 { - compatible = "ti,pruss-cfg", "syscon"; - reg = <0x26000 0x200>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x2000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - icssg1_coreclk_mux: coreclk-mux@3c { - reg = <0x3c>; - #clock-cells = <0>; - clocks = <&k3_clks 120 54>, /* icssg1_core_clk */ - <&k3_clks 120 4>; /* icssg1_iclk */ - assigned-clocks = <&icssg1_coreclk_mux>; - assigned-clock-parents = <&k3_clks 120 4>; - }; - - icssg1_iepclk_mux: iepclk-mux@30 { - reg = <0x30>; - #clock-cells = <0>; - clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */ - <&icssg1_coreclk_mux>; /* core_clk */ - assigned-clocks = <&icssg1_iepclk_mux>; - assigned-clock-parents = <&icssg1_coreclk_mux>; - }; - }; - }; - - icssg1_mii_rt: mii-rt@32000 { - compatible = "ti,pruss-mii", "syscon"; - reg = <0x32000 0x100>; - }; - - icssg1_mii_g_rt: mii-g-rt@33000 { - compatible = "ti,pruss-mii-g", "syscon"; - reg = <0x33000 0x1000>; - }; - - icssg1_intc: interrupt-controller@20000 { - compatible = "ti,icssg-intc"; - reg = <0x20000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = , - , - , - , - , - , - , - ; - interrupt-names = "host_intr0", "host_intr1", - "host_intr2", "host_intr3", - "host_intr4", "host_intr5", - "host_intr6", "host_intr7"; - }; - - pru1_0: pru@34000 { - compatible = "ti,j721e-pru"; - reg = <0x34000 0x4000>, - <0x22000 0x100>, - <0x22400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-pru1_0-fw"; - }; - - rtu1_0: rtu@4000 { - compatible = "ti,j721e-rtu"; - reg = <0x4000 0x2000>, - <0x23000 0x100>, - <0x23400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-rtu1_0-fw"; - }; - - tx_pru1_0: txpru@a000 { - compatible = "ti,j721e-tx-pru"; - reg = <0xa000 0x1800>, - <0x25000 0x100>, - <0x25400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-txpru1_0-fw"; - }; - - pru1_1: pru@38000 { - compatible = "ti,j721e-pru"; - reg = <0x38000 0x4000>, - <0x24000 0x100>, - <0x24400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-pru1_1-fw"; - }; - - rtu1_1: rtu@6000 { - compatible = "ti,j721e-rtu"; - reg = <0x6000 0x2000>, - <0x23800 0x100>, - <0x23c00 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-rtu1_1-fw"; - }; - - tx_pru1_1: txpru@c000 { - compatible = "ti,j721e-tx-pru"; - reg = <0xc000 0x1800>, - <0x25800 0x100>, - <0x25c00 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-txpru1_1-fw"; - }; - - icssg1_mdio: mdio@32400 { - compatible = "ti,davinci_mdio"; - reg = <0x32400 0x100>; - clocks = <&k3_clks 120 4>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <0>; - bus_freq = <1000000>; - status = "disabled"; - }; - }; - - main_mcan0: can@2701000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02701000 0x00 0x200>, - <0x00 0x02708000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 156 0>, <&k3_clks 156 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan1: can@2711000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02711000 0x00 0x200>, - <0x00 0x02718000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 158 0>, <&k3_clks 158 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan2: can@2721000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02721000 0x00 0x200>, - <0x00 0x02728000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 160 0>, <&k3_clks 160 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan3: can@2731000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02731000 0x00 0x200>, - <0x00 0x02738000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 161 0>, <&k3_clks 161 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan4: can@2741000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02741000 0x00 0x200>, - <0x00 0x02748000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 162 0>, <&k3_clks 162 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan5: can@2751000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02751000 0x00 0x200>, - <0x00 0x02758000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 163 0>, <&k3_clks 163 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan6: can@2761000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02761000 0x00 0x200>, - <0x00 0x02768000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 164 0>, <&k3_clks 164 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan7: can@2771000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02771000 0x00 0x200>, - <0x00 0x02778000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 165 0>, <&k3_clks 165 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan8: can@2781000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02781000 0x00 0x200>, - <0x00 0x02788000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 166 0>, <&k3_clks 166 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan9: can@2791000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02791000 0x00 0x200>, - <0x00 0x02798000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 167 0>, <&k3_clks 167 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan10: can@27a1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x027a1000 0x00 0x200>, - <0x00 0x027a8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 168 0>, <&k3_clks 168 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan11: can@27b1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x027b1000 0x00 0x200>, - <0x00 0x027b8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 169 0>, <&k3_clks 169 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan12: can@27c1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x027c1000 0x00 0x200>, - <0x00 0x027c8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 170 0>, <&k3_clks 170 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan13: can@27d1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x027d1000 0x00 0x200>, - <0x00 0x027d8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 171 0>, <&k3_clks 171 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_spi0: spi@2100000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02100000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 266 1>; - status = "disabled"; - }; - - main_spi1: spi@2110000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02110000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 267 1>; - status = "disabled"; - }; - - main_spi2: spi@2120000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02120000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 268 1>; - status = "disabled"; - }; - - main_spi3: spi@2130000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02130000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 269 1>; - status = "disabled"; - }; - - main_spi4: spi@2140000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02140000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 270 1>; - status = "disabled"; - }; - - main_spi5: spi@2150000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02150000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 271 1>; - status = "disabled"; - }; - - main_spi6: spi@2160000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02160000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 272 1>; - status = "disabled"; - }; - - main_spi7: spi@2170000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02170000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 273 1>; - status = "disabled"; - }; - - main_esm: esm@700000 { - compatible = "ti,j721e-esm"; - reg = <0x0 0x700000 0x0 0x1000>; - ti,esm-pins = <344>, <345>; - }; -}; diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi deleted file mode 100644 index f7ab7719fc0..00000000000 --- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi +++ /dev/null @@ -1,681 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals - * - * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&cbass_mcu_wakeup { - dmsc: system-controller@44083000 { - compatible = "ti,k2g-sci"; - ti,host-id = <12>; - - mbox-names = "rx", "tx"; - - mboxes = <&secure_proxy_main 11>, - <&secure_proxy_main 13>; - - reg-names = "debug_messages"; - reg = <0x00 0x44083000 0x0 0x1000>; - - k3_pds: power-controller { - compatible = "ti,sci-pm-domain"; - #power-domain-cells = <2>; - }; - - k3_clks: clock-controller { - compatible = "ti,k2g-sci-clk"; - #clock-cells = <2>; - }; - - k3_reset: reset-controller { - compatible = "ti,sci-reset"; - #reset-cells = <2>; - }; - }; - - mcu_conf: syscon@40f00000 { - compatible = "syscon", "simple-mfd"; - reg = <0x0 0x40f00000 0x0 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x40f00000 0x20000>; - - phy_gmii_sel: phy@4040 { - compatible = "ti,am654-phy-gmii-sel"; - reg = <0x4040 0x4>; - #phy-cells = <1>; - }; - }; - - chipid@43000014 { - compatible = "ti,am654-chipid"; - reg = <0x0 0x43000014 0x0 0x4>; - }; - - wkup_pmx0: pinctrl@4301c000 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c000 0x00 0x178>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ - mcu_timerio_input: pinctrl@40f04200 { - compatible = "pinctrl-single"; - reg = <0x00 0x40f04200 0x00 0x28>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000f>; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ - mcu_timerio_output: pinctrl@40f04280 { - compatible = "pinctrl-single"; - reg = <0x00 0x40f04280 0x00 0x28>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000f>; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_ram: sram@41c00000 { - compatible = "mmio-sram"; - reg = <0x00 0x41c00000 0x00 0x100000>; - ranges = <0x0 0x00 0x41c00000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - mcu_timer0: timer@40400000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40400000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 35 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 35 1>; - assigned-clock-parents = <&k3_clks 35 2>; - power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer1: timer@40410000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40410000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 71 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>; - assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 322 1>; - power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer2: timer@40420000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40420000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 72 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 72 1>; - assigned-clock-parents = <&k3_clks 72 2>; - power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer3: timer@40430000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40430000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 73 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>; - assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 323 1>; - power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer4: timer@40440000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40440000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 74 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 74 1>; - assigned-clock-parents = <&k3_clks 74 2>; - power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer5: timer@40450000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40450000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 75 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 75 1>, <&k3_clks 324 0>; - assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 324 1>; - power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer6: timer@40460000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40460000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 76 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 76 1>; - assigned-clock-parents = <&k3_clks 76 2>; - power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer7: timer@40470000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40470000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 77 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 77 1>, <&k3_clks 325 0>; - assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 325 1>; - power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer8: timer@40480000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40480000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 78 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 78 1>; - assigned-clock-parents = <&k3_clks 78 2>; - power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer9: timer@40490000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40490000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 79 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 79 1>, <&k3_clks 326 0>; - assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 326 1>; - power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - wkup_uart0: serial@42300000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x42300000 0x00 0x100>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 287 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - mcu_uart0: serial@40a00000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x40a00000 0x00 0x100>; - interrupts = ; - clock-frequency = <96000000>; - current-speed = <115200>; - power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 149 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - wkup_gpio_intr: interrupt-controller@42200000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x42200000 0x00 0x400>; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <137>; - ti,interrupt-ranges = <16 960 16>; - }; - - wkup_gpio0: gpio@42110000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x42110000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&wkup_gpio_intr>; - interrupts = <103>, <104>, <105>, <106>, <107>, <108>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <84>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 113 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - wkup_gpio1: gpio@42100000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x42100000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&wkup_gpio_intr>; - interrupts = <112>, <113>, <114>, <115>, <116>, <117>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <84>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 114 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - mcu_i2c0: i2c@40b00000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x40b00000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 194 0>; - power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcu_i2c1: i2c@40b10000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x40b10000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 195 0>; - power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - wkup_i2c0: i2c@42120000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x42120000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 197 0>; - power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; - status = "disabled"; - }; - - fss: bus@47000000 { - compatible = "simple-bus"; - reg = <0x0 0x47000000 0x0 0x100>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hbmc_mux: mux-controller@47000004 { - compatible = "reg-mux"; - reg = <0x00 0x47000004 0x00 0x2>; - #mux-control-cells = <1>; - mux-reg-masks = <0x4 0x2>; /* HBMC select */ - }; - - hbmc: hyperbus@47034000 { - compatible = "ti,am654-hbmc"; - reg = <0x00 0x47034000 0x00 0x100>, - <0x05 0x00000000 0x01 0x0000000>; - power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 102 0>; - assigned-clocks = <&k3_clks 102 5>; - assigned-clock-rates = <333333333>; - #address-cells = <2>; - #size-cells = <1>; - mux-controls = <&hbmc_mux 0>; - status = "disabled"; - }; - - ospi0: spi@47040000 { - compatible = "ti,am654-ospi", "cdns,qspi-nor"; - reg = <0x0 0x47040000 0x0 0x100>, - <0x5 0x00000000 0x1 0x0000000>; - interrupts = ; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x0>; - clocks = <&k3_clks 103 0>; - assigned-clocks = <&k3_clks 103 0>; - assigned-clock-parents = <&k3_clks 103 2>; - assigned-clock-rates = <166666666>; - power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ospi1: spi@47050000 { - compatible = "ti,am654-ospi", "cdns,qspi-nor"; - reg = <0x0 0x47050000 0x0 0x100>, - <0x7 0x00000000 0x1 0x00000000>; - interrupts = ; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x0>; - clocks = <&k3_clks 104 0>; - power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - tscadc0: tscadc@40200000 { - compatible = "ti,am3359-tscadc"; - reg = <0x0 0x40200000 0x0 0x1000>; - interrupts = ; - power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 0 1>; - assigned-clocks = <&k3_clks 0 3>; - assigned-clock-rates = <60000000>; - clock-names = "fck"; - dmas = <&main_udmap 0x7400>, - <&main_udmap 0x7401>; - dma-names = "fifo0", "fifo1"; - status = "disabled"; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am3359-adc"; - }; - }; - - tscadc1: tscadc@40210000 { - compatible = "ti,am3359-tscadc"; - reg = <0x0 0x40210000 0x0 0x1000>; - interrupts = ; - power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 1 1>; - assigned-clocks = <&k3_clks 1 3>; - assigned-clock-rates = <60000000>; - clock-names = "fck"; - dmas = <&main_udmap 0x7402>, - <&main_udmap 0x7403>; - dma-names = "fifo0", "fifo1"; - status = "disabled"; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am3359-adc"; - }; - }; - - mcu_navss: bus@28380000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; - dma-coherent; - dma-ranges; - - ti,sci-dev-id = <232>; - - mcu_ringacc: ringacc@2b800000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x2b800000 0x0 0x400000>, - <0x0 0x2b000000 0x0 0x400000>, - <0x0 0x28590000 0x0 0x100>, - <0x0 0x2a500000 0x0 0x40000>, - <0x0 0x28440000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; - ti,num-rings = <286>; - ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ - ti,sci = <&dmsc>; - ti,sci-dev-id = <235>; - msi-parent = <&main_udmass_inta>; - }; - - mcu_udmap: dma-controller@285c0000 { - compatible = "ti,j721e-navss-mcu-udmap"; - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x2aa00000 0x0 0x40000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&main_udmass_inta>; - #dma-cells = <1>; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <236>; - ti,ringacc = <&mcu_ringacc>; - - ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ - <0x0f>; /* TX_HCHAN */ - ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ - <0x0b>; /* RX_HCHAN */ - ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ - }; - }; - - secure_proxy_mcu: mailbox@2a480000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x0 0x2a480000 0x0 0x80000>, - <0x0 0x2a380000 0x0 0x80000>, - <0x0 0x2a400000 0x0 0x80000>; - /* - * Marked Disabled: - * Node is incomplete as it is meant for bootloaders and - * firmware on non-MPU processors - */ - status = "disabled"; - }; - - mcu_cpsw: ethernet@46000000 { - compatible = "ti,j721e-cpsw-nuss"; - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x46000000 0x0 0x200000>; - reg-names = "cpsw_nuss"; - ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; - dma-coherent; - clocks = <&k3_clks 18 22>; - clock-names = "fck"; - power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; - - dmas = <&mcu_udmap 0xf000>, - <&mcu_udmap 0xf001>, - <&mcu_udmap 0xf002>, - <&mcu_udmap 0xf003>, - <&mcu_udmap 0xf004>, - <&mcu_udmap 0xf005>, - <&mcu_udmap 0xf006>, - <&mcu_udmap 0xf007>, - <&mcu_udmap 0x7000>; - dma-names = "tx0", "tx1", "tx2", "tx3", - "tx4", "tx5", "tx6", "tx7", - "rx"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - cpsw_port1: port@1 { - reg = <1>; - ti,mac-only; - label = "port1"; - ti,syscon-efuse = <&mcu_conf 0x200>; - phys = <&phy_gmii_sel 1>; - }; - }; - - davinci_mdio: mdio@f00 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x0 0xf00 0x0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 18 22>; - clock-names = "fck"; - bus_freq = <1000000>; - }; - - cpts@3d000 { - compatible = "ti,am65-cpts"; - reg = <0x0 0x3d000 0x0 0x400>; - clocks = <&k3_clks 18 2>; - clock-names = "cpts"; - interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cpts"; - ti,cpts-ext-ts-inputs = <4>; - ti,cpts-periodic-outputs = <2>; - }; - }; - - mcu_r5fss0: r5fss@41000000 { - compatible = "ti,j721e-r5fss"; - ti,cluster-mode = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x41000000 0x00 0x41000000 0x20000>, - <0x41400000 0x00 0x41400000 0x20000>; - power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; - - mcu_r5fss0_core0: r5f@41000000 { - compatible = "ti,j721e-r5f"; - reg = <0x41000000 0x00008000>, - <0x41010000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <250>; - ti,sci-proc-ids = <0x01 0xff>; - resets = <&k3_reset 250 1>; - firmware-name = "j7-mcu-r5f0_0-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - - mcu_r5fss0_core1: r5f@41400000 { - compatible = "ti,j721e-r5f"; - reg = <0x41400000 0x00008000>, - <0x41410000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <251>; - ti,sci-proc-ids = <0x02 0xff>; - resets = <&k3_reset 251 1>; - firmware-name = "j7-mcu-r5f0_1-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - }; - - mcu_mcan0: can@40528000 { - compatible = "bosch,m_can"; - reg = <0x00 0x40528000 0x00 0x200>, - <0x00 0x40500000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 172 0>, <&k3_clks 172 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - mcu_mcan1: can@40568000 { - compatible = "bosch,m_can"; - reg = <0x00 0x40568000 0x00 0x200>, - <0x00 0x40540000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 173 0>, <&k3_clks 173 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - mcu_spi0: spi@40300000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x040300000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 274 0>; - status = "disabled"; - }; - - mcu_spi1: spi@40310000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x040310000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 275 0>; - status = "disabled"; - }; - - mcu_spi2: spi@40320000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x040320000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 276 0>; - status = "disabled"; - }; - - wkup_vtm0: temperature-sensor@42040000 { - compatible = "ti,j721e-vtm"; - reg = <0x00 0x42040000 0x00 0x350>, - <0x00 0x42050000 0x00 0x350>, - <0x00 0x43000300 0x00 0x10>; - power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; - #thermal-sensor-cells = <1>; - }; - - mcu_esm: esm@40800000 { - compatible = "ti,j721e-esm"; - reg = <0x00 0x40800000 0x00 0x1000>; - ti,esm-pins = <95>; - bootph-pre-ram; - }; -}; diff --git a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi index 6d0f7457ccd..07ed7b40fed 100644 --- a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi @@ -15,10 +15,10 @@ &cbass_mcu_wakeup { bootph-all; +}; - chipid@43000014 { - bootph-all; - }; +&chipid { + bootph-all; }; &mcu_navss { @@ -26,19 +26,11 @@ }; &mcu_ringacc { - bootph-all; + bootph-all; }; &mcu_udmap { - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x284c0000 0x0 0x4000>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x284a0000 0x0 0x4000>, - <0x0 0x2aa00000 0x0 0x40000>, - <0x0 0x28400000 0x0 0x2000>; - reg-names = "gcfg", "rchan", "rchanrt", "tchan", - "tchanrt", "rflow"; - bootph-all; + bootph-all; }; &secure_proxy_main { @@ -158,7 +150,7 @@ #ifdef CONFIG_TARGET_J721E_A72_EVM -#define SPL_J721E_SK_DTB "spl/dts/k3-j721e-sk.dtb" +#define SPL_J721E_SK_DTB "spl/dts/ti/k3-j721e-sk.dtb" #define J721E_SK_DTB "u-boot.dtb" &spl_j721e_dtb { diff --git a/arch/arm/dts/k3-j721e-sk.dts b/arch/arm/dts/k3-j721e-sk.dts deleted file mode 100644 index 42fe8eee9ec..00000000000 --- a/arch/arm/dts/k3-j721e-sk.dts +++ /dev/null @@ -1,1074 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ - * - * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM - */ - -/dts-v1/; - -#include "k3-j721e.dtsi" -#include -#include -#include - -/ { - compatible = "ti,j721e-sk", "ti,j721e"; - model = "Texas Instruments J721E SK"; - - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - ethernet0 = &cpsw_port1; - mmc1 = &main_sdhci1; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - /* 4G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x80000000>, - <0x00000008 0x80000000 0x00000000 0x80000000>; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; - alignment = <0x1000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0100000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c66_1_dma_memory_region: c66-dma-memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c66_0_memory_region: c66-memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c66_0_dma_memory_region: c66-dma-memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c66_1_memory_region: c66-memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a8000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a8100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@aa000000 { - reg = <0x00 0xaa000000 0x00 0x01c00000>; - alignment = <0x1000>; - no-map; - }; - }; - - vusb_main: fixedregulator-vusb-main5v0 { - /* USB MAIN INPUT 5V DC */ - compatible = "regulator-fixed"; - regulator-name = "vusb-main5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_3v3: fixedregulator-vsys3v3 { - /* Output of LM5141 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vusb_main>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_mmc1: fixedregulator-sd { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_mmc1_en_pins_default>; - regulator-name = "vdd_mmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - vin-supply = <&vsys_3v3>; - gpio = <&wkup_gpio0 8 GPIO_ACTIVE_HIGH>; - }; - - vdd_sd_dv_alt: gpio-regulator-tps659411 { - compatible = "regulator-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; - regulator-name = "tps659411"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - vin-supply = <&vsys_3v3>; - gpios = <&wkup_gpio0 9 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0>, - <3300000 0x1>; - }; - - dp_pwr_3v3: fixedregulator-dp-prw { - compatible = "regulator-fixed"; - regulator-name = "dp-pwr"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&dp_pwr_en_pins_default>; - gpio = <&main_gpio0 111 0>; /* DP0_3V3 _EN */ - enable-active-high; - }; - - dp0: connector { - compatible = "dp-connector"; - label = "DP0"; - type = "full-size"; - dp-pwr-supply = <&dp_pwr_3v3>; - - port { - dp_connector_in: endpoint { - remote-endpoint = <&dp0_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - label = "hdmi"; - type = "a"; - - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_pins_default>; - - ddc-i2c-bus = <&main_i2c1>; - - /* HDMI_HPD */ - hpd-gpios = <&main_gpio1 0 GPIO_ACTIVE_HIGH>; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - dvi-bridge { - compatible = "ti,tfp410"; - - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pdn_pins_default>; - - powerdown-gpios = <&main_gpio0 127 GPIO_ACTIVE_LOW>; - ti,deskew = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi1_out>; - pclk-sample = <1>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = - <&hdmi_connector_in>; - }; - }; - }; - }; -}; - -&main_pmx0 { - main_mmc1_pins_default: main-mmc1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ - J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ - J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ - J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ - J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ - J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ - J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ - J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ - >; - }; - - main_uart0_pins_default: main-uart0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */ - J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */ - J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ - J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ - >; - }; - - main_uart1_pins_default: main-uart1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */ - J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */ - >; - }; - - main_i2c0_pins_default: main-i2c0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ - J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ - >; - }; - - main_i2c1_pins_default: main-i2c1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ - J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ - >; - }; - - main_i2c3_pins_default: main-i2c3-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ - J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ - >; - }; - - main_usbss0_pins_default: main-usbss0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ - J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ - >; - }; - - main_usbss1_pins_default: main-usbss1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ - >; - }; - - dp0_pins_default: dp0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ - >; - }; - - dp_pwr_en_pins_default: dp-pwr-en-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */ - >; - }; - - dss_vout0_pins_default: dss-vout0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */ - J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */ - J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */ - J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */ - J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */ - J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */ - J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */ - J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */ - J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */ - J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */ - J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */ - J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */ - J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */ - J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */ - J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */ - J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */ - J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */ - J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */ - J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */ - J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */ - J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */ - J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */ - J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */ - J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */ - J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */ - J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */ - J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */ - J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */ - >; - }; - - hdmi_hpd_pins_default: hdmi-hpd-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x204, PIN_INPUT, 7) /* (AD5) UART1_RTSn.GPIO1_0 */ - >; - }; - - hdmi_pdn_pins_default: hdmi-pdn-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ - >; - }; - - /* Reset for M.2 E Key slot on PCIe0 */ - ekey_reset_pins_default: ekey-reset-pns-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */ - >; - }; - - main_i2c5_pins_default: main-i2c5-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ - J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ - >; - }; - - rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */ - J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */ - J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ - J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */ - J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ - J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ - J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ - J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */ - J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */ - J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */ - J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */ - J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */ - J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */ - J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */ - J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ - J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */ - J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ - J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */ - J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */ - J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */ - J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */ - J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */ - J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */ - >; - }; - - rpi_header_gpio1_pins_default: rpi-header-gpio1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */ - >; - }; -}; - -&wkup_pmx0 { - mcu_cpsw_pins_default: mcu-cpsw-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ - J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ - J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */ - J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */ - J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */ - J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */ - J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */ - J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */ - J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */ - J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */ - J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */ - J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */ - >; - }; - - mcu_mdio_pins_default: mcu-mdio1-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ - J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ - >; - }; - - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */ - J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */ - J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */ - J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */ - J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */ - J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */ - J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */ - J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */ - J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */ - J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */ - J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */ - >; - }; - - vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */ - >; - }; - - vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */ - >; - }; - - wkup_uart0_pins_default: wkup-uart0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ - J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ - >; - }; - - mcu_uart0_pins_default: mcu-uart0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */ - J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */ - J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ - J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ - >; - }; - - wkup_i2c0_pins_default: wkup-i2c0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ - J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ - >; - }; - - /* Reset for M.2 M Key slot on PCIe1 */ - mkey_reset_pins_default: mkey-reset-pns-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */ - >; - }; -}; - -&wkup_uart0 { - /* Wakeup UART is used by System firmware */ - status = "reserved"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_uart0_pins_default>; -}; - -&wkup_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <400000>; - - eeprom@51 { - /* AT24C512C-MAHM-T */ - compatible = "atmel,24c512"; - reg = <0x51>; - }; -}; - -&mcu_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_uart0_pins_default>; -}; - -&main_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart0_pins_default>; - /* Shared with ATF on this platform */ - power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; -}; - -&main_uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart1_pins_default>; -}; - -&main_sdhci1 { - /* SD Card */ - status = "okay"; - vmmc-supply = <&vdd_mmc1>; - vqmmc-supply = <&vdd_sd_dv_alt>; - pinctrl-names = "default"; - pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&ospi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <8>; - spi-rx-bus-width = <8>; - spi-max-frequency = <25000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "ospi.tiboot3"; - reg = <0x0 0x80000>; - }; - - partition@80000 { - label = "ospi.tispl"; - reg = <0x80000 0x200000>; - }; - - partition@280000 { - label = "ospi.u-boot"; - reg = <0x280000 0x400000>; - }; - - partition@680000 { - label = "ospi.env"; - reg = <0x680000 0x40000>; - }; - - partition@6c0000 { - label = "ospi.sysfw"; - reg = <0x6c0000 0x100000>; - }; - - partition@7c0000 { - label = "ospi.env.backup"; - reg = <0x7c0000 0x40000>; - }; - - partition@800000 { - label = "ospi.rootfs"; - reg = <0x800000 0x37c0000>; - }; - - partition@3fc0000 { - label = "ospi.phypattern"; - reg = <0x3fc0000 0x40000>; - }; - }; - }; -}; - -&main_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - i2c-mux@71 { - compatible = "nxp,pca9543"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - - /* PCIe1 M.2 M Key I2C */ - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - /* PCIe0 M.2 E Key I2C */ - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - }; -}; - -&main_i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_pins_default>; - /* i2c1 is used for DVI DDC, so we need to use 100kHz */ - clock-frequency = <100000>; -}; - -&main_i2c3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c3_pins_default>; - clock-frequency = <400000>; - - i2c-mux@70 { - compatible = "nxp,pca9543"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - /* CSI0 I2C */ - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - /* CSI1 I2C */ - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - }; -}; - -&main_i2c5 { - /* Brought out on RPi Header */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c5_pins_default>; - clock-frequency = <400000>; -}; - -&main_gpio0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&rpi_header_gpio0_pins_default>; -}; - -&main_gpio1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&rpi_header_gpio1_pins_default>; -}; - -&wkup_gpio0 { - status = "okay"; -}; - -&usb_serdes_mux { - idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ -}; - -&serdes_ln_ctrl { - idle-states = , , - , , - , , - , , - , , - , ; -}; - -&serdes_wiz3 { - typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; - typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ -}; - -&serdes3 { - serdes3_usb_link: phy@0 { - reg = <0>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = ; - resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; - }; -}; - -&serdes4 { - torrent_phy_dp: phy@0 { - reg = <0>; - resets = <&serdes_wiz4 1>; - cdns,phy-type = ; - cdns,num-lanes = <4>; - cdns,max-bit-rate = <5400>; - #phy-cells = <0>; - }; -}; - -&mhdp { - phys = <&torrent_phy_dp>; - phy-names = "dpphy"; - pinctrl-names = "default"; - pinctrl-0 = <&dp0_pins_default>; -}; - -&usbss0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_usbss0_pins_default>; - ti,vbus-divider; -}; - -&usb0 { - dr_mode = "otg"; - maximum-speed = "super-speed"; - phys = <&serdes3_usb_link>; - phy-names = "cdns3,usb3-phy"; -}; - -&serdes2 { - serdes2_usb_link: phy@1 { - reg = <1>; - cdns,num-lanes = <1>; - #phy-cells = <0>; - cdns,phy-type = ; - resets = <&serdes_wiz2 2>; - }; -}; - -&usbss1 { - pinctrl-names = "default"; - pinctrl-0 = <&main_usbss1_pins_default>; - ti,vbus-divider; -}; - -&usb1 { - dr_mode = "host"; - maximum-speed = "super-speed"; - phys = <&serdes2_usb_link>; - phy-names = "cdns3,usb3-phy"; -}; - -&mcu_cpsw { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; -}; - -&davinci_mdio { - phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = ; - ti,fifo-depth = ; - }; -}; - -&cpsw_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&phy0>; -}; - -&dss { - pinctrl-names = "default"; - pinctrl-0 = <&dss_vout0_pins_default>; - - assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */ - <&k3_clks 152 4>, /* VP 2 pixel clock */ - <&k3_clks 152 9>, /* VP 3 pixel clock */ - <&k3_clks 152 13>; /* VP 4 pixel clock */ - assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ - <&k3_clks 152 6>, /* DPI0_EXT_CLKSEL_OUT0 */ - <&k3_clks 152 11>, /* PLL18_HSDIV0 */ - <&k3_clks 152 18>; /* DPI1_EXT_CLKSEL_OUT0 */ -}; - -&dss_ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dpi0_out: endpoint { - remote-endpoint = <&dp0_in>; - }; - }; - - port@1 { - reg = <1>; - - dpi1_out: endpoint { - remote-endpoint = <&tfp410_in>; - }; - }; -}; - -&dp0_ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dp0_in: endpoint { - remote-endpoint = <&dpi0_out>; - }; - }; - - port@4 { - reg = <4>; - dp0_out: endpoint { - remote-endpoint = <&dp_connector_in>; - }; - }; -}; - -&serdes0 { - serdes0_pcie_link: phy@0 { - reg = <0>; - cdns,num-lanes = <1>; - #phy-cells = <0>; - cdns,phy-type = ; - resets = <&serdes_wiz0 1>; - }; -}; - -&serdes1 { - serdes1_pcie_link: phy@0 { - reg = <0>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = ; - resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; - }; -}; - -&pcie0_rc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ekey_reset_pins_default>; - reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>; - - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <1>; -}; - -&pcie1_rc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mkey_reset_pins_default>; - reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>; - - phys = <&serdes1_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; -}; - -&ufs_wrapper { - status = "disabled"; -}; - -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - status = "okay"; - interrupts = <424>; - - mbox_c66_0: mbox-c66-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c66_1: mbox-c66-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&c66_0 { - status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; - memory-region = <&c66_0_dma_memory_region>, - <&c66_0_memory_region>; -}; - -&c66_1 { - status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; - memory-region = <&c66_1_dma_memory_region>, - <&c66_1_memory_region>; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; diff --git a/arch/arm/dts/k3-j721e-som-p0.dtsi b/arch/arm/dts/k3-j721e-som-p0.dtsi deleted file mode 100644 index 7f0686c2ce3..00000000000 --- a/arch/arm/dts/k3-j721e-som-p0.dtsi +++ /dev/null @@ -1,446 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/ - * - * Product Link: https://www.ti.com/tool/J721EXSOMXEVM - */ - -/dts-v1/; - -#include "k3-j721e.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - /* 4G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x80000000>, - <0x00000008 0x80000000 0x00000000 0x80000000>; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; - alignment = <0x1000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0100000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c66_1_dma_memory_region: c66-dma-memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c66_0_memory_region: c66-memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c66_0_dma_memory_region: c66-dma-memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c66_1_memory_region: c66-memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a8000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a8100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@aa000000 { - reg = <0x00 0xaa000000 0x00 0x01c00000>; - alignment = <0x1000>; - no-map; - }; - }; -}; - -&wkup_pmx0 { - wkup_i2c0_pins_default: wkup-i2c0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ - J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ - >; - }; - - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ - J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ - J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ - J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ - J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ - J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ - J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ - J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ - J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ - J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ - J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ - >; - }; - - mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CK */ - J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CKn */ - J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CSn0 */ - J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* MCU_HYPERBUS0_CSn1 */ - J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_RESETn */ - J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* MCU_HYPERBUS0_RWDS */ - J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ0 */ - J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ1 */ - J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ2 */ - J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ3 */ - J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ4 */ - J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ5 */ - J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ6 */ - J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ7 */ - >; - }; -}; - -&wkup_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <400000>; - - eeprom@50 { - /* CAV24C256WE-GT3 */ - compatible = "atmel,24c256"; - reg = <0x50>; - }; -}; - -&ospi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <8>; - spi-rx-bus-width = <8>; - spi-max-frequency = <25000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <0>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "ospi.tiboot3"; - reg = <0x0 0x80000>; - }; - - partition@80000 { - label = "ospi.tispl"; - reg = <0x80000 0x200000>; - }; - - partition@280000 { - label = "ospi.u-boot"; - reg = <0x280000 0x400000>; - }; - - partition@680000 { - label = "ospi.env"; - reg = <0x680000 0x20000>; - }; - - partition@6a0000 { - label = "ospi.env.backup"; - reg = <0x6a0000 0x20000>; - }; - - partition@6c0000 { - label = "ospi.sysfw"; - reg = <0x6c0000 0x100000>; - }; - - partition@800000 { - label = "ospi.rootfs"; - reg = <0x800000 0x37c0000>; - }; - - partition@3fe0000 { - label = "ospi.phypattern"; - reg = <0x3fe0000 0x20000>; - }; - }; - }; -}; - -&hbmc { - /* OSPI and HBMC are muxed inside FSS, Bootloader will enable - * appropriate node based on board detection - */ - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; - ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */ - <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */ - - flash@0,0 { - compatible = "cypress,hyperflash", "cfi-flash"; - reg = <0x00 0x00 0x4000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "hbmc.tiboot3"; - reg = <0x0 0x80000>; - }; - - partition@80000 { - label = "hbmc.tispl"; - reg = <0x80000 0x200000>; - }; - - partition@280000 { - label = "hbmc.u-boot"; - reg = <0x280000 0x400000>; - }; - - partition@680000 { - label = "hbmc.env"; - reg = <0x680000 0x40000>; - }; - - partition@6c0000 { - label = "hbmc.sysfw"; - reg = <0x6c0000 0x100000>; - }; - - partition@800000 { - label = "hbmc.rootfs"; - reg = <0x800000 0x3800000>; - }; - }; - }; -}; - -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - status = "okay"; - interrupts = <424>; - - mbox_c66_0: mbox-c66-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c66_1: mbox-c66-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&c66_0 { - status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; - memory-region = <&c66_0_dma_memory_region>, - <&c66_0_memory_region>; -}; - -&c66_1 { - status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; - memory-region = <&c66_1_dma_memory_region>, - <&c66_1_memory_region>; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; diff --git a/arch/arm/dts/k3-j721e-thermal.dtsi b/arch/arm/dts/k3-j721e-thermal.dtsi deleted file mode 100644 index c2523279001..00000000000 --- a/arch/arm/dts/k3-j721e-thermal.dtsi +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include - -thermal_zones: thermal-zones { - wkup_thermal: wkup-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 0>; - - trips { - wkup_crit: wkup-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; - - mpu_thermal: mpu-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 1>; - - trips { - mpu_crit: mpu-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; - - c7x_thermal: c7x-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 2>; - - trips { - c7x_crit: c7x-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; - - gpu_thermal: gpu-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 3>; - - trips { - gpu_crit: gpu-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; - - r5f_thermal: r5f-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 4>; - - trips { - r5f_crit: r5f-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; -}; diff --git a/arch/arm/dts/k3-j721e.dtsi b/arch/arm/dts/k3-j721e.dtsi deleted file mode 100644 index a200810df54..00000000000 --- a/arch/arm/dts/k3-j721e.dtsi +++ /dev/null @@ -1,176 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J721E SoC Family - * - * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include -#include -#include - -#include "k3-pinctrl.h" - -/ { - model = "Texas Instruments K3 J721E SoC"; - compatible = "ti,j721e"; - interrupt-parent = <&gic500>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu-map { - cluster0: cluster0 { - core0 { - cpu = <&cpu0>; - }; - - core1 { - cpu = <&cpu1>; - }; - }; - - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a72"; - reg = <0x000>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a72"; - reg = <0x001>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_0>; - }; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - cache-unified; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - next-level-cache = <&msmc_l3>; - }; - - msmc_l3: l3-cache0 { - compatible = "cache"; - cache-level = <3>; - cache-unified; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - - psci: psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - }; - - a72_timer0: timer-cl0-cpu0 { - compatible = "arm,armv8-timer"; - interrupts = , /* cntpsirq */ - , /* cntpnsirq */ - , /* cntvirq */ - ; /* cnthpirq */ - }; - - pmu: pmu { - compatible = "arm,cortex-a72-pmu"; - /* Recommendation from GIC500 TRM Table A.3 */ - interrupts = ; - }; - - cbass_main: bus@100000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ - <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ - <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ - <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ - <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ - <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */ - <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */ - <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ - <0x00 0x0c000000 0x00 0x0c000000 0x00 0x0d000000>, /* CPSW9G */ - <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ - <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/ - <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/ - <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ - <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */ - <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ - <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */ - <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */ - <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ - <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */ - <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ - <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */ - - /* MCUSS_WKUP Range */ - <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, - <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; - - cbass_mcu_wakeup: bus@28380000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ - <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ - }; - }; - - #include "k3-j721e-thermal.dtsi" -}; - -/* Now include the peripherals for each bus segments */ -#include "k3-j721e-main.dtsi" -#include "k3-j721e-mcu-wakeup.dtsi" diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index b8d7c33c45c..451a6a91c4f 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -14,7 +14,7 @@ CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_ENV_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board" +CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j721e-common-proc-board" CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y @@ -88,7 +88,7 @@ CONFIG_MMC_SPEED_MODE_SET=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="k3-j721e-common-proc-board" +CONFIG_OF_LIST="ti/k3-j721e-common-proc-board" CONFIG_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y @@ -101,6 +101,7 @@ CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y +CONFIG_OF_UPSTREAM=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_TI_SCI=y diff --git a/configs/j721e_sk_a72_defconfig b/configs/j721e_sk_a72_defconfig index 8907b8ae58f..80e3e90cafd 100644 --- a/configs/j721e_sk_a72_defconfig +++ b/configs/j721e_sk_a72_defconfig @@ -5,5 +5,5 @@ CONFIG_ARCH_K3=y CONFIG_SOC_K3_J721E=y CONFIG_TARGET_J721E_A72_EVM=y -CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-sk" -CONFIG_OF_LIST="k3-j721e-sk" +CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j721e-sk" +CONFIG_OF_LIST="ti/k3-j721e-sk" From 145a23450c7ee0c0ed9a68e33a1a52f23705a6b6 Mon Sep 17 00:00:00 2001 From: Manorit Chawdhry Date: Tue, 21 May 2024 16:26:45 +0530 Subject: [PATCH 105/383] include: mach-k3: move k3 security functions to security.h ti_secure_image_post_process and ti_secure_image_check_binary is used for the authentication purposes in the current boot flow. Authentication of remoteproc firmware images require ti_secure_image_post_process to be available outside mach-k3. Signed-off-by: Manorit Chawdhry Signed-off-by: Udit Kumar Signed-off-by: Simon Glass Reviewed-by: Andy Shevchenko # Intel Edison Reviewed-by: Bin Meng --- arch/arm/mach-k3/common.h | 4 ++-- arch/arm/mach-k3/include/mach/security.h | 11 +++++++++++ 2 files changed, 13 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-k3/include/mach/security.h diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index 53aa186b31a..7bd72da1de8 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -2,12 +2,13 @@ /* * K3: Architecture common definitions * - * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla */ #include #include +#include #define K3_FIREWALL_BACKGROUND_BIT (8) @@ -41,7 +42,6 @@ void spl_enable_cache(void); void mmr_unlock(uintptr_t base, u32 partition); bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data); enum k3_device_type get_device_type(void); -void ti_secure_image_post_process(void **p_image, size_t *p_size); struct ti_sci_handle *get_ti_sci_handle(void); void do_board_detect(void); void ti_secure_image_check_binary(void **p_image, size_t *p_size); diff --git a/arch/arm/mach-k3/include/mach/security.h b/arch/arm/mach-k3/include/mach/security.h new file mode 100644 index 00000000000..8502b57bd80 --- /dev/null +++ b/arch/arm/mach-k3/include/mach/security.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * K3: Security related definitions + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * Manorit Chawdhry + */ + +#include + +void ti_secure_image_post_process(void **p_image, size_t *p_size); From 5b5bb51af8b37412f35f6721694e062c59616df4 Mon Sep 17 00:00:00 2001 From: Manorit Chawdhry Date: Tue, 21 May 2024 16:26:46 +0530 Subject: [PATCH 106/383] drivers: remoteproc: ti_k3 : enable secure booting with firmware images Remoteproc firmware images aren't authenticated in the current boot flow. Authenticates remoteproc firmware images to complete the root of trust in secure booting. Signed-off-by: Manorit Chawdhry Signed-off-by: Simon Glass Reviewed-by: Andy Shevchenko # Intel Edison Reviewed-by: Bin Meng --- drivers/remoteproc/ti_k3_dsp_rproc.c | 4 ++++ drivers/remoteproc/ti_k3_r5f_rproc.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/drivers/remoteproc/ti_k3_dsp_rproc.c b/drivers/remoteproc/ti_k3_dsp_rproc.c index 57fe1037da0..7617bbb986d 100644 --- a/drivers/remoteproc/ti_k3_dsp_rproc.c +++ b/drivers/remoteproc/ti_k3_dsp_rproc.c @@ -21,6 +21,7 @@ #include #include #include "ti_sci_proc.h" +#include #define KEYSTONE_RPROC_LOCAL_ADDRESS_MASK (SZ_16M - 1) @@ -127,6 +128,7 @@ static int k3_dsp_load(struct udevice *dev, ulong addr, ulong size) struct k3_dsp_privdata *dsp = dev_get_priv(dev); struct k3_dsp_boot_data *data = dsp->data; u32 boot_vector; + void *image_addr = (void *)addr; int ret; if (dsp->in_use) { @@ -148,6 +150,8 @@ static int k3_dsp_load(struct udevice *dev, ulong addr, ulong size) goto proc_release; } + ti_secure_image_post_process(&image_addr, &size); + ret = rproc_elf_load_image(dev, addr, size); if (ret < 0) { dev_err(dev, "Loading elf failed %d\n", ret); diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c index b55b1dc10d4..b9c6549e185 100644 --- a/drivers/remoteproc/ti_k3_r5f_rproc.c +++ b/drivers/remoteproc/ti_k3_r5f_rproc.c @@ -20,6 +20,7 @@ #include #include #include "ti_sci_proc.h" +#include /* * R5F's view of this address can either be for ATCM or BTCM with the other @@ -301,6 +302,7 @@ static int k3_r5f_load(struct udevice *dev, ulong addr, ulong size) u64 boot_vector; u32 ctrl, sts, cfg = 0; bool mem_auto_init; + void *image_addr = (void *)addr; int ret; dev_dbg(dev, "%s addr = 0x%lx, size = 0x%lx\n", __func__, addr, size); @@ -328,6 +330,8 @@ static int k3_r5f_load(struct udevice *dev, ulong addr, ulong size) k3_r5f_init_tcm_memories(core, mem_auto_init); + ti_secure_image_post_process(&image_addr, &size); + ret = rproc_elf_load_image(dev, addr, size); if (ret < 0) { dev_err(dev, "Loading elf failedi %d\n", ret); From 457d0b5d435cb63e4494e4635a3eeb5b459c6778 Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Tue, 21 May 2024 16:26:47 +0530 Subject: [PATCH 107/383] include: env: ti: Add support for secure firmwares Secure firmwares must be loaded if SOC is secure, currently rproc framework chooses non-secure firmware always. So adding support to load secure firmware, when SOC is secure Signed-off-by: Manorit Chawdhry Signed-off-by: Udit Kumar Signed-off-by: Simon Glass Reviewed-by: Andy Shevchenko # Intel Edison Reviewed-by: Bin Meng --- include/env/ti/k3_rproc.env | 6 +++++- include/env/ti/ti_common.env | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/include/env/ti/k3_rproc.env b/include/env/ti/k3_rproc.env index 87d9d76eba4..d4f0f1708ca 100644 --- a/include/env/ti/k3_rproc.env +++ b/include/env/ti/k3_rproc.env @@ -13,11 +13,15 @@ rproc_load_and_boot_one= boot_rprocs_mmc= env set rproc_id; env set rproc_fw; + env set secure_suffix; + if test ${secure_rprocs} -eq 1; then + env set secure_suffix -sec; + fi; for i in ${rproc_fw_binaries} ; do if test -z "${rproc_id}" ; then env set rproc_id $i; else - env set rproc_fw $i; + env set rproc_fw $i${secure_suffix}; run rproc_load_and_boot_one; env set rproc_id; env set rproc_fw; diff --git a/include/env/ti/ti_common.env b/include/env/ti/ti_common.env index 02b410c3adc..c5c36421770 100644 --- a/include/env/ti/ti_common.env +++ b/include/env/ti/ti_common.env @@ -12,6 +12,7 @@ bootm_size=0x10000000 boot_fdt=try boot_fit=0 +secure_rprocs=0 addr_fit=0x90000000 name_fit=fitImage update_to_fit=setenv loadaddr ${addr_fit}; setenv bootfile ${name_fit} From 4db7d62f858b82b493a7c6a32d5ba25a85a6f9dd Mon Sep 17 00:00:00 2001 From: Manorit Chawdhry Date: Tue, 21 May 2024 16:26:48 +0530 Subject: [PATCH 108/383] mach-k3: common.c: add a flag for booting authenticated rproc binaries The flag will be used for booting authenticated remote procs from hs-se devices which can optionally be used in hs-fs devices also. Signed-off-by: Manorit Chawdhry Signed-off-by: Udit Kumar Signed-off-by: Simon Glass Reviewed-by: Andy Shevchenko # Intel Edison Reviewed-by: Bin Meng --- arch/arm/mach-k3/common.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 1a269d6934a..eaa7d361767 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -283,8 +283,10 @@ int misc_init_r(void) } /* Default FIT boot on HS-SE devices */ - if (get_device_type() == K3_DEVICE_TYPE_HS_SE) + if (get_device_type() == K3_DEVICE_TYPE_HS_SE) { env_set("boot_fit", "1"); + env_set("secure_rprocs", "1"); + } return 0; } From 8b9ed788eadc5a331e48a1b50d4498c8c024ff1f Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Wed, 22 May 2024 10:23:30 +0530 Subject: [PATCH 109/383] configs: j784s4_evm_a72_defconfig: Enable remoteproc drivers The K3 J784S4 SoC has four dual-core R5F subsystems and four C71x DSP subsystems. Set config values to enable the remoteproc functionality with these R5F and DSP subsystems. Signed-off-by: Beleswar Padhi --- configs/j784s4_evm_a72_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig index bb9603bef0f..158d064c19c 100644 --- a/configs/j784s4_evm_a72_defconfig +++ b/configs/j784s4_evm_a72_defconfig @@ -59,6 +59,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y +CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y @@ -134,6 +135,8 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_RAM=y CONFIG_SPL_RAM=y +CONFIG_REMOTEPROC_TI_K3_DSP=y +CONFIG_REMOTEPROC_TI_K3_R5F=y CONFIG_RESET_TI_SCI=y CONFIG_SCSI=y CONFIG_DM_SERIAL=y From 3736453c294c3144758bad1e89ece38395703ea4 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Wed, 22 May 2024 10:23:31 +0530 Subject: [PATCH 110/383] board: ti: j784s4: j784s4.env: Set remoteproc firmware names Include k3_rproc.env to access rproc boot commands and specify rproc firmware names for adding remoteproc support in J784S4 SoCs. Signed-off-by: Beleswar Padhi --- board/ti/j784s4/j784s4.env | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/board/ti/j784s4/j784s4.env b/board/ti/j784s4/j784s4.env index 7e54ca042ef..f5b72c7505e 100644 --- a/board/ti/j784s4/j784s4.env +++ b/board/ti/j784s4/j784s4.env @@ -3,6 +3,10 @@ #include #include +#if CONFIG_CMD_REMOTEPROC +#include +#endif + name_kern=Image console=ttyS2,115200n8 args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02880000 @@ -15,3 +19,5 @@ mmcdev=1 bootpart=1:2 bootdir=/boot rd_spec=- + +rproc_fw_binaries= 2 /lib/firmware/j784s4-main-r5f0_0-fw 3 /lib/firmware/j784s4-main-r5f0_1-fw 4 /lib/firmware/j784s4-main-r5f1_0-fw 5 /lib/firmware/j784s4-main-r5f1_1-fw 6 /lib/firmware/j784s4-main-r5f2_0-fw 7 /lib/firmware/j784s4-main-r5f2_1-fw 8 /lib/firmware/j784s4-c71_0-fw 9 /lib/firmware/j784s4-c71_1-fw 10 /lib/firmware/j784s4-c71_2-fw 11 /lib/firmware/j784s4-c71_3-fw From 0329547377756bc1433c46088e9d1d2a2c93ccdd Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Tue, 21 May 2024 23:18:22 -0700 Subject: [PATCH 111/383] board: phytec: common: Move eeprom read to new function We need to read multiple times from different offsets in API v3. Move the EEPROM read logic into a dedicated function to make it usable multiple times. Signed-off-by: Daniel Schultz Tested-by: Wadim Egorov --- board/phytec/common/phytec_som_detection.c | 46 +++++++++++++--------- 1 file changed, 28 insertions(+), 18 deletions(-) diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c index b14bb3dbb7f..a089fe9bc90 100644 --- a/board/phytec/common/phytec_som_detection.c +++ b/board/phytec/common/phytec_som_detection.c @@ -47,6 +47,31 @@ int phytec_eeprom_data_setup(struct phytec_eeprom_data *data, return ret; } +int phytec_eeprom_read(u8 *data, int bus_num, int addr, int size, int offset) +{ + int ret; + +#if CONFIG_IS_ENABLED(DM_I2C) + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, addr, 2, &dev); + if (ret) { + pr_err("%s: i2c EEPROM not found: %i.\n", __func__, ret); + return ret; + } + + ret = dm_i2c_read(dev, offset, (uint8_t *)data, size); + if (ret) { + pr_err("%s: Unable to read EEPROM data: %i\n", __func__, ret); + return ret; + } +#else + i2c_set_bus_num(bus_num); + ret = i2c_read(addr, offset, 2, (uint8_t *)data, size); +#endif + return ret; +} + int phytec_eeprom_data_init(struct phytec_eeprom_data *data, int bus_num, int addr) { @@ -58,25 +83,10 @@ int phytec_eeprom_data_init(struct phytec_eeprom_data *data, if (!data) data = &eeprom_data; -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, addr, 2, &dev); - if (ret) { - pr_err("%s: i2c EEPROM not found: %i.\n", __func__, ret); + ret = phytec_eeprom_read((u8 *)data, bus_num, addr, + payload_size, 0); + if (ret) goto err; - } - - ret = dm_i2c_read(dev, 0, (uint8_t *)data, payload_size); - if (ret) { - pr_err("%s: Unable to read EEPROM data: %i\n", __func__, ret); - goto err; - } -#else - i2c_set_bus_num(bus_num); - ret = i2c_read(addr, 0, 2, (uint8_t *)data, - sizeof(struct phytec_eeprom_data)); -#endif if (data->payload.api_rev == 0xff) { pr_err("%s: EEPROM is not flashed. Prototype?\n", __func__); From 38b96407f69469702b60a22aa847bf7675a1f9b7 Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Tue, 21 May 2024 23:18:23 -0700 Subject: [PATCH 112/383] board: phytec: common: Define PHYTEC_API2_DATA_LEN The EEPROM image length for API v2 is fixed to 32 bytes. No need to use sizeof while this value won't change. This value is also be required for API v3 to know where the API v3 header starts. Signed-off-by: Daniel Schultz Tested-by: Wadim Egorov --- board/phytec/common/phytec_som_detection.c | 9 ++++----- board/phytec/common/phytec_som_detection.h | 2 ++ 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c index a089fe9bc90..f0e35d8d2ec 100644 --- a/board/phytec/common/phytec_som_detection.c +++ b/board/phytec/common/phytec_som_detection.c @@ -78,13 +78,12 @@ int phytec_eeprom_data_init(struct phytec_eeprom_data *data, int ret, i; unsigned int crc; u8 *ptr; - const unsigned int payload_size = sizeof(struct phytec_eeprom_payload); if (!data) data = &eeprom_data; ret = phytec_eeprom_read((u8 *)data, bus_num, addr, - payload_size, 0); + PHYTEC_API2_DATA_LEN, 0); if (ret) goto err; @@ -95,11 +94,11 @@ int phytec_eeprom_data_init(struct phytec_eeprom_data *data, } ptr = (u8 *)data; - for (i = 0; i < payload_size; ++i) + for (i = 0; i < PHYTEC_API2_DATA_LEN; ++i) if (ptr[i] != 0x0) break; - if (i == payload_size) { + if (i == PHYTEC_API2_DATA_LEN) { pr_err("%s: EEPROM data is all zero. Erased?\n", __func__); ret = -EINVAL; goto err; @@ -111,7 +110,7 @@ int phytec_eeprom_data_init(struct phytec_eeprom_data *data, return 0; } - crc = crc8(0, (const unsigned char *)&data->payload, payload_size); + crc = crc8(0, (const unsigned char *)&data->payload, PHYTEC_API2_DATA_LEN); debug("%s: crc: %x\n", __func__, crc); if (crc) { diff --git a/board/phytec/common/phytec_som_detection.h b/board/phytec/common/phytec_som_detection.h index 0ad5c14ef4e..1ccf36c8e7a 100644 --- a/board/phytec/common/phytec_som_detection.h +++ b/board/phytec/common/phytec_som_detection.h @@ -10,6 +10,8 @@ #define PHYTEC_MAX_OPTIONS 17 #define PHYTEC_EEPROM_INVAL 0xff +#define PHYTEC_API2_DATA_LEN 32 + #define PHYTEC_GET_OPTION(option) \ (((option) > '9') ? (option) - 'A' + 10 : (option) - '0') From 2c3afb76d74f4218edcbc25b4f851d45ee0964c7 Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Tue, 21 May 2024 23:18:24 -0700 Subject: [PATCH 113/383] board: phytec: common: Move API v2 init to new function Move the entire initialization code for API v2 into a dedicated function. This rework will allow to easily integrate the API v3 as next step during init. Signed-off-by: Daniel Schultz Tested-by: Wadim Egorov --- board/phytec/common/phytec_som_detection.c | 38 +++++++++++++--------- 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c index f0e35d8d2ec..ab2d5a7b726 100644 --- a/board/phytec/common/phytec_som_detection.c +++ b/board/phytec/common/phytec_som_detection.c @@ -72,11 +72,29 @@ int phytec_eeprom_read(u8 *data, int bus_num, int addr, int size, int offset) return ret; } +int phytec_eeprom_data_init_v2(struct phytec_eeprom_data *data) +{ + unsigned int crc; + + if (!data) + return -1; + + crc = crc8(0, (const unsigned char *)&data->payload, PHYTEC_API2_DATA_LEN); + debug("%s: crc: %x\n", __func__, crc); + + if (crc) { + pr_err("%s: CRC mismatch. EEPROM data is not usable.\n", + __func__); + return -EINVAL; + } + + return 0; +} + int phytec_eeprom_data_init(struct phytec_eeprom_data *data, int bus_num, int addr) { int ret, i; - unsigned int crc; u8 *ptr; if (!data) @@ -104,20 +122,10 @@ int phytec_eeprom_data_init(struct phytec_eeprom_data *data, goto err; } - /* We are done here for early revisions */ - if (data->payload.api_rev <= PHYTEC_API_REV1) { - data->valid = true; - return 0; - } - - crc = crc8(0, (const unsigned char *)&data->payload, PHYTEC_API2_DATA_LEN); - debug("%s: crc: %x\n", __func__, crc); - - if (crc) { - pr_err("%s: CRC mismatch. EEPROM data is not usable.\n", - __func__); - ret = -EINVAL; - goto err; + if (data->payload.api_rev >= PHYTEC_API_REV2) { + ret = phytec_eeprom_data_init_v2(data); + if (ret) + goto err; } data->valid = true; From b100c2458a13356e33ddcad0cb14906e41522cea Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Tue, 21 May 2024 23:18:25 -0700 Subject: [PATCH 114/383] board: phytec: common: Add API v3 This API is based on a block structure with a 8 Byte large API v3 header and various of different blocks following. It extends our current API v2, which is always 32 Byte large, and is located directly after v2. Add the MAC block as first block type. It contains the physical Ehternet interface number, a MAC address and a CRC checksum over the MAC payload. Signed-off-by: Daniel Schultz Tested-by: Wadim Egorov --- board/phytec/common/Kconfig | 9 ++ board/phytec/common/Makefile | 2 +- board/phytec/common/phytec_som_detection.c | 153 ++++++++++++++++++ board/phytec/common/phytec_som_detection.h | 7 + .../common/phytec_som_detection_blocks.c | 105 ++++++++++++ .../common/phytec_som_detection_blocks.h | 61 +++++++ 6 files changed, 336 insertions(+), 1 deletion(-) create mode 100644 board/phytec/common/phytec_som_detection_blocks.c create mode 100644 board/phytec/common/phytec_som_detection_blocks.h diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig index 1077f0f4b61..668afe2a534 100644 --- a/board/phytec/common/Kconfig +++ b/board/phytec/common/Kconfig @@ -4,6 +4,13 @@ config PHYTEC_SOM_DETECTION help Support of I2C EEPROM based SoM detection. +config PHYTEC_SOM_DETECTION_BLOCKS + bool "Extend SoM detection with block support" + depends on PHYTEC_SOM_DETECTION + help + Extend the I2C EEPROM based SoM detection with API v3. This API + introduces blocks with different payloads. + config PHYTEC_IMX8M_SOM_DETECTION bool "Support SoM detection for i.MX8M PHYTEC platforms" depends on ARCH_IMX8M && PHYTEC_SOM_DETECTION @@ -16,6 +23,7 @@ config PHYTEC_AM62_SOM_DETECTION bool "Support SoM detection for AM62x PHYTEC platforms" depends on (TARGET_PHYCORE_AM62X_A53 || TARGET_PHYCORE_AM62X_R5) && \ PHYTEC_SOM_DETECTION + select PHYTEC_SOM_DETECTION_BLOCKS default y help Support of I2C EEPROM based SoM detection. Supported @@ -25,6 +33,7 @@ config PHYTEC_AM64_SOM_DETECTION bool "Support SoM detection for AM64x PHYTEC platforms" depends on (TARGET_PHYCORE_AM64X_A53 || TARGET_PHYCORE_AM64X_R5) && \ PHYTEC_SOM_DETECTION + select PHYTEC_SOM_DETECTION_BLOCKS default y help Support of I2C EEPROM based SoM detection. Supported diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile index c34fc503059..446c481a6e6 100644 --- a/board/phytec/common/Makefile +++ b/board/phytec/common/Makefile @@ -9,6 +9,6 @@ else obj-$(CONFIG_ARCH_K3) += k3/ endif -obj-y += phytec_som_detection.o +obj-y += phytec_som_detection.o phytec_som_detection_blocks.o obj-$(CONFIG_ARCH_K3) += am6_som_detection.o obj-$(CONFIG_ARCH_IMX8M) += imx8m_som_detection.o diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c index ab2d5a7b726..166c3eae565 100644 --- a/board/phytec/common/phytec_som_detection.c +++ b/board/phytec/common/phytec_som_detection.c @@ -91,6 +91,134 @@ int phytec_eeprom_data_init_v2(struct phytec_eeprom_data *data) return 0; } +#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS) + +int phytec_eeprom_data_init_v3_block(struct phytec_eeprom_data *data, + struct phytec_api3_block_header *header, + u8 *payload) +{ + struct phytec_api3_element *element = NULL; + struct phytec_api3_element *list_iterator; + + if (!header) + return -1; + if (!payload) + return -1; + + debug("%s: block type: %i\n", __func__, header->block_type); + switch (header->block_type) { + case PHYTEC_API3_BLOCK_MAC: + element = phytec_blocks_init_mac(header, payload); + break; + default: + debug("%s: Unknown block type %i\n", __func__, + header->block_type); + } + if (!element) + return -1; + + if (!data->payload.block_head) { + data->payload.block_head = element; + return 0; + } + + list_iterator = data->payload.block_head; + while (list_iterator && list_iterator->next) + list_iterator = list_iterator->next; + list_iterator->next = element; + + return 0; +} + +int phytec_eeprom_data_init_v3(struct phytec_eeprom_data *data, + int bus_num, int addr) +{ + int ret, i; + struct phytec_api3_header header; + unsigned int crc; + u8 *payload; + int block_addr; + struct phytec_api3_block_header *block_header; + + if (!data) + return -1; + + ret = phytec_eeprom_read((uint8_t *)&header, bus_num, addr, + PHYTEC_API3_DATA_HEADER_LEN, + PHYTEC_API2_DATA_LEN); + if (ret) { + pr_err("%s: Failed to read API v3 data header.\n", __func__); + goto err; + } + + crc = crc8(0, (const unsigned char *)&header, + PHYTEC_API3_DATA_HEADER_LEN); + debug("%s: crc: %x\n", __func__, crc); + if (crc) { + pr_err("%s: CRC mismatch. API3 header is unusable.\n", + __func__); + goto err; + } + + debug("%s: data length: %i\n", __func__, header.data_length); + payload = malloc(header.data_length); + if (!payload) { + pr_err("%s: Unable to allocate memory\n", __func__); + goto err_payload; + } + + ret = phytec_eeprom_read(payload, bus_num, addr, header.data_length, + PHYTEC_API3_DATA_HEADER_LEN + + PHYTEC_API2_DATA_LEN); + if (ret) { + pr_err("%s: Failed to read API v3 data payload.\n", __func__); + goto err_payload; + } + + block_addr = 0; + debug("%s: block count: %i\n", __func__, header.block_count); + for (i = 0; i < header.block_count; i++) { + debug("%s: block_addr: %i\n", __func__, block_addr); + block_header = (struct phytec_api3_block_header *) + &payload[block_addr]; + crc = crc8(0, (const unsigned char *)block_header, + PHYTEC_API3_BLOCK_HEADER_LEN); + + debug("%s: crc: %x\n", __func__, crc); + if (crc) { + pr_err("%s: CRC mismatch. API3 block header is unusable\n", + __func__); + goto err_payload; + } + + ret = phytec_eeprom_data_init_v3_block(data, block_header, + &payload[block_addr + PHYTEC_API3_BLOCK_HEADER_LEN]); + /* Ignore failed block initialization and continue. */ + if (ret) + debug("%s: Unable to create block with index %i.\n", + __func__, i); + + block_addr = block_header->next_block; + } + + free(payload); + return 0; +err_payload: + free(payload); +err: + return -1; +} + +#else + +inline int phytec_eeprom_data_init_v3(struct phytec_eeprom_data *data, + int bus_num, int addr) +{ + return 0; +} + +#endif + int phytec_eeprom_data_init(struct phytec_eeprom_data *data, int bus_num, int addr) { @@ -104,6 +232,7 @@ int phytec_eeprom_data_init(struct phytec_eeprom_data *data, PHYTEC_API2_DATA_LEN, 0); if (ret) goto err; + data->payload.block_head = NULL; if (data->payload.api_rev == 0xff) { pr_err("%s: EEPROM is not flashed. Prototype?\n", __func__); @@ -128,6 +257,13 @@ int phytec_eeprom_data_init(struct phytec_eeprom_data *data, goto err; } + if (IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS)) + if (data->payload.api_rev >= PHYTEC_API_REV3) { + ret = phytec_eeprom_data_init_v3(data, bus_num, addr); + if (ret) + goto err; + } + data->valid = true; return 0; err: @@ -265,6 +401,17 @@ struct extension *phytec_add_extension(const char *name, const char *overlay, } #endif /* IS_ENABLED(CONFIG_CMD_EXTENSION) */ +struct phytec_api3_element * + __maybe_unused phytec_get_block_head(struct phytec_eeprom_data *data) +{ + if (!data) + data = &eeprom_data; + if (!data->valid) + return NULL; + + return data->payload.block_head; +} + #else inline int phytec_eeprom_data_setup(struct phytec_eeprom_data *data, @@ -305,6 +452,12 @@ u8 __maybe_unused phytec_get_som_type(struct phytec_eeprom_data *data) return PHYTEC_EEPROM_INVAL; } +inline struct phytec_api3_element * __maybe_unused + phytec_get_block_head(struct phytec_eeprom_data *data) +{ + return NULL; +} + #if IS_ENABLED(CONFIG_CMD_EXTENSION) inline struct extension *phytec_add_extension(const char *name, const char *overlay, diff --git a/board/phytec/common/phytec_som_detection.h b/board/phytec/common/phytec_som_detection.h index 1ccf36c8e7a..5e35a13cb21 100644 --- a/board/phytec/common/phytec_som_detection.h +++ b/board/phytec/common/phytec_som_detection.h @@ -7,6 +7,8 @@ #ifndef _PHYTEC_SOM_DETECTION_H #define _PHYTEC_SOM_DETECTION_H +#include "phytec_som_detection_blocks.h" + #define PHYTEC_MAX_OPTIONS 17 #define PHYTEC_EEPROM_INVAL 0xff @@ -19,6 +21,7 @@ enum { PHYTEC_API_REV0 = 0, PHYTEC_API_REV1, PHYTEC_API_REV2, + PHYTEC_API_REV3, }; enum phytec_som_type_str { @@ -63,6 +66,7 @@ struct phytec_eeprom_payload { struct phytec_api0_data data_api0; struct phytec_api2_data data_api2; } data; + struct phytec_api3_element *block_head; } __packed; struct phytec_eeprom_data { @@ -88,4 +92,7 @@ struct extension *phytec_add_extension(const char *name, const char *overlay, const char *other); #endif /* IS_ENABLED(CONFIG_CMD_EXTENSION) */ +struct phytec_api3_element * + __maybe_unused phytec_get_block_head(struct phytec_eeprom_data *data); + #endif /* _PHYTEC_SOM_DETECTION_H */ diff --git a/board/phytec/common/phytec_som_detection_blocks.c b/board/phytec/common/phytec_som_detection_blocks.c new file mode 100644 index 00000000000..5f3c27ef0c2 --- /dev/null +++ b/board/phytec/common/phytec_som_detection_blocks.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Daniel Schultz + */ + +#include +#include +#include +#include + +#include "phytec_som_detection_blocks.h" + +#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS) + +struct phytec_api3_element * + phytec_blocks_init_mac(struct phytec_api3_block_header *header, + uint8_t *payload) +{ + struct phytec_api3_element *element; + struct phytec_api3_block_mac *mac; + unsigned int crc; + unsigned int len = sizeof(struct phytec_api3_block_mac); + + if (!header) + return NULL; + if (!payload) + return NULL; + + element = (struct phytec_api3_element *) + calloc(8, PHYTEC_API3_ELEMENT_HEADER_SIZE + len); + if (!element) { + pr_err("%s: Unable to allocate memory\n", __func__); + return NULL; + } + element->block_type = header->block_type; + memcpy(&element->block.mac, payload, len); + mac = &element->block.mac; + + debug("%s: interface: %i\n", __func__, mac->interface); + debug("%s: MAC %pM\n", __func__, mac->address); + + crc = crc8(0, (const unsigned char *)mac, len); + debug("%s: crc: %x\n", __func__, crc); + if (crc) { + pr_err("%s: CRC mismatch. API3 block payload is unusable\n", + __func__); + return NULL; + } + + return element; +} + +int __maybe_unused + phytec_blocks_add_mac_to_env(struct phytec_api3_element *element) +{ + char enetenv[9] = "ethaddr"; + char buf[ARP_HLEN_ASCII + 1]; + struct phytec_api3_block_mac *block = &element->block.mac; + int ret; + + if (!is_valid_ethaddr(block->address)) { + pr_err("%s: Invalid MAC address in block.\n", __func__); + return -1; + } + + if (block->interface > 0) { + ret = sprintf(enetenv, "eth%iaddr", block->interface); + if (ret != 8) { + pr_err("%s: Unable to create env string\n", __func__); + return -1; + } + } + + ret = sprintf(buf, "%pM", block->address); + if (ret != ARP_HLEN_ASCII) { + pr_err("%s: Unable to convert MAC address\n", __func__); + return -1; + } + ret = env_set(enetenv, buf); + if (ret) { + pr_err("%s: Failed to set MAC address to env.\n", __func__); + return -1; + } + + debug("%s: Added %s to %s\n", __func__, buf, enetenv); + return 0; +} + +#else + +inline struct phytec_api3_element * + phytec_api3_init_mac_block(struct phytec_api3_block_header *header, + uint8_t *payload) +{ + return NULL; +} + +inline int __maybe_unused + phytec_blocks_add_mac_to_env(struct phytec_api3_element *element) +{ + return -1; +} + +#endif diff --git a/board/phytec/common/phytec_som_detection_blocks.h b/board/phytec/common/phytec_som_detection_blocks.h new file mode 100644 index 00000000000..2a5a83c9039 --- /dev/null +++ b/board/phytec/common/phytec_som_detection_blocks.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Daniel Schultz + */ + +#ifndef _PHYTEC_SOM_DETECTION_BLOCKS_H +#define _PHYTEC_SOM_DETECTION_BLOCKS_H + +#define PHYTEC_API3_DATA_HEADER_LEN 8 +#define PHYTEC_API3_BLOCK_HEADER_LEN 4 +#define PHYTEC_API3_PAYLOAD_START \ + (PHYTEC_API2_DATA_LEN + PHYTEC_API3_DATA_HEADER_LEN) + +#define PHYTEC_API3_ELEMENT_HEADER_SIZE \ + (sizeof(struct phytec_api3_element *) + \ + sizeof(enum phytec_api3_block_types)) + +#define PHYTEC_API3_FOREACH_BLOCK(elem, data) \ + for (elem = phytec_get_block_head(data); elem; elem = elem->next) + +struct phytec_api3_header { + u16 data_length; /* Total length in Bytes of all blocks */ + u8 block_count; /* Number of blocks */ + u8 sub_version; /* Block specification version */ + u8 reserved[3]; /* Reserved */ + u8 crc8; /* checksum */ +} __packed; + +struct phytec_api3_block_header { + u8 block_type; /* Block payload identifier */ + u16 next_block; /* Address of the next block */ + u8 crc8; /* checksum */ +} __packed; + +enum phytec_api3_block_types { + PHYTEC_API3_BLOCK_MAC = 0, +}; + +struct phytec_api3_block_mac { + u8 interface; /* Ethernet interface number */ + u8 address[6]; /* MAC-Address */ + u8 crc8; /* checksum */ +} __packed; + +struct phytec_api3_element { + struct phytec_api3_element *next; + enum phytec_api3_block_types block_type; + union { + struct phytec_api3_block_mac mac; + } block; +} __packed; + +struct phytec_api3_element * + phytec_blocks_init_mac(struct phytec_api3_block_header *header, + uint8_t *payload); + +int __maybe_unused +phytec_blocks_add_mac_to_env(struct phytec_api3_element *element); + +#endif /* _PHYTEC_SOM_DETECTION_BLOCKS_H */ From 946ae83246e89c05ddb83af6637b8af29f32bc2f Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Tue, 21 May 2024 23:18:26 -0700 Subject: [PATCH 115/383] board: phytec: common: k3: Set MAC Read the EEPROM API v3 content and set all available MAC-Addresses to the environment. Signed-off-by: Daniel Schultz Reviewed-by: Wadim Egorov Tested-by: Wadim Egorov --- board/phytec/common/k3/board.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c index 9cb168c36cb..f21e154d4fe 100644 --- a/board/phytec/common/k3/board.c +++ b/board/phytec/common/k3/board.c @@ -8,6 +8,8 @@ #include #include +#include "../am6_som_detection.h" + #if IS_ENABLED(CONFIG_ENV_IS_IN_FAT) || IS_ENABLED(CONFIG_ENV_IS_IN_MMC) int mmc_get_env_dev(void) { @@ -68,6 +70,27 @@ int board_late_init(void) break; }; + if (IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS)) { + struct phytec_api3_element *block_element; + struct phytec_eeprom_data data; + int ret; + + ret = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR); + if (ret || !data.valid) + return 0; + + PHYTEC_API3_FOREACH_BLOCK(block_element, &data) { + switch (block_element->block_type) { + case PHYTEC_API3_BLOCK_MAC: + phytec_blocks_add_mac_to_env(block_element); + break; + default: + debug("%s: Unknown block type %i\n", __func__, + block_element->block_type); + } + } + } + return 0; } #endif From 7377f7e3f67c4c6d7c8ea5db15c6d3fe8d780770 Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Tue, 21 May 2024 23:18:27 -0700 Subject: [PATCH 116/383] configs: phycore_am62x_a53_defconfig: Enable CONFIG_ENV_OVERWRITE Enable CONFIG_ENV_OVERWRITE to overwrite ethaddr in the environment. This is required because our environment is not located in the boot partition. Signed-off-by: Daniel Schultz Tested-by: Wadim Egorov --- configs/phycore_am62x_a53_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index fd36edc29dd..286cd89c5a6 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -59,6 +59,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_NET_RANDOM_ETHADDR=y From 12f09c19b7c9cc9c4cbe88b0c33f69eea716c344 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Wed, 22 May 2024 09:55:01 +0200 Subject: [PATCH 117/383] board: phytec: Make AM6 SoM detection depend on I2C SoM detection is using I2C driver model functions. Let's depend on I2C. Signed-off-by: Wadim Egorov Tested-by: John Ma Reviewed-by: Dhruva Gole --- board/phytec/common/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig index 1077f0f4b61..56c8290f641 100644 --- a/board/phytec/common/Kconfig +++ b/board/phytec/common/Kconfig @@ -16,6 +16,7 @@ config PHYTEC_AM62_SOM_DETECTION bool "Support SoM detection for AM62x PHYTEC platforms" depends on (TARGET_PHYCORE_AM62X_A53 || TARGET_PHYCORE_AM62X_R5) && \ PHYTEC_SOM_DETECTION + depends on SPL_I2C && DM_I2C default y help Support of I2C EEPROM based SoM detection. Supported @@ -25,6 +26,7 @@ config PHYTEC_AM64_SOM_DETECTION bool "Support SoM detection for AM64x PHYTEC platforms" depends on (TARGET_PHYCORE_AM64X_A53 || TARGET_PHYCORE_AM64X_R5) && \ PHYTEC_SOM_DETECTION + depends on SPL_I2C && DM_I2C default y help Support of I2C EEPROM based SoM detection. Supported From 161acbdfb0fc00c41845aded6667479be2a99e95 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Wed, 22 May 2024 09:55:02 +0200 Subject: [PATCH 118/383] board: phytec: Fix function definitions in AM6x SOM detection Functions are declared as phytec_am6* and not phytec_am62*. Update the definitions to match the declarations. Fixes: 9d152c23279c ("board: phytec: Add SOM detection for AM6x") Signed-off-by: Wadim Egorov Tested-by: John Ma Reviewed-by: Dhruva Gole --- board/phytec/common/am6_som_detection.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/board/phytec/common/am6_som_detection.c b/board/phytec/common/am6_som_detection.c index 2e9884dab44..7930ab42d1c 100644 --- a/board/phytec/common/am6_som_detection.c +++ b/board/phytec/common/am6_som_detection.c @@ -73,7 +73,7 @@ static u8 phytec_check_opt(struct phytec_eeprom_data *data, u8 option) * - The size * - PHYTEC_EEPROM_INVAL when the data is invalid. */ -u8 __maybe_unused phytec_get_am62_ddr_size(struct phytec_eeprom_data *data) +u8 __maybe_unused phytec_get_am6_ddr_size(struct phytec_eeprom_data *data) { u8 ddr_id = phytec_check_opt(data, 3); @@ -89,7 +89,7 @@ u8 __maybe_unused phytec_get_am62_ddr_size(struct phytec_eeprom_data *data) * - Otherwise a board depended code for the size. * - PHYTEC_EEPROM_INVAL when the data is invalid. */ -u8 __maybe_unused phytec_get_am62_spi(struct phytec_eeprom_data *data) +u8 __maybe_unused phytec_get_am6_spi(struct phytec_eeprom_data *data) { u8 spi = phytec_check_opt(data, 5); @@ -105,7 +105,7 @@ u8 __maybe_unused phytec_get_am62_spi(struct phytec_eeprom_data *data) * - 0x1 if 10/100/1000 MBit Phy is populated. * - PHYTEC_EEPROM_INVAL when the data is invalid. */ -u8 __maybe_unused phytec_get_am62_eth(struct phytec_eeprom_data *data) +u8 __maybe_unused phytec_get_am6_eth(struct phytec_eeprom_data *data) { u8 eth = phytec_check_opt(data, 6); @@ -121,7 +121,7 @@ u8 __maybe_unused phytec_get_am62_eth(struct phytec_eeprom_data *data) * - 1 if it is populated. * - PHYTEC_EEPROM_INVAL when the data is invalid. */ -u8 __maybe_unused phytec_get_am62_rtc(struct phytec_eeprom_data *data) +u8 __maybe_unused phytec_get_am6_rtc(struct phytec_eeprom_data *data) { u8 rtc = phytec_check_opt(data, 7); @@ -131,28 +131,28 @@ u8 __maybe_unused phytec_get_am62_rtc(struct phytec_eeprom_data *data) #else -inline int __maybe_unused phytec_am62_detect(struct phytec_eeprom_data *data) +inline int __maybe_unused phytec_am6_detect(struct phytec_eeprom_data *data) { return -1; } inline u8 __maybe_unused -phytec_get_am62_ddr_size(struct phytec_eeprom_data *data) +phytec_get_am6_ddr_size(struct phytec_eeprom_data *data) { return PHYTEC_EEPROM_INVAL; } -inline u8 __maybe_unused phytec_get_am62_spi(struct phytec_eeprom_data *data) +inline u8 __maybe_unused phytec_get_am6_spi(struct phytec_eeprom_data *data) { return PHYTEC_EEPROM_INVAL; } -inline u8 __maybe_unused phytec_get_am62_eth(struct phytec_eeprom_data *data) +inline u8 __maybe_unused phytec_get_am6_eth(struct phytec_eeprom_data *data) { return PHYTEC_EEPROM_INVAL; } -inline u8 __maybe_unused phytec_get_am62_rtc(struct phytec_eeprom_data *data) +inline u8 __maybe_unused phytec_get_am6_rtc(struct phytec_eeprom_data *data) { return PHYTEC_EEPROM_INVAL; } From e63908adbdf0b2dfada86fe848006f572f7df4a3 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Wed, 22 May 2024 09:55:03 +0200 Subject: [PATCH 119/383] arm: mach-k3: am625: Call do_board_detect() before DDR probing Call do_board_detect() hook before the K3 DDRSS driver gets probed. It will allow boards to adjust DDR timings in do_board_detect(). Signed-off-by: Wadim Egorov Tested-by: John Ma --- arch/arm/mach-k3/am62x/am625_init.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-k3/am62x/am625_init.c b/arch/arm/mach-k3/am62x/am625_init.c index ed8d24e0433..72a752d38e8 100644 --- a/arch/arm/mach-k3/am62x/am625_init.c +++ b/arch/arm/mach-k3/am62x/am625_init.c @@ -213,6 +213,8 @@ void board_init_f(ulong dummy) preloader_console_init(); + do_board_detect(); + /* * Allow establishing an early console as required for example when * doing a UART-based boot. Note that this console may not "survive" From cbf5c99ef317a135ffa9127794d3442a687e4fb8 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Wed, 22 May 2024 09:55:04 +0200 Subject: [PATCH 120/383] board: phytec: common: Introduce a method to inject DDR timings deltas Introduce fdt_apply_ddrss_timings_patch() to allow board code to override DDR settings in the device tree prior to DDRSS driver probing. Signed-off-by: Wadim Egorov Tested-by: John Ma --- board/phytec/common/Makefile | 4 +- board/phytec/common/k3/Makefile | 1 + board/phytec/common/k3/k3_ddrss_patch.c | 68 +++++++++++++++++++++++++ board/phytec/common/k3/k3_ddrss_patch.h | 28 ++++++++++ board/phytec/phycore_am62x/MAINTAINERS | 1 + 5 files changed, 99 insertions(+), 3 deletions(-) create mode 100644 board/phytec/common/k3/k3_ddrss_patch.c create mode 100644 board/phytec/common/k3/k3_ddrss_patch.h diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile index c34fc503059..988c5742db5 100644 --- a/board/phytec/common/Makefile +++ b/board/phytec/common/Makefile @@ -5,10 +5,8 @@ ifdef CONFIG_SPL_BUILD # necessary to create built-in.o obj- := __dummy__.o -else -obj-$(CONFIG_ARCH_K3) += k3/ endif obj-y += phytec_som_detection.o -obj-$(CONFIG_ARCH_K3) += am6_som_detection.o +obj-$(CONFIG_ARCH_K3) += am6_som_detection.o k3/ obj-$(CONFIG_ARCH_IMX8M) += imx8m_som_detection.o diff --git a/board/phytec/common/k3/Makefile b/board/phytec/common/k3/Makefile index bcca1a9f846..40e91a43e99 100644 --- a/board/phytec/common/k3/Makefile +++ b/board/phytec/common/k3/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y += board.o +obj-$(CONFIG_K3_DDRSS) += k3_ddrss_patch.o diff --git a/board/phytec/common/k3/k3_ddrss_patch.c b/board/phytec/common/k3/k3_ddrss_patch.c new file mode 100644 index 00000000000..39f7be8dc92 --- /dev/null +++ b/board/phytec/common/k3/k3_ddrss_patch.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov + */ + +#include "k3_ddrss_patch.h" + +#include +#include + +#ifdef CONFIG_K3_AM64_DDRSS +#define LPDDR4_INTR_CTL_REG_COUNT (423U) +#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (345U) +#endif + +static int fdt_setprop_inplace_idx_u32(void *fdt, int nodeoffset, + const char *name, uint32_t idx, u32 val) +{ + val = cpu_to_be32(val); + return fdt_setprop_inplace_namelen_partial(fdt, nodeoffset, name, + strlen(name), + idx * sizeof(val), &val, + sizeof(val)); +} + +int fdt_apply_ddrss_timings_patch(void *fdt, struct ddrss *ddrss) +{ + int i, j; + int ret; + int mem_offset; + + mem_offset = fdt_path_offset(fdt, "/memorycontroller@f300000"); + if (mem_offset < 0) + return -ENODEV; + + for (i = 0; i < LPDDR4_INTR_CTL_REG_COUNT; i++) + for (j = 0; j < ddrss->ctl_regs_num; j++) + if (i == ddrss->ctl_regs[j].off) { + ret = fdt_setprop_inplace_idx_u32(fdt, + mem_offset, "ti,ctl-data", i, + ddrss->ctl_regs[j].val); + if (ret) + return ret; + } + + for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++) + for (j = 0; j < ddrss->pi_regs_num; j++) + if (i == ddrss->pi_regs[j].off) { + ret = fdt_setprop_inplace_idx_u32(fdt, + mem_offset, "ti,pi-data", i, + ddrss->pi_regs[j].val); + if (ret) + return ret; + } + + for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++) + for (j = 0; j < ddrss->phy_regs_num; j++) + if (i == ddrss->phy_regs[j].off) { + ret = fdt_setprop_inplace_idx_u32(fdt, + mem_offset, "ti,phy-data", i, + ddrss->phy_regs[j].val); + if (ret) + return ret; + } + + return 0; +} diff --git a/board/phytec/common/k3/k3_ddrss_patch.h b/board/phytec/common/k3/k3_ddrss_patch.h new file mode 100644 index 00000000000..0a47c85116a --- /dev/null +++ b/board/phytec/common/k3/k3_ddrss_patch.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov + */ + +#ifndef K3_DDRSS_PATCH +#define K3_DDRSS_PATCH + +#include + +struct ddr_reg { + u32 off; + u32 val; +}; + +struct ddrss { + struct ddr_reg *ctl_regs; + u32 ctl_regs_num; + struct ddr_reg *pi_regs; + u32 pi_regs_num; + struct ddr_reg *phy_regs; + u32 phy_regs_num; +}; + +int fdt_apply_ddrss_timings_patch(void *fdt, struct ddrss *ddrss); + +#endif /* K3_DDRSS_PATCH */ diff --git a/board/phytec/phycore_am62x/MAINTAINERS b/board/phytec/phycore_am62x/MAINTAINERS index 02ac88e58a4..42463ad054e 100644 --- a/board/phytec/phycore_am62x/MAINTAINERS +++ b/board/phytec/phycore_am62x/MAINTAINERS @@ -11,3 +11,4 @@ F: configs/phycore_am62x_a53_defconfig F: configs/phycore_am62x_r5_defconfig F: include/configs/phycore_am62x.h F: doc/board/phytec/phycore-am62x.rst +F: board/phytec/common/k3 From 0be402375d9fcddc7d4910f1918d2475c21dd735 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Wed, 22 May 2024 09:55:05 +0200 Subject: [PATCH 121/383] board: phytec: am62x: Add support for 1 & 4 GB RAM variants Use content of EEPROM to detect the actual RAM size and adjust DDR timings, size and banks accordingly. Also enable the SoM detection per default in the defconfigs. Signed-off-by: Wadim Egorov Tested-by: John Ma --- board/phytec/common/am6_som_detection.h | 8 + board/phytec/phycore_am62x/Kconfig | 30 +++ board/phytec/phycore_am62x/phycore-am62x.c | 152 ++++++++++++- board/phytec/phycore_am62x/phycore-ddr-data.h | 206 ++++++++++++++++++ configs/phycore_am62x_a53_defconfig | 4 + configs/phycore_am62x_r5_defconfig | 4 + 6 files changed, 402 insertions(+), 2 deletions(-) create mode 100644 board/phytec/phycore_am62x/phycore-ddr-data.h diff --git a/board/phytec/common/am6_som_detection.h b/board/phytec/common/am6_som_detection.h index 032f9da3aab..c5c6e179da6 100644 --- a/board/phytec/common/am6_som_detection.h +++ b/board/phytec/common/am6_som_detection.h @@ -9,11 +9,19 @@ #include "phytec_som_detection.h" +#define EEPROM_ADDR 0x50 #define PHYTEC_AM62X_SOM 71 #define PHYTEC_AM64X_SOM 72 #define PHYTEC_EEPROM_VALUE_X 0x21 #define PHYTEC_EEPROM_NOR_FLASH_64MB_QSPI 0xC +enum { + EEPROM_RAM_SIZE_512MB = 0, + EEPROM_RAM_SIZE_1GB = 1, + EEPROM_RAM_SIZE_2GB = 2, + EEPROM_RAM_SIZE_4GB = 4 +}; + int __maybe_unused phytec_am6_detect(struct phytec_eeprom_data *data); u8 __maybe_unused phytec_get_am6_ddr_size(struct phytec_eeprom_data *data); u8 __maybe_unused phytec_get_am6_spi(struct phytec_eeprom_data *data); diff --git a/board/phytec/phycore_am62x/Kconfig b/board/phytec/phycore_am62x/Kconfig index 1de8850c6c4..7c179ef0078 100644 --- a/board/phytec/phycore_am62x/Kconfig +++ b/board/phytec/phycore_am62x/Kconfig @@ -35,3 +35,33 @@ config SPL_LDSCRIPT source "board/phytec/common/Kconfig" endif + +config PHYCORE_AM62X_RAM_SIZE_FIX + bool "Set phyCORE-AM62x RAM size fix instead of detecting" + default false + help + RAM size is automatic being detected with the help of + the EEPROM introspection data. Set RAM size to a fix value + instead. + +choice + prompt "phyCORE-AM62x RAM size" + depends on PHYCORE_AM62X_RAM_SIZE_FIX + default PHYCORE_AM62X_RAM_SIZE_2GB + +config PHYCORE_AM62X_RAM_SIZE_1GB + bool "1GB RAM" + help + Set RAM size fix to 1GB for phyCORE-AM62x. + +config PHYCORE_AM62X_RAM_SIZE_2GB + bool "2GB RAM" + help + Set RAM size fix to 2GB for phyCORE-AM62x. + +config PHYCORE_AM62X_RAM_SIZE_4GB + bool "4GB RAM" + help + Set RAM size fix to 4GB for phyCORE-AM62x. + +endchoice diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c index a082b886bda..4a76f1343d7 100644 --- a/board/phytec/phycore_am62x/phycore-am62x.c +++ b/board/phytec/phycore_am62x/phycore-am62x.c @@ -8,6 +8,13 @@ #include #include +#include "phycore-ddr-data.h" +#include "../common/k3/k3_ddrss_patch.h" +#include "../common/am6_som_detection.h" + +#define AM64_DDRSS_SS_BASE 0x0F300000 +#define DDRSS_V2A_CTL_REG 0x0020 + DECLARE_GLOBAL_DATA_PTR; int board_init(void) @@ -15,16 +22,157 @@ int board_init(void) return 0; } +static u8 phytec_get_am62_ddr_size_default(void) +{ + int ret; + struct phytec_eeprom_data data; + + if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_FIX)) { + if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_1GB)) + return EEPROM_RAM_SIZE_1GB; + else if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_2GB)) + return EEPROM_RAM_SIZE_2GB; + else if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_4GB)) + return EEPROM_RAM_SIZE_4GB; + } + + ret = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR); + if (!ret && data.valid) + return phytec_get_am6_ddr_size(&data); + + /* Default DDR size is 2GB */ + return EEPROM_RAM_SIZE_2GB; +} + int dram_init(void) { - return fdtdec_setup_mem_size_base(); + u8 ram_size = phytec_get_am62_ddr_size_default(); + + /* + * HACK: ddrss driver support 2GB RAM by default + * V2A_CTL_REG should be updated to support other RAM size + */ + if (IS_ENABLED(CONFIG_K3_AM64_DDRSS)) + if (ram_size == EEPROM_RAM_SIZE_4GB) + writel(0x00000210, AM64_DDRSS_SS_BASE + DDRSS_V2A_CTL_REG); + + switch (ram_size) { + case EEPROM_RAM_SIZE_1GB: + gd->ram_size = 0x40000000; + break; + case EEPROM_RAM_SIZE_2GB: + gd->ram_size = 0x80000000; + break; + case EEPROM_RAM_SIZE_4GB: +#ifdef CONFIG_PHYS_64BIT + gd->ram_size = 0x100000000; +#else + gd->ram_size = 0x80000000; +#endif + break; + default: + gd->ram_size = 0x80000000; + } + + return 0; +} + +phys_size_t board_get_usable_ram_top(phys_size_t total_size) +{ +#ifdef CONFIG_PHYS_64BIT + /* Limit RAM used by U-Boot to the DDR low region */ + if (gd->ram_top > 0x100000000) + return 0x100000000; +#endif + return gd->ram_top; } int dram_init_banksize(void) { - return fdtdec_setup_memory_banksize(); + u8 ram_size; + + ram_size = phytec_get_am62_ddr_size_default(); + switch (ram_size) { + case EEPROM_RAM_SIZE_1GB: + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x40000000; + gd->ram_size = 0x40000000; + break; + + case EEPROM_RAM_SIZE_2GB: + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x80000000; + gd->ram_size = 0x80000000; + break; + + case EEPROM_RAM_SIZE_4GB: + /* Bank 0 declares the memory available in the DDR low region */ + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x80000000; + gd->ram_size = 0x80000000; + +#ifdef CONFIG_PHYS_64BIT + /* Bank 1 declares the memory available in the DDR upper region */ + gd->bd->bi_dram[1].start = 0x880000000; + gd->bd->bi_dram[1].size = 0x80000000; + gd->ram_size = 0x100000000; +#endif + break; + default: + /* Continue with default 2GB setup */ + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x80000000; + gd->ram_size = 0x80000000; + printf("DDR size %d is not supported\n", ram_size); + } + + return 0; } +#if defined(CONFIG_K3_DDRSS) +int update_ddrss_timings(void) +{ + int ret; + u8 ram_size; + struct ddrss *ddr_patch = NULL; + void *fdt = (void *)gd->fdt_blob; + + ram_size = phytec_get_am62_ddr_size_default(); + switch (ram_size) { + case EEPROM_RAM_SIZE_1GB: + ddr_patch = &phycore_ddrss_data[PHYCORE_1GB]; + break; + case EEPROM_RAM_SIZE_2GB: + ddr_patch = NULL; + break; + case EEPROM_RAM_SIZE_4GB: + ddr_patch = &phycore_ddrss_data[PHYCORE_4GB]; + break; + default: + break; + } + + /* Nothing to patch */ + if (!ddr_patch) + return 0; + + debug("Applying DDRSS timings patch for ram_size %d\n", ram_size); + + ret = fdt_apply_ddrss_timings_patch(fdt, ddr_patch); + if (ret < 0) { + printf("Failed to apply ddrs timings patch %d\n", ret); + return ret; + } + + return 0; +} + +int do_board_detect(void) +{ + return update_ddrss_timings(); +} +#endif + #define CTRLMMR_USB0_PHY_CTRL 0x43004008 #define CTRLMMR_USB1_PHY_CTRL 0x43004018 #define CORE_VOLTAGE 0x80000000 diff --git a/board/phytec/phycore_am62x/phycore-ddr-data.h b/board/phytec/phycore_am62x/phycore-ddr-data.h new file mode 100644 index 00000000000..fe6eccd959e --- /dev/null +++ b/board/phytec/phycore_am62x/phycore-ddr-data.h @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov + */ + +#ifndef PHYCORE_DDR_DATA +#define PHYCORE_DDR_DATA + +#include "../common/k3/k3_ddrss_patch.h" + +/* 1 GB variant delta */ +struct ddr_reg ddr_1gb_ctl_regs[] = { + { 55, 0x0400DB60 }, + { 58, 0x0400DB60 }, + { 61, 0x0400DB60 }, + { 73, 0x00001860 }, + { 75, 0x00001860 }, + { 77, 0x00001860 }, + { 119, 0x00061800 }, + { 120, 0x00061800 }, + { 121, 0x00061800 }, + { 122, 0x00061800 }, + { 123, 0x00061800 }, + { 125, 0x0000AAA0 }, + { 126, 0x00061800 }, + { 127, 0x00061800 }, + { 128, 0x00061800 }, + { 129, 0x00061800 }, + { 130, 0x00061800 }, + { 132, 0x0000AAA0 }, + { 133, 0x00061800 }, + { 134, 0x00061800 }, + { 135, 0x00061800 }, + { 136, 0x00061800 }, + { 137, 0x00061800 }, + { 139, 0x0000AAA0 }, + { 206, 0x00000000 }, + { 209, 0x00000000 }, + { 212, 0x00000000 }, + { 215, 0x00000000 }, + { 218, 0x00000000 }, + { 221, 0x00000000 }, + { 230, 0x00000000 }, + { 231, 0x00000000 }, + { 232, 0x00000000 }, + { 233, 0x00000000 }, + { 234, 0x00000000 }, + { 235, 0x00000000 }, + { 316, 0x01010000 }, + { 318, 0x3FFF0000 }, + { 327, 0x00000C01 }, + { 328, 0x00000000 }, + { 385, 0x000030C0 }, + { 390, 0x0000DB60 }, + { 391, 0x0001E780 }, + { 394, 0x000030C0 }, + { 399, 0x0000DB60 }, + { 400, 0x0001E780 }, + { 403, 0x000030C0 }, + { 408, 0x0000DB60 }, + { 409, 0x0001E780 } +}; + +struct ddr_reg ddr_1gb_pi_regs[] = { + { 77, 0x04000100 }, + { 176, 0x00001860 }, + { 178, 0x00001860 }, + { 180, 0x04001860 }, + { 233, 0x0000C570 }, + { 238, 0x0000C570 }, + { 243, 0x0000C570 }, + { 247, 0x000030C0 }, + { 248, 0x0001E780 }, + { 249, 0x000030C0 }, + { 250, 0x0001E780 }, + { 251, 0x000030C0 }, + { 252, 0x0001E780 }, + { 299, 0x00000000 }, + { 301, 0x00000000 }, + { 307, 0x00000000 }, + { 309, 0x00000000 }, + { 315, 0x00000000 }, + { 317, 0x00000000 }, + { 323, 0x00000000 }, + { 325, 0x00000000 }, + { 331, 0x00000000 }, + { 333, 0x00000000 }, + { 339, 0x00000000 }, + { 341, 0x00000000 } +}; + +struct ddr_reg ddr_1gb_phy_regs[] = { + { 1371, 0x0001F7C2 }, +}; + +/* 4 GB variant delta */ +struct ddr_reg ddr_4gb_ctl_regs[] = { + { 55, 0x0400DB60 }, + { 58, 0x0400DB60 }, + { 61, 0x0400DB60 }, + { 73, 0x00001860 }, + { 75, 0x00001860 }, + { 77, 0x00001860 }, + { 119, 0x00061800 }, + { 120, 0x00061800 }, + { 121, 0x00061800 }, + { 122, 0x00061800 }, + { 123, 0x00061800 }, + { 125, 0x0000AAA0 }, + { 126, 0x00061800 }, + { 127, 0x00061800 }, + { 128, 0x00061800 }, + { 129, 0x00061800 }, + { 130, 0x00061800 }, + { 132, 0x0000AAA0 }, + { 133, 0x00061800 }, + { 134, 0x00061800 }, + { 135, 0x00061800 }, + { 136, 0x00061800 }, + { 137, 0x00061800 }, + { 139, 0x0000AAA0 }, + { 206, 0x00000000 }, + { 209, 0x00000000 }, + { 212, 0x00000000 }, + { 215, 0x00000000 }, + { 218, 0x00000000 }, + { 221, 0x00000000 }, + { 230, 0x00000000 }, + { 231, 0x00000000 }, + { 232, 0x00000000 }, + { 233, 0x00000000 }, + { 234, 0x00000000 }, + { 235, 0x00000000 }, + { 316, 0x00000000 }, + { 318, 0x7FFF0000 }, + { 327, 0x01000C01 }, + { 328, 0x00000001 }, + { 385, 0x000030C0 }, + { 390, 0x0000DB60 }, + { 391, 0x0001E780 }, + { 394, 0x000030C0 }, + { 399, 0x0000DB60 }, + { 400, 0x0001E780 }, + { 403, 0x000030C0 }, + { 408, 0x0000DB60 }, + { 409, 0x0001E780 } +}; + +struct ddr_reg ddr_4gb_pi_regs[] = { + { 77, 0x04000000 }, + { 176, 0x00001860 }, + { 178, 0x00001860 }, + { 180, 0x04001860 }, + { 233, 0x0000C570 }, + { 238, 0x0000C570 }, + { 243, 0x0000C570 }, + { 247, 0x000030C0 }, + { 248, 0x0001E780 }, + { 249, 0x000030C0 }, + { 250, 0x0001E780 }, + { 251, 0x000030C0 }, + { 252, 0x0001E780 }, + { 299, 0x00000000 }, + { 301, 0x00000000 }, + { 307, 0x00000000 }, + { 309, 0x00000000 }, + { 315, 0x00000000 }, + { 317, 0x00000000 }, + { 323, 0x00000000 }, + { 325, 0x00000000 }, + { 331, 0x00000000 }, + { 333, 0x00000000 }, + { 339, 0x00000000 }, + { 341, 0x00000000 } +}; + +struct ddr_reg ddr_4gb_phy_regs[] = { + { 1371, 0x0001F7C2 }, +}; + +enum { + PHYCORE_1GB, + PHYCORE_4GB, +}; + +struct ddrss phycore_ddrss_data[] = { + [PHYCORE_1GB] = { + .ctl_regs = &ddr_1gb_ctl_regs[0], + .ctl_regs_num = ARRAY_SIZE(ddr_1gb_ctl_regs), + .pi_regs = &ddr_1gb_pi_regs[0], + .pi_regs_num = ARRAY_SIZE(ddr_1gb_pi_regs), + .phy_regs = &ddr_1gb_phy_regs[0], + .phy_regs_num = ARRAY_SIZE(ddr_1gb_phy_regs), + }, + [PHYCORE_4GB] = { + .ctl_regs = &ddr_4gb_ctl_regs[0], + .ctl_regs_num = ARRAY_SIZE(ddr_4gb_ctl_regs), + .pi_regs = &ddr_4gb_pi_regs[0], + .pi_regs_num = ARRAY_SIZE(ddr_4gb_pi_regs), + .phy_regs = &ddr_4gb_phy_regs[0], + .phy_regs_num = ARRAY_SIZE(ddr_4gb_phy_regs), + }, +}; + +#endif /* PHYCORE_DDR_DATA */ diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index fd36edc29dd..145887c0286 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_SOC_K3_AM625=y +CONFIG_PHYTEC_SOM_DETECTION=y CONFIG_TARGET_PHYCORE_AM62X_A53=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000 @@ -45,6 +46,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" +CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER_DOMAIN=y @@ -73,6 +75,8 @@ CONFIG_CLK_TI_SCI=y CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/phycore_am62x_r5_defconfig b/configs/phycore_am62x_r5_defconfig index 389672d5227..0062a4e3569 100644 --- a/configs/phycore_am62x_r5_defconfig +++ b/configs/phycore_am62x_r5_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_SOC_K3_AM625=y +CONFIG_PHYTEC_SOM_DETECTION=y CONFIG_TARGET_PHYCORE_AM62X_R5=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c3a7f0 @@ -50,6 +51,7 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y @@ -88,6 +90,7 @@ CONFIG_SPL_CLK_K3_PLL=y CONFIG_SPL_CLK_K3=y CONFIG_TI_SCI_PROTOCOL=y CONFIG_DA8XX_GPIO=y +CONFIG_DM_I2C=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_SPL_MISC=y @@ -129,3 +132,4 @@ CONFIG_SPL_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_LIB_RATIONAL=y CONFIG_SPL_LIB_RATIONAL=y +CONFIG_SYS_I2C_OMAP24XX=y From 38cf6819ca32d61f495c574a5695ee5e0cedc16d Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Wed, 22 May 2024 00:21:00 -0700 Subject: [PATCH 122/383] include: extension_board: Increase overlay file name size Upstream overlays like the ARM64 TI k3-am625-beagleplay-csi2-tevi-ov5640.dtso can easily have more then 32 characters. Increase the overlay length to 64 characters to apply overlays with longer names. Signed-off-by: Daniel Schultz Acked-by: Kory Maincent --- include/extension_board.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/extension_board.h b/include/extension_board.h index 87d404c0074..22e4104bc54 100644 --- a/include/extension_board.h +++ b/include/extension_board.h @@ -14,7 +14,7 @@ struct extension { char name[32]; char owner[32]; char version[32]; - char overlay[32]; + char overlay[64]; char other[32]; }; From 25a1fcee342a573232a965e98cf02e7fd2c3ab54 Mon Sep 17 00:00:00 2001 From: Aniket Limaye Date: Tue, 21 May 2024 11:18:42 +0530 Subject: [PATCH 123/383] arm: dts: k3-j7200: Move to OF_UPSTREAM Move to using OF_UPSTREAM config and thus using the devicetree-rebasing subtree. Signed-off-by: Aniket Limaye Acked-by: Sumit Garg --- arch/arm/dts/Makefile | 1 - arch/arm/dts/k3-j7200-binman.dtsi | 2 +- .../k3-j7200-common-proc-board-u-boot.dtsi | 14 +- arch/arm/dts/k3-j7200-common-proc-board.dts | 396 ----- arch/arm/dts/k3-j7200-main.dtsi | 1284 ----------------- arch/arm/dts/k3-j7200-mcu-wakeup.dtsi | 647 --------- arch/arm/dts/k3-j7200-som-p0.dtsi | 327 ----- arch/arm/dts/k3-j7200-thermal.dtsi | 47 - arch/arm/dts/k3-j7200.dtsi | 164 --- configs/j7200_evm_a72_defconfig | 3 +- 10 files changed, 8 insertions(+), 2877 deletions(-) delete mode 100644 arch/arm/dts/k3-j7200-common-proc-board.dts delete mode 100644 arch/arm/dts/k3-j7200-main.dtsi delete mode 100644 arch/arm/dts/k3-j7200-mcu-wakeup.dtsi delete mode 100644 arch/arm/dts/k3-j7200-som-p0.dtsi delete mode 100644 arch/arm/dts/k3-j7200-thermal.dtsi delete mode 100644 arch/arm/dts/k3-j7200.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ed1fe47b9f0..cef42ab53af 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1180,7 +1180,6 @@ dtb-$(CONFIG_SOC_K3_AM654) += \ k3-am654-icssg2.dtbo dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-r5-common-proc-board.dtb \ - k3-j7200-common-proc-board.dtb \ k3-j7200-r5-common-proc-board.dtb \ k3-j721e-r5-sk.dtb \ k3-j721e-beagleboneai64.dtb \ diff --git a/arch/arm/dts/k3-j7200-binman.dtsi b/arch/arm/dts/k3-j7200-binman.dtsi index e8020fec2dc..e79ba3b3775 100644 --- a/arch/arm/dts/k3-j7200-binman.dtsi +++ b/arch/arm/dts/k3-j7200-binman.dtsi @@ -273,7 +273,7 @@ #ifdef CONFIG_TARGET_J7200_A72_EVM -#define SPL_J7200_EVM_DTB "spl/dts/k3-j7200-common-proc-board.dtb" +#define SPL_J7200_EVM_DTB "spl/dts/ti/k3-j7200-common-proc-board.dtb" #define J7200_EVM_DTB "u-boot.dtb" &binman { diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index 485f17c5f06..045ef170e17 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -26,8 +26,12 @@ &cbass_mcu_wakeup { bootph-all; - chipid@43000014 { + wkup_conf: bus@43000000 { bootph-all; + + chipid: chipid@14 { + bootph-all; + }; }; }; @@ -40,14 +44,6 @@ }; &mcu_udmap { - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x284c0000 0x0 0x4000>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x284a0000 0x0 0x4000>, - <0x0 0x2aa00000 0x0 0x40000>, - <0x0 0x28400000 0x0 0x2000>; - reg-names = "gcfg", "rchan", "rchanrt", "tchan", - "tchanrt", "rflow"; bootph-all; }; diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts b/arch/arm/dts/k3-j7200-common-proc-board.dts deleted file mode 100644 index cee2b4b0eb8..00000000000 --- a/arch/arm/dts/k3-j7200-common-proc-board.dts +++ /dev/null @@ -1,396 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; - -#include "k3-j7200-som-p0.dtsi" -#include -#include -#include - -#include "k3-serdes.h" - -/ { - compatible = "ti,j7200-evm", "ti,j7200"; - model = "Texas Instruments J7200 EVM"; - - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - serial5 = &main_uart3; - mmc0 = &main_sdhci0; - mmc1 = &main_sdhci1; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - evm_12v0: fixedregulator-evm12v0 { - /* main supply */ - compatible = "regulator-fixed"; - regulator-name = "evm_12v0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_3v3: fixedregulator-vsys3v3 { - /* Output of LM5140 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_5v0: fixedregulator-vsys5v0 { - /* Output of LM5140 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_mmc1: fixedregulator-sd { - /* Output of TPS22918 */ - compatible = "regulator-fixed"; - regulator-name = "vdd_mmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - vin-supply = <&vsys_3v3>; - gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; - }; - - vdd_sd_dv: gpio-regulator-TLV71033 { - /* Output of TLV71033 */ - compatible = "regulator-gpio"; - regulator-name = "tlv71033"; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_sd_dv_pins_default>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - vin-supply = <&vsys_5v0>; - gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0>, - <3300000 0x1>; - }; -}; - -&wkup_pmx0 { - mcu_uart0_pins_default: mcu-uart0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ - J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ - J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */ - J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ - >; - }; - - wkup_uart0_pins_default: wkup-uart0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ - J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ - >; - }; -}; - -&wkup_pmx2 { - mcu_cpsw_pins_default: mcu-cpsw-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ - J721E_WKUP_IOPAD(0x0004, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ - J721E_WKUP_IOPAD(0x0008, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ - J721E_WKUP_IOPAD(0x000c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ - J721E_WKUP_IOPAD(0x0010, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ - J721E_WKUP_IOPAD(0x0014, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ - J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ - J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ - J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ - J721E_WKUP_IOPAD(0x002c, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ - J721E_WKUP_IOPAD(0x0018, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ - J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ - >; - }; - - wkup_gpio_pins_default: wkup-gpio-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */ - >; - }; - - mcu_mdio_pins_default: mcu-mdio1-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ - J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ - >; - }; -}; - -&main_pmx0 { - main_uart0_pins_default: main-uart0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */ - J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */ - J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */ - J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */ - >; - }; - - main_uart1_pins_default: main-uart1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0xb8, PIN_INPUT, 0) /* (T18) UART1_RXD */ - J721E_IOPAD(0xbc, PIN_INPUT, 0) /* (T20) UART1_TXD */ - >; - }; - - main_uart3_pins_default: main-uart3-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x60, PIN_INPUT, 11) /* (T15) MCAN8_TX.UART3_CTSn */ - J721E_IOPAD(0x30, PIN_INPUT, 11) /* (Y18) MCAN2_TX.UART3_RXD */ - >; - }; - - main_i2c1_pins_default: main-i2c1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */ - J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */ - >; - }; - - main_mmc1_pins_default: main-mmc1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */ - J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */ - J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ - J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */ - J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */ - J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */ - J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */ - J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */ - >; - }; - - vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ - >; - }; -}; - -&main_pmx1 { - main_usbss0_pins_default: main-usbss0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ - >; - }; -}; - -&wkup_uart0 { - /* Wakeup UART is used by System firmware */ - status = "reserved"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_uart0_pins_default>; -}; - -&mcu_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_uart0_pins_default>; - clock-frequency = <96000000>; -}; - -&main_uart0 { - status = "okay"; - /* Shared with ATF on this platform */ - power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart0_pins_default>; -}; - -&main_uart1 { - status = "okay"; - /* Default pinmux */ - pinctrl-names = "default"; - pinctrl-0 = <&main_uart1_pins_default>; -}; - -&main_uart2 { - /* MAIN UART 2 is used by R5F firmware */ - status = "reserved"; -}; - -&main_uart3 { - /* Shared with MCAN Interface */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart3_pins_default>; -}; - -&main_gpio0 { - status = "okay"; -}; - -&wkup_gpio0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_gpio_pins_default>; -}; - -&mcu_cpsw { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; -}; - -&davinci_mdio { - phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = ; - ti,fifo-depth = ; - }; -}; - -&cpsw_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&phy0>; -}; - -&main_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - exp1: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - exp2: gpio@22 { - compatible = "ti,tca6424"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -/* - * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be - * swapped on the CPB. - * - * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3. - * The i2c1 of the CPB (as it is labeled) is not connected to j7200. - */ -&main_i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_pins_default>; - clock-frequency = <400000>; - - exp3: gpio@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn", - "UB926_LOCK", "UB926_PWR_SW_CNTRL", - "UB926_TUNER_RESET", "UB926_GPIO_SPARE", ""; - }; -}; - -&main_sdhci0 { - /* eMMC */ - status = "okay"; - non-removable; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&main_sdhci1 { - /* SD card */ - status = "okay"; - pinctrl-0 = <&main_mmc1_pins_default>; - pinctrl-names = "default"; - vmmc-supply = <&vdd_mmc1>; - vqmmc-supply = <&vdd_sd_dv>; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&serdes_ln_ctrl { - idle-states = , , - , ; -}; - -&usb_serdes_mux { - idle-states = <1>; /* USB0 to SERDES lane 3 */ -}; - -&usbss0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_usbss0_pins_default>; - ti,vbus-divider; - ti,usb2-only; -}; - -&usb0 { - dr_mode = "otg"; - maximum-speed = "high-speed"; -}; - -&tscadc0 { - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&serdes_refclk { - clock-frequency = <100000000>; -}; - -&serdes0 { - serdes0_pcie_link: phy@0 { - reg = <0>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = ; - resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; - }; - - serdes0_qsgmii_link: phy@1 { - reg = <2>; - cdns,num-lanes = <1>; - #phy-cells = <0>; - cdns,phy-type = ; - resets = <&serdes_wiz0 3>; - }; -}; - -&pcie1_rc { - reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; -}; - -&pcie1_ep { - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; - status = "disabled"; -}; diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi deleted file mode 100644 index 264913f8328..00000000000 --- a/arch/arm/dts/k3-j7200-main.dtsi +++ /dev/null @@ -1,1284 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J7200 SoC Family Main Domain peripherals - * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/ { - serdes_refclk: serdes-refclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; -}; - -&cbass_main { - msmc_ram: sram@70000000 { - compatible = "mmio-sram"; - reg = <0x00 0x70000000 0x00 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00 0x00 0x70000000 0x100000>; - - atf-sram@0 { - reg = <0x00 0x20000>; - }; - }; - - scm_conf: scm-conf@100000 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00 0x00100000 0x00 0x1c000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00 0x00 0x00100000 0x1c000>; - - serdes_ln_ctrl: mux-controller@4080 { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ - <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ - }; - - cpsw0_phy_gmii_sel: phy@4044 { - compatible = "ti,j7200-cpsw5g-phy-gmii-sel"; - ti,qsgmii-main-ports = <1>; - reg = <0x4044 0x10>; - #phy-cells = <1>; - }; - - usb_serdes_mux: mux-controller@4000 { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ - }; - }; - - gic500: interrupt-controller@1800000 { - compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ - <0x00 0x01900000 0x00 0x100000>, /* GICR */ - <0x00 0x6f000000 0x00 0x2000>, /* GICC */ - <0x00 0x6f010000 0x00 0x1000>, /* GICH */ - <0x00 0x6f020000 0x00 0x2000>; /* GICV */ - - /* vcpumntirq: virtual CPU interface maintenance interrupt */ - interrupts = ; - - gic_its: msi-controller@1820000 { - compatible = "arm,gic-v3-its"; - reg = <0x00 0x01820000 0x00 0x10000>; - socionext,synquacer-pre-its = <0x1000000 0x400000>; - msi-controller; - #msi-cells = <1>; - }; - }; - - main_gpio_intr: interrupt-controller@a00000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x00a00000 0x00 0x800>; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <131>; - ti,interrupt-ranges = <8 392 56>; - }; - - main_navss: bus@30000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; - ti,sci-dev-id = <199>; - dma-coherent; - dma-ranges; - - main_navss_intr: interrupt-controller@310e0000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x310e0000 0x00 0x4000>; - ti,intr-trigger-type = <4>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <213>; - ti,interrupt-ranges = <0 64 64>, - <64 448 64>, - <128 672 64>; - }; - - main_udmass_inta: msi-controller@33d00000 { - compatible = "ti,sci-inta"; - reg = <0x00 0x33d00000 0x00 0x100000>; - interrupt-controller; - #interrupt-cells = <0>; - interrupt-parent = <&main_navss_intr>; - msi-controller; - ti,sci = <&dmsc>; - ti,sci-dev-id = <209>; - ti,interrupt-ranges = <0 0 256>; - }; - - secure_proxy_main: mailbox@32c00000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x00 0x32c00000 0x00 0x100000>, - <0x00 0x32400000 0x00 0x100000>, - <0x00 0x32800000 0x00 0x100000>; - interrupt-names = "rx_011"; - interrupts = ; - }; - - hwspinlock: spinlock@30e00000 { - compatible = "ti,am654-hwspinlock"; - reg = <0x00 0x30e00000 0x00 0x1000>; - #hwlock-cells = <1>; - }; - - mailbox0_cluster0: mailbox@31f80000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f80000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster1: mailbox@31f81000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f81000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster2: mailbox@31f82000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f82000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster3: mailbox@31f83000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f83000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster4: mailbox@31f84000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f84000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster5: mailbox@31f85000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f85000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster6: mailbox@31f86000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f86000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster7: mailbox@31f87000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f87000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster8: mailbox@31f88000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f88000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster9: mailbox@31f89000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f89000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster10: mailbox@31f8a000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f8a000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster11: mailbox@31f8b000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f8b000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - main_ringacc: ringacc@3c000000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x00 0x3c000000 0x00 0x400000>, - <0x00 0x38000000 0x00 0x400000>, - <0x00 0x31120000 0x00 0x100>, - <0x00 0x33000000 0x00 0x40000>, - <0x00 0x31080000 0x00 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; - ti,num-rings = <1024>; - ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ - ti,sci = <&dmsc>; - ti,sci-dev-id = <211>; - msi-parent = <&main_udmass_inta>; - }; - - main_udmap: dma-controller@31150000 { - compatible = "ti,j721e-navss-main-udmap"; - reg = <0x00 0x31150000 0x00 0x100>, - <0x00 0x34000000 0x00 0x100000>, - <0x00 0x35000000 0x00 0x100000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&main_udmass_inta>; - #dma-cells = <1>; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <212>; - ti,ringacc = <&main_ringacc>; - - ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ - <0x0f>, /* TX_HCHAN */ - <0x10>; /* TX_UHCHAN */ - ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ - <0x0b>, /* RX_HCHAN */ - <0x0c>; /* RX_UHCHAN */ - ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ - }; - - cpts@310d0000 { - compatible = "ti,j721e-cpts"; - reg = <0x00 0x310d0000 0x00 0x400>; - reg-names = "cpts"; - clocks = <&k3_clks 201 1>; - clock-names = "cpts"; - interrupts-extended = <&main_navss_intr 391>; - interrupt-names = "cpts"; - ti,cpts-periodic-outputs = <6>; - ti,cpts-ext-ts-inputs = <8>; - }; - }; - - cpsw0: ethernet@c000000 { - compatible = "ti,j7200-cpswxg-nuss"; - #address-cells = <2>; - #size-cells = <2>; - reg = <0x00 0xc000000 0x00 0x200000>; - reg-names = "cpsw_nuss"; - ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>; - clocks = <&k3_clks 19 33>; - clock-names = "fck"; - power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; - - dmas = <&main_udmap 0xca00>, - <&main_udmap 0xca01>, - <&main_udmap 0xca02>, - <&main_udmap 0xca03>, - <&main_udmap 0xca04>, - <&main_udmap 0xca05>, - <&main_udmap 0xca06>, - <&main_udmap 0xca07>, - <&main_udmap 0x4a00>; - dma-names = "tx0", "tx1", "tx2", "tx3", - "tx4", "tx5", "tx6", "tx7", - "rx"; - - status = "disabled"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - cpsw0_port1: port@1 { - reg = <1>; - ti,mac-only; - label = "port1"; - status = "disabled"; - }; - - cpsw0_port2: port@2 { - reg = <2>; - ti,mac-only; - label = "port2"; - status = "disabled"; - }; - - cpsw0_port3: port@3 { - reg = <3>; - ti,mac-only; - label = "port3"; - status = "disabled"; - }; - - cpsw0_port4: port@4 { - reg = <4>; - ti,mac-only; - label = "port4"; - status = "disabled"; - }; - }; - - cpsw5g_mdio: mdio@f00 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x00 0xf00 0x00 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 19 33>; - clock-names = "fck"; - bus_freq = <1000000>; - status = "disabled"; - }; - - cpts@3d000 { - compatible = "ti,j721e-cpts"; - reg = <0x00 0x3d000 0x00 0x400>; - clocks = <&k3_clks 19 16>; - clock-names = "cpts"; - interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cpts"; - ti,cpts-ext-ts-inputs = <4>; - ti,cpts-periodic-outputs = <2>; - }; - }; - - /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ - main_timerio_input: pinctrl@104200 { - compatible = "pinctrl-single"; - reg = <0x0 0x104200 0x0 0x50>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x000001ff>; - }; - - /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ - main_timerio_output: pinctrl@104280 { - compatible = "pinctrl-single"; - reg = <0x0 0x104280 0x0 0x20>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000001f>; - }; - - main_pmx0: pinctrl@11c000 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x11c000 0x00 0x10c>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - main_pmx1: pinctrl@11c11c { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x11c11c 0x00 0xc>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - main_uart0: serial@2800000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02800000 0x00 0x100>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 146 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart1: serial@2810000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02810000 0x00 0x100>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 278 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart2: serial@2820000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02820000 0x00 0x100>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 279 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart3: serial@2830000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02830000 0x00 0x100>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 280 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart4: serial@2840000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02840000 0x00 0x100>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 281 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart5: serial@2850000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02850000 0x00 0x100>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 282 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart6: serial@2860000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02860000 0x00 0x100>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 283 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart7: serial@2870000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02870000 0x00 0x100>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 284 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart8: serial@2880000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02880000 0x00 0x100>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 285 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart9: serial@2890000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02890000 0x00 0x100>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 286 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_i2c0: i2c@2000000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2000000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 187 1>; - power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; - status = "disabled"; - }; - - main_i2c1: i2c@2010000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2010000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 188 1>; - power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c2: i2c@2020000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2020000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 189 1>; - power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c3: i2c@2030000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2030000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 190 1>; - power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c4: i2c@2040000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2040000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 191 1>; - power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c5: i2c@2050000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2050000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 192 1>; - power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c6: i2c@2060000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2060000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 193 1>; - power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_sdhci0: mmc@4f80000 { - compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; - reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; - interrupts = ; - power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_ahb", "clk_xin"; - clocks = <&k3_clks 91 0>, <&k3_clks 91 3>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-mmc-hs = <0x0>; - ti,otap-del-sel-ddr52 = <0x6>; - ti,otap-del-sel-hs200 = <0x8>; - ti,otap-del-sel-hs400 = <0x5>; - ti,itap-del-sel-legacy = <0x10>; - ti,itap-del-sel-mmc-hs = <0xa>; - ti,strobe-sel = <0x77>; - ti,clkbuf-sel = <0x7>; - ti,trm-icp = <0x8>; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - dma-coherent; - status = "disabled"; - }; - - main_sdhci1: mmc@4fb0000 { - compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; - reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; - interrupts = ; - power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_ahb", "clk_xin"; - clocks = <&k3_clks 92 1>, <&k3_clks 92 2>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0xf>; - ti,otap-del-sel-sdr25 = <0xf>; - ti,otap-del-sel-sdr50 = <0xc>; - ti,otap-del-sel-sdr104 = <0x5>; - ti,otap-del-sel-ddr50 = <0xc>; - ti,itap-del-sel-legacy = <0x0>; - ti,itap-del-sel-sd-hs = <0x0>; - ti,itap-del-sel-sdr12 = <0x0>; - ti,itap-del-sel-sdr25 = <0x0>; - ti,clkbuf-sel = <0x7>; - ti,trm-icp = <0x8>; - dma-coherent; - status = "disabled"; - }; - - serdes_wiz0: wiz@5060000 { - compatible = "ti,j721e-wiz-10g"; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>; - clock-names = "fck", "core_ref_clk", "ext_ref_clk"; - num-lanes = <4>; - #reset-cells = <1>; - ranges = <0x5060000 0x0 0x5060000 0x10000>; - - assigned-clocks = <&k3_clks 292 85>; - assigned-clock-parents = <&k3_clks 292 89>; - - wiz0_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 292 85>, <&serdes_refclk>; - clock-output-names = "wiz0_pll0_refclk"; - #clock-cells = <0>; - assigned-clocks = <&wiz0_pll0_refclk>; - assigned-clock-parents = <&k3_clks 292 85>; - }; - - wiz0_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 292 85>, <&serdes_refclk>; - clock-output-names = "wiz0_pll1_refclk"; - #clock-cells = <0>; - assigned-clocks = <&wiz0_pll1_refclk>; - assigned-clock-parents = <&k3_clks 292 85>; - }; - - wiz0_refclk_dig: refclk-dig { - clocks = <&k3_clks 292 85>, <&serdes_refclk>; - clock-output-names = "wiz0_refclk_dig"; - #clock-cells = <0>; - assigned-clocks = <&wiz0_refclk_dig>; - assigned-clock-parents = <&k3_clks 292 85>; - }; - - wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { - clocks = <&wiz0_refclk_dig>; - #clock-cells = <0>; - }; - - serdes0: serdes@5060000 { - compatible = "ti,j721e-serdes-10g"; - reg = <0x05060000 0x00010000>; - reg-names = "torrent_phy"; - resets = <&serdes_wiz0 0>; - reset-names = "torrent_reset"; - clocks = <&wiz0_pll0_refclk>; - clock-names = "refclk"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - pcie1_rc: pcie@2910000 { - compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; - reg = <0x00 0x02910000 0x00 0x1000>, - <0x00 0x02917000 0x00 0x400>, - <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x00001000>; - reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - interrupt-names = "link_state"; - interrupts = ; - device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; - max-link-speed = <3>; - num-lanes = <4>; - power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 240 6>; - clock-names = "fck"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - cdns,no-bar-match-nbits = <64>; - vendor-id = <0x104c>; - device-id = <0xb00f>; - msi-map = <0x0 &gic_its 0x0 0x10000>; - dma-coherent; - ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, - <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; - dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - }; - - pcie1_ep: pcie-ep@2910000 { - compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; - reg = <0x00 0x02910000 0x00 0x1000>, - <0x00 0x02917000 0x00 0x400>, - <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = ; - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; - max-link-speed = <3>; - num-lanes = <4>; - power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 240 6>; - clock-names = "fck"; - max-functions = /bits/ 8 <6>; - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; - dma-coherent; - }; - - usbss0: cdns-usb@4104000 { - compatible = "ti,j721e-usb"; - reg = <0x00 0x4104000 0x00 0x100>; - dma-coherent; - power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; - clock-names = "ref", "lpm"; - assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ - assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ - #address-cells = <2>; - #size-cells = <2>; - ranges; - - usb0: usb@6000000 { - compatible = "cdns,usb3"; - reg = <0x00 0x6000000 0x00 0x10000>, - <0x00 0x6010000 0x00 0x10000>, - <0x00 0x6020000 0x00 0x10000>; - reg-names = "otg", "xhci", "dev"; - interrupts = , /* irq.0 */ - , /* irq.6 */ - ; /* otgirq.0 */ - interrupt-names = "host", - "peripheral", - "otg"; - maximum-speed = "super-speed"; - dr_mode = "otg"; - cdns,phyrst-a-enable; - }; - }; - - main_gpio0: gpio@600000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00600000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <145>, <146>, <147>, <148>, - <149>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <69>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 105 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio2: gpio@610000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00610000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <154>, <155>, <156>, <157>, - <158>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <69>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 107 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio4: gpio@620000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00620000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <163>, <164>, <165>, <166>, - <167>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <69>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 109 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio6: gpio@630000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00630000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <172>, <173>, <174>, <175>, - <176>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <69>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 111 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_spi0: spi@2100000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02100000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 266 1>; - status = "disabled"; - }; - - main_spi1: spi@2110000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02110000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 267 1>; - status = "disabled"; - }; - - main_spi2: spi@2120000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02120000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 268 1>; - status = "disabled"; - }; - - main_spi3: spi@2130000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02130000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 269 1>; - status = "disabled"; - }; - - main_spi4: spi@2140000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02140000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 270 1>; - status = "disabled"; - }; - - main_spi5: spi@2150000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02150000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 271 1>; - status = "disabled"; - }; - - main_spi6: spi@2160000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02160000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 272 1>; - status = "disabled"; - }; - - main_spi7: spi@2170000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02170000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 273 1>; - status = "disabled"; - }; - - watchdog0: watchdog@2200000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x0 0x2200000 0x0 0x100>; - clocks = <&k3_clks 252 1>; - power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 252 1>; - assigned-clock-parents = <&k3_clks 252 5>; - }; - - watchdog1: watchdog@2210000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x0 0x2210000 0x0 0x100>; - clocks = <&k3_clks 253 1>; - power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 253 1>; - assigned-clock-parents = <&k3_clks 253 5>; - }; - - main_timer0: timer@2400000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2400000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 49 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 49 1>; - assigned-clock-parents = <&k3_clks 49 2>; - power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer1: timer@2410000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2410000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 50 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>; - assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>; - power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer2: timer@2420000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2420000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 51 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 51 1>; - assigned-clock-parents = <&k3_clks 51 2>; - power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer3: timer@2430000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2430000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 52 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>; - assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>; - power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer4: timer@2440000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2440000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 53 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 53 1>; - assigned-clock-parents = <&k3_clks 53 2>; - power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer5: timer@2450000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2450000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 54 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>; - assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>; - power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer6: timer@2460000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2460000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 55 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 55 1>; - assigned-clock-parents = <&k3_clks 55 2>; - power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer7: timer@2470000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2470000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 57 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>; - assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>; - power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer8: timer@2480000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2480000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 58 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 58 1>; - assigned-clock-parents = <&k3_clks 58 2>; - power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer9: timer@2490000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2490000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 59 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>; - assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>; - power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer10: timer@24a0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24a0000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 60 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 60 1>; - assigned-clock-parents = <&k3_clks 60 2>; - power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer11: timer@24b0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24b0000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 62 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>; - assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>; - power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer12: timer@24c0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24c0000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 63 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 63 1>; - assigned-clock-parents = <&k3_clks 63 2>; - power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer13: timer@24d0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24d0000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 64 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>; - assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>; - power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer14: timer@24e0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24e0000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 65 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 65 1>; - assigned-clock-parents = <&k3_clks 65 2>; - power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer15: timer@24f0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24f0000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 66 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>; - assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>; - power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer16: timer@2500000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2500000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 67 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 67 1>; - assigned-clock-parents = <&k3_clks 67 2>; - power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer17: timer@2510000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2510000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 68 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>; - assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>; - power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer18: timer@2520000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2520000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 69 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 69 1>; - assigned-clock-parents = <&k3_clks 69 2>; - power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer19: timer@2530000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2530000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 70 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>; - assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>; - power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_r5fss0: r5fss@5c00000 { - compatible = "ti,j7200-r5fss"; - ti,cluster-mode = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5c00000 0x00 0x5c00000 0x20000>, - <0x5d00000 0x00 0x5d00000 0x20000>; - power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; - - main_r5fss0_core0: r5f@5c00000 { - compatible = "ti,j7200-r5f"; - reg = <0x5c00000 0x00010000>, - <0x5c10000 0x00010000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <245>; - ti,sci-proc-ids = <0x06 0xff>; - resets = <&k3_reset 245 1>; - firmware-name = "j7200-main-r5f0_0-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - - main_r5fss0_core1: r5f@5d00000 { - compatible = "ti,j7200-r5f"; - reg = <0x5d00000 0x00008000>, - <0x5d10000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <246>; - ti,sci-proc-ids = <0x07 0xff>; - resets = <&k3_reset 246 1>; - firmware-name = "j7200-main-r5f0_1-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - }; - - main_esm: esm@700000 { - compatible = "ti,j721e-esm"; - reg = <0x0 0x700000 0x0 0x1000>; - ti,esm-pins = <656>, <657>; - }; -}; diff --git a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi deleted file mode 100644 index 3fc588b848c..00000000000 --- a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi +++ /dev/null @@ -1,647 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals - * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&cbass_mcu_wakeup { - dmsc: system-controller@44083000 { - compatible = "ti,k2g-sci"; - ti,host-id = <12>; - - mbox-names = "rx", "tx"; - - mboxes = <&secure_proxy_main 11>, - <&secure_proxy_main 13>; - - reg-names = "debug_messages"; - reg = <0x00 0x44083000 0x00 0x1000>; - - k3_pds: power-controller { - compatible = "ti,sci-pm-domain"; - #power-domain-cells = <2>; - }; - - k3_clks: clock-controller { - compatible = "ti,k2g-sci-clk"; - #clock-cells = <2>; - }; - - k3_reset: reset-controller { - compatible = "ti,sci-reset"; - #reset-cells = <2>; - }; - }; - - mcu_timer0: timer@40400000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40400000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 35 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 35 1>; - assigned-clock-parents = <&k3_clks 35 2>; - power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_timer1: timer@40410000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40410000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 71 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>; - assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 308 1>; - power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_timer2: timer@40420000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40420000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 72 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 72 1>; - assigned-clock-parents = <&k3_clks 72 2>; - power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_timer3: timer@40430000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40430000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 73 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>; - assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 309 1>; - power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_timer4: timer@40440000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40440000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 74 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 74 1>; - assigned-clock-parents = <&k3_clks 74 2>; - power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_timer5: timer@40450000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40450000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 75 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>; - assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 310 1>; - power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_timer6: timer@40460000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40460000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 76 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 76 1>; - assigned-clock-parents = <&k3_clks 76 2>; - power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_timer7: timer@40470000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40470000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 77 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 77 1>, <&k3_clks 311 0>; - assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 311 1>; - power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_timer8: timer@40480000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40480000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 78 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 78 1>; - assigned-clock-parents = <&k3_clks 78 2>; - power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_timer9: timer@40490000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40490000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 79 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 79 1>, <&k3_clks 312 0>; - assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 312 1>; - power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_conf: syscon@40f00000 { - compatible = "syscon", "simple-mfd"; - reg = <0x00 0x40f00000 0x00 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00 0x00 0x40f00000 0x20000>; - - phy_gmii_sel: phy@4040 { - compatible = "ti,am654-phy-gmii-sel"; - reg = <0x4040 0x4>; - #phy-cells = <1>; - }; - }; - - chipid@43000014 { - compatible = "ti,am654-chipid"; - reg = <0x00 0x43000014 0x00 0x4>; - }; - - /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ - mcu_timerio_input: pinctrl@40f04200 { - compatible = "pinctrl-single"; - reg = <0x0 0x40f04200 0x0 0x28>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000F>; - status = "reserved"; - }; - - /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ - mcu_timerio_output: pinctrl@40f04280 { - compatible = "pinctrl-single"; - reg = <0x0 0x40f04280 0x0 0x28>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000F>; - status = "reserved"; - }; - - wkup_pmx0: pinctrl@4301c000 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c000 0x00 0x34>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - wkup_pmx1: pinctrl@4301c038 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c038 0x00 0x8>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - wkup_pmx2: pinctrl@4301c068 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c068 0x00 0xec>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - wkup_pmx3: pinctrl@4301c174 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c174 0x00 0x20>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - mcu_ram: sram@41c00000 { - compatible = "mmio-sram"; - reg = <0x00 0x41c00000 0x00 0x100000>; - ranges = <0x00 0x00 0x41c00000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - wkup_uart0: serial@42300000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x42300000 0x00 0x100>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 287 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - mcu_uart0: serial@40a00000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x40a00000 0x00 0x100>; - interrupts = ; - clock-frequency = <96000000>; - current-speed = <115200>; - power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 149 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - wkup_gpio_intr: interrupt-controller@42200000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x42200000 0x00 0x400>; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <137>; - ti,interrupt-ranges = <16 960 16>; - }; - - wkup_gpio0: gpio@42110000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x42110000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&wkup_gpio_intr>; - interrupts = <103>, <104>, <105>, <106>, <107>, <108>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <85>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 113 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - wkup_gpio1: gpio@42100000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x42100000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&wkup_gpio_intr>; - interrupts = <112>, <113>, <114>, <115>, <116>, <117>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <85>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 114 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - mcu_navss: bus@28380000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; - dma-coherent; - dma-ranges; - ti,sci-dev-id = <232>; - - mcu_ringacc: ringacc@2b800000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x00 0x2b800000 0x00 0x400000>, - <0x00 0x2b000000 0x00 0x400000>, - <0x00 0x28590000 0x00 0x100>, - <0x00 0x2a500000 0x00 0x40000>, - <0x00 0x28440000 0x00 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", - "proxy_target", "cfg"; - ti,num-rings = <286>; - ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ - ti,sci = <&dmsc>; - ti,sci-dev-id = <235>; - msi-parent = <&main_udmass_inta>; - }; - - mcu_udmap: dma-controller@285c0000 { - compatible = "ti,j721e-navss-mcu-udmap"; - reg = <0x00 0x285c0000 0x00 0x100>, - <0x00 0x2a800000 0x00 0x40000>, - <0x00 0x2aa00000 0x00 0x40000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&main_udmass_inta>; - #dma-cells = <1>; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <236>; - ti,ringacc = <&mcu_ringacc>; - - ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ - <0x0f>; /* TX_HCHAN */ - ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ - <0x0b>; /* RX_HCHAN */ - ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ - }; - }; - - secure_proxy_mcu: mailbox@2a480000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x0 0x2a480000 0x0 0x80000>, - <0x0 0x2a380000 0x0 0x80000>, - <0x0 0x2a400000 0x0 0x80000>; - /* - * Marked Disabled: - * Node is incomplete as it is meant for bootloaders and - * firmware on non-MPU processors - */ - status = "disabled"; - }; - - mcu_cpsw: ethernet@46000000 { - compatible = "ti,j721e-cpsw-nuss"; - #address-cells = <2>; - #size-cells = <2>; - reg = <0x00 0x46000000 0x00 0x200000>; - reg-names = "cpsw_nuss"; - ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>; - dma-coherent; - clocks = <&k3_clks 18 21>; - clock-names = "fck"; - power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; - - dmas = <&mcu_udmap 0xf000>, - <&mcu_udmap 0xf001>, - <&mcu_udmap 0xf002>, - <&mcu_udmap 0xf003>, - <&mcu_udmap 0xf004>, - <&mcu_udmap 0xf005>, - <&mcu_udmap 0xf006>, - <&mcu_udmap 0xf007>, - <&mcu_udmap 0x7000>; - dma-names = "tx0", "tx1", "tx2", "tx3", - "tx4", "tx5", "tx6", "tx7", - "rx"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - cpsw_port1: port@1 { - reg = <1>; - ti,mac-only; - label = "port1"; - ti,syscon-efuse = <&mcu_conf 0x200>; - phys = <&phy_gmii_sel 1>; - }; - }; - - davinci_mdio: mdio@f00 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x00 0xf00 0x00 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 18 21>; - clock-names = "fck"; - bus_freq = <1000000>; - }; - - cpts@3d000 { - compatible = "ti,am65-cpts"; - reg = <0x00 0x3d000 0x00 0x400>; - clocks = <&k3_clks 18 2>; - clock-names = "cpts"; - interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cpts"; - ti,cpts-ext-ts-inputs = <4>; - ti,cpts-periodic-outputs = <2>; - }; - }; - - mcu_i2c0: i2c@40b00000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x40b00000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 194 1>; - power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcu_i2c1: i2c@40b10000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x40b10000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 195 1>; - power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - wkup_i2c0: i2c@42120000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x42120000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 197 1>; - power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; - status = "disabled"; - }; - - mcu_spi0: spi@40300000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x040300000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 274 0>; - status = "disabled"; - }; - - mcu_spi1: spi@40310000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x040310000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 275 0>; - status = "disabled"; - }; - - mcu_spi2: spi@40320000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x040320000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 276 0>; - status = "disabled"; - }; - - fss: syscon@47000000 { - compatible = "syscon", "simple-mfd"; - reg = <0x00 0x47000000 0x00 0x100>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hbmc_mux: hbmc-mux { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x4 0x2>; /* HBMC select */ - }; - - hbmc: hyperbus@47034000 { - compatible = "ti,am654-hbmc"; - reg = <0x00 0x47034000 0x00 0x100>, - <0x05 0x00000000 0x01 0x0000000>; - power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 102 0>; - assigned-clocks = <&k3_clks 102 5>; - assigned-clock-rates = <333333333>; - #address-cells = <2>; - #size-cells = <1>; - mux-controls = <&hbmc_mux 0>; - }; - - ospi0: spi@47040000 { - compatible = "ti,am654-ospi", "cdns,qspi-nor"; - reg = <0x0 0x47040000 0x0 0x100>, - <0x5 0x00000000 0x1 0x0000000>; - interrupts = ; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x0>; - clocks = <&k3_clks 103 0>; - assigned-clocks = <&k3_clks 103 0>; - assigned-clock-parents = <&k3_clks 103 2>; - assigned-clock-rates = <166666666>; - power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - tscadc0: tscadc@40200000 { - compatible = "ti,am3359-tscadc"; - reg = <0x00 0x40200000 0x00 0x1000>; - interrupts = ; - power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 0 1>; - assigned-clocks = <&k3_clks 0 3>; - assigned-clock-rates = <60000000>; - clock-names = "fck"; - dmas = <&main_udmap 0x7400>, - <&main_udmap 0x7401>; - dma-names = "fifo0", "fifo1"; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am3359-adc"; - }; - }; - - mcu_r5fss0: r5fss@41000000 { - compatible = "ti,j7200-r5fss"; - ti,cluster-mode = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x41000000 0x00 0x41000000 0x20000>, - <0x41400000 0x00 0x41400000 0x20000>; - power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; - - mcu_r5fss0_core0: r5f@41000000 { - compatible = "ti,j7200-r5f"; - reg = <0x41000000 0x00010000>, - <0x41010000 0x00010000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <250>; - ti,sci-proc-ids = <0x01 0xff>; - resets = <&k3_reset 250 1>; - firmware-name = "j7200-mcu-r5f0_0-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - - mcu_r5fss0_core1: r5f@41400000 { - compatible = "ti,j7200-r5f"; - reg = <0x41400000 0x00008000>, - <0x41410000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <251>; - ti,sci-proc-ids = <0x02 0xff>; - resets = <&k3_reset 251 1>; - firmware-name = "j7200-mcu-r5f0_1-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - }; - - mcu_crypto: crypto@40900000 { - compatible = "ti,j721e-sa2ul"; - reg = <0x00 0x40900000 0x00 0x1200>; - power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; - dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>, - <&mcu_udmap 0x7503>; - dma-names = "tx", "rx1", "rx2"; - - rng: rng@40910000 { - compatible = "inside-secure,safexcel-eip76"; - reg = <0x00 0x40910000 0x00 0x7d>; - interrupts = ; - status = "disabled"; /* Used by OP-TEE */ - }; - }; - - wkup_vtm0: temperature-sensor@42040000 { - compatible = "ti,j7200-vtm"; - reg = <0x00 0x42040000 0x00 0x350>, - <0x00 0x42050000 0x00 0x350>; - power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; - #thermal-sensor-cells = <1>; - }; - - mcu_esm: esm@40800000 { - compatible = "ti,j721e-esm"; - reg = <0x00 0x40800000 0x00 0x1000>; - ti,esm-pins = <95>; - bootph-pre-ram; - }; -}; diff --git a/arch/arm/dts/k3-j7200-som-p0.dtsi b/arch/arm/dts/k3-j7200-som-p0.dtsi deleted file mode 100644 index 5a300d4c8ba..00000000000 --- a/arch/arm/dts/k3-j7200-som-p0.dtsi +++ /dev/null @@ -1,327 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; - -#include "k3-j7200.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - /* 4G RAM */ - reg = <0x00 0x80000000 0x00 0x80000000>, - <0x08 0x80000000 0x00 0x80000000>; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; - alignment = <0x1000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0100000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a4000000 { - reg = <0x00 0xa4000000 0x00 0x00800000>; - alignment = <0x1000>; - no-map; - }; - }; -}; - -&wkup_pmx0 { - mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ - J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ - J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */ - J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */ - J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */ - J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */ - J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */ - J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */ - J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */ - J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */ - J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */ - J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ - J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ - >; - }; - - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ - J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ - J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ - J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ - J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ - J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ - J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ - J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ - J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ - J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ - J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ - >; - }; -}; - -&wkup_pmx2 { - wkup_i2c0_pins_default: wkup-i2c0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */ - J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ - >; - }; -}; - -&main_pmx0 { - main_i2c0_pins_default: main-i2c0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ - J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ - >; - }; -}; - -&hbmc { - /* OSPI and HBMC are muxed inside FSS, Bootloader will enable - * appropriate node based on board detection - */ - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; - ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */ - <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */ - - flash@0,0 { - compatible = "cypress,hyperflash", "cfi-flash"; - reg = <0x00 0x00 0x4000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "hbmc.tiboot3"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "hbmc.tispl"; - reg = <0x100000 0x200000>; - }; - - partition@300000 { - label = "hbmc.u-boot"; - reg = <0x300000 0x400000>; - }; - - partition@700000 { - label = "hbmc.env"; - reg = <0x700000 0x40000>; - }; - - partition@800000 { - label = "hbmc.rootfs"; - reg = <0x800000 0x3800000>; - }; - }; - }; -}; - -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - exp_som: gpio@21 { - compatible = "ti,tca6408"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0", - "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1", - "UART/LIN_MUX_SEL", "TRC_D17/AUDIO_REFCLK_SEL", - "GPIO_LIN_EN", "CAN_STB"; - }; -}; - -&wkup_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <400000>; - - eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - }; -}; - -&ospi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <8>; - spi-rx-bus-width = <8>; - spi-max-frequency = <25000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "ospi.tiboot3"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "ospi.tispl"; - reg = <0x100000 0x200000>; - }; - - partition@300000 { - label = "ospi.u-boot"; - reg = <0x300000 0x400000>; - }; - - partition@700000 { - label = "ospi.env"; - reg = <0x700000 0x40000>; - }; - - partition@740000 { - label = "ospi.env.backup"; - reg = <0x740000 0x40000>; - }; - - partition@800000 { - label = "ospi.rootfs"; - reg = <0x800000 0x37c0000>; - }; - - partition@3fc0000 { - label = "ospi.phypattern"; - reg = <0x3fc0000 0x40000>; - }; - }; - }; -}; diff --git a/arch/arm/dts/k3-j7200-thermal.dtsi b/arch/arm/dts/k3-j7200-thermal.dtsi deleted file mode 100644 index e7e3a643a6f..00000000000 --- a/arch/arm/dts/k3-j7200-thermal.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include - -thermal_zones: thermal-zones { - mcu_thermal: mcu-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 0>; - - trips { - wkup_crit: wkup-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; - - mpu_thermal: mpu-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 1>; - - trips { - mpu_crit: mpu-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; - - main_thermal: main-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 2>; - - trips { - c7x_crit: c7x-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; -}; diff --git a/arch/arm/dts/k3-j7200.dtsi b/arch/arm/dts/k3-j7200.dtsi deleted file mode 100644 index ef73e6d7e85..00000000000 --- a/arch/arm/dts/k3-j7200.dtsi +++ /dev/null @@ -1,164 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J7200 SoC Family - * - * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include -#include -#include - -#include "k3-pinctrl.h" - -/ { - model = "Texas Instruments K3 J7200 SoC"; - compatible = "ti,j7200"; - interrupt-parent = <&gic500>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu-map { - cluster0: cluster0 { - core0 { - cpu = <&cpu0>; - }; - - core1 { - cpu = <&cpu1>; - }; - }; - - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a72"; - reg = <0x000>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a72"; - reg = <0x001>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_0>; - }; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - cache-unified; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - next-level-cache = <&msmc_l3>; - }; - - msmc_l3: l3-cache0 { - compatible = "cache"; - cache-level = <3>; - cache-unified; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - - psci: psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - }; - - a72_timer0: timer-cl0-cpu0 { - compatible = "arm,armv8-timer"; - interrupts = , /* cntpsirq */ - , /* cntpnsirq */ - , /* cntvirq */ - ; /* cnthpirq */ - }; - - pmu: pmu { - compatible = "arm,cortex-a72-pmu"; - interrupts = ; - }; - - cbass_main: bus@100000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ - <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ - <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ - <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ - <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ - <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ - <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ - <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */ - <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ - <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ - - /* MCUSS_WKUP Range */ - <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, - <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; - - cbass_mcu_wakeup: bus@28380000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ - <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */ - }; - }; - - #include "k3-j7200-thermal.dtsi" -}; - -/* Now include the peripherals for each bus segments */ -#include "k3-j7200-main.dtsi" -#include "k3-j7200-mcu-wakeup.dtsi" diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index fe8e84c9214..4db5654ca1c 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -15,7 +15,7 @@ CONFIG_SF_DEFAULT_MODE=0 CONFIG_ENV_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-common-proc-board" +CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j7200-common-proc-board" CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y @@ -96,6 +96,7 @@ CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y +CONFIG_OF_UPSTREAM=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_CCF=y From 4f836fb324ba500ecabdba4146c3ca9e1600cdf5 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Wed, 15 May 2024 15:20:08 +0300 Subject: [PATCH 124/383] memory: ti-gpmc: use printf to dump settings/timings pr_info() depends on CONFIG_LOGLEVEL > 6. If user has enabled CONFIG_TI_GPMC_DEBUG then we should print the GPMC settings/timings regardless of CONFIG_LOGLEVEL. So use printf() instead of pr_info(). Signed-off-by: Roger Quadros --- drivers/memory/ti-gpmc.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/memory/ti-gpmc.c b/drivers/memory/ti-gpmc.c index 8af48e199a7..e979c431e33 100644 --- a/drivers/memory/ti-gpmc.c +++ b/drivers/memory/ti-gpmc.c @@ -242,20 +242,20 @@ static int get_gpmc_timing_reg(/* timing specifiers */ if (l) time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1; time_ns = gpmc_clk_ticks_to_ns(l, cs, cd); - pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n", - name, time_ns, time_ns_min, time_ns, l, - invalid ? "; invalid " : " "); + printf("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n", + name, time_ns, time_ns_min, time_ns, l, + invalid ? "; invalid " : " "); } else { /* raw format */ - pr_info("gpmc,%s = <%u>;%s\n", name, l, - invalid ? " /* invalid */" : ""); + printf("gpmc,%s = <%u>;%s\n", name, l, + invalid ? " /* invalid */" : ""); } return l; } #define GPMC_PRINT_CONFIG(cs, config) \ - pr_info("CS%i %s: 0x%08x\n", cs, #config, \ + printf("CS%i %s: 0x%08x\n", cs, #config, \ gpmc_cs_read_reg(cs, config)) #define GPMC_GET_RAW(reg, st, end, field) \ get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0) @@ -274,7 +274,7 @@ static int get_gpmc_timing_reg(/* timing specifiers */ static void gpmc_show_regs(int cs, const char *desc) { - pr_info("gpmc cs%i %s:\n", cs, desc); + printf("gpmc cs%i %s:\n", cs, desc); GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1); GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2); GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3); @@ -291,7 +291,7 @@ static void gpmc_cs_show_timings(int cs, const char *desc) { gpmc_show_regs(cs, desc); - pr_info("gpmc cs%i access configuration:\n", cs); + printf("gpmc cs%i access configuration:\n", cs); GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity"); GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data"); GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1, @@ -318,7 +318,7 @@ static void gpmc_cs_show_timings(int cs, const char *desc) GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen"); GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen"); - pr_info("gpmc cs%i timings configuration:\n", cs); + printf("gpmc cs%i timings configuration:\n", cs); GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns"); GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns"); GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns"); @@ -409,9 +409,9 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max l = gpmc_cs_read_reg(cs, reg); if (IS_ENABLED(CONFIG_TI_GPMC_DEBUG)) { - pr_info("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", - cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000, - (l >> st_bit) & mask, time); + printf("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", + cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000, + (l >> st_bit) & mask, time); } l &= ~(mask << st_bit); @@ -618,8 +618,8 @@ static int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t, return -ENXIO; if (IS_ENABLED(CONFIG_TI_GPMC_DEBUG)) { - pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n", - cs, (div * gpmc_get_fclk_period()) / 1000, div); + printf("GPMC CS%d CLK period is %lu ns (div %d)\n", + cs, (div * gpmc_get_fclk_period()) / 1000, div); } gpmc_cs_bool_timings(cs, &t->bool_timings); From 2b6c4b66e5df5c82e5197191d32ac7b81e29abcb Mon Sep 17 00:00:00 2001 From: Maxim Moskalets Date: Wed, 15 May 2024 23:13:30 +0300 Subject: [PATCH 125/383] dm: use newly added linux/compat alloc functions Signed-off-by: Maxim Moskalets --- include/dm/devres.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/include/dm/devres.h b/include/dm/devres.h index 697534aa5be..27761deb6d1 100644 --- a/include/dm/devres.h +++ b/include/dm/devres.h @@ -266,17 +266,13 @@ static inline void *devm_kzalloc(struct udevice *dev, size_t size, gfp_t gfp) static inline void *devm_kmalloc_array(struct udevice *dev, size_t n, size_t size, gfp_t flags) { - /* TODO: add kmalloc_array() to linux/compat.h */ - if (size != 0 && n > SIZE_MAX / size) - return NULL; - return kmalloc(n * size, flags); + return kmalloc_array(n, size, flags); } static inline void *devm_kcalloc(struct udevice *dev, size_t n, size_t size, gfp_t flags) { - /* TODO: add kcalloc() to linux/compat.h */ - return kmalloc(n * size, flags | __GFP_ZERO); + return kcalloc(n, size, flags); } static inline void devm_kfree(struct udevice *dev, void *ptr) From 6068abe33fff28ba50a0f68eabc5d9eb31b7045d Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Wed, 15 May 2024 07:37:16 +0300 Subject: [PATCH 126/383] fs: relax ext4_write_file() dependency ext4_write_file() depends on CONFIG_EXT4_WRITE. Allow build without CONFIG_CMD_EXT4_WRITE. Signed-off-by: Baruch Siach --- fs/fs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/fs.c b/fs/fs.c index bed1f7242f4..0c47943f333 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -224,7 +224,7 @@ static struct fstype_info fstypes[] = { .exists = ext4fs_exists, .size = ext4fs_size, .read = ext4_read_file, -#ifdef CONFIG_CMD_EXT4_WRITE +#ifdef CONFIG_EXT4_WRITE .write = ext4_write_file, .ln = ext4fs_create_link, #else From 3078766134ae6d9c8746300b084a293105e35f60 Mon Sep 17 00:00:00 2001 From: Mattijs Korpershoek Date: Thu, 23 May 2024 11:27:09 +0200 Subject: [PATCH 127/383] image: Set load_end on partial loads When decompressing, it's possible that the algorithm only performs a partial decompression. This usually happens when CONFIG_SYS_BOOTM_LEN is too small for the uncompressed image. When that happens, image_decomp() returns an error and *load_end == load. The error is then handled by handle_decomp_error(). handle_decomp_error() expects the number of uncompressed bytes in uncomp_size but receives *load_end - load == load - load == 0. Because of this, handle_decomp_error does not report the expected "Image too large: increase CONFIG_SYS_BOOTM_LEN" error message. Modify the image_decomp() logic to always report the decompressed size, even when a partial decompression happened. Signed-off-by: Mattijs Korpershoek --- boot/image.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/boot/image.c b/boot/image.c index bacf5146e13..fc774d605d1 100644 --- a/boot/image.c +++ b/boot/image.c @@ -528,10 +528,10 @@ int image_decomp(int comp, ulong load, ulong image_start, int type, printf("Unimplemented compression type %d\n", comp); return ret; } - if (ret) - return ret; *load_end = load + image_len; + if (ret) + return ret; return 0; } From c1eb7a993d615410cdc902d5dcde32756f8fa8a5 Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Tue, 28 May 2024 09:18:27 +0300 Subject: [PATCH 128/383] arm: move _end to linker symbols commit 6e2228fb052b ("Merge patch series "Clean up arm linker scripts") was cleaning up linker scripts for armv7 and v8 but was leaving _end and __secure_stack_start/end. commit d0b5d9da5de2 ("arm: make _end compiler-generated") was moving _end to be compiler generated. _end is defined as c variable in its own section to force the compiler emit relative a reference. However, defining those in the linker script will do the same thing since [0]. So let's remove the special sections from the linker scripts, the variable definitions from sections.c and define them as a symbols. It's worth noting that _image_binary_end symbol is now redundant and can be removed in the future. - SPL The .end section has been removed from the new binary [ 5] .end PROGBITS 00000000fffdf488 000000000002f488 0 0000000000000000 0000000000000000 0 1 [0000000000000003]: WRITE, ALLOC $~ bloat-o-meter kria_old/spl/u-boot-spl krina_new/spl/u-boot-spl add/remove: 0/0 grow/shrink: 0/0 up/down: 0/0 (0) Function old new delta Total: Before=115980, After=115980, chg +0.00% $~ readelf -sW kria_old/u-boot kria_new/u-boot | grep -w _end 12047: 000000000813a0f0 0 OBJECT GLOBAL DEFAULT 11 _end 12047: 000000000813a118 0 NOTYPE GLOBAL DEFAULT 11 _end $~ readelf -sW kria_old/spl/u-boot-spl kria_new/spl/u-boot-spl | grep -w _end 1605: 00000000fffdf488 0 OBJECT GLOBAL DEFAULT 5 _end 1603: 00000000fffdf498 0 NOTYPE GLOBAL DEFAULT 4 _end $~ readelf -sW old/u-boot new/u-boot | grep -w _end 8847: 0000000000103710 0 OBJECT GLOBAL DEFAULT 11 _end 8847: 0000000000103738 0 NOTYPE GLOBAL DEFAULT 11 _end $~ readelf -sW old_v7/u-boot new_v7/u-boot | grep -w _end 10638: 000da824 0 OBJECT GLOBAL DEFAULT 10 _end 10637: 000da84c 0 NOTYPE GLOBAL DEFAULT 10 _end - For both QEMU instances $~ bloat-o-meter old/u-boot new/u-boot add/remove: 0/0 grow/shrink: 1/0 up/down: 20/0 (20) Function old new delta version_string 50 70 +20 Total: Before=656915, After=656935, chg +0.00% [0] binutils commit 6b3b0ab89663 ("Make linker assigned symbol dynamic only for shared object") Signed-off-by: Ilias Apalodimas --- arch/arm/cpu/arm1136/u-boot-spl.lds | 6 +----- arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds | 6 +----- arch/arm/cpu/armv8/u-boot-spl.lds | 7 +------ arch/arm/cpu/u-boot-spl.lds | 6 +----- arch/arm/cpu/u-boot.lds | 6 +----- arch/arm/lib/sections.c | 1 - arch/arm/mach-aspeed/ast2600/u-boot-spl.lds | 6 +----- arch/arm/mach-at91/arm926ejs/u-boot-spl.lds | 7 +------ arch/arm/mach-at91/armv7/u-boot-spl.lds | 7 +------ arch/arm/mach-omap2/u-boot-spl.lds | 7 +------ arch/arm/mach-rockchip/u-boot-tpl-v8.lds | 7 +------ arch/arm/mach-zynq/u-boot.lds | 6 +----- board/davinci/da8xxevm/u-boot-spl-da850evm.lds | 7 +------ board/samsung/common/exynos-uboot-spl.lds | 6 +----- 14 files changed, 13 insertions(+), 72 deletions(-) diff --git a/arch/arm/cpu/arm1136/u-boot-spl.lds b/arch/arm/cpu/arm1136/u-boot-spl.lds index f83988fd7e6..b7af29183a9 100644 --- a/arch/arm/cpu/arm1136/u-boot-spl.lds +++ b/arch/arm/cpu/arm1136/u-boot-spl.lds @@ -33,11 +33,7 @@ SECTIONS .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram . = ALIGN(4); __image_copy_end = .; - - .end : - { - *(.__end) - } + _end = .; .bss : { diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds index 7e20448f810..7c6309246f8 100644 --- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds @@ -49,11 +49,7 @@ SECTIONS __bss_end = .; } - .end : - { - *(.__end) - } - + _end = .; _image_binary_end = .; .dynsym _image_binary_end : { *(.dynsym) } diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds b/arch/arm/cpu/armv8/u-boot-spl.lds index ef8af67e11c..215cedd69a8 100644 --- a/arch/arm/cpu/armv8/u-boot-spl.lds +++ b/arch/arm/cpu/armv8/u-boot-spl.lds @@ -53,12 +53,7 @@ SECTIONS . = ALIGN(8); __image_copy_end = .; - - .end : { - . = ALIGN(8); - *(.__end) - } >.sram - + _end = .; _image_binary_end = .; .bss : { diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds index 9ed62395a9c..eee463a1b1c 100644 --- a/arch/arm/cpu/u-boot-spl.lds +++ b/arch/arm/cpu/u-boot-spl.lds @@ -53,12 +53,8 @@ SECTIONS __rel_dyn_end = .; } - .end : - { - *(.__end) - } - _image_binary_end = .; + _end = .; .bss __rel_dyn_start (OVERLAY) : { __bss_start = .; diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 707b19795f0..2f50087f57a 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -166,11 +166,7 @@ SECTIONS __rel_dyn_end = .; } - .end : - { - *(.__end) - } - + _end = .; _image_binary_end = .; /* diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c index db5463b2bbb..07efabaa7dc 100644 --- a/arch/arm/lib/sections.c +++ b/arch/arm/lib/sections.c @@ -23,4 +23,3 @@ char __secure_start[0] __section(".__secure_start"); char __secure_end[0] __section(".__secure_end"); char __secure_stack_start[0] __section(".__secure_stack_start"); char __secure_stack_end[0] __section(".__secure_stack_end"); -char _end[0] __section(".__end"); diff --git a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds index ada6570d971..9502a7384b5 100644 --- a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds +++ b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds @@ -61,11 +61,7 @@ SECTIONS __rel_dyn_end = .; } > .nor - .end : - { - *(.__end) - } > .nor - + _end = .; _image_binary_end = .; .bss : { diff --git a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds index 1a8bf94dee0..09cf838cf96 100644 --- a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds +++ b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds @@ -33,12 +33,7 @@ SECTIONS . = ALIGN(4); __image_copy_end = .; - - .end : - { - *(.__end) - } >.sram - + _end = .; _image_binary_end = .; .bss : diff --git a/arch/arm/mach-at91/armv7/u-boot-spl.lds b/arch/arm/mach-at91/armv7/u-boot-spl.lds index 6ca725fc4ce..460a91d93ec 100644 --- a/arch/arm/mach-at91/armv7/u-boot-spl.lds +++ b/arch/arm/mach-at91/armv7/u-boot-spl.lds @@ -40,12 +40,7 @@ SECTIONS . = ALIGN(4); __image_copy_end = .; - - .end : - { - *(.__end) - } >.sram - + _end = .; _image_binary_end = .; .bss : diff --git a/arch/arm/mach-omap2/u-boot-spl.lds b/arch/arm/mach-omap2/u-boot-spl.lds index 1d6e5d45b46..3bb759d8a1c 100644 --- a/arch/arm/mach-omap2/u-boot-spl.lds +++ b/arch/arm/mach-omap2/u-boot-spl.lds @@ -39,12 +39,7 @@ SECTIONS . = ALIGN(4); __image_copy_end = .; - - .end : - { - *(.__end) - } - + _end = .; _image_binary_end = .; .bss : diff --git a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds index ad32654085b..958a1b70aef 100644 --- a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds +++ b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds @@ -46,12 +46,7 @@ SECTIONS . = ALIGN(8); __image_copy_end = .; - - .end : { - . = ALIGN(8); - *(.__end) - } - + _end = .; _image_binary_end = .; .bss ALIGN(8) : { diff --git a/arch/arm/mach-zynq/u-boot.lds b/arch/arm/mach-zynq/u-boot.lds index 3e0c96c5055..f52523edf49 100644 --- a/arch/arm/mach-zynq/u-boot.lds +++ b/arch/arm/mach-zynq/u-boot.lds @@ -68,11 +68,7 @@ SECTIONS __rel_dyn_end = .; } - .end : - { - *(.__end) - } - + _end = .; _image_binary_end = .; /* diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds index 7e0f09f3b5b..56d6f4f114b 100644 --- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds +++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds @@ -46,12 +46,7 @@ SECTIONS } >.sram __image_copy_end = .; - - .end : - { - *(.__end) - } - + _end = .; _image_binary_end = .; .bss : diff --git a/board/samsung/common/exynos-uboot-spl.lds b/board/samsung/common/exynos-uboot-spl.lds index 73cd97a1b1d..9d3b57e98db 100644 --- a/board/samsung/common/exynos-uboot-spl.lds +++ b/board/samsung/common/exynos-uboot-spl.lds @@ -41,11 +41,7 @@ SECTIONS . = ALIGN(4); __image_copy_end = .; - - .end : - { - *(.__end) - } >.sram + _end = .; .bss : { From da3447d09fa045c6919370a0ac24693efe317901 Mon Sep 17 00:00:00 2001 From: Roman Stratiienko Date: Sun, 19 May 2024 13:09:51 +0000 Subject: [PATCH 129/383] android: Fix ramdisk loading for bootimage v3+ The boot_ramdisk and vendor_ramdisk must be both concatenated together. Without this change, Android root is missing some of the necessary tools to complete virtual AB OTA. Signed-off-by: Roman Stratiienko Reviewed-by: Mattijs Korpershoek --- boot/image-android.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/boot/image-android.c b/boot/image-android.c index ddd8ffd5e54..ee626972c11 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -63,7 +63,6 @@ static void android_boot_image_v3_v4_parse_hdr(const struct andr_boot_img_hdr_v3 data->kcmdline = hdr->cmdline; data->header_version = hdr->header_version; - data->ramdisk_ptr = env_get_ulong("ramdisk_addr_r", 16, 0); /* * The header takes a full page, the remaining components are aligned @@ -74,6 +73,7 @@ static void android_boot_image_v3_v4_parse_hdr(const struct andr_boot_img_hdr_v3 data->kernel_ptr = end; data->kernel_size = hdr->kernel_size; end += ALIGN(hdr->kernel_size, ANDR_GKI_PAGE_SIZE); + data->ramdisk_ptr = end; data->ramdisk_size = hdr->ramdisk_size; data->boot_ramdisk_size = hdr->ramdisk_size; end += ALIGN(hdr->ramdisk_size, ANDR_GKI_PAGE_SIZE); @@ -393,25 +393,24 @@ int android_image_get_ramdisk(const void *hdr, const void *vendor_boot_img, return -1; } if (img_data.header_version > 2) { - ramdisk_ptr = img_data.ramdisk_ptr; + ramdisk_ptr = img_data.ramdisk_addr; memcpy((void *)(ramdisk_ptr), (void *)img_data.vendor_ramdisk_ptr, img_data.vendor_ramdisk_size); - memcpy((void *)(ramdisk_ptr + img_data.vendor_ramdisk_size), - (void *)img_data.ramdisk_ptr, + ramdisk_ptr += img_data.vendor_ramdisk_size; + memcpy((void *)(ramdisk_ptr), (void *)img_data.ramdisk_ptr, img_data.boot_ramdisk_size); + ramdisk_ptr += img_data.boot_ramdisk_size; if (img_data.bootconfig_size) { memcpy((void *) - (ramdisk_ptr + img_data.vendor_ramdisk_size + - img_data.boot_ramdisk_size), - (void *)img_data.bootconfig_addr, + (ramdisk_ptr), (void *)img_data.bootconfig_addr, img_data.bootconfig_size); } } printf("RAM disk load addr 0x%08lx size %u KiB\n", - img_data.ramdisk_ptr, DIV_ROUND_UP(img_data.ramdisk_size, 1024)); + img_data.ramdisk_addr, DIV_ROUND_UP(img_data.ramdisk_size, 1024)); - *rd_data = img_data.ramdisk_ptr; + *rd_data = img_data.ramdisk_addr; *rd_len = img_data.ramdisk_size; return 0; From 17b1656dcd07136d83082b23118c20b2042d73e0 Mon Sep 17 00:00:00 2001 From: Roman Stratiienko Date: Thu, 23 May 2024 07:06:07 +0000 Subject: [PATCH 130/383] abootimg: Add init_boot image support Quote from [1]: "For devices launching with Android 13, the generic ramdisk is removed from the boot image and placed in a separate init_boot image. This change leaves the boot image with only the GKI kernel." While at it, update wrong error handling message when vendor_boot cannot be loaded. [1]: https://source.android.com/docs/core/architecture/partitions/generic-boot Signed-off-by: Roman Stratiienko Reviewed-by: Mattijs Korpershoek --- boot/image-board.c | 13 ++++++++++--- cmd/abootimg.c | 26 +++++++++++++++++++++----- include/image.h | 7 +++++++ 3 files changed, 38 insertions(+), 8 deletions(-) diff --git a/boot/image-board.c b/boot/image-board.c index b7884b8c5dc..f2124013046 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -406,13 +406,20 @@ static int select_ramdisk(struct bootm_headers *images, const char *select, u8 a if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE)) { int ret; if (IS_ENABLED(CONFIG_CMD_ABOOTIMG)) { - void *boot_img = map_sysmem(get_abootimg_addr(), 0); + ulong boot_img = get_abootimg_addr(); + ulong init_boot_img = get_ainit_bootimg_addr(); void *vendor_boot_img = map_sysmem(get_avendor_bootimg_addr(), 0); + void *ramdisk_img; - ret = android_image_get_ramdisk(boot_img, vendor_boot_img, + if (init_boot_img == -1) + ramdisk_img = map_sysmem(boot_img, 0); + else + ramdisk_img = map_sysmem(init_boot_img, 0); + + ret = android_image_get_ramdisk(ramdisk_img, vendor_boot_img, rd_datap, rd_lenp); unmap_sysmem(vendor_boot_img); - unmap_sysmem(boot_img); + unmap_sysmem(ramdisk_img); } else { void *ptr = map_sysmem(images->os.start, 0); diff --git a/cmd/abootimg.c b/cmd/abootimg.c index 88c77d99929..327712a536c 100644 --- a/cmd/abootimg.c +++ b/cmd/abootimg.c @@ -14,6 +14,7 @@ /* Please use abootimg_addr() macro to obtain the boot image address */ static ulong _abootimg_addr = -1; +static ulong _ainit_bootimg_addr = -1; static ulong _avendor_bootimg_addr = -1; ulong get_abootimg_addr(void) @@ -21,6 +22,11 @@ ulong get_abootimg_addr(void) return (_abootimg_addr == -1 ? image_load_addr : _abootimg_addr); } +ulong get_ainit_bootimg_addr(void) +{ + return _ainit_bootimg_addr; +} + ulong get_avendor_bootimg_addr(void) { return _avendor_bootimg_addr; @@ -179,7 +185,7 @@ static int do_abootimg_addr(struct cmd_tbl *cmdtp, int flag, int argc, char *endp; ulong img_addr; - if (argc < 2 || argc > 3) + if (argc < 2 || argc > 4) return CMD_RET_USAGE; img_addr = hextoul(argv[1], &endp); @@ -190,16 +196,26 @@ static int do_abootimg_addr(struct cmd_tbl *cmdtp, int flag, int argc, _abootimg_addr = img_addr; - if (argc == 3) { + if (argc > 2) { img_addr = simple_strtoul(argv[2], &endp, 16); if (*endp != '\0') { - printf("Error: Wrong vendor image address\n"); + printf("Error: Wrong vendor_boot image address\n"); return CMD_RET_FAILURE; } _avendor_bootimg_addr = img_addr; } + if (argc == 4) { + img_addr = simple_strtoul(argv[3], &endp, 16); + if (*endp != '\0') { + printf("Error: Wrong init_boot image address\n"); + return CMD_RET_FAILURE; + } + + _ainit_bootimg_addr = img_addr; + } + return CMD_RET_SUCCESS; } @@ -243,7 +259,7 @@ static int do_abootimg_dump(struct cmd_tbl *cmdtp, int flag, int argc, } static struct cmd_tbl cmd_abootimg_sub[] = { - U_BOOT_CMD_MKENT(addr, 3, 1, do_abootimg_addr, "", ""), + U_BOOT_CMD_MKENT(addr, 4, 1, do_abootimg_addr, "", ""), U_BOOT_CMD_MKENT(dump, 2, 1, do_abootimg_dump, "", ""), U_BOOT_CMD_MKENT(get, 5, 1, do_abootimg_get, "", ""), }; @@ -271,7 +287,7 @@ static int do_abootimg(struct cmd_tbl *cmdtp, int flag, int argc, U_BOOT_CMD( abootimg, CONFIG_SYS_MAXARGS, 0, do_abootimg, "manipulate Android Boot Image", - "addr []>\n" + "addr [ []]\n" " - set the address in RAM where boot image is located\n" " ($loadaddr is used by default)\n" "abootimg dump dtb\n" diff --git a/include/image.h b/include/image.h index acffd17e0df..c5b288f62b4 100644 --- a/include/image.h +++ b/include/image.h @@ -1970,6 +1970,13 @@ bool is_android_vendor_boot_image_header(const void *vendor_boot_img); */ ulong get_abootimg_addr(void); +/** + * get_ainit_bootimg_addr() - Get Android init boot image address + * + * Return: Android init boot image address + */ +ulong get_ainit_bootimg_addr(void); + /** * get_avendor_bootimg_addr() - Get Android vendor boot image address * From f9886bc60f42d5bcfcfa4e474af7dc230400b6be Mon Sep 17 00:00:00 2001 From: "Brunham, Kalen" Date: Fri, 17 May 2024 19:13:48 +0000 Subject: [PATCH 131/383] Added arm64 assembly for examples/api crt0 I've encountered a problem when compiling the 'examples/api' directory for ARM64 in U-boot. The problem lies in the assembly code in 'examples/api/crt0.S' where the current CONFIG_ARM code is only 32-bit. When targeting ARM64, a 64-bit version is necessary. I have proposed a fix by including a 'CONFIG_ARM64' section in the assembly code as shown below. These changes have been check via https://github.com/u-boot/u-boot/pull/538. Feedback is welcome. Signed-off-by: Kalen Brunham --- examples/api/crt0.S | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/examples/api/crt0.S b/examples/api/crt0.S index 57bba9d851d..06f6d1f9ad4 100644 --- a/examples/api/crt0.S +++ b/examples/api/crt0.S @@ -33,6 +33,21 @@ _start: str sp, [ip] b main +#elif defined(CONFIG_ARM64) + + .text + .globl _start +_start: + ldr ip0, =search_hint + str sp_el2, [ip0] + b main + + + .globl syscall +syscall: + ldr ip0, =syscall_ptr + ldr pc_el2, [ip0] + .globl syscall syscall: From bf03333d09669371ed2ee90a8ccddccc7d8aaa24 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Fri, 24 May 2024 14:54:26 +0200 Subject: [PATCH 132/383] efi_loader: allow concatenation with contained end node Allow appending a device-path to a device-path that contains an end node as separator. We need this feature for creating boot options specifying kernel, initrd, and dtb. Signed-off-by: Heinrich Schuchardt Reviewed-by: Ilias Apalodimas --- cmd/eficonfig.c | 6 +++--- cmd/efidebug.c | 4 ++-- include/efi_loader.h | 2 +- lib/efi_loader/efi_bootbin.c | 2 +- lib/efi_loader/efi_bootmgr.c | 2 +- lib/efi_loader/efi_boottime.c | 2 +- lib/efi_loader/efi_device_path.c | 20 +++++++++++++------- lib/efi_loader/efi_device_path_utilities.c | 2 +- 8 files changed, 23 insertions(+), 17 deletions(-) diff --git a/cmd/eficonfig.c b/cmd/eficonfig.c index 4164cb4f9b8..7bb92e510dc 100644 --- a/cmd/eficonfig.c +++ b/cmd/eficonfig.c @@ -530,7 +530,7 @@ struct efi_device_path *eficonfig_create_device_path(struct efi_device_path *dp_ dp = efi_dp_shorten(dp_volume); if (!dp) dp = dp_volume; - dp = efi_dp_concat(dp, &fp->dp, false); + dp = efi_dp_concat(dp, &fp->dp, 0); free(buf); return dp; @@ -1484,7 +1484,7 @@ static efi_status_t eficonfig_edit_boot_option(u16 *varname, struct eficonfig_bo goto out; } initrd_dp = efi_dp_concat((const struct efi_device_path *)&id_dp, - dp, false); + dp, 0); efi_free_pool(dp); } @@ -1495,7 +1495,7 @@ static efi_status_t eficonfig_edit_boot_option(u16 *varname, struct eficonfig_bo } final_dp_size = efi_dp_size(dp) + sizeof(END); if (initrd_dp) { - final_dp = efi_dp_concat(dp, initrd_dp, true); + final_dp = efi_dp_concat(dp, initrd_dp, 1); final_dp_size += efi_dp_size(initrd_dp) + sizeof(END); } else { final_dp = efi_dp_dup(dp); diff --git a/cmd/efidebug.c b/cmd/efidebug.c index e978e74aad9..186d62e7552 100644 --- a/cmd/efidebug.c +++ b/cmd/efidebug.c @@ -696,7 +696,7 @@ struct efi_device_path *create_initrd_dp(const char *dev, const char *part, short_fp = tmp_fp; initrd_dp = efi_dp_concat((const struct efi_device_path *)&id_dp, - short_fp, false); + short_fp, 0); out: efi_free_pool(tmp_dp); @@ -916,7 +916,7 @@ static int do_efi_boot_add(struct cmd_tbl *cmdtp, int flag, goto out; } - final_fp = efi_dp_concat(file_path, initrd_dp, true); + final_fp = efi_dp_concat(file_path, initrd_dp, 1); if (!final_fp) { printf("Cannot create final device path\n"); r = CMD_RET_FAILURE; diff --git a/include/efi_loader.h b/include/efi_loader.h index 9600941aa32..ddf2e41a95c 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -946,7 +946,7 @@ struct efi_device_path *efi_dp_from_lo(struct efi_load_option *lo, const efi_guid_t *guid); struct efi_device_path *efi_dp_concat(const struct efi_device_path *dp1, const struct efi_device_path *dp2, - bool split_end_node); + size_t split_end_node); struct efi_device_path *search_gpt_dp_node(struct efi_device_path *device_path); efi_status_t efi_deserialize_load_option(struct efi_load_option *lo, u8 *data, efi_uintn_t *size); diff --git a/lib/efi_loader/efi_bootbin.c b/lib/efi_loader/efi_bootbin.c index b7910f78fb6..a87006b3c0e 100644 --- a/lib/efi_loader/efi_bootbin.c +++ b/lib/efi_loader/efi_bootbin.c @@ -150,7 +150,7 @@ efi_status_t efi_run_image(void *source_buffer, efi_uintn_t source_size) msg_path = file_path; } else { file_path = efi_dp_concat(bootefi_device_path, - bootefi_image_path, false); + bootefi_image_path, 0); msg_path = bootefi_image_path; log_debug("Loaded from disk\n"); } diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c index 7da3139f917..b0bf21cf841 100644 --- a/lib/efi_loader/efi_bootmgr.c +++ b/lib/efi_loader/efi_bootmgr.c @@ -130,7 +130,7 @@ static efi_status_t try_load_from_file_path(efi_handle_t *fs_handles, if (!dp) continue; - dp = efi_dp_concat(dp, fp, false); + dp = efi_dp_concat(dp, fp, 0); if (!dp) continue; diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index 1951291747c..630c5f52c4f 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -1816,7 +1816,7 @@ efi_status_t efi_setup_loaded_image(struct efi_device_path *device_path, if (device_path) { info->device_handle = efi_dp_find_obj(device_path, NULL, NULL); - dp = efi_dp_concat(device_path, file_path, false); + dp = efi_dp_concat(device_path, file_path, 0); if (!dp) { ret = EFI_OUT_OF_RESOURCES; goto failure; diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c index aec224d8466..18be8a1b4f1 100644 --- a/lib/efi_loader/efi_device_path.c +++ b/lib/efi_loader/efi_device_path.c @@ -276,10 +276,11 @@ struct efi_device_path *efi_dp_dup(const struct efi_device_path *dp) * * @dp1: First device path * @dp2: Second device path - * @split_end_node: If true the two device paths will be concatenated and - * separated by an end node (DEVICE_PATH_SUB_TYPE_END). - * If false the second device path will be concatenated to the - * first one as-is. + * @split_end_node: + * * 0 to concatenate + * * 1 to concatenate with end node added as separator + * * size of dp1 excluding last end node to concatenate with end node as + * separator in case dp1 contains an end node * * Return: * concatenated device path or NULL. Caller must free the returned value @@ -287,7 +288,7 @@ struct efi_device_path *efi_dp_dup(const struct efi_device_path *dp) struct efi_device_path *efi_dp_concat(const struct efi_device_path *dp1, const struct efi_device_path *dp2, - bool split_end_node) + size_t split_end_node) { struct efi_device_path *ret; size_t end_size; @@ -301,10 +302,15 @@ efi_device_path *efi_dp_concat(const struct efi_device_path *dp1, ret = efi_dp_dup(dp1); } else { /* both dp1 and dp2 are non-null */ - unsigned sz1 = efi_dp_size(dp1); - unsigned sz2 = efi_dp_size(dp2); + size_t sz1; + size_t sz2 = efi_dp_size(dp2); void *p; + if (split_end_node < sizeof(struct efi_device_path)) + sz1 = efi_dp_size(dp1); + else + sz1 = split_end_node; + if (split_end_node) end_size = 2 * sizeof(END); else diff --git a/lib/efi_loader/efi_device_path_utilities.c b/lib/efi_loader/efi_device_path_utilities.c index c95dbfa9b5f..ac250bbfcc9 100644 --- a/lib/efi_loader/efi_device_path_utilities.c +++ b/lib/efi_loader/efi_device_path_utilities.c @@ -76,7 +76,7 @@ static struct efi_device_path * EFIAPI append_device_path( const struct efi_device_path *src2) { EFI_ENTRY("%pD, %pD", src1, src2); - return EFI_EXIT(efi_dp_concat(src1, src2, false)); + return EFI_EXIT(efi_dp_concat(src1, src2, 0)); } /* From 58bef195f94eae4ae90bd5409a81a204c0cbbca3 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Fri, 26 Apr 2024 16:13:11 +0200 Subject: [PATCH 133/383] cmd: eficonfig: add support for setting fdt We already support creating a load option where the device-path field contains the concatenation of the binary device-path and optionally the device path of the initrd which we expose via the EFI_LOAD_FILE2_PROTOCOL. Allow to append another device-path pointing to the device-tree identified by the device-tree GUID. Signed-off-by: Heinrich Schuchardt Reviewed-by: Ilias Apalodimas --- cmd/eficonfig.c | 79 ++++++++++++++++++++++++++++--------- include/efi_loader.h | 14 +++++++ lib/efi_loader/efi_helper.c | 44 +++++++++++++++++++++ 3 files changed, 119 insertions(+), 18 deletions(-) diff --git a/cmd/eficonfig.c b/cmd/eficonfig.c index 7bb92e510dc..6108b4243ac 100644 --- a/cmd/eficonfig.c +++ b/cmd/eficonfig.c @@ -61,6 +61,7 @@ struct eficonfig_filepath_info { struct eficonfig_boot_option { struct eficonfig_select_file_info file_info; struct eficonfig_select_file_info initrd_info; + struct eficonfig_select_file_info fdt_info; unsigned int boot_index; u16 *description; u16 *optional_data; @@ -1307,6 +1308,10 @@ static efi_status_t eficonfig_show_boot_option(struct eficonfig_boot_option *bo, if (ret != EFI_SUCCESS) goto out; + ret = prepare_file_selection_entry(efi_menu, "Fdt File: ", &bo->fdt_info); + if (ret != EFI_SUCCESS) + goto out; + ret = create_boot_option_entry(efi_menu, "Optional Data: ", bo->optional_data, eficonfig_boot_add_optional_data, bo); if (ret != EFI_SUCCESS) @@ -1387,27 +1392,44 @@ static efi_status_t eficonfig_edit_boot_option(u16 *varname, struct eficonfig_bo efi_status_t ret; char *tmp = NULL, *p; struct efi_load_option lo = {0}; - efi_uintn_t final_dp_size; + efi_uintn_t dp_size; struct efi_device_path *dp = NULL; efi_uintn_t size = load_option_size; - struct efi_device_path *final_dp = NULL; struct efi_device_path *device_dp = NULL; struct efi_device_path *initrd_dp = NULL; + struct efi_device_path *fdt_dp = NULL; struct efi_device_path *initrd_device_dp = NULL; + struct efi_device_path *fdt_device_dp = NULL; - const struct efi_initrd_dp id_dp = { + const struct efi_initrd_dp initrd_prefix = { .vendor = { { DEVICE_PATH_TYPE_MEDIA_DEVICE, DEVICE_PATH_SUB_TYPE_VENDOR_PATH, - sizeof(id_dp.vendor), + sizeof(initrd_prefix.vendor), }, EFI_INITRD_MEDIA_GUID, }, .end = { DEVICE_PATH_TYPE_END, DEVICE_PATH_SUB_TYPE_END, - sizeof(id_dp.end), + sizeof(initrd_prefix.end), + } + }; + + const struct efi_initrd_dp fdt_prefix = { + .vendor = { + { + DEVICE_PATH_TYPE_MEDIA_DEVICE, + DEVICE_PATH_SUB_TYPE_VENDOR_PATH, + sizeof(fdt_prefix.vendor), + }, + EFI_FDT_GUID, + }, + .end = { + DEVICE_PATH_TYPE_END, + DEVICE_PATH_SUB_TYPE_END, + sizeof(initrd_prefix.end), } }; @@ -1423,6 +1445,12 @@ static efi_status_t eficonfig_edit_boot_option(u16 *varname, struct eficonfig_bo goto out; } + bo->fdt_info.current_path = calloc(1, EFICONFIG_FILE_PATH_BUF_SIZE); + if (!bo->fdt_info.current_path) { + ret = EFI_OUT_OF_RESOURCES; + goto out; + } + bo->description = calloc(1, EFICONFIG_DESCRIPTION_MAX * sizeof(u16)); if (!bo->description) { ret = EFI_OUT_OF_RESOURCES; @@ -1455,13 +1483,20 @@ static efi_status_t eficonfig_edit_boot_option(u16 *varname, struct eficonfig_bo if (lo.file_path) fill_file_info(lo.file_path, &bo->file_info, device_dp); - /* Initrd file path(optional) is placed at second instance. */ + /* Initrd file path (optional) is placed at second instance. */ initrd_dp = efi_dp_from_lo(&lo, &efi_lf2_initrd_guid); if (initrd_dp) { fill_file_info(initrd_dp, &bo->initrd_info, initrd_device_dp); efi_free_pool(initrd_dp); } + /* Fdt file path (optional) is placed as third instance. */ + fdt_dp = efi_dp_from_lo(&lo, &efi_guid_fdt); + if (fdt_dp) { + fill_file_info(fdt_dp, &bo->fdt_info, fdt_device_dp); + efi_free_pool(fdt_dp); + } + if (size > 0) memcpy(bo->optional_data, lo.optional_data, size); } @@ -1483,26 +1518,31 @@ static efi_status_t eficonfig_edit_boot_option(u16 *varname, struct eficonfig_bo ret = EFI_OUT_OF_RESOURCES; goto out; } - initrd_dp = efi_dp_concat((const struct efi_device_path *)&id_dp, + initrd_dp = efi_dp_concat((const struct efi_device_path *)&initrd_prefix, dp, 0); efi_free_pool(dp); } + if (bo->fdt_info.dp_volume) { + dp = eficonfig_create_device_path(bo->fdt_info.dp_volume, + bo->fdt_info.current_path); + if (!dp) { + ret = EFI_OUT_OF_RESOURCES; + goto out; + } + fdt_dp = efi_dp_concat((const struct efi_device_path *)&fdt_prefix, + dp, 0); + efi_free_pool(dp); + } + dp = eficonfig_create_device_path(bo->file_info.dp_volume, bo->file_info.current_path); if (!dp) { ret = EFI_OUT_OF_RESOURCES; goto out; } - final_dp_size = efi_dp_size(dp) + sizeof(END); - if (initrd_dp) { - final_dp = efi_dp_concat(dp, initrd_dp, 1); - final_dp_size += efi_dp_size(initrd_dp) + sizeof(END); - } else { - final_dp = efi_dp_dup(dp); - } - efi_free_pool(dp); - if (!final_dp) + ret = efi_load_option_dp_join(&dp, &dp_size, initrd_dp, fdt_dp); + if (ret != EFI_SUCCESS) goto out; if (utf16_utf8_strlen(bo->optional_data)) { @@ -1514,17 +1554,20 @@ static efi_status_t eficonfig_edit_boot_option(u16 *varname, struct eficonfig_bo utf16_utf8_strncpy(&p, bo->optional_data, u16_strlen(bo->optional_data)); } - ret = eficonfig_set_boot_option(varname, final_dp, final_dp_size, bo->description, tmp); + ret = eficonfig_set_boot_option(varname, dp, dp_size, bo->description, tmp); out: free(tmp); free(bo->optional_data); free(bo->description); free(bo->file_info.current_path); free(bo->initrd_info.current_path); + free(bo->fdt_info.current_path); efi_free_pool(device_dp); efi_free_pool(initrd_device_dp); efi_free_pool(initrd_dp); - efi_free_pool(final_dp); + efi_free_pool(fdt_device_dp); + efi_free_pool(fdt_dp); + efi_free_pool(dp); return ret; } diff --git a/include/efi_loader.h b/include/efi_loader.h index ddf2e41a95c..1236eecff0f 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -1185,4 +1185,18 @@ efi_status_t efi_disk_get_device_name(const efi_handle_t handle, char *buf, int */ void efi_add_known_memory(void); +/** + * efi_load_option_dp_join() - join device-paths for load option + * + * @dp: in: binary device-path, out: joined device-path + * @dp_size: size of joined device-path + * @initrd_dp: initrd device-path or NULL + * @fdt_dp: device-tree device-path or NULL + * Return: status_code + */ +efi_status_t efi_load_option_dp_join(struct efi_device_path **dp, + size_t *dp_size, + struct efi_device_path *initrd_dp, + struct efi_device_path *fdt_dp); + #endif /* _EFI_LOADER_H */ diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c index 73d0279e843..348612c3dad 100644 --- a/lib/efi_loader/efi_helper.c +++ b/lib/efi_loader/efi_helper.c @@ -99,6 +99,50 @@ err: return NULL; } +/** + * efi_load_option_dp_join() - join device-paths for load option + * + * @dp: in: binary device-path, out: joined device-path + * @dp_size: size of joined device-path + * @initrd_dp: initrd device-path or NULL + * @fdt_dp: device-tree device-path or NULL + * Return: status_code + */ +efi_status_t efi_load_option_dp_join(struct efi_device_path **dp, + size_t *dp_size, + struct efi_device_path *initrd_dp, + struct efi_device_path *fdt_dp) +{ + if (!dp) + return EFI_INVALID_PARAMETER; + + *dp_size = efi_dp_size(*dp); + + if (initrd_dp) { + struct efi_device_path *tmp_dp = *dp; + + *dp = efi_dp_concat(tmp_dp, initrd_dp, *dp_size); + efi_free_pool(tmp_dp); + if (!*dp) + return EFI_OUT_OF_RESOURCES; + *dp_size += efi_dp_size(initrd_dp) + sizeof(END); + } + + if (fdt_dp) { + struct efi_device_path *tmp_dp = *dp; + + *dp = efi_dp_concat(tmp_dp, fdt_dp, *dp_size); + efi_free_pool(tmp_dp); + if (!dp) + return EFI_OUT_OF_RESOURCES; + *dp_size += efi_dp_size(fdt_dp) + sizeof(END); + } + + *dp_size += sizeof(END); + + return EFI_SUCCESS; +} + const struct guid_to_hash_map { efi_guid_t guid; const char algo[32]; From d9f7f4245122b9766ca1e0af3caa91fdd6a1a7b5 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Fri, 26 Apr 2024 16:13:12 +0200 Subject: [PATCH 134/383] cmd: efidebug: add support for setting fdt We already support creating a load option where the device-path field contains the concatenation of the binary device-path and optionally the device path of the initrd which we expose via the EFI_LOAD_FILE2_PROTOCOL. Allow to append another device-path pointing to the device-tree identified by the device-tree GUID. Signed-off-by: Heinrich Schuchardt Reviewed-by: Ilias Apalodimas --- cmd/efidebug.c | 129 +++++++++++++++++++++++++++++++++++-------------- 1 file changed, 92 insertions(+), 37 deletions(-) diff --git a/cmd/efidebug.c b/cmd/efidebug.c index 186d62e7552..083059106fd 100644 --- a/cmd/efidebug.c +++ b/cmd/efidebug.c @@ -653,38 +653,80 @@ static int do_efi_show_tables(struct cmd_tbl *cmdtp, int flag, } /** - * create_initrd_dp() - create a special device for our Boot### option + * enum efi_lo_dp_part - part of device path in load option + */ +enum efi_lo_dp_part { + /** @EFI_LO_DP_PART_BINARY: binary */ + EFI_LO_DP_PART_BINARY, + /** @EFI_LO_DP_PART_INITRD: initial RAM disk */ + EFI_LO_DP_PART_INITRD, + /** @EFI_LP_DP_PART_FDT: device-tree */ + EFI_LP_DP_PART_FDT, +}; + +/** + * create_lo_dp() - create a special device path for our Boot### option * * @dev: device * @part: disk partition * @file: filename * @shortform: create short form device path + * @type: part of device path to be created * Return: pointer to the device path or ERR_PTR */ static -struct efi_device_path *create_initrd_dp(const char *dev, const char *part, - const char *file, int shortform) +struct efi_device_path *create_lo_dp_part(const char *dev, const char *part, + const char *file, bool shortform, + enum efi_lo_dp_part type) { struct efi_device_path *tmp_dp = NULL, *tmp_fp = NULL, *short_fp = NULL; - struct efi_device_path *initrd_dp = NULL; + struct efi_device_path *dp = NULL; + const struct efi_device_path *dp_prefix; efi_status_t ret; - const struct efi_initrd_dp id_dp = { + const struct efi_initrd_dp fdt_dp = { .vendor = { { DEVICE_PATH_TYPE_MEDIA_DEVICE, DEVICE_PATH_SUB_TYPE_VENDOR_PATH, - sizeof(id_dp.vendor), + sizeof(fdt_dp.vendor), + }, + EFI_FDT_GUID, + }, + .end = { + DEVICE_PATH_TYPE_END, + DEVICE_PATH_SUB_TYPE_END, + sizeof(fdt_dp.end), + } + }; + const struct efi_initrd_dp initrd_dp = { + .vendor = { + { + DEVICE_PATH_TYPE_MEDIA_DEVICE, + DEVICE_PATH_SUB_TYPE_VENDOR_PATH, + sizeof(initrd_dp.vendor), }, EFI_INITRD_MEDIA_GUID, }, .end = { DEVICE_PATH_TYPE_END, DEVICE_PATH_SUB_TYPE_END, - sizeof(id_dp.end), + sizeof(initrd_dp.end), } }; + switch (type) { + case EFI_LO_DP_PART_INITRD: + dp_prefix = &initrd_dp.vendor.dp; + break; + case EFI_LP_DP_PART_FDT: + dp_prefix = &fdt_dp.vendor.dp; + break; + default: + dp_prefix = NULL; + break; + } + ret = efi_dp_from_name(dev, part, file, &tmp_dp, &tmp_fp); if (ret != EFI_SUCCESS) { printf("Cannot create device path for \"%s %s\"\n", part, file); @@ -695,13 +737,12 @@ struct efi_device_path *create_initrd_dp(const char *dev, const char *part, if (!short_fp) short_fp = tmp_fp; - initrd_dp = efi_dp_concat((const struct efi_device_path *)&id_dp, - short_fp, 0); + dp = efi_dp_concat(dp_prefix, short_fp, 0); out: efi_free_pool(tmp_dp); efi_free_pool(tmp_fp); - return initrd_dp; + return dp; } /** @@ -792,9 +833,8 @@ static int do_efi_boot_add(struct cmd_tbl *cmdtp, int flag, efi_guid_t guid; u16 *label; struct efi_device_path *file_path = NULL; - struct efi_device_path *fp_free = NULL; - struct efi_device_path *final_fp = NULL; struct efi_device_path *initrd_dp = NULL; + struct efi_device_path *fdt_dp = NULL; struct efi_load_option lo; void *data = NULL; efi_uintn_t size; @@ -842,22 +882,31 @@ static int do_efi_boot_add(struct cmd_tbl *cmdtp, int flag, lo.label = label; /* label will be changed below */ /* file path */ - ret = efi_dp_from_name(argv[3], argv[4], argv[5], - NULL, &fp_free); - if (ret != EFI_SUCCESS) { - printf("Cannot create device path for \"%s %s\"\n", - argv[3], argv[4]); + file_path = create_lo_dp_part(argv[3], argv[4], argv[5], + shortform, + EFI_LO_DP_PART_BINARY); + argc -= 5; + argv += 5; + break; + case 'd': + shortform = 1; + fallthrough; + case 'D': + if (argc < 3 || fdt_dp) { + r = CMD_RET_USAGE; + goto out; + } + + fdt_dp = create_lo_dp_part(argv[1], argv[2], argv[3], + shortform, + EFI_LP_DP_PART_FDT); + if (!fdt_dp) { + printf("Cannot add a device-tree\n"); r = CMD_RET_FAILURE; goto out; } - if (shortform) - file_path = efi_dp_shorten(fp_free); - if (!file_path) - file_path = fp_free; - fp_size += efi_dp_size(file_path) + - sizeof(struct efi_device_path); - argc -= 5; - argv += 5; + argc -= 3; + argv += 3; break; case 'i': shortform = 1; @@ -868,8 +917,9 @@ static int do_efi_boot_add(struct cmd_tbl *cmdtp, int flag, goto out; } - initrd_dp = create_initrd_dp(argv[1], argv[2], argv[3], - shortform); + initrd_dp = create_lo_dp_part(argv[1], argv[2], argv[3], + shortform, + EFI_LO_DP_PART_INITRD); if (!initrd_dp) { printf("Cannot add an initrd\n"); r = CMD_RET_FAILURE; @@ -877,8 +927,6 @@ static int do_efi_boot_add(struct cmd_tbl *cmdtp, int flag, } argc -= 3; argv += 3; - fp_size += efi_dp_size(initrd_dp) + - sizeof(struct efi_device_path); break; case 's': if (argc < 1 || lo.optional_data) { @@ -896,7 +944,6 @@ static int do_efi_boot_add(struct cmd_tbl *cmdtp, int flag, &file_path, &fp_size); if (r != CMD_RET_SUCCESS) goto out; - fp_free = file_path; argc -= 3; argv += 3; } else{ @@ -916,14 +963,14 @@ static int do_efi_boot_add(struct cmd_tbl *cmdtp, int flag, goto out; } - final_fp = efi_dp_concat(file_path, initrd_dp, 1); - if (!final_fp) { + ret = efi_load_option_dp_join(&file_path, &fp_size, initrd_dp, fdt_dp); + if (ret != EFI_SUCCESS) { printf("Cannot create final device path\n"); r = CMD_RET_FAILURE; goto out; } - lo.file_path = final_fp; + lo.file_path = file_path; lo.file_path_length = fp_size; size = efi_serialize_load_option(&lo, (u8 **)&data); @@ -944,9 +991,9 @@ static int do_efi_boot_add(struct cmd_tbl *cmdtp, int flag, out: free(data); - efi_free_pool(final_fp); efi_free_pool(initrd_dp); - efi_free_pool(fp_free); + efi_free_pool(fdt_dp); + efi_free_pool(file_path); free(lo.label); return r; @@ -1008,7 +1055,8 @@ static int do_efi_boot_rm(struct cmd_tbl *cmdtp, int flag, */ static void show_efi_boot_opt_data(u16 *varname16, void *data, size_t *size) { - struct efi_device_path *initrd_path = NULL; + struct efi_device_path *fdt_path; + struct efi_device_path *initrd_path; struct efi_load_option lo; efi_status_t ret; @@ -1037,6 +1085,12 @@ static void show_efi_boot_opt_data(u16 *varname16, void *data, size_t *size) efi_free_pool(initrd_path); } + fdt_path = efi_dp_from_lo(&lo, &efi_guid_fdt); + if (fdt_path) { + printf(" device-tree path: %pD\n", fdt_path); + efi_free_pool(fdt_path); + } + printf(" data:\n"); print_hex_dump(" ", DUMP_PREFIX_OFFSET, 16, 1, lo.optional_data, *size, true); @@ -1564,8 +1618,9 @@ U_BOOT_LONGHELP(efidebug, "\n" "efidebug boot add - set UEFI BootXXXX variable\n" " -b|-B