soc: xilinx: versal-net: Add soc_xilinx_versal_net driver

Add soc_xilinx_versal_net driver to identify the family & revision of
versal-net SoC. Add Kconfig option CONFIG_SOC_XILINX_VERSAL_NET to
enable/disable this driver. To enable this driver by default, add this
config to xilinx_versal_net_virt_defconfig file. This driver will be
probed using platdata U_BOOT_DEVICE structure which is specified in
mach-versal-net/cpu.c.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/613d6bcffd9070f62cf348079ed16c120f8fc56f.1668612993.git.michal.simek@amd.com

MAINTAINERS

@@ -664,6 +664,7 @@ M:	Michal Simek <michal.simek@amd.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
 F:	arch/arm/mach-versal-net/
+F:	drivers/soc/soc_xilinx_versal_net.c
 N:	(?<!uni)versal-net
 
 ARM VERSAL

arch/arm/mach-versal-net/cpu.c

@@ -15,6 +15,7 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/cache.h>
+#include <dm/platdata.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -87,3 +88,7 @@ u64 get_page_table_size(void)
 {
 	return 0x14000;
 }
+
+U_BOOT_DRVINFO(soc_xilinx_versal_net) = {
+	.name = "soc_xilinx_versal_net",
+};

configs/xilinx_versal_net_virt_defconfig

@@ -108,6 +108,8 @@ CONFIG_RESET_ZYNQMP=y
 CONFIG_ARM_DCC=y
 CONFIG_PL01X_SERIAL=y
 CONFIG_XILINX_UARTLITE=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_XILINX_VERSAL_NET=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_CADENCE_QSPI=y

drivers/soc/Kconfig

@@ -32,6 +32,14 @@ config SOC_XILINX_VERSAL
 	  This allows other drivers to verify the SoC familiy & revision using
 	  matching SoC attributes.
 
+config SOC_XILINX_VERSAL_NET
+	bool "Enable SoC Device ID driver for Xilinx Versal NET"
+	depends on SOC_DEVICE && ARCH_VERSAL_NET
+	help
+	  Enable this option to select SoC device id driver for Xilinx Versal NET.
+	  This allows other drivers to verify the SoC familiy & revision using
+	  matching SoC attributes.
+
 source "drivers/soc/ti/Kconfig"
 
 endmenu

drivers/soc/Makefile

@@ -8,3 +8,4 @@ obj-$(CONFIG_SOC_DEVICE_TI_K3) += soc_ti_k3.o
 obj-$(CONFIG_SANDBOX) += soc_sandbox.o
 obj-$(CONFIG_SOC_XILINX_ZYNQMP) += soc_xilinx_zynqmp.o
 obj-$(CONFIG_SOC_XILINX_VERSAL) += soc_xilinx_versal.o
+obj-$(CONFIG_SOC_XILINX_VERSAL_NET) += soc_xilinx_versal_net.o

drivers/soc/soc_xilinx_versal_net.c

@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal NET SOC driver
+ *
+ * Copyright (C) 2022, Advanced Micro Devices, Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <soc.h>
+#include <zynqmp_firmware.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+#include <linux/bitfield.h>
+
+/*
+ * v1 -> 0x10 - ES1
+ * v2 -> 0x20 - Production
+ */
+static const char versal_family[] = "Versal NET";
+
+struct soc_xilinx_versal_net_priv {
+	const char *family;
+	char revision;
+};
+
+static int soc_xilinx_versal_net_get_family(struct udevice *dev, char *buf, int size)
+{
+	struct soc_xilinx_versal_net_priv *priv = dev_get_priv(dev);
+
+	return snprintf(buf, size, "%s", priv->family);
+}
+
+static int soc_xilinx_versal_net_get_revision(struct udevice *dev, char *buf, int size)
+{
+	struct soc_xilinx_versal_net_priv *priv = dev_get_priv(dev);
+
+	return snprintf(buf, size, "v%d", priv->revision);
+}
+
+static const struct soc_ops soc_xilinx_versal_net_ops = {
+	.get_family = soc_xilinx_versal_net_get_family,
+	.get_revision = soc_xilinx_versal_net_get_revision,
+};
+
+static int soc_xilinx_versal_net_probe(struct udevice *dev)
+{
+	struct soc_xilinx_versal_net_priv *priv = dev_get_priv(dev);
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	int ret;
+
+	priv->family = versal_family;
+
+	if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) {
+		ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0,
+					ret_payload);
+		if (ret)
+			return ret;
+	} else {
+		ret_payload[2] = readl(PMC_TAP_VERSION);
+		if (!ret_payload[2])
+			return -EINVAL;
+	}
+
+	priv->revision = FIELD_GET(PS_VERSION_MASK, ret_payload[2]);
+
+	return 0;
+}
+
+U_BOOT_DRIVER(soc_xilinx_versal_net) = {
+	.name		= "soc_xilinx_versal_net",
+	.id		= UCLASS_SOC,
+	.ops		= &soc_xilinx_versal_net_ops,
+	.probe		= soc_xilinx_versal_net_probe,
+	.priv_auto	= sizeof(struct soc_xilinx_versal_net_priv),
+	.flags		= DM_FLAG_PRE_RELOC,
+};