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Merge patch series "Add AVS support for J721S2"

Browse source 
Manorit Chawdhry <m-chawdhry@ti.com> says:

This series adds support for Adaptive voltage scaling on J721S2 device [0].

[0]: https://www.ti.com/lit/pdf/spruj28 (Section 5.2.4.1 AVS Support)

AVS Test for J721S2: https://gist.github.com/manorit2001/b2fd9f6764a863294d4aa0755c83c84f
Boot Test results: https://gist.github.com/manorit2001/d44e035552cb19aadeb0d928d5cb5f26

Link: https://lore.kernel.org/r/20241015-b4-upstream-j721s2-avs-v5-0-5c8087387dc5@ti.com
This commit is contained in:
Tom Rini 2024-10-21 17:52:40 -06:00
commit 63a3dbb7b9
20 changed files with 97 additions and 15 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
arch/arm/dts/k3-am62-r5-lp-sk.dts
View file

@ -25,7 +25,8 @@
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;

3
arch/arm/dts/k3-am625-r5-beagleplay.dts
View file

@ -24,7 +24,8 @@
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1250000000>;

3
arch/arm/dts/k3-am625-r5-sk.dts
View file

@ -25,7 +25,8 @@
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;

3
arch/arm/dts/k3-am62a7-r5-sk.dts
View file

@ -23,7 +23,8 @@
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;

3
arch/arm/dts/k3-am62p5-r5-sk.dts
View file

@ -26,7 +26,8 @@
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;

3
arch/arm/dts/k3-am642-r5-evm.dts
View file

@ -22,7 +22,8 @@
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1000000000>;

3
arch/arm/dts/k3-am642-r5-sk.dts
View file

@ -22,7 +22,8 @@
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1000000000>;

3
arch/arm/dts/k3-am654-r5-base-board.dts
View file

@ -22,7 +22,8 @@
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
clocks = <&k3_clks 61 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 202 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 202 0>;
assigned-clock-rates = <800000000>;
ti,sci = <&dmsc>;

3
arch/arm/dts/k3-am69-r5-sk.dts
View file

@ -26,7 +26,8 @@
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
clocks = <&k3_clks 61 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 202 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 202 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <2000000000>;

3
arch/arm/dts/k3-j7200-r5-common-proc-board.dts
View file

@ -23,7 +23,8 @@
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
clocks = <&k3_clks 61 1>;
clocks = <&k3_clks 61 1>, <&k3_clks 202 2>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 323 0>;
assigned-clock-parents= <0>, <0>, <&k3_clks 323 2>;
assigned-clock-rates = <2000000000>, <200000000>;

3
arch/arm/dts/k3-j721e-r5.dtsi
View file

@ -20,7 +20,8 @@
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
clocks = <&k3_clks 61 1>;
clocks = <&k3_clks 61 1>, <&k3_clks 202 2>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
assigned-clock-rates = <2000000000>, <200000000>;
ti,sci = <&dmsc>;

9
arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
View file

@ -10,3 +10,12 @@
#include "k3-j721s2-ddr.dtsi"
#include "k3-j721s2-common-proc-board-u-boot.dtsi"
#include "k3-j721s2-r5.dtsi"
&tps659411 {
bootph-pre-ram;
};
&wkup_vtm0 {
bootph-pre-ram;
vdd-supply-2 = <&bucka1234>;
};

3
arch/arm/dts/k3-j721s2-r5.dtsi
View file

@ -20,7 +20,8 @@
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
clocks = <&k3_clks 61 1>;
clocks = <&k3_clks 61 1>, <&k3_clks 202 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>;
assigned-clock-parents = <&k3_clks 61 3>;
assigned-clock-rates = <200000000>, <2000000000>;

3
arch/arm/dts/k3-j722s-r5-evm.dts
View file

@ -25,7 +25,8 @@
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;

3
arch/arm/dts/k3-j784s4-r5-evm.dts
View file

@ -26,7 +26,8 @@
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
clocks = <&k3_clks 61 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 202 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 202 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <2000000000>;

10
arch/arm/mach-k3/j721s2/j721s2_init.c
View file

@ -315,6 +315,9 @@ void do_dt_magic(void)
#ifdef CONFIG_XPL_BUILD
void board_init_f(ulong dummy)
{
struct udevice *dev;
int ret;
k3_spl_init();
#if defined(CONFIG_SPL_OF_LIST) && defined(CONFIG_TI_I2C_BOARD_DETECT)
do_dt_magic();
@ -325,6 +328,13 @@ void board_init_f(ulong dummy)
setup_navss_nb();
setup_qos();
if (IS_ENABLED(CONFIG_CPU_V7R) && IS_ENABLED(CONFIG_K3_AVS0)) {
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
&dev);
if (ret)
printf("AVS init failed: %d\n", ret);
}
}
#endif

4
configs/am68_sk_r5_defconfig
View file

@ -5,6 +5,10 @@ CONFIG_ARCH_K3=y
CONFIG_SOC_K3_J721S2=y
CONFIG_TARGET_J721S2_R5_EVM=y
CONFIG_K3_AVS0=n
CONFIG_DM_REGULATOR_TPS65941=n
CONFIG_PMIC_TPS65941=n
CONFIG_DEFAULT_DEVICE_TREE="k3-am68-sk-r5-base-board"
CONFIG_SPL_OF_LIST="k3-am68-sk-r5-base-board"
CONFIG_OF_LIST="k3-am68-sk-r5-base-board"

6
configs/j721s2_evm_r5_defconfig
View file

@ -111,6 +111,7 @@ CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_FS_LOADER=y
CONFIG_SPL_FS_LOADER=y
CONFIG_K3_AVS0=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_MMC_SDHCI=y
@ -140,6 +141,11 @@ CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_POWER_DOMAIN=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_TPS65941=y
CONFIG_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_TPS65941=y
CONFIG_K3_SYSTEM_CONTROLLER=y
CONFIG_REMOTEPROC_TI_K3_ARM64=y
CONFIG_RESET_TI_SCI=y

40
drivers/misc/k3_avs.c
View file

@ -352,6 +352,9 @@ static int k3_avs_probe(struct udevice *dev)
struct k3_avs_privdata *priv;
struct vd_data *vd;
int ret;
ofnode node;
struct ofnode_phandle_args phandle_args;
int i = 0;
priv = dev_get_priv(dev);
priv->dev = dev;
@ -367,6 +370,32 @@ static int k3_avs_probe(struct udevice *dev)
return -ENODEV;
for (vd = priv->vd_config->vds; vd->id >= 0; vd++) {
/* Get the clock and dev id for Jacinto platforms */
if (vd->id == J721E_VDD_MPU) {
node = ofnode_by_compatible(ofnode_null(), "ti,am654-rproc");
if (!ofnode_valid(node))
return -ENODEV;
i = ofnode_stringlist_search(node, "clock-names", "core");
if (i < 0)
return -ENODEV;
ret = ofnode_parse_phandle_with_args(node, "clocks",
"#clock-cells",
0, i,
&phandle_args);
if (ret) {
printf("Couldn't get the clock node, ret = %d\n", ret);
return ret;
}
vd->dev_id = phandle_args.args[0];
vd->clk_id = phandle_args.args[1];
debug("%s: MPU dev_id: %d, clk_id: %d", __func__,
vd->dev_id, vd->clk_id);
}
if (!(readl(AM6_VTM_DEVINFO(vd->id)) &
AM6_VTM_AVS0_SUPPORTED)) {
dev_warn(dev, "AVS-class 0 not supported for VD%d\n",
@ -391,7 +420,10 @@ static int k3_avs_probe(struct udevice *dev)
if (vd->flags & VD_FLAG_INIT_DONE)
continue;
k3_avs_program_voltage(priv, vd, vd->opp);
ret = k3_avs_program_voltage(priv, vd, vd->opp);
if (ret)
dev_warn(dev, "Could not program AVS voltage for VD%d, vd->opp=%d, ret=%d\n",
vd->id, vd->opp, ret);
}
if (!device_is_compatible(priv->dev, "ti,am654-avs"))
@ -460,6 +492,12 @@ static struct vd_data j721e_vd_data[] = {
{
.id = J721E_VDD_MPU,
.opp = AM6_OPP_NOM,
/*
* XXX: DEPRECATION WARNING: Around 2 u-boot versions
*
* These values will be picked up from DT, kept for backward
* compatibility
*/
.dev_id = 202, /* J721E_DEV_A72SS0_CORE0 */
.clk_id = 2, /* ARM clock */
.opps = {

1
drivers/power/pmic/Kconfig
View file

@ -394,6 +394,7 @@ config SPL_PMIC_LP87565
config PMIC_TPS65941
bool "Enable driver for Texas Instruments TPS65941 PMIC"
depends on DM_PMIC
help
The TPS65941 is a PMIC containing a bunch of SMPS & LDOs.
This driver binds the pmic children.