diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 928511c62b2..bde2176ec7f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1337,6 +1337,8 @@ dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \ dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \ k3-am625-r5-sk.dtb \ + k3-am625-beagleplay.dtb \ + k3-am625-r5-beagleplay.dtb \ k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-r5.dtb diff --git a/arch/arm/dts/k3-am625-beagleplay-ddr4-1600MTs.dtsi b/arch/arm/dts/k3-am625-beagleplay-ddr4-1600MTs.dtsi new file mode 100644 index 00000000000..3d7a41c27d7 --- /dev/null +++ b/arch/arm/dts/k3-am625-beagleplay-ddr4-1600MTs.dtsi @@ -0,0 +1,2195 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * https://beagleboard.org/play + * + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation + * + * This file was generated with the + * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.06 + * Thu Feb 09 2023 11:57:18 GMT-0600 (Central Standard Time) + * DDR Part number: K4AAG165WA-BCWE K4A4G165WF-BCTD + * DDR Type: DDR4 + * Frequency = 800MHz (1600MTs) + * Density: 16Gb + * Number of Ranks: 1 + */ + +#define DDRSS_PLL_FHS_CNT 6 +#define DDRSS_PLL_FREQUENCY_1 400000000 +#define DDRSS_PLL_FREQUENCY_2 400000000 + +#define DDRSS_CTL_0_DATA 0x00000A00 +#define DDRSS_CTL_1_DATA 0x00000000 +#define DDRSS_CTL_2_DATA 0x00000000 +#define DDRSS_CTL_3_DATA 0x00000000 +#define DDRSS_CTL_4_DATA 0x00000000 +#define DDRSS_CTL_5_DATA 0x00000000 +#define DDRSS_CTL_6_DATA 0x00000000 +#define DDRSS_CTL_7_DATA 0x000890B8 +#define DDRSS_CTL_8_DATA 0x00000000 +#define DDRSS_CTL_9_DATA 0x00000000 +#define DDRSS_CTL_10_DATA 0x00000000 +#define DDRSS_CTL_11_DATA 0x000890B8 +#define DDRSS_CTL_12_DATA 0x00000000 +#define DDRSS_CTL_13_DATA 0x00000000 +#define DDRSS_CTL_14_DATA 0x00000000 +#define DDRSS_CTL_15_DATA 0x000890B8 +#define DDRSS_CTL_16_DATA 0x00000000 +#define DDRSS_CTL_17_DATA 0x00000000 +#define DDRSS_CTL_18_DATA 0x00000000 +#define DDRSS_CTL_19_DATA 0x01010100 +#define DDRSS_CTL_20_DATA 0x01000100 +#define DDRSS_CTL_21_DATA 0x01000110 +#define DDRSS_CTL_22_DATA 0x02010002 +#define DDRSS_CTL_23_DATA 0x00027100 +#define DDRSS_CTL_24_DATA 0x00061A80 +#define DDRSS_CTL_25_DATA 0x04000400 +#define DDRSS_CTL_26_DATA 0x00000400 +#define DDRSS_CTL_27_DATA 0x00000000 +#define DDRSS_CTL_28_DATA 0x00000000 +#define DDRSS_CTL_29_DATA 0x00000000 +#define DDRSS_CTL_30_DATA 0x00000000 +#define DDRSS_CTL_31_DATA 0x00000000 +#define DDRSS_CTL_32_DATA 0x00000000 +#define DDRSS_CTL_33_DATA 0x00000000 +#define DDRSS_CTL_34_DATA 0x00000000 +#define DDRSS_CTL_35_DATA 0x00000000 +#define DDRSS_CTL_36_DATA 0x00000000 +#define DDRSS_CTL_37_DATA 0x00000000 +#define DDRSS_CTL_38_DATA 0x0400091C +#define DDRSS_CTL_39_DATA 0x1C1C1C1C +#define DDRSS_CTL_40_DATA 0x0400091C +#define DDRSS_CTL_41_DATA 0x1C1C1C1C +#define DDRSS_CTL_42_DATA 0x0400091C +#define DDRSS_CTL_43_DATA 0x1C1C1C1C +#define DDRSS_CTL_44_DATA 0x05050404 +#define DDRSS_CTL_45_DATA 0x00002706 +#define DDRSS_CTL_46_DATA 0x0602001D +#define DDRSS_CTL_47_DATA 0x05001D0B +#define DDRSS_CTL_48_DATA 0x00270605 +#define DDRSS_CTL_49_DATA 0x0602001D +#define DDRSS_CTL_50_DATA 0x05001D0B +#define DDRSS_CTL_51_DATA 0x00270605 +#define DDRSS_CTL_52_DATA 0x0602001D +#define DDRSS_CTL_53_DATA 0x07001D0B +#define DDRSS_CTL_54_DATA 0x00180807 +#define DDRSS_CTL_55_DATA 0x0400DB60 +#define DDRSS_CTL_56_DATA 0x07070009 +#define DDRSS_CTL_57_DATA 0x00001808 +#define DDRSS_CTL_58_DATA 0x0400DB60 +#define DDRSS_CTL_59_DATA 0x07070009 +#define DDRSS_CTL_60_DATA 0x00001808 +#define DDRSS_CTL_61_DATA 0x0400DB60 +#define DDRSS_CTL_62_DATA 0x03000009 +#define DDRSS_CTL_63_DATA 0x0D0C0002 +#define DDRSS_CTL_64_DATA 0x0D0C0D0C +#define DDRSS_CTL_65_DATA 0x01010000 +#define DDRSS_CTL_66_DATA 0x03191919 +#define DDRSS_CTL_67_DATA 0x0B0B0B0B +#define DDRSS_CTL_68_DATA 0x00000B0B +#define DDRSS_CTL_69_DATA 0x00000101 +#define DDRSS_CTL_70_DATA 0x00000000 +#define DDRSS_CTL_71_DATA 0x01000000 +#define DDRSS_CTL_72_DATA 0x01180803 +#define DDRSS_CTL_73_DATA 0x00001860 +#define DDRSS_CTL_74_DATA 0x00000118 +#define DDRSS_CTL_75_DATA 0x00001860 +#define DDRSS_CTL_76_DATA 0x00000118 +#define DDRSS_CTL_77_DATA 0x00001860 +#define DDRSS_CTL_78_DATA 0x00000005 +#define DDRSS_CTL_79_DATA 0x00000000 +#define DDRSS_CTL_80_DATA 0x00000000 +#define DDRSS_CTL_81_DATA 0x00000000 +#define DDRSS_CTL_82_DATA 0x00000000 +#define DDRSS_CTL_83_DATA 0x00000000 +#define DDRSS_CTL_84_DATA 0x00000000 +#define DDRSS_CTL_85_DATA 0x00000000 +#define DDRSS_CTL_86_DATA 0x00000000 +#define DDRSS_CTL_87_DATA 0x00090009 +#define DDRSS_CTL_88_DATA 0x00000009 +#define DDRSS_CTL_89_DATA 0x00000000 +#define DDRSS_CTL_90_DATA 0x00000000 +#define DDRSS_CTL_91_DATA 0x00000000 +#define DDRSS_CTL_92_DATA 0x00000000 +#define DDRSS_CTL_93_DATA 0x00000000 +#define DDRSS_CTL_94_DATA 0x00010001 +#define DDRSS_CTL_95_DATA 0x00040001 +#define DDRSS_CTL_96_DATA 0x04000120 +#define DDRSS_CTL_97_DATA 0x04000120 +#define DDRSS_CTL_98_DATA 0x01200120 +#define DDRSS_CTL_99_DATA 0x01200120 +#define DDRSS_CTL_100_DATA 0x00000000 +#define DDRSS_CTL_101_DATA 0x00000000 +#define DDRSS_CTL_102_DATA 0x00000000 +#define DDRSS_CTL_103_DATA 0x00000000 +#define DDRSS_CTL_104_DATA 0x00000000 +#define DDRSS_CTL_105_DATA 0x00000000 +#define DDRSS_CTL_106_DATA 0x03010000 +#define DDRSS_CTL_107_DATA 0x00010000 +#define DDRSS_CTL_108_DATA 0x00000000 +#define DDRSS_CTL_109_DATA 0x01000000 +#define DDRSS_CTL_110_DATA 0x80104002 +#define DDRSS_CTL_111_DATA 0x00040003 +#define DDRSS_CTL_112_DATA 0x00040005 +#define DDRSS_CTL_113_DATA 0x00030000 +#define DDRSS_CTL_114_DATA 0x00050004 +#define DDRSS_CTL_115_DATA 0x00000004 +#define DDRSS_CTL_116_DATA 0x00040003 +#define DDRSS_CTL_117_DATA 0x00040005 +#define DDRSS_CTL_118_DATA 0x00000000 +#define DDRSS_CTL_119_DATA 0x00061800 +#define DDRSS_CTL_120_DATA 0x00061800 +#define DDRSS_CTL_121_DATA 0x00061800 +#define DDRSS_CTL_122_DATA 0x00061800 +#define DDRSS_CTL_123_DATA 0x00061800 +#define DDRSS_CTL_124_DATA 0x00000000 +#define DDRSS_CTL_125_DATA 0x0000AAA0 +#define DDRSS_CTL_126_DATA 0x00061800 +#define DDRSS_CTL_127_DATA 0x00061800 +#define DDRSS_CTL_128_DATA 0x00061800 +#define DDRSS_CTL_129_DATA 0x00061800 +#define DDRSS_CTL_130_DATA 0x00061800 +#define DDRSS_CTL_131_DATA 0x00000000 +#define DDRSS_CTL_132_DATA 0x0000AAA0 +#define DDRSS_CTL_133_DATA 0x00061800 +#define DDRSS_CTL_134_DATA 0x00061800 +#define DDRSS_CTL_135_DATA 0x00061800 +#define DDRSS_CTL_136_DATA 0x00061800 +#define DDRSS_CTL_137_DATA 0x00061800 +#define DDRSS_CTL_138_DATA 0x00000000 +#define DDRSS_CTL_139_DATA 0x0000AAA0 +#define DDRSS_CTL_140_DATA 0x00000000 +#define DDRSS_CTL_141_DATA 0x00000000 +#define DDRSS_CTL_142_DATA 0x00000000 +#define DDRSS_CTL_143_DATA 0x00000000 +#define DDRSS_CTL_144_DATA 0x00000000 +#define DDRSS_CTL_145_DATA 0x00000000 +#define DDRSS_CTL_146_DATA 0x00000000 +#define DDRSS_CTL_147_DATA 0x00000000 +#define DDRSS_CTL_148_DATA 0x00000000 +#define DDRSS_CTL_149_DATA 0x00000000 +#define DDRSS_CTL_150_DATA 0x00000000 +#define DDRSS_CTL_151_DATA 0x00000000 +#define DDRSS_CTL_152_DATA 0x00000000 +#define DDRSS_CTL_153_DATA 0x00000000 +#define DDRSS_CTL_154_DATA 0x00000000 +#define DDRSS_CTL_155_DATA 0x00000000 +#define DDRSS_CTL_156_DATA 0x080C0000 +#define DDRSS_CTL_157_DATA 0x080C080C +#define DDRSS_CTL_158_DATA 0x08000000 +#define DDRSS_CTL_159_DATA 0x00000808 +#define DDRSS_CTL_160_DATA 0x000E0000 +#define DDRSS_CTL_161_DATA 0x00080808 +#define DDRSS_CTL_162_DATA 0x0E000000 +#define DDRSS_CTL_163_DATA 0x08080800 +#define DDRSS_CTL_164_DATA 0x00000000 +#define DDRSS_CTL_165_DATA 0x0000080E +#define DDRSS_CTL_166_DATA 0x00040003 +#define DDRSS_CTL_167_DATA 0x00000007 +#define DDRSS_CTL_168_DATA 0x00000000 +#define DDRSS_CTL_169_DATA 0x00000000 +#define DDRSS_CTL_170_DATA 0x00000000 +#define DDRSS_CTL_171_DATA 0x00000000 +#define DDRSS_CTL_172_DATA 0x00000000 +#define DDRSS_CTL_173_DATA 0x00000000 +#define DDRSS_CTL_174_DATA 0x01000000 +#define DDRSS_CTL_175_DATA 0x00000000 +#define DDRSS_CTL_176_DATA 0x00001500 +#define DDRSS_CTL_177_DATA 0x0000100E +#define DDRSS_CTL_178_DATA 0x00000000 +#define DDRSS_CTL_179_DATA 0x00000000 +#define DDRSS_CTL_180_DATA 0x00000001 +#define DDRSS_CTL_181_DATA 0x00000002 +#define DDRSS_CTL_182_DATA 0x00000C00 +#define DDRSS_CTL_183_DATA 0x00001000 +#define DDRSS_CTL_184_DATA 0x00000C00 +#define DDRSS_CTL_185_DATA 0x00001000 +#define DDRSS_CTL_186_DATA 0x00000C00 +#define DDRSS_CTL_187_DATA 0x00001000 +#define DDRSS_CTL_188_DATA 0x00000000 +#define DDRSS_CTL_189_DATA 0x00000000 +#define DDRSS_CTL_190_DATA 0x00000000 +#define DDRSS_CTL_191_DATA 0x00000000 +#define DDRSS_CTL_192_DATA 0x00000000 +#define DDRSS_CTL_193_DATA 0x00000000 +#define DDRSS_CTL_194_DATA 0x00000000 +#define DDRSS_CTL_195_DATA 0x00000000 +#define DDRSS_CTL_196_DATA 0x00000000 +#define DDRSS_CTL_197_DATA 0x00000000 +#define DDRSS_CTL_198_DATA 0x00000000 +#define DDRSS_CTL_199_DATA 0x00000000 +#define DDRSS_CTL_200_DATA 0x00000000 +#define DDRSS_CTL_201_DATA 0x00000000 +#define DDRSS_CTL_202_DATA 0x00000000 +#define DDRSS_CTL_203_DATA 0x00000000 +#define DDRSS_CTL_204_DATA 0x00042400 +#define DDRSS_CTL_205_DATA 0x00000301 +#define DDRSS_CTL_206_DATA 0x00000000 +#define DDRSS_CTL_207_DATA 0x00000424 +#define DDRSS_CTL_208_DATA 0x00000301 +#define DDRSS_CTL_209_DATA 0x00000000 +#define DDRSS_CTL_210_DATA 0x00000424 +#define DDRSS_CTL_211_DATA 0x00000301 +#define DDRSS_CTL_212_DATA 0x00000000 +#define DDRSS_CTL_213_DATA 0x00000424 +#define DDRSS_CTL_214_DATA 0x00000301 +#define DDRSS_CTL_215_DATA 0x00000000 +#define DDRSS_CTL_216_DATA 0x00000424 +#define DDRSS_CTL_217_DATA 0x00000301 +#define DDRSS_CTL_218_DATA 0x00000000 +#define DDRSS_CTL_219_DATA 0x00000424 +#define DDRSS_CTL_220_DATA 0x00000301 +#define DDRSS_CTL_221_DATA 0x00000000 +#define DDRSS_CTL_222_DATA 0x00000000 +#define DDRSS_CTL_223_DATA 0x00000000 +#define DDRSS_CTL_224_DATA 0x00000000 +#define DDRSS_CTL_225_DATA 0x00000000 +#define DDRSS_CTL_226_DATA 0x00000000 +#define DDRSS_CTL_227_DATA 0x00000000 +#define DDRSS_CTL_228_DATA 0x00000000 +#define DDRSS_CTL_229_DATA 0x00000000 +#define DDRSS_CTL_230_DATA 0x00000000 +#define DDRSS_CTL_231_DATA 0x00000000 +#define DDRSS_CTL_232_DATA 0x00000000 +#define DDRSS_CTL_233_DATA 0x00000000 +#define DDRSS_CTL_234_DATA 0x00000000 +#define DDRSS_CTL_235_DATA 0x00000000 +#define DDRSS_CTL_236_DATA 0x00001401 +#define DDRSS_CTL_237_DATA 0x00001401 +#define DDRSS_CTL_238_DATA 0x00001401 +#define DDRSS_CTL_239_DATA 0x00001401 +#define DDRSS_CTL_240_DATA 0x00001401 +#define DDRSS_CTL_241_DATA 0x00001401 +#define DDRSS_CTL_242_DATA 0x00000493 +#define DDRSS_CTL_243_DATA 0x00000493 +#define DDRSS_CTL_244_DATA 0x00000493 +#define DDRSS_CTL_245_DATA 0x00000493 +#define DDRSS_CTL_246_DATA 0x00000493 +#define DDRSS_CTL_247_DATA 0x00000493 +#define DDRSS_CTL_248_DATA 0x00000000 +#define DDRSS_CTL_249_DATA 0x00000000 +#define DDRSS_CTL_250_DATA 0x00000000 +#define DDRSS_CTL_251_DATA 0x00000000 +#define DDRSS_CTL_252_DATA 0x00000000 +#define DDRSS_CTL_253_DATA 0x00000000 +#define DDRSS_CTL_254_DATA 0x00000000 +#define DDRSS_CTL_255_DATA 0x00000000 +#define DDRSS_CTL_256_DATA 0x00000000 +#define DDRSS_CTL_257_DATA 0x00000000 +#define DDRSS_CTL_258_DATA 0x00000000 +#define DDRSS_CTL_259_DATA 0x00000000 +#define DDRSS_CTL_260_DATA 0x00000000 +#define DDRSS_CTL_261_DATA 0x00000000 +#define DDRSS_CTL_262_DATA 0x00000000 +#define DDRSS_CTL_263_DATA 0x00000000 +#define DDRSS_CTL_264_DATA 0x00000000 +#define DDRSS_CTL_265_DATA 0x00000000 +#define DDRSS_CTL_266_DATA 0x00000000 +#define DDRSS_CTL_267_DATA 0x00000000 +#define DDRSS_CTL_268_DATA 0x00000000 +#define DDRSS_CTL_269_DATA 0x00000000 +#define DDRSS_CTL_270_DATA 0x00000000 +#define DDRSS_CTL_271_DATA 0x00000000 +#define DDRSS_CTL_272_DATA 0x00000000 +#define DDRSS_CTL_273_DATA 0x00000000 +#define DDRSS_CTL_274_DATA 0x00000000 +#define DDRSS_CTL_275_DATA 0x00000000 +#define DDRSS_CTL_276_DATA 0x00000000 +#define DDRSS_CTL_277_DATA 0x00010000 +#define DDRSS_CTL_278_DATA 0x00000000 +#define DDRSS_CTL_279_DATA 0x00000000 +#define DDRSS_CTL_280_DATA 0x00000000 +#define DDRSS_CTL_281_DATA 0x00000101 +#define DDRSS_CTL_282_DATA 0x00000000 +#define DDRSS_CTL_283_DATA 0x00000000 +#define DDRSS_CTL_284_DATA 0x00000000 +#define DDRSS_CTL_285_DATA 0x00000000 +#define DDRSS_CTL_286_DATA 0x00000000 +#define DDRSS_CTL_287_DATA 0x00000000 +#define DDRSS_CTL_288_DATA 0x00000000 +#define DDRSS_CTL_289_DATA 0x00000000 +#define DDRSS_CTL_290_DATA 0x0C181511 +#define DDRSS_CTL_291_DATA 0x00000304 +#define DDRSS_CTL_292_DATA 0x00000000 +#define DDRSS_CTL_293_DATA 0x00000000 +#define DDRSS_CTL_294_DATA 0x00000000 +#define DDRSS_CTL_295_DATA 0x00000000 +#define DDRSS_CTL_296_DATA 0x00000000 +#define DDRSS_CTL_297_DATA 0x00000000 +#define DDRSS_CTL_298_DATA 0x00000000 +#define DDRSS_CTL_299_DATA 0x00000000 +#define DDRSS_CTL_300_DATA 0x00000000 +#define DDRSS_CTL_301_DATA 0x00000000 +#define DDRSS_CTL_302_DATA 0x00000000 +#define DDRSS_CTL_303_DATA 0x00000000 +#define DDRSS_CTL_304_DATA 0x00000000 +#define DDRSS_CTL_305_DATA 0x00040000 +#define DDRSS_CTL_306_DATA 0x00800200 +#define DDRSS_CTL_307_DATA 0x00000000 +#define DDRSS_CTL_308_DATA 0x02000400 +#define DDRSS_CTL_309_DATA 0x00000080 +#define DDRSS_CTL_310_DATA 0x00040000 +#define DDRSS_CTL_311_DATA 0x00800200 +#define DDRSS_CTL_312_DATA 0x00000000 +#define DDRSS_CTL_313_DATA 0x00000000 +#define DDRSS_CTL_314_DATA 0x00000000 +#define DDRSS_CTL_315_DATA 0x00000100 +#define DDRSS_CTL_316_DATA 0x01010000 +#define DDRSS_CTL_317_DATA 0x00000000 +#define DDRSS_CTL_318_DATA 0x3FFF0000 +#define DDRSS_CTL_319_DATA 0x000FFF00 +#define DDRSS_CTL_320_DATA 0xFFFFFFFF +#define DDRSS_CTL_321_DATA 0x00FFFF00 +#define DDRSS_CTL_322_DATA 0x0A000000 +#define DDRSS_CTL_323_DATA 0x0001FFFF +#define DDRSS_CTL_324_DATA 0x01010101 +#define DDRSS_CTL_325_DATA 0x01010101 +#define DDRSS_CTL_326_DATA 0x00000118 +#define DDRSS_CTL_327_DATA 0x00000C01 +#define DDRSS_CTL_328_DATA 0x00000000 +#define DDRSS_CTL_329_DATA 0x00000000 +#define DDRSS_CTL_330_DATA 0x00000000 +#define DDRSS_CTL_331_DATA 0x01000000 +#define DDRSS_CTL_332_DATA 0x00000100 +#define DDRSS_CTL_333_DATA 0x00010000 +#define DDRSS_CTL_334_DATA 0x00000000 +#define DDRSS_CTL_335_DATA 0x00000000 +#define DDRSS_CTL_336_DATA 0x00000000 +#define DDRSS_CTL_337_DATA 0x00000000 +#define DDRSS_CTL_338_DATA 0x00000000 +#define DDRSS_CTL_339_DATA 0x00000000 +#define DDRSS_CTL_340_DATA 0x00000000 +#define DDRSS_CTL_341_DATA 0x00000000 +#define DDRSS_CTL_342_DATA 0x00000000 +#define DDRSS_CTL_343_DATA 0x00000000 +#define DDRSS_CTL_344_DATA 0x00000000 +#define DDRSS_CTL_345_DATA 0x00000000 +#define DDRSS_CTL_346_DATA 0x00000000 +#define DDRSS_CTL_347_DATA 0x00000000 +#define DDRSS_CTL_348_DATA 0x00000000 +#define DDRSS_CTL_349_DATA 0x00000000 +#define DDRSS_CTL_350_DATA 0x00000000 +#define DDRSS_CTL_351_DATA 0x00000000 +#define DDRSS_CTL_352_DATA 0x00000000 +#define DDRSS_CTL_353_DATA 0x00000000 +#define DDRSS_CTL_354_DATA 0x00000000 +#define DDRSS_CTL_355_DATA 0x00000000 +#define DDRSS_CTL_356_DATA 0x00000000 +#define DDRSS_CTL_357_DATA 0x00000000 +#define DDRSS_CTL_358_DATA 0x00000000 +#define DDRSS_CTL_359_DATA 0x00000000 +#define DDRSS_CTL_360_DATA 0x00000000 +#define DDRSS_CTL_361_DATA 0x00000000 +#define DDRSS_CTL_362_DATA 0x00000000 +#define DDRSS_CTL_363_DATA 0x00000000 +#define DDRSS_CTL_364_DATA 0x00000000 +#define DDRSS_CTL_365_DATA 0x00000000 +#define DDRSS_CTL_366_DATA 0x00000000 +#define DDRSS_CTL_367_DATA 0x00000000 +#define DDRSS_CTL_368_DATA 0x00000000 +#define DDRSS_CTL_369_DATA 0x00000000 +#define DDRSS_CTL_370_DATA 0x0C000000 +#define DDRSS_CTL_371_DATA 0x060C0606 +#define DDRSS_CTL_372_DATA 0x06060C06 +#define DDRSS_CTL_373_DATA 0x00010101 +#define DDRSS_CTL_374_DATA 0x02000000 +#define DDRSS_CTL_375_DATA 0x05020101 +#define DDRSS_CTL_376_DATA 0x00000505 +#define DDRSS_CTL_377_DATA 0x02020200 +#define DDRSS_CTL_378_DATA 0x02020202 +#define DDRSS_CTL_379_DATA 0x02020202 +#define DDRSS_CTL_380_DATA 0x02020202 +#define DDRSS_CTL_381_DATA 0x00000000 +#define DDRSS_CTL_382_DATA 0x00000000 +#define DDRSS_CTL_383_DATA 0x04000100 +#define DDRSS_CTL_384_DATA 0x1E000004 +#define DDRSS_CTL_385_DATA 0x000030C0 +#define DDRSS_CTL_386_DATA 0x00000200 +#define DDRSS_CTL_387_DATA 0x00000200 +#define DDRSS_CTL_388_DATA 0x00000200 +#define DDRSS_CTL_389_DATA 0x00000200 +#define DDRSS_CTL_390_DATA 0x0000DB60 +#define DDRSS_CTL_391_DATA 0x0001E780 +#define DDRSS_CTL_392_DATA 0x0C0D0302 +#define DDRSS_CTL_393_DATA 0x001E090A +#define DDRSS_CTL_394_DATA 0x000030C0 +#define DDRSS_CTL_395_DATA 0x00000200 +#define DDRSS_CTL_396_DATA 0x00000200 +#define DDRSS_CTL_397_DATA 0x00000200 +#define DDRSS_CTL_398_DATA 0x00000200 +#define DDRSS_CTL_399_DATA 0x0000DB60 +#define DDRSS_CTL_400_DATA 0x0001E780 +#define DDRSS_CTL_401_DATA 0x0C0D0302 +#define DDRSS_CTL_402_DATA 0x001E090A +#define DDRSS_CTL_403_DATA 0x000030C0 +#define DDRSS_CTL_404_DATA 0x00000200 +#define DDRSS_CTL_405_DATA 0x00000200 +#define DDRSS_CTL_406_DATA 0x00000200 +#define DDRSS_CTL_407_DATA 0x00000200 +#define DDRSS_CTL_408_DATA 0x0000DB60 +#define DDRSS_CTL_409_DATA 0x0001E780 +#define DDRSS_CTL_410_DATA 0x0C0D0302 +#define DDRSS_CTL_411_DATA 0x0000090A +#define DDRSS_CTL_412_DATA 0x00000000 +#define DDRSS_CTL_413_DATA 0x0302000A +#define DDRSS_CTL_414_DATA 0x01000500 +#define DDRSS_CTL_415_DATA 0x01010001 +#define DDRSS_CTL_416_DATA 0x00010001 +#define DDRSS_CTL_417_DATA 0x01010001 +#define DDRSS_CTL_418_DATA 0x02010000 +#define DDRSS_CTL_419_DATA 0x00000200 +#define DDRSS_CTL_420_DATA 0x02000201 +#define DDRSS_CTL_421_DATA 0x00000000 +#define DDRSS_CTL_422_DATA 0x00202020 +#define DDRSS_PI_0_DATA 0x00000A00 +#define DDRSS_PI_1_DATA 0x00000000 +#define DDRSS_PI_2_DATA 0x00000000 +#define DDRSS_PI_3_DATA 0x01000000 +#define DDRSS_PI_4_DATA 0x00000001 +#define DDRSS_PI_5_DATA 0x00010064 +#define DDRSS_PI_6_DATA 0x00000000 +#define DDRSS_PI_7_DATA 0x00000000 +#define DDRSS_PI_8_DATA 0x00000000 +#define DDRSS_PI_9_DATA 0x00000000 +#define DDRSS_PI_10_DATA 0x00000000 +#define DDRSS_PI_11_DATA 0x00000000 +#define DDRSS_PI_12_DATA 0x00000000 +#define DDRSS_PI_13_DATA 0x00010001 +#define DDRSS_PI_14_DATA 0x00000000 +#define DDRSS_PI_15_DATA 0x00010001 +#define DDRSS_PI_16_DATA 0x00000005 +#define DDRSS_PI_17_DATA 0x00000000 +#define DDRSS_PI_18_DATA 0x00000000 +#define DDRSS_PI_19_DATA 0x00000000 +#define DDRSS_PI_20_DATA 0x00000000 +#define DDRSS_PI_21_DATA 0x00000000 +#define DDRSS_PI_22_DATA 0x00000000 +#define DDRSS_PI_23_DATA 0x00000000 +#define DDRSS_PI_24_DATA 0x280D0001 +#define DDRSS_PI_25_DATA 0x00000000 +#define DDRSS_PI_26_DATA 0x00010000 +#define DDRSS_PI_27_DATA 0x00003200 +#define DDRSS_PI_28_DATA 0x00000000 +#define DDRSS_PI_29_DATA 0x00000000 +#define DDRSS_PI_30_DATA 0x00060602 +#define DDRSS_PI_31_DATA 0x00000000 +#define DDRSS_PI_32_DATA 0x00000000 +#define DDRSS_PI_33_DATA 0x00000000 +#define DDRSS_PI_34_DATA 0x00000001 +#define DDRSS_PI_35_DATA 0x00000055 +#define DDRSS_PI_36_DATA 0x000000AA +#define DDRSS_PI_37_DATA 0x000000AD +#define DDRSS_PI_38_DATA 0x00000052 +#define DDRSS_PI_39_DATA 0x0000006A +#define DDRSS_PI_40_DATA 0x00000095 +#define DDRSS_PI_41_DATA 0x00000095 +#define DDRSS_PI_42_DATA 0x000000AD +#define DDRSS_PI_43_DATA 0x00000000 +#define DDRSS_PI_44_DATA 0x00000000 +#define DDRSS_PI_45_DATA 0x00010100 +#define DDRSS_PI_46_DATA 0x00000014 +#define DDRSS_PI_47_DATA 0x000007D0 +#define DDRSS_PI_48_DATA 0x00000300 +#define DDRSS_PI_49_DATA 0x00000000 +#define DDRSS_PI_50_DATA 0x00000000 +#define DDRSS_PI_51_DATA 0x01000000 +#define DDRSS_PI_52_DATA 0x00010101 +#define DDRSS_PI_53_DATA 0x01000000 +#define DDRSS_PI_54_DATA 0x00000000 +#define DDRSS_PI_55_DATA 0x00010000 +#define DDRSS_PI_56_DATA 0x00000000 +#define DDRSS_PI_57_DATA 0x00000000 +#define DDRSS_PI_58_DATA 0x00000000 +#define DDRSS_PI_59_DATA 0x00000000 +#define DDRSS_PI_60_DATA 0x00001400 +#define DDRSS_PI_61_DATA 0x00000000 +#define DDRSS_PI_62_DATA 0x01000000 +#define DDRSS_PI_63_DATA 0x00000404 +#define DDRSS_PI_64_DATA 0x00000001 +#define DDRSS_PI_65_DATA 0x0001010E +#define DDRSS_PI_66_DATA 0x02040100 +#define DDRSS_PI_67_DATA 0x00010000 +#define DDRSS_PI_68_DATA 0x00000034 +#define DDRSS_PI_69_DATA 0x00000000 +#define DDRSS_PI_70_DATA 0x00000000 +#define DDRSS_PI_71_DATA 0x00000000 +#define DDRSS_PI_72_DATA 0x00000000 +#define DDRSS_PI_73_DATA 0x00000000 +#define DDRSS_PI_74_DATA 0x00000000 +#define DDRSS_PI_75_DATA 0x00000005 +#define DDRSS_PI_76_DATA 0x01000000 +#define DDRSS_PI_77_DATA 0x04000100 +#define DDRSS_PI_78_DATA 0x00020000 +#define DDRSS_PI_79_DATA 0x00010002 +#define DDRSS_PI_80_DATA 0x00000001 +#define DDRSS_PI_81_DATA 0x00020001 +#define DDRSS_PI_82_DATA 0x00020002 +#define DDRSS_PI_83_DATA 0x00000000 +#define DDRSS_PI_84_DATA 0x00000000 +#define DDRSS_PI_85_DATA 0x00000000 +#define DDRSS_PI_86_DATA 0x00000000 +#define DDRSS_PI_87_DATA 0x00000000 +#define DDRSS_PI_88_DATA 0x00000000 +#define DDRSS_PI_89_DATA 0x00000000 +#define DDRSS_PI_90_DATA 0x00000000 +#define DDRSS_PI_91_DATA 0x00000300 +#define DDRSS_PI_92_DATA 0x0A090B0C +#define DDRSS_PI_93_DATA 0x04060708 +#define DDRSS_PI_94_DATA 0x01000005 +#define DDRSS_PI_95_DATA 0x00000800 +#define DDRSS_PI_96_DATA 0x00000000 +#define DDRSS_PI_97_DATA 0x00010008 +#define DDRSS_PI_98_DATA 0x00000000 +#define DDRSS_PI_99_DATA 0x0000AA00 +#define DDRSS_PI_100_DATA 0x00000000 +#define DDRSS_PI_101_DATA 0x00010000 +#define DDRSS_PI_102_DATA 0x00000000 +#define DDRSS_PI_103_DATA 0x00000000 +#define DDRSS_PI_104_DATA 0x00000000 +#define DDRSS_PI_105_DATA 0x00000000 +#define DDRSS_PI_106_DATA 0x00000000 +#define DDRSS_PI_107_DATA 0x00000000 +#define DDRSS_PI_108_DATA 0x00000000 +#define DDRSS_PI_109_DATA 0x00000000 +#define DDRSS_PI_110_DATA 0x00000000 +#define DDRSS_PI_111_DATA 0x00000000 +#define DDRSS_PI_112_DATA 0x00000000 +#define DDRSS_PI_113_DATA 0x00000000 +#define DDRSS_PI_114_DATA 0x00000000 +#define DDRSS_PI_115_DATA 0x00000000 +#define DDRSS_PI_116_DATA 0x00000000 +#define DDRSS_PI_117_DATA 0x00000000 +#define DDRSS_PI_118_DATA 0x00000000 +#define DDRSS_PI_119_DATA 0x00000000 +#define DDRSS_PI_120_DATA 0x00000000 +#define DDRSS_PI_121_DATA 0x00000000 +#define DDRSS_PI_122_DATA 0x00000000 +#define DDRSS_PI_123_DATA 0x00000000 +#define DDRSS_PI_124_DATA 0x00000008 +#define DDRSS_PI_125_DATA 0x00000000 +#define DDRSS_PI_126_DATA 0x00000000 +#define DDRSS_PI_127_DATA 0x00000000 +#define DDRSS_PI_128_DATA 0x00000000 +#define DDRSS_PI_129_DATA 0x00000000 +#define DDRSS_PI_130_DATA 0x00000000 +#define DDRSS_PI_131_DATA 0x00000000 +#define DDRSS_PI_132_DATA 0x00000000 +#define DDRSS_PI_133_DATA 0x00010100 +#define DDRSS_PI_134_DATA 0x00000000 +#define DDRSS_PI_135_DATA 0x00000000 +#define DDRSS_PI_136_DATA 0x00027100 +#define DDRSS_PI_137_DATA 0x00061A80 +#define DDRSS_PI_138_DATA 0x00000100 +#define DDRSS_PI_139_DATA 0x00000000 +#define DDRSS_PI_140_DATA 0x00000000 +#define DDRSS_PI_141_DATA 0x00000000 +#define DDRSS_PI_142_DATA 0x00000000 +#define DDRSS_PI_143_DATA 0x00000000 +#define DDRSS_PI_144_DATA 0x01000000 +#define DDRSS_PI_145_DATA 0x00010003 +#define DDRSS_PI_146_DATA 0x02000101 +#define DDRSS_PI_147_DATA 0x01030001 +#define DDRSS_PI_148_DATA 0x00010400 +#define DDRSS_PI_149_DATA 0x06000105 +#define DDRSS_PI_150_DATA 0x01070001 +#define DDRSS_PI_151_DATA 0x00000000 +#define DDRSS_PI_152_DATA 0x00000000 +#define DDRSS_PI_153_DATA 0x00000000 +#define DDRSS_PI_154_DATA 0x00010000 +#define DDRSS_PI_155_DATA 0x00000000 +#define DDRSS_PI_156_DATA 0x00000000 +#define DDRSS_PI_157_DATA 0x00000000 +#define DDRSS_PI_158_DATA 0x00000000 +#define DDRSS_PI_159_DATA 0x00010000 +#define DDRSS_PI_160_DATA 0x00000004 +#define DDRSS_PI_161_DATA 0x00000000 +#define DDRSS_PI_162_DATA 0x00000000 +#define DDRSS_PI_163_DATA 0x00000000 +#define DDRSS_PI_164_DATA 0x00007800 +#define DDRSS_PI_165_DATA 0x00780078 +#define DDRSS_PI_166_DATA 0x00141414 +#define DDRSS_PI_167_DATA 0x0000003A +#define DDRSS_PI_168_DATA 0x0000003A +#define DDRSS_PI_169_DATA 0x0004003A +#define DDRSS_PI_170_DATA 0x04000400 +#define DDRSS_PI_171_DATA 0xC8040009 +#define DDRSS_PI_172_DATA 0x0400091C +#define DDRSS_PI_173_DATA 0x00091CC8 +#define DDRSS_PI_174_DATA 0x001CC804 +#define DDRSS_PI_175_DATA 0x00000118 +#define DDRSS_PI_176_DATA 0x00001860 +#define DDRSS_PI_177_DATA 0x00000118 +#define DDRSS_PI_178_DATA 0x00001860 +#define DDRSS_PI_179_DATA 0x00000118 +#define DDRSS_PI_180_DATA 0x04001860 +#define DDRSS_PI_181_DATA 0x01010404 +#define DDRSS_PI_182_DATA 0x00001901 +#define DDRSS_PI_183_DATA 0x00190019 +#define DDRSS_PI_184_DATA 0x010C010C +#define DDRSS_PI_185_DATA 0x0000010C +#define DDRSS_PI_186_DATA 0x00000000 +#define DDRSS_PI_187_DATA 0x05000000 +#define DDRSS_PI_188_DATA 0x01010505 +#define DDRSS_PI_189_DATA 0x01010101 +#define DDRSS_PI_190_DATA 0x00181818 +#define DDRSS_PI_191_DATA 0x00000000 +#define DDRSS_PI_192_DATA 0x00000000 +#define DDRSS_PI_193_DATA 0x0D000000 +#define DDRSS_PI_194_DATA 0x0A0A0D0D +#define DDRSS_PI_195_DATA 0x0303030A +#define DDRSS_PI_196_DATA 0x00000000 +#define DDRSS_PI_197_DATA 0x00000000 +#define DDRSS_PI_198_DATA 0x00000000 +#define DDRSS_PI_199_DATA 0x00000000 +#define DDRSS_PI_200_DATA 0x00000000 +#define DDRSS_PI_201_DATA 0x00000000 +#define DDRSS_PI_202_DATA 0x00000000 +#define DDRSS_PI_203_DATA 0x00000000 +#define DDRSS_PI_204_DATA 0x00000000 +#define DDRSS_PI_205_DATA 0x00000000 +#define DDRSS_PI_206_DATA 0x00000000 +#define DDRSS_PI_207_DATA 0x00000000 +#define DDRSS_PI_208_DATA 0x00000000 +#define DDRSS_PI_209_DATA 0x0D090000 +#define DDRSS_PI_210_DATA 0x0D09000D +#define DDRSS_PI_211_DATA 0x0D09000D +#define DDRSS_PI_212_DATA 0x0000000D +#define DDRSS_PI_213_DATA 0x00000000 +#define DDRSS_PI_214_DATA 0x00000000 +#define DDRSS_PI_215_DATA 0x00000000 +#define DDRSS_PI_216_DATA 0x00000000 +#define DDRSS_PI_217_DATA 0x16000000 +#define DDRSS_PI_218_DATA 0x001600C8 +#define DDRSS_PI_219_DATA 0x001600C8 +#define DDRSS_PI_220_DATA 0x010100C8 +#define DDRSS_PI_221_DATA 0x00001B01 +#define DDRSS_PI_222_DATA 0x1F0F0053 +#define DDRSS_PI_223_DATA 0x05000001 +#define DDRSS_PI_224_DATA 0x001B0A0D +#define DDRSS_PI_225_DATA 0x1F0F0053 +#define DDRSS_PI_226_DATA 0x05000001 +#define DDRSS_PI_227_DATA 0x001B0A0D +#define DDRSS_PI_228_DATA 0x1F0F0053 +#define DDRSS_PI_229_DATA 0x05000001 +#define DDRSS_PI_230_DATA 0x00010A0D +#define DDRSS_PI_231_DATA 0x0C0B0700 +#define DDRSS_PI_232_DATA 0x000D0605 +#define DDRSS_PI_233_DATA 0x0000C570 +#define DDRSS_PI_234_DATA 0x0000001D +#define DDRSS_PI_235_DATA 0x180A0800 +#define DDRSS_PI_236_DATA 0x0B071C1C +#define DDRSS_PI_237_DATA 0x0D06050C +#define DDRSS_PI_238_DATA 0x0000C570 +#define DDRSS_PI_239_DATA 0x0000001D +#define DDRSS_PI_240_DATA 0x180A0800 +#define DDRSS_PI_241_DATA 0x0B071C1C +#define DDRSS_PI_242_DATA 0x0D06050C +#define DDRSS_PI_243_DATA 0x0000C570 +#define DDRSS_PI_244_DATA 0x0000001D +#define DDRSS_PI_245_DATA 0x180A0800 +#define DDRSS_PI_246_DATA 0x00001C1C +#define DDRSS_PI_247_DATA 0x000030C0 +#define DDRSS_PI_248_DATA 0x0001E780 +#define DDRSS_PI_249_DATA 0x000030C0 +#define DDRSS_PI_250_DATA 0x0001E780 +#define DDRSS_PI_251_DATA 0x000030C0 +#define DDRSS_PI_252_DATA 0x0001E780 +#define DDRSS_PI_253_DATA 0x04000400 +#define DDRSS_PI_254_DATA 0x03030400 +#define DDRSS_PI_255_DATA 0x00040003 +#define DDRSS_PI_256_DATA 0x04000400 +#define DDRSS_PI_257_DATA 0x0C080C08 +#define DDRSS_PI_258_DATA 0x00000C08 +#define DDRSS_PI_259_DATA 0x000890B8 +#define DDRSS_PI_260_DATA 0x00000000 +#define DDRSS_PI_261_DATA 0x00000000 +#define DDRSS_PI_262_DATA 0x00000000 +#define DDRSS_PI_263_DATA 0x00000120 +#define DDRSS_PI_264_DATA 0x000890B8 +#define DDRSS_PI_265_DATA 0x00000000 +#define DDRSS_PI_266_DATA 0x00000000 +#define DDRSS_PI_267_DATA 0x00000000 +#define DDRSS_PI_268_DATA 0x00000120 +#define DDRSS_PI_269_DATA 0x000890B8 +#define DDRSS_PI_270_DATA 0x00000000 +#define DDRSS_PI_271_DATA 0x00000000 +#define DDRSS_PI_272_DATA 0x00000000 +#define DDRSS_PI_273_DATA 0x02000120 +#define DDRSS_PI_274_DATA 0x00000080 +#define DDRSS_PI_275_DATA 0x00020000 +#define DDRSS_PI_276_DATA 0x00000080 +#define DDRSS_PI_277_DATA 0x00020000 +#define DDRSS_PI_278_DATA 0x00000080 +#define DDRSS_PI_279_DATA 0x00000000 +#define DDRSS_PI_280_DATA 0x00000000 +#define DDRSS_PI_281_DATA 0x00040404 +#define DDRSS_PI_282_DATA 0x00000000 +#define DDRSS_PI_283_DATA 0x02010102 +#define DDRSS_PI_284_DATA 0x67676767 +#define DDRSS_PI_285_DATA 0x00000202 +#define DDRSS_PI_286_DATA 0x00000000 +#define DDRSS_PI_287_DATA 0x00000000 +#define DDRSS_PI_288_DATA 0x00000000 +#define DDRSS_PI_289_DATA 0x00000000 +#define DDRSS_PI_290_DATA 0x00000000 +#define DDRSS_PI_291_DATA 0x0D100F00 +#define DDRSS_PI_292_DATA 0x0003020E +#define DDRSS_PI_293_DATA 0x00000001 +#define DDRSS_PI_294_DATA 0x01000000 +#define DDRSS_PI_295_DATA 0x00020201 +#define DDRSS_PI_296_DATA 0x00000000 +#define DDRSS_PI_297_DATA 0x00000424 +#define DDRSS_PI_298_DATA 0x00000301 +#define DDRSS_PI_299_DATA 0x00000000 +#define DDRSS_PI_300_DATA 0x00000000 +#define DDRSS_PI_301_DATA 0x00000000 +#define DDRSS_PI_302_DATA 0x00001401 +#define DDRSS_PI_303_DATA 0x00000493 +#define DDRSS_PI_304_DATA 0x00000000 +#define DDRSS_PI_305_DATA 0x00000424 +#define DDRSS_PI_306_DATA 0x00000301 +#define DDRSS_PI_307_DATA 0x00000000 +#define DDRSS_PI_308_DATA 0x00000000 +#define DDRSS_PI_309_DATA 0x00000000 +#define DDRSS_PI_310_DATA 0x00001401 +#define DDRSS_PI_311_DATA 0x00000493 +#define DDRSS_PI_312_DATA 0x00000000 +#define DDRSS_PI_313_DATA 0x00000424 +#define DDRSS_PI_314_DATA 0x00000301 +#define DDRSS_PI_315_DATA 0x00000000 +#define DDRSS_PI_316_DATA 0x00000000 +#define DDRSS_PI_317_DATA 0x00000000 +#define DDRSS_PI_318_DATA 0x00001401 +#define DDRSS_PI_319_DATA 0x00000493 +#define DDRSS_PI_320_DATA 0x00000000 +#define DDRSS_PI_321_DATA 0x00000424 +#define DDRSS_PI_322_DATA 0x00000301 +#define DDRSS_PI_323_DATA 0x00000000 +#define DDRSS_PI_324_DATA 0x00000000 +#define DDRSS_PI_325_DATA 0x00000000 +#define DDRSS_PI_326_DATA 0x00001401 +#define DDRSS_PI_327_DATA 0x00000493 +#define DDRSS_PI_328_DATA 0x00000000 +#define DDRSS_PI_329_DATA 0x00000424 +#define DDRSS_PI_330_DATA 0x00000301 +#define DDRSS_PI_331_DATA 0x00000000 +#define DDRSS_PI_332_DATA 0x00000000 +#define DDRSS_PI_333_DATA 0x00000000 +#define DDRSS_PI_334_DATA 0x00001401 +#define DDRSS_PI_335_DATA 0x00000493 +#define DDRSS_PI_336_DATA 0x00000000 +#define DDRSS_PI_337_DATA 0x00000424 +#define DDRSS_PI_338_DATA 0x00000301 +#define DDRSS_PI_339_DATA 0x00000000 +#define DDRSS_PI_340_DATA 0x00000000 +#define DDRSS_PI_341_DATA 0x00000000 +#define DDRSS_PI_342_DATA 0x00001401 +#define DDRSS_PI_343_DATA 0x00000493 +#define DDRSS_PI_344_DATA 0x00000000 +#define DDRSS_PHY_0_DATA 0x04C00000 +#define DDRSS_PHY_1_DATA 0x00000000 +#define DDRSS_PHY_2_DATA 0x00000200 +#define DDRSS_PHY_3_DATA 0x00000000 +#define DDRSS_PHY_4_DATA 0x00000000 +#define DDRSS_PHY_5_DATA 0x00000000 +#define DDRSS_PHY_6_DATA 0x00000000 +#define DDRSS_PHY_7_DATA 0x00000000 +#define DDRSS_PHY_8_DATA 0x00000001 +#define DDRSS_PHY_9_DATA 0x00000000 +#define DDRSS_PHY_10_DATA 0x00000000 +#define DDRSS_PHY_11_DATA 0x010101FF +#define DDRSS_PHY_12_DATA 0x00010000 +#define DDRSS_PHY_13_DATA 0x00C00004 +#define DDRSS_PHY_14_DATA 0x00CC0008 +#define DDRSS_PHY_15_DATA 0x00660201 +#define DDRSS_PHY_16_DATA 0x00000000 +#define DDRSS_PHY_17_DATA 0x00000000 +#define DDRSS_PHY_18_DATA 0x00000000 +#define DDRSS_PHY_19_DATA 0x0000AAAA +#define DDRSS_PHY_20_DATA 0x00005555 +#define DDRSS_PHY_21_DATA 0x0000B5B5 +#define DDRSS_PHY_22_DATA 0x00004A4A +#define DDRSS_PHY_23_DATA 0x00005656 +#define DDRSS_PHY_24_DATA 0x0000A9A9 +#define DDRSS_PHY_25_DATA 0x0000B7B7 +#define DDRSS_PHY_26_DATA 0x00004848 +#define DDRSS_PHY_27_DATA 0x00000000 +#define DDRSS_PHY_28_DATA 0x00000000 +#define DDRSS_PHY_29_DATA 0x08000000 +#define DDRSS_PHY_30_DATA 0x0F000008 +#define DDRSS_PHY_31_DATA 0x00000F0F +#define DDRSS_PHY_32_DATA 0x00E4E400 +#define DDRSS_PHY_33_DATA 0x00070820 +#define DDRSS_PHY_34_DATA 0x000C0020 +#define DDRSS_PHY_35_DATA 0x00062000 +#define DDRSS_PHY_36_DATA 0x00000000 +#define DDRSS_PHY_37_DATA 0x55555555 +#define DDRSS_PHY_38_DATA 0xAAAAAAAA +#define DDRSS_PHY_39_DATA 0x55555555 +#define DDRSS_PHY_40_DATA 0xAAAAAAAA +#define DDRSS_PHY_41_DATA 0x00005555 +#define DDRSS_PHY_42_DATA 0x01000100 +#define DDRSS_PHY_43_DATA 0x00800180 +#define DDRSS_PHY_44_DATA 0x00000000 +#define DDRSS_PHY_45_DATA 0x00000000 +#define DDRSS_PHY_46_DATA 0x00000000 +#define DDRSS_PHY_47_DATA 0x00000000 +#define DDRSS_PHY_48_DATA 0x00000000 +#define DDRSS_PHY_49_DATA 0x00000000 +#define DDRSS_PHY_50_DATA 0x00000000 +#define DDRSS_PHY_51_DATA 0x00000000 +#define DDRSS_PHY_52_DATA 0x00000000 +#define DDRSS_PHY_53_DATA 0x00000000 +#define DDRSS_PHY_54_DATA 0x00000000 +#define DDRSS_PHY_55_DATA 0x00000000 +#define DDRSS_PHY_56_DATA 0x00000000 +#define DDRSS_PHY_57_DATA 0x00000000 +#define DDRSS_PHY_58_DATA 0x00000000 +#define DDRSS_PHY_59_DATA 0x00000000 +#define DDRSS_PHY_60_DATA 0x00000000 +#define DDRSS_PHY_61_DATA 0x00000000 +#define DDRSS_PHY_62_DATA 0x00000000 +#define DDRSS_PHY_63_DATA 0x00000000 +#define DDRSS_PHY_64_DATA 0x00000000 +#define DDRSS_PHY_65_DATA 0x00000004 +#define DDRSS_PHY_66_DATA 0x00000000 +#define DDRSS_PHY_67_DATA 0x00000000 +#define DDRSS_PHY_68_DATA 0x00000000 +#define DDRSS_PHY_69_DATA 0x00000000 +#define DDRSS_PHY_70_DATA 0x00000000 +#define DDRSS_PHY_71_DATA 0x00000000 +#define DDRSS_PHY_72_DATA 0x041F07FF +#define DDRSS_PHY_73_DATA 0x00000000 +#define DDRSS_PHY_74_DATA 0x01CCB001 +#define DDRSS_PHY_75_DATA 0x2000CCB0 +#define DDRSS_PHY_76_DATA 0x20000140 +#define DDRSS_PHY_77_DATA 0x07FF0200 +#define DDRSS_PHY_78_DATA 0x0000DD01 +#define DDRSS_PHY_79_DATA 0x10100303 +#define DDRSS_PHY_80_DATA 0x10101010 +#define DDRSS_PHY_81_DATA 0x10101010 +#define DDRSS_PHY_82_DATA 0x00021010 +#define DDRSS_PHY_83_DATA 0x00100010 +#define DDRSS_PHY_84_DATA 0x00100010 +#define DDRSS_PHY_85_DATA 0x00100010 +#define DDRSS_PHY_86_DATA 0x00100010 +#define DDRSS_PHY_87_DATA 0x02020010 +#define DDRSS_PHY_88_DATA 0x51515041 +#define DDRSS_PHY_89_DATA 0x31804000 +#define DDRSS_PHY_90_DATA 0x04BF0340 +#define DDRSS_PHY_91_DATA 0x01008080 +#define DDRSS_PHY_92_DATA 0x04050001 +#define DDRSS_PHY_93_DATA 0x00000504 +#define DDRSS_PHY_94_DATA 0x42100010 +#define DDRSS_PHY_95_DATA 0x010C053E +#define DDRSS_PHY_96_DATA 0x000F0C14 +#define DDRSS_PHY_97_DATA 0x01000140 +#define DDRSS_PHY_98_DATA 0x007A0120 +#define DDRSS_PHY_99_DATA 0x00000C00 +#define DDRSS_PHY_100_DATA 0x000001CC +#define DDRSS_PHY_101_DATA 0x20100200 +#define DDRSS_PHY_102_DATA 0x00000005 +#define DDRSS_PHY_103_DATA 0x76543210 +#define DDRSS_PHY_104_DATA 0x00000008 +#define DDRSS_PHY_105_DATA 0x02800280 +#define DDRSS_PHY_106_DATA 0x02800280 +#define DDRSS_PHY_107_DATA 0x02800280 +#define DDRSS_PHY_108_DATA 0x02800280 +#define DDRSS_PHY_109_DATA 0x00000280 +#define DDRSS_PHY_110_DATA 0x00008000 +#define DDRSS_PHY_111_DATA 0x00800080 +#define DDRSS_PHY_112_DATA 0x00800080 +#define DDRSS_PHY_113_DATA 0x00800080 +#define DDRSS_PHY_114_DATA 0x00800080 +#define DDRSS_PHY_115_DATA 0x00800080 +#define DDRSS_PHY_116_DATA 0x00800080 +#define DDRSS_PHY_117_DATA 0x00800080 +#define DDRSS_PHY_118_DATA 0x00800080 +#define DDRSS_PHY_119_DATA 0x01000080 +#define DDRSS_PHY_120_DATA 0x01000000 +#define DDRSS_PHY_121_DATA 0x00000000 +#define DDRSS_PHY_122_DATA 0x00000000 +#define DDRSS_PHY_123_DATA 0x00080200 +#define DDRSS_PHY_124_DATA 0x00000000 +#define DDRSS_PHY_125_DATA 0x00000000 +#define DDRSS_PHY_126_DATA 0x00000000 +#define DDRSS_PHY_127_DATA 0x00000000 +#define DDRSS_PHY_128_DATA 0x00000000 +#define DDRSS_PHY_129_DATA 0x00000000 +#define DDRSS_PHY_130_DATA 0x00000000 +#define DDRSS_PHY_131_DATA 0x00000000 +#define DDRSS_PHY_132_DATA 0x00000000 +#define DDRSS_PHY_133_DATA 0x00000000 +#define DDRSS_PHY_134_DATA 0x00000000 +#define DDRSS_PHY_135_DATA 0x00000000 +#define DDRSS_PHY_136_DATA 0x00000000 +#define DDRSS_PHY_137_DATA 0x00000000 +#define DDRSS_PHY_138_DATA 0x00000000 +#define DDRSS_PHY_139_DATA 0x00000000 +#define DDRSS_PHY_140_DATA 0x00000000 +#define DDRSS_PHY_141_DATA 0x00000000 +#define DDRSS_PHY_142_DATA 0x00000000 +#define DDRSS_PHY_143_DATA 0x00000000 +#define DDRSS_PHY_144_DATA 0x00000000 +#define DDRSS_PHY_145_DATA 0x00000000 +#define DDRSS_PHY_146_DATA 0x00000000 +#define DDRSS_PHY_147_DATA 0x00000000 +#define DDRSS_PHY_148_DATA 0x00000000 +#define DDRSS_PHY_149_DATA 0x00000000 +#define DDRSS_PHY_150_DATA 0x00000000 +#define DDRSS_PHY_151_DATA 0x00000000 +#define DDRSS_PHY_152_DATA 0x00000000 +#define DDRSS_PHY_153_DATA 0x00000000 +#define DDRSS_PHY_154_DATA 0x00000000 +#define DDRSS_PHY_155_DATA 0x00000000 +#define DDRSS_PHY_156_DATA 0x00000000 +#define DDRSS_PHY_157_DATA 0x00000000 +#define DDRSS_PHY_158_DATA 0x00000000 +#define DDRSS_PHY_159_DATA 0x00000000 +#define DDRSS_PHY_160_DATA 0x00000000 +#define DDRSS_PHY_161_DATA 0x00000000 +#define DDRSS_PHY_162_DATA 0x00000000 +#define DDRSS_PHY_163_DATA 0x00000000 +#define DDRSS_PHY_164_DATA 0x00000000 +#define DDRSS_PHY_165_DATA 0x00000000 +#define DDRSS_PHY_166_DATA 0x00000000 +#define DDRSS_PHY_167_DATA 0x00000000 +#define DDRSS_PHY_168_DATA 0x00000000 +#define DDRSS_PHY_169_DATA 0x00000000 +#define DDRSS_PHY_170_DATA 0x00000000 +#define DDRSS_PHY_171_DATA 0x00000000 +#define DDRSS_PHY_172_DATA 0x00000000 +#define DDRSS_PHY_173_DATA 0x00000000 +#define DDRSS_PHY_174_DATA 0x00000000 +#define DDRSS_PHY_175_DATA 0x00000000 +#define DDRSS_PHY_176_DATA 0x00000000 +#define DDRSS_PHY_177_DATA 0x00000000 +#define DDRSS_PHY_178_DATA 0x00000000 +#define DDRSS_PHY_179_DATA 0x00000000 +#define DDRSS_PHY_180_DATA 0x00000000 +#define DDRSS_PHY_181_DATA 0x00000000 +#define DDRSS_PHY_182_DATA 0x00000000 +#define DDRSS_PHY_183_DATA 0x00000000 +#define DDRSS_PHY_184_DATA 0x00000000 +#define DDRSS_PHY_185_DATA 0x00000000 +#define DDRSS_PHY_186_DATA 0x00000000 +#define DDRSS_PHY_187_DATA 0x00000000 +#define DDRSS_PHY_188_DATA 0x00000000 +#define DDRSS_PHY_189_DATA 0x00000000 +#define DDRSS_PHY_190_DATA 0x00000000 +#define DDRSS_PHY_191_DATA 0x00000000 +#define DDRSS_PHY_192_DATA 0x00000000 +#define DDRSS_PHY_193_DATA 0x00000000 +#define DDRSS_PHY_194_DATA 0x00000000 +#define DDRSS_PHY_195_DATA 0x00000000 +#define DDRSS_PHY_196_DATA 0x00000000 +#define DDRSS_PHY_197_DATA 0x00000000 +#define DDRSS_PHY_198_DATA 0x00000000 +#define DDRSS_PHY_199_DATA 0x00000000 +#define DDRSS_PHY_200_DATA 0x00000000 +#define DDRSS_PHY_201_DATA 0x00000000 +#define DDRSS_PHY_202_DATA 0x00000000 +#define DDRSS_PHY_203_DATA 0x00000000 +#define DDRSS_PHY_204_DATA 0x00000000 +#define DDRSS_PHY_205_DATA 0x00000000 +#define DDRSS_PHY_206_DATA 0x00000000 +#define DDRSS_PHY_207_DATA 0x00000000 +#define DDRSS_PHY_208_DATA 0x00000000 +#define DDRSS_PHY_209_DATA 0x00000000 +#define DDRSS_PHY_210_DATA 0x00000000 +#define DDRSS_PHY_211_DATA 0x00000000 +#define DDRSS_PHY_212_DATA 0x00000000 +#define DDRSS_PHY_213_DATA 0x00000000 +#define DDRSS_PHY_214_DATA 0x00000000 +#define DDRSS_PHY_215_DATA 0x00000000 +#define DDRSS_PHY_216_DATA 0x00000000 +#define DDRSS_PHY_217_DATA 0x00000000 +#define DDRSS_PHY_218_DATA 0x00000000 +#define DDRSS_PHY_219_DATA 0x00000000 +#define DDRSS_PHY_220_DATA 0x00000000 +#define DDRSS_PHY_221_DATA 0x00000000 +#define DDRSS_PHY_222_DATA 0x00000000 +#define DDRSS_PHY_223_DATA 0x00000000 +#define DDRSS_PHY_224_DATA 0x00000000 +#define DDRSS_PHY_225_DATA 0x00000000 +#define DDRSS_PHY_226_DATA 0x00000000 +#define DDRSS_PHY_227_DATA 0x00000000 +#define DDRSS_PHY_228_DATA 0x00000000 +#define DDRSS_PHY_229_DATA 0x00000000 +#define DDRSS_PHY_230_DATA 0x00000000 +#define DDRSS_PHY_231_DATA 0x00000000 +#define DDRSS_PHY_232_DATA 0x00000000 +#define DDRSS_PHY_233_DATA 0x00000000 +#define DDRSS_PHY_234_DATA 0x00000000 +#define DDRSS_PHY_235_DATA 0x00000000 +#define DDRSS_PHY_236_DATA 0x00000000 +#define DDRSS_PHY_237_DATA 0x00000000 +#define DDRSS_PHY_238_DATA 0x00000000 +#define DDRSS_PHY_239_DATA 0x00000000 +#define DDRSS_PHY_240_DATA 0x00000000 +#define DDRSS_PHY_241_DATA 0x00000000 +#define DDRSS_PHY_242_DATA 0x00000000 +#define DDRSS_PHY_243_DATA 0x00000000 +#define DDRSS_PHY_244_DATA 0x00000000 +#define DDRSS_PHY_245_DATA 0x00000000 +#define DDRSS_PHY_246_DATA 0x00000000 +#define DDRSS_PHY_247_DATA 0x00000000 +#define DDRSS_PHY_248_DATA 0x00000000 +#define DDRSS_PHY_249_DATA 0x00000000 +#define DDRSS_PHY_250_DATA 0x00000000 +#define DDRSS_PHY_251_DATA 0x00000000 +#define DDRSS_PHY_252_DATA 0x00000000 +#define DDRSS_PHY_253_DATA 0x00000000 +#define DDRSS_PHY_254_DATA 0x00000000 +#define DDRSS_PHY_255_DATA 0x00000000 +#define DDRSS_PHY_256_DATA 0x04C00000 +#define DDRSS_PHY_257_DATA 0x00000000 +#define DDRSS_PHY_258_DATA 0x00000200 +#define DDRSS_PHY_259_DATA 0x00000000 +#define DDRSS_PHY_260_DATA 0x00000000 +#define DDRSS_PHY_261_DATA 0x00000000 +#define DDRSS_PHY_262_DATA 0x00000000 +#define DDRSS_PHY_263_DATA 0x00000000 +#define DDRSS_PHY_264_DATA 0x00000001 +#define DDRSS_PHY_265_DATA 0x00000000 +#define DDRSS_PHY_266_DATA 0x00000000 +#define DDRSS_PHY_267_DATA 0x010101FF +#define DDRSS_PHY_268_DATA 0x00010000 +#define DDRSS_PHY_269_DATA 0x00C00004 +#define DDRSS_PHY_270_DATA 0x00CC0008 +#define DDRSS_PHY_271_DATA 0x00660201 +#define DDRSS_PHY_272_DATA 0x00000000 +#define DDRSS_PHY_273_DATA 0x00000000 +#define DDRSS_PHY_274_DATA 0x00000000 +#define DDRSS_PHY_275_DATA 0x0000AAAA +#define DDRSS_PHY_276_DATA 0x00005555 +#define DDRSS_PHY_277_DATA 0x0000B5B5 +#define DDRSS_PHY_278_DATA 0x00004A4A +#define DDRSS_PHY_279_DATA 0x00005656 +#define DDRSS_PHY_280_DATA 0x0000A9A9 +#define DDRSS_PHY_281_DATA 0x0000B7B7 +#define DDRSS_PHY_282_DATA 0x00004848 +#define DDRSS_PHY_283_DATA 0x00000000 +#define DDRSS_PHY_284_DATA 0x00000000 +#define DDRSS_PHY_285_DATA 0x08000000 +#define DDRSS_PHY_286_DATA 0x0F000008 +#define DDRSS_PHY_287_DATA 0x00000F0F +#define DDRSS_PHY_288_DATA 0x00E4E400 +#define DDRSS_PHY_289_DATA 0x00070820 +#define DDRSS_PHY_290_DATA 0x000C0020 +#define DDRSS_PHY_291_DATA 0x00062000 +#define DDRSS_PHY_292_DATA 0x00000000 +#define DDRSS_PHY_293_DATA 0x55555555 +#define DDRSS_PHY_294_DATA 0xAAAAAAAA +#define DDRSS_PHY_295_DATA 0x55555555 +#define DDRSS_PHY_296_DATA 0xAAAAAAAA +#define DDRSS_PHY_297_DATA 0x00005555 +#define DDRSS_PHY_298_DATA 0x01000100 +#define DDRSS_PHY_299_DATA 0x00800180 +#define DDRSS_PHY_300_DATA 0x00000000 +#define DDRSS_PHY_301_DATA 0x00000000 +#define DDRSS_PHY_302_DATA 0x00000000 +#define DDRSS_PHY_303_DATA 0x00000000 +#define DDRSS_PHY_304_DATA 0x00000000 +#define DDRSS_PHY_305_DATA 0x00000000 +#define DDRSS_PHY_306_DATA 0x00000000 +#define DDRSS_PHY_307_DATA 0x00000000 +#define DDRSS_PHY_308_DATA 0x00000000 +#define DDRSS_PHY_309_DATA 0x00000000 +#define DDRSS_PHY_310_DATA 0x00000000 +#define DDRSS_PHY_311_DATA 0x00000000 +#define DDRSS_PHY_312_DATA 0x00000000 +#define DDRSS_PHY_313_DATA 0x00000000 +#define DDRSS_PHY_314_DATA 0x00000000 +#define DDRSS_PHY_315_DATA 0x00000000 +#define DDRSS_PHY_316_DATA 0x00000000 +#define DDRSS_PHY_317_DATA 0x00000000 +#define DDRSS_PHY_318_DATA 0x00000000 +#define DDRSS_PHY_319_DATA 0x00000000 +#define DDRSS_PHY_320_DATA 0x00000000 +#define DDRSS_PHY_321_DATA 0x00000004 +#define DDRSS_PHY_322_DATA 0x00000000 +#define DDRSS_PHY_323_DATA 0x00000000 +#define DDRSS_PHY_324_DATA 0x00000000 +#define DDRSS_PHY_325_DATA 0x00000000 +#define DDRSS_PHY_326_DATA 0x00000000 +#define DDRSS_PHY_327_DATA 0x00000000 +#define DDRSS_PHY_328_DATA 0x041F07FF +#define DDRSS_PHY_329_DATA 0x00000000 +#define DDRSS_PHY_330_DATA 0x01CCB001 +#define DDRSS_PHY_331_DATA 0x2000CCB0 +#define DDRSS_PHY_332_DATA 0x20000140 +#define DDRSS_PHY_333_DATA 0x07FF0200 +#define DDRSS_PHY_334_DATA 0x0000DD01 +#define DDRSS_PHY_335_DATA 0x10100303 +#define DDRSS_PHY_336_DATA 0x10101010 +#define DDRSS_PHY_337_DATA 0x10101010 +#define DDRSS_PHY_338_DATA 0x00021010 +#define DDRSS_PHY_339_DATA 0x00100010 +#define DDRSS_PHY_340_DATA 0x00100010 +#define DDRSS_PHY_341_DATA 0x00100010 +#define DDRSS_PHY_342_DATA 0x00100010 +#define DDRSS_PHY_343_DATA 0x02020010 +#define DDRSS_PHY_344_DATA 0x51515041 +#define DDRSS_PHY_345_DATA 0x31804000 +#define DDRSS_PHY_346_DATA 0x04BF0340 +#define DDRSS_PHY_347_DATA 0x01008080 +#define DDRSS_PHY_348_DATA 0x04050001 +#define DDRSS_PHY_349_DATA 0x00000504 +#define DDRSS_PHY_350_DATA 0x42100010 +#define DDRSS_PHY_351_DATA 0x010C053E +#define DDRSS_PHY_352_DATA 0x000F0C14 +#define DDRSS_PHY_353_DATA 0x01000140 +#define DDRSS_PHY_354_DATA 0x007A0120 +#define DDRSS_PHY_355_DATA 0x00000C00 +#define DDRSS_PHY_356_DATA 0x000001CC +#define DDRSS_PHY_357_DATA 0x20100200 +#define DDRSS_PHY_358_DATA 0x00000005 +#define DDRSS_PHY_359_DATA 0x76543210 +#define DDRSS_PHY_360_DATA 0x00000008 +#define DDRSS_PHY_361_DATA 0x02800280 +#define DDRSS_PHY_362_DATA 0x02800280 +#define DDRSS_PHY_363_DATA 0x02800280 +#define DDRSS_PHY_364_DATA 0x02800280 +#define DDRSS_PHY_365_DATA 0x00000280 +#define DDRSS_PHY_366_DATA 0x00008000 +#define DDRSS_PHY_367_DATA 0x00800080 +#define DDRSS_PHY_368_DATA 0x00800080 +#define DDRSS_PHY_369_DATA 0x00800080 +#define DDRSS_PHY_370_DATA 0x00800080 +#define DDRSS_PHY_371_DATA 0x00800080 +#define DDRSS_PHY_372_DATA 0x00800080 +#define DDRSS_PHY_373_DATA 0x00800080 +#define DDRSS_PHY_374_DATA 0x00800080 +#define DDRSS_PHY_375_DATA 0x01000080 +#define DDRSS_PHY_376_DATA 0x01000000 +#define DDRSS_PHY_377_DATA 0x00000000 +#define DDRSS_PHY_378_DATA 0x00000000 +#define DDRSS_PHY_379_DATA 0x00080200 +#define DDRSS_PHY_380_DATA 0x00000000 +#define DDRSS_PHY_381_DATA 0x00000000 +#define DDRSS_PHY_382_DATA 0x00000000 +#define DDRSS_PHY_383_DATA 0x00000000 +#define DDRSS_PHY_384_DATA 0x00000000 +#define DDRSS_PHY_385_DATA 0x00000000 +#define DDRSS_PHY_386_DATA 0x00000000 +#define DDRSS_PHY_387_DATA 0x00000000 +#define DDRSS_PHY_388_DATA 0x00000000 +#define DDRSS_PHY_389_DATA 0x00000000 +#define DDRSS_PHY_390_DATA 0x00000000 +#define DDRSS_PHY_391_DATA 0x00000000 +#define DDRSS_PHY_392_DATA 0x00000000 +#define DDRSS_PHY_393_DATA 0x00000000 +#define DDRSS_PHY_394_DATA 0x00000000 +#define DDRSS_PHY_395_DATA 0x00000000 +#define DDRSS_PHY_396_DATA 0x00000000 +#define DDRSS_PHY_397_DATA 0x00000000 +#define DDRSS_PHY_398_DATA 0x00000000 +#define DDRSS_PHY_399_DATA 0x00000000 +#define DDRSS_PHY_400_DATA 0x00000000 +#define DDRSS_PHY_401_DATA 0x00000000 +#define DDRSS_PHY_402_DATA 0x00000000 +#define DDRSS_PHY_403_DATA 0x00000000 +#define DDRSS_PHY_404_DATA 0x00000000 +#define DDRSS_PHY_405_DATA 0x00000000 +#define DDRSS_PHY_406_DATA 0x00000000 +#define DDRSS_PHY_407_DATA 0x00000000 +#define DDRSS_PHY_408_DATA 0x00000000 +#define DDRSS_PHY_409_DATA 0x00000000 +#define DDRSS_PHY_410_DATA 0x00000000 +#define DDRSS_PHY_411_DATA 0x00000000 +#define DDRSS_PHY_412_DATA 0x00000000 +#define DDRSS_PHY_413_DATA 0x00000000 +#define DDRSS_PHY_414_DATA 0x00000000 +#define DDRSS_PHY_415_DATA 0x00000000 +#define DDRSS_PHY_416_DATA 0x00000000 +#define DDRSS_PHY_417_DATA 0x00000000 +#define DDRSS_PHY_418_DATA 0x00000000 +#define DDRSS_PHY_419_DATA 0x00000000 +#define DDRSS_PHY_420_DATA 0x00000000 +#define DDRSS_PHY_421_DATA 0x00000000 +#define DDRSS_PHY_422_DATA 0x00000000 +#define DDRSS_PHY_423_DATA 0x00000000 +#define DDRSS_PHY_424_DATA 0x00000000 +#define DDRSS_PHY_425_DATA 0x00000000 +#define DDRSS_PHY_426_DATA 0x00000000 +#define DDRSS_PHY_427_DATA 0x00000000 +#define DDRSS_PHY_428_DATA 0x00000000 +#define DDRSS_PHY_429_DATA 0x00000000 +#define DDRSS_PHY_430_DATA 0x00000000 +#define DDRSS_PHY_431_DATA 0x00000000 +#define DDRSS_PHY_432_DATA 0x00000000 +#define DDRSS_PHY_433_DATA 0x00000000 +#define DDRSS_PHY_434_DATA 0x00000000 +#define DDRSS_PHY_435_DATA 0x00000000 +#define DDRSS_PHY_436_DATA 0x00000000 +#define DDRSS_PHY_437_DATA 0x00000000 +#define DDRSS_PHY_438_DATA 0x00000000 +#define DDRSS_PHY_439_DATA 0x00000000 +#define DDRSS_PHY_440_DATA 0x00000000 +#define DDRSS_PHY_441_DATA 0x00000000 +#define DDRSS_PHY_442_DATA 0x00000000 +#define DDRSS_PHY_443_DATA 0x00000000 +#define DDRSS_PHY_444_DATA 0x00000000 +#define DDRSS_PHY_445_DATA 0x00000000 +#define DDRSS_PHY_446_DATA 0x00000000 +#define DDRSS_PHY_447_DATA 0x00000000 +#define DDRSS_PHY_448_DATA 0x00000000 +#define DDRSS_PHY_449_DATA 0x00000000 +#define DDRSS_PHY_450_DATA 0x00000000 +#define DDRSS_PHY_451_DATA 0x00000000 +#define DDRSS_PHY_452_DATA 0x00000000 +#define DDRSS_PHY_453_DATA 0x00000000 +#define DDRSS_PHY_454_DATA 0x00000000 +#define DDRSS_PHY_455_DATA 0x00000000 +#define DDRSS_PHY_456_DATA 0x00000000 +#define DDRSS_PHY_457_DATA 0x00000000 +#define DDRSS_PHY_458_DATA 0x00000000 +#define DDRSS_PHY_459_DATA 0x00000000 +#define DDRSS_PHY_460_DATA 0x00000000 +#define DDRSS_PHY_461_DATA 0x00000000 +#define DDRSS_PHY_462_DATA 0x00000000 +#define DDRSS_PHY_463_DATA 0x00000000 +#define DDRSS_PHY_464_DATA 0x00000000 +#define DDRSS_PHY_465_DATA 0x00000000 +#define DDRSS_PHY_466_DATA 0x00000000 +#define DDRSS_PHY_467_DATA 0x00000000 +#define DDRSS_PHY_468_DATA 0x00000000 +#define DDRSS_PHY_469_DATA 0x00000000 +#define DDRSS_PHY_470_DATA 0x00000000 +#define DDRSS_PHY_471_DATA 0x00000000 +#define DDRSS_PHY_472_DATA 0x00000000 +#define DDRSS_PHY_473_DATA 0x00000000 +#define DDRSS_PHY_474_DATA 0x00000000 +#define DDRSS_PHY_475_DATA 0x00000000 +#define DDRSS_PHY_476_DATA 0x00000000 +#define DDRSS_PHY_477_DATA 0x00000000 +#define DDRSS_PHY_478_DATA 0x00000000 +#define DDRSS_PHY_479_DATA 0x00000000 +#define DDRSS_PHY_480_DATA 0x00000000 +#define DDRSS_PHY_481_DATA 0x00000000 +#define DDRSS_PHY_482_DATA 0x00000000 +#define DDRSS_PHY_483_DATA 0x00000000 +#define DDRSS_PHY_484_DATA 0x00000000 +#define DDRSS_PHY_485_DATA 0x00000000 +#define DDRSS_PHY_486_DATA 0x00000000 +#define DDRSS_PHY_487_DATA 0x00000000 +#define DDRSS_PHY_488_DATA 0x00000000 +#define DDRSS_PHY_489_DATA 0x00000000 +#define DDRSS_PHY_490_DATA 0x00000000 +#define DDRSS_PHY_491_DATA 0x00000000 +#define DDRSS_PHY_492_DATA 0x00000000 +#define DDRSS_PHY_493_DATA 0x00000000 +#define DDRSS_PHY_494_DATA 0x00000000 +#define DDRSS_PHY_495_DATA 0x00000000 +#define DDRSS_PHY_496_DATA 0x00000000 +#define DDRSS_PHY_497_DATA 0x00000000 +#define DDRSS_PHY_498_DATA 0x00000000 +#define DDRSS_PHY_499_DATA 0x00000000 +#define DDRSS_PHY_500_DATA 0x00000000 +#define DDRSS_PHY_501_DATA 0x00000000 +#define DDRSS_PHY_502_DATA 0x00000000 +#define DDRSS_PHY_503_DATA 0x00000000 +#define DDRSS_PHY_504_DATA 0x00000000 +#define DDRSS_PHY_505_DATA 0x00000000 +#define DDRSS_PHY_506_DATA 0x00000000 +#define DDRSS_PHY_507_DATA 0x00000000 +#define DDRSS_PHY_508_DATA 0x00000000 +#define DDRSS_PHY_509_DATA 0x00000000 +#define DDRSS_PHY_510_DATA 0x00000000 +#define DDRSS_PHY_511_DATA 0x00000000 +#define DDRSS_PHY_512_DATA 0x00000100 +#define DDRSS_PHY_513_DATA 0x00000000 +#define DDRSS_PHY_514_DATA 0x00000000 +#define DDRSS_PHY_515_DATA 0x00000000 +#define DDRSS_PHY_516_DATA 0x00000000 +#define DDRSS_PHY_517_DATA 0x00000100 +#define DDRSS_PHY_518_DATA 0x00000000 +#define DDRSS_PHY_519_DATA 0x00000000 +#define DDRSS_PHY_520_DATA 0x00000000 +#define DDRSS_PHY_521_DATA 0x00000000 +#define DDRSS_PHY_522_DATA 0x00000000 +#define DDRSS_PHY_523_DATA 0x00000000 +#define DDRSS_PHY_524_DATA 0x00000000 +#define DDRSS_PHY_525_DATA 0x00DCBA98 +#define DDRSS_PHY_526_DATA 0x00000000 +#define DDRSS_PHY_527_DATA 0x00000000 +#define DDRSS_PHY_528_DATA 0x00000000 +#define DDRSS_PHY_529_DATA 0x00000000 +#define DDRSS_PHY_530_DATA 0x00000000 +#define DDRSS_PHY_531_DATA 0x00000000 +#define DDRSS_PHY_532_DATA 0x00000000 +#define DDRSS_PHY_533_DATA 0x00000000 +#define DDRSS_PHY_534_DATA 0x00000000 +#define DDRSS_PHY_535_DATA 0x00000000 +#define DDRSS_PHY_536_DATA 0x00000000 +#define DDRSS_PHY_537_DATA 0x00000000 +#define DDRSS_PHY_538_DATA 0x00000000 +#define DDRSS_PHY_539_DATA 0x00000000 +#define DDRSS_PHY_540_DATA 0x0A418820 +#define DDRSS_PHY_541_DATA 0x103F0000 +#define DDRSS_PHY_542_DATA 0x000F0100 +#define DDRSS_PHY_543_DATA 0x0000000F +#define DDRSS_PHY_544_DATA 0x020002CC +#define DDRSS_PHY_545_DATA 0x00030000 +#define DDRSS_PHY_546_DATA 0x00000300 +#define DDRSS_PHY_547_DATA 0x00000300 +#define DDRSS_PHY_548_DATA 0x00000300 +#define DDRSS_PHY_549_DATA 0x00000300 +#define DDRSS_PHY_550_DATA 0x00000300 +#define DDRSS_PHY_551_DATA 0x42080010 +#define DDRSS_PHY_552_DATA 0x0000003E +#define DDRSS_PHY_553_DATA 0x00000000 +#define DDRSS_PHY_554_DATA 0x00000000 +#define DDRSS_PHY_555_DATA 0x00000000 +#define DDRSS_PHY_556_DATA 0x00000000 +#define DDRSS_PHY_557_DATA 0x00000000 +#define DDRSS_PHY_558_DATA 0x00000000 +#define DDRSS_PHY_559_DATA 0x00000000 +#define DDRSS_PHY_560_DATA 0x00000000 +#define DDRSS_PHY_561_DATA 0x00000000 +#define DDRSS_PHY_562_DATA 0x00000000 +#define DDRSS_PHY_563_DATA 0x00000000 +#define DDRSS_PHY_564_DATA 0x00000000 +#define DDRSS_PHY_565_DATA 0x00000000 +#define DDRSS_PHY_566_DATA 0x00000000 +#define DDRSS_PHY_567_DATA 0x00000000 +#define DDRSS_PHY_568_DATA 0x00000000 +#define DDRSS_PHY_569_DATA 0x00000000 +#define DDRSS_PHY_570_DATA 0x00000000 +#define DDRSS_PHY_571_DATA 0x00000000 +#define DDRSS_PHY_572_DATA 0x00000000 +#define DDRSS_PHY_573_DATA 0x00000000 +#define DDRSS_PHY_574_DATA 0x00000000 +#define DDRSS_PHY_575_DATA 0x00000000 +#define DDRSS_PHY_576_DATA 0x00000000 +#define DDRSS_PHY_577_DATA 0x00000000 +#define DDRSS_PHY_578_DATA 0x00000000 +#define DDRSS_PHY_579_DATA 0x00000000 +#define DDRSS_PHY_580_DATA 0x00000000 +#define DDRSS_PHY_581_DATA 0x00000000 +#define DDRSS_PHY_582_DATA 0x00000000 +#define DDRSS_PHY_583_DATA 0x00000000 +#define DDRSS_PHY_584_DATA 0x00000000 +#define DDRSS_PHY_585_DATA 0x00000000 +#define DDRSS_PHY_586_DATA 0x00000000 +#define DDRSS_PHY_587_DATA 0x00000000 +#define DDRSS_PHY_588_DATA 0x00000000 +#define DDRSS_PHY_589_DATA 0x00000000 +#define DDRSS_PHY_590_DATA 0x00000000 +#define DDRSS_PHY_591_DATA 0x00000000 +#define DDRSS_PHY_592_DATA 0x00000000 +#define DDRSS_PHY_593_DATA 0x00000000 +#define DDRSS_PHY_594_DATA 0x00000000 +#define DDRSS_PHY_595_DATA 0x00000000 +#define DDRSS_PHY_596_DATA 0x00000000 +#define DDRSS_PHY_597_DATA 0x00000000 +#define DDRSS_PHY_598_DATA 0x00000000 +#define DDRSS_PHY_599_DATA 0x00000000 +#define DDRSS_PHY_600_DATA 0x00000000 +#define DDRSS_PHY_601_DATA 0x00000000 +#define DDRSS_PHY_602_DATA 0x00000000 +#define DDRSS_PHY_603_DATA 0x00000000 +#define DDRSS_PHY_604_DATA 0x00000000 +#define DDRSS_PHY_605_DATA 0x00000000 +#define DDRSS_PHY_606_DATA 0x00000000 +#define DDRSS_PHY_607_DATA 0x00000000 +#define DDRSS_PHY_608_DATA 0x00000000 +#define DDRSS_PHY_609_DATA 0x00000000 +#define DDRSS_PHY_610_DATA 0x00000000 +#define DDRSS_PHY_611_DATA 0x00000000 +#define DDRSS_PHY_612_DATA 0x00000000 +#define DDRSS_PHY_613_DATA 0x00000000 +#define DDRSS_PHY_614_DATA 0x00000000 +#define DDRSS_PHY_615_DATA 0x00000000 +#define DDRSS_PHY_616_DATA 0x00000000 +#define DDRSS_PHY_617_DATA 0x00000000 +#define DDRSS_PHY_618_DATA 0x00000000 +#define DDRSS_PHY_619_DATA 0x00000000 +#define DDRSS_PHY_620_DATA 0x00000000 +#define DDRSS_PHY_621_DATA 0x00000000 +#define DDRSS_PHY_622_DATA 0x00000000 +#define DDRSS_PHY_623_DATA 0x00000000 +#define DDRSS_PHY_624_DATA 0x00000000 +#define DDRSS_PHY_625_DATA 0x00000000 +#define DDRSS_PHY_626_DATA 0x00000000 +#define DDRSS_PHY_627_DATA 0x00000000 +#define DDRSS_PHY_628_DATA 0x00000000 +#define DDRSS_PHY_629_DATA 0x00000000 +#define DDRSS_PHY_630_DATA 0x00000000 +#define DDRSS_PHY_631_DATA 0x00000000 +#define DDRSS_PHY_632_DATA 0x00000000 +#define DDRSS_PHY_633_DATA 0x00000000 +#define DDRSS_PHY_634_DATA 0x00000000 +#define DDRSS_PHY_635_DATA 0x00000000 +#define DDRSS_PHY_636_DATA 0x00000000 +#define DDRSS_PHY_637_DATA 0x00000000 +#define DDRSS_PHY_638_DATA 0x00000000 +#define DDRSS_PHY_639_DATA 0x00000000 +#define DDRSS_PHY_640_DATA 0x00000000 +#define DDRSS_PHY_641_DATA 0x00000000 +#define DDRSS_PHY_642_DATA 0x00000000 +#define DDRSS_PHY_643_DATA 0x00000000 +#define DDRSS_PHY_644_DATA 0x00000000 +#define DDRSS_PHY_645_DATA 0x00000000 +#define DDRSS_PHY_646_DATA 0x00000000 +#define DDRSS_PHY_647_DATA 0x00000000 +#define DDRSS_PHY_648_DATA 0x00000000 +#define DDRSS_PHY_649_DATA 0x00000000 +#define DDRSS_PHY_650_DATA 0x00000000 +#define DDRSS_PHY_651_DATA 0x00000000 +#define DDRSS_PHY_652_DATA 0x00000000 +#define DDRSS_PHY_653_DATA 0x00000000 +#define DDRSS_PHY_654_DATA 0x00000000 +#define DDRSS_PHY_655_DATA 0x00000000 +#define DDRSS_PHY_656_DATA 0x00000000 +#define DDRSS_PHY_657_DATA 0x00000000 +#define DDRSS_PHY_658_DATA 0x00000000 +#define DDRSS_PHY_659_DATA 0x00000000 +#define DDRSS_PHY_660_DATA 0x00000000 +#define DDRSS_PHY_661_DATA 0x00000000 +#define DDRSS_PHY_662_DATA 0x00000000 +#define DDRSS_PHY_663_DATA 0x00000000 +#define DDRSS_PHY_664_DATA 0x00000000 +#define DDRSS_PHY_665_DATA 0x00000000 +#define DDRSS_PHY_666_DATA 0x00000000 +#define DDRSS_PHY_667_DATA 0x00000000 +#define DDRSS_PHY_668_DATA 0x00000000 +#define DDRSS_PHY_669_DATA 0x00000000 +#define DDRSS_PHY_670_DATA 0x00000000 +#define DDRSS_PHY_671_DATA 0x00000000 +#define DDRSS_PHY_672_DATA 0x00000000 +#define DDRSS_PHY_673_DATA 0x00000000 +#define DDRSS_PHY_674_DATA 0x00000000 +#define DDRSS_PHY_675_DATA 0x00000000 +#define DDRSS_PHY_676_DATA 0x00000000 +#define DDRSS_PHY_677_DATA 0x00000000 +#define DDRSS_PHY_678_DATA 0x00000000 +#define DDRSS_PHY_679_DATA 0x00000000 +#define DDRSS_PHY_680_DATA 0x00000000 +#define DDRSS_PHY_681_DATA 0x00000000 +#define DDRSS_PHY_682_DATA 0x00000000 +#define DDRSS_PHY_683_DATA 0x00000000 +#define DDRSS_PHY_684_DATA 0x00000000 +#define DDRSS_PHY_685_DATA 0x00000000 +#define DDRSS_PHY_686_DATA 0x00000000 +#define DDRSS_PHY_687_DATA 0x00000000 +#define DDRSS_PHY_688_DATA 0x00000000 +#define DDRSS_PHY_689_DATA 0x00000000 +#define DDRSS_PHY_690_DATA 0x00000000 +#define DDRSS_PHY_691_DATA 0x00000000 +#define DDRSS_PHY_692_DATA 0x00000000 +#define DDRSS_PHY_693_DATA 0x00000000 +#define DDRSS_PHY_694_DATA 0x00000000 +#define DDRSS_PHY_695_DATA 0x00000000 +#define DDRSS_PHY_696_DATA 0x00000000 +#define DDRSS_PHY_697_DATA 0x00000000 +#define DDRSS_PHY_698_DATA 0x00000000 +#define DDRSS_PHY_699_DATA 0x00000000 +#define DDRSS_PHY_700_DATA 0x00000000 +#define DDRSS_PHY_701_DATA 0x00000000 +#define DDRSS_PHY_702_DATA 0x00000000 +#define DDRSS_PHY_703_DATA 0x00000000 +#define DDRSS_PHY_704_DATA 0x00000000 +#define DDRSS_PHY_705_DATA 0x00000000 +#define DDRSS_PHY_706_DATA 0x00000000 +#define DDRSS_PHY_707_DATA 0x00000000 +#define DDRSS_PHY_708_DATA 0x00000000 +#define DDRSS_PHY_709_DATA 0x00000000 +#define DDRSS_PHY_710_DATA 0x00000000 +#define DDRSS_PHY_711_DATA 0x00000000 +#define DDRSS_PHY_712_DATA 0x00000000 +#define DDRSS_PHY_713_DATA 0x00000000 +#define DDRSS_PHY_714_DATA 0x00000000 +#define DDRSS_PHY_715_DATA 0x00000000 +#define DDRSS_PHY_716_DATA 0x00000000 +#define DDRSS_PHY_717_DATA 0x00000000 +#define DDRSS_PHY_718_DATA 0x00000000 +#define DDRSS_PHY_719_DATA 0x00000000 +#define DDRSS_PHY_720_DATA 0x00000000 +#define DDRSS_PHY_721_DATA 0x00000000 +#define DDRSS_PHY_722_DATA 0x00000000 +#define DDRSS_PHY_723_DATA 0x00000000 +#define DDRSS_PHY_724_DATA 0x00000000 +#define DDRSS_PHY_725_DATA 0x00000000 +#define DDRSS_PHY_726_DATA 0x00000000 +#define DDRSS_PHY_727_DATA 0x00000000 +#define DDRSS_PHY_728_DATA 0x00000000 +#define DDRSS_PHY_729_DATA 0x00000000 +#define DDRSS_PHY_730_DATA 0x00000000 +#define DDRSS_PHY_731_DATA 0x00000000 +#define DDRSS_PHY_732_DATA 0x00000000 +#define DDRSS_PHY_733_DATA 0x00000000 +#define DDRSS_PHY_734_DATA 0x00000000 +#define DDRSS_PHY_735_DATA 0x00000000 +#define DDRSS_PHY_736_DATA 0x00000000 +#define DDRSS_PHY_737_DATA 0x00000000 +#define DDRSS_PHY_738_DATA 0x00000000 +#define DDRSS_PHY_739_DATA 0x00000000 +#define DDRSS_PHY_740_DATA 0x00000000 +#define DDRSS_PHY_741_DATA 0x00000000 +#define DDRSS_PHY_742_DATA 0x00000000 +#define DDRSS_PHY_743_DATA 0x00000000 +#define DDRSS_PHY_744_DATA 0x00000000 +#define DDRSS_PHY_745_DATA 0x00000000 +#define DDRSS_PHY_746_DATA 0x00000000 +#define DDRSS_PHY_747_DATA 0x00000000 +#define DDRSS_PHY_748_DATA 0x00000000 +#define DDRSS_PHY_749_DATA 0x00000000 +#define DDRSS_PHY_750_DATA 0x00000000 +#define DDRSS_PHY_751_DATA 0x00000000 +#define DDRSS_PHY_752_DATA 0x00000000 +#define DDRSS_PHY_753_DATA 0x00000000 +#define DDRSS_PHY_754_DATA 0x00000000 +#define DDRSS_PHY_755_DATA 0x00000000 +#define DDRSS_PHY_756_DATA 0x00000000 +#define DDRSS_PHY_757_DATA 0x00000000 +#define DDRSS_PHY_758_DATA 0x00000000 +#define DDRSS_PHY_759_DATA 0x00000000 +#define DDRSS_PHY_760_DATA 0x00000000 +#define DDRSS_PHY_761_DATA 0x00000000 +#define DDRSS_PHY_762_DATA 0x00000000 +#define DDRSS_PHY_763_DATA 0x00000000 +#define DDRSS_PHY_764_DATA 0x00000000 +#define DDRSS_PHY_765_DATA 0x00000000 +#define DDRSS_PHY_766_DATA 0x00000000 +#define DDRSS_PHY_767_DATA 0x00000000 +#define DDRSS_PHY_768_DATA 0x00000100 +#define DDRSS_PHY_769_DATA 0x00000000 +#define DDRSS_PHY_770_DATA 0x00000000 +#define DDRSS_PHY_771_DATA 0x00000000 +#define DDRSS_PHY_772_DATA 0x00000000 +#define DDRSS_PHY_773_DATA 0x00000100 +#define DDRSS_PHY_774_DATA 0x00000000 +#define DDRSS_PHY_775_DATA 0x00000000 +#define DDRSS_PHY_776_DATA 0x00000000 +#define DDRSS_PHY_777_DATA 0x00000000 +#define DDRSS_PHY_778_DATA 0x00000000 +#define DDRSS_PHY_779_DATA 0x00000000 +#define DDRSS_PHY_780_DATA 0x00000000 +#define DDRSS_PHY_781_DATA 0x00DCBA98 +#define DDRSS_PHY_782_DATA 0x00000000 +#define DDRSS_PHY_783_DATA 0x00000000 +#define DDRSS_PHY_784_DATA 0x00000000 +#define DDRSS_PHY_785_DATA 0x00000000 +#define DDRSS_PHY_786_DATA 0x00000000 +#define DDRSS_PHY_787_DATA 0x00000000 +#define DDRSS_PHY_788_DATA 0x00000000 +#define DDRSS_PHY_789_DATA 0x00000000 +#define DDRSS_PHY_790_DATA 0x00000000 +#define DDRSS_PHY_791_DATA 0x00000000 +#define DDRSS_PHY_792_DATA 0x00000000 +#define DDRSS_PHY_793_DATA 0x00000000 +#define DDRSS_PHY_794_DATA 0x00000000 +#define DDRSS_PHY_795_DATA 0x00000000 +#define DDRSS_PHY_796_DATA 0x16A4A0E6 +#define DDRSS_PHY_797_DATA 0x103F0000 +#define DDRSS_PHY_798_DATA 0x000F0000 +#define DDRSS_PHY_799_DATA 0x0000000F +#define DDRSS_PHY_800_DATA 0x020002CC +#define DDRSS_PHY_801_DATA 0x00030000 +#define DDRSS_PHY_802_DATA 0x00000300 +#define DDRSS_PHY_803_DATA 0x00000300 +#define DDRSS_PHY_804_DATA 0x00000300 +#define DDRSS_PHY_805_DATA 0x00000300 +#define DDRSS_PHY_806_DATA 0x00000300 +#define DDRSS_PHY_807_DATA 0x42080010 +#define DDRSS_PHY_808_DATA 0x0000003E +#define DDRSS_PHY_809_DATA 0x00000000 +#define DDRSS_PHY_810_DATA 0x00000000 +#define DDRSS_PHY_811_DATA 0x00000000 +#define DDRSS_PHY_812_DATA 0x00000000 +#define DDRSS_PHY_813_DATA 0x00000000 +#define DDRSS_PHY_814_DATA 0x00000000 +#define DDRSS_PHY_815_DATA 0x00000000 +#define DDRSS_PHY_816_DATA 0x00000000 +#define DDRSS_PHY_817_DATA 0x00000000 +#define DDRSS_PHY_818_DATA 0x00000000 +#define DDRSS_PHY_819_DATA 0x00000000 +#define DDRSS_PHY_820_DATA 0x00000000 +#define DDRSS_PHY_821_DATA 0x00000000 +#define DDRSS_PHY_822_DATA 0x00000000 +#define DDRSS_PHY_823_DATA 0x00000000 +#define DDRSS_PHY_824_DATA 0x00000000 +#define DDRSS_PHY_825_DATA 0x00000000 +#define DDRSS_PHY_826_DATA 0x00000000 +#define DDRSS_PHY_827_DATA 0x00000000 +#define DDRSS_PHY_828_DATA 0x00000000 +#define DDRSS_PHY_829_DATA 0x00000000 +#define DDRSS_PHY_830_DATA 0x00000000 +#define DDRSS_PHY_831_DATA 0x00000000 +#define DDRSS_PHY_832_DATA 0x00000000 +#define DDRSS_PHY_833_DATA 0x00000000 +#define DDRSS_PHY_834_DATA 0x00000000 +#define DDRSS_PHY_835_DATA 0x00000000 +#define DDRSS_PHY_836_DATA 0x00000000 +#define DDRSS_PHY_837_DATA 0x00000000 +#define DDRSS_PHY_838_DATA 0x00000000 +#define DDRSS_PHY_839_DATA 0x00000000 +#define DDRSS_PHY_840_DATA 0x00000000 +#define DDRSS_PHY_841_DATA 0x00000000 +#define DDRSS_PHY_842_DATA 0x00000000 +#define DDRSS_PHY_843_DATA 0x00000000 +#define DDRSS_PHY_844_DATA 0x00000000 +#define DDRSS_PHY_845_DATA 0x00000000 +#define DDRSS_PHY_846_DATA 0x00000000 +#define DDRSS_PHY_847_DATA 0x00000000 +#define DDRSS_PHY_848_DATA 0x00000000 +#define DDRSS_PHY_849_DATA 0x00000000 +#define DDRSS_PHY_850_DATA 0x00000000 +#define DDRSS_PHY_851_DATA 0x00000000 +#define DDRSS_PHY_852_DATA 0x00000000 +#define DDRSS_PHY_853_DATA 0x00000000 +#define DDRSS_PHY_854_DATA 0x00000000 +#define DDRSS_PHY_855_DATA 0x00000000 +#define DDRSS_PHY_856_DATA 0x00000000 +#define DDRSS_PHY_857_DATA 0x00000000 +#define DDRSS_PHY_858_DATA 0x00000000 +#define DDRSS_PHY_859_DATA 0x00000000 +#define DDRSS_PHY_860_DATA 0x00000000 +#define DDRSS_PHY_861_DATA 0x00000000 +#define DDRSS_PHY_862_DATA 0x00000000 +#define DDRSS_PHY_863_DATA 0x00000000 +#define DDRSS_PHY_864_DATA 0x00000000 +#define DDRSS_PHY_865_DATA 0x00000000 +#define DDRSS_PHY_866_DATA 0x00000000 +#define DDRSS_PHY_867_DATA 0x00000000 +#define DDRSS_PHY_868_DATA 0x00000000 +#define DDRSS_PHY_869_DATA 0x00000000 +#define DDRSS_PHY_870_DATA 0x00000000 +#define DDRSS_PHY_871_DATA 0x00000000 +#define DDRSS_PHY_872_DATA 0x00000000 +#define DDRSS_PHY_873_DATA 0x00000000 +#define DDRSS_PHY_874_DATA 0x00000000 +#define DDRSS_PHY_875_DATA 0x00000000 +#define DDRSS_PHY_876_DATA 0x00000000 +#define DDRSS_PHY_877_DATA 0x00000000 +#define DDRSS_PHY_878_DATA 0x00000000 +#define DDRSS_PHY_879_DATA 0x00000000 +#define DDRSS_PHY_880_DATA 0x00000000 +#define DDRSS_PHY_881_DATA 0x00000000 +#define DDRSS_PHY_882_DATA 0x00000000 +#define DDRSS_PHY_883_DATA 0x00000000 +#define DDRSS_PHY_884_DATA 0x00000000 +#define DDRSS_PHY_885_DATA 0x00000000 +#define DDRSS_PHY_886_DATA 0x00000000 +#define DDRSS_PHY_887_DATA 0x00000000 +#define DDRSS_PHY_888_DATA 0x00000000 +#define DDRSS_PHY_889_DATA 0x00000000 +#define DDRSS_PHY_890_DATA 0x00000000 +#define DDRSS_PHY_891_DATA 0x00000000 +#define DDRSS_PHY_892_DATA 0x00000000 +#define DDRSS_PHY_893_DATA 0x00000000 +#define DDRSS_PHY_894_DATA 0x00000000 +#define DDRSS_PHY_895_DATA 0x00000000 +#define DDRSS_PHY_896_DATA 0x00000000 +#define DDRSS_PHY_897_DATA 0x00000000 +#define DDRSS_PHY_898_DATA 0x00000000 +#define DDRSS_PHY_899_DATA 0x00000000 +#define DDRSS_PHY_900_DATA 0x00000000 +#define DDRSS_PHY_901_DATA 0x00000000 +#define DDRSS_PHY_902_DATA 0x00000000 +#define DDRSS_PHY_903_DATA 0x00000000 +#define DDRSS_PHY_904_DATA 0x00000000 +#define DDRSS_PHY_905_DATA 0x00000000 +#define DDRSS_PHY_906_DATA 0x00000000 +#define DDRSS_PHY_907_DATA 0x00000000 +#define DDRSS_PHY_908_DATA 0x00000000 +#define DDRSS_PHY_909_DATA 0x00000000 +#define DDRSS_PHY_910_DATA 0x00000000 +#define DDRSS_PHY_911_DATA 0x00000000 +#define DDRSS_PHY_912_DATA 0x00000000 +#define DDRSS_PHY_913_DATA 0x00000000 +#define DDRSS_PHY_914_DATA 0x00000000 +#define DDRSS_PHY_915_DATA 0x00000000 +#define DDRSS_PHY_916_DATA 0x00000000 +#define DDRSS_PHY_917_DATA 0x00000000 +#define DDRSS_PHY_918_DATA 0x00000000 +#define DDRSS_PHY_919_DATA 0x00000000 +#define DDRSS_PHY_920_DATA 0x00000000 +#define DDRSS_PHY_921_DATA 0x00000000 +#define DDRSS_PHY_922_DATA 0x00000000 +#define DDRSS_PHY_923_DATA 0x00000000 +#define DDRSS_PHY_924_DATA 0x00000000 +#define DDRSS_PHY_925_DATA 0x00000000 +#define DDRSS_PHY_926_DATA 0x00000000 +#define DDRSS_PHY_927_DATA 0x00000000 +#define DDRSS_PHY_928_DATA 0x00000000 +#define DDRSS_PHY_929_DATA 0x00000000 +#define DDRSS_PHY_930_DATA 0x00000000 +#define DDRSS_PHY_931_DATA 0x00000000 +#define DDRSS_PHY_932_DATA 0x00000000 +#define DDRSS_PHY_933_DATA 0x00000000 +#define DDRSS_PHY_934_DATA 0x00000000 +#define DDRSS_PHY_935_DATA 0x00000000 +#define DDRSS_PHY_936_DATA 0x00000000 +#define DDRSS_PHY_937_DATA 0x00000000 +#define DDRSS_PHY_938_DATA 0x00000000 +#define DDRSS_PHY_939_DATA 0x00000000 +#define DDRSS_PHY_940_DATA 0x00000000 +#define DDRSS_PHY_941_DATA 0x00000000 +#define DDRSS_PHY_942_DATA 0x00000000 +#define DDRSS_PHY_943_DATA 0x00000000 +#define DDRSS_PHY_944_DATA 0x00000000 +#define DDRSS_PHY_945_DATA 0x00000000 +#define DDRSS_PHY_946_DATA 0x00000000 +#define DDRSS_PHY_947_DATA 0x00000000 +#define DDRSS_PHY_948_DATA 0x00000000 +#define DDRSS_PHY_949_DATA 0x00000000 +#define DDRSS_PHY_950_DATA 0x00000000 +#define DDRSS_PHY_951_DATA 0x00000000 +#define DDRSS_PHY_952_DATA 0x00000000 +#define DDRSS_PHY_953_DATA 0x00000000 +#define DDRSS_PHY_954_DATA 0x00000000 +#define DDRSS_PHY_955_DATA 0x00000000 +#define DDRSS_PHY_956_DATA 0x00000000 +#define DDRSS_PHY_957_DATA 0x00000000 +#define DDRSS_PHY_958_DATA 0x00000000 +#define DDRSS_PHY_959_DATA 0x00000000 +#define DDRSS_PHY_960_DATA 0x00000000 +#define DDRSS_PHY_961_DATA 0x00000000 +#define DDRSS_PHY_962_DATA 0x00000000 +#define DDRSS_PHY_963_DATA 0x00000000 +#define DDRSS_PHY_964_DATA 0x00000000 +#define DDRSS_PHY_965_DATA 0x00000000 +#define DDRSS_PHY_966_DATA 0x00000000 +#define DDRSS_PHY_967_DATA 0x00000000 +#define DDRSS_PHY_968_DATA 0x00000000 +#define DDRSS_PHY_969_DATA 0x00000000 +#define DDRSS_PHY_970_DATA 0x00000000 +#define DDRSS_PHY_971_DATA 0x00000000 +#define DDRSS_PHY_972_DATA 0x00000000 +#define DDRSS_PHY_973_DATA 0x00000000 +#define DDRSS_PHY_974_DATA 0x00000000 +#define DDRSS_PHY_975_DATA 0x00000000 +#define DDRSS_PHY_976_DATA 0x00000000 +#define DDRSS_PHY_977_DATA 0x00000000 +#define DDRSS_PHY_978_DATA 0x00000000 +#define DDRSS_PHY_979_DATA 0x00000000 +#define DDRSS_PHY_980_DATA 0x00000000 +#define DDRSS_PHY_981_DATA 0x00000000 +#define DDRSS_PHY_982_DATA 0x00000000 +#define DDRSS_PHY_983_DATA 0x00000000 +#define DDRSS_PHY_984_DATA 0x00000000 +#define DDRSS_PHY_985_DATA 0x00000000 +#define DDRSS_PHY_986_DATA 0x00000000 +#define DDRSS_PHY_987_DATA 0x00000000 +#define DDRSS_PHY_988_DATA 0x00000000 +#define DDRSS_PHY_989_DATA 0x00000000 +#define DDRSS_PHY_990_DATA 0x00000000 +#define DDRSS_PHY_991_DATA 0x00000000 +#define DDRSS_PHY_992_DATA 0x00000000 +#define DDRSS_PHY_993_DATA 0x00000000 +#define DDRSS_PHY_994_DATA 0x00000000 +#define DDRSS_PHY_995_DATA 0x00000000 +#define DDRSS_PHY_996_DATA 0x00000000 +#define DDRSS_PHY_997_DATA 0x00000000 +#define DDRSS_PHY_998_DATA 0x00000000 +#define DDRSS_PHY_999_DATA 0x00000000 +#define DDRSS_PHY_1000_DATA 0x00000000 +#define DDRSS_PHY_1001_DATA 0x00000000 +#define DDRSS_PHY_1002_DATA 0x00000000 +#define DDRSS_PHY_1003_DATA 0x00000000 +#define DDRSS_PHY_1004_DATA 0x00000000 +#define DDRSS_PHY_1005_DATA 0x00000000 +#define DDRSS_PHY_1006_DATA 0x00000000 +#define DDRSS_PHY_1007_DATA 0x00000000 +#define DDRSS_PHY_1008_DATA 0x00000000 +#define DDRSS_PHY_1009_DATA 0x00000000 +#define DDRSS_PHY_1010_DATA 0x00000000 +#define DDRSS_PHY_1011_DATA 0x00000000 +#define DDRSS_PHY_1012_DATA 0x00000000 +#define DDRSS_PHY_1013_DATA 0x00000000 +#define DDRSS_PHY_1014_DATA 0x00000000 +#define DDRSS_PHY_1015_DATA 0x00000000 +#define DDRSS_PHY_1016_DATA 0x00000000 +#define DDRSS_PHY_1017_DATA 0x00000000 +#define DDRSS_PHY_1018_DATA 0x00000000 +#define DDRSS_PHY_1019_DATA 0x00000000 +#define DDRSS_PHY_1020_DATA 0x00000000 +#define DDRSS_PHY_1021_DATA 0x00000000 +#define DDRSS_PHY_1022_DATA 0x00000000 +#define DDRSS_PHY_1023_DATA 0x00000000 +#define DDRSS_PHY_1024_DATA 0x00000100 +#define DDRSS_PHY_1025_DATA 0x00000000 +#define DDRSS_PHY_1026_DATA 0x00000000 +#define DDRSS_PHY_1027_DATA 0x00000000 +#define DDRSS_PHY_1028_DATA 0x00000000 +#define DDRSS_PHY_1029_DATA 0x00000100 +#define DDRSS_PHY_1030_DATA 0x00000000 +#define DDRSS_PHY_1031_DATA 0x00000000 +#define DDRSS_PHY_1032_DATA 0x00000000 +#define DDRSS_PHY_1033_DATA 0x00000000 +#define DDRSS_PHY_1034_DATA 0x00000000 +#define DDRSS_PHY_1035_DATA 0x00000000 +#define DDRSS_PHY_1036_DATA 0x00000000 +#define DDRSS_PHY_1037_DATA 0x00DCBA98 +#define DDRSS_PHY_1038_DATA 0x00000000 +#define DDRSS_PHY_1039_DATA 0x00000000 +#define DDRSS_PHY_1040_DATA 0x00000000 +#define DDRSS_PHY_1041_DATA 0x00000000 +#define DDRSS_PHY_1042_DATA 0x00000000 +#define DDRSS_PHY_1043_DATA 0x00000000 +#define DDRSS_PHY_1044_DATA 0x00000000 +#define DDRSS_PHY_1045_DATA 0x00000000 +#define DDRSS_PHY_1046_DATA 0x00000000 +#define DDRSS_PHY_1047_DATA 0x00000000 +#define DDRSS_PHY_1048_DATA 0x00000000 +#define DDRSS_PHY_1049_DATA 0x00000000 +#define DDRSS_PHY_1050_DATA 0x00000000 +#define DDRSS_PHY_1051_DATA 0x00000000 +#define DDRSS_PHY_1052_DATA 0x2307B9AC +#define DDRSS_PHY_1053_DATA 0x10030000 +#define DDRSS_PHY_1054_DATA 0x000F0000 +#define DDRSS_PHY_1055_DATA 0x0000000F +#define DDRSS_PHY_1056_DATA 0x020002CC +#define DDRSS_PHY_1057_DATA 0x00030000 +#define DDRSS_PHY_1058_DATA 0x00000300 +#define DDRSS_PHY_1059_DATA 0x00000300 +#define DDRSS_PHY_1060_DATA 0x00000300 +#define DDRSS_PHY_1061_DATA 0x00000300 +#define DDRSS_PHY_1062_DATA 0x00000300 +#define DDRSS_PHY_1063_DATA 0x42080010 +#define DDRSS_PHY_1064_DATA 0x0000003E +#define DDRSS_PHY_1065_DATA 0x00000000 +#define DDRSS_PHY_1066_DATA 0x00000000 +#define DDRSS_PHY_1067_DATA 0x00000000 +#define DDRSS_PHY_1068_DATA 0x00000000 +#define DDRSS_PHY_1069_DATA 0x00000000 +#define DDRSS_PHY_1070_DATA 0x00000000 +#define DDRSS_PHY_1071_DATA 0x00000000 +#define DDRSS_PHY_1072_DATA 0x00000000 +#define DDRSS_PHY_1073_DATA 0x00000000 +#define DDRSS_PHY_1074_DATA 0x00000000 +#define DDRSS_PHY_1075_DATA 0x00000000 +#define DDRSS_PHY_1076_DATA 0x00000000 +#define DDRSS_PHY_1077_DATA 0x00000000 +#define DDRSS_PHY_1078_DATA 0x00000000 +#define DDRSS_PHY_1079_DATA 0x00000000 +#define DDRSS_PHY_1080_DATA 0x00000000 +#define DDRSS_PHY_1081_DATA 0x00000000 +#define DDRSS_PHY_1082_DATA 0x00000000 +#define DDRSS_PHY_1083_DATA 0x00000000 +#define DDRSS_PHY_1084_DATA 0x00000000 +#define DDRSS_PHY_1085_DATA 0x00000000 +#define DDRSS_PHY_1086_DATA 0x00000000 +#define DDRSS_PHY_1087_DATA 0x00000000 +#define DDRSS_PHY_1088_DATA 0x00000000 +#define DDRSS_PHY_1089_DATA 0x00000000 +#define DDRSS_PHY_1090_DATA 0x00000000 +#define DDRSS_PHY_1091_DATA 0x00000000 +#define DDRSS_PHY_1092_DATA 0x00000000 +#define DDRSS_PHY_1093_DATA 0x00000000 +#define DDRSS_PHY_1094_DATA 0x00000000 +#define DDRSS_PHY_1095_DATA 0x00000000 +#define DDRSS_PHY_1096_DATA 0x00000000 +#define DDRSS_PHY_1097_DATA 0x00000000 +#define DDRSS_PHY_1098_DATA 0x00000000 +#define DDRSS_PHY_1099_DATA 0x00000000 +#define DDRSS_PHY_1100_DATA 0x00000000 +#define DDRSS_PHY_1101_DATA 0x00000000 +#define DDRSS_PHY_1102_DATA 0x00000000 +#define DDRSS_PHY_1103_DATA 0x00000000 +#define DDRSS_PHY_1104_DATA 0x00000000 +#define DDRSS_PHY_1105_DATA 0x00000000 +#define DDRSS_PHY_1106_DATA 0x00000000 +#define DDRSS_PHY_1107_DATA 0x00000000 +#define DDRSS_PHY_1108_DATA 0x00000000 +#define DDRSS_PHY_1109_DATA 0x00000000 +#define DDRSS_PHY_1110_DATA 0x00000000 +#define DDRSS_PHY_1111_DATA 0x00000000 +#define DDRSS_PHY_1112_DATA 0x00000000 +#define DDRSS_PHY_1113_DATA 0x00000000 +#define DDRSS_PHY_1114_DATA 0x00000000 +#define DDRSS_PHY_1115_DATA 0x00000000 +#define DDRSS_PHY_1116_DATA 0x00000000 +#define DDRSS_PHY_1117_DATA 0x00000000 +#define DDRSS_PHY_1118_DATA 0x00000000 +#define DDRSS_PHY_1119_DATA 0x00000000 +#define DDRSS_PHY_1120_DATA 0x00000000 +#define DDRSS_PHY_1121_DATA 0x00000000 +#define DDRSS_PHY_1122_DATA 0x00000000 +#define DDRSS_PHY_1123_DATA 0x00000000 +#define DDRSS_PHY_1124_DATA 0x00000000 +#define DDRSS_PHY_1125_DATA 0x00000000 +#define DDRSS_PHY_1126_DATA 0x00000000 +#define DDRSS_PHY_1127_DATA 0x00000000 +#define DDRSS_PHY_1128_DATA 0x00000000 +#define DDRSS_PHY_1129_DATA 0x00000000 +#define DDRSS_PHY_1130_DATA 0x00000000 +#define DDRSS_PHY_1131_DATA 0x00000000 +#define DDRSS_PHY_1132_DATA 0x00000000 +#define DDRSS_PHY_1133_DATA 0x00000000 +#define DDRSS_PHY_1134_DATA 0x00000000 +#define DDRSS_PHY_1135_DATA 0x00000000 +#define DDRSS_PHY_1136_DATA 0x00000000 +#define DDRSS_PHY_1137_DATA 0x00000000 +#define DDRSS_PHY_1138_DATA 0x00000000 +#define DDRSS_PHY_1139_DATA 0x00000000 +#define DDRSS_PHY_1140_DATA 0x00000000 +#define DDRSS_PHY_1141_DATA 0x00000000 +#define DDRSS_PHY_1142_DATA 0x00000000 +#define DDRSS_PHY_1143_DATA 0x00000000 +#define DDRSS_PHY_1144_DATA 0x00000000 +#define DDRSS_PHY_1145_DATA 0x00000000 +#define DDRSS_PHY_1146_DATA 0x00000000 +#define DDRSS_PHY_1147_DATA 0x00000000 +#define DDRSS_PHY_1148_DATA 0x00000000 +#define DDRSS_PHY_1149_DATA 0x00000000 +#define DDRSS_PHY_1150_DATA 0x00000000 +#define DDRSS_PHY_1151_DATA 0x00000000 +#define DDRSS_PHY_1152_DATA 0x00000000 +#define DDRSS_PHY_1153_DATA 0x00000000 +#define DDRSS_PHY_1154_DATA 0x00000000 +#define DDRSS_PHY_1155_DATA 0x00000000 +#define DDRSS_PHY_1156_DATA 0x00000000 +#define DDRSS_PHY_1157_DATA 0x00000000 +#define DDRSS_PHY_1158_DATA 0x00000000 +#define DDRSS_PHY_1159_DATA 0x00000000 +#define DDRSS_PHY_1160_DATA 0x00000000 +#define DDRSS_PHY_1161_DATA 0x00000000 +#define DDRSS_PHY_1162_DATA 0x00000000 +#define DDRSS_PHY_1163_DATA 0x00000000 +#define DDRSS_PHY_1164_DATA 0x00000000 +#define DDRSS_PHY_1165_DATA 0x00000000 +#define DDRSS_PHY_1166_DATA 0x00000000 +#define DDRSS_PHY_1167_DATA 0x00000000 +#define DDRSS_PHY_1168_DATA 0x00000000 +#define DDRSS_PHY_1169_DATA 0x00000000 +#define DDRSS_PHY_1170_DATA 0x00000000 +#define DDRSS_PHY_1171_DATA 0x00000000 +#define DDRSS_PHY_1172_DATA 0x00000000 +#define DDRSS_PHY_1173_DATA 0x00000000 +#define DDRSS_PHY_1174_DATA 0x00000000 +#define DDRSS_PHY_1175_DATA 0x00000000 +#define DDRSS_PHY_1176_DATA 0x00000000 +#define DDRSS_PHY_1177_DATA 0x00000000 +#define DDRSS_PHY_1178_DATA 0x00000000 +#define DDRSS_PHY_1179_DATA 0x00000000 +#define DDRSS_PHY_1180_DATA 0x00000000 +#define DDRSS_PHY_1181_DATA 0x00000000 +#define DDRSS_PHY_1182_DATA 0x00000000 +#define DDRSS_PHY_1183_DATA 0x00000000 +#define DDRSS_PHY_1184_DATA 0x00000000 +#define DDRSS_PHY_1185_DATA 0x00000000 +#define DDRSS_PHY_1186_DATA 0x00000000 +#define DDRSS_PHY_1187_DATA 0x00000000 +#define DDRSS_PHY_1188_DATA 0x00000000 +#define DDRSS_PHY_1189_DATA 0x00000000 +#define DDRSS_PHY_1190_DATA 0x00000000 +#define DDRSS_PHY_1191_DATA 0x00000000 +#define DDRSS_PHY_1192_DATA 0x00000000 +#define DDRSS_PHY_1193_DATA 0x00000000 +#define DDRSS_PHY_1194_DATA 0x00000000 +#define DDRSS_PHY_1195_DATA 0x00000000 +#define DDRSS_PHY_1196_DATA 0x00000000 +#define DDRSS_PHY_1197_DATA 0x00000000 +#define DDRSS_PHY_1198_DATA 0x00000000 +#define DDRSS_PHY_1199_DATA 0x00000000 +#define DDRSS_PHY_1200_DATA 0x00000000 +#define DDRSS_PHY_1201_DATA 0x00000000 +#define DDRSS_PHY_1202_DATA 0x00000000 +#define DDRSS_PHY_1203_DATA 0x00000000 +#define DDRSS_PHY_1204_DATA 0x00000000 +#define DDRSS_PHY_1205_DATA 0x00000000 +#define DDRSS_PHY_1206_DATA 0x00000000 +#define DDRSS_PHY_1207_DATA 0x00000000 +#define DDRSS_PHY_1208_DATA 0x00000000 +#define DDRSS_PHY_1209_DATA 0x00000000 +#define DDRSS_PHY_1210_DATA 0x00000000 +#define DDRSS_PHY_1211_DATA 0x00000000 +#define DDRSS_PHY_1212_DATA 0x00000000 +#define DDRSS_PHY_1213_DATA 0x00000000 +#define DDRSS_PHY_1214_DATA 0x00000000 +#define DDRSS_PHY_1215_DATA 0x00000000 +#define DDRSS_PHY_1216_DATA 0x00000000 +#define DDRSS_PHY_1217_DATA 0x00000000 +#define DDRSS_PHY_1218_DATA 0x00000000 +#define DDRSS_PHY_1219_DATA 0x00000000 +#define DDRSS_PHY_1220_DATA 0x00000000 +#define DDRSS_PHY_1221_DATA 0x00000000 +#define DDRSS_PHY_1222_DATA 0x00000000 +#define DDRSS_PHY_1223_DATA 0x00000000 +#define DDRSS_PHY_1224_DATA 0x00000000 +#define DDRSS_PHY_1225_DATA 0x00000000 +#define DDRSS_PHY_1226_DATA 0x00000000 +#define DDRSS_PHY_1227_DATA 0x00000000 +#define DDRSS_PHY_1228_DATA 0x00000000 +#define DDRSS_PHY_1229_DATA 0x00000000 +#define DDRSS_PHY_1230_DATA 0x00000000 +#define DDRSS_PHY_1231_DATA 0x00000000 +#define DDRSS_PHY_1232_DATA 0x00000000 +#define DDRSS_PHY_1233_DATA 0x00000000 +#define DDRSS_PHY_1234_DATA 0x00000000 +#define DDRSS_PHY_1235_DATA 0x00000000 +#define DDRSS_PHY_1236_DATA 0x00000000 +#define DDRSS_PHY_1237_DATA 0x00000000 +#define DDRSS_PHY_1238_DATA 0x00000000 +#define DDRSS_PHY_1239_DATA 0x00000000 +#define DDRSS_PHY_1240_DATA 0x00000000 +#define DDRSS_PHY_1241_DATA 0x00000000 +#define DDRSS_PHY_1242_DATA 0x00000000 +#define DDRSS_PHY_1243_DATA 0x00000000 +#define DDRSS_PHY_1244_DATA 0x00000000 +#define DDRSS_PHY_1245_DATA 0x00000000 +#define DDRSS_PHY_1246_DATA 0x00000000 +#define DDRSS_PHY_1247_DATA 0x00000000 +#define DDRSS_PHY_1248_DATA 0x00000000 +#define DDRSS_PHY_1249_DATA 0x00000000 +#define DDRSS_PHY_1250_DATA 0x00000000 +#define DDRSS_PHY_1251_DATA 0x00000000 +#define DDRSS_PHY_1252_DATA 0x00000000 +#define DDRSS_PHY_1253_DATA 0x00000000 +#define DDRSS_PHY_1254_DATA 0x00000000 +#define DDRSS_PHY_1255_DATA 0x00000000 +#define DDRSS_PHY_1256_DATA 0x00000000 +#define DDRSS_PHY_1257_DATA 0x00000000 +#define DDRSS_PHY_1258_DATA 0x00000000 +#define DDRSS_PHY_1259_DATA 0x00000000 +#define DDRSS_PHY_1260_DATA 0x00000000 +#define DDRSS_PHY_1261_DATA 0x00000000 +#define DDRSS_PHY_1262_DATA 0x00000000 +#define DDRSS_PHY_1263_DATA 0x00000000 +#define DDRSS_PHY_1264_DATA 0x00000000 +#define DDRSS_PHY_1265_DATA 0x00000000 +#define DDRSS_PHY_1266_DATA 0x00000000 +#define DDRSS_PHY_1267_DATA 0x00000000 +#define DDRSS_PHY_1268_DATA 0x00000000 +#define DDRSS_PHY_1269_DATA 0x00000000 +#define DDRSS_PHY_1270_DATA 0x00000000 +#define DDRSS_PHY_1271_DATA 0x00000000 +#define DDRSS_PHY_1272_DATA 0x00000000 +#define DDRSS_PHY_1273_DATA 0x00000000 +#define DDRSS_PHY_1274_DATA 0x00000000 +#define DDRSS_PHY_1275_DATA 0x00000000 +#define DDRSS_PHY_1276_DATA 0x00000000 +#define DDRSS_PHY_1277_DATA 0x00000000 +#define DDRSS_PHY_1278_DATA 0x00000000 +#define DDRSS_PHY_1279_DATA 0x00000000 +#define DDRSS_PHY_1280_DATA 0x00000000 +#define DDRSS_PHY_1281_DATA 0x00000100 +#define DDRSS_PHY_1282_DATA 0x00000000 +#define DDRSS_PHY_1283_DATA 0x00000000 +#define DDRSS_PHY_1284_DATA 0x00000000 +#define DDRSS_PHY_1285_DATA 0x00000000 +#define DDRSS_PHY_1286_DATA 0x00050000 +#define DDRSS_PHY_1287_DATA 0x04000100 +#define DDRSS_PHY_1288_DATA 0x00000055 +#define DDRSS_PHY_1289_DATA 0x00000000 +#define DDRSS_PHY_1290_DATA 0x00000000 +#define DDRSS_PHY_1291_DATA 0x00000000 +#define DDRSS_PHY_1292_DATA 0x00000000 +#define DDRSS_PHY_1293_DATA 0x01002000 +#define DDRSS_PHY_1294_DATA 0x00004001 +#define DDRSS_PHY_1295_DATA 0x00020028 +#define DDRSS_PHY_1296_DATA 0x00010100 +#define DDRSS_PHY_1297_DATA 0x00000001 +#define DDRSS_PHY_1298_DATA 0x00000000 +#define DDRSS_PHY_1299_DATA 0x0F0F0E06 +#define DDRSS_PHY_1300_DATA 0x00010101 +#define DDRSS_PHY_1301_DATA 0x010F0004 +#define DDRSS_PHY_1302_DATA 0x00000000 +#define DDRSS_PHY_1303_DATA 0x00000000 +#define DDRSS_PHY_1304_DATA 0x00000064 +#define DDRSS_PHY_1305_DATA 0x00000000 +#define DDRSS_PHY_1306_DATA 0x00000000 +#define DDRSS_PHY_1307_DATA 0x01020103 +#define DDRSS_PHY_1308_DATA 0x0F020102 +#define DDRSS_PHY_1309_DATA 0x03030303 +#define DDRSS_PHY_1310_DATA 0x03030303 +#define DDRSS_PHY_1311_DATA 0x00040000 +#define DDRSS_PHY_1312_DATA 0x00004201 +#define DDRSS_PHY_1313_DATA 0x00000000 +#define DDRSS_PHY_1314_DATA 0x00000000 +#define DDRSS_PHY_1315_DATA 0x00000000 +#define DDRSS_PHY_1316_DATA 0x00000000 +#define DDRSS_PHY_1317_DATA 0x00000000 +#define DDRSS_PHY_1318_DATA 0x00000000 +#define DDRSS_PHY_1319_DATA 0x07070001 +#define DDRSS_PHY_1320_DATA 0x00005400 +#define DDRSS_PHY_1321_DATA 0x000040A2 +#define DDRSS_PHY_1322_DATA 0x00024410 +#define DDRSS_PHY_1323_DATA 0x00004410 +#define DDRSS_PHY_1324_DATA 0x00004410 +#define DDRSS_PHY_1325_DATA 0x00004410 +#define DDRSS_PHY_1326_DATA 0x00004410 +#define DDRSS_PHY_1327_DATA 0x00004410 +#define DDRSS_PHY_1328_DATA 0x00004410 +#define DDRSS_PHY_1329_DATA 0x00004410 +#define DDRSS_PHY_1330_DATA 0x00004410 +#define DDRSS_PHY_1331_DATA 0x00004410 +#define DDRSS_PHY_1332_DATA 0x00000000 +#define DDRSS_PHY_1333_DATA 0x00000046 +#define DDRSS_PHY_1334_DATA 0x00000400 +#define DDRSS_PHY_1335_DATA 0x00000008 +#define DDRSS_PHY_1336_DATA 0x00000000 +#define DDRSS_PHY_1337_DATA 0x00000000 +#define DDRSS_PHY_1338_DATA 0x00000000 +#define DDRSS_PHY_1339_DATA 0x00000000 +#define DDRSS_PHY_1340_DATA 0x00000000 +#define DDRSS_PHY_1341_DATA 0x03000000 +#define DDRSS_PHY_1342_DATA 0x00000000 +#define DDRSS_PHY_1343_DATA 0x00000000 +#define DDRSS_PHY_1344_DATA 0x00000000 +#define DDRSS_PHY_1345_DATA 0x04102006 +#define DDRSS_PHY_1346_DATA 0x00041020 +#define DDRSS_PHY_1347_DATA 0x01C98C98 +#define DDRSS_PHY_1348_DATA 0x3F400000 +#define DDRSS_PHY_1349_DATA 0x3F3F1F3F +#define DDRSS_PHY_1350_DATA 0x0000001F +#define DDRSS_PHY_1351_DATA 0x00000000 +#define DDRSS_PHY_1352_DATA 0x00000000 +#define DDRSS_PHY_1353_DATA 0x00000000 +#define DDRSS_PHY_1354_DATA 0x00000001 +#define DDRSS_PHY_1355_DATA 0x00000000 +#define DDRSS_PHY_1356_DATA 0x00000000 +#define DDRSS_PHY_1357_DATA 0x00000000 +#define DDRSS_PHY_1358_DATA 0x00000000 +#define DDRSS_PHY_1359_DATA 0x76543210 +#define DDRSS_PHY_1360_DATA 0x00000098 +#define DDRSS_PHY_1361_DATA 0x00000000 +#define DDRSS_PHY_1362_DATA 0x00000000 +#define DDRSS_PHY_1363_DATA 0x00000000 +#define DDRSS_PHY_1364_DATA 0x00040700 +#define DDRSS_PHY_1365_DATA 0x00000000 +#define DDRSS_PHY_1366_DATA 0x00000000 +#define DDRSS_PHY_1367_DATA 0x00000000 +#define DDRSS_PHY_1368_DATA 0x00000002 +#define DDRSS_PHY_1369_DATA 0x00000100 +#define DDRSS_PHY_1370_DATA 0x00000000 +#define DDRSS_PHY_1371_DATA 0x00000FC3 +#define DDRSS_PHY_1372_DATA 0x00020002 +#define DDRSS_PHY_1373_DATA 0x00000000 +#define DDRSS_PHY_1374_DATA 0x00001142 +#define DDRSS_PHY_1375_DATA 0x03020400 +#define DDRSS_PHY_1376_DATA 0x00000080 +#define DDRSS_PHY_1377_DATA 0x03900390 +#define DDRSS_PHY_1378_DATA 0x03900390 +#define DDRSS_PHY_1379_DATA 0x03900390 +#define DDRSS_PHY_1380_DATA 0x03900390 +#define DDRSS_PHY_1381_DATA 0x03900390 +#define DDRSS_PHY_1382_DATA 0x03900390 +#define DDRSS_PHY_1383_DATA 0x00000300 +#define DDRSS_PHY_1384_DATA 0x00000300 +#define DDRSS_PHY_1385_DATA 0x00000300 +#define DDRSS_PHY_1386_DATA 0x00000300 +#define DDRSS_PHY_1387_DATA 0x31823FC7 +#define DDRSS_PHY_1388_DATA 0x00000000 +#define DDRSS_PHY_1389_DATA 0x0C000D3F +#define DDRSS_PHY_1390_DATA 0x30000D3F +#define DDRSS_PHY_1391_DATA 0x300D3F11 +#define DDRSS_PHY_1392_DATA 0x01990000 +#define DDRSS_PHY_1393_DATA 0x000D3FCC +#define DDRSS_PHY_1394_DATA 0x00000C11 +#define DDRSS_PHY_1395_DATA 0x300D3F11 +#define DDRSS_PHY_1396_DATA 0x01990000 +#define DDRSS_PHY_1397_DATA 0x300C3F11 +#define DDRSS_PHY_1398_DATA 0x01990000 +#define DDRSS_PHY_1399_DATA 0x300C3F11 +#define DDRSS_PHY_1400_DATA 0x01990000 +#define DDRSS_PHY_1401_DATA 0x300D3F11 +#define DDRSS_PHY_1402_DATA 0x01990000 +#define DDRSS_PHY_1403_DATA 0x300D3F11 +#define DDRSS_PHY_1404_DATA 0x01990000 +#define DDRSS_PHY_1405_DATA 0x20040004 diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi new file mode 100644 index 00000000000..f8c04e8a300 --- /dev/null +++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * https://beagleboard.org/play + * + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation + */ + +#include "k3-am625-sk-binman.dtsi" + +/ { + chosen { + tick-timer = &main_timer0; + }; + + memory@80000000 { + bootph-pre-ram; + }; + + /* Keep the LEDs on by default to indicate life */ + leds { + bootph-pre-ram; + led-0 { + default-state = "on"; + bootph-pre-ram; + }; + + led-1 { + default-state = "on"; + bootph-pre-ram; + }; + + led-2 { + default-state = "on"; + bootph-pre-ram; + }; + + led-3 { + default-state = "on"; + bootph-pre-ram; + }; + + led-4 { + default-state = "on"; + bootph-pre-ram; + }; + }; +}; + +&cbass_main { + bootph-pre-ram; +}; + +&main_timer0 { + clock-frequency = <25000000>; + bootph-pre-ram; +}; + +&dmss { + bootph-pre-ram; +}; + +&secure_proxy_main { + bootph-pre-ram; +}; + +&dmsc { + bootph-pre-ram; +}; + +&k3_pds { + bootph-pre-ram; +}; + +&k3_clks { + bootph-pre-ram; +}; + +&k3_reset { + bootph-pre-ram; +}; + +&dmsc { + bootph-pre-ram; + k3_sysreset: sysreset-controller { + compatible = "ti,sci-sysreset"; + bootph-pre-ram; + }; +}; + +&wkup_conf { + bootph-pre-ram; +}; + +&chipid { + bootph-pre-ram; +}; + +&main_pmx0 { + bootph-pre-ram; +}; + +&main_uart0 { + bootph-pre-ram; +}; + +&console_pins_default { + bootph-pre-ram; +}; + +&cbass_mcu { + bootph-pre-ram; +}; + +&cbass_wakeup { + bootph-pre-ram; +}; + +&mcu_pmx0 { + bootph-pre-ram; +}; + +&main_i2c0 { + bootph-pre-ram; +}; + +&local_i2c_pins_default { + bootph-pre-ram; +}; + +&gpio0_pins_default { + bootph-pre-ram; +}; + +&main_gpio0 { + bootph-pre-ram; +}; + +&main_gpio1 { + bootph-pre-ram; +}; + +&sdhci0 { + /* EMMC */ + bootph-pre-ram; +}; + +&emmc_pins_default { + bootph-pre-ram; +}; + +&sd_pins_default { + bootph-pre-ram; + /* Force to use SDCD card detect pin */ + pinctrl-single,pins = < + AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ + AM62X_IOPAD(0x0234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ + AM62X_IOPAD(0x0230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ + AM62X_IOPAD(0x022c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ + AM62X_IOPAD(0x0228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ + AM62X_IOPAD(0x0224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ + AM62X_IOPAD(0x0240, PIN_INPUT, 0) /* (D17) MMC1_SDCD.MMC1_SDCD */ + >; +}; + +&tps65219 { + bootph-pre-ram; +}; + +&sdhci1 { + bootph-pre-ram; +}; + +#ifdef CONFIG_TARGET_AM625_A53_EVM + +#define SPL_AM625_BEAGLEPLAY_DTB "spl/dts/k3-am625-beagleplay.dtb" +#define AM625_BEAGLEPLAY_DTB "arch/arm/dts/k3-am625-beagleplay.dtb" + +&spl_am625_sk_dtb { + filename = SPL_AM625_BEAGLEPLAY_DTB; +}; + +&am625_sk_dtb { + filename = AM625_BEAGLEPLAY_DTB; +}; + +&spl_am625_sk_dtb_unsigned { + filename = SPL_AM625_BEAGLEPLAY_DTB; +}; + +&am625_sk_dtb_unsigned { + filename = AM625_BEAGLEPLAY_DTB; +}; + +#endif diff --git a/arch/arm/dts/k3-am625-beagleplay.dts b/arch/arm/dts/k3-am625-beagleplay.dts new file mode 100644 index 00000000000..589bf998bc5 --- /dev/null +++ b/arch/arm/dts/k3-am625-beagleplay.dts @@ -0,0 +1,758 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * https://beagleplay.org/ + * + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation + */ + +/dts-v1/; + +#include +#include +#include +#include "k3-am625.dtsi" + +/ { + compatible = "beagle,am625-beagleplay", "ti,am625"; + model = "BeagleBoard.org BeaglePlay"; + + aliases { + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; + gpio0 = &main_gpio0; + gpio1 = &main_gpio1; + gpio2 = &mcu_gpio0; + i2c0 = &main_i2c0; + i2c1 = &main_i2c1; + i2c2 = &main_i2c2; + i2c3 = &main_i2c3; + i2c4 = &wkup_i2c0; + i2c5 = &mcu_i2c0; + mdio-gpio0 = &mdio0; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + mmc2 = &sdhci2; + rtc0 = &rtc; + serial0 = &main_uart5; + serial1 = &main_uart6; + serial2 = &main_uart0; + usb0 = &usb0; + usb1 = &usb1; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops: ramoops@9ca00000 { + compatible = "ramoops"; + reg = <0x00 0x9c700000 0x00 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x00>; + pmsg-size = <0x8000>; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9db00000 0x00 0xc00000>; + no-map; + }; + }; + + vsys_5v0: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "vsys_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_3v3: regulator-2 { + /* output of TLV62595DMQR-U12 */ + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vsys_5v0>; + regulator-always-on; + regulator-boot-on; + }; + + wlan_en: regulator-3 { + /* OUTPUT of SN74AVC2T244DQMR */ + compatible = "regulator-fixed"; + regulator-name = "wlan_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + regulator-always-on; + vin-supply = <&vdd_3v3>; + gpio = <&main_gpio0 38 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_en_pins_default>; + }; + + vdd_3v3_sd: regulator-4 { + /* output of TPS22918DBVR-U21 */ + pinctrl-names = "default"; + pinctrl-0 = <&vdd_3v3_sd_pins_default>; + + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-always-on; + vin-supply = <&vdd_3v3>; + gpio = <&main_gpio1 19 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv: regulator-5 { + compatible = "regulator-gpio"; + regulator-name = "sd_hs200_switch"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&ldo1_reg>; + gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + gpios = <&main_gpio0 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + default-state = "off"; + }; + + led-1 { + gpios = <&main_gpio0 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + function = LED_FUNCTION_DISK_ACTIVITY; + default-state = "keep"; + }; + + led-2 { + gpios = <&main_gpio0 5 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_CPU; + }; + + led-3 { + gpios = <&main_gpio0 6 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_LAN; + }; + + led-4 { + gpios = <&main_gpio0 9 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_WLAN; + }; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&usr_button_pins_default>; + + usr: button-usr { + label = "User Key"; + linux,code = ; + gpios = <&main_gpio0 18 GPIO_ACTIVE_LOW>; + }; + + }; + + /* Workaround for errata i2329 - just use mdio bitbang */ + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_pins_default>; + gpios = <&main_gpio0 86 GPIO_ACTIVE_HIGH>, /* MDC */ + <&main_gpio0 85 GPIO_ACTIVE_HIGH>; /* MDIO */ + #address-cells = <1>; + #size-cells = <0>; + + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + }; + + cpsw3g_phy1: ethernet-phy@1 { + reg = <1>; + reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <25>; + reset-deassert-us = <60000>; /* T2 */ + }; + }; +}; + +&main_pmx0 { + gpio0_pins_default: gpio0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0004, PIN_INPUT, 7) /* (G25) OSPI0_LBCLKO.GPIO0_1 */ + AM62X_IOPAD(0x0008, PIN_INPUT, 7) /* (J24) OSPI0_DQS.GPIO0_2 */ + AM62X_IOPAD(0x000c, PIN_INPUT, 7) /* (E25) OSPI0_D0.GPIO0_3 */ + AM62X_IOPAD(0x0010, PIN_INPUT, 7) /* (G24) OSPI0_D1.GPIO0_4 */ + AM62X_IOPAD(0x0014, PIN_INPUT, 7) /* (F25) OSPI0_D2.GPIO0_5 */ + AM62X_IOPAD(0x0018, PIN_INPUT, 7) /* (F24) OSPI0_D3.GPIO0_6 */ + AM62X_IOPAD(0x0024, PIN_INPUT, 7) /* (H25) OSPI0_D6.GPIO0_9 */ + AM62X_IOPAD(0x0028, PIN_INPUT, 7) /* (J22) OSPI0_D7.GPIO0_10 */ + AM62X_IOPAD(0x002c, PIN_INPUT, 7) /* (F23) OSPI0_CSn0.GPIO0_11 */ + AM62X_IOPAD(0x0030, PIN_INPUT, 7) /* (G21) OSPI0_CSn1.GPIO0_12 */ + AM62X_IOPAD(0x0034, PIN_INPUT, 7) /* (H21) OSPI0_CSn2.GPIO0_13 */ + AM62X_IOPAD(0x0038, PIN_INPUT, 7) /* (E24) OSPI0_CSn3.GPIO0_14 */ + AM62X_IOPAD(0x00a4, PIN_INPUT, 7) /* (M22) GPMC0_DIR.GPIO0_40 */ + AM62X_IOPAD(0x00ac, PIN_INPUT, 7) /* (L21) GPMC0_CSn1.GPIO0_42 */ + >; + }; + + vdd_sd_dv_pins_default: vdd-sd-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ + >; + }; + + usr_button_pins_default: usr-button-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0048, PIN_INPUT, 7) /* (N25) GPMC0_AD3.GPIO0_18 */ + >; + }; + + grove_pins_default: grove-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ + AM62X_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ + >; + }; + + local_i2c_pins_default: local-i2c-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ + AM62X_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ + >; + }; + + i2c2_1v8_pins_default: i2c2-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ + AM62X_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ + >; + }; + + mdio0_pins_default: mdio0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0160, PIN_OUTPUT, 7) /* (AD24) MDIO0_MDC.GPIO0_86 */ + AM62X_IOPAD(0x015c, PIN_INPUT, 7) /* (AB22) MDIO0_MDIO.GPIO0_85 */ + >; + }; + + rgmii1_pins_default: rgmii1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x014c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ + AM62X_IOPAD(0x0150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ + AM62X_IOPAD(0x0154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ + AM62X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ + AM62X_IOPAD(0x0148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ + AM62X_IOPAD(0x0144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ + AM62X_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */ + AM62X_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */ + AM62X_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */ + AM62X_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */ + AM62X_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ + AM62X_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ + >; + }; + + emmc_pins_default: emmc-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ + AM62X_IOPAD(0x0218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ + AM62X_IOPAD(0x0214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ + AM62X_IOPAD(0x0210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */ + AM62X_IOPAD(0x020c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */ + AM62X_IOPAD(0x0208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */ + AM62X_IOPAD(0x0204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */ + AM62X_IOPAD(0x0200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */ + AM62X_IOPAD(0x01fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */ + AM62X_IOPAD(0x01f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + + vdd_3v3_sd_pins_default: vdd-3v3-sd-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1_GPIO1_19 */ + >; + }; + + sd_pins_default: sd-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ + AM62X_IOPAD(0x0234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ + AM62X_IOPAD(0x0230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ + AM62X_IOPAD(0x022c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ + AM62X_IOPAD(0x0228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ + AM62X_IOPAD(0x0224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ + AM62X_IOPAD(0x0240, PIN_INPUT, 7) /* (D17) MMC1_SDCD.GPIO1_48 */ + >; + }; + + wifi_pins_default: wifi-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0120, PIN_INPUT, 0) /* (C24) MMC2_CMD */ + AM62X_IOPAD(0x0118, PIN_INPUT, 0) /* (D25) MMC2_CLK */ + AM62X_IOPAD(0x0114, PIN_INPUT, 0) /* (B24) MMC2_DAT0 */ + AM62X_IOPAD(0x0110, PIN_INPUT, 0) /* (C25) MMC2_DAT1 */ + AM62X_IOPAD(0x010c, PIN_INPUT, 0) /* (E23) MMC2_DAT2 */ + AM62X_IOPAD(0x0108, PIN_INPUT, 0) /* (D24) MMC2_DAT3 */ + AM62X_IOPAD(0x0124, PIN_INPUT, 0) /* (A23) MMC2_SDCD */ + AM62X_IOPAD(0x11c, PIN_INPUT, 0) /* (#N/A) MMC2_CLKB */ + >; + }; + + wifi_en_pins_default: wifi-en-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x009c, PIN_OUTPUT, 7) /* (V25) GPMC0_WAIT1.GPIO0_38 */ + >; + }; + + wifi_wlirq_pins_default: wifi-wlirq-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x00a8, PIN_INPUT, 7) /* (M21) GPMC0_CSn0.GPIO0_41 */ + >; + }; + + spe_pins_default: spe-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0168, PIN_INPUT, 1) /* (AE21) RGMII2_TXC.RMII2_CRS_DV */ + AM62X_IOPAD(0x0180, PIN_INPUT, 1) /* (AD23) RGMII2_RXC.RMII2_REF_CLK */ + AM62X_IOPAD(0x0184, PIN_INPUT, 1) /* (AE23) RGMII2_RD0.RMII2_RXD0 */ + AM62X_IOPAD(0x0188, PIN_INPUT, 1) /* (AB20) RGMII2_RD1.RMII2_RXD1 */ + AM62X_IOPAD(0x017c, PIN_INPUT, 1) /* (AD22) RGMII2_RX_CTL.RMII2_RX_ER */ + AM62X_IOPAD(0x016c, PIN_INPUT, 1) /* (Y18) RGMII2_TD0.RMII2_TXD0 */ + AM62X_IOPAD(0x0170, PIN_INPUT, 1) /* (AA18) RGMII2_TD1.RMII2_TXD1 */ + AM62X_IOPAD(0x0164, PIN_INPUT, 1) /* (AA19) RGMII2_TX_CTL.RMII2_TX_EN */ + AM62X_IOPAD(0x018c, PIN_OUTPUT, 7) /* (AC21) RGMII2_RD2.GPIO1_5 */ + AM62X_IOPAD(0x0190, PIN_INPUT, 7) /* (AE22) RGMII2_RD3.GPIO1_6 */ + AM62X_IOPAD(0x01f0, PIN_OUTPUT, 5) /* (A18) EXT_REFCLK1.CLKOUT0 */ + >; + }; + + mikrobus_i2c_pins_default: mikrobus-i2c-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A15) UART0_CTSn.I2C3_SCL */ + AM62X_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (B15) UART0_RTSn.I2C3_SDA */ + >; + }; + + mikrobus_uart_pins_default: mikrobus-uart-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01d8, PIN_INPUT, 1) /* (C15) MCAN0_TX.UART5_RXD */ + AM62X_IOPAD(0x01dc, PIN_OUTPUT, 1) /* (E15) MCAN0_RX.UART5_TXD */ + >; + }; + + mikrobus_spi_pins_default: mikrobus-spi-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01b0, PIN_INPUT, 1) /* (A20) MCASP0_ACLKR.SPI2_CLK */ + AM62X_IOPAD(0x01ac, PIN_INPUT, 1) /* (E19) MCASP0_AFSR.SPI2_CS0 */ + AM62X_IOPAD(0x0194, PIN_INPUT, 1) /* (B19) MCASP0_AXR3.SPI2_D0 */ + AM62X_IOPAD(0x0198, PIN_INPUT, 1) /* (A19) MCASP0_AXR2.SPI2_D1 */ + >; + }; + + mikrobus_gpio_pins_default: mikrobus-gpio-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x019c, PIN_INPUT, 7) /* (B18) MCASP0_AXR1.GPIO1_9 */ + AM62X_IOPAD(0x01a0, PIN_INPUT, 7) /* (E18) MCASP0_AXR0.GPIO1_10 */ + AM62X_IOPAD(0x01a8, PIN_INPUT, 7) /* (D20) MCASP0_AFSX.GPIO1_12 */ + >; + }; + + console_pins_default: console-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ + AM62X_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ + >; + }; + + wifi_debug_uart_pins_default: wifi-debug-uart-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x001c, PIN_INPUT, 3) /* (J23) OSPI0_D4.UART6_RXD */ + AM62X_IOPAD(0x0020, PIN_OUTPUT, 3) /* (J25) OSPI0_D5.UART6_TXD */ + >; + }; + + usb1_pins_default: usb1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0258, PIN_INPUT, 0) /* (F18) USB1_DRVVBUS */ + >; + }; + + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (D16) EXTINTn */ + >; + }; +}; + +&mcu_pmx0 { + i2c_qwiic_pins_default: i2c-qwiic-default-pins { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0044, PIN_INPUT, 0) /* (A8) MCU_I2C0_SCL */ + AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */ + >; + }; + + gbe_pmx_obsclk: gbe-pmx-clk-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0004, PIN_OUTPUT, 1) /* (B8) MCU_SPI0_CS1.MCU_OBSCLK0 */ + >; + }; + + i2c_csi_pins_default: i2c-csi-default-pins { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x004c, PIN_INPUT_PULLUP, 0) /* (B9) WKUP_I2C0_SCL */ + AM62X_MCU_IOPAD(0x0050, PIN_INPUT_PULLUP, 0) /* (A9) WKUP_I2C0_SDA */ + >; + }; + + wifi_32k_clk: mcu-clk-out-default-pins { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (A12) WKUP_CLKOUT0 */ + >; + }; +}; + +&a53_opp_table { + /* Requires VDD_CORE to be at 0.85V */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + }; +}; + +&wkup_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_csi_pins_default>; + clock-frequency = <400000>; + /* Enable with overlay for camera sensor */ +}; + +&mcu_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_qwiic_pins_default>; + clock-frequency = <100000>; + status = "okay"; +}; + +&usbss0 { + ti,vbus-divider; + status = "okay"; +}; + +&usb0 { + dr_mode = "peripheral"; +}; + +&usbss1 { + ti,vbus-divider; + status = "okay"; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins_default>; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins_default>, <&spe_pins_default>, + <&gbe_pmx_obsclk>; + assigned-clocks = <&k3_clks 157 70>, <&k3_clks 157 20>; + assigned-clock-parents = <&k3_clks 157 72>, <&k3_clks 157 22>; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw_port2 { + phy-mode = "rmii"; + phy-handle = <&cpsw3g_phy1>; +}; + +&cpsw3g_mdio { + /* Workaround for errata i2329 - Use mdio bitbang */ + status = "disabled"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_pins_default>; + gpio-line-names = "BL_EN_3V3", "SPE_PO_EN", "RTC_INT", /* 0-2 */ + "USR0", "USR1", "USR2", "USR3", "", "", "USR4", /* 3-9 */ + "EEPROM_WP", /* 10 */ + "CSI2_CAMERA_GPIO1", "CSI2_CAMERA_GPIO2", /* 11-12 */ + "CC1352P7_BOOT", "CC1352P7_RSTN", "", "", "", /* 13-17 */ + "USR_BUTTON", "", "", "", "", "", "", "", "", /* 18-26 */ + "", "", "", "", "", "", "", "", "", "HDMI_INT", /* 27-36 */ + "", "VDD_WLAN_EN", "", "", "WL_IRQ", "GBE_INTN",/* 37-42 */ + "", "", "", "", "", "", "", "", "", "", "", "", /* 43-54 */ + "", "", "", "", "", "", "", "", "", "", "", "", /* 55-66 */ + "", "", "", "", "", "", "", "", "", "", "", "", /* 67-78 */ + "", "", "", "", "", "", /* 79-84 */ + "BITBANG_MDIO_DATA", "BITBANG_MDIO_CLK", /* 85-86 */ + "", "", "", "", ""; /* 87-91 */ +}; + +&main_gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&mikrobus_gpio_pins_default>; + gpio-line-names = "", "", "", "", "", /* 0-4 */ + "SPE_RSTN", "SPE_INTN", "MIKROBUS_GPIO1_7", /* 5-7 */ + "MIKROBUS_GPIO1_8", "MIKROBUS_GPIO1_9", /* 8-9 */ + "MIKROBUS_GPIO1_10", "MIKROBUS_GPIO1_11", /* 10-11 */ + "MIKROBUS_GPIO1_12", "MIKROBUS_W1_GPIO0", /* 12-13 */ + "MIKROBUS_GPIO1_14", /* 14 */ + "", "", "", "", "VDD_3V3_SD", "", "", /* 15-21 */ + "MIKROBUS_GPIO1_22", "MIKROBUS_GPIO1_23", /* 22-23 */ + "MIKROBUS_GPIO1_24", "MIKROBUS_GPIO1_25", /* 24-25 */ + "", "", "", "", "", "", "", "", "", "", "", "", /* 26-37 */ + "", "", "", "", "", "", "", "", "", "", /* 38-47 */ + "SD_CD", "SD_VOLT_SEL", "", ""; /* 48-51 */ +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&local_i2c_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + + rtc: rtc@68 { + compatible = "ti,bq32000"; + reg = <0x68>; + interrupt-parent = <&main_gpio0>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + }; + + tps65219: pmic@30 { + compatible = "ti,tps65219"; + reg = <0x30>; + buck1-supply = <&vsys_5v0>; + buck2-supply = <&vsys_5v0>; + buck3-supply = <&vsys_5v0>; + ldo1-supply = <&vdd_3v3>; + ldo2-supply = <&buck2_reg>; + ldo3-supply = <&vdd_3v3>; + ldo4-supply = <&vdd_3v3>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&gic500>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + system-power-controller; + ti,power-button; + + regulators { + buck1_reg: buck1 { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + buck2_reg: buck2 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck3_reg: buck3 { + regulator-name = "VDD_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + /* + * Regulator is left as is unused, vdd_sd + * is controlled via GPIO with bypass config + * as per the NVM configuration + */ + regulator-name = "VDD_SD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allow-bypass; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + regulator-name = "VDDA_0V85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + regulator-name = "VDDA_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: ldo4 { + regulator-name = "VDD_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&grove_pins_default>; + clock-frequency = <100000>; + status = "okay"; +}; + +&main_i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_1v8_pins_default>; + clock-frequency = <100000>; + status = "okay"; +}; + +&main_i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&mikrobus_i2c_pins_default>; + clock-frequency = <400000>; + status = "okay"; +}; + +&main_spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&mikrobus_spi_pins_default>; + status = "okay"; +}; + +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; + status = "okay"; +}; + +&sdhci1 { + /* SD/MMC */ + pinctrl-names = "default"; + pinctrl-0 = <&sd_pins_default>; + + vmmc-supply = <&vdd_3v3_sd>; + vqmmc-supply = <&vdd_sd_dv>; + ti,driver-strength-ohm = <50>; + disable-wp; + cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>; + cd-debounce-delay-ms = <100>; + ti,fails-without-test-cd; + status = "okay"; +}; + +&sdhci2 { + vmmc-supply = <&wlan_en>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pins_default>, <&wifi_32k_clk>; + bus-width = <4>; + non-removable; + ti,fails-without-test-cd; + cap-power-off-card; + keep-power-in-suspend; + ti,driver-strength-ohm = <50>; + assigned-clocks = <&k3_clks 157 158>; + assigned-clock-parents = <&k3_clks 157 160>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,wl1807"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_wlirq_pins_default>; + interrupt-parent = <&main_gpio0>; + interrupts = <41 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&console_pins_default>; + status = "okay"; +}; + +&main_uart1 { + /* Main UART1 is used by TIFS firmware */ + status = "reserved"; +}; + +&main_uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&mikrobus_uart_pins_default>; + status = "okay"; +}; + +&main_uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_debug_uart_pins_default>; + status = "okay"; +}; diff --git a/arch/arm/dts/k3-am625-r5-beagleplay.dts b/arch/arm/dts/k3-am625-r5-beagleplay.dts new file mode 100644 index 00000000000..9c9d0570592 --- /dev/null +++ b/arch/arm/dts/k3-am625-r5-beagleplay.dts @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * https://beagleboard.org/play + * + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation + */ + +#include "k3-am625-beagleplay.dts" +#include "k3-am625-beagleplay-ddr4-1600MTs.dtsi" +#include "k3-am62-ddr.dtsi" + +#include "k3-am625-beagleplay-u-boot.dtsi" + +/ { + aliases { + remoteproc0 = &sysctrler; + remoteproc1 = &a53_0; + }; + + a53_0: a53@0 { + compatible = "ti,am654-rproc"; + reg = <0x00 0x00a90000 0x00 0x10>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 135 0>; + clocks = <&k3_clks 61 0>; + assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + assigned-clock-parents = <&k3_clks 61 2>; + assigned-clock-rates = <200000000>, <1250000000>; + ti,sci = <&dmsc>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + bootph-pre-ram; + }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <36>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_main 22>, + <&secure_proxy_main 23>; + bootph-pre-ram; + }; +}; + +&dmsc { + mboxes= <&secure_proxy_main 0>, + <&secure_proxy_main 1>, + <&secure_proxy_main 0>; + mbox-names = "rx", "tx", "notify"; + ti,host-id = <35>; + ti,secure-host; +}; + +&mcu_esm { + bootph-pre-ram; +}; + +&secure_proxy_sa3 { + bootph-pre-ram; + /* We require this for boot handshake */ + status = "okay"; +}; + +&cbass_main { + sysctrler: sysctrler { + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>; + mbox-names = "tx", "rx", "boot_notify"; + bootph-pre-ram; + }; +}; + +&main_esm { + bootph-pre-ram; +}; + +&main_pktdma { + ti,sci = <&dm_tifs>; +}; + +&main_bcdma { + ti,sci = <&dm_tifs>; +}; diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi index a35d6418c25..41277bf4bfd 100644 --- a/arch/arm/dts/k3-am625-sk-binman.dtsi +++ b/arch/arm/dts/k3-am625-sk-binman.dtsi @@ -389,7 +389,7 @@ type = "flat_dt"; arch = "arm"; compression = "none"; - blob { + spl_am625_sk_dtb_unsigned: blob { filename = SPL_AM625_SK_DTB; }; }; @@ -438,7 +438,7 @@ type = "flat_dt"; arch = "arm"; compression = "none"; - blob { + am625_sk_dtb_unsigned: blob { filename = AM625_SK_DTB; }; hash { diff --git a/arch/arm/dts/k3-am65-iot2050-common.dtsi b/arch/arm/dts/k3-am65-iot2050-common.dtsi index 65da226847f..b6135b849f1 100644 --- a/arch/arm/dts/k3-am65-iot2050-common.dtsi +++ b/arch/arm/dts/k3-am65-iot2050-common.dtsi @@ -64,6 +64,12 @@ alignment = <0x1000>; no-map; }; + + /* To reserve the power-on(PON) reason for watchdog reset */ + wdt_reset_memory_region: wdt-memory@a2200000 { + reg = <0x00 0xa2200000 0x00 0x00001000>; + no-map; + }; }; leds { @@ -720,6 +726,11 @@ mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; }; +&mcu_rti1 { + memory-region = <&wdt_reset_memory_region>; + +}; + &icssg0_mdio { status = "disabled"; }; diff --git a/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi index 5a6f9b11b8e..a0285ce0520 100644 --- a/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi +++ b/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi @@ -1,9 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ - * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.9.1 - * This file was generated on 07/17/2022 -*/ + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.10.0 + * This file was generated on 04/12/2023 + */ #define DDRSS_PLL_FHS_CNT 10 #define DDRSS_PLL_FREQUENCY_0 27500000 @@ -54,11 +54,11 @@ #define DDRSS_CTL_41_DATA 0x1B60008B #define DDRSS_CTL_42_DATA 0x2000422B #define DDRSS_CTL_43_DATA 0x000A0A09 -#define DDRSS_CTL_44_DATA 0x0400078A +#define DDRSS_CTL_44_DATA 0x040003C5 #define DDRSS_CTL_45_DATA 0x1E161104 -#define DDRSS_CTL_46_DATA 0x10012458 +#define DDRSS_CTL_46_DATA 0x1000922C #define DDRSS_CTL_47_DATA 0x1E161110 -#define DDRSS_CTL_48_DATA 0x10012458 +#define DDRSS_CTL_48_DATA 0x1000922C #define DDRSS_CTL_49_DATA 0x02030410 #define DDRSS_CTL_50_DATA 0x2C040500 #define DDRSS_CTL_51_DATA 0x082D2C2D @@ -71,11 +71,11 @@ #define DDRSS_CTL_58_DATA 0x00010100 #define DDRSS_CTL_59_DATA 0x03010000 #define DDRSS_CTL_60_DATA 0x00001008 -#define DDRSS_CTL_61_DATA 0x000000CE +#define DDRSS_CTL_61_DATA 0x00000063 #define DDRSS_CTL_62_DATA 0x00000256 -#define DDRSS_CTL_63_DATA 0x00002073 +#define DDRSS_CTL_63_DATA 0x00001035 #define DDRSS_CTL_64_DATA 0x00000256 -#define DDRSS_CTL_65_DATA 0x00002073 +#define DDRSS_CTL_65_DATA 0x00001035 #define DDRSS_CTL_66_DATA 0x00000005 #define DDRSS_CTL_67_DATA 0x00040000 #define DDRSS_CTL_68_DATA 0x00950012 @@ -112,27 +112,27 @@ #define DDRSS_CTL_99_DATA 0x00000000 #define DDRSS_CTL_100_DATA 0x00040005 #define DDRSS_CTL_101_DATA 0x00000000 -#define DDRSS_CTL_102_DATA 0x00003380 -#define DDRSS_CTL_103_DATA 0x00003380 -#define DDRSS_CTL_104_DATA 0x00003380 -#define DDRSS_CTL_105_DATA 0x00003380 -#define DDRSS_CTL_106_DATA 0x00003380 +#define DDRSS_CTL_102_DATA 0x000018C0 +#define DDRSS_CTL_103_DATA 0x000018C0 +#define DDRSS_CTL_104_DATA 0x000018C0 +#define DDRSS_CTL_105_DATA 0x000018C0 +#define DDRSS_CTL_106_DATA 0x000018C0 #define DDRSS_CTL_107_DATA 0x00000000 -#define DDRSS_CTL_108_DATA 0x000005A2 -#define DDRSS_CTL_109_DATA 0x00081CC0 -#define DDRSS_CTL_110_DATA 0x00081CC0 -#define DDRSS_CTL_111_DATA 0x00081CC0 -#define DDRSS_CTL_112_DATA 0x00081CC0 -#define DDRSS_CTL_113_DATA 0x00081CC0 +#define DDRSS_CTL_108_DATA 0x000002B5 +#define DDRSS_CTL_109_DATA 0x00040D40 +#define DDRSS_CTL_110_DATA 0x00040D40 +#define DDRSS_CTL_111_DATA 0x00040D40 +#define DDRSS_CTL_112_DATA 0x00040D40 +#define DDRSS_CTL_113_DATA 0x00040D40 #define DDRSS_CTL_114_DATA 0x00000000 -#define DDRSS_CTL_115_DATA 0x0000E325 -#define DDRSS_CTL_116_DATA 0x00081CC0 -#define DDRSS_CTL_117_DATA 0x00081CC0 -#define DDRSS_CTL_118_DATA 0x00081CC0 -#define DDRSS_CTL_119_DATA 0x00081CC0 -#define DDRSS_CTL_120_DATA 0x00081CC0 +#define DDRSS_CTL_115_DATA 0x00007173 +#define DDRSS_CTL_116_DATA 0x00040D40 +#define DDRSS_CTL_117_DATA 0x00040D40 +#define DDRSS_CTL_118_DATA 0x00040D40 +#define DDRSS_CTL_119_DATA 0x00040D40 +#define DDRSS_CTL_120_DATA 0x00040D40 #define DDRSS_CTL_121_DATA 0x00000000 -#define DDRSS_CTL_122_DATA 0x0000E325 +#define DDRSS_CTL_122_DATA 0x00007173 #define DDRSS_CTL_123_DATA 0x00000000 #define DDRSS_CTL_124_DATA 0x00000000 #define DDRSS_CTL_125_DATA 0x00000000 @@ -399,29 +399,29 @@ #define DDRSS_CTL_386_DATA 0x00000000 #define DDRSS_CTL_387_DATA 0x3A3A1B00 #define DDRSS_CTL_388_DATA 0x000A0000 -#define DDRSS_CTL_389_DATA 0x0000019C +#define DDRSS_CTL_389_DATA 0x000000C6 #define DDRSS_CTL_390_DATA 0x00000200 #define DDRSS_CTL_391_DATA 0x00000200 #define DDRSS_CTL_392_DATA 0x00000200 #define DDRSS_CTL_393_DATA 0x00000200 -#define DDRSS_CTL_394_DATA 0x000004D4 -#define DDRSS_CTL_395_DATA 0x00001018 +#define DDRSS_CTL_394_DATA 0x00000252 +#define DDRSS_CTL_395_DATA 0x000007BC #define DDRSS_CTL_396_DATA 0x00000204 -#define DDRSS_CTL_397_DATA 0x000040E6 +#define DDRSS_CTL_397_DATA 0x0000206A #define DDRSS_CTL_398_DATA 0x00000200 #define DDRSS_CTL_399_DATA 0x00000200 #define DDRSS_CTL_400_DATA 0x00000200 #define DDRSS_CTL_401_DATA 0x00000200 -#define DDRSS_CTL_402_DATA 0x0000C2B2 -#define DDRSS_CTL_403_DATA 0x000288FC +#define DDRSS_CTL_402_DATA 0x0000613E +#define DDRSS_CTL_403_DATA 0x00014424 #define DDRSS_CTL_404_DATA 0x00000E15 -#define DDRSS_CTL_405_DATA 0x000040E6 +#define DDRSS_CTL_405_DATA 0x0000206A #define DDRSS_CTL_406_DATA 0x00000200 #define DDRSS_CTL_407_DATA 0x00000200 #define DDRSS_CTL_408_DATA 0x00000200 #define DDRSS_CTL_409_DATA 0x00000200 -#define DDRSS_CTL_410_DATA 0x0000C2B2 -#define DDRSS_CTL_411_DATA 0x000288FC +#define DDRSS_CTL_410_DATA 0x0000613E +#define DDRSS_CTL_411_DATA 0x00014424 #define DDRSS_CTL_412_DATA 0x02020E15 #define DDRSS_CTL_413_DATA 0x03030202 #define DDRSS_CTL_414_DATA 0x00000022 @@ -640,11 +640,11 @@ #define DDRSS_PI_167_DATA 0x02000200 #define DDRSS_PI_168_DATA 0x48120C04 #define DDRSS_PI_169_DATA 0x00104812 -#define DDRSS_PI_170_DATA 0x000000CE +#define DDRSS_PI_170_DATA 0x00000063 #define DDRSS_PI_171_DATA 0x00000256 -#define DDRSS_PI_172_DATA 0x00002073 +#define DDRSS_PI_172_DATA 0x00001035 #define DDRSS_PI_173_DATA 0x00000256 -#define DDRSS_PI_174_DATA 0x04002073 +#define DDRSS_PI_174_DATA 0x04001035 #define DDRSS_PI_175_DATA 0x01010404 #define DDRSS_PI_176_DATA 0x00001501 #define DDRSS_PI_177_DATA 0x00150015 @@ -689,22 +689,22 @@ #define DDRSS_PI_216_DATA 0x3212005B #define DDRSS_PI_217_DATA 0x09000301 #define DDRSS_PI_218_DATA 0x04010504 -#define DDRSS_PI_219_DATA 0x040006C9 +#define DDRSS_PI_219_DATA 0x04000364 #define DDRSS_PI_220_DATA 0x0A032001 #define DDRSS_PI_221_DATA 0x2C31110A #define DDRSS_PI_222_DATA 0x00002D1C -#define DDRSS_PI_223_DATA 0x6001071C +#define DDRSS_PI_223_DATA 0x6000838E #define DDRSS_PI_224_DATA 0x1E202008 #define DDRSS_PI_225_DATA 0x2C311116 #define DDRSS_PI_226_DATA 0x00002D1C -#define DDRSS_PI_227_DATA 0x6001071C +#define DDRSS_PI_227_DATA 0x6000838E #define DDRSS_PI_228_DATA 0x1E202008 -#define DDRSS_PI_229_DATA 0x00019C16 -#define DDRSS_PI_230_DATA 0x00001018 -#define DDRSS_PI_231_DATA 0x000040E6 -#define DDRSS_PI_232_DATA 0x000288FC -#define DDRSS_PI_233_DATA 0x000040E6 -#define DDRSS_PI_234_DATA 0x000288FC +#define DDRSS_PI_229_DATA 0x0000C616 +#define DDRSS_PI_230_DATA 0x000007BC +#define DDRSS_PI_231_DATA 0x0000206A +#define DDRSS_PI_232_DATA 0x00014424 +#define DDRSS_PI_233_DATA 0x0000206A +#define DDRSS_PI_234_DATA 0x00014424 #define DDRSS_PI_235_DATA 0x02660010 #define DDRSS_PI_236_DATA 0x03030266 #define DDRSS_PI_237_DATA 0x002AF803 diff --git a/arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi index c91576bf093..45fa0619160 100644 --- a/arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi +++ b/arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi @@ -1,11 +1,11 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ - * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.7.0 - * This file was generated on 10/14/2021 + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.10.0 + * This file was generated on 04/12/2023 */ -#define DDRSS_PLL_FHS_CNT 10 +#define DDRSS_PLL_FHS_CNT 5 #define DDRSS_PLL_FREQUENCY_0 27500000 #define DDRSS_PLL_FREQUENCY_1 1066500000 #define DDRSS_PLL_FREQUENCY_2 1066500000 @@ -60,11 +60,11 @@ #define DDRSS0_CTL_41_DATA 0x1760008B #define DDRSS0_CTL_42_DATA 0x2000422B #define DDRSS0_CTL_43_DATA 0x000A0A09 -#define DDRSS0_CTL_44_DATA 0x0400078A +#define DDRSS0_CTL_44_DATA 0x040003C5 #define DDRSS0_CTL_45_DATA 0x1E161104 -#define DDRSS0_CTL_46_DATA 0x10012458 +#define DDRSS0_CTL_46_DATA 0x1000922C #define DDRSS0_CTL_47_DATA 0x1E161110 -#define DDRSS0_CTL_48_DATA 0x10012458 +#define DDRSS0_CTL_48_DATA 0x1000922C #define DDRSS0_CTL_49_DATA 0x02030410 #define DDRSS0_CTL_50_DATA 0x2C040500 #define DDRSS0_CTL_51_DATA 0x08292C29 @@ -77,11 +77,11 @@ #define DDRSS0_CTL_58_DATA 0x00010100 #define DDRSS0_CTL_59_DATA 0x03010000 #define DDRSS0_CTL_60_DATA 0x00001508 -#define DDRSS0_CTL_61_DATA 0x000000CE +#define DDRSS0_CTL_61_DATA 0x00000063 #define DDRSS0_CTL_62_DATA 0x0000032B -#define DDRSS0_CTL_63_DATA 0x00002073 +#define DDRSS0_CTL_63_DATA 0x00001035 #define DDRSS0_CTL_64_DATA 0x0000032B -#define DDRSS0_CTL_65_DATA 0x00002073 +#define DDRSS0_CTL_65_DATA 0x00001035 #define DDRSS0_CTL_66_DATA 0x00000005 #define DDRSS0_CTL_67_DATA 0x00050000 #define DDRSS0_CTL_68_DATA 0x00CB0012 @@ -118,27 +118,27 @@ #define DDRSS0_CTL_99_DATA 0x00000000 #define DDRSS0_CTL_100_DATA 0x00040005 #define DDRSS0_CTL_101_DATA 0x00000000 -#define DDRSS0_CTL_102_DATA 0x00003380 -#define DDRSS0_CTL_103_DATA 0x00003380 -#define DDRSS0_CTL_104_DATA 0x00003380 -#define DDRSS0_CTL_105_DATA 0x00003380 -#define DDRSS0_CTL_106_DATA 0x00003380 +#define DDRSS0_CTL_102_DATA 0x000018C0 +#define DDRSS0_CTL_103_DATA 0x000018C0 +#define DDRSS0_CTL_104_DATA 0x000018C0 +#define DDRSS0_CTL_105_DATA 0x000018C0 +#define DDRSS0_CTL_106_DATA 0x000018C0 #define DDRSS0_CTL_107_DATA 0x00000000 -#define DDRSS0_CTL_108_DATA 0x000005A2 -#define DDRSS0_CTL_109_DATA 0x00081CC0 -#define DDRSS0_CTL_110_DATA 0x00081CC0 -#define DDRSS0_CTL_111_DATA 0x00081CC0 -#define DDRSS0_CTL_112_DATA 0x00081CC0 -#define DDRSS0_CTL_113_DATA 0x00081CC0 +#define DDRSS0_CTL_108_DATA 0x000002B5 +#define DDRSS0_CTL_109_DATA 0x00040D40 +#define DDRSS0_CTL_110_DATA 0x00040D40 +#define DDRSS0_CTL_111_DATA 0x00040D40 +#define DDRSS0_CTL_112_DATA 0x00040D40 +#define DDRSS0_CTL_113_DATA 0x00040D40 #define DDRSS0_CTL_114_DATA 0x00000000 -#define DDRSS0_CTL_115_DATA 0x0000E325 -#define DDRSS0_CTL_116_DATA 0x00081CC0 -#define DDRSS0_CTL_117_DATA 0x00081CC0 -#define DDRSS0_CTL_118_DATA 0x00081CC0 -#define DDRSS0_CTL_119_DATA 0x00081CC0 -#define DDRSS0_CTL_120_DATA 0x00081CC0 +#define DDRSS0_CTL_115_DATA 0x00007173 +#define DDRSS0_CTL_116_DATA 0x00040D40 +#define DDRSS0_CTL_117_DATA 0x00040D40 +#define DDRSS0_CTL_118_DATA 0x00040D40 +#define DDRSS0_CTL_119_DATA 0x00040D40 +#define DDRSS0_CTL_120_DATA 0x00040D40 #define DDRSS0_CTL_121_DATA 0x00000000 -#define DDRSS0_CTL_122_DATA 0x0000E325 +#define DDRSS0_CTL_122_DATA 0x00007173 #define DDRSS0_CTL_123_DATA 0x00000000 #define DDRSS0_CTL_124_DATA 0x00000000 #define DDRSS0_CTL_125_DATA 0x00000000 @@ -192,17 +192,17 @@ #define DDRSS0_CTL_173_DATA 0x00000000 #define DDRSS0_CTL_174_DATA 0x00000000 #define DDRSS0_CTL_175_DATA 0x3FF40084 -#define DDRSS0_CTL_176_DATA 0x33003FF4 -#define DDRSS0_CTL_177_DATA 0x00003333 -#define DDRSS0_CTL_178_DATA 0x56000000 -#define DDRSS0_CTL_179_DATA 0x27270056 +#define DDRSS0_CTL_176_DATA 0xB3003FF4 +#define DDRSS0_CTL_177_DATA 0x0000B3B3 +#define DDRSS0_CTL_178_DATA 0x36000000 +#define DDRSS0_CTL_179_DATA 0x27270036 #define DDRSS0_CTL_180_DATA 0x0F0F0000 #define DDRSS0_CTL_181_DATA 0x16000000 #define DDRSS0_CTL_182_DATA 0x00841616 #define DDRSS0_CTL_183_DATA 0x3FF43FF4 -#define DDRSS0_CTL_184_DATA 0x33333300 +#define DDRSS0_CTL_184_DATA 0xB3B3B300 #define DDRSS0_CTL_185_DATA 0x00000000 -#define DDRSS0_CTL_186_DATA 0x00565600 +#define DDRSS0_CTL_186_DATA 0x00363600 #define DDRSS0_CTL_187_DATA 0x00002727 #define DDRSS0_CTL_188_DATA 0x00000F0F #define DDRSS0_CTL_189_DATA 0x16161600 @@ -245,17 +245,17 @@ #define DDRSS0_CTL_226_DATA 0x00000000 #define DDRSS0_CTL_227_DATA 0x15110000 #define DDRSS0_CTL_228_DATA 0x00040C18 -#define DDRSS0_CTL_229_DATA 0x00000000 -#define DDRSS0_CTL_230_DATA 0x00000000 +#define DDRSS0_CTL_229_DATA 0xF000C000 +#define DDRSS0_CTL_230_DATA 0x0000F000 #define DDRSS0_CTL_231_DATA 0x00000000 #define DDRSS0_CTL_232_DATA 0x00000000 -#define DDRSS0_CTL_233_DATA 0x00000000 -#define DDRSS0_CTL_234_DATA 0x00000000 +#define DDRSS0_CTL_233_DATA 0xC0000000 +#define DDRSS0_CTL_234_DATA 0xF000F000 #define DDRSS0_CTL_235_DATA 0x00000000 #define DDRSS0_CTL_236_DATA 0x00000000 #define DDRSS0_CTL_237_DATA 0x00000000 -#define DDRSS0_CTL_238_DATA 0x00000000 -#define DDRSS0_CTL_239_DATA 0x00000000 +#define DDRSS0_CTL_238_DATA 0xF000C000 +#define DDRSS0_CTL_239_DATA 0x0000F000 #define DDRSS0_CTL_240_DATA 0x00000000 #define DDRSS0_CTL_241_DATA 0x00000000 #define DDRSS0_CTL_242_DATA 0x00030000 @@ -283,7 +283,7 @@ #define DDRSS0_CTL_264_DATA 0x00000040 #define DDRSS0_CTL_265_DATA 0x006B0003 #define DDRSS0_CTL_266_DATA 0x0100006B -#define DDRSS0_CTL_267_DATA 0x00000000 +#define DDRSS0_CTL_267_DATA 0x03030303 #define DDRSS0_CTL_268_DATA 0x00000000 #define DDRSS0_CTL_269_DATA 0x00000202 #define DDRSS0_CTL_270_DATA 0x00001FFF @@ -307,7 +307,7 @@ #define DDRSS0_CTL_288_DATA 0x00000000 #define DDRSS0_CTL_289_DATA 0x00000000 #define DDRSS0_CTL_290_DATA 0x03030300 -#define DDRSS0_CTL_291_DATA 0x00000001 +#define DDRSS0_CTL_291_DATA 0x00000101 #define DDRSS0_CTL_292_DATA 0x00000000 #define DDRSS0_CTL_293_DATA 0x00000000 #define DDRSS0_CTL_294_DATA 0x00000000 @@ -405,29 +405,29 @@ #define DDRSS0_CTL_386_DATA 0x00000000 #define DDRSS0_CTL_387_DATA 0x3A3A1B00 #define DDRSS0_CTL_388_DATA 0x000A0000 -#define DDRSS0_CTL_389_DATA 0x0000019C +#define DDRSS0_CTL_389_DATA 0x000000C6 #define DDRSS0_CTL_390_DATA 0x00000200 #define DDRSS0_CTL_391_DATA 0x00000200 #define DDRSS0_CTL_392_DATA 0x00000200 #define DDRSS0_CTL_393_DATA 0x00000200 -#define DDRSS0_CTL_394_DATA 0x000004D4 -#define DDRSS0_CTL_395_DATA 0x00001018 +#define DDRSS0_CTL_394_DATA 0x00000252 +#define DDRSS0_CTL_395_DATA 0x000007BC #define DDRSS0_CTL_396_DATA 0x00000204 -#define DDRSS0_CTL_397_DATA 0x000040E6 +#define DDRSS0_CTL_397_DATA 0x0000206A #define DDRSS0_CTL_398_DATA 0x00000200 #define DDRSS0_CTL_399_DATA 0x00000200 #define DDRSS0_CTL_400_DATA 0x00000200 #define DDRSS0_CTL_401_DATA 0x00000200 -#define DDRSS0_CTL_402_DATA 0x0000C2B2 -#define DDRSS0_CTL_403_DATA 0x000288FC +#define DDRSS0_CTL_402_DATA 0x0000613E +#define DDRSS0_CTL_403_DATA 0x00014424 #define DDRSS0_CTL_404_DATA 0x00000E15 -#define DDRSS0_CTL_405_DATA 0x000040E6 +#define DDRSS0_CTL_405_DATA 0x0000206A #define DDRSS0_CTL_406_DATA 0x00000200 #define DDRSS0_CTL_407_DATA 0x00000200 #define DDRSS0_CTL_408_DATA 0x00000200 #define DDRSS0_CTL_409_DATA 0x00000200 -#define DDRSS0_CTL_410_DATA 0x0000C2B2 -#define DDRSS0_CTL_411_DATA 0x000288FC +#define DDRSS0_CTL_410_DATA 0x0000613E +#define DDRSS0_CTL_411_DATA 0x00014424 #define DDRSS0_CTL_412_DATA 0x02020E15 #define DDRSS0_CTL_413_DATA 0x03030202 #define DDRSS0_CTL_414_DATA 0x00000022 @@ -488,8 +488,8 @@ #define DDRSS0_PI_09_DATA 0x00000000 #define DDRSS0_PI_10_DATA 0x00000000 #define DDRSS0_PI_11_DATA 0x00000000 -#define DDRSS0_PI_12_DATA 0x00000007 -#define DDRSS0_PI_13_DATA 0x00010002 +#define DDRSS0_PI_12_DATA 0x00000003 +#define DDRSS0_PI_13_DATA 0x00010001 #define DDRSS0_PI_14_DATA 0x0800000F #define DDRSS0_PI_15_DATA 0x00000103 #define DDRSS0_PI_16_DATA 0x00000005 @@ -537,18 +537,18 @@ #define DDRSS0_PI_58_DATA 0x00000000 #define DDRSS0_PI_59_DATA 0x00000000 #define DDRSS0_PI_60_DATA 0x0A0A140A -#define DDRSS0_PI_61_DATA 0x10020101 +#define DDRSS0_PI_61_DATA 0x10020201 #define DDRSS0_PI_62_DATA 0x00020805 #define DDRSS0_PI_63_DATA 0x01000404 #define DDRSS0_PI_64_DATA 0x00000000 #define DDRSS0_PI_65_DATA 0x00000000 -#define DDRSS0_PI_66_DATA 0x00000100 -#define DDRSS0_PI_67_DATA 0x0001010F +#define DDRSS0_PI_66_DATA 0x01000100 +#define DDRSS0_PI_67_DATA 0x0102020F #define DDRSS0_PI_68_DATA 0x00340000 #define DDRSS0_PI_69_DATA 0x00000000 #define DDRSS0_PI_70_DATA 0x00000000 #define DDRSS0_PI_71_DATA 0x0000FFFF -#define DDRSS0_PI_72_DATA 0x00000000 +#define DDRSS0_PI_72_DATA 0x01000000 #define DDRSS0_PI_73_DATA 0x00080000 #define DDRSS0_PI_74_DATA 0x02000200 #define DDRSS0_PI_75_DATA 0x01000100 @@ -646,19 +646,19 @@ #define DDRSS0_PI_167_DATA 0x02000200 #define DDRSS0_PI_168_DATA 0x48120C04 #define DDRSS0_PI_169_DATA 0x00154812 -#define DDRSS0_PI_170_DATA 0x000000CE +#define DDRSS0_PI_170_DATA 0x00000063 #define DDRSS0_PI_171_DATA 0x0000032B -#define DDRSS0_PI_172_DATA 0x00002073 +#define DDRSS0_PI_172_DATA 0x00001035 #define DDRSS0_PI_173_DATA 0x0000032B -#define DDRSS0_PI_174_DATA 0x04002073 +#define DDRSS0_PI_174_DATA 0x04001035 #define DDRSS0_PI_175_DATA 0x01010404 -#define DDRSS0_PI_176_DATA 0x00001501 +#define DDRSS0_PI_176_DATA 0x00001500 #define DDRSS0_PI_177_DATA 0x00150015 #define DDRSS0_PI_178_DATA 0x01000100 #define DDRSS0_PI_179_DATA 0x00000100 #define DDRSS0_PI_180_DATA 0x00000000 #define DDRSS0_PI_181_DATA 0x01010101 -#define DDRSS0_PI_182_DATA 0x00000101 +#define DDRSS0_PI_182_DATA 0x00000000 #define DDRSS0_PI_183_DATA 0x00000000 #define DDRSS0_PI_184_DATA 0x00000000 #define DDRSS0_PI_185_DATA 0x15040000 @@ -667,7 +667,7 @@ #define DDRSS0_PI_188_DATA 0x000D0035 #define DDRSS0_PI_189_DATA 0x00218049 #define DDRSS0_PI_190_DATA 0x00218049 -#define DDRSS0_PI_191_DATA 0x01010101 +#define DDRSS0_PI_191_DATA 0x01000101 #define DDRSS0_PI_192_DATA 0x0004000E #define DDRSS0_PI_193_DATA 0x00040216 #define DDRSS0_PI_194_DATA 0x01000216 @@ -693,24 +693,24 @@ #define DDRSS0_PI_214_DATA 0x03013212 #define DDRSS0_PI_215_DATA 0x00003600 #define DDRSS0_PI_216_DATA 0x3212005B -#define DDRSS0_PI_217_DATA 0x09000301 +#define DDRSS0_PI_217_DATA 0x09000001 #define DDRSS0_PI_218_DATA 0x04010504 -#define DDRSS0_PI_219_DATA 0x040006C9 +#define DDRSS0_PI_219_DATA 0x04000364 #define DDRSS0_PI_220_DATA 0x0A032001 #define DDRSS0_PI_221_DATA 0x2C31110A #define DDRSS0_PI_222_DATA 0x00002918 -#define DDRSS0_PI_223_DATA 0x6001071C +#define DDRSS0_PI_223_DATA 0x6000838E #define DDRSS0_PI_224_DATA 0x1E202008 #define DDRSS0_PI_225_DATA 0x2C311116 #define DDRSS0_PI_226_DATA 0x00002918 -#define DDRSS0_PI_227_DATA 0x6001071C +#define DDRSS0_PI_227_DATA 0x6000838E #define DDRSS0_PI_228_DATA 0x1E202008 -#define DDRSS0_PI_229_DATA 0x00019C16 -#define DDRSS0_PI_230_DATA 0x00001018 -#define DDRSS0_PI_231_DATA 0x000040E6 -#define DDRSS0_PI_232_DATA 0x000288FC -#define DDRSS0_PI_233_DATA 0x000040E6 -#define DDRSS0_PI_234_DATA 0x000288FC +#define DDRSS0_PI_229_DATA 0x0000C616 +#define DDRSS0_PI_230_DATA 0x000007BC +#define DDRSS0_PI_231_DATA 0x0000206A +#define DDRSS0_PI_232_DATA 0x00014424 +#define DDRSS0_PI_233_DATA 0x0000206A +#define DDRSS0_PI_234_DATA 0x00014424 #define DDRSS0_PI_235_DATA 0x033B0016 #define DDRSS0_PI_236_DATA 0x0303033B #define DDRSS0_PI_237_DATA 0x002AF803 @@ -751,29 +751,29 @@ #define DDRSS0_PI_272_DATA 0x00080804 #define DDRSS0_PI_273_DATA 0x00000000 #define DDRSS0_PI_274_DATA 0x00000000 -#define DDRSS0_PI_275_DATA 0x00330084 +#define DDRSS0_PI_275_DATA 0x00B30084 #define DDRSS0_PI_276_DATA 0x00160000 -#define DDRSS0_PI_277_DATA 0x56333FF4 +#define DDRSS0_PI_277_DATA 0x36B33FF4 #define DDRSS0_PI_278_DATA 0x00160F27 -#define DDRSS0_PI_279_DATA 0x56333FF4 +#define DDRSS0_PI_279_DATA 0x36B33FF4 #define DDRSS0_PI_280_DATA 0x00160F27 -#define DDRSS0_PI_281_DATA 0x00330084 +#define DDRSS0_PI_281_DATA 0x00B30084 #define DDRSS0_PI_282_DATA 0x00160000 -#define DDRSS0_PI_283_DATA 0x56333FF4 +#define DDRSS0_PI_283_DATA 0x36B33FF4 #define DDRSS0_PI_284_DATA 0x00160F27 -#define DDRSS0_PI_285_DATA 0x56333FF4 +#define DDRSS0_PI_285_DATA 0x36B33FF4 #define DDRSS0_PI_286_DATA 0x00160F27 -#define DDRSS0_PI_287_DATA 0x00330084 +#define DDRSS0_PI_287_DATA 0x00B30084 #define DDRSS0_PI_288_DATA 0x00160000 -#define DDRSS0_PI_289_DATA 0x56333FF4 +#define DDRSS0_PI_289_DATA 0x36B33FF4 #define DDRSS0_PI_290_DATA 0x00160F27 -#define DDRSS0_PI_291_DATA 0x56333FF4 +#define DDRSS0_PI_291_DATA 0x36B33FF4 #define DDRSS0_PI_292_DATA 0x00160F27 -#define DDRSS0_PI_293_DATA 0x00330084 +#define DDRSS0_PI_293_DATA 0x00B30084 #define DDRSS0_PI_294_DATA 0x00160000 -#define DDRSS0_PI_295_DATA 0x56333FF4 +#define DDRSS0_PI_295_DATA 0x36B33FF4 #define DDRSS0_PI_296_DATA 0x00160F27 -#define DDRSS0_PI_297_DATA 0x56333FF4 +#define DDRSS0_PI_297_DATA 0x36B33FF4 #define DDRSS0_PI_298_DATA 0x00160F27 #define DDRSS0_PI_299_DATA 0x00000000 @@ -789,7 +789,7 @@ #define DDRSS0_PHY_09_DATA 0x00000000 #define DDRSS0_PHY_10_DATA 0x00000000 #define DDRSS0_PHY_11_DATA 0x01000001 -#define DDRSS0_PHY_12_DATA 0x00000100 +#define DDRSS0_PHY_12_DATA 0x00000200 #define DDRSS0_PHY_13_DATA 0x000800C0 #define DDRSS0_PHY_14_DATA 0x060100CC #define DDRSS0_PHY_15_DATA 0x00030066 @@ -808,9 +808,9 @@ #define DDRSS0_PHY_28_DATA 0x2A000000 #define DDRSS0_PHY_29_DATA 0x00000808 #define DDRSS0_PHY_30_DATA 0x0F000000 -#define DDRSS0_PHY_31_DATA 0x00000F0F -#define DDRSS0_PHY_32_DATA 0x10200000 -#define DDRSS0_PHY_33_DATA 0x0C002006 +#define DDRSS0_PHY_31_DATA 0x00000F08 +#define DDRSS0_PHY_32_DATA 0x10400000 +#define DDRSS0_PHY_33_DATA 0x0C002002 #define DDRSS0_PHY_34_DATA 0x00000000 #define DDRSS0_PHY_35_DATA 0x00000000 #define DDRSS0_PHY_36_DATA 0x55555555 @@ -877,7 +877,7 @@ #define DDRSS0_PHY_97_DATA 0x00050010 #define DDRSS0_PHY_98_DATA 0x51517041 #define DDRSS0_PHY_99_DATA 0x31C06001 -#define DDRSS0_PHY_100_DATA 0x07AB0340 +#define DDRSS0_PHY_100_DATA 0x07AB01AB #define DDRSS0_PHY_101_DATA 0x00C0C001 #define DDRSS0_PHY_102_DATA 0x0E0D0001 #define DDRSS0_PHY_103_DATA 0x10001000 @@ -913,7 +913,7 @@ #define DDRSS0_PHY_133_DATA 0x00000000 #define DDRSS0_PHY_134_DATA 0x00080200 #define DDRSS0_PHY_135_DATA 0x00000000 -#define DDRSS0_PHY_136_DATA 0x20202000 +#define DDRSS0_PHY_136_DATA 0x20202020 #define DDRSS0_PHY_137_DATA 0x20202020 #define DDRSS0_PHY_138_DATA 0xF0F02020 #define DDRSS0_PHY_139_DATA 0x00000000 @@ -1045,7 +1045,7 @@ #define DDRSS0_PHY_265_DATA 0x00000000 #define DDRSS0_PHY_266_DATA 0x00000000 #define DDRSS0_PHY_267_DATA 0x01000001 -#define DDRSS0_PHY_268_DATA 0x00000100 +#define DDRSS0_PHY_268_DATA 0x00000200 #define DDRSS0_PHY_269_DATA 0x000800C0 #define DDRSS0_PHY_270_DATA 0x060100CC #define DDRSS0_PHY_271_DATA 0x00030066 @@ -1064,9 +1064,9 @@ #define DDRSS0_PHY_284_DATA 0x2A000000 #define DDRSS0_PHY_285_DATA 0x00000808 #define DDRSS0_PHY_286_DATA 0x0F000000 -#define DDRSS0_PHY_287_DATA 0x00000F0F -#define DDRSS0_PHY_288_DATA 0x10200000 -#define DDRSS0_PHY_289_DATA 0x0C002006 +#define DDRSS0_PHY_287_DATA 0x00000F08 +#define DDRSS0_PHY_288_DATA 0x10400000 +#define DDRSS0_PHY_289_DATA 0x0C002002 #define DDRSS0_PHY_290_DATA 0x00000000 #define DDRSS0_PHY_291_DATA 0x00000000 #define DDRSS0_PHY_292_DATA 0x55555555 @@ -1133,7 +1133,7 @@ #define DDRSS0_PHY_353_DATA 0x00050010 #define DDRSS0_PHY_354_DATA 0x51517041 #define DDRSS0_PHY_355_DATA 0x31C06001 -#define DDRSS0_PHY_356_DATA 0x07AB0340 +#define DDRSS0_PHY_356_DATA 0x07AB01AB #define DDRSS0_PHY_357_DATA 0x00C0C001 #define DDRSS0_PHY_358_DATA 0x0E0D0001 #define DDRSS0_PHY_359_DATA 0x10001000 @@ -1169,7 +1169,7 @@ #define DDRSS0_PHY_389_DATA 0x00000000 #define DDRSS0_PHY_390_DATA 0x00080200 #define DDRSS0_PHY_391_DATA 0x00000000 -#define DDRSS0_PHY_392_DATA 0x20202000 +#define DDRSS0_PHY_392_DATA 0x20202020 #define DDRSS0_PHY_393_DATA 0x20202020 #define DDRSS0_PHY_394_DATA 0xF0F02020 #define DDRSS0_PHY_395_DATA 0x00000000 @@ -1301,7 +1301,7 @@ #define DDRSS0_PHY_521_DATA 0x00000000 #define DDRSS0_PHY_522_DATA 0x00000000 #define DDRSS0_PHY_523_DATA 0x01000001 -#define DDRSS0_PHY_524_DATA 0x00000100 +#define DDRSS0_PHY_524_DATA 0x00000200 #define DDRSS0_PHY_525_DATA 0x000800C0 #define DDRSS0_PHY_526_DATA 0x060100CC #define DDRSS0_PHY_527_DATA 0x00030066 @@ -1320,9 +1320,9 @@ #define DDRSS0_PHY_540_DATA 0x2A000000 #define DDRSS0_PHY_541_DATA 0x00000808 #define DDRSS0_PHY_542_DATA 0x0F000000 -#define DDRSS0_PHY_543_DATA 0x00000F0F -#define DDRSS0_PHY_544_DATA 0x10200000 -#define DDRSS0_PHY_545_DATA 0x0C002006 +#define DDRSS0_PHY_543_DATA 0x00000F08 +#define DDRSS0_PHY_544_DATA 0x10400000 +#define DDRSS0_PHY_545_DATA 0x0C002002 #define DDRSS0_PHY_546_DATA 0x00000000 #define DDRSS0_PHY_547_DATA 0x00000000 #define DDRSS0_PHY_548_DATA 0x55555555 @@ -1389,7 +1389,7 @@ #define DDRSS0_PHY_609_DATA 0x00050010 #define DDRSS0_PHY_610_DATA 0x51517041 #define DDRSS0_PHY_611_DATA 0x31C06001 -#define DDRSS0_PHY_612_DATA 0x07AB0340 +#define DDRSS0_PHY_612_DATA 0x07AB01AB #define DDRSS0_PHY_613_DATA 0x00C0C001 #define DDRSS0_PHY_614_DATA 0x0E0D0001 #define DDRSS0_PHY_615_DATA 0x10001000 @@ -1425,7 +1425,7 @@ #define DDRSS0_PHY_645_DATA 0x00000000 #define DDRSS0_PHY_646_DATA 0x00080200 #define DDRSS0_PHY_647_DATA 0x00000000 -#define DDRSS0_PHY_648_DATA 0x20202000 +#define DDRSS0_PHY_648_DATA 0x20202020 #define DDRSS0_PHY_649_DATA 0x20202020 #define DDRSS0_PHY_650_DATA 0xF0F02020 #define DDRSS0_PHY_651_DATA 0x00000000 @@ -1557,7 +1557,7 @@ #define DDRSS0_PHY_777_DATA 0x00000000 #define DDRSS0_PHY_778_DATA 0x00000000 #define DDRSS0_PHY_779_DATA 0x01000001 -#define DDRSS0_PHY_780_DATA 0x00000100 +#define DDRSS0_PHY_780_DATA 0x00000200 #define DDRSS0_PHY_781_DATA 0x000800C0 #define DDRSS0_PHY_782_DATA 0x060100CC #define DDRSS0_PHY_783_DATA 0x00030066 @@ -1576,9 +1576,9 @@ #define DDRSS0_PHY_796_DATA 0x2A000000 #define DDRSS0_PHY_797_DATA 0x00000808 #define DDRSS0_PHY_798_DATA 0x0F000000 -#define DDRSS0_PHY_799_DATA 0x00000F0F -#define DDRSS0_PHY_800_DATA 0x10200000 -#define DDRSS0_PHY_801_DATA 0x0C002006 +#define DDRSS0_PHY_799_DATA 0x00000F08 +#define DDRSS0_PHY_800_DATA 0x10400000 +#define DDRSS0_PHY_801_DATA 0x0C002002 #define DDRSS0_PHY_802_DATA 0x00000000 #define DDRSS0_PHY_803_DATA 0x00000000 #define DDRSS0_PHY_804_DATA 0x55555555 @@ -1645,7 +1645,7 @@ #define DDRSS0_PHY_865_DATA 0x00050010 #define DDRSS0_PHY_866_DATA 0x51517041 #define DDRSS0_PHY_867_DATA 0x31C06001 -#define DDRSS0_PHY_868_DATA 0x07AB0340 +#define DDRSS0_PHY_868_DATA 0x07AB01AB #define DDRSS0_PHY_869_DATA 0x00C0C001 #define DDRSS0_PHY_870_DATA 0x0E0D0001 #define DDRSS0_PHY_871_DATA 0x10001000 @@ -1681,7 +1681,7 @@ #define DDRSS0_PHY_901_DATA 0x00000000 #define DDRSS0_PHY_902_DATA 0x00080200 #define DDRSS0_PHY_903_DATA 0x00000000 -#define DDRSS0_PHY_904_DATA 0x20202000 +#define DDRSS0_PHY_904_DATA 0x20202020 #define DDRSS0_PHY_905_DATA 0x20202020 #define DDRSS0_PHY_906_DATA 0xF0F02020 #define DDRSS0_PHY_907_DATA 0x00000000 @@ -2080,14 +2080,14 @@ #define DDRSS0_PHY_1300_DATA 0x00040101 #define DDRSS0_PHY_1301_DATA 0x0000010F #define DDRSS0_PHY_1302_DATA 0x00000000 -#define DDRSS0_PHY_1303_DATA 0x0000FFFF +#define DDRSS0_PHY_1303_DATA 0x00000064 #define DDRSS0_PHY_1304_DATA 0x00000000 #define DDRSS0_PHY_1305_DATA 0x01010000 #define DDRSS0_PHY_1306_DATA 0x01080402 #define DDRSS0_PHY_1307_DATA 0x01200F02 #define DDRSS0_PHY_1308_DATA 0x00194280 #define DDRSS0_PHY_1309_DATA 0x00000004 -#define DDRSS0_PHY_1310_DATA 0x00052000 +#define DDRSS0_PHY_1310_DATA 0x00042000 #define DDRSS0_PHY_1311_DATA 0x00000000 #define DDRSS0_PHY_1312_DATA 0x00000000 #define DDRSS0_PHY_1313_DATA 0x00000000 @@ -2174,7 +2174,7 @@ #define DDRSS0_PHY_1394_DATA 0x00000003 #define DDRSS0_PHY_1395_DATA 0x00000000 #define DDRSS0_PHY_1396_DATA 0x00001142 -#define DDRSS0_PHY_1397_DATA 0x010207AB +#define DDRSS0_PHY_1397_DATA 0x040207AB #define DDRSS0_PHY_1398_DATA 0x01000080 #define DDRSS0_PHY_1399_DATA 0x03900390 #define DDRSS0_PHY_1400_DATA 0x03900390 @@ -2236,7 +2236,7 @@ #define DDRSS1_CTL_32_DATA 0x00000000 #define DDRSS1_CTL_33_DATA 0x00000000 #define DDRSS1_CTL_34_DATA 0x040C0000 -#define DDRSS1_CTL_35_DATA 0x12481248 +#define DDRSS1_CTL_35_DATA 0x12501250 #define DDRSS1_CTL_36_DATA 0x00050804 #define DDRSS1_CTL_37_DATA 0x09040008 #define DDRSS1_CTL_38_DATA 0x15000204 @@ -2245,11 +2245,11 @@ #define DDRSS1_CTL_41_DATA 0x1760008B #define DDRSS1_CTL_42_DATA 0x2000422B #define DDRSS1_CTL_43_DATA 0x000A0A09 -#define DDRSS1_CTL_44_DATA 0x0400078A +#define DDRSS1_CTL_44_DATA 0x040003C5 #define DDRSS1_CTL_45_DATA 0x1E161104 -#define DDRSS1_CTL_46_DATA 0x10012458 +#define DDRSS1_CTL_46_DATA 0x1000922C #define DDRSS1_CTL_47_DATA 0x1E161110 -#define DDRSS1_CTL_48_DATA 0x10012458 +#define DDRSS1_CTL_48_DATA 0x1000922C #define DDRSS1_CTL_49_DATA 0x02030410 #define DDRSS1_CTL_50_DATA 0x2C040500 #define DDRSS1_CTL_51_DATA 0x08292C29 @@ -2262,11 +2262,11 @@ #define DDRSS1_CTL_58_DATA 0x00010100 #define DDRSS1_CTL_59_DATA 0x03010000 #define DDRSS1_CTL_60_DATA 0x00001508 -#define DDRSS1_CTL_61_DATA 0x000000CE +#define DDRSS1_CTL_61_DATA 0x00000063 #define DDRSS1_CTL_62_DATA 0x0000032B -#define DDRSS1_CTL_63_DATA 0x00002073 +#define DDRSS1_CTL_63_DATA 0x00001035 #define DDRSS1_CTL_64_DATA 0x0000032B -#define DDRSS1_CTL_65_DATA 0x00002073 +#define DDRSS1_CTL_65_DATA 0x00001035 #define DDRSS1_CTL_66_DATA 0x00000005 #define DDRSS1_CTL_67_DATA 0x00050000 #define DDRSS1_CTL_68_DATA 0x00CB0012 @@ -2303,27 +2303,27 @@ #define DDRSS1_CTL_99_DATA 0x00000000 #define DDRSS1_CTL_100_DATA 0x00040005 #define DDRSS1_CTL_101_DATA 0x00000000 -#define DDRSS1_CTL_102_DATA 0x00003380 -#define DDRSS1_CTL_103_DATA 0x00003380 -#define DDRSS1_CTL_104_DATA 0x00003380 -#define DDRSS1_CTL_105_DATA 0x00003380 -#define DDRSS1_CTL_106_DATA 0x00003380 +#define DDRSS1_CTL_102_DATA 0x000018C0 +#define DDRSS1_CTL_103_DATA 0x000018C0 +#define DDRSS1_CTL_104_DATA 0x000018C0 +#define DDRSS1_CTL_105_DATA 0x000018C0 +#define DDRSS1_CTL_106_DATA 0x000018C0 #define DDRSS1_CTL_107_DATA 0x00000000 -#define DDRSS1_CTL_108_DATA 0x000005A2 -#define DDRSS1_CTL_109_DATA 0x00081CC0 -#define DDRSS1_CTL_110_DATA 0x00081CC0 -#define DDRSS1_CTL_111_DATA 0x00081CC0 -#define DDRSS1_CTL_112_DATA 0x00081CC0 -#define DDRSS1_CTL_113_DATA 0x00081CC0 +#define DDRSS1_CTL_108_DATA 0x000002B5 +#define DDRSS1_CTL_109_DATA 0x00040D40 +#define DDRSS1_CTL_110_DATA 0x00040D40 +#define DDRSS1_CTL_111_DATA 0x00040D40 +#define DDRSS1_CTL_112_DATA 0x00040D40 +#define DDRSS1_CTL_113_DATA 0x00040D40 #define DDRSS1_CTL_114_DATA 0x00000000 -#define DDRSS1_CTL_115_DATA 0x0000E325 -#define DDRSS1_CTL_116_DATA 0x00081CC0 -#define DDRSS1_CTL_117_DATA 0x00081CC0 -#define DDRSS1_CTL_118_DATA 0x00081CC0 -#define DDRSS1_CTL_119_DATA 0x00081CC0 -#define DDRSS1_CTL_120_DATA 0x00081CC0 +#define DDRSS1_CTL_115_DATA 0x00007173 +#define DDRSS1_CTL_116_DATA 0x00040D40 +#define DDRSS1_CTL_117_DATA 0x00040D40 +#define DDRSS1_CTL_118_DATA 0x00040D40 +#define DDRSS1_CTL_119_DATA 0x00040D40 +#define DDRSS1_CTL_120_DATA 0x00040D40 #define DDRSS1_CTL_121_DATA 0x00000000 -#define DDRSS1_CTL_122_DATA 0x0000E325 +#define DDRSS1_CTL_122_DATA 0x00007173 #define DDRSS1_CTL_123_DATA 0x00000000 #define DDRSS1_CTL_124_DATA 0x00000000 #define DDRSS1_CTL_125_DATA 0x00000000 @@ -2377,17 +2377,17 @@ #define DDRSS1_CTL_173_DATA 0x00000000 #define DDRSS1_CTL_174_DATA 0x00000000 #define DDRSS1_CTL_175_DATA 0x3FF40084 -#define DDRSS1_CTL_176_DATA 0x33003FF4 -#define DDRSS1_CTL_177_DATA 0x00003333 -#define DDRSS1_CTL_178_DATA 0x56000000 -#define DDRSS1_CTL_179_DATA 0x27270056 +#define DDRSS1_CTL_176_DATA 0xF3003FF4 +#define DDRSS1_CTL_177_DATA 0x0000F3F3 +#define DDRSS1_CTL_178_DATA 0x36000000 +#define DDRSS1_CTL_179_DATA 0x27270036 #define DDRSS1_CTL_180_DATA 0x0F0F0000 #define DDRSS1_CTL_181_DATA 0x16000000 #define DDRSS1_CTL_182_DATA 0x00841616 #define DDRSS1_CTL_183_DATA 0x3FF43FF4 -#define DDRSS1_CTL_184_DATA 0x33333300 +#define DDRSS1_CTL_184_DATA 0xF3F3F300 #define DDRSS1_CTL_185_DATA 0x00000000 -#define DDRSS1_CTL_186_DATA 0x00565600 +#define DDRSS1_CTL_186_DATA 0x00363600 #define DDRSS1_CTL_187_DATA 0x00002727 #define DDRSS1_CTL_188_DATA 0x00000F0F #define DDRSS1_CTL_189_DATA 0x16161600 @@ -2430,17 +2430,17 @@ #define DDRSS1_CTL_226_DATA 0x00000000 #define DDRSS1_CTL_227_DATA 0x15110000 #define DDRSS1_CTL_228_DATA 0x00040C18 -#define DDRSS1_CTL_229_DATA 0x00000000 -#define DDRSS1_CTL_230_DATA 0x00000000 +#define DDRSS1_CTL_229_DATA 0xF000C000 +#define DDRSS1_CTL_230_DATA 0x0000F000 #define DDRSS1_CTL_231_DATA 0x00000000 #define DDRSS1_CTL_232_DATA 0x00000000 -#define DDRSS1_CTL_233_DATA 0x00000000 -#define DDRSS1_CTL_234_DATA 0x00000000 +#define DDRSS1_CTL_233_DATA 0xC0000000 +#define DDRSS1_CTL_234_DATA 0xF000F000 #define DDRSS1_CTL_235_DATA 0x00000000 #define DDRSS1_CTL_236_DATA 0x00000000 #define DDRSS1_CTL_237_DATA 0x00000000 -#define DDRSS1_CTL_238_DATA 0x00000000 -#define DDRSS1_CTL_239_DATA 0x00000000 +#define DDRSS1_CTL_238_DATA 0xF000C000 +#define DDRSS1_CTL_239_DATA 0x0000F000 #define DDRSS1_CTL_240_DATA 0x00000000 #define DDRSS1_CTL_241_DATA 0x00000000 #define DDRSS1_CTL_242_DATA 0x00030000 @@ -2468,7 +2468,7 @@ #define DDRSS1_CTL_264_DATA 0x00000040 #define DDRSS1_CTL_265_DATA 0x006B0003 #define DDRSS1_CTL_266_DATA 0x0100006B -#define DDRSS1_CTL_267_DATA 0x00000000 +#define DDRSS1_CTL_267_DATA 0x03030303 #define DDRSS1_CTL_268_DATA 0x00000000 #define DDRSS1_CTL_269_DATA 0x00000202 #define DDRSS1_CTL_270_DATA 0x00001FFF @@ -2492,7 +2492,7 @@ #define DDRSS1_CTL_288_DATA 0x00000000 #define DDRSS1_CTL_289_DATA 0x00000000 #define DDRSS1_CTL_290_DATA 0x03030300 -#define DDRSS1_CTL_291_DATA 0x00000001 +#define DDRSS1_CTL_291_DATA 0x00010101 #define DDRSS1_CTL_292_DATA 0x00000000 #define DDRSS1_CTL_293_DATA 0x00000000 #define DDRSS1_CTL_294_DATA 0x00000000 @@ -2520,7 +2520,7 @@ #define DDRSS1_CTL_316_DATA 0x01010001 #define DDRSS1_CTL_317_DATA 0x00010101 #define DDRSS1_CTL_318_DATA 0x050A0A03 -#define DDRSS1_CTL_319_DATA 0x10081F1F +#define DDRSS1_CTL_319_DATA 0x10082323 #define DDRSS1_CTL_320_DATA 0x00090310 #define DDRSS1_CTL_321_DATA 0x0B0C030F #define DDRSS1_CTL_322_DATA 0x0B0C0306 @@ -2590,30 +2590,30 @@ #define DDRSS1_CTL_386_DATA 0x00000000 #define DDRSS1_CTL_387_DATA 0x3A3A1B00 #define DDRSS1_CTL_388_DATA 0x000A0000 -#define DDRSS1_CTL_389_DATA 0x0000019C +#define DDRSS1_CTL_389_DATA 0x000000C6 #define DDRSS1_CTL_390_DATA 0x00000200 #define DDRSS1_CTL_391_DATA 0x00000200 #define DDRSS1_CTL_392_DATA 0x00000200 #define DDRSS1_CTL_393_DATA 0x00000200 -#define DDRSS1_CTL_394_DATA 0x000004D4 -#define DDRSS1_CTL_395_DATA 0x00001018 +#define DDRSS1_CTL_394_DATA 0x00000252 +#define DDRSS1_CTL_395_DATA 0x000007BC #define DDRSS1_CTL_396_DATA 0x00000204 -#define DDRSS1_CTL_397_DATA 0x000040E6 +#define DDRSS1_CTL_397_DATA 0x0000206A #define DDRSS1_CTL_398_DATA 0x00000200 #define DDRSS1_CTL_399_DATA 0x00000200 #define DDRSS1_CTL_400_DATA 0x00000200 #define DDRSS1_CTL_401_DATA 0x00000200 -#define DDRSS1_CTL_402_DATA 0x0000C2B2 -#define DDRSS1_CTL_403_DATA 0x000288FC -#define DDRSS1_CTL_404_DATA 0x00000E15 -#define DDRSS1_CTL_405_DATA 0x000040E6 +#define DDRSS1_CTL_402_DATA 0x0000613E +#define DDRSS1_CTL_403_DATA 0x00014424 +#define DDRSS1_CTL_404_DATA 0x00000E19 +#define DDRSS1_CTL_405_DATA 0x0000206A #define DDRSS1_CTL_406_DATA 0x00000200 #define DDRSS1_CTL_407_DATA 0x00000200 #define DDRSS1_CTL_408_DATA 0x00000200 #define DDRSS1_CTL_409_DATA 0x00000200 -#define DDRSS1_CTL_410_DATA 0x0000C2B2 -#define DDRSS1_CTL_411_DATA 0x000288FC -#define DDRSS1_CTL_412_DATA 0x02020E15 +#define DDRSS1_CTL_410_DATA 0x0000613E +#define DDRSS1_CTL_411_DATA 0x00014424 +#define DDRSS1_CTL_412_DATA 0x02020E19 #define DDRSS1_CTL_413_DATA 0x03030202 #define DDRSS1_CTL_414_DATA 0x00000022 #define DDRSS1_CTL_415_DATA 0x00000000 @@ -2630,7 +2630,7 @@ #define DDRSS1_CTL_426_DATA 0x00000000 #define DDRSS1_CTL_427_DATA 0x02000000 #define DDRSS1_CTL_428_DATA 0x01000404 -#define DDRSS1_CTL_429_DATA 0x0B1E0B1E +#define DDRSS1_CTL_429_DATA 0x0B220B22 #define DDRSS1_CTL_430_DATA 0x00000105 #define DDRSS1_CTL_431_DATA 0x00010101 #define DDRSS1_CTL_432_DATA 0x00010101 @@ -2673,8 +2673,8 @@ #define DDRSS1_PI_09_DATA 0x00000000 #define DDRSS1_PI_10_DATA 0x00000000 #define DDRSS1_PI_11_DATA 0x00000000 -#define DDRSS1_PI_12_DATA 0x00000007 -#define DDRSS1_PI_13_DATA 0x00010002 +#define DDRSS1_PI_12_DATA 0x00000003 +#define DDRSS1_PI_13_DATA 0x00010001 #define DDRSS1_PI_14_DATA 0x0800000F #define DDRSS1_PI_15_DATA 0x00000103 #define DDRSS1_PI_16_DATA 0x00000005 @@ -2722,18 +2722,18 @@ #define DDRSS1_PI_58_DATA 0x00000000 #define DDRSS1_PI_59_DATA 0x00000000 #define DDRSS1_PI_60_DATA 0x0A0A140A -#define DDRSS1_PI_61_DATA 0x10020101 +#define DDRSS1_PI_61_DATA 0x10020201 #define DDRSS1_PI_62_DATA 0x00020805 #define DDRSS1_PI_63_DATA 0x01000404 #define DDRSS1_PI_64_DATA 0x00000000 #define DDRSS1_PI_65_DATA 0x00000000 #define DDRSS1_PI_66_DATA 0x00000100 -#define DDRSS1_PI_67_DATA 0x0001010F +#define DDRSS1_PI_67_DATA 0x0002020F #define DDRSS1_PI_68_DATA 0x00340000 #define DDRSS1_PI_69_DATA 0x00000000 #define DDRSS1_PI_70_DATA 0x00000000 #define DDRSS1_PI_71_DATA 0x0000FFFF -#define DDRSS1_PI_72_DATA 0x00000000 +#define DDRSS1_PI_72_DATA 0x01000000 #define DDRSS1_PI_73_DATA 0x00080000 #define DDRSS1_PI_74_DATA 0x02000200 #define DDRSS1_PI_75_DATA 0x01000100 @@ -2826,33 +2826,33 @@ #define DDRSS1_PI_162_DATA 0x00000000 #define DDRSS1_PI_163_DATA 0x2B2B0200 #define DDRSS1_PI_164_DATA 0x00000034 -#define DDRSS1_PI_165_DATA 0x00000064 -#define DDRSS1_PI_166_DATA 0x00020064 +#define DDRSS1_PI_165_DATA 0x00000068 +#define DDRSS1_PI_166_DATA 0x00020068 #define DDRSS1_PI_167_DATA 0x02000200 -#define DDRSS1_PI_168_DATA 0x48120C04 -#define DDRSS1_PI_169_DATA 0x00154812 -#define DDRSS1_PI_170_DATA 0x000000CE +#define DDRSS1_PI_168_DATA 0x50120C04 +#define DDRSS1_PI_169_DATA 0x00155012 +#define DDRSS1_PI_170_DATA 0x00000063 #define DDRSS1_PI_171_DATA 0x0000032B -#define DDRSS1_PI_172_DATA 0x00002073 +#define DDRSS1_PI_172_DATA 0x00001035 #define DDRSS1_PI_173_DATA 0x0000032B -#define DDRSS1_PI_174_DATA 0x04002073 +#define DDRSS1_PI_174_DATA 0x04001035 #define DDRSS1_PI_175_DATA 0x01010404 -#define DDRSS1_PI_176_DATA 0x00001501 +#define DDRSS1_PI_176_DATA 0x00001500 #define DDRSS1_PI_177_DATA 0x00150015 #define DDRSS1_PI_178_DATA 0x01000100 #define DDRSS1_PI_179_DATA 0x00000100 #define DDRSS1_PI_180_DATA 0x00000000 #define DDRSS1_PI_181_DATA 0x01010101 -#define DDRSS1_PI_182_DATA 0x00000101 +#define DDRSS1_PI_182_DATA 0x00000000 #define DDRSS1_PI_183_DATA 0x00000000 #define DDRSS1_PI_184_DATA 0x00000000 -#define DDRSS1_PI_185_DATA 0x15040000 -#define DDRSS1_PI_186_DATA 0x0E0E0215 +#define DDRSS1_PI_185_DATA 0x19040000 +#define DDRSS1_PI_186_DATA 0x0E0E0219 #define DDRSS1_PI_187_DATA 0x00040402 #define DDRSS1_PI_188_DATA 0x000D0035 #define DDRSS1_PI_189_DATA 0x00218049 #define DDRSS1_PI_190_DATA 0x00218049 -#define DDRSS1_PI_191_DATA 0x01010101 +#define DDRSS1_PI_191_DATA 0x01000101 #define DDRSS1_PI_192_DATA 0x0004000E #define DDRSS1_PI_193_DATA 0x00040216 #define DDRSS1_PI_194_DATA 0x01000216 @@ -2874,28 +2874,28 @@ #define DDRSS1_PI_210_DATA 0x00110216 #define DDRSS1_PI_211_DATA 0x32000056 #define DDRSS1_PI_212_DATA 0x00000301 -#define DDRSS1_PI_213_DATA 0x005B0036 +#define DDRSS1_PI_213_DATA 0x005F0036 #define DDRSS1_PI_214_DATA 0x03013212 #define DDRSS1_PI_215_DATA 0x00003600 -#define DDRSS1_PI_216_DATA 0x3212005B -#define DDRSS1_PI_217_DATA 0x09000301 +#define DDRSS1_PI_216_DATA 0x3212005F +#define DDRSS1_PI_217_DATA 0x09000001 #define DDRSS1_PI_218_DATA 0x04010504 -#define DDRSS1_PI_219_DATA 0x040006C9 +#define DDRSS1_PI_219_DATA 0x04000364 #define DDRSS1_PI_220_DATA 0x0A032001 #define DDRSS1_PI_221_DATA 0x2C31110A #define DDRSS1_PI_222_DATA 0x00002918 -#define DDRSS1_PI_223_DATA 0x6001071C +#define DDRSS1_PI_223_DATA 0x6000838E #define DDRSS1_PI_224_DATA 0x1E202008 #define DDRSS1_PI_225_DATA 0x2C311116 #define DDRSS1_PI_226_DATA 0x00002918 -#define DDRSS1_PI_227_DATA 0x6001071C +#define DDRSS1_PI_227_DATA 0x6000838E #define DDRSS1_PI_228_DATA 0x1E202008 -#define DDRSS1_PI_229_DATA 0x00019C16 -#define DDRSS1_PI_230_DATA 0x00001018 -#define DDRSS1_PI_231_DATA 0x000040E6 -#define DDRSS1_PI_232_DATA 0x000288FC -#define DDRSS1_PI_233_DATA 0x000040E6 -#define DDRSS1_PI_234_DATA 0x000288FC +#define DDRSS1_PI_229_DATA 0x0000C616 +#define DDRSS1_PI_230_DATA 0x000007BC +#define DDRSS1_PI_231_DATA 0x0000206A +#define DDRSS1_PI_232_DATA 0x00014424 +#define DDRSS1_PI_233_DATA 0x0000206A +#define DDRSS1_PI_234_DATA 0x00014424 #define DDRSS1_PI_235_DATA 0x033B0016 #define DDRSS1_PI_236_DATA 0x0303033B #define DDRSS1_PI_237_DATA 0x002AF803 @@ -2936,29 +2936,29 @@ #define DDRSS1_PI_272_DATA 0x00080804 #define DDRSS1_PI_273_DATA 0x00000000 #define DDRSS1_PI_274_DATA 0x00000000 -#define DDRSS1_PI_275_DATA 0x00330084 +#define DDRSS1_PI_275_DATA 0x00F30084 #define DDRSS1_PI_276_DATA 0x00160000 -#define DDRSS1_PI_277_DATA 0x56333FF4 +#define DDRSS1_PI_277_DATA 0x36F33FF4 #define DDRSS1_PI_278_DATA 0x00160F27 -#define DDRSS1_PI_279_DATA 0x56333FF4 +#define DDRSS1_PI_279_DATA 0x36F33FF4 #define DDRSS1_PI_280_DATA 0x00160F27 -#define DDRSS1_PI_281_DATA 0x00330084 +#define DDRSS1_PI_281_DATA 0x00F30084 #define DDRSS1_PI_282_DATA 0x00160000 -#define DDRSS1_PI_283_DATA 0x56333FF4 +#define DDRSS1_PI_283_DATA 0x36F33FF4 #define DDRSS1_PI_284_DATA 0x00160F27 -#define DDRSS1_PI_285_DATA 0x56333FF4 +#define DDRSS1_PI_285_DATA 0x36F33FF4 #define DDRSS1_PI_286_DATA 0x00160F27 -#define DDRSS1_PI_287_DATA 0x00330084 +#define DDRSS1_PI_287_DATA 0x00F30084 #define DDRSS1_PI_288_DATA 0x00160000 -#define DDRSS1_PI_289_DATA 0x56333FF4 +#define DDRSS1_PI_289_DATA 0x36F33FF4 #define DDRSS1_PI_290_DATA 0x00160F27 -#define DDRSS1_PI_291_DATA 0x56333FF4 +#define DDRSS1_PI_291_DATA 0x36F33FF4 #define DDRSS1_PI_292_DATA 0x00160F27 -#define DDRSS1_PI_293_DATA 0x00330084 +#define DDRSS1_PI_293_DATA 0x00F30084 #define DDRSS1_PI_294_DATA 0x00160000 -#define DDRSS1_PI_295_DATA 0x56333FF4 +#define DDRSS1_PI_295_DATA 0x36F33FF4 #define DDRSS1_PI_296_DATA 0x00160F27 -#define DDRSS1_PI_297_DATA 0x56333FF4 +#define DDRSS1_PI_297_DATA 0x36F33FF4 #define DDRSS1_PI_298_DATA 0x00160F27 #define DDRSS1_PI_299_DATA 0x00000000 @@ -2974,7 +2974,7 @@ #define DDRSS1_PHY_09_DATA 0x00000000 #define DDRSS1_PHY_10_DATA 0x00000000 #define DDRSS1_PHY_11_DATA 0x01000001 -#define DDRSS1_PHY_12_DATA 0x00000100 +#define DDRSS1_PHY_12_DATA 0x00000200 #define DDRSS1_PHY_13_DATA 0x000800C0 #define DDRSS1_PHY_14_DATA 0x060100CC #define DDRSS1_PHY_15_DATA 0x00030066 @@ -2993,8 +2993,8 @@ #define DDRSS1_PHY_28_DATA 0x2A000000 #define DDRSS1_PHY_29_DATA 0x00000808 #define DDRSS1_PHY_30_DATA 0x0F000000 -#define DDRSS1_PHY_31_DATA 0x00000F0F -#define DDRSS1_PHY_32_DATA 0x10200000 +#define DDRSS1_PHY_31_DATA 0x00000F08 +#define DDRSS1_PHY_32_DATA 0x10400000 #define DDRSS1_PHY_33_DATA 0x0C002006 #define DDRSS1_PHY_34_DATA 0x00000000 #define DDRSS1_PHY_35_DATA 0x00000000 @@ -3062,9 +3062,9 @@ #define DDRSS1_PHY_97_DATA 0x00050010 #define DDRSS1_PHY_98_DATA 0x51517041 #define DDRSS1_PHY_99_DATA 0x31C06001 -#define DDRSS1_PHY_100_DATA 0x07AB0340 +#define DDRSS1_PHY_100_DATA 0x07AB01AB #define DDRSS1_PHY_101_DATA 0x00C0C001 -#define DDRSS1_PHY_102_DATA 0x0E0D0001 +#define DDRSS1_PHY_102_DATA 0x0E0D0101 #define DDRSS1_PHY_103_DATA 0x10001000 #define DDRSS1_PHY_104_DATA 0x0C083E42 #define DDRSS1_PHY_105_DATA 0x0F0C3701 @@ -3098,7 +3098,7 @@ #define DDRSS1_PHY_133_DATA 0x00000000 #define DDRSS1_PHY_134_DATA 0x00080200 #define DDRSS1_PHY_135_DATA 0x00000000 -#define DDRSS1_PHY_136_DATA 0x20202000 +#define DDRSS1_PHY_136_DATA 0x20202020 #define DDRSS1_PHY_137_DATA 0x20202020 #define DDRSS1_PHY_138_DATA 0xF0F02020 #define DDRSS1_PHY_139_DATA 0x00000000 @@ -3230,7 +3230,7 @@ #define DDRSS1_PHY_265_DATA 0x00000000 #define DDRSS1_PHY_266_DATA 0x00000000 #define DDRSS1_PHY_267_DATA 0x01000001 -#define DDRSS1_PHY_268_DATA 0x00000100 +#define DDRSS1_PHY_268_DATA 0x00000200 #define DDRSS1_PHY_269_DATA 0x000800C0 #define DDRSS1_PHY_270_DATA 0x060100CC #define DDRSS1_PHY_271_DATA 0x00030066 @@ -3249,8 +3249,8 @@ #define DDRSS1_PHY_284_DATA 0x2A000000 #define DDRSS1_PHY_285_DATA 0x00000808 #define DDRSS1_PHY_286_DATA 0x0F000000 -#define DDRSS1_PHY_287_DATA 0x00000F0F -#define DDRSS1_PHY_288_DATA 0x10200000 +#define DDRSS1_PHY_287_DATA 0x00000F08 +#define DDRSS1_PHY_288_DATA 0x10400000 #define DDRSS1_PHY_289_DATA 0x0C002006 #define DDRSS1_PHY_290_DATA 0x00000000 #define DDRSS1_PHY_291_DATA 0x00000000 @@ -3318,9 +3318,9 @@ #define DDRSS1_PHY_353_DATA 0x00050010 #define DDRSS1_PHY_354_DATA 0x51517041 #define DDRSS1_PHY_355_DATA 0x31C06001 -#define DDRSS1_PHY_356_DATA 0x07AB0340 +#define DDRSS1_PHY_356_DATA 0x07AB01AB #define DDRSS1_PHY_357_DATA 0x00C0C001 -#define DDRSS1_PHY_358_DATA 0x0E0D0001 +#define DDRSS1_PHY_358_DATA 0x0E0D0101 #define DDRSS1_PHY_359_DATA 0x10001000 #define DDRSS1_PHY_360_DATA 0x0C083E42 #define DDRSS1_PHY_361_DATA 0x0F0C3701 @@ -3354,7 +3354,7 @@ #define DDRSS1_PHY_389_DATA 0x00000000 #define DDRSS1_PHY_390_DATA 0x00080200 #define DDRSS1_PHY_391_DATA 0x00000000 -#define DDRSS1_PHY_392_DATA 0x20202000 +#define DDRSS1_PHY_392_DATA 0x20202020 #define DDRSS1_PHY_393_DATA 0x20202020 #define DDRSS1_PHY_394_DATA 0xF0F02020 #define DDRSS1_PHY_395_DATA 0x00000000 @@ -3486,7 +3486,7 @@ #define DDRSS1_PHY_521_DATA 0x00000000 #define DDRSS1_PHY_522_DATA 0x00000000 #define DDRSS1_PHY_523_DATA 0x01000001 -#define DDRSS1_PHY_524_DATA 0x00000100 +#define DDRSS1_PHY_524_DATA 0x00000200 #define DDRSS1_PHY_525_DATA 0x000800C0 #define DDRSS1_PHY_526_DATA 0x060100CC #define DDRSS1_PHY_527_DATA 0x00030066 @@ -3505,8 +3505,8 @@ #define DDRSS1_PHY_540_DATA 0x2A000000 #define DDRSS1_PHY_541_DATA 0x00000808 #define DDRSS1_PHY_542_DATA 0x0F000000 -#define DDRSS1_PHY_543_DATA 0x00000F0F -#define DDRSS1_PHY_544_DATA 0x10200000 +#define DDRSS1_PHY_543_DATA 0x00000F08 +#define DDRSS1_PHY_544_DATA 0x10400000 #define DDRSS1_PHY_545_DATA 0x0C002006 #define DDRSS1_PHY_546_DATA 0x00000000 #define DDRSS1_PHY_547_DATA 0x00000000 @@ -3574,9 +3574,9 @@ #define DDRSS1_PHY_609_DATA 0x00050010 #define DDRSS1_PHY_610_DATA 0x51517041 #define DDRSS1_PHY_611_DATA 0x31C06001 -#define DDRSS1_PHY_612_DATA 0x07AB0340 +#define DDRSS1_PHY_612_DATA 0x07AB01AB #define DDRSS1_PHY_613_DATA 0x00C0C001 -#define DDRSS1_PHY_614_DATA 0x0E0D0001 +#define DDRSS1_PHY_614_DATA 0x0E0D0101 #define DDRSS1_PHY_615_DATA 0x10001000 #define DDRSS1_PHY_616_DATA 0x0C083E42 #define DDRSS1_PHY_617_DATA 0x0F0C3701 @@ -3610,7 +3610,7 @@ #define DDRSS1_PHY_645_DATA 0x00000000 #define DDRSS1_PHY_646_DATA 0x00080200 #define DDRSS1_PHY_647_DATA 0x00000000 -#define DDRSS1_PHY_648_DATA 0x20202000 +#define DDRSS1_PHY_648_DATA 0x20202020 #define DDRSS1_PHY_649_DATA 0x20202020 #define DDRSS1_PHY_650_DATA 0xF0F02020 #define DDRSS1_PHY_651_DATA 0x00000000 @@ -3742,7 +3742,7 @@ #define DDRSS1_PHY_777_DATA 0x00000000 #define DDRSS1_PHY_778_DATA 0x00000000 #define DDRSS1_PHY_779_DATA 0x01000001 -#define DDRSS1_PHY_780_DATA 0x00000100 +#define DDRSS1_PHY_780_DATA 0x00000200 #define DDRSS1_PHY_781_DATA 0x000800C0 #define DDRSS1_PHY_782_DATA 0x060100CC #define DDRSS1_PHY_783_DATA 0x00030066 @@ -3761,8 +3761,8 @@ #define DDRSS1_PHY_796_DATA 0x2A000000 #define DDRSS1_PHY_797_DATA 0x00000808 #define DDRSS1_PHY_798_DATA 0x0F000000 -#define DDRSS1_PHY_799_DATA 0x00000F0F -#define DDRSS1_PHY_800_DATA 0x10200000 +#define DDRSS1_PHY_799_DATA 0x00000F08 +#define DDRSS1_PHY_800_DATA 0x10400000 #define DDRSS1_PHY_801_DATA 0x0C002006 #define DDRSS1_PHY_802_DATA 0x00000000 #define DDRSS1_PHY_803_DATA 0x00000000 @@ -3830,9 +3830,9 @@ #define DDRSS1_PHY_865_DATA 0x00050010 #define DDRSS1_PHY_866_DATA 0x51517041 #define DDRSS1_PHY_867_DATA 0x31C06001 -#define DDRSS1_PHY_868_DATA 0x07AB0340 +#define DDRSS1_PHY_868_DATA 0x07AB01AB #define DDRSS1_PHY_869_DATA 0x00C0C001 -#define DDRSS1_PHY_870_DATA 0x0E0D0001 +#define DDRSS1_PHY_870_DATA 0x0E0D0101 #define DDRSS1_PHY_871_DATA 0x10001000 #define DDRSS1_PHY_872_DATA 0x0C083E42 #define DDRSS1_PHY_873_DATA 0x0F0C3701 @@ -3866,7 +3866,7 @@ #define DDRSS1_PHY_901_DATA 0x00000000 #define DDRSS1_PHY_902_DATA 0x00080200 #define DDRSS1_PHY_903_DATA 0x00000000 -#define DDRSS1_PHY_904_DATA 0x20202000 +#define DDRSS1_PHY_904_DATA 0x20202020 #define DDRSS1_PHY_905_DATA 0x20202020 #define DDRSS1_PHY_906_DATA 0xF0F02020 #define DDRSS1_PHY_907_DATA 0x00000000 @@ -4265,14 +4265,14 @@ #define DDRSS1_PHY_1300_DATA 0x00040101 #define DDRSS1_PHY_1301_DATA 0x0000010F #define DDRSS1_PHY_1302_DATA 0x00000000 -#define DDRSS1_PHY_1303_DATA 0x0000FFFF +#define DDRSS1_PHY_1303_DATA 0x00000064 #define DDRSS1_PHY_1304_DATA 0x00000000 #define DDRSS1_PHY_1305_DATA 0x01010000 #define DDRSS1_PHY_1306_DATA 0x01080402 #define DDRSS1_PHY_1307_DATA 0x01200F02 #define DDRSS1_PHY_1308_DATA 0x00194280 #define DDRSS1_PHY_1309_DATA 0x00000004 -#define DDRSS1_PHY_1310_DATA 0x00052000 +#define DDRSS1_PHY_1310_DATA 0x00042000 #define DDRSS1_PHY_1311_DATA 0x00000000 #define DDRSS1_PHY_1312_DATA 0x00000000 #define DDRSS1_PHY_1313_DATA 0x00000000 @@ -4359,7 +4359,7 @@ #define DDRSS1_PHY_1394_DATA 0x00000003 #define DDRSS1_PHY_1395_DATA 0x00000000 #define DDRSS1_PHY_1396_DATA 0x00001142 -#define DDRSS1_PHY_1397_DATA 0x010207AB +#define DDRSS1_PHY_1397_DATA 0x040207AB #define DDRSS1_PHY_1398_DATA 0x01000080 #define DDRSS1_PHY_1399_DATA 0x03900390 #define DDRSS1_PHY_1400_DATA 0x03900390 diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c index 0e5d44269eb..8fa36f7b913 100644 --- a/arch/arm/mach-k3/am625_init.c +++ b/arch/arm/mach-k3/am625_init.c @@ -80,8 +80,6 @@ static __maybe_unused void enable_mcu_esm_reset(void) writel(stat, CTRLMMR_MCU_RST_CTRL); } -#if defined(CONFIG_CPU_V7R) - /* * RTC Erratum i2327 Workaround for Silicon Revision 1 * @@ -94,7 +92,7 @@ static __maybe_unused void enable_mcu_esm_reset(void) * * https://www.ti.com/lit/er/sprz487c/sprz487c.pdf */ -void rtc_erratumi2327_init(void) +static __maybe_unused void rtc_erratumi2327_init(void) { u32 counter; @@ -112,19 +110,17 @@ void rtc_erratumi2327_init(void) */ writel(K3RTC_KICK0_UNLOCK_VALUE, REG_K3RTC_KICK0); writel(K3RTC_KICK1_UNLOCK_VALUE, REG_K3RTC_KICK1); - return; } -#endif void board_init_f(ulong dummy) { struct udevice *dev; int ret; -#if defined(CONFIG_CPU_V7R) - setup_k3_mpu_regions(); - rtc_erratumi2327_init(); -#endif + if (IS_ENABLED(CONFIG_CPU_V7R)) { + setup_k3_mpu_regions(); + rtc_erratumi2327_init(); + } /* * Cannot delay this further as there is a chance that @@ -156,29 +152,28 @@ void board_init_f(ulong dummy) preloader_console_init(); -#ifdef CONFIG_K3_EARLY_CONS /* * Allow establishing an early console as required for example when * doing a UART-based boot. Note that this console may not "survive" * through a SYSFW PM-init step and will need a re-init in some way * due to changing module clock frequencies. */ - early_console_init(); -#endif + if (IS_ENABLED(CONFIG_K3_EARLY_CONS)) + early_console_init(); -#if defined(CONFIG_K3_LOAD_SYSFW) /* * Configure and start up system controller firmware. Provide * the U-Boot console init function to the SYSFW post-PM configuration * callback hook, effectively switching on (or over) the console * output. */ - ret = is_rom_loaded_sysfw(&bootdata); - if (!ret) - panic("ROM has not loaded TIFS firmware\n"); + if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) { + ret = is_rom_loaded_sysfw(&bootdata); + if (!ret) + panic("ROM has not loaded TIFS firmware\n"); - k3_sysfw_loader(true, NULL, NULL); -#endif + k3_sysfw_loader(true, NULL, NULL); + } /* * Force probe of clk_k3 driver here to ensure basic default clock @@ -209,11 +204,11 @@ void board_init_f(ulong dummy) enable_mcu_esm_reset(); } -#if defined(CONFIG_K3_AM64_DDRSS) - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) - panic("DRAM init failed: %d\n", ret); -#endif + if (IS_ENABLED(CONFIG_K3_AM64_DDRSS)) { + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) + panic("DRAM init failed: %d\n", ret); + } spl_enable_dcache(); } @@ -225,9 +220,15 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; - switch (bootmode) { case BOOT_DEVICE_EMMC: + if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) { + if (spl_mmc_emmc_boot_partition(mmc)) + return MMCSD_MODE_EMMCBOOT; + return MMCSD_MODE_FS; + } + if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4)) + return MMCSD_MODE_FS; return MMCSD_MODE_EMMCBOOT; case BOOT_DEVICE_MMC: if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK) diff --git a/board/siemens/iot2050/iot2050.env b/board/siemens/iot2050/iot2050.env index caa9f80e3fc..8bbd7abe98f 100644 --- a/board/siemens/iot2050/iot2050.env +++ b/board/siemens/iot2050/iot2050.env @@ -6,7 +6,7 @@ * Jan Kiszka */ -#include +#include usb_pgood_delay=900 diff --git a/board/ti/am62ax/am62ax.env b/board/ti/am62ax/am62ax.env index 3f7c333fa40..bfed7f36084 100644 --- a/board/ti/am62ax/am62ax.env +++ b/board/ti/am62ax/am62ax.env @@ -1,4 +1,4 @@ -#include +#include #include default_device_tree=ti/k3-am62a7-sk.dtb diff --git a/board/ti/am62x/MAINTAINERS b/board/ti/am62x/MAINTAINERS index 105e741995e..6ac4e65f5af 100644 --- a/board/ti/am62x/MAINTAINERS +++ b/board/ti/am62x/MAINTAINERS @@ -6,3 +6,10 @@ F: board/ti/am62x/ F: include/configs/am62x_evm.h F: configs/am62x_evm_r5_defconfig F: configs/am62x_evm_a53_defconfig + +BEAGLEPLAY BOARD +M: Nishanth Menon +M: Robert Nelson +M: Tom Rini +S: Maintained +N: beagleplay diff --git a/board/ti/am62x/am62x.env b/board/ti/am62x/am62x.env index f2dc87893a9..3b79ae1b3f0 100644 --- a/board/ti/am62x/am62x.env +++ b/board/ti/am62x/am62x.env @@ -1,16 +1,14 @@ -#include +#include +#include #include -default_device_tree=ti/k3-am625-sk.dtb -findfdt= - setenv name_fdt ${default_device_tree}; - setenv fdtfile ${name_fdt} name_kern=Image console=ttyS2,115200n8 args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000 ${mtdparts} run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr} +boot_targets=ti_mmc mmc0 mmc1 usb pxe dhcp boot=mmc mmcdev=1 bootpart=1:2 diff --git a/board/ti/am62x/beagleplay.env b/board/ti/am62x/beagleplay.env new file mode 100644 index 00000000000..4f0a94a8113 --- /dev/null +++ b/board/ti/am62x/beagleplay.env @@ -0,0 +1,19 @@ +#include +#include +#include + +name_kern=Image +console=ttyS2,115200n8 +args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000 +run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr} +set_led_state_fail_load= led led-0 off; led led-1 on; + led led-2 off; led led-3 on; led led-4 off +set_led_state_start_load=led led-0 on; led led-1 off; + led led-2 on; led led-3 off; led led-4 on +boot=mmc +mmcdev=1 +bootpart=1:1 +bootdir=/boot +boot_targets=mmc1 mmc0 usb pxe +bootmeths=script extlinux efi pxe +rd_spec=- diff --git a/board/ti/am62x/beagleplay_a53.config b/board/ti/am62x/beagleplay_a53.config new file mode 100644 index 00000000000..f0380416cc5 --- /dev/null +++ b/board/ti/am62x/beagleplay_a53.config @@ -0,0 +1,55 @@ +# Defconfig fragment to apply on top of am62x_evm_a53_defconfig + +CONFIG_DEFAULT_DEVICE_TREE="k3-am625-beagleplay" +CONFIG_OF_LIST="k3-am625-beagleplay" +CONFIG_SPL_OF_LIST="k3-am625-beagleplay" +CONFIG_BOOTCOMMAND="run set_led_state_start_load;run findfdt; run envboot; bootflow scan -lb;run set_led_state_fail_load" +CONFIG_EXT4_WRITE=y +CONFIG_LZO=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" +CONFIG_AUTOBOOT_DELAY_STR="d" +CONFIG_AUTOBOOT_STOP_STR=" " +# Use the Beagleplay env file +CONFIG_ENV_SOURCE_FILE="beagleplay" +# Do not use emmc boot - we will use FS only +CONFIG_SUPPORT_EMMC_BOOT=n +CONFIG_MMC_IO_VOLTAGE=y +# CONFIG_SPL_MMC_IO_VOLTAGE is not set +CONFIG_MMC_UHS_SUPPORT=y +# CONFIG_SPL_MMC_UHS_SUPPORT is not set +CONFIG_MMC_HS200_SUPPORT=y +# CONFIG_SPL_MMC_HS200_SUPPORT is not set +# Enable GPIO control +CONFIG_DM_GPIO=y +CONFIG_SPL_GPIO=y +CONFIG_DA8XX_GPIO=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPIO_READ=y +# Enable LEDs +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_SPL_LED=y +CONFIG_SPL_LED_GPIO=y +# Enable I2C bus +CONFIG_SPL_I2C=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_CMD_I2C=y +# Regulator +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_CMD_REGULATOR=y +CONFIG_DM_REGULATOR_TPS65219=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_TPS65219=y +CONFIG_CMD_PMIC=y +# Uses Realtek phy rather than TI phy +CONFIG_PHY_TI_DP83867=n +CONFIG_PHY_REALTEK=y +# No SPI flash on Beagleplay +CONFIG_SPI=n +CONFIG_SPI_FLASH=n +CONFIG_SPL_DM_SPI_FLASH=n +CONFIG_SPL_SPI_FLASH_SUPPORT=n diff --git a/board/ti/am62x/beagleplay_r5.config b/board/ti/am62x/beagleplay_r5.config new file mode 100644 index 00000000000..4ee0375a2a1 --- /dev/null +++ b/board/ti/am62x/beagleplay_r5.config @@ -0,0 +1,15 @@ +# Defconfig fragment to apply on top of: +# am62x_evm_r5_defconfig +# +CONFIG_DEFAULT_DEVICE_TREE="k3-am625-r5-beagleplay" +CONFIG_OF_LIST="k3-am625-r5-beagleplay" +CONFIG_SPL_OF_LIST="k3-am625-r5-beagleplay" +# Do spl board init +CONFIG_SPL_BOARD_INIT=y +# Do not use emmc boot - we will use FS only +CONFIG_SUPPORT_EMMC_BOOT=n +# No SPI flash on Beagleplay +CONFIG_SPI=n +CONFIG_SPI_FLASH=n +CONFIG_SPL_DM_SPI_FLASH=n +CONFIG_SPL_SPI_FLASH_SUPPORT=n diff --git a/board/ti/am64x/am64x.env b/board/ti/am64x/am64x.env index 1567907fcbd..68e42222b7f 100644 --- a/board/ti/am64x/am64x.env +++ b/board/ti/am64x/am64x.env @@ -1,4 +1,4 @@ -#include +#include #include #include diff --git a/board/ti/am65x/am65x.env b/board/ti/am65x/am65x.env index 755bff2707c..286b9c300c0 100644 --- a/board/ti/am65x/am65x.env +++ b/board/ti/am65x/am65x.env @@ -1,4 +1,4 @@ -#include +#include #include #include #if CONFIG_CMD_REMOTEPROC diff --git a/board/ti/j721e/j721e.env b/board/ti/j721e/j721e.env index 2f2fb059127..8cc8232fc13 100644 --- a/board/ti/j721e/j721e.env +++ b/board/ti/j721e/j721e.env @@ -1,4 +1,4 @@ -#include +#include #include #include #include diff --git a/board/ti/j721s2/j721s2.env b/board/ti/j721s2/j721s2.env index 6825b146985..64e3d9da85f 100644 --- a/board/ti/j721s2/j721s2.env +++ b/board/ti/j721s2/j721s2.env @@ -1,4 +1,4 @@ -#include +#include #include #include #include diff --git a/board/ti/ks2_evm/k2e_evm.env b/board/ti/ks2_evm/k2e_evm.env index a145db53e5f..3dbb7934c59 100644 --- a/board/ti/ks2_evm/k2e_evm.env +++ b/board/ti/ks2_evm/k2e_evm.env @@ -1,4 +1,4 @@ -#include +#include #include findfdt=setenv fdtfile ${name_fdt} diff --git a/board/ti/ks2_evm/k2g_evm.env b/board/ti/ks2_evm/k2g_evm.env index 4f4941dd090..2b500fc6edf 100644 --- a/board/ti/ks2_evm/k2g_evm.env +++ b/board/ti/ks2_evm/k2g_evm.env @@ -1,4 +1,4 @@ -#include +#include #include #include diff --git a/board/ti/ks2_evm/k2hk_evm.env b/board/ti/ks2_evm/k2hk_evm.env index 0714a51090e..9991b76f8fc 100644 --- a/board/ti/ks2_evm/k2hk_evm.env +++ b/board/ti/ks2_evm/k2hk_evm.env @@ -1,4 +1,4 @@ -#include +#include #include findfdt=setenv fdtfile ${name_fdt} diff --git a/board/ti/ks2_evm/k2l_evm.env b/board/ti/ks2_evm/k2l_evm.env index e8a803a4ed7..4e2debca4bd 100644 --- a/board/ti/ks2_evm/k2l_evm.env +++ b/board/ti/ks2_evm/k2l_evm.env @@ -1,4 +1,4 @@ -#include +#include #include findfdt=setenv fdtfile ${name_fdt} diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c index a3d1d07a0cb..d09dda5bccc 100644 --- a/board/toradex/verdin-am62/verdin-am62.c +++ b/board/toradex/verdin-am62/verdin-am62.c @@ -28,8 +28,8 @@ int dram_init(void) { gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE); - if (gd->ram_size < SZ_64M) - puts("## WARNING: Less than 64MB RAM detected\n"); + if (gd->ram_size < SZ_512M) + puts("## WARNING: Less than 512MB RAM detected\n"); return 0; } diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig index d55caabe22c..a2729c1d0e3 100644 --- a/configs/am62x_evm_a53_defconfig +++ b/configs/am62x_evm_a53_defconfig @@ -25,11 +25,13 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y +# CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 -CONFIG_DISTRO_DEFAULTS=y -CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;" +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTSTD_DEFAULTS=y +CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x80c80000 @@ -69,6 +71,7 @@ CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig index 3c5f3672984..489ee943fe3 100644 --- a/configs/am62x_evm_r5_defconfig +++ b/configs/am62x_evm_r5_defconfig @@ -92,6 +92,7 @@ CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_SPL_MISC=y CONFIG_ESM_K3=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y diff --git a/doc/board/ti/am62x_beagleplay.rst b/doc/board/ti/am62x_beagleplay.rst new file mode 100644 index 00000000000..39913b29ab2 --- /dev/null +++ b/doc/board/ti/am62x_beagleplay.rst @@ -0,0 +1,322 @@ +.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +.. sectionauthor:: Nishanth Menon + +AM62x Beagleboard.org Beagleplay +================================ + +Introduction: +------------- + +BeagleBoard.org BeaglePlay is an easy to use, affordable open source +hardware single board computer based on the Texas Instruments AM625 +SoC that allows you to create connected devices that work even at long +distances using IEEE 802.15.4g LR-WPAN and IEEE 802.3cg 10Base-T1L. +Expansion is provided over open standards based mikroBUS, Grove and +QWIIC headers among other interfaces. + +Further information can be found at: + +* Product Page: https://beagleplay.org/ +* Hardware documentation: https://git.beagleboard.org/beagleplay/beagleplay + +Boot Flow: +---------- +Below is the pictorial representation of boot flow: + +.. image:: img/boot_diagram_k3_current.svg + :alt: Boot flow diagram + +- On this platform, 'TI Foundational Security' (TIFS) functions as the + security enclave master while 'Device Manager' (DM), also known as the + 'TISCI server' in "TI terminology", offers all the essential services. + The A53 or M4F (Aux core) sends requests to TIFS/DM to accomplish these + services, as illustrated in the diagram above. + +Sources: +-------- +.. include:: k3.rst + :start-after: .. k3_rst_include_start_boot_sources + :end-before: .. k3_rst_include_end_boot_sources + +Build procedure: +---------------- +0. Setup the environment variables: + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_common_env_vars_desc + :end-before: .. k3_rst_include_end_common_env_vars_desc + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_board_env_vars_desc + :end-before: .. k3_rst_include_end_board_env_vars_desc + +Set the variables corresponding to this platform: + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_common_env_vars_defn + :end-before: .. k3_rst_include_end_common_env_vars_defn +.. code-block:: bash + + $ export UBOOT_CFG_CORTEXR="am62x_evm_r5_defconfig beagleplay_r5.config" + $ export UBOOT_CFG_CORTEXA="am62x_evm_a53_defconfig beagleplay_a53.config" + $ export TFA_BOARD=lite + $ # we dont use any extra TFA parameters + $ unset TFA_EXTRA_ARGS + $ export OPTEE_PLATFORM=k3-am62x + $ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y" + +.. include:: am62x_sk.rst + :start-after: .. am62x_evm_rst_include_start_build_steps + :end-before: .. am62x_evm_rst_include_end_build_steps + +Target Images +-------------- +Copy the below images to an SD card and boot: + +* tiboot3-am62x-gp-evm.bin from R5 build as tiboot3.bin +* tispl.bin_unsigned from Cortex-A build as tispl.bin +* u-boot.img_unsigned from Cortex-A build as u-boot.img + +Image formats +------------- + +- tiboot3.bin + +.. image:: img/multi_cert_tiboot3.bin.svg + :alt: tiboot3.bin image format + +- tispl.bin + +.. image:: img/dm_tispl.bin.svg + :alt: tispl.bin image format + +Additional hardware for U-Boot development +------------------------------------------ + +* Serial Console is critical for U-Boot development on BeaglePlay. See + `BeaglePlay serial console documentation + `_. +* uSD is preferred option over eMMC, and a SD/MMC reader will be needed. +* (optionally) JTAG is useful when working with very early stages of boot. + +Default storage options +----------------------- + +There are multiple storage media options on BeaglePlay, but primarily: + +* Onboard eMMC (default) - reliable, fast and meant for deployment use. +* SD/MMC card interface (hold 'USR' switch and power on) - Entirely + depends on the SD card quality. + +Flash to uSD card or how to deal with "bricked" Board +-------------------------------------------------------- + +When deploying or working on Linux, it's common to use the onboard +eMMC. However, avoiding the eMMC and using the uSD card is safer when +working with U-Boot. + +If you choose to hand format your own bootable uSD card, be +aware that it can be difficult. The following information +may be helpful, but remember that it is only sometimes +reliable, and partition options can cause issues. These +can potentially help: + +* https://git.ti.com/cgit/arago-project/tisdk-setup-scripts/tree/create-sdcard.sh +* https://elinux.org/Beagleboard:Expanding_File_System_Partition_On_A_microSD + +The simplest option is to start with a standard distribution +image like those in `BeagleBoard.org Distros Page +`_ and download a disk image for +BeaglePlay. Pick a 16GB+ uSD card to be on the safer side. + +With an SD/MMC Card reader and `Balena Etcher +`_, having a functional setup in minutes is +a trivial matter, and it works on almost all Host Operating Systems. +Yes Windows users, Windows Subsystem for Linux(WSL) based development +with U-Boot and update uSD card is practical. + +Updating U-Boot is a matter of copying the tiboot3.bin, tispl.bin and +u-boot.img to the "BOOT" partition of the uSD card. Remember to sync +and unmount (or Eject - depending on the Operating System) the uSD +card prior to physically removing from SD card reader. + +Also see following section on switch setting used for booting using +uSD card. + +.. note:: + Great news! If the board has not been damaged physically, there's no + need to worry about it being "bricked" on this platform. You only have + to flash an uSD card, plug it in, and reinstall the image on eMMC. This + means that even if you make a mistake, you can quickly fix it and rest + easy. + + If you are frequently working with uSD cards, you might find the + following useful: + + * `USB-SD-Mux `_ + * `SD-Wire `_ + +Flash to eMMC +------------- + +The eMMC layout selected is user-friendly for developers. The +boot hardware partition of the eMMC only contains the fixed-size +tiboot3.bin image. This is because the contents of the boot partitions +need to run from the SoC's internal SRAM, which remains a fixed size +constant. The other components of the boot sequence, such as tispl.bin +and u-boot.img, are located in the /BOOT partition in the User Defined +Area (UDA) hardware partition of the eMMC. These components can vary +significantly in size. The choice of keeping tiboot3.bin in boot0 or +boot1 partition depends on A/B update requirements. + +.. image:: img/beagleplay_emmc.svg + :alt: eMMC partitions and boot file organization for BeaglePlay + +The following are the steps from Linux shell to program eMMC: + +.. code-block:: bash + + # # Enable Boot0 boot + # mmc bootpart enable 1 2 /dev/mmcblk0 + # mmc bootbus set single_backward x1 x8 /dev/mmcblk0 + # mmc hwreset enable /dev/mmcblk0 + + # # Clear eMMC boot0 + # echo '0' >> /sys/class/block/mmcblk0boot0/force_ro + # dd if=/dev/zero of=/dev/mmcblk0boot0 count=32 bs=128k + # # Write tiboot3.bin + # dd if=tiboot3.bin of=/dev/mmcblk0boot0 bs=128k + + # # Copy the rest of the boot binaries + # mount /dev/mmcblk0p1 /boot/firmware + # cp tispl.bin /boot/firmware + # cp u-boot.img /boot/firmware + # sync + +.. warning :: + + U-Boot is configured to prioritize booting from an SD card if it + detects a valid boot partition and boot files on it, even if the + system initially booted from eMMC. The boot order is set as follows: + + * SD/MMC + * eMMC + * USB + * PXE + +LED patterns during boot +------------------------ + +.. list-table:: USR LED status indication + :widths: 16 16 + :header-rows: 1 + + * - USR LEDs (012345) + - Indicates + + * - 00000 + - Boot failure or R5 image not started up + + * - 11111 + - A53 SPL/U-boot has started up + + * - 10101 + - OS boot process has been initiated + + * - 01010 + - OS boot process failed and drops to U-Boot shell + +.. note :: + + In the table above, 0 indicates LED switched off and 1 indicates LED + switched ON. + +.. warning :: + + If the "red" power LED is not glowing, the system power supply is not + functional. Please refer to `BeaglePlay documentation + `_ for further information. + +A53 SPL DDR Memory Layout +------------------------- + +.. include:: am62x_sk.rst + :start-after: .. am62x_evm_rst_include_start_ddr_mem_layout + :end-before: .. am62x_evm_rst_include_end_ddr_mem_layout + +Switch Setting for Boot Mode +---------------------------- + +The boot time option is configured via "USR" button on the board. +See `Beagleplay Schematics `_ +for details. + +.. list-table:: Boot Modes + :widths: 16 16 16 + :header-rows: 1 + + * - USR Switch Position + - Primary Boot + - Secondary Boot + + * - Not Pressed + - eMMC + - UART + + * - Pressed + - SD/MMC File System (FS) mode + - USB Device Firmware Upgrade (DFU) mode + +To switch to SD card boot mode, hold the USR button while powering on +with Type-C power supply, then release when power LED lights up. + +Debugging U-Boot +---------------- + +See :ref:`Common Debugging environment - OpenOCD`: for +detailed setup and debugging information. + +.. warning:: + + **OpenOCD support since**: v0.12.0 + + If the default package version of OpenOCD in your development + environment's distribution needs to be updated, it might be necessary to + build OpenOCD from the source. + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_openocd_connect_tag_connect + :end-before: .. k3_rst_include_end_openocd_connect_tag_connect + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_openocd_cfg_external_intro + :end-before: .. k3_rst_include_end_openocd_cfg_external_intro + +For example, with BeaglePlay (AM62X platform), the openocd_connect.cfg: + +.. code-block:: tcl + + # TUMPA example: + # http://www.tiaowiki.com/w/TIAO_USB_Multi_Protocol_Adapter_User's_Manual + source [find interface/ftdi/tumpa.cfg] + + transport select jtag + + # default JTAG configuration has only SRST and no TRST + reset_config srst_only srst_push_pull + + # delay after SRST goes inactive + adapter srst delay 20 + + if { ![info exists SOC] } { + # Set the SoC of interest + set SOC am625 + } + + source [find target/ti_k3.cfg] + + ftdi tdo_sample_edge falling + + # Speeds for FT2232H are in multiples of 2, and 32MHz is tops + # max speed we seem to achieve is ~20MHz.. so we pick 16MHz + adapter speed 16000 diff --git a/doc/board/ti/img/beagleplay_emmc.svg b/doc/board/ti/img/beagleplay_emmc.svg new file mode 100644 index 00000000000..c6ff19b7738 --- /dev/null +++ b/doc/board/ti/img/beagleplay_emmc.svg @@ -0,0 +1,697 @@ + + + + + + + + + + + + + + + + + + + + Boot0 + + + + Boot0 + + + + + + + + + Boot1 + + + + Boot1 + + + + + + + + + RPMB + + + + RPMB + + + + + + + + + User Defined Area (UDA) + + + + User Defined Area (UDA) + + + + + + + + + BOOT + + + + BOOT + + + + + + + + + rootfs + + + + rootfs + + + + + + + + + swap + + + + swap + + + + + + + + + ... + + + + ... + + + + + + + + + tiboot3.bin + + + + tiboot3.bin + + + + + + + + + tispl.bin + + + + tispl.bin + + + + + + + + + u-boot.img + + + + u-boot.img + + + + + + + + + extlinux/extlinux.conf + + + + extlinux/extlinux.conf + + + + + + + + + uEnv.txt / boot.scr +(optional) + + + + uEnv.txt / boot.scr... + + + + + + + + + eMMC +hardware partitions + + + + eMMC... + + + + + + + + + UDA partitions + + + + UDA partit... + + + + + + + Text is not SVG - cannot display + + + diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst index 95cdb366252..8b5c1a88ed0 100644 --- a/doc/board/ti/k3.rst +++ b/doc/board/ti/k3.rst @@ -30,6 +30,7 @@ K3 Based SoCs .. toctree:: :maxdepth: 1 + am62x_beagleplay am62x_sk ../toradex/verdin-am62 am64x_evm diff --git a/include/configs/am62x_evm.h b/include/configs/am62x_evm.h index 44180dc7687..c8fe59b7531 100644 --- a/include/configs/am62x_evm.h +++ b/include/configs/am62x_evm.h @@ -9,12 +9,6 @@ #ifndef __CONFIG_AM625_EVM_H #define __CONFIG_AM625_EVM_H -#include -#include - -/* DDR Configuration */ -#define CFG_SYS_SDRAM_BASE1 0x880000000 - /* Now for the remaining common defines */ #include diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index dbbeff34ba8..4e30d0d2ddf 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -200,7 +200,7 @@ #define CFG_EXTRA_ENV_SETTINGS \ BOOTENV -#endif +#endif /* CONFIG_DISTRO_DEFAULTS */ #endif /* CONFIG_ARM64 */ diff --git a/include/configs/verdin-am62.h b/include/configs/verdin-am62.h index 7990ea83102..9d2e37f2d96 100644 --- a/include/configs/verdin-am62.h +++ b/include/configs/verdin-am62.h @@ -13,8 +13,7 @@ /* DDR Configuration */ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CFG_SYS_SDRAM_BASE1 0x880000000 -#define CFG_SYS_SDRAM_SIZE SZ_2G /* Maximum supported size */ +#define CFG_SYS_SDRAM_SIZE SZ_2G /* Maximum supported size, auto-detection is used */ #define MEM_LAYOUT_ENV_SETTINGS \ "fdt_addr_r=0x90200000\0" \ @@ -46,10 +45,20 @@ "fdt_board=dev\0" \ "setup=setenv setupargs console=tty1 console=${console},${baudrate} " \ "consoleblank=0 earlycon=ns16550a,mmio32,0x02800000\0" \ - "update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \ + "update_tiboot3=askenv confirm Did you load tiboot3.bin (y/N)?; " \ "if test \"$confirm\" = \"y\"; then " \ "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \ + "${blkcnt}; fi\0" \ + "update_tispl=askenv confirm Did you load tispl.bin (y/N)?; " \ + "if test \"$confirm\" = \"y\"; then " \ + "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ + "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x400 " \ + "${blkcnt}; fi\0" \ + "update_uboot=askenv confirm Did you load u-boot.img (y/N)?; " \ + "if test \"$confirm\" = \"y\"; then " \ + "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ + "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x1400 " \ "${blkcnt}; fi\0" #endif /* __VERDIN_AM62_H */ diff --git a/include/env/ti/default_findfdt.env b/include/env/ti/default_findfdt.env new file mode 100644 index 00000000000..a2b51dd923b --- /dev/null +++ b/include/env/ti/default_findfdt.env @@ -0,0 +1,12 @@ +default_device_tree=CONFIG_DEFAULT_DEVICE_TREE +default_device_tree_arch=ti +#ifdef CONFIG_ARM64 +findfdt= + setenv name_fdt ${default_device_tree_arch}/${default_device_tree}.dtb; + setenv fdtfile ${name_fdt} +#else +default_device_tree_subarch=omap +findfdt= + setenv name_fdt ${default_device_tree_arch}/${default_device_tree_subarch}/${default_device_tree}.dtb; + setenv fdtfile ${name_fdt} +#endif diff --git a/include/env/ti/mmc.env b/include/env/ti/mmc.env index 6fb47fb2667..0256a2d2aac 100644 --- a/include/env/ti/mmc.env +++ b/include/env/ti/mmc.env @@ -5,7 +5,9 @@ args_mmc=run finduuid;setenv bootargs console=${console} ${optargs} root=PARTUUID=${uuid} rw rootfstype=${mmcrootfstype} +#ifndef CONFIG_BOOTSTD loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr +#endif bootscript=echo Running bootscript from mmc${mmcdev} ...; source ${loadaddr} bootenvfile=uEnv.txt @@ -15,10 +17,10 @@ loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile} loadimage=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${bootfile} loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/dtb/${fdtfile} get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/dtb/${name_fdt} -envboot=mmc dev ${mmcdev}; +envboot=if mmc dev ${mmcdev}; then if mmc rescan; then echo SD/MMC found on device ${mmcdev}; - if run loadbootscript; then + if test -n "${loadbootscript}" && run loadbootscript; then run bootscript; else if run loadbootenv; then @@ -31,6 +33,7 @@ envboot=mmc dev ${mmcdev}; fi; fi; fi; + fi; mmcloados= if test ${boot_fdt} = yes || test ${boot_fdt} = try; then if run get_fdt_mmc; then @@ -45,7 +48,7 @@ mmcloados= else bootz; fi; -mmcboot=mmc dev ${mmcdev}; +mmcboot=if mmc dev ${mmcdev}; then devnum=${mmcdev}; devtype=mmc; if mmc rescan; then @@ -58,7 +61,8 @@ mmcboot=mmc dev ${mmcdev}; run mmcloados; fi; fi; -fi; + fi; + fi; init_mmc=run args_all args_mmc get_overlay_mmc= diff --git a/include/env/ti/ti_armv7_common.env b/include/env/ti/ti_common.env similarity index 100% rename from include/env/ti/ti_armv7_common.env rename to include/env/ti/ti_common.env