Djam/u-boot
1
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2025-05-09 03:21:51 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

ppc: Remove duplicate newlines

Browse source 
Drop all duplicate newlines. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut 2024-07-13 15:19:29 +02:00 • committed by Tom Rini
parent 6671056402
commit 5f9a3003be
28 changed files with 0 additions and 43 deletions
Download patch file Download diff file Expand all files Collapse all files

5
arch/powerpc/cpu/mpc83xx/interrupts.c
View file

@ -32,7 +32,6 @@ void interrupt_init_cpu (unsigned *decrementer_count)
immr->sysconf.spcr |= 0x00400000;
}
/*
* Handle external interrupts
*/
@ -41,7 +40,6 @@ void external_interrupt(struct pt_regs *regs)
{
}
/*
* Install and free an interrupt handler.
*/
@ -51,19 +49,16 @@ irq_install_handler(int irq, interrupt_handler_t * handler, void *arg)
{
}
void irq_free_handler(int irq)
{
}
void timer_interrupt_cpu (struct pt_regs *regs)
{
/* nothing to do here */
return;
}
#if defined(CONFIG_CMD_IRQ)
/* ripped this out of ppc4xx/interrupts.c */

2
arch/powerpc/cpu/mpc83xx/traps.c
View file

@ -74,7 +74,6 @@ void show_regs(struct pt_regs *regs)
}
}
static void _exception(int signr, struct pt_regs *regs)
{
show_regs(regs);
@ -191,7 +190,6 @@ void SoftEmuException(struct pt_regs *regs)
panic("Software Emulation Exception");
}
void UnknownException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)

3
arch/powerpc/cpu/mpc85xx/cpu.c
View file

@ -297,7 +297,6 @@ int checkcpu (void)
return 0;
}
/* ------------------------------------------------------------------------- */
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
@ -337,7 +336,6 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
return 1;
}
/*
* Get timebase clock frequency
*/
@ -348,7 +346,6 @@ __weak unsigned long get_tbclk(void)
return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
}
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()

1
arch/powerpc/cpu/mpc85xx/cpu_init.c
View file

@ -128,7 +128,6 @@ void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
}
#endif
#if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,

1
arch/powerpc/cpu/mpc85xx/fdt.c
View file

@ -428,7 +428,6 @@ static inline void ft_fixup_cache(void *blob)
ft_fixup_l2cache(blob);
}
void fdt_add_enet_stashing(void *fdt)
{
do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1);

1
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
View file

@ -482,7 +482,6 @@ static void wait_for_rstdone(unsigned int bank)
printf("SERDES: timeout resetting bank %u\n", bank + 1);
}
static void __soc_serdes_init(void)
{
/* Allow for SoC-specific initialization in <SOC>_serdes.c */

1
arch/powerpc/cpu/mpc85xx/mp.c
View file

@ -191,7 +191,6 @@ u32 determine_mp_bootpg(unsigned int *pagesize)
struct law_entry e;
#endif
/* use last 4K of mapped memory */
bootpg = ((gd->ram_size > CFG_MAX_MEM_MAPPED) ?
CFG_MAX_MEM_MAPPED : gd->ram_size) +

1
arch/powerpc/cpu/mpc85xx/p1010_serdes.c
View file

@ -29,7 +29,6 @@ static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
[0x03] = {PCIE1, PCIE2},
};
int is_serdes_configured(enum srds_prtcl device)
{
int ret;

1
arch/powerpc/cpu/mpc85xx/speed.c
View file

@ -625,7 +625,6 @@ int get_clocks(void)
else return (1);
}
/********************************************
* get_bus_freq
* return system bus freq in Hz

1
arch/powerpc/cpu/mpc85xx/t1024_serdes.c
View file

@ -7,7 +7,6 @@
#include <asm/processor.h>
#include <asm/io.h>
static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
[0x40] = {PCIE1, PCIE1, PCIE1, PCIE1},
[0xD5] = {QSGMII_FM1_A, PCIE3, PCIE2, PCIE1},

1
arch/powerpc/cpu/mpc85xx/t1040_serdes.c
View file

@ -9,7 +9,6 @@
#include <asm/io.h>
#include <asm/ppc.h>
static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
[0x00] = {PCIE1, PCIE1, PCIE1, PCIE1,
PCIE2, PCIE2, PCIE2, PCIE2},

1
arch/powerpc/cpu/mpc85xx/tlb.c
View file

@ -354,5 +354,4 @@ void clear_ddr_tlbs(unsigned int memsize_in_meg)
clear_ddr_tlbs_phys(CFG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
}
#endif /* not SPL */

1
arch/powerpc/cpu/mpc85xx/traps.c
View file

@ -111,7 +111,6 @@ void show_regs(struct pt_regs *regs)
}
}
static void _exception(int signr, struct pt_regs *regs)
{
show_regs(regs);

1
arch/powerpc/cpu/mpc8xx/immap.c
View file

@ -206,7 +206,6 @@ static int do_iopset(struct cmd_tbl *cmdtp, int flag, int argc,
if (pin > 31)
rcode = 1;
switch (argv[3][0]) {
case 'd':
if (argv[3][1] == 'a')

2
arch/powerpc/cpu/mpc8xx/traps.c
View file

@ -75,7 +75,6 @@ void show_regs(struct pt_regs *regs)
}
}
static void _exception(int signr, struct pt_regs *regs)
{
show_regs(regs);
@ -142,7 +141,6 @@ void SoftEmuException(struct pt_regs *regs)
panic("Software Emulation Exception");
}
void UnknownException(struct pt_regs *regs)
{
printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",

1
arch/powerpc/cpu/mpc8xxx/cpu.c
View file

@ -300,7 +300,6 @@ __weak int cpu_numcores(void)
return cpu->num_cores;
}
/*
* Check if the given core ID is valid
*

1
arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
View file

@ -20,7 +20,6 @@ static void __lbc_sdram_init(void)
void lbc_sdram_init(void) __attribute__((weak, alias("__lbc_sdram_init")));
#endif
void print_lbc_regs(void)
{
int i;

3
arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
View file

@ -26,7 +26,6 @@ static inline int __ilog2_roundup_64(uint64_t val)
return __ilog2_u64(val) + 1;
}
static inline int count_lsb_zeroes(unsigned long val)
{
return ffs(val) - 1;
@ -332,7 +331,6 @@ void pamu_disable(void)
u32 i = 0;
u32 base_addr = CFG_SYS_PAMU_ADDR;
for (i = 0; i < CFG_NUM_PAMU; i++) {
clrbits_be32((void *)base_addr + PAMU_PCR_OFFSET, PAMU_PCR_PE);
sync();
@ -340,7 +338,6 @@ void pamu_disable(void)
}
}
static uint64_t find_max(uint64_t arr[], int num)
{
int i = 0;

1
arch/powerpc/cpu/mpc8xxx/law.c
View file

@ -31,7 +31,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define LAWBAR_SHIFT 12
#endif
static inline phys_addr_t get_law_base_addr(int idx)
{
#ifdef CONFIG_FSL_CORENET

1
arch/powerpc/include/asm/bitops.h
View file

@ -270,7 +270,6 @@ found_middle:
return result + ffz(tmp);
}
#define _EXT2_HAVE_ASM_BITOPS_
#ifdef __KERNEL__

2
arch/powerpc/include/asm/config_mpc85xx.h
View file

@ -82,7 +82,6 @@
#define CFG_SYS_FM_MURAM_SIZE 0x28000
#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_T4240)
#ifdef CONFIG_ARCH_T4240
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
@ -168,7 +167,6 @@
#define CFG_SYS_FM_MURAM_SIZE 0x28000
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#elif defined(CONFIG_ARCH_C29X)
#define CFG_SYS_FSL_SEC_IDX_OFFSET 0x20000

1
arch/powerpc/include/asm/fsl_pci.h
View file

@ -269,5 +269,4 @@ int fsl_pcie_init_board(int busno);
#error FT_FSL_PCI_SETUP not defined
#endif
#endif

1
arch/powerpc/include/asm/io.h
View file

@ -92,7 +92,6 @@ extern void _outsl_ns(volatile u32 *port, const void *buf, int nl);
#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
#define IO_SPACE_LIMIT ~0
#define memset_io(a,b,c) memset((void __force *)(a),(b),(c))

3
arch/powerpc/include/asm/mmu.h
View file

@ -126,7 +126,6 @@ typedef struct _pte {
#define PT_MASK 0x02FF
#define PG_SHIFT (12) /* Page Entry */
/* MMU context */
typedef struct _MMU_context {
@ -304,7 +303,6 @@ extern void print_bats(void);
#define M_CASID 793 /* Address space ID (context) to match */
#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */
/* These are the Ks and Kp from the PowerPC books. For proper operation,
* Ks = 0, Kp = 1.
*/
@ -349,7 +347,6 @@ extern void print_bats(void);
#define MD_SVALID 0x00000001 /* Segment entry is valid */
/* Reset value is undefined */
/* Real page number. Defined by the pte. Writing this register
* causes a TLB entry to be created for the data TLB, using
* additional information from the MD_EPN, and MD_TWC registers.

3
arch/powerpc/include/asm/mpc8349_pci.h
View file

@ -1,7 +1,6 @@
#ifndef _PPC_KERNEL_MPC8349_PCI_H
#define _PPC_KERNEL_MPC8349_PCI_H
#define M8265_PCIBR0 0x101ac
#define M8265_PCIBR1 0x101b0
#define M8265_PCIMSK0 0x101c4
@ -30,10 +29,8 @@
#define PCIMSK_512MB 0xE0000000
#define PCIMSK_1GB 0xC0000000 /* Size of window, largest */
#define M826X_SCCR_PCI_MODE_EN 0x100
/*
* Outbound ATU registers (3 sets). These registers control how 60x bus
* (local) addresses are translated to PCI addresses when the MPC826x is

1
arch/powerpc/include/asm/sigcontext.h
View file

@ -3,7 +3,6 @@
#include <asm/ptrace.h>
struct sigcontext_struct {
unsigned long _unused[4];
int signal;

1
arch/powerpc/lib/bootm.c
View file

@ -6,7 +6,6 @@
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
#include <config.h>
#include <bootm.h>
#include <bootstage.h>

1
arch/powerpc/lib/interrupts.c
View file

@ -32,7 +32,6 @@ static __inline__ unsigned long get_dec (void)
return val;
}
static __inline__ void set_dec (unsigned long val)
{
if (val)