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chromebook_coral: Move CONFIG_BLOBLIST_ADDR to CAR

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Reading doc/board/google/chromebook_coral.rst we can see that at some
point it was intended to put the bloblist in CAR, rather than DRAM, at
some point during development. This is fine for TPL/SPL stages where we
have very minimal information stored in the bloblist and so we can set
the limit there to 4KiB and then expand it to 196KiB in U-Boot proper so
there's room for ACPI tables and so forth. We also update the
documentation to use the same location for CONFIG_BLOBLIST_ADDR in both
references.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2024-12-17 10:22:15 -06:00
parent 079214e4be
commit 5c72a2afbf
2 changed files with 4 additions and 3 deletions
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5
configs/chromebook_coral_defconfig
View file

@ -2,6 +2,7 @@ CONFIG_X86=y
CONFIG_TEXT_BASE=0x1110000
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x3d00
CONFIG_BLOBLIST_SIZE_RELOC=0x30000
CONFIG_NR_DRAM_BANKS=8
CONFIG_MAX_CPUS=8
CONFIG_SPL_DM_SPI=y
@ -44,8 +45,8 @@ CONFIG_LOGF_FUNC=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BLOBLIST=y
# CONFIG_TPL_BLOBLIST is not set
CONFIG_BLOBLIST_ADDR=0x100000
CONFIG_BLOBLIST_SIZE=0x30000
CONFIG_BLOBLIST_ADDR=0xfef10000
CONFIG_BLOBLIST_SIZE=0x1000
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_HANDOFF=y
CONFIG_SPL_SEPARATE_BSS=y

2
doc/board/google/chromebook_coral.rst
View file

@ -243,7 +243,7 @@ board_init_r(), as per the rules, and DRAM is available then.
SPL sets up a bloblist and passes the SPL hand-off information to U-Boot proper.
This includes a pointer to the HOB list as well as DRAM information. See
struct arch_spl_handoff. The bloblist address is set by CONFIG_BLOBLIST_ADDR,
normally 100000.
normally fef10000.
SPL uses SPI flash to update the MRC caches in ROM. This speeds up subsequent
boots. Be warned that SPL can take 30 seconds without this cache! This is a