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pci: Add support for Qualcomm PCIe controller
Add support for the PCIe busses on Qualcomm platforms, by using the pcie_dw_common infrastructure. The driver is based on the Linux driver but only supporting the "1_9_0" and compatible platforms like: - sa8540p - sc7280 - sc8180x - sc8280xp - sdm845 - sdx55 - sm8150 - sm8250 - sm8350 - sm8450 - sm8550 - sm8650 - x1e80100 But it has only been tested on: - sc7280 - sm8550 - sm8650 - x1e80100 It supports setting the IOMMU SID table for supported platforms. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241125-topic-pcie-controller-v1-2-45c20070dd53@linaro.org Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
This commit is contained in:
Neil Armstrong
Caleb Connolly
parent
aeeebdadc5
commit
5b7ec7fb44
4 changed files with 584 additions and 0 deletions
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@ -371,6 +371,14 @@ config PCIE_DW_MESON
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Say Y here if you want to enable DW PCIe controller support on
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Amlogic SoCs.
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config PCIE_DW_QCOM
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bool "Qualcomm DesignWare based PCIe controller"
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depends on ARCH_SNAPDRAGON
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select PCIE_DW_COMMON
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help
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Say Y here if you want to enable DW PCIe controller support on
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Qualcomm SoCs.
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config PCIE_ROCKCHIP
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bool "Enable Rockchip PCIe driver"
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depends on ARCH_ROCKCHIP
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@ -47,6 +47,7 @@ obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie_mediatek_gen3.o
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obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o
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obj-$(CONFIG_PCIE_DW_ROCKCHIP) += pcie_dw_rockchip.o
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obj-$(CONFIG_PCIE_DW_MESON) += pcie_dw_meson.o
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obj-$(CONFIG_PCIE_DW_QCOM) += pcie_dw_qcom.o
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obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o
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obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
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obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
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571
drivers/pci/pcie_dw_qcom.c
Normal file
571
drivers/pci/pcie_dw_qcom.c
Normal file
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@ -0,0 +1,571 @@
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// SPDX-License-Identifier: GPL-2.0+
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#include <clk.h>
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#include <dm.h>
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#include <generic-phy.h>
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#include <pci.h>
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#include <u-boot/crc.h>
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#include <power-domain.h>
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#include <reset.h>
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#include <syscon.h>
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#include <malloc.h>
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#include <power/regulator.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm-generic/gpio.h>
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#include <dm/device_compat.h>
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#include <linux/iopoll.h>
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#include <linux/delay.h>
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#include <linux/log2.h>
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#include <linux/bitfield.h>
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#include "pcie_dw_common.h"
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DECLARE_GLOBAL_DATA_PTR;
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struct qcom_pcie;
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struct qcom_pcie_ops {
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int (*config_sid)(struct qcom_pcie *priv);
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};
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#define NUM_SUPPLIES 2
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struct qcom_pcie {
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/* Must be first member of the struct */
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struct pcie_dw dw;
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void *parf;
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struct phy phy;
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struct reset_ctl_bulk rsts;
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struct clk_bulk clks;
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struct gpio_desc rst_gpio;
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struct qcom_pcie_ops *ops;
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struct udevice *vregs[NUM_SUPPLIES];
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};
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/* PARF registers */
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#define PARF_SYS_CTRL 0x00
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#define PARF_PM_CTRL 0x20
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#define PARF_PCS_DEEMPH 0x34
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#define PARF_PCS_SWING 0x38
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#define PARF_PHY_CTRL 0x40
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#define PARF_PHY_REFCLK 0x4c
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#define PARF_CONFIG_BITS 0x50
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#define PARF_DBI_BASE_ADDR 0x168
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#define PARF_MHI_CLOCK_RESET_CTRL 0x174
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#define PARF_AXI_MSTR_WR_ADDR_HALT 0x178
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#define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8
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#define PARF_Q2A_FLUSH 0x1ac
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#define PARF_LTSSM 0x1b0
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#define PARF_SID_OFFSET 0x234
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#define PARF_BDF_TRANSLATE_CFG 0x24c
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#define PARF_SLV_ADDR_SPACE_SIZE 0x358
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#define PARF_DEVICE_TYPE 0x1000
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#define PARF_BDF_TO_SID_TABLE_N 0x2000
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/* ELBI registers */
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#define ELBI_SYS_CTRL 0x04
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/* DBI registers */
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#define AXI_MSTR_RESP_COMP_CTRL0 0x818
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#define AXI_MSTR_RESP_COMP_CTRL1 0x81c
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#define MISC_CONTROL_1_REG 0x8bc
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/* MHI registers */
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#define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04
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#define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c
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#define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10
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#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84
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#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88
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/* PARF_SYS_CTRL register fields */
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#define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29)
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#define MST_WAKEUP_EN BIT(13)
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#define SLV_WAKEUP_EN BIT(12)
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#define MSTR_ACLK_CGC_DIS BIT(10)
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#define SLV_ACLK_CGC_DIS BIT(9)
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#define CORE_CLK_CGC_DIS BIT(6)
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#define AUX_PWR_DET BIT(4)
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#define L23_CLK_RMV_DIS BIT(2)
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#define L1_CLK_RMV_DIS BIT(1)
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/* PARF_PM_CTRL register fields */
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#define REQ_NOT_ENTR_L1 BIT(5)
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/* PARF_PCS_DEEMPH register fields */
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#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) FIELD_PREP(GENMASK(21, 16), x)
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#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) FIELD_PREP(GENMASK(13, 8), x)
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#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) FIELD_PREP(GENMASK(5, 0), x)
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/* PARF_PCS_SWING register fields */
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#define PCS_SWING_TX_SWING_FULL(x) FIELD_PREP(GENMASK(14, 8), x)
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#define PCS_SWING_TX_SWING_LOW(x) FIELD_PREP(GENMASK(6, 0), x)
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/* PARF_PHY_CTRL register fields */
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#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
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#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) FIELD_PREP(PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK, x)
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#define PHY_TEST_PWR_DOWN BIT(0)
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/* PARF_PHY_REFCLK register fields */
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#define PHY_REFCLK_SSP_EN BIT(16)
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#define PHY_REFCLK_USE_PAD BIT(12)
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/* PARF_CONFIG_BITS register fields */
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#define PHY_RX0_EQ(x) FIELD_PREP(GENMASK(26, 24), x)
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/* PARF_SLV_ADDR_SPACE_SIZE register value */
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#define SLV_ADDR_SPACE_SZ 0x10000000
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/* PARF_MHI_CLOCK_RESET_CTRL register fields */
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#define AHB_CLK_EN BIT(0)
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#define MSTR_AXI_CLK_EN BIT(1)
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#define BYPASS BIT(4)
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/* PARF_AXI_MSTR_WR_ADDR_HALT register fields */
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#define EN BIT(31)
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/* PARF_LTSSM register fields */
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#define LTSSM_EN BIT(8)
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/* PARF_DEVICE_TYPE register fields */
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#define DEVICE_TYPE_RC 0x4
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/* ELBI_SYS_CTRL register fields */
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#define ELBI_SYS_CTRL_LT_ENABLE BIT(0)
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/* AXI_MSTR_RESP_COMP_CTRL0 register fields */
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#define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4
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#define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5
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/* AXI_MSTR_RESP_COMP_CTRL1 register fields */
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#define CFG_BRIDGE_SB_INIT BIT(0)
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/* MISC_CONTROL_1_REG register fields */
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#define DBI_RO_WR_EN 1
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/* PCI_EXP_SLTCAP register fields */
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#define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, 250)
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#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, 1)
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#define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP | \
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PCI_EXP_SLTCAP_PCP | \
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PCI_EXP_SLTCAP_MRLSP | \
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PCI_EXP_SLTCAP_AIP | \
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PCI_EXP_SLTCAP_PIP | \
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PCI_EXP_SLTCAP_HPS | \
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PCI_EXP_SLTCAP_HPC | \
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PCI_EXP_SLTCAP_EIP | \
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PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
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PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
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#define PERST_DELAY_US 1000
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#define LINK_WAIT_MAX_RETRIES 10
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#define LINK_WAIT_USLEEP 100000
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#define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0))
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#define CRC8_TABLE_SIZE 256
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static bool qcom_pcie_wait_link_up(struct qcom_pcie *priv)
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{
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u8 offset = pcie_dw_find_capability(&priv->dw, PCI_CAP_ID_EXP);
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unsigned int cnt = 0;
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u16 val;
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do {
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val = readw(priv->dw.dbi_base + offset + PCI_EXP_LNKSTA);
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if ((val & PCI_EXP_LNKSTA_DLLLA))
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return true;
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cnt++;
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udelay(LINK_WAIT_USLEEP);
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} while (cnt < LINK_WAIT_MAX_RETRIES);
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return false;
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}
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static void qcom_pcie_clear_aspm_l0s(struct qcom_pcie *priv)
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{
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u8 offset = pcie_dw_find_capability(&priv->dw, PCI_CAP_ID_EXP);
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u32 val;
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dw_pcie_dbi_write_enable(&priv->dw, true);
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val = readl(priv->dw.dbi_base + offset + PCI_EXP_LNKCAP);
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val &= ~PCI_EXP_LNKCAP_ASPM_L0S;
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writel(val, priv->dw.dbi_base + offset + PCI_EXP_LNKCAP);
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dw_pcie_dbi_write_enable(&priv->dw, false);
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}
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static void qcom_pcie_clear_hpc(struct qcom_pcie *priv)
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{
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u8 offset = pcie_dw_find_capability(&priv->dw, PCI_CAP_ID_EXP);
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u32 val;
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dw_pcie_dbi_write_enable(&priv->dw, true);
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val = readl(priv->dw.dbi_base + offset + PCI_EXP_SLTCAP);
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val &= ~PCI_EXP_SLTCAP_HPC;
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writel(val, priv->dw.dbi_base + offset + PCI_EXP_SLTCAP);
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dw_pcie_dbi_write_enable(&priv->dw, false);
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}
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static void qcom_pcie_set_lanes(struct qcom_pcie *priv, unsigned int lanes)
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{
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u8 offset = pcie_dw_find_capability(&priv->dw, PCI_CAP_ID_EXP);
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u32 val;
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val = readl(priv->dw.dbi_base + offset + PCI_EXP_LNKCAP);
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val &= ~PCI_EXP_LNKCAP_MLW;
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val |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, lanes);
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writel(val, priv->dw.dbi_base + offset + PCI_EXP_LNKCAP);
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}
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static int qcom_pcie_config_sid_1_9_0(struct qcom_pcie *priv)
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{
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/* iommu map structure */
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struct {
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u32 bdf;
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u32 phandle;
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u32 smmu_sid;
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u32 smmu_sid_len;
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} *map;
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void *bdf_to_sid_base = priv->parf + PARF_BDF_TO_SID_TABLE_N;
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int i, nr_map, size = 0;
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u32 smmu_sid_base;
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dev_read_prop(priv->dw.dev, "iommu-map", &size);
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if (!size)
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return 0;
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map = malloc(size);
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if (!map)
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return -ENOMEM;
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dev_read_u32_array(priv->dw.dev, "iommu-map", (u32 *)map, size / sizeof(u32));
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nr_map = size / (sizeof(*map));
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/* Registers need to be zero out first */
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memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32));
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/* Extract the SMMU SID base from the first entry of iommu-map */
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smmu_sid_base = map[0].smmu_sid;
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/* Look for an available entry to hold the mapping */
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for (i = 0; i < nr_map; i++) {
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__be16 bdf_be = cpu_to_be16(map[i].bdf);
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u32 val;
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u8 hash;
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hash = crc8(QCOM_PCIE_CRC8_POLYNOMIAL, (u8 *)&bdf_be, sizeof(bdf_be));
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val = readl(bdf_to_sid_base + hash * sizeof(u32));
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/* If the register is already populated, look for next available entry */
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while (val) {
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u8 current_hash = hash++;
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u8 next_mask = 0xff;
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/* If NEXT field is NULL then update it with next hash */
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if (!(val & next_mask)) {
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val |= (u32)hash;
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writel(val, bdf_to_sid_base + current_hash * sizeof(u32));
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}
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val = readl(bdf_to_sid_base + hash * sizeof(u32));
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}
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/* BDF [31:16] | SID [15:8] | NEXT [7:0] */
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val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0;
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writel(val, bdf_to_sid_base + hash * sizeof(u32));
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}
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free(map);
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return 0;
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}
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static void qcom_pcie_configure(struct qcom_pcie *priv)
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{
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u32 val;
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dw_pcie_dbi_write_enable(&priv->dw, true);
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val = readl(priv->dw.dbi_base + PCIE_PORT_LINK_CONTROL);
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val &= ~PORT_LINK_FAST_LINK_MODE;
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val |= PORT_LINK_DLL_LINK_EN;
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val &= ~PORT_LINK_MODE_MASK;
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val |= PORT_LINK_MODE_2_LANES;
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writel(val, priv->dw.dbi_base + PCIE_PORT_LINK_CONTROL);
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val = readl(priv->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
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val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
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val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
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writel(val, priv->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
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qcom_pcie_set_lanes(priv, 2);
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dw_pcie_dbi_write_enable(&priv->dw, false);
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}
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static int qcom_pcie_init_port(struct udevice *dev)
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{
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struct qcom_pcie *priv = dev_get_priv(dev);
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int vreg, ret;
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u32 val;
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dm_gpio_set_value(&priv->rst_gpio, 1);
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udelay(PERST_DELAY_US);
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ret = generic_phy_init(&priv->phy);
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if (ret) {
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dev_err(dev, "failed to init phy (%d)\n", ret);
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return ret;
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}
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udelay(PERST_DELAY_US);
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for (vreg = 0; vreg < NUM_SUPPLIES; ++vreg) {
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ret = regulator_set_enable(priv->vregs[vreg], true);
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if (ret && ret != -ENOSYS)
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dev_warn(dev, "failed to enable regulator %d (%d)\n", vreg, ret);
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}
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ret = clk_enable_bulk(&priv->clks);
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if (ret) {
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dev_err(dev, "failed to enable clocks (%d)\n", ret);
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goto err_power_off_phy;
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}
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ret = reset_assert_bulk(&priv->rsts);
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if (ret) {
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dev_err(dev, "failed to assert resets (%d)\n", ret);
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goto err_disable_clks;
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}
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udelay(PERST_DELAY_US);
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ret = reset_deassert_bulk(&priv->rsts);
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if (ret) {
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dev_err(dev, "failed to deassert resets (%d)\n", ret);
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goto err_power_off_phy;
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}
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udelay(PERST_DELAY_US);
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/* configure PCIe to RC mode */
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writel(DEVICE_TYPE_RC, priv->parf + PARF_DEVICE_TYPE);
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/* enable PCIe clocks and resets */
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val = readl(priv->parf + PARF_PHY_CTRL);
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val &= ~PHY_TEST_PWR_DOWN;
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writel(val, priv->parf + PARF_PHY_CTRL);
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/* change DBI base address */
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writel(0, priv->parf + PARF_DBI_BASE_ADDR);
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/* MAC PHY_POWERDOWN MUX DISABLE */
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val = readl(priv->parf + PARF_SYS_CTRL);
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val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN;
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writel(val, priv->parf + PARF_SYS_CTRL);
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val = readl(priv->parf + PARF_MHI_CLOCK_RESET_CTRL);
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val |= BYPASS;
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writel(val, priv->parf + PARF_MHI_CLOCK_RESET_CTRL);
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|
||||
/* Enable L1 and L1SS */
|
||||
val = readl(priv->parf + PARF_PM_CTRL);
|
||||
val &= ~REQ_NOT_ENTR_L1;
|
||||
writel(val, priv->parf + PARF_PM_CTRL);
|
||||
|
||||
val = readl(priv->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
|
||||
val |= EN;
|
||||
writel(val, priv->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
|
||||
|
||||
ret = generic_phy_power_on(&priv->phy);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to power on phy (%d)\n", ret);
|
||||
goto err_exit_phy;
|
||||
}
|
||||
|
||||
qcom_pcie_clear_aspm_l0s(priv);
|
||||
qcom_pcie_clear_hpc(priv);
|
||||
|
||||
mdelay(100);
|
||||
dm_gpio_set_value(&priv->rst_gpio, 0);
|
||||
udelay(PERST_DELAY_US);
|
||||
|
||||
if (priv->ops && priv->ops->config_sid) {
|
||||
ret = priv->ops->config_sid(priv);
|
||||
if (ret)
|
||||
goto err_deassert_bulk;
|
||||
}
|
||||
|
||||
qcom_pcie_configure(priv);
|
||||
|
||||
pcie_dw_setup_host(&priv->dw);
|
||||
|
||||
/* enable link training */
|
||||
val = readl(priv->parf + PARF_LTSSM);
|
||||
val |= LTSSM_EN;
|
||||
writel(val, priv->parf + PARF_LTSSM);
|
||||
|
||||
return 0;
|
||||
err_deassert_bulk:
|
||||
reset_assert_bulk(&priv->rsts);
|
||||
err_disable_clks:
|
||||
clk_disable_bulk(&priv->clks);
|
||||
err_power_off_phy:
|
||||
generic_phy_power_off(&priv->phy);
|
||||
err_exit_phy:
|
||||
generic_phy_exit(&priv->phy);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const char *qcom_pcie_vregs[NUM_SUPPLIES] = {
|
||||
"vdda-supply",
|
||||
"vddpe-3v3-supply",
|
||||
};
|
||||
|
||||
static int qcom_pcie_parse_dt(struct udevice *dev)
|
||||
{
|
||||
struct qcom_pcie *priv = dev_get_priv(dev);
|
||||
int vreg, ret;
|
||||
|
||||
priv->dw.dbi_base = dev_read_addr_name_ptr(dev, "dbi");
|
||||
if (!priv->dw.dbi_base)
|
||||
return -EINVAL;
|
||||
|
||||
dev_dbg(dev, "DBI address is 0x%p\n", priv->dw.dbi_base);
|
||||
|
||||
priv->dw.atu_base = dev_read_addr_name_ptr(dev, "atu");
|
||||
if (!priv->dw.atu_base)
|
||||
return -EINVAL;
|
||||
|
||||
dev_dbg(dev, "ATU address is 0x%p\n", priv->dw.atu_base);
|
||||
|
||||
priv->parf = dev_read_addr_name_ptr(dev, "parf");
|
||||
if (!priv->parf)
|
||||
return -EINVAL;
|
||||
|
||||
dev_dbg(dev, "PARF address is 0x%p\n", priv->parf);
|
||||
|
||||
ret = gpio_request_by_name(dev, "perst-gpios", 0,
|
||||
&priv->rst_gpio, GPIOD_IS_OUT);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to find reset-gpios property\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = reset_get_bulk(dev, &priv->rsts);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to get resets (%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_get_bulk(dev, &priv->clks);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to get clocks (%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = generic_phy_get_by_index(dev, 0, &priv->phy);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to get pcie phy (%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
for (vreg = 0; vreg < NUM_SUPPLIES; ++vreg) {
|
||||
ret = device_get_supply_regulator(dev, qcom_pcie_vregs[vreg], &priv->vregs[vreg]);
|
||||
if (ret)
|
||||
dev_warn(dev, "failed to get regulator %d (%d)\n", vreg, ret);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* qcom_pcie_probe() - Probe the PCIe bus for active link
|
||||
*
|
||||
* @dev: A pointer to the device being operated on
|
||||
*
|
||||
* Probe for an active link on the PCIe bus and configure the controller
|
||||
* to enable this port.
|
||||
*
|
||||
* Return: 0 on success, else -ENODEV
|
||||
*/
|
||||
static int qcom_pcie_probe(struct udevice *dev)
|
||||
{
|
||||
struct qcom_pcie *priv = dev_get_priv(dev);
|
||||
struct udevice *ctlr = pci_get_controller(dev);
|
||||
struct pci_controller *hose = dev_get_uclass_priv(ctlr);
|
||||
int ret = 0;
|
||||
|
||||
priv->dw.first_busno = dev_seq(dev);
|
||||
priv->dw.dev = dev;
|
||||
|
||||
ret = qcom_pcie_parse_dt(dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = qcom_pcie_init_port(dev);
|
||||
if (ret) {
|
||||
dm_gpio_free(dev, &priv->rst_gpio);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (qcom_pcie_wait_link_up(priv))
|
||||
printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n",
|
||||
dev_seq(dev), pcie_dw_get_link_speed(&priv->dw),
|
||||
pcie_dw_get_link_width(&priv->dw),
|
||||
hose->first_busno);
|
||||
else
|
||||
printf("PCIE-%d: Link up timeout\n", dev_seq(dev));
|
||||
|
||||
return pcie_dw_prog_outbound_atu_unroll(&priv->dw,
|
||||
PCIE_ATU_REGION_INDEX0,
|
||||
PCIE_ATU_TYPE_MEM,
|
||||
priv->dw.mem.phys_start,
|
||||
priv->dw.mem.bus_start,
|
||||
priv->dw.mem.size);
|
||||
}
|
||||
|
||||
static const struct dm_pci_ops qcom_pcie_ops = {
|
||||
.read_config = pcie_dw_read_config,
|
||||
.write_config = pcie_dw_write_config,
|
||||
};
|
||||
|
||||
static const struct qcom_pcie_ops ops_1_9_0 = {
|
||||
.config_sid = qcom_pcie_config_sid_1_9_0,
|
||||
};
|
||||
|
||||
static const struct udevice_id qcom_pcie_ids[] = {
|
||||
{ .compatible = "qcom,pcie-sa8540p", .data = (ulong)&ops_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-sc7280", .data = (ulong)&ops_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-sc8180x", .data = (ulong)&ops_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-sc8280xp", .data = (ulong)&ops_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-sdm845" },
|
||||
{ .compatible = "qcom,pcie-sdx55", .data = (ulong)&ops_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-sm8150", .data = (ulong)&ops_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-sm8250", .data = (ulong)&ops_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-sm8350", .data = (ulong)&ops_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-sm8450-pcie0", .data = (ulong)&ops_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-sm8450-pcie1", .data = (ulong)&ops_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-sm8550", .data = (ulong)&ops_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-x1e80100", .data = (ulong)&ops_1_9_0 },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(qcom_dw_pcie) = {
|
||||
.name = "pcie_dw_qcom",
|
||||
.id = UCLASS_PCI,
|
||||
.of_match = qcom_pcie_ids,
|
||||
.ops = &qcom_pcie_ops,
|
||||
.probe = qcom_pcie_probe,
|
||||
.priv_auto = sizeof(struct qcom_pcie),
|
||||
};
|
||||
|
|
@ -390,6 +390,9 @@
|
|||
#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
|
||||
#define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */
|
||||
#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
|
||||
#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */
|
||||
#define PCI_EXP_LNKCAP_ASPM_L0S 0x00000400 /* ASPM L0s Support */
|
||||
#define PCI_EXP_LNKCAP_ASPM_L1 0x00000800 /* ASPM L1 Support */
|
||||
#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
|
||||
#define PCI_EXP_LNKCTL 16 /* Link Control */
|
||||
#define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */
|
||||
|
|
@ -404,6 +407,7 @@
|
|||
#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
|
||||
#define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */
|
||||
#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
|
||||
#define PCI_EXP_SLTCAP_HPC 0x00000040 /* Hot-Plug Capable */
|
||||
#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
|
||||
#define PCI_EXP_RTCTL 28 /* Root Control */
|
||||
#define PCI_EXP_RTCTL_CRSSVE 0x0010 /* CRS Software Visibility Enable */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue