mirror of
https://github.com/u-boot/u-boot.git
synced 2025-04-29 09:45:52 +00:00
freescale/layerscape: Rename the config CONFIG_SECURE_BOOT name
Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC to avoid conflict with UEFI secure boot. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
parent
56e6f810b0
commit
5536c3c9d0
46 changed files with 57 additions and 57 deletions
|
@ -50,8 +50,8 @@ config MAX_CPUS
|
||||||
cores, count the reserved ports. This will allocate enough memory
|
cores, count the reserved ports. This will allocate enough memory
|
||||||
in spin table to properly handle all cores.
|
in spin table to properly handle all cores.
|
||||||
|
|
||||||
config SECURE_BOOT
|
config NXP_ESBC
|
||||||
bool "Secure Boot"
|
bool "NXP_ESBC"
|
||||||
help
|
help
|
||||||
Enable Freescale Secure Boot feature. Normally selected
|
Enable Freescale Secure Boot feature. Normally selected
|
||||||
by defconfig. If unsure, do not change.
|
by defconfig. If unsure, do not change.
|
||||||
|
|
|
@ -376,8 +376,8 @@ config EMC2305
|
||||||
Enable the EMC2305 fan controller for configuration of fan
|
Enable the EMC2305 fan controller for configuration of fan
|
||||||
speed.
|
speed.
|
||||||
|
|
||||||
config SECURE_BOOT
|
config NXP_ESBC
|
||||||
bool "Secure Boot"
|
bool "NXP_ESBC"
|
||||||
help
|
help
|
||||||
Enable Freescale Secure Boot feature
|
Enable Freescale Secure Boot feature
|
||||||
|
|
||||||
|
|
|
@ -34,7 +34,7 @@ u32 spl_boot_device(void)
|
||||||
|
|
||||||
void spl_board_init(void)
|
void spl_board_init(void)
|
||||||
{
|
{
|
||||||
#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_LSCH2)
|
#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_LSCH2)
|
||||||
/*
|
/*
|
||||||
* In case of Secure Boot, the IBR configures the SMMU
|
* In case of Secure Boot, the IBR configures the SMMU
|
||||||
* to allow only Secure transactions.
|
* to allow only Secure transactions.
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
config CHAIN_OF_TRUST
|
config CHAIN_OF_TRUST
|
||||||
depends on !FIT_SIGNATURE && SECURE_BOOT
|
depends on !FIT_SIGNATURE && NXP_ESBC
|
||||||
imply CMD_BLOB
|
imply CMD_BLOB
|
||||||
imply CMD_HASH if ARM
|
imply CMD_HASH if ARM
|
||||||
select FSL_CAAM
|
select FSL_CAAM
|
||||||
|
|
|
@ -75,7 +75,7 @@ obj-$(CONFIG_TARGET_P5040DS) += p_corenet/
|
||||||
|
|
||||||
obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ns_access.o
|
obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ns_access.o
|
||||||
|
|
||||||
ifdef CONFIG_SECURE_BOOT
|
ifdef CONFIG_NXP_ESBC
|
||||||
obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o
|
obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o
|
||||||
endif
|
endif
|
||||||
obj-$(CONFIG_CHAIN_OF_TRUST) += fsl_chain_of_trust.o
|
obj-$(CONFIG_CHAIN_OF_TRUST) += fsl_chain_of_trust.o
|
||||||
|
|
|
@ -196,7 +196,7 @@ int board_init(void)
|
||||||
init_final_memctl_regs();
|
init_final_memctl_regs();
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_SECURE_BOOT
|
#ifdef CONFIG_NXP_ESBC
|
||||||
/* In case of Secure Boot, the IBR configures the SMMU
|
/* In case of Secure Boot, the IBR configures the SMMU
|
||||||
* to allow only Secure transactions.
|
* to allow only Secure transactions.
|
||||||
* SMMU must be reset in bypass mode.
|
* SMMU must be reset in bypass mode.
|
||||||
|
|
|
@ -126,7 +126,7 @@ int checkboard(void)
|
||||||
|
|
||||||
int board_init(void)
|
int board_init(void)
|
||||||
{
|
{
|
||||||
#ifdef CONFIG_SECURE_BOOT
|
#ifdef CONFIG_NXP_ESBC
|
||||||
/*
|
/*
|
||||||
* In case of Secure Boot, the IBR configures the SMMU
|
* In case of Secure Boot, the IBR configures the SMMU
|
||||||
* to allow only Secure transactions.
|
* to allow only Secure transactions.
|
||||||
|
|
|
@ -407,7 +407,7 @@ int board_init(void)
|
||||||
ppa_init();
|
ppa_init();
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_SECURE_BOOT
|
#ifdef CONFIG_NXP_ESBC
|
||||||
/*
|
/*
|
||||||
* In case of Secure Boot, the IBR configures the SMMU
|
* In case of Secure Boot, the IBR configures the SMMU
|
||||||
* to allow only Secure transactions.
|
* to allow only Secure transactions.
|
||||||
|
|
|
@ -69,7 +69,7 @@ int board_init(void)
|
||||||
{
|
{
|
||||||
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
|
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
|
||||||
|
|
||||||
#ifdef CONFIG_SECURE_BOOT
|
#ifdef CONFIG_NXP_ESBC
|
||||||
/*
|
/*
|
||||||
* In case of Secure Boot, the IBR configures the SMMU
|
* In case of Secure Boot, the IBR configures the SMMU
|
||||||
* to allow only Secure transactions.
|
* to allow only Secure transactions.
|
||||||
|
|
|
@ -1,7 +1,7 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_TARGET_LS1012AFRWY=y
|
CONFIG_TARGET_LS1012AFRWY=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x40100000
|
CONFIG_SYS_TEXT_BASE=0x40100000
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_FSL_LS_PPA=y
|
CONFIG_FSL_LS_PPA=y
|
||||||
CONFIG_NR_DRAM_BANKS=2
|
CONFIG_NR_DRAM_BANKS=2
|
||||||
CONFIG_AHCI=y
|
CONFIG_AHCI=y
|
||||||
|
|
|
@ -2,7 +2,7 @@ CONFIG_ARM=y
|
||||||
CONFIG_TARGET_LS1012AFRWY=y
|
CONFIG_TARGET_LS1012AFRWY=y
|
||||||
CONFIG_TFABOOT=y
|
CONFIG_TFABOOT=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x82000000
|
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_NR_DRAM_BANKS=2
|
CONFIG_NR_DRAM_BANKS=2
|
||||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||||
|
|
|
@ -2,7 +2,7 @@ CONFIG_ARM=y
|
||||||
CONFIG_TARGET_LS1012AQDS=y
|
CONFIG_TARGET_LS1012AQDS=y
|
||||||
CONFIG_TFABOOT=y
|
CONFIG_TFABOOT=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x82000000
|
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_QSPI_AHB_INIT=y
|
CONFIG_QSPI_AHB_INIT=y
|
||||||
CONFIG_NR_DRAM_BANKS=2
|
CONFIG_NR_DRAM_BANKS=2
|
||||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||||
|
|
|
@ -1,7 +1,7 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_TARGET_LS1012ARDB=y
|
CONFIG_TARGET_LS1012ARDB=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x40100000
|
CONFIG_SYS_TEXT_BASE=0x40100000
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_FSL_LS_PPA=y
|
CONFIG_FSL_LS_PPA=y
|
||||||
CONFIG_QSPI_AHB_INIT=y
|
CONFIG_QSPI_AHB_INIT=y
|
||||||
CONFIG_NR_DRAM_BANKS=2
|
CONFIG_NR_DRAM_BANKS=2
|
||||||
|
|
|
@ -2,7 +2,7 @@ CONFIG_ARM=y
|
||||||
CONFIG_TARGET_LS1012ARDB=y
|
CONFIG_TARGET_LS1012ARDB=y
|
||||||
CONFIG_TFABOOT=y
|
CONFIG_TFABOOT=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x82000000
|
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_QSPI_AHB_INIT=y
|
CONFIG_QSPI_AHB_INIT=y
|
||||||
CONFIG_NR_DRAM_BANKS=2
|
CONFIG_NR_DRAM_BANKS=2
|
||||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||||
|
|
|
@ -1,7 +1,7 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_TARGET_LS1021AQDS=y
|
CONFIG_TARGET_LS1021AQDS=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x60100000
|
CONFIG_SYS_TEXT_BASE=0x60100000
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_NR_DRAM_BANKS=1
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
CONFIG_AHCI=y
|
CONFIG_AHCI=y
|
||||||
# CONFIG_SYS_MALLOC_F is not set
|
# CONFIG_SYS_MALLOC_F is not set
|
||||||
|
|
|
@ -1,7 +1,7 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_TARGET_LS1021ATWR=y
|
CONFIG_TARGET_LS1021ATWR=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x60100000
|
CONFIG_SYS_TEXT_BASE=0x60100000
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_NR_DRAM_BANKS=1
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
CONFIG_AHCI=y
|
CONFIG_AHCI=y
|
||||||
CONFIG_DISTRO_DEFAULTS=y
|
CONFIG_DISTRO_DEFAULTS=y
|
||||||
|
|
|
@ -3,7 +3,7 @@ CONFIG_TARGET_LS1021ATWR=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x82000000
|
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_SPL_MMC_SUPPORT=y
|
CONFIG_SPL_MMC_SUPPORT=y
|
||||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||||
|
|
|
@ -2,7 +2,7 @@ CONFIG_ARM=y
|
||||||
CONFIG_TARGET_LS1028AQDS=y
|
CONFIG_TARGET_LS1028AQDS=y
|
||||||
CONFIG_TFABOOT=y
|
CONFIG_TFABOOT=y
|
||||||
CONFIG_SYS_MALLOC_F_LEN=0x6000
|
CONFIG_SYS_MALLOC_F_LEN=0x6000
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_SYS_FSL_SDHC_CLK_DIV=1
|
CONFIG_SYS_FSL_SDHC_CLK_DIV=1
|
||||||
CONFIG_NR_DRAM_BANKS=2
|
CONFIG_NR_DRAM_BANKS=2
|
||||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||||
|
|
|
@ -2,7 +2,7 @@ CONFIG_ARM=y
|
||||||
CONFIG_TARGET_LS1028ARDB=y
|
CONFIG_TARGET_LS1028ARDB=y
|
||||||
CONFIG_TFABOOT=y
|
CONFIG_TFABOOT=y
|
||||||
CONFIG_SYS_MALLOC_F_LEN=0x6000
|
CONFIG_SYS_MALLOC_F_LEN=0x6000
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_SYS_FSL_SDHC_CLK_DIV=1
|
CONFIG_SYS_FSL_SDHC_CLK_DIV=1
|
||||||
CONFIG_NR_DRAM_BANKS=2
|
CONFIG_NR_DRAM_BANKS=2
|
||||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||||
|
|
|
@ -2,7 +2,7 @@ CONFIG_ARM=y
|
||||||
CONFIG_TARGET_LS1043AQDS=y
|
CONFIG_TARGET_LS1043AQDS=y
|
||||||
CONFIG_TFABOOT=y
|
CONFIG_TFABOOT=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x82000000
|
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_NR_DRAM_BANKS=2
|
CONFIG_NR_DRAM_BANKS=2
|
||||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||||
|
|
|
@ -1,7 +1,7 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_TARGET_LS1043ARDB=y
|
CONFIG_TARGET_LS1043ARDB=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x60100000
|
CONFIG_SYS_TEXT_BASE=0x60100000
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_FSL_LS_PPA=y
|
CONFIG_FSL_LS_PPA=y
|
||||||
CONFIG_NR_DRAM_BANKS=2
|
CONFIG_NR_DRAM_BANKS=2
|
||||||
CONFIG_DISTRO_DEFAULTS=y
|
CONFIG_DISTRO_DEFAULTS=y
|
||||||
|
|
|
@ -3,7 +3,7 @@ CONFIG_TARGET_LS1043ARDB=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x82000000
|
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_FSL_LS_PPA=y
|
CONFIG_FSL_LS_PPA=y
|
||||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||||
|
|
|
@ -3,7 +3,7 @@ CONFIG_TARGET_LS1043ARDB=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x82000000
|
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_FSL_LS_PPA=y
|
CONFIG_FSL_LS_PPA=y
|
||||||
CONFIG_SPL_MMC_SUPPORT=y
|
CONFIG_SPL_MMC_SUPPORT=y
|
||||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||||
|
|
|
@ -2,7 +2,7 @@ CONFIG_ARM=y
|
||||||
CONFIG_TARGET_LS1043ARDB=y
|
CONFIG_TARGET_LS1043ARDB=y
|
||||||
CONFIG_TFABOOT=y
|
CONFIG_TFABOOT=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x82000000
|
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_NR_DRAM_BANKS=2
|
CONFIG_NR_DRAM_BANKS=2
|
||||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||||
|
|
|
@ -1,7 +1,7 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_TARGET_LS1046AQDS=y
|
CONFIG_TARGET_LS1046AQDS=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x60100000
|
CONFIG_SYS_TEXT_BASE=0x60100000
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_FSL_LS_PPA=y
|
CONFIG_FSL_LS_PPA=y
|
||||||
CONFIG_NR_DRAM_BANKS=2
|
CONFIG_NR_DRAM_BANKS=2
|
||||||
CONFIG_AHCI=y
|
CONFIG_AHCI=y
|
||||||
|
|
|
@ -2,7 +2,7 @@ CONFIG_ARM=y
|
||||||
CONFIG_TARGET_LS1046AQDS=y
|
CONFIG_TARGET_LS1046AQDS=y
|
||||||
CONFIG_TFABOOT=y
|
CONFIG_TFABOOT=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x82000000
|
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_NR_DRAM_BANKS=2
|
CONFIG_NR_DRAM_BANKS=2
|
||||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||||
|
|
|
@ -1,7 +1,7 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_TARGET_LS1046ARDB=y
|
CONFIG_TARGET_LS1046ARDB=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x40100000
|
CONFIG_SYS_TEXT_BASE=0x40100000
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_FSL_LS_PPA=y
|
CONFIG_FSL_LS_PPA=y
|
||||||
CONFIG_QSPI_AHB_INIT=y
|
CONFIG_QSPI_AHB_INIT=y
|
||||||
CONFIG_NR_DRAM_BANKS=2
|
CONFIG_NR_DRAM_BANKS=2
|
||||||
|
|
|
@ -3,7 +3,7 @@ CONFIG_TARGET_LS1046ARDB=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x82000000
|
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_FSL_LS_PPA=y
|
CONFIG_FSL_LS_PPA=y
|
||||||
CONFIG_SPL_MMC_SUPPORT=y
|
CONFIG_SPL_MMC_SUPPORT=y
|
||||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||||
|
|
|
@ -2,7 +2,7 @@ CONFIG_ARM=y
|
||||||
CONFIG_TARGET_LS1046ARDB=y
|
CONFIG_TARGET_LS1046ARDB=y
|
||||||
CONFIG_TFABOOT=y
|
CONFIG_TFABOOT=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x82000000
|
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_QSPI_AHB_INIT=y
|
CONFIG_QSPI_AHB_INIT=y
|
||||||
CONFIG_NR_DRAM_BANKS=2
|
CONFIG_NR_DRAM_BANKS=2
|
||||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||||
|
|
|
@ -1,7 +1,7 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_TARGET_LS1088AQDS=y
|
CONFIG_TARGET_LS1088AQDS=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x20100000
|
CONFIG_SYS_TEXT_BASE=0x20100000
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_FSL_LS_PPA=y
|
CONFIG_FSL_LS_PPA=y
|
||||||
CONFIG_QSPI_AHB_INIT=y
|
CONFIG_QSPI_AHB_INIT=y
|
||||||
CONFIG_NR_DRAM_BANKS=2
|
CONFIG_NR_DRAM_BANKS=2
|
||||||
|
|
|
@ -1,7 +1,7 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_TARGET_LS1088ARDB=y
|
CONFIG_TARGET_LS1088ARDB=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x20100000
|
CONFIG_SYS_TEXT_BASE=0x20100000
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_FSL_LS_PPA=y
|
CONFIG_FSL_LS_PPA=y
|
||||||
CONFIG_QSPI_AHB_INIT=y
|
CONFIG_QSPI_AHB_INIT=y
|
||||||
CONFIG_NR_DRAM_BANKS=2
|
CONFIG_NR_DRAM_BANKS=2
|
||||||
|
|
|
@ -3,7 +3,7 @@ CONFIG_TARGET_LS1088ARDB=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x80400000
|
CONFIG_SYS_TEXT_BASE=0x80400000
|
||||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_FSL_LS_PPA=y
|
CONFIG_FSL_LS_PPA=y
|
||||||
CONFIG_SPL_MMC_SUPPORT=y
|
CONFIG_SPL_MMC_SUPPORT=y
|
||||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||||
|
|
|
@ -3,7 +3,7 @@ CONFIG_TARGET_LS1088ARDB=y
|
||||||
CONFIG_TFABOOT=y
|
CONFIG_TFABOOT=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x82000000
|
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||||
CONFIG_SYS_MALLOC_F_LEN=0x6000
|
CONFIG_SYS_MALLOC_F_LEN=0x6000
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_QSPI_AHB_INIT=y
|
CONFIG_QSPI_AHB_INIT=y
|
||||||
CONFIG_NR_DRAM_BANKS=2
|
CONFIG_NR_DRAM_BANKS=2
|
||||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||||
|
|
|
@ -1,7 +1,7 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_TARGET_LS2080AQDS=y
|
CONFIG_TARGET_LS2080AQDS=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x30100000
|
CONFIG_SYS_TEXT_BASE=0x30100000
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_FSL_LS_PPA=y
|
CONFIG_FSL_LS_PPA=y
|
||||||
CONFIG_NR_DRAM_BANKS=3
|
CONFIG_NR_DRAM_BANKS=3
|
||||||
CONFIG_AHCI=y
|
CONFIG_AHCI=y
|
||||||
|
|
|
@ -1,7 +1,7 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_TARGET_LS2080ARDB=y
|
CONFIG_TARGET_LS2080ARDB=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x30100000
|
CONFIG_SYS_TEXT_BASE=0x30100000
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_FSL_LS_PPA=y
|
CONFIG_FSL_LS_PPA=y
|
||||||
CONFIG_NR_DRAM_BANKS=3
|
CONFIG_NR_DRAM_BANKS=3
|
||||||
CONFIG_AHCI=y
|
CONFIG_AHCI=y
|
||||||
|
|
|
@ -1,7 +1,7 @@
|
||||||
CONFIG_ARM=y
|
CONFIG_ARM=y
|
||||||
CONFIG_TARGET_LS2080ARDB=y
|
CONFIG_TARGET_LS2080ARDB=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x20100000
|
CONFIG_SYS_TEXT_BASE=0x20100000
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_FSL_LS_PPA=y
|
CONFIG_FSL_LS_PPA=y
|
||||||
CONFIG_QSPI_AHB_INIT=y
|
CONFIG_QSPI_AHB_INIT=y
|
||||||
CONFIG_NR_DRAM_BANKS=3
|
CONFIG_NR_DRAM_BANKS=3
|
||||||
|
|
|
@ -3,7 +3,7 @@ CONFIG_TARGET_LS2080ARDB=y
|
||||||
CONFIG_TFABOOT=y
|
CONFIG_TFABOOT=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x82000000
|
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||||
CONFIG_SYS_MALLOC_F_LEN=0x6000
|
CONFIG_SYS_MALLOC_F_LEN=0x6000
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_QSPI_AHB_INIT=y
|
CONFIG_QSPI_AHB_INIT=y
|
||||||
CONFIG_NR_DRAM_BANKS=3
|
CONFIG_NR_DRAM_BANKS=3
|
||||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||||
|
|
|
@ -3,7 +3,7 @@ CONFIG_TARGET_LX2160AQDS=y
|
||||||
CONFIG_TFABOOT=y
|
CONFIG_TFABOOT=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x82000000
|
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||||
CONFIG_SYS_MALLOC_F_LEN=0x6000
|
CONFIG_SYS_MALLOC_F_LEN=0x6000
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_NR_DRAM_BANKS=3
|
CONFIG_NR_DRAM_BANKS=3
|
||||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||||
|
|
|
@ -3,7 +3,7 @@ CONFIG_TARGET_LX2160ARDB=y
|
||||||
CONFIG_TFABOOT=y
|
CONFIG_TFABOOT=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x82000000
|
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||||
CONFIG_SYS_MALLOC_F_LEN=0x6000
|
CONFIG_SYS_MALLOC_F_LEN=0x6000
|
||||||
CONFIG_SECURE_BOOT=y
|
CONFIG_NXP_ESBC=y
|
||||||
CONFIG_EMC2305=y
|
CONFIG_EMC2305=y
|
||||||
CONFIG_NR_DRAM_BANKS=3
|
CONFIG_NR_DRAM_BANKS=3
|
||||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||||
|
|
|
@ -66,13 +66,13 @@
|
||||||
board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
|
board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_SECURE_BOOT
|
#ifdef CONFIG_NXP_ESBC
|
||||||
/*
|
/*
|
||||||
* HDR would be appended at end of image and copied to DDR along
|
* HDR would be appended at end of image and copied to DDR along
|
||||||
* with U-Boot image.
|
* with U-Boot image.
|
||||||
*/
|
*/
|
||||||
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
|
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
|
||||||
#endif /* ifdef CONFIG_SECURE_BOOT */
|
#endif /* ifdef CONFIG_NXP_ESBC */
|
||||||
|
|
||||||
#define CONFIG_SPL_MAX_SIZE 0x1a000
|
#define CONFIG_SPL_MAX_SIZE 0x1a000
|
||||||
#define CONFIG_SPL_STACK 0x1001d000
|
#define CONFIG_SPL_STACK 0x1001d000
|
||||||
|
|
|
@ -192,7 +192,7 @@
|
||||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
|
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
|
||||||
|
|
||||||
#ifdef CONFIG_SECURE_BOOT
|
#ifdef CONFIG_NXP_ESBC
|
||||||
#include <asm/fsl_secure_boot.h>
|
#include <asm/fsl_secure_boot.h>
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
|
@ -74,7 +74,7 @@
|
||||||
#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
|
#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
|
||||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
|
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
|
||||||
|
|
||||||
#ifdef CONFIG_SECURE_BOOT
|
#ifdef CONFIG_NXP_ESBC
|
||||||
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
|
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
|
||||||
/*
|
/*
|
||||||
* HDR would be appended at end of image and copied to DDR along
|
* HDR would be appended at end of image and copied to DDR along
|
||||||
|
@ -85,7 +85,7 @@
|
||||||
#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
|
#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
|
||||||
#else
|
#else
|
||||||
#define CONFIG_SYS_MONITOR_LEN 0x100000
|
#define CONFIG_SYS_MONITOR_LEN 0x100000
|
||||||
#endif /* ifdef CONFIG_SECURE_BOOT */
|
#endif /* ifdef CONFIG_NXP_ESBC */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* NAND SPL */
|
/* NAND SPL */
|
||||||
|
@ -100,9 +100,9 @@
|
||||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
|
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
|
||||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
|
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
|
||||||
|
|
||||||
#ifdef CONFIG_SECURE_BOOT
|
#ifdef CONFIG_NXP_ESBC
|
||||||
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
|
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
|
||||||
#endif /* ifdef CONFIG_SECURE_BOOT */
|
#endif /* ifdef CONFIG_NXP_ESBC */
|
||||||
|
|
||||||
#ifdef CONFIG_U_BOOT_HDR_SIZE
|
#ifdef CONFIG_U_BOOT_HDR_SIZE
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -73,7 +73,7 @@
|
||||||
CONFIG_SPL_BSS_MAX_SIZE)
|
CONFIG_SPL_BSS_MAX_SIZE)
|
||||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
|
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
|
||||||
|
|
||||||
#ifdef CONFIG_SECURE_BOOT
|
#ifdef CONFIG_NXP_ESBC
|
||||||
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
|
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
|
||||||
/*
|
/*
|
||||||
* HDR would be appended at end of image and copied to DDR along
|
* HDR would be appended at end of image and copied to DDR along
|
||||||
|
@ -84,7 +84,7 @@
|
||||||
#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
|
#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
|
||||||
#else
|
#else
|
||||||
#define CONFIG_SYS_MONITOR_LEN 0x100000
|
#define CONFIG_SYS_MONITOR_LEN 0x100000
|
||||||
#endif /* ifdef CONFIG_SECURE_BOOT */
|
#endif /* ifdef CONFIG_NXP_ESBC */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL)
|
#if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL)
|
||||||
|
|
|
@ -235,7 +235,7 @@ unsigned long long get_qixis_addr(void);
|
||||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
|
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
|
||||||
#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
|
#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
|
||||||
|
|
||||||
#ifdef CONFIG_SECURE_BOOT
|
#ifdef CONFIG_NXP_ESBC
|
||||||
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
|
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
|
||||||
/*
|
/*
|
||||||
* HDR would be appended at end of image and copied to DDR along
|
* HDR would be appended at end of image and copied to DDR along
|
||||||
|
@ -246,7 +246,7 @@ unsigned long long get_qixis_addr(void);
|
||||||
#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
|
#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
|
||||||
#else
|
#else
|
||||||
#define CONFIG_SYS_MONITOR_LEN 0x100000
|
#define CONFIG_SYS_MONITOR_LEN 0x100000
|
||||||
#endif /* ifdef CONFIG_SECURE_BOOT */
|
#endif /* ifdef CONFIG_NXP_ESBC */
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
||||||
|
|
|
@ -407,7 +407,7 @@ unsigned long get_board_ddr_clk(void);
|
||||||
QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
|
QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
|
||||||
|
|
||||||
/* Initial environment variables */
|
/* Initial environment variables */
|
||||||
#ifdef CONFIG_SECURE_BOOT
|
#ifdef CONFIG_NXP_ESBC
|
||||||
#undef CONFIG_EXTRA_ENV_SETTINGS
|
#undef CONFIG_EXTRA_ENV_SETTINGS
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||||
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
|
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
|
||||||
|
@ -426,7 +426,7 @@ unsigned long get_board_ddr_clk(void);
|
||||||
"sf read 0xa0740000 0x740000 0x4000;esbc_validate 0xa0740000;" \
|
"sf read 0xa0740000 0x740000 0x4000;esbc_validate 0xa0740000;" \
|
||||||
"fsl_mc start mc 0xa0a00000 0xa0e00000\0" \
|
"fsl_mc start mc 0xa0a00000 0xa0e00000\0" \
|
||||||
"mcmemsize=0x70000000 \0"
|
"mcmemsize=0x70000000 \0"
|
||||||
#else /* if !(CONFIG_SECURE_BOOT) */
|
#else /* if !(CONFIG_NXP_ESBC) */
|
||||||
#ifdef CONFIG_TFABOOT
|
#ifdef CONFIG_TFABOOT
|
||||||
#define QSPI_MC_INIT_CMD \
|
#define QSPI_MC_INIT_CMD \
|
||||||
"sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
|
"sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
|
||||||
|
@ -522,7 +522,7 @@ unsigned long get_board_ddr_clk(void);
|
||||||
"mcmemsize=0x70000000 \0"
|
"mcmemsize=0x70000000 \0"
|
||||||
#endif
|
#endif
|
||||||
#endif /* CONFIG_TFABOOT */
|
#endif /* CONFIG_TFABOOT */
|
||||||
#endif /* CONFIG_SECURE_BOOT */
|
#endif /* CONFIG_NXP_ESBC */
|
||||||
|
|
||||||
#ifdef CONFIG_FSL_MC_ENET
|
#ifdef CONFIG_FSL_MC_ENET
|
||||||
#define CONFIG_FSL_MEMAC
|
#define CONFIG_FSL_MEMAC
|
||||||
|
|
|
@ -352,7 +352,7 @@ unsigned long get_board_ddr_clk(void);
|
||||||
|
|
||||||
/* Initial environment variables */
|
/* Initial environment variables */
|
||||||
#undef CONFIG_EXTRA_ENV_SETTINGS
|
#undef CONFIG_EXTRA_ENV_SETTINGS
|
||||||
#ifdef CONFIG_SECURE_BOOT
|
#ifdef CONFIG_NXP_ESBC
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||||
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
|
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
|
||||||
"loadaddr=0x80100000\0" \
|
"loadaddr=0x80100000\0" \
|
||||||
|
@ -442,7 +442,7 @@ unsigned long get_board_ddr_clk(void);
|
||||||
"mcinitcmd=fsl_mc start mc 0x580a00000" \
|
"mcinitcmd=fsl_mc start mc 0x580a00000" \
|
||||||
" 0x580e00000 \0"
|
" 0x580e00000 \0"
|
||||||
#endif /* CONFIG_TFABOOT */
|
#endif /* CONFIG_TFABOOT */
|
||||||
#endif /* CONFIG_SECURE_BOOT */
|
#endif /* CONFIG_NXP_ESBC */
|
||||||
|
|
||||||
#ifdef CONFIG_TFABOOT
|
#ifdef CONFIG_TFABOOT
|
||||||
#define SD_BOOTCOMMAND \
|
#define SD_BOOTCOMMAND \
|
||||||
|
|
Loading…
Add table
Reference in a new issue