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arm: imx8m: add support for Compulab iot-gate-imx8 (imx8mm-cl-iot-gate)
Add initial support for Compulab iot-gate-imx8 board (imx8mm-cl-iot-gate). The initial support includes: - MMC - eMMC - I2C - FEC - Serial console Signed-off-by: Kirill Kapranov <kirill.kapranov@compulab.co.il> Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il> Signed-off-by: Valentin Raevsky <valentin@compulab.co.il> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: Peter Robinson <pbrobinson@gmail.com>
This commit is contained in:
Ying-Chun Liu (PaulLiu)
Stefano Babic
parent
8350211af4
commit
53b516c58d
16 changed files with 8289 additions and 0 deletions
211
board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
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211
board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017 NXP
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* Copyright 2020 Linaro
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*
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*/
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#include <common.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <command.h>
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#include <asm/io.h>
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#include <asm/arch/lpddr4_define.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/gpio.h>
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#include <asm-generic/gpio.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/imx8mq_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/clock.h>
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#include <asm/mach-imx/gpio.h>
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#include "ddr.h"
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static unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr)
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{
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unsigned int tmp;
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reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1);
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do {
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tmp = reg32_read(DDRC_MRSTAT(0));
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} while (tmp & 0x1);
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reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1);
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reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8));
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reg32setbit(DDRC_MRCTRL0(0), 31);
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do {
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tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0));
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} while ((tmp & 0x8) == 0);
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tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0));
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reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4);
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while (tmp) { //try to find a significant byte in the word
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if (tmp & 0xff) {
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tmp &= 0xff;
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break;
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}
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tmp >>= 8;
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}
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return tmp;
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}
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struct lpddr4_desc {
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char name[16];
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unsigned int id;
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unsigned int size;
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unsigned int count;
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/* an optional field
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* use it if default is not the
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* 1-st array entry
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*/
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unsigned int _default;
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/* An optional field to distiguish DRAM chips that
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* have different geometry, though return the same MRR.
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* Default value 0xff
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*/
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u8 subind;
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struct dram_timing_info *timing;
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char *desc[4];
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};
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#define DEFAULT (('D' << 24) + ('E' << 16) + ('F' << 8) + 'A')
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static const struct lpddr4_desc lpddr4_array[] = {
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{ .name = "Nanya", .id = 0x05000010, .subind = 0xff,
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.size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
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{ .name = "Samsung", .id = 0x01061010, .subind = 0xff,
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.size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
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{ .name = "Kingston", .id = 0xff000010, .subind = 0x04,
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.size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110},
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{ .name = "Kingston", .id = 0xff000010, .subind = 0x02,
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.size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
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{ .name = "Micron", .id = 0xff020008, .subind = 0xff,
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.size = 2048, .count = 1, .timing = &ucm_dram_timing_ff020008},
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{ .name = "Micron", .id = 0xff000110, .subind = 0xff,
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.size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110},
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};
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static unsigned int lpddr4_get_mr(void)
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{
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int i = 0, attempts = 5;
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unsigned int ddr_info = 0;
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unsigned int regs[] = { 5, 6, 7, 8 };
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do {
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for (i = 0 ; i < ARRAY_SIZE(regs) ; i++) {
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unsigned int data = 0;
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data = lpddr4_mr_read(0xF, regs[i]);
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ddr_info <<= 8;
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ddr_info += (data & 0xFF);
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}
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if (ddr_info != 0xFFFFFFFF && ddr_info != 0)
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break; // The attempt was successful
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} while (--attempts);
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return ddr_info;
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}
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static void spl_tcm_init(struct lpddr4_tcm_desc *lpddr4_tcm_desc)
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{
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if (lpddr4_tcm_desc->sign == DEFAULT)
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return;
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lpddr4_tcm_desc->sign = DEFAULT;
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lpddr4_tcm_desc->index = 0;
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}
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static void spl_tcm_fini(struct lpddr4_tcm_desc *lpddr4_tcm_desc)
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{
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if (lpddr4_tcm_desc->sign != DEFAULT)
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return;
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lpddr4_tcm_desc->sign = ~DEFAULT;
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lpddr4_tcm_desc->index = 0;
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}
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#define SPL_TCM_DATA 0x7e0000
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#define SPL_TCM_INIT spl_tcm_init(lpddr4_tcm_desc)
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#define SPL_TCM_FINI spl_tcm_fini(lpddr4_tcm_desc)
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void spl_dram_init_compulab(void)
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{
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unsigned int ddr_info = 0xdeadbeef;
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unsigned int ddr_info_mrr = 0xdeadbeef;
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unsigned int ddr_found = 0;
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int i = 0;
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struct lpddr4_tcm_desc *lpddr4_tcm_desc =
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(struct lpddr4_tcm_desc *)SPL_TCM_DATA;
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if (lpddr4_tcm_desc->sign != DEFAULT) {
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/* if not in tcm scan mode */
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for (i = 0; i < ARRAY_SIZE(lpddr4_array); i++) {
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if (lpddr4_array[i].id == ddr_info &&
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lpddr4_array[i].subind == 0xff) {
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ddr_found = 1;
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break;
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}
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}
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}
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/* Walk trought all available ddr ids and apply
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* one by one. Save the index at the tcm memory that
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* persists after the reset.
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*/
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if (ddr_found == 0) {
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SPL_TCM_INIT;
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if (lpddr4_tcm_desc->index < ARRAY_SIZE(lpddr4_array)) {
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printf("DDRINFO: Cfg attempt: [ %d/%lu ]\n",
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lpddr4_tcm_desc->index + 1,
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ARRAY_SIZE(lpddr4_array));
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i = lpddr4_tcm_desc->index;
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lpddr4_tcm_desc->index += 1;
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} else {
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/* Ran out all available ddr setings */
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printf("DDRINFO: Ran out all [ %lu ] cfg attempts. A non supported configuration.\n",
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ARRAY_SIZE(lpddr4_array));
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while (1)
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;
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}
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ddr_info = lpddr4_array[i].id;
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} else {
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printf("DDRINFO(%s): %s %dG\n", (ddr_found ? "D" : "?"),
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lpddr4_array[i].name,
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lpddr4_array[i].size);
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}
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if (ddr_init(lpddr4_array[i].timing)) {
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SPL_TCM_INIT;
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do_reset(NULL, 0, 0, NULL);
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}
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ddr_info_mrr = lpddr4_get_mr();
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if (ddr_info_mrr == 0xFFFFFFFF) {
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printf("DDRINFO(M): mr5-8 [ 0x%x ] is invalid; reset\n",
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ddr_info_mrr);
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SPL_TCM_INIT;
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do_reset(NULL, 0, 0, NULL);
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}
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printf("DDRINFO(M): mr5-8 [ 0x%x ]\n", ddr_info_mrr);
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printf("DDRINFO(%s): mr5-8 [ 0x%x ]\n", (ddr_found ? "E" : "T"),
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ddr_info);
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if (ddr_info_mrr != ddr_info) {
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SPL_TCM_INIT;
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do_reset(NULL, 0, 0, NULL);
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}
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SPL_TCM_FINI;
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/* Pass the dram size to th U-Boot through the tcm memory */
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{ /* To figure out what to store into the TCM buffer */
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/* For debug purpouse only. To override the real memsize */
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unsigned int ddr_tcm_size = 0;
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if (ddr_tcm_size == 0 || ddr_tcm_size == -1)
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ddr_tcm_size = lpddr4_array[i].size;
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lpddr4_tcm_desc->size = ddr_tcm_size;
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}
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}
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