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phy: phy-mtk-tphy: add properties for phy tuning
Add properties to improve eye diagram which sometimes need adjust some parameters of u2phy; Add a property to tune disconnect threshold; Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
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69600f4156
commit
4f6dd25800
1 changed files with 57 additions and 1 deletions
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@ -47,6 +47,11 @@
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#define PA0_USB20_PLL_PREDIV GENMASK(7, 6)
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#define PA0_USB20_PLL_PREDIV GENMASK(7, 6)
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#define PA0_RG_USB20_INTR_EN BIT(5)
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#define PA0_RG_USB20_INTR_EN BIT(5)
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#define U3P_USBPHYACR1 0x004
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#define PA1_RG_INTR_CAL GENMASK(23, 19)
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#define PA1_RG_VRT_SEL GENMASK(14, 12)
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#define PA1_RG_TERM_SEL GENMASK(10, 8)
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#define U3P_USBPHYACR2 0x008
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#define U3P_USBPHYACR2 0x008
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#define PA2_RG_U2PLL_BW GENMASK(21, 19)
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#define PA2_RG_U2PLL_BW GENMASK(21, 19)
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@ -56,8 +61,10 @@
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#define PA5_RG_U2_HS_100U_U3_EN BIT(11)
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#define PA5_RG_U2_HS_100U_U3_EN BIT(11)
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#define U3P_USBPHYACR6 0x018
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#define U3P_USBPHYACR6 0x018
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#define PA6_RG_U2_PRE_EMP GENMASK(31, 30)
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#define PA6_RG_U2_BC11_SW_EN BIT(23)
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#define PA6_RG_U2_BC11_SW_EN BIT(23)
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#define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20)
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#define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20)
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#define PA6_RG_U2_DISCTH GENMASK(7, 4)
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#define PA6_RG_U2_SQTH GENMASK(3, 0)
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#define PA6_RG_U2_SQTH GENMASK(3, 0)
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#define U3P_U2PHYACR4 0x020
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#define U3P_U2PHYACR4 0x020
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@ -240,7 +247,7 @@ struct u3phy_banks {
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struct mtk_phy_instance {
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struct mtk_phy_instance {
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void __iomem *port_base;
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void __iomem *port_base;
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const struct device_node *np;
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struct device_node *np;
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union {
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union {
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struct u2phy_banks u2_banks;
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struct u2phy_banks u2_banks;
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struct u3phy_banks u3_banks;
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struct u3phy_banks u3_banks;
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@ -250,6 +257,11 @@ struct mtk_phy_instance {
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struct clk da_ref_clk; /* reference clock of analog phy */
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struct clk da_ref_clk; /* reference clock of analog phy */
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u32 index;
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u32 index;
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u32 type;
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u32 type;
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u32 eye_vrt;
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u32 eye_term;
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u32 discth;
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u32 pre_emphasis;
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};
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};
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struct mtk_tphy {
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struct mtk_tphy {
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@ -564,6 +576,47 @@ static void phy_v2_banks_init(struct mtk_tphy *tphy,
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}
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}
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}
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}
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static void phy_parse_property(struct mtk_tphy *tphy,
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struct mtk_phy_instance *instance)
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{
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ofnode node = np_to_ofnode(instance->np);
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if (instance->type != PHY_TYPE_USB2)
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return;
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ofnode_read_u32(node, "mediatek,eye-vrt", &instance->eye_vrt);
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ofnode_read_u32(node, "mediatek,eye-term", &instance->eye_term);
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ofnode_read_u32(node, "mediatek,discth", &instance->discth);
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ofnode_read_u32(node, "mediatek,pre-emphasis", &instance->pre_emphasis);
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dev_dbg(tphy->dev, "vrt:%d, term:%d, disc:%d, emp:%d\n",
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instance->eye_vrt, instance->eye_term,
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instance->discth, instance->pre_emphasis);
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}
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static void u2_phy_props_set(struct mtk_tphy *tphy,
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struct mtk_phy_instance *instance)
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{
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struct u2phy_banks *u2_banks = &instance->u2_banks;
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void __iomem *com = u2_banks->com;
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if (instance->eye_vrt)
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clrsetbits_le32(com + U3P_USBPHYACR1, PA1_RG_VRT_SEL,
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FIELD_PREP(PA1_RG_VRT_SEL, instance->eye_vrt));
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if (instance->eye_term)
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clrsetbits_le32(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL,
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FIELD_PREP(PA1_RG_TERM_SEL, instance->eye_term));
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if (instance->discth)
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clrsetbits_le32(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH,
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FIELD_PREP(PA6_RG_U2_DISCTH, instance->discth));
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if (instance->pre_emphasis)
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clrsetbits_le32(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP,
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FIELD_PREP(PA6_RG_U2_PRE_EMP, instance->pre_emphasis));
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}
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static int mtk_phy_init(struct phy *phy)
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static int mtk_phy_init(struct phy *phy)
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{
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{
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struct mtk_tphy *tphy = dev_get_priv(phy->dev);
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struct mtk_tphy *tphy = dev_get_priv(phy->dev);
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@ -586,6 +639,7 @@ static int mtk_phy_init(struct phy *phy)
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switch (instance->type) {
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switch (instance->type) {
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case PHY_TYPE_USB2:
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case PHY_TYPE_USB2:
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u2_phy_instance_init(tphy, instance);
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u2_phy_instance_init(tphy, instance);
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u2_phy_props_set(tphy, instance);
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break;
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break;
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case PHY_TYPE_USB3:
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case PHY_TYPE_USB3:
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u3_phy_instance_init(tphy, instance);
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u3_phy_instance_init(tphy, instance);
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@ -692,6 +746,8 @@ static int mtk_phy_xlate(struct phy *phy,
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return -EINVAL;
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return -EINVAL;
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}
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}
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phy_parse_property(tphy, instance);
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return 0;
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return 0;
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}
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}
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