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driver/ddr: Change Freescale ARM DDR driver to support both big and little endian

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Initially it was believed the DDR controller on Freescale ARM would have
big endian. But some platform will have little endian.

Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
York Sun 2014-02-10 13:59:42 -08:00 • committed by Tom Rini
parent 9c89614d3f
commit 4e5b1bd0df
5 changed files with 74 additions and 58 deletions
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12
drivers/ddr/fsl/util.c
View file

@ -146,21 +146,21 @@ void board_add_ram_info(int use_default)
u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
#endif
#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
uint32_t cs0_config = in_be32(&ddr->cs0_config);
uint32_t cs0_config = ddr_in32(&ddr->cs0_config);
#endif
uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg);
uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg);
int cas_lat;
#if CONFIG_NUM_DDR_CONTROLLERS >= 2
if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
sdram_cfg = in_be32(&ddr->sdram_cfg);
sdram_cfg = ddr_in32(&ddr->sdram_cfg);
}
#endif
#if CONFIG_NUM_DDR_CONTROLLERS >= 3
if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
sdram_cfg = in_be32(&ddr->sdram_cfg);
sdram_cfg = ddr_in32(&ddr->sdram_cfg);
}
#endif
puts(" (DDR");
@ -188,8 +188,8 @@ void board_add_ram_info(int use_default)
puts(", 64-bit");
/* Calculate CAS latency based on timing cfg values */
cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1;
if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1)
cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1;
if ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 1)
cas_lat += (8 << 1);
printf(", CL=%d", cas_lat >> 1);
if (cas_lat & 0x1)