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arm: mach: exynos: Remove duplicate newlines

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Drop all duplicate newlines. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut 2024-07-13 15:19:08 +02:00 • committed by Tom Rini
parent 22a2c92c46
commit 4d1778e2e3
10 changed files with 0 additions and 15 deletions
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1
arch/arm/mach-exynos/common_setup.h
View file

@ -61,7 +61,6 @@ enum l2_cache_params {
CACHE_ENABLE_FORCE_L2_LOGIC = (1 << 27) CACHE_ENABLE_FORCE_L2_LOGIC = (1 << 27)
}; };
#if !defined(CONFIG_SYS_L2CACHE_OFF) && defined(CONFIG_EXYNOS5420) #if !defined(CONFIG_SYS_L2CACHE_OFF) && defined(CONFIG_EXYNOS5420)
/* /*
* Configure L2CTLR to get timings that keep us from hanging/crashing. * Configure L2CTLR to get timings that keep us from hanging/crashing.

2
arch/arm/mach-exynos/exynos4_setup.h
View file

@ -284,7 +284,6 @@
#define MFC_0_SEL MFC_SEL_MPLL #define MFC_0_SEL MFC_SEL_MPLL
#define CLK_SRC_MFC_VAL ((MFC_SEL << 8) | (MFC_0_SEL)) #define CLK_SRC_MFC_VAL ((MFC_SEL << 8) | (MFC_0_SEL))
/* CLK_DIV_MFC */ /* CLK_DIV_MFC */
#define MFC_RATIO 3 #define MFC_RATIO 3
#define CLK_DIV_MFC_VAL (MFC_RATIO) #define CLK_DIV_MFC_VAL (MFC_RATIO)
@ -498,7 +497,6 @@ struct mem_timings {
| ADD_LAT_PALL | MEM_TYPE_DDR3 | MEM_WIDTH_32\ | ADD_LAT_PALL | MEM_TYPE_DDR3 | MEM_WIDTH_32\
| NUM_CHIP_2 | BL_8) | NUM_CHIP_2 | BL_8)
#define CHIP_BANK_8 (0x3 << 0) #define CHIP_BANK_8 (0x3 << 0)
#define CHIP_ROW_14 (0x2 << 4) #define CHIP_ROW_14 (0x2 << 4)
#define CHIP_COL_10 (0x3 << 8) #define CHIP_COL_10 (0x3 << 8)

4
arch/arm/mach-exynos/exynos5_setup.h
View file

@ -685,7 +685,6 @@
#define PWM_RATIO 8 #define PWM_RATIO 8
#define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0) #define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0)
/* CLK_DIV_PERIC4 */ /* CLK_DIV_PERIC4 */
#define CLK_DIV_PERIC4_VAL NOT_AVAILABLE #define CLK_DIV_PERIC4_VAL NOT_AVAILABLE
@ -710,7 +709,6 @@
/* MPLL_CON1 */ /* MPLL_CON1 */
#define MPLL_CON1_VAL (0x0020F300) #define MPLL_CON1_VAL (0x0020F300)
/* CPLL_CON1 */ /* CPLL_CON1 */
#define CPLL_CON1_VAL 0x0020f300 #define CPLL_CON1_VAL 0x0020f300
@ -720,7 +718,6 @@
/* GPLL_CON1 */ /* GPLL_CON1 */
#define GPLL_CON1_VAL (NOT_AVAILABLE) #define GPLL_CON1_VAL (NOT_AVAILABLE)
/* EPLL_CON1, CON2 */ /* EPLL_CON1, CON2 */
#define EPLL_CON1_VAL 0x00000000 #define EPLL_CON1_VAL 0x00000000
#define EPLL_CON2_VAL 0x00000080 #define EPLL_CON2_VAL 0x00000080
@ -750,7 +747,6 @@
#define CLK_DIV_ISP0_VAL 0x13131300 #define CLK_DIV_ISP0_VAL 0x13131300
#define CLK_DIV_ISP1_VAL 0xbb110202 #define CLK_DIV_ISP1_VAL 0xbb110202
/* CLK_FSYS */ /* CLK_FSYS */
#define CLK_SRC_FSYS0_VAL 0x33033300 #define CLK_SRC_FSYS0_VAL 0x33033300
#define CLK_DIV_FSYS0_VAL 0x0 #define CLK_DIV_FSYS0_VAL 0x0

1
arch/arm/mach-exynos/include/mach/cpu.h
View file

@ -190,7 +190,6 @@
#define EXYNOS5420_MODEM_BASE DEVICE_NOT_AVAILABLE #define EXYNOS5420_MODEM_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5420_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE #define EXYNOS5420_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
#include <asm/io.h> #include <asm/io.h>
/* CPU detection macros */ /* CPU detection macros */

1
arch/arm/mach-exynos/include/mach/dp_info.h
View file

@ -183,7 +183,6 @@ enum {
VIDEO_TIMING_FROM_REGISTER VIDEO_TIMING_FROM_REGISTER
}; };
struct exynos_dp_platform_data { struct exynos_dp_platform_data {
struct exynos_dp_priv *edp_dev_info; struct exynos_dp_priv *edp_dev_info;
}; };

1
arch/arm/mach-exynos/include/mach/power.h
View file

@ -1752,7 +1752,6 @@ void set_xclkout(void);
*/ */
uint32_t get_reset_status(void); uint32_t get_reset_status(void);
/* Read the resume function and call it */ /* Read the resume function and call it */
void power_exit_wakeup(void); void power_exit_wakeup(void);

1
arch/arm/mach-exynos/include/mach/sound.h
View file

@ -4,7 +4,6 @@
* Rajeshwari Shinde <rajeshwari.s@samsung.com> * Rajeshwari Shinde <rajeshwari.s@samsung.com>
*/ */
#ifndef __SOUND_ARCH_H__ #ifndef __SOUND_ARCH_H__
#define __SOUND_ARCH_H__ #define __SOUND_ARCH_H__

1
arch/arm/mach-exynos/pinmux.c
View file

@ -391,7 +391,6 @@ static void exynos5420_i2s_config(int peripheral)
} }
} }
void exynos5_spi_config(int peripheral) void exynos5_spi_config(int peripheral)
{ {
int cfg = 0, pin = 0, i; int cfg = 0, pin = 0, i;

2
arch/arm/mach-exynos/power.c
View file

@ -20,7 +20,6 @@ static void exynos4_mipi_phy_control(unsigned int dev_index,
else else
addr = (unsigned int)&pmu->mipi_phy1_control; addr = (unsigned int)&pmu->mipi_phy1_control;
cfg = readl(addr); cfg = readl(addr);
if (enable) if (enable)
cfg |= (EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE); cfg |= (EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
@ -174,7 +173,6 @@ void set_ps_hold_ctrl(void)
exynos5_set_ps_hold_ctrl(); exynos5_set_ps_hold_ctrl();
} }
static void exynos5_set_xclkout(void) static void exynos5_set_xclkout(void)
{ {
struct exynos5_power *power = struct exynos5_power *power =

1
arch/arm/mach-s5pc1xx/include/mach/cpu.h
View file

@ -45,7 +45,6 @@
#define S5PC110_PHY_BASE 0xEC100000 #define S5PC110_PHY_BASE 0xEC100000
#define S5PC110_USB_PHY_CONTROL 0xE010E80C #define S5PC110_USB_PHY_CONTROL 0xE010E80C
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
#include <asm/io.h> #include <asm/io.h>
/* CPU detection macros */ /* CPU detection macros */