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net: dwc_eth_qos: Add glue driver for Intel MAC
Add dwc_eth_qos glue driver for the Intel Elkhart-Lake SOC. Signed-off-by: Philip Oberfichtner <pro@denx.de>
This commit is contained in:
Philip Oberfichtner
Tom Rini
parent
2689b14ef3
commit
49d8fe07f9
7 changed files with 536 additions and 0 deletions
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@ -243,6 +243,13 @@ config DWC_ETH_QOS_IMX
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The Synopsys Designware Ethernet QOS IP block with the specific
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configuration used in IMX soc.
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config DWC_ETH_QOS_INTEL
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bool "Synopsys DWC Ethernet QOS device support for Intel"
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depends on DWC_ETH_QOS
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help
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The Synopsys Designware Ethernet QOS IP block with the specific
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configuration used in the Intel Elkhart-Lake soc.
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config DWC_ETH_QOS_ROCKCHIP
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bool "Synopsys DWC Ethernet QOS device support for Rockchip SoCs"
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depends on DWC_ETH_QOS
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@ -20,6 +20,7 @@ obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
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obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
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obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
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obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
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obj-$(CONFIG_DWC_ETH_QOS_INTEL) += dwc_eth_qos_intel.o
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obj-$(CONFIG_DWC_ETH_QOS_ROCKCHIP) += dwc_eth_qos_rockchip.o
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obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o
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obj-$(CONFIG_DWC_ETH_XGMAC) += dwc_eth_xgmac.o
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@ -1434,6 +1434,18 @@ int eqos_get_base_addr_dt(struct udevice *dev)
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return eqos_get_base_addr_common(dev, addr);
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}
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int eqos_get_base_addr_pci(struct udevice *dev)
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{
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fdt_addr_t addr;
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void *paddr;
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paddr = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE,
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PCI_REGION_MEM);
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addr = paddr ? (fdt_addr_t)paddr : FDT_ADDR_T_NONE;
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return eqos_get_base_addr_common(dev, addr);
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}
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static int eqos_probe(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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@ -290,6 +290,7 @@ void eqos_flush_desc_generic(void *desc);
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void eqos_inval_buffer_generic(void *buf, size_t size);
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void eqos_flush_buffer_generic(void *buf, size_t size);
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int eqos_get_base_addr_dt(struct udevice *dev);
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int eqos_get_base_addr_pci(struct udevice *dev);
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int eqos_null_ops(struct udevice *dev);
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void *eqos_get_driver_data(struct udevice *dev);
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449
drivers/net/dwc_eth_qos_intel.c
Normal file
449
drivers/net/dwc_eth_qos_intel.c
Normal file
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@ -0,0 +1,449 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2023-2024 DENX Software Engineering GmbH
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* Philip Oberfichtner <pro@denx.de>
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*
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* Based on linux v6.6.39, especially drivers/net/ethernet/stmicro/stmmac
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*/
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#include <asm/io.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#include <miiphy.h>
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#include <net.h>
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#include <pci.h>
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#include "dwc_eth_qos.h"
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#include "dwc_eth_qos_intel.h"
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static struct pci_device_id intel_pci_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_RGMII1G) },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_SGMII1) },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_SGMII2G5) },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G) },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G) },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5) },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G) },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G) },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5) },
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{}
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};
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static int pci_config(struct udevice *dev)
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{
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u32 val;
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/* Try to enable I/O accesses and bus-mastering */
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dm_pci_read_config32(dev, PCI_COMMAND, &val);
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val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
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dm_pci_write_config32(dev, PCI_COMMAND, val);
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/* Make sure it worked */
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dm_pci_read_config32(dev, PCI_COMMAND, &val);
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if (!(val & PCI_COMMAND_MEMORY)) {
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dev_err(dev, "%s: Can't enable I/O memory\n", __func__);
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return -ENOSPC;
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}
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if (!(val & PCI_COMMAND_MASTER)) {
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dev_err(dev, "%s: Can't enable bus-mastering\n", __func__);
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return -EPERM;
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}
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return 0;
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}
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static void limit_fifo_size(struct udevice *dev)
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{
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/*
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* As described in Intel Erratum EHL22, Document Number: 636674-2.1,
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* the PSE GbE Controllers advertise a wrong RX and TX fifo size.
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* Software should limit this value to 64KB.
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*/
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struct eqos_priv *eqos = dev_get_priv(dev);
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eqos->tx_fifo_sz = 0x8000;
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eqos->rx_fifo_sz = 0x8000;
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}
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static int serdes_status_poll(struct udevice *dev,
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unsigned char phyaddr, unsigned char phyreg,
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unsigned short mask, unsigned short val)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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unsigned int retries = 10;
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unsigned short val_rd;
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do {
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miiphy_read(eqos->mii->name, phyaddr, phyreg, &val_rd);
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if ((val_rd & mask) == (val & mask))
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return 0;
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udelay(POLL_DELAY_US);
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} while (--retries);
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return -ETIMEDOUT;
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}
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/* Returns -ve if MAC is unknown and 0 on success */
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static int mac_check_pse(const struct udevice *dev, bool *is_pse)
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{
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struct pci_child_plat *plat = dev_get_parent_plat(dev);
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if (!plat || plat->vendor != PCI_VENDOR_ID_INTEL)
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return -ENXIO;
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switch (plat->device) {
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case PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G:
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case PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G:
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case PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G:
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case PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G:
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case PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5:
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case PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5:
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*is_pse = 1;
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return 0;
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case PCI_DEVICE_ID_INTEL_EHL_RGMII1G:
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case PCI_DEVICE_ID_INTEL_EHL_SGMII1:
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case PCI_DEVICE_ID_INTEL_EHL_SGMII2G5:
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*is_pse = 0;
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return 0;
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};
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return -ENXIO;
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}
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/* Check if we're in 2G5 mode */
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static bool serdes_link_mode_2500(struct udevice *dev)
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{
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const unsigned char phyad = INTEL_MGBE_ADHOC_ADDR;
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struct eqos_priv *eqos = dev_get_priv(dev);
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unsigned short data;
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miiphy_read(eqos->mii->name, phyad, SERDES_GCR, &data);
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if (FIELD_GET(SERDES_LINK_MODE_MASK, data) == SERDES_LINK_MODE_2G5)
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return true;
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return false;
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}
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static int serdes_powerup(struct udevice *dev)
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{
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/* Based on linux/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c */
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const unsigned char phyad = INTEL_MGBE_ADHOC_ADDR;
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struct eqos_priv *eqos = dev_get_priv(dev);
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unsigned short data;
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int ret;
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bool is_pse;
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/* Set the serdes rate and the PCLK rate */
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miiphy_read(eqos->mii->name, phyad, SERDES_GCR0, &data);
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data &= ~SERDES_RATE_MASK;
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data &= ~SERDES_PCLK_MASK;
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if (serdes_link_mode_2500(dev))
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data |= SERDES_RATE_PCIE_GEN2 << SERDES_RATE_PCIE_SHIFT |
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SERDES_PCLK_37p5MHZ << SERDES_PCLK_SHIFT;
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else
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data |= SERDES_RATE_PCIE_GEN1 << SERDES_RATE_PCIE_SHIFT |
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SERDES_PCLK_70MHZ << SERDES_PCLK_SHIFT;
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miiphy_write(eqos->mii->name, phyad, SERDES_GCR0, data);
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/* assert clk_req */
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miiphy_read(eqos->mii->name, phyad, SERDES_GCR0, &data);
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data |= SERDES_PLL_CLK;
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miiphy_write(eqos->mii->name, phyad, SERDES_GCR0, data);
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/* check for clk_ack assertion */
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ret = serdes_status_poll(dev, phyad, SERDES_GSR0,
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SERDES_PLL_CLK, SERDES_PLL_CLK);
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if (ret) {
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dev_err(dev, "Serdes PLL clk request timeout\n");
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return ret;
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}
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/* assert lane reset*/
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miiphy_read(eqos->mii->name, phyad, SERDES_GCR0, &data);
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data |= SERDES_RST;
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miiphy_write(eqos->mii->name, phyad, SERDES_GCR0, data);
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/* check for assert lane reset reflection */
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ret = serdes_status_poll(dev, phyad, SERDES_GSR0,
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SERDES_RST, SERDES_RST);
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if (ret) {
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dev_err(dev, "Serdes assert lane reset timeout\n");
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return ret;
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}
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/* move power state to P0 */
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miiphy_read(eqos->mii->name, phyad, SERDES_GCR0, &data);
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data &= ~SERDES_PWR_ST_MASK;
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data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT;
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miiphy_write(eqos->mii->name, phyad, SERDES_GCR0, data);
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/* Check for P0 state */
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ret = serdes_status_poll(dev, phyad, SERDES_GSR0,
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SERDES_PWR_ST_MASK,
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SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT);
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if (ret) {
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dev_err(dev, "Serdes power state P0 timeout.\n");
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return ret;
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}
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/* PSE only - ungate SGMII PHY Rx Clock*/
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ret = mac_check_pse(dev, &is_pse);
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if (ret) {
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dev_err(dev, "Failed to determine MAC type.\n");
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return ret;
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}
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if (is_pse) {
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miiphy_read(eqos->mii->name, phyad, SERDES_GCR0, &data);
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data |= SERDES_PHY_RX_CLK;
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miiphy_write(eqos->mii->name, phyad, SERDES_GCR0, data);
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}
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return 0;
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}
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static int xpcs_access(struct udevice *dev, int reg, int v)
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{
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/*
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* Common read/write helper function
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*
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* It may seem a bit odd at a first glance that we use bus->read()
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* directly insetad of one of the wrapper functions. But:
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*
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* (1) phy_read() can't be used because we do not access an acutal PHY,
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* but a MAC-internal submodule.
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*
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* (2) miiphy_read() can't be used because it assumes MDIO_DEVAD_NONE.
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*/
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int port = INTEL_MGBE_XPCS_ADDR;
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int devad = 0x1f;
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u16 val;
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struct eqos_priv *eqos;
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struct mii_dev *bus;
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eqos = dev_get_priv(dev);
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bus = eqos->mii;
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if (v < 0)
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return bus->read(bus, port, devad, reg);
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val = v;
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return bus->write(bus, port, devad, reg, val);
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}
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static int xpcs_read(struct udevice *dev, int reg)
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{
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return xpcs_access(dev, reg, -1);
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}
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static int xpcs_write(struct udevice *dev, int reg, u16 val)
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{
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return xpcs_access(dev, reg, val);
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}
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static int xpcs_clr_bits(struct udevice *dev, int reg, u16 bits)
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{
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int ret;
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ret = xpcs_read(dev, reg);
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if (ret < 0)
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return ret;
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ret &= ~bits;
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return xpcs_write(dev, reg, ret);
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}
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static int xpcs_set_bits(struct udevice *dev, int reg, u16 bits)
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{
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int ret;
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ret = xpcs_read(dev, reg);
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if (ret < 0)
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return ret;
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ret |= bits;
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return xpcs_write(dev, reg, ret);
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}
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static int xpcs_init(struct udevice *dev)
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{
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/* Based on linux/drivers/net/pcs/pcs-xpcs.c */
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struct eqos_priv *eqos = dev_get_priv(dev);
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phy_interface_t interface = eqos->config->interface(dev);
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if (interface != PHY_INTERFACE_MODE_SGMII)
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return 0;
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if (xpcs_clr_bits(dev, VR_MII_MMD_CTRL, XPCS_AN_CL37_EN) ||
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xpcs_set_bits(dev, VR_MII_AN_CTRL, XPCS_MODE_SGMII) ||
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xpcs_set_bits(dev, VR_MII_DIG_CTRL1, XPCS_MAC_AUTO_SW) ||
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xpcs_set_bits(dev, VR_MII_MMD_CTRL, XPCS_AN_CL37_EN))
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return -EIO;
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return 0;
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}
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static int eqos_probe_ressources_intel(struct udevice *dev)
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{
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int ret;
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ret = eqos_get_base_addr_pci(dev);
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if (ret) {
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dev_err(dev, "eqos_get_base_addr_pci failed: %d\n", ret);
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return ret;
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}
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limit_fifo_size(dev);
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ret = pci_config(dev);
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if (ret) {
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dev_err(dev, "pci_config failed: %d\n", ret);
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return ret;
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}
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return 0;
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}
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struct eqos_config eqos_intel_config;
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/*
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* overwrite __weak function from eqos_intel.c
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*
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* For PCI devices the devcie tree is optional. Choose driver data based on PCI
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* IDs instead.
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*/
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void *eqos_get_driver_data(struct udevice *dev)
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{
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const struct pci_device_id *id;
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const struct pci_child_plat *plat;
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plat = dev_get_parent_plat(dev);
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if (!plat)
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return NULL;
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/* last intel_pci_ids element is zero initialized */
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for (id = intel_pci_ids; id->vendor != 0; id++) {
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if (id->vendor == plat->vendor && id->device == plat->device)
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return &eqos_intel_config;
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}
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return NULL;
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}
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static int eqos_start_resets_intel(struct udevice *dev)
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{
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int ret;
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ret = xpcs_init(dev);
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if (ret) {
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dev_err(dev, "xpcs init failed.\n");
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return ret;
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}
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ret = serdes_powerup(dev);
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if (ret) {
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dev_err(dev, "Failed to power up serdes.\n");
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return ret;
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}
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return 0;
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}
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static ulong eqos_get_tick_clk_rate_intel(struct udevice *dev)
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{
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return 0;
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}
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static int eqos_get_enetaddr_intel(struct udevice *dev)
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{
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/* Assume MAC address is programmed by previous boot stage */
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struct eth_pdata *plat = dev_get_plat(dev);
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struct eqos_priv *eqos = dev_get_priv(dev);
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u8 *lo = (u8 *)&eqos->mac_regs->address0_low;
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u8 *hi = (u8 *)&eqos->mac_regs->address0_high;
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|
||||
plat->enetaddr[0] = lo[0];
|
||||
plat->enetaddr[1] = lo[1];
|
||||
plat->enetaddr[2] = lo[2];
|
||||
plat->enetaddr[3] = lo[3];
|
||||
plat->enetaddr[4] = hi[0];
|
||||
plat->enetaddr[5] = hi[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static phy_interface_t eqos_get_interface_intel(const struct udevice *dev)
|
||||
{
|
||||
struct pci_child_plat *plat = dev_get_parent_plat(dev);
|
||||
|
||||
if (!plat || plat->vendor != PCI_VENDOR_ID_INTEL)
|
||||
return PHY_INTERFACE_MODE_NA;
|
||||
|
||||
switch (plat->device) {
|
||||
/* The GbE Host Controller has no RGMII interface */
|
||||
case PCI_DEVICE_ID_INTEL_EHL_RGMII1G:
|
||||
return PHY_INTERFACE_MODE_NA;
|
||||
|
||||
case PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G:
|
||||
case PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G:
|
||||
return PHY_INTERFACE_MODE_RGMII;
|
||||
|
||||
/* Host SGMII and Host SGMII2G5 share the same device id */
|
||||
case PCI_DEVICE_ID_INTEL_EHL_SGMII1:
|
||||
case PCI_DEVICE_ID_INTEL_EHL_SGMII2G5:
|
||||
case PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5:
|
||||
case PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G:
|
||||
case PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G:
|
||||
case PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5:
|
||||
return PHY_INTERFACE_MODE_SGMII;
|
||||
};
|
||||
|
||||
return PHY_INTERFACE_MODE_NA;
|
||||
}
|
||||
|
||||
static struct eqos_ops eqos_intel_ops = {
|
||||
.eqos_inval_desc = eqos_inval_desc_generic,
|
||||
.eqos_flush_desc = eqos_flush_desc_generic,
|
||||
.eqos_inval_buffer = eqos_inval_buffer_generic,
|
||||
.eqos_flush_buffer = eqos_flush_buffer_generic,
|
||||
.eqos_probe_resources = eqos_probe_ressources_intel,
|
||||
.eqos_remove_resources = eqos_null_ops,
|
||||
.eqos_stop_resets = eqos_null_ops,
|
||||
.eqos_start_resets = eqos_start_resets_intel,
|
||||
.eqos_stop_clks = eqos_null_ops,
|
||||
.eqos_start_clks = eqos_null_ops,
|
||||
.eqos_calibrate_pads = eqos_null_ops,
|
||||
.eqos_disable_calibration = eqos_null_ops,
|
||||
.eqos_set_tx_clk_speed = eqos_null_ops,
|
||||
.eqos_get_enetaddr = eqos_get_enetaddr_intel,
|
||||
.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_intel,
|
||||
};
|
||||
|
||||
struct eqos_config eqos_intel_config = {
|
||||
.reg_access_always_ok = false,
|
||||
.mdio_wait = 10,
|
||||
.swr_wait = 50,
|
||||
.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
|
||||
.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
|
||||
.axi_bus_width = EQOS_AXI_WIDTH_64,
|
||||
.interface = eqos_get_interface_intel,
|
||||
.ops = &eqos_intel_ops
|
||||
};
|
||||
|
||||
extern U_BOOT_DRIVER(eth_eqos);
|
||||
U_BOOT_PCI_DEVICE(eth_eqos, intel_pci_ids);
|
||||
57
drivers/net/dwc_eth_qos_intel.h
Normal file
57
drivers/net/dwc_eth_qos_intel.h
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* Copyright (c) 2023-2024 DENX Software Engineering GmbH
|
||||
* Philip Oberfichtner <pro@denx.de>
|
||||
*
|
||||
* This header is based on linux v6.6.39,
|
||||
*
|
||||
* drivers/net/pcs/pcs-xpcs.h
|
||||
* drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h,
|
||||
*
|
||||
* Copyright (c) 2020 Synopsys, Inc. and/or its affiliates
|
||||
* Copyright (c) 2020 Intel Corporation
|
||||
*/
|
||||
|
||||
#ifndef __DWMAC_INTEL_H__
|
||||
#define __DWMAC_INTEL_H__
|
||||
|
||||
#define POLL_DELAY_US 8
|
||||
|
||||
/* SERDES Register */
|
||||
#define SERDES_GCR 0x0 /* Global Conguration */
|
||||
#define SERDES_GSR0 0x5 /* Global Status Reg0 */
|
||||
#define SERDES_GCR0 0xb /* Global Configuration Reg0 */
|
||||
|
||||
/* SERDES defines */
|
||||
#define SERDES_PLL_CLK BIT(0) /* PLL clk valid signal */
|
||||
#define SERDES_PHY_RX_CLK BIT(1) /* PSE SGMII PHY rx clk */
|
||||
#define SERDES_RST BIT(2) /* Serdes Reset */
|
||||
#define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/
|
||||
#define SERDES_RATE_MASK GENMASK(9, 8)
|
||||
#define SERDES_PCLK_MASK GENMASK(14, 12) /* PCLK rate to PHY */
|
||||
#define SERDES_LINK_MODE_MASK GENMASK(2, 1)
|
||||
#define SERDES_PWR_ST_SHIFT 4
|
||||
#define SERDES_PWR_ST_P0 0x0
|
||||
#define SERDES_PWR_ST_P3 0x3
|
||||
#define SERDES_LINK_MODE_2G5 0x3
|
||||
#define SERSED_LINK_MODE_1G 0x2
|
||||
#define SERDES_PCLK_37p5MHZ 0x0
|
||||
#define SERDES_PCLK_70MHZ 0x1
|
||||
#define SERDES_RATE_PCIE_GEN1 0x0
|
||||
#define SERDES_RATE_PCIE_GEN2 0x1
|
||||
#define SERDES_RATE_PCIE_SHIFT 8
|
||||
#define SERDES_PCLK_SHIFT 12
|
||||
|
||||
#define INTEL_MGBE_ADHOC_ADDR 0x15
|
||||
#define INTEL_MGBE_XPCS_ADDR 0x16
|
||||
|
||||
/* XPCS defines */
|
||||
#define XPCS_MODE_SGMII BIT(2)
|
||||
#define XPCS_MAC_AUTO_SW BIT(9)
|
||||
#define XPCS_AN_CL37_EN BIT(12)
|
||||
|
||||
#define VR_MII_MMD_CTRL 0x0000
|
||||
#define VR_MII_DIG_CTRL1 0x8000
|
||||
#define VR_MII_AN_CTRL 0x8001
|
||||
|
||||
#endif /* __DWMAC_INTEL_H__ */
|
||||
|
|
@ -2600,6 +2600,15 @@
|
|||
#define PCI_DEVICE_ID_DCI_PCCOM2 0x0004
|
||||
|
||||
#define PCI_VENDOR_ID_INTEL 0x8086
|
||||
#define PCI_DEVICE_ID_INTEL_EHL_RGMII1G 0x4b30
|
||||
#define PCI_DEVICE_ID_INTEL_EHL_SGMII1 0x4b31
|
||||
#define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5 0x4b32
|
||||
#define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G 0x4ba0
|
||||
#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G 0x4ba1
|
||||
#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5 0x4ba2
|
||||
#define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G 0x4bb0
|
||||
#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G 0x4bb1
|
||||
#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5 0x4bb2
|
||||
#define PCI_DEVICE_ID_INTEL_EESSC 0x0008
|
||||
#define PCI_DEVICE_ID_INTEL_SNB_IMC 0x0100
|
||||
#define PCI_DEVICE_ID_INTEL_IVB_IMC 0x0154
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue