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Merge tag 'u-boot-imx-master-20240706' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Browse source 
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/21504

- Fixes for i.MX8M and i.MX93 clk-composite.
- Set CAN oscillator frequency based on model on verdin-imx8mm.
- Enable CAAM for phycore-imx8mp_defconfig.
- Miscellaneous improvements for Gateworks i.MX8M boards.
- Fix initramfs boot on msc_sm2s_imx8mp.
- Fixe EQoS on imx8mp-beacon-kit.
- Fix error message in fsl_esdhc_imx.
This commit is contained in:
Tom Rini 2024-07-08 08:45:02 -06:00
commit 4480b53b19
14 changed files with 92 additions and 24 deletions
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1
arch/arm/dts/Makefile
View file

@ -1298,6 +1298,7 @@ targets += $(dtb-y)
# Add any required device tree compiler flags here
DTC_FLAGS += -a 0x8
DTC_FLAGS_imx8mp-dhcom-som-overlay-rev100 += -Wno-avoid_default_addr_size -Wno-reg_format
DTC_FLAGS_imx8mp-dhcom-pdk3-overlay-rev100 += -Wno-avoid_default_addr_size -Wno-reg_format
PHONY += dtbs

6
arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi
View file

@ -32,12 +32,6 @@
bootph-pre-ram;
};
&eqos {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&ethphy0 {
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
reset-assert-us = <15000>;

5
arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts
View file

@ -35,6 +35,7 @@
&ethphy0f { /* SMSC LAN8740Ai */
pinctrl-0 = <&pinctrl_ethphy0 &pinctrl_ioexp>;
reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
reg = <0>;
};
&ethphy0g { /* Micrel KSZ9131RNXI */
@ -42,6 +43,10 @@
reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
};
&ethphy1f { /* SMSC LAN8740Ai */
reg = <1>;
};
&i2c3 {
adc@48 {
compatible = "ti,tla2024";

8
arch/arm/dts/imx8mp-dhcom-som.dtsi
View file

@ -100,14 +100,14 @@
#size-cells = <0>;
/* Up to one of these two PHYs may be populated. */
ethphy0f: ethernet-phy@0 { /* SMSC LAN8740Ai */
ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */
compatible = "ethernet-phy-id0007.c110",
"ethernet-phy-ieee802.3-c22";
interrupt-parent = <&gpio3>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_ethphy0>;
pinctrl-names = "default";
reg = <0>;
reg = <1>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>;
@ -146,14 +146,14 @@
#size-cells = <0>;
/* Up to one PHY may be populated. */
ethphy1f: ethernet-phy@1 { /* SMSC LAN8740Ai */
ethphy1f: ethernet-phy@2 { /* SMSC LAN8740Ai */
compatible = "ethernet-phy-id0007.c110",
"ethernet-phy-ieee802.3-c22";
interrupt-parent = <&gpio4>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_ethphy1>;
pinctrl-names = "default";
reg = <1>;
reg = <2>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;

29
board/toradex/verdin-imx8mm/verdin-imx8mm.c
View file

@ -126,6 +126,35 @@ int board_phys_sdram_size(phys_size_t *size)
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
const char *canoscpath = "/oscillator";
int freq = 40000000; /* 40 MHz is used on most variants */
int canoscoff, ret;
canoscoff = fdt_path_offset(blob, canoscpath);
if (canoscoff < 0) /* No CAN oscillator found. */
goto exit;
/*
* The following "prodid" (PID4 in Toradex naming) use
* a 20MHz CAN oscillator:
* - 0055, V1.1A, V1.1B, V1.1C and V1.1D
* - 0059, V1.1A and V1.1B
*/
if ((tdx_hw_tag.ver_major == 1 && tdx_hw_tag.ver_minor == 1) &&
((tdx_hw_tag.prodid == VERDIN_IMX8MMQ_IT &&
tdx_hw_tag.ver_assembly <= 1) || /* 0059 rev. A or B */
(tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT &&
tdx_hw_tag.ver_assembly <= 3))) { /* 0055 rev. A/B/C/D */
freq = 20000000;
}
ret = fdt_setprop_u32(blob, canoscoff, "clock-frequency", freq);
if (ret < 0) {
printf("Failed to set CAN oscillator clock-frequency, ret=%d\n",
ret);
}
exit:
return ft_common_board_setup(blob, bd);
}
#endif

3
configs/imx8mp_dhcom_pdk2_defconfig
View file

@ -108,6 +108,8 @@ CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CAT=y
CONFIG_CMD_XXD=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_DHCP6=y
CONFIG_CMD_TFTPPUT=y
@ -180,6 +182,7 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_GPIO_HOG=y
CONFIG_SPL_GPIO_HOG=y
CONFIG_MXC_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
# CONFIG_INPUT is not set
CONFIG_LED=y

2
configs/imx8mp_dhcom_pdk3_defconfig
View file

@ -111,6 +111,8 @@ CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CAT=y
CONFIG_CMD_XXD=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_DHCP6=y
CONFIG_CMD_TFTPPUT=y

5
configs/phycore-imx8mp_defconfig
View file

@ -32,6 +32,7 @@ CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="oftree"
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2074
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SPL_BOARD_INIT=y
@ -44,6 +45,7 @@ CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
# CONFIG_SPL_CRYPTO is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
@ -86,6 +88,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_CLK_IMX8MP=y
CONFIG_FSL_CAAM=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x42800000
CONFIG_FASTBOOT_BUF_SIZE=0x13000000
@ -101,7 +104,6 @@ CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
# CONFIG_SPL_DM_I2C is not set
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x51
CONFIG_SUPPORT_EMMC_BOOT=y
@ -151,3 +153,4 @@ CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_IMX_WATCHDOG=y
# CONFIG_SPL_SHA_HW_ACCEL is not set

5
drivers/clk/clk-mux.c
View file

@ -101,8 +101,7 @@ u8 clk_mux_get_parent(struct clk *clk)
return clk_mux_val_to_index(clk, mux->table, mux->flags, val);
}
static int clk_fetch_parent_index(struct clk *clk,
struct clk *parent)
int clk_mux_fetch_parent_index(struct clk *clk, struct clk *parent)
{
struct clk_mux *mux = to_clk_mux(clk);
@ -126,7 +125,7 @@ static int clk_mux_set_parent(struct clk *clk, struct clk *parent)
u32 val;
u32 reg;
index = clk_fetch_parent_index(clk, parent);
index = clk_mux_fetch_parent_index(clk, parent);
if (index < 0) {
log_err("Could not fetch index\n");
return index;

41
drivers/clk/imx/clk-composite-8m.c
View file

@ -116,6 +116,41 @@ static const struct clk_ops imx8m_clk_composite_divider_ops = {
.set_rate = imx8m_clk_composite_divider_set_rate,
};
static int imx8m_clk_mux_set_parent(struct clk *clk, struct clk *parent)
{
struct clk_mux *mux = to_clk_mux(clk);
int index;
u32 val;
u32 reg;
index = clk_mux_fetch_parent_index(clk, parent);
if (index < 0) {
log_err("Could not fetch index\n");
return index;
}
val = clk_mux_index_to_val(mux->table, mux->flags, index);
reg = readl(mux->reg);
reg &= ~(mux->mask << mux->shift);
val = val << mux->shift;
reg |= val;
/*
* write twice to make sure non-target interface
* SEL_A/B point the same clk input.
*/
writel(reg, mux->reg);
writel(reg, mux->reg);
return 0;
}
const struct clk_ops imx8m_clk_mux_ops = {
.get_rate = clk_generic_get_rate,
.set_parent = imx8m_clk_mux_set_parent,
};
struct clk *imx8m_clk_composite_flags(const char *name,
const char * const *parent_names,
int num_parents, void __iomem *reg,
@ -134,7 +169,6 @@ struct clk *imx8m_clk_composite_flags(const char *name,
mux->shift = PCG_PCS_SHIFT;
mux->mask = PCG_PCS_MASK;
mux->num_parents = num_parents;
mux->flags = flags;
mux->parent_names = parent_names;
div = kzalloc(sizeof(*div), GFP_KERNEL);
@ -144,7 +178,7 @@ struct clk *imx8m_clk_composite_flags(const char *name,
div->reg = reg;
div->shift = PCG_PREDIV_SHIFT;
div->width = PCG_PREDIV_WIDTH;
div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags;
div->flags = CLK_DIVIDER_ROUND_CLOSEST;
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
if (!gate)
@ -152,11 +186,10 @@ struct clk *imx8m_clk_composite_flags(const char *name,
gate->reg = reg;
gate->bit_idx = PCG_CGC_SHIFT;
gate->flags = flags;
clk = clk_register_composite(NULL, name,
parent_names, num_parents,
&mux->clk, &clk_mux_ops, &div->clk,
&mux->clk, &imx8m_clk_mux_ops, &div->clk,
&imx8m_clk_composite_divider_ops,
&gate->clk, &clk_gate_ops, flags);
if (IS_ERR(clk))

2
drivers/clk/imx/clk-composite-93.c
View file

@ -102,7 +102,6 @@ struct clk *imx93_clk_composite_flags(const char *name,
mux->mask = CCM_MUX_MASK;
mux->num_parents = num_parents;
mux->parent_names = parent_names;
mux->flags = flags;
div = kzalloc(sizeof(*div), GFP_KERNEL);
if (!div)
@ -119,7 +118,6 @@ struct clk *imx93_clk_composite_flags(const char *name,
gate->reg = reg;
gate->bit_idx = CCM_OFF_SHIFT;
gate->flags = flags;
clk = clk_register_composite(NULL, name,
parent_names, num_parents,

4
drivers/mmc/fsl_esdhc_imx.c
View file

@ -766,7 +766,7 @@ static int esdhc_set_voltage(struct mmc *mmc)
ret = regulator_set_value(priv->vqmmc_dev,
3300000);
if (ret) {
printf("Setting to 3.3V error");
printf("Setting to 3.3V error: %d\n", ret);
return -EIO;
}
mdelay(5);
@ -784,7 +784,7 @@ static int esdhc_set_voltage(struct mmc *mmc)
ret = regulator_set_value(priv->vqmmc_dev,
1800000);
if (ret) {
printf("Setting to 1.8V error");
printf("Setting to 1.8V error: %d\n", ret);
return -EIO;
}
}

4
include/configs/msc_sm2s_imx8mp.h
View file

@ -35,10 +35,10 @@
"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"image=Image\0" \
"console=ttymxc1,115200\0" \
"fdt_addr_r=0x43000000\0" \
"fdt_addr_r=0x48600000\0" \
"boot_fdt=try\0" \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
"initrd_addr=0x43800000\0" \
"initrd_addr=0x48680000\0" \
"bootm_size=0x10000000\0" \
"mmcpart=1\0" \
"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \

1
include/linux/clk-provider.h
View file

@ -74,6 +74,7 @@ struct clk_mux {
#define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk)
extern const struct clk_ops clk_mux_ops;
u8 clk_mux_get_parent(struct clk *clk);
int clk_mux_fetch_parent_index(struct clk *clk, struct clk *parent);
/**
* clk_mux_index_to_val() - Convert the parent index to the register value