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riscv: dts: t-head: Add basic device tree for Sipeed Lichee PI 4A board
Only add basic support for CPU, PLIC UART and Timer. Reviewed-by: Wei Fu <wefu@redhat.com> Signed-off-by: Yixun Lan <dlan@gentoo.org>
This commit is contained in:
Yixun Lan
Leo Yu-Chi Liang
parent
5f3a7fdb72
commit
4416f07940
4 changed files with 473 additions and 0 deletions
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@ -8,6 +8,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
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dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
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dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
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dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2.dtb
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dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb
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include $(srctree)/scripts/Makefile.dts
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targets += $(dtb-y)
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34
arch/riscv/dts/th1520-lichee-module-4a.dtsi
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34
arch/riscv/dts/th1520-lichee-module-4a.dtsi
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@ -0,0 +1,34 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
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*/
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/dts-v1/;
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#include "th1520.dtsi"
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/ {
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model = "Sipeed Lichee Module 4A";
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compatible = "sipeed,lichee-module-4a", "thead,th1520";
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x00000000 0x2 0x00000000>;
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};
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};
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&osc {
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clock-frequency = <24000000>;
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};
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&osc_32k {
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clock-frequency = <32768>;
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};
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&apb_clk {
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clock-frequency = <62500000>;
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};
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&uart_sclk {
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clock-frequency = <100000000>;
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};
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32
arch/riscv/dts/th1520-lichee-pi-4a.dts
Normal file
32
arch/riscv/dts/th1520-lichee-pi-4a.dts
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@ -0,0 +1,32 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
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*/
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#include "th1520-lichee-module-4a.dtsi"
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/ {
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model = "Sipeed Lichee Pi 4A";
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compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520";
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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gpio3 = &gpio3;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &uart5;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&uart0 {
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status = "okay";
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};
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406
arch/riscv/dts/th1520.dtsi
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406
arch/riscv/dts/th1520.dtsi
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@ -0,0 +1,406 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 Alibaba Group Holding Limited.
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* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "thead,th1520";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <3000000>;
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c910_0: cpu@0 {
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compatible = "thead,c910", "riscv";
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device_type = "cpu";
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riscv,isa = "rv64imafdc";
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reg = <0>;
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i-cache-block-size = <64>;
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i-cache-size = <65536>;
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i-cache-sets = <512>;
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d-cache-block-size = <64>;
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d-cache-size = <65536>;
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d-cache-sets = <512>;
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next-level-cache = <&l2_cache>;
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mmu-type = "riscv,sv39";
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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c910_1: cpu@1 {
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compatible = "thead,c910", "riscv";
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device_type = "cpu";
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riscv,isa = "rv64imafdc";
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reg = <1>;
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i-cache-block-size = <64>;
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i-cache-size = <65536>;
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i-cache-sets = <512>;
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d-cache-block-size = <64>;
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d-cache-size = <65536>;
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d-cache-sets = <512>;
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next-level-cache = <&l2_cache>;
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mmu-type = "riscv,sv39";
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cpu1_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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c910_2: cpu@2 {
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compatible = "thead,c910", "riscv";
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device_type = "cpu";
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riscv,isa = "rv64imafdc";
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reg = <2>;
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i-cache-block-size = <64>;
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i-cache-size = <65536>;
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i-cache-sets = <512>;
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d-cache-block-size = <64>;
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d-cache-size = <65536>;
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d-cache-sets = <512>;
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next-level-cache = <&l2_cache>;
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mmu-type = "riscv,sv39";
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cpu2_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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c910_3: cpu@3 {
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compatible = "thead,c910", "riscv";
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device_type = "cpu";
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riscv,isa = "rv64imafdc";
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reg = <3>;
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i-cache-block-size = <64>;
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i-cache-size = <65536>;
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i-cache-sets = <512>;
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d-cache-block-size = <64>;
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d-cache-size = <65536>;
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d-cache-sets = <512>;
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next-level-cache = <&l2_cache>;
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mmu-type = "riscv,sv39";
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cpu3_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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l2_cache: l2-cache {
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compatible = "cache";
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cache-block-size = <64>;
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cache-level = <2>;
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cache-size = <1048576>;
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cache-sets = <1024>;
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cache-unified;
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};
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};
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osc: oscillator {
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compatible = "fixed-clock";
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clock-output-names = "osc_24m";
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#clock-cells = <0>;
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};
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osc_32k: 32k-oscillator {
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compatible = "fixed-clock";
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clock-output-names = "osc_32k";
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#clock-cells = <0>;
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};
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apb_clk: apb-clk-clock {
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compatible = "fixed-clock";
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clock-output-names = "apb_clk";
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#clock-cells = <0>;
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};
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uart_sclk: uart-sclk-clock {
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compatible = "fixed-clock";
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clock-output-names = "uart_sclk";
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#clock-cells = <0>;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&plic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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plic: interrupt-controller@ffd8000000 {
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compatible = "thead,th1520-plic", "thead,c900-plic";
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reg = <0xff 0xd8000000 0x0 0x01000000>;
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interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
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<&cpu1_intc 11>, <&cpu1_intc 9>,
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<&cpu2_intc 11>, <&cpu2_intc 9>,
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<&cpu3_intc 11>, <&cpu3_intc 9>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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riscv,ndev = <240>;
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};
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clint: timer@ffdc000000 {
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compatible = "thead,th1520-clint", "thead,c900-clint";
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reg = <0xff 0xdc000000 0x0 0x00010000>;
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interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
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<&cpu1_intc 3>, <&cpu1_intc 7>,
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<&cpu2_intc 3>, <&cpu2_intc 7>,
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<&cpu3_intc 3>, <&cpu3_intc 7>;
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};
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uart0: serial@ffe7014000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xff 0xe7014000 0x0 0x100>;
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interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uart_sclk>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart1: serial@ffe7f00000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xff 0xe7f00000 0x0 0x100>;
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interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uart_sclk>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart3: serial@ffe7f04000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xff 0xe7f04000 0x0 0x100>;
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interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uart_sclk>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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gpio2: gpio@ffe7f34000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0xff 0xe7f34000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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portc: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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gpio3: gpio@ffe7f38000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0xff 0xe7f38000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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portd: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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gpio0: gpio@ffec005000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0xff 0xec005000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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porta: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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gpio1: gpio@ffec006000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0xff 0xec006000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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portb: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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uart2: serial@ffec010000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xff 0xec010000 0x0 0x4000>;
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interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uart_sclk>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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timer0: timer@ffefc32000 {
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compatible = "snps,dw-apb-timer";
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reg = <0xff 0xefc32000 0x0 0x14>;
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clocks = <&apb_clk>;
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clock-names = "timer";
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interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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timer1: timer@ffefc32014 {
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compatible = "snps,dw-apb-timer";
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reg = <0xff 0xefc32014 0x0 0x14>;
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clocks = <&apb_clk>;
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clock-names = "timer";
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interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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timer2: timer@ffefc32028 {
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compatible = "snps,dw-apb-timer";
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reg = <0xff 0xefc32028 0x0 0x14>;
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clocks = <&apb_clk>;
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clock-names = "timer";
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interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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timer3: timer@ffefc3203c {
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compatible = "snps,dw-apb-timer";
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reg = <0xff 0xefc3203c 0x0 0x14>;
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clocks = <&apb_clk>;
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clock-names = "timer";
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interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart4: serial@fff7f08000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xff 0xf7f08000 0x0 0x4000>;
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interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uart_sclk>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart5: serial@fff7f0c000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xff 0xf7f0c000 0x0 0x4000>;
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interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uart_sclk>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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timer4: timer@ffffc33000 {
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compatible = "snps,dw-apb-timer";
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reg = <0xff 0xffc33000 0x0 0x14>;
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clocks = <&apb_clk>;
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clock-names = "timer";
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interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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timer5: timer@ffffc33014 {
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compatible = "snps,dw-apb-timer";
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reg = <0xff 0xffc33014 0x0 0x14>;
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clocks = <&apb_clk>;
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clock-names = "timer";
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interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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timer6: timer@ffffc33028 {
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compatible = "snps,dw-apb-timer";
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reg = <0xff 0xffc33028 0x0 0x14>;
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clocks = <&apb_clk>;
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clock-names = "timer";
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interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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timer7: timer@ffffc3303c {
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compatible = "snps,dw-apb-timer";
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reg = <0xff 0xffc3303c 0x0 0x14>;
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clocks = <&apb_clk>;
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clock-names = "timer";
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interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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ao_gpio0: gpio@fffff41000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0xff 0xfff41000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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porte: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
ao_gpio1: gpio@fffff52000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xff 0xfff52000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portf: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <32>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Add table
Reference in a new issue